__raw_writel(reg, gpc_base + 0x14);
/* PU power gating. */
- org_ldo = reg = __raw_readl(ANADIG_REG_CORE);
+ reg = __raw_readl(ANADIG_REG_CORE);
+ org_ldo = reg & (ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
reg &= ~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
__raw_writel(reg, ANADIG_REG_CORE);
reg |= 0x80000000;
__raw_writel(reg, ANADIG_MISC1_REG);
}
+
mutex_unlock(&bus_freq_mutex);
}
/* Enable the PU LDO */
if (low_bus_freq_mode || audio_bus_freq_mode) {
- /* Set the voltage of VDDSOC as in normal mode. */
- __raw_writel(org_ldo, ANADIG_REG_CORE);
+ /* Set the voltage of VDDPU as in normal mode. */
+ __raw_writel(org_ldo | (__raw_readl(ANADIG_REG_CORE) &
+ (~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET))), ANADIG_REG_CORE);
/* Need to wait for the regulator to come back up */
/*
extern int dvfs_core_is_active;
extern struct cpu_op *(*get_cpu_op)(int *op);
extern int low_bus_freq_mode;
-extern int audio_bus_freq_mode;
extern int high_bus_freq_mode;
extern int set_low_bus_freq(void);
extern int set_high_bus_freq(int high_bus_speed);
#endif
/*Set the voltage for the GP domain. */
if (freq > org_cpu_rate) {
- if (low_bus_freq_mode || audio_bus_freq_mode)
+ if (low_bus_freq_mode)
set_high_bus_freq(0);
ret = regulator_set_voltage(cpu_regulator, gp_volt,
gp_volt);