drm/radeon: adjust default radeon_vm_block_size v2

v2: rebase on vm_size scale change. Adjust vm_size default to 8,
    Better handle the default and smaller values.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 248bce86af5185ddc209f702c5baa3b4e4e25907..c8ea050c8fa463b8ae5fa6768a5cf67cc924f119 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1123,7 +1123,19 @@ static void radeon_check_arguments(struct radeon_device *rdev)
        /* defines number of bits in page table versus page directory,
         * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
         * page table and the remaining bits are in the page directory */
-       if (radeon_vm_block_size < 9) {
+       if (radeon_vm_block_size == -1) {
+
+               /* Total bits covered by PD + PTs */
+               unsigned bits = ilog2(radeon_vm_size) + 17;
+
+               /* Make sure the PD is 4K in size up to 8GB address space.
+                  Above that split equal between PD and PTs */
+               if (radeon_vm_size <= 8)
+                       radeon_vm_block_size = bits - 9;
+               else
+                       radeon_vm_block_size = (bits + 3) / 2;
+
+       } else if (radeon_vm_block_size < 9) {
                dev_warn(rdev->dev, "VM page table size (%d) too small\n",
                         radeon_vm_block_size);
                radeon_vm_block_size = 9;

diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 54aa293a8175a315ce397fefcbdc2c202871c586..8688e860e6a07776c66cb660539420ec26783d7e 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -175,8 +175,8 @@ int radeon_dpm = -1;
 int radeon_aspm = -1;
 int radeon_runtime_pm = -1;
 int radeon_hard_reset = 0;
-int radeon_vm_size = 4;
-int radeon_vm_block_size = 9;
+int radeon_vm_size = 8;
+int radeon_vm_block_size = -1;
 int radeon_deep_color = 0;
 
 MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
@@ -248,7 +248,7 @@ module_param_named(hard_reset, radeon_hard_reset, int, 0444);
 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
 module_param_named(vm_size, radeon_vm_size, int, 0444);
 
-MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default 9)");
+MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
 module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
 
 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");