]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
ENGR00221438 [MX6]Adjust CPU setpoint according to datasheet
authorAnson Huang <b20788@freescale.com>
Sat, 25 Aug 2012 08:39:06 +0000 (16:39 +0800)
committerLothar Waßmann <LW@KARO-electronics.de>
Fri, 24 May 2013 06:35:20 +0000 (08:35 +0200)
1. Adjust ARM/SOC/PU voltage according to latest datasheet;
2. Remove Rigel's 200M setpoint to align with Arik.

Signed-off-by: Anson Huang <b20788@freescale.com>
arch/arm/mach-mx6/cpu_op-mx6.c
arch/arm/mach-mx6/mx6q_sabreauto_pmic_pfuze100.c
arch/arm/mach-mx6/mx6q_sabresd_pmic_pfuze100.c

index 3415f01f238c7501e7255c7716a3dae59fe74de3..80e1c108963228a0c78f64a4e02f73ca3a26c3f8 100644 (file)
@@ -29,8 +29,8 @@ static struct cpu_op mx6q_cpu_op_1_2G[] = {
         .pll_rate = 1200000000,
         .cpu_rate = 1200000000,
         .cpu_podf = 0,
-        .pu_voltage = 1250000,
-        .soc_voltage = 1250000,
+        .pu_voltage = 1275000,
+        .soc_voltage = 1275000,
         .cpu_voltage = 1275000,},
        {
         .pll_rate = 792000000,
@@ -38,13 +38,13 @@ static struct cpu_op mx6q_cpu_op_1_2G[] = {
         .cpu_podf = 0,
 #ifdef CONFIG_MX6_VPU_352M
        /*VPU 352Mhz need voltage 1.25V*/
-        .pu_voltage = 1250000,
-        .soc_voltage = 1250000,
+       .pu_voltage = 1250000,
+       .soc_voltage = 1250000,
 #else
-        .pu_voltage = 1150000,
-        .soc_voltage = 1150000,
+        .pu_voltage = 1175000,
+        .soc_voltage = 1175000,
 #endif
-        .cpu_voltage = 1100000,},
+        .cpu_voltage = 1150000,},
 #ifdef CONFIG_MX6_VPU_352M
        /*pll2_pfd_400M will be fix on 352M,to avoid modify other code
        which assume ARM clock sourcing from pll2_pfd_400M, change cpu
@@ -55,15 +55,15 @@ static struct cpu_op mx6q_cpu_op_1_2G[] = {
          .cpu_podf = 0,
          .pu_voltage = 1250000,
          .soc_voltage = 1250000,
-         .cpu_voltage = 925000,},
+         .cpu_voltage = 950000,},
 #else
         {
          .pll_rate = 396000000,
          .cpu_rate = 396000000,
          .cpu_podf = 0,
-         .pu_voltage = 1150000,
-         .soc_voltage = 1150000,
-         .cpu_voltage = 925000,},
+         .pu_voltage = 1175000,
+         .soc_voltage = 1175000,
+         .cpu_voltage = 950000,},
 #endif
 };
 
@@ -73,9 +73,9 @@ static struct cpu_op mx6q_cpu_op_1G[] = {
         .pll_rate = 996000000,
         .cpu_rate = 996000000,
         .cpu_podf = 0,
-        .pu_voltage = 1200000,
-        .soc_voltage = 1200000,
-        .cpu_voltage = 1225000,},
+        .pu_voltage = 1250000,
+        .soc_voltage = 1250000,
+        .cpu_voltage = 1250000,},
        {
         .pll_rate = 792000000,
         .cpu_rate = 792000000,
@@ -85,10 +85,10 @@ static struct cpu_op mx6q_cpu_op_1G[] = {
         .pu_voltage = 1250000,
         .soc_voltage = 1250000,
 #else
-        .pu_voltage = 1150000,
-        .soc_voltage = 1150000,
+        .pu_voltage = 1175000,
+        .soc_voltage = 1175000,
 #endif
-        .cpu_voltage = 1100000,},
+        .cpu_voltage = 1150000,},
 #ifdef CONFIG_MX6_VPU_352M
        /*pll2_pfd_400M will be fix on 352M,to avoid modify other code
        which assume ARM clock sourcing from pll2_pfd_400M, change cpu
@@ -99,15 +99,15 @@ static struct cpu_op mx6q_cpu_op_1G[] = {
          .cpu_podf = 0,
          .pu_voltage = 1250000,
          .soc_voltage = 1250000,
-         .cpu_voltage = 925000,},
+         .cpu_voltage = 950000,},
 #else
         {
          .pll_rate = 396000000,
          .cpu_rate = 396000000,
          .cpu_podf = 0,
-         .pu_voltage = 1150000,
-         .soc_voltage = 1150000,
-         .cpu_voltage = 925000,},
+         .pu_voltage = 1175000,
+         .soc_voltage = 1175000,
+         .cpu_voltage = 950000,},
 #endif
 };
 
@@ -121,10 +121,10 @@ static struct cpu_op mx6q_cpu_op[] = {
         .pu_voltage = 1250000,
         .soc_voltage = 1250000,
 #else
-        .pu_voltage = 1150000,
-        .soc_voltage = 1150000,
+        .pu_voltage = 1175000,
+        .soc_voltage = 1175000,
 #endif
-        .cpu_voltage = 1100000,},
+        .cpu_voltage = 1150000,},
 #ifdef CONFIG_MX6_VPU_352M
        /*pll2_pfd_400M will be fix on 352M,to avoid modify other code
        which assume ARM clock sourcing from pll2_pfd_400M, change cpu
@@ -135,15 +135,15 @@ static struct cpu_op mx6q_cpu_op[] = {
          .cpu_podf = 0,
          .pu_voltage = 1250000,
          .soc_voltage = 1250000,
-         .cpu_voltage = 925000,},
+         .cpu_voltage = 950000,},
 #else
         {
          .pll_rate = 396000000,
          .cpu_rate = 396000000,
          .cpu_podf = 0,
-         .pu_voltage = 1150000,
-         .soc_voltage = 1150000,
-         .cpu_voltage = 925000,},
+         .pu_voltage = 1175000,
+         .soc_voltage = 1175000,
+         .cpu_voltage = 950000,},
 #endif
 };
 
@@ -153,30 +153,23 @@ static struct cpu_op mx6dl_cpu_op_1_2G[] = {
         .pll_rate = 1200000000,
         .cpu_rate = 1200000000,
         .cpu_podf = 0,
-        .pu_voltage = 1250000,
-        .soc_voltage = 1250000,
+        .pu_voltage = 1275000,
+        .soc_voltage = 1275000,
         .cpu_voltage = 1275000,},
        {
         .pll_rate = 792000000,
         .cpu_rate = 792000000,
         .cpu_podf = 0,
-        .pu_voltage = 1150000,
-        .soc_voltage = 1150000,
-        .cpu_voltage = 1100000,},
+        .pu_voltage = 1175000,
+        .soc_voltage = 1175000,
+        .cpu_voltage = 1150000,},
         {
          .pll_rate = 396000000,
          .cpu_rate = 396000000,
          .cpu_podf = 0,
-         .pu_voltage = 1150000,
-         .soc_voltage = 1150000,
-         .cpu_voltage = 1025000,},
-        {
-         .pll_rate = 396000000,
-         .cpu_rate = 198000000,
-         .cpu_podf = 1,
-         .pu_voltage = 1150000,
-         .soc_voltage = 1150000,
-         .cpu_voltage = 1025000,},
+         .pu_voltage = 1175000,
+         .soc_voltage = 1175000,
+         .cpu_voltage = 1075000,},
 };
 /* working point(wp): 0 - 1GHz; 1 - 800MHz, 2 - 400MHz, 3  - 200MHz */
 static struct cpu_op mx6dl_cpu_op_1G[] = {
@@ -184,53 +177,39 @@ static struct cpu_op mx6dl_cpu_op_1G[] = {
         .pll_rate = 996000000,
         .cpu_rate = 996000000,
         .cpu_podf = 0,
-        .pu_voltage = 1200000,
-        .soc_voltage = 1200000,
-        .cpu_voltage = 1225000,},
+        .pu_voltage = 1250000,
+        .soc_voltage = 1250000,
+        .cpu_voltage = 1250000,},
        {
         .pll_rate = 792000000,
         .cpu_rate = 792000000,
         .cpu_podf = 0,
-        .pu_voltage = 1150000,
-        .soc_voltage = 1150000,
-        .cpu_voltage = 1100000,},
+        .pu_voltage = 1175000,
+        .soc_voltage = 1175000,
+        .cpu_voltage = 1150000,},
        {
         .pll_rate = 396000000,
         .cpu_rate = 396000000,
         .cpu_podf = 0,
-        .pu_voltage = 1150000,
-        .soc_voltage = 1150000,
-        .cpu_voltage = 1025000,},
-        {
-         .pll_rate = 396000000,
-         .cpu_rate = 198000000,
-         .cpu_podf = 1,
-         .pu_voltage = 1150000,
-         .soc_voltage = 1150000,
-         .cpu_voltage = 1025000,},
+        .pu_voltage = 1175000,
+        .soc_voltage = 1175000,
+        .cpu_voltage = 1075000,},
 };
 static struct cpu_op mx6dl_cpu_op[] = {
        {
         .pll_rate = 792000000,
         .cpu_rate = 792000000,
         .cpu_podf = 0,
-        .pu_voltage = 1150000,
-        .soc_voltage = 1150000,
-        .cpu_voltage = 1100000,},
+        .pu_voltage = 1175000,
+        .soc_voltage = 1175000,
+        .cpu_voltage = 1150000,},
         {
          .pll_rate = 396000000,
          .cpu_rate = 396000000,
          .cpu_podf = 0,
-         .pu_voltage = 1150000,
-         .soc_voltage = 1150000,
-         .cpu_voltage = 1025000,},
-       {
-        .pll_rate = 396000000,
-        .cpu_rate = 198000000,
-        .cpu_podf = 1,
-        .pu_voltage = 1150000,
-        .soc_voltage = 1150000,
-        .cpu_voltage = 1025000,},
+         .pu_voltage = 1175000,
+         .soc_voltage = 1175000,
+         .cpu_voltage = 1075000,},
 };
 
 static struct cpu_op mx6sl_cpu_op_1G[] = {
index cc12a0224ab2a2171686e793da3a78e6e9478512..8cb4ffcc78fa0ed7732c2427472a8b9cb9bffe4e 100644 (file)
 
  /*SWBST*/
 #define PFUZE100_SW1ASTANDBY    33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL   (0x18)
+#define PFUZE100_SW1ASTANDBY_STBY_VAL   (0x19)
 #define PFUZE100_SW1ASTANDBY_STBY_M     (0x3f<<0)
 #define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x18)
+#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)
 #define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
 #define PFUZE100_SW1CSTANDBY    47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL   (0x18)
+#define PFUZE100_SW1CSTANDBY_STBY_VAL   (0x19)
 #define PFUZE100_SW1CSTANDBY_STBY_M     (0x3f<<0)
 #define PFUZE100_SW2STANDBY     54
 #define PFUZE100_SW2STANDBY_STBY_VAL    0x0
index f7e7099468c1710c5fc4648d9372c45805f40570..a53036c3df03b30b4e134a9ba7d1da238ebb1098 100644 (file)
 #define PFUZE100_SW1CVOL       46
 #define PFUZE100_SW1CVOL_VSEL_M        (0x3f<<0)
 #define PFUZE100_SW1ASTANDBY   33
-#define PFUZE100_SW1ASTANDBY_STBY_VAL  (0x18)
+#define PFUZE100_SW1ASTANDBY_STBY_VAL  (0x19)
 #define PFUZE100_SW1ASTANDBY_STBY_M    (0x3f<<0)
 #define PFUZE100_SW1BSTANDBY   40
-#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x18)
+#define PFUZE100_SW1BSTANDBY_STBY_VAL  (0x19)
 #define PFUZE100_SW1BSTANDBY_STBY_M    (0x3f<<0)
 #define PFUZE100_SW1CSTANDBY   47
-#define PFUZE100_SW1CSTANDBY_STBY_VAL  (0x18)
+#define PFUZE100_SW1CSTANDBY_STBY_VAL  (0x19)
 #define PFUZE100_SW1CSTANDBY_STBY_M    (0x3f<<0)
 #define PFUZE100_SW2STANDBY     54
 #define PFUZE100_SW2STANDBY_STBY_VAL    0x0