MIPS: mipsregs.h: Move TX39 macros out of the way

TX39 CP0 Configuration Register 3 macro definitions have been randomly
thrown in the middle of a block of CP0 Status register value macros.
Move them to the end of the whole CP0 register value macro block,
complementing the location of the TX39 Cache register name macro at the
end of the CP0 register name macro block.

[ralf@linux-mips.org: Fix conflict.]

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9668/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 0e8af630916096f46aef8645465ec91568ad963f..a706d429a7417307af2e70c97684dd34d0372062 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -276,39 +276,6 @@
  */
 #define ST0_MX                 0x01000000
 
-/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT    19
-#define TX39_CONF_ICS_MASK     0x00380000
-#define TX39_CONF_ICS_1KB      0x00000000
-#define TX39_CONF_ICS_2KB      0x00080000
-#define TX39_CONF_ICS_4KB      0x00100000
-#define TX39_CONF_ICS_8KB      0x00180000
-#define TX39_CONF_ICS_16KB     0x00200000
-
-#define TX39_CONF_DCS_SHIFT    16
-#define TX39_CONF_DCS_MASK     0x00070000
-#define TX39_CONF_DCS_1KB      0x00000000
-#define TX39_CONF_DCS_2KB      0x00010000
-#define TX39_CONF_DCS_4KB      0x00020000
-#define TX39_CONF_DCS_8KB      0x00030000
-#define TX39_CONF_DCS_16KB     0x00040000
-
-#define TX39_CONF_CWFON                0x00004000
-#define TX39_CONF_WBON         0x00002000
-#define TX39_CONF_RF_SHIFT     10
-#define TX39_CONF_RF_MASK      0x00000c00
-#define TX39_CONF_DOZE         0x00000200
-#define TX39_CONF_HALT         0x00000100
-#define TX39_CONF_LOCK         0x00000080
-#define TX39_CONF_ICE          0x00000020
-#define TX39_CONF_DCE          0x00000010
-#define TX39_CONF_IRSIZE_SHIFT 2
-#define TX39_CONF_IRSIZE_MASK  0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT 0
-#define TX39_CONF_DRSIZE_MASK  0x00000003
-
 /*
  * Status register bits available in all MIPS CPUs.
  */
@@ -685,6 +652,39 @@
 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 #define MIPS_CDMMBASE_ADDR_START 15
 
+/*
+ * Bitfields in the TX39 family CP0 Configuration Register 3
+ */
+#define TX39_CONF_ICS_SHIFT    19
+#define TX39_CONF_ICS_MASK     0x00380000
+#define TX39_CONF_ICS_1KB      0x00000000
+#define TX39_CONF_ICS_2KB      0x00080000
+#define TX39_CONF_ICS_4KB      0x00100000
+#define TX39_CONF_ICS_8KB      0x00180000
+#define TX39_CONF_ICS_16KB     0x00200000
+
+#define TX39_CONF_DCS_SHIFT    16
+#define TX39_CONF_DCS_MASK     0x00070000
+#define TX39_CONF_DCS_1KB      0x00000000
+#define TX39_CONF_DCS_2KB      0x00010000
+#define TX39_CONF_DCS_4KB      0x00020000
+#define TX39_CONF_DCS_8KB      0x00030000
+#define TX39_CONF_DCS_16KB     0x00040000
+
+#define TX39_CONF_CWFON                0x00004000
+#define TX39_CONF_WBON         0x00002000
+#define TX39_CONF_RF_SHIFT     10
+#define TX39_CONF_RF_MASK      0x00000c00
+#define TX39_CONF_DOZE         0x00000200
+#define TX39_CONF_HALT         0x00000100
+#define TX39_CONF_LOCK         0x00000080
+#define TX39_CONF_ICE          0x00000020
+#define TX39_CONF_DCE          0x00000010
+#define TX39_CONF_IRSIZE_SHIFT 2
+#define TX39_CONF_IRSIZE_MASK  0x0000000c
+#define TX39_CONF_DRSIZE_SHIFT 0
+#define TX39_CONF_DRSIZE_MASK  0x00000003
+
 
 /*
  * Coprocessor 1 (FPU) register names