high_bus_freq_mode = 0;
med_bus_freq_mode = 0;
- /* Disable the brown out detection since we are going to be
- * disabling the LDO.
- */
- reg = __raw_readl(ANA_MISC2_BASE_ADDR);
- reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
- __raw_writel(reg, ANA_MISC2_BASE_ADDR);
-
- /* Power gate the PU LDO. */
- /* Power gate the PU domain first. */
- /* enable power down request */
- reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
- __raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
- /* power down request */
- reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET);
- __raw_writel(reg | 0x1, gpc_base + GPC_CNTR_OFFSET);
- /* Wait for power down to complete. */
- while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x1)
- ;
-
- /* Mask the ANATOP brown out interrupt in the GPC. */
- reg = __raw_readl(gpc_base + 0x14);
- reg |= 0x80000000;
- __raw_writel(reg, gpc_base + 0x14);
-
- /* PU power gating. */
- org_ldo = reg = __raw_readl(ANADIG_REG_CORE);
- reg &= ~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
- __raw_writel(reg, ANADIG_REG_CORE);
-
- /* Clear the BO interrupt in the ANATOP. */
- reg = __raw_readl(ANADIG_MISC1_REG);
- reg |= 0x80000000;
- __raw_writel(reg, ANADIG_MISC1_REG);
+ /* Do not disable PU LDO if it is not enabled */
+ reg = __raw_readl(ANADIG_REG_CORE) & (ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
+ if ((low_bus_freq_mode || audio_bus_freq_mode) && reg != 0) {
+ /* Disable the brown out detection since we are going to be
+ * disabling the LDO.
+ */
+ reg = __raw_readl(ANA_MISC2_BASE_ADDR);
+ reg &= ~ANADIG_ANA_MISC2_REG1_BO_EN;
+ __raw_writel(reg, ANA_MISC2_BASE_ADDR);
+ /* Power gate the PU LDO. */
+ /* Power gate the PU domain first. */
+ /* enable power down request */
+ reg = __raw_readl(gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
+ __raw_writel(reg | 0x1, gpc_base + GPC_PGC_GPU_PGCR_OFFSET);
+ /* power down request */
+ reg = __raw_readl(gpc_base + GPC_CNTR_OFFSET);
+ __raw_writel(reg | 0x1, gpc_base + GPC_CNTR_OFFSET);
+ /* Wait for power down to complete. */
+ while (__raw_readl(gpc_base + GPC_CNTR_OFFSET) & 0x1)
+ ;
+
+ /* Mask the ANATOP brown out interrupt in the GPC. */
+ reg = __raw_readl(gpc_base + 0x14);
+ reg |= 0x80000000;
+ __raw_writel(reg, gpc_base + 0x14);
+
+ /* PU power gating. */
+ org_ldo = reg = __raw_readl(ANADIG_REG_CORE);
+ reg &= ~(ANADIG_REG_TARGET_MASK << ANADIG_REG1_PU_TARGET_OFFSET);
+ __raw_writel(reg, ANADIG_REG_CORE);
+
+ /* Clear the BO interrupt in the ANATOP. */
+ reg = __raw_readl(ANADIG_MISC1_REG);
+ reg |= 0x80000000;
+ __raw_writel(reg, ANADIG_MISC1_REG);
+ }
mutex_unlock(&bus_freq_mutex);
}
}
/* Enable the PU LDO */
- if (low_bus_freq_mode) {
+ if (low_bus_freq_mode || audio_bus_freq_mode) {
/* Set the voltage of VDDSOC as in normal mode. */
__raw_writel(org_ldo, ANADIG_REG_CORE);
/* Set the AHB dividers before the switch. */
/* Don't change AXI clock divider. */
- /* Set the MMDC_DIV=1, AHB_DIV=4 (need to maintain GPT divider). */
+ /* Set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4 (need to maintain GPT divider). */
ldr r0, [r6, #0x14]
- ldr r2, =0x381D00
+ ldr r2, =0x3f1f00
bic r0, r0, r2
- orr r0, r0, #0xD00
+ orr r0, r0, #0xd00
+ orr r0, r0, #0x10000
str r0, [r6, #0x14]
wait_div_update528:
* would be too fast when switching to PLL3.
*/
/* Don't change AXI clock divider. */
- /* Set the MMDC_DIV=1, AHB_DIV=4 (need to maintain GPT divider). */
+ /* Set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4 (need to maintain GPT divider). */
ldr r0, [r6, #0x14]
- ldr r2, =0x381D00
+ ldr r2, =0x3f1f00
bic r0, r0, r2
- orr r0, r0, #0xD00
- /* Make sure AXI clock divider is 1 */
- bic r0, r0, #0x70000
+ orr r0, r0, #0xd00
orr r0, r0, #0x10000
str r0, [r6, #0x14]
* would be too fast when switching to PLL3.
*/
/* Don't change AXI clock divider. */
- /* Set the MMDC_DIV=1, AHB_DIV=4 (need to maintain GPT divider). */
+ /* Set the MMDC_DIV=1, AXI_DIV = 2, AHB_DIV=4 (need to maintain GPT divider). */
ldr r0, [r6, #0x14]
- ldr r2, =0x381D00
+ ldr r2, =0x3f1f00
bic r0, r0, r2
- orr r0, r0, #0xD00
+ orr r0, r0, #0x900
+ orr r0, r0, #0x10000
str r0, [r6, #0x14]
wait_div_update400_1:
/* Change AHB divider so that we are at 400/3=133MHz. */
/* Don't change AXI clock divider. */
- /* Set the MMDC_DIV=1, AHB_DIV=3 (need to maintain GPT divider). */
+ /* Set the MMDC_DIV=1, AXI_DIV=2, AHB_DIV=3 (need to maintain GPT divider). */
ldr r0, [r6, #0x14]
- ldr r2, =0x381D00
+ ldr r2, =0x3f1f00
bic r0, r0, r2
orr r0, r0, #0x900
- /* Make sure AXI clock divider is 1 */
- bic r0, r0, #0x70000
orr r0, r0, #0x10000
str r0, [r6, #0x14]
/* Set the MMDC_DIV=4, AXI_DIV = 4, AHB_DIV=8 (need to maintain GPT divider). */
ldr r0, [r6, #0x14]
- ldr r2, =0x3F1C00
+ ldr r2, =0x3f1f00
bic r0, r0, r2
orr r0, r0, #0x180000
orr r0, r0, #0x30000
/* If changing AHB divider remember to change the IPGPER divider too below. */
- orr r0, r0, #0x1C00
- str r0, [r6, #0x14]
+ orr r0, r0, #0x1d00
+ str r0, [r6, #0x14]
wait_div_update_50:
ldr r0, [r6, #0x48]
/* Change the GPT divider so that its at 6MHz. */
ldr r0, [r6, #0x1C]
bic r0, r0, #0x3F
- orr r0, r0, #0x3
+ orr r0, r0, #0x1
str r0, [r6, #0x1C]
.endm
/* Change all the dividers to 1. */
ldr r0, [r6, #0x14]
- ldr r2, =0x3F1C00
+ ldr r2, =0x3f1f00
bic r0, r0, r2
+ orr r0, r0, #0x100
str r0, [r6, #0x14]
/* Wait for the divider to change. */