drm/i915: Move HAS_HW_CONTEXTS definition to platform

Moving all GPU features to the platform definition allows for
	- standard place when adding new features from new platforms
	- possible to see supported features when dumping struct
	  definitions

Signed-off-by: Carlos Santa <carlos.santa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 66548d6b9ea02b0adc6205a1d423a8a9ab60fe09..e39d2150df0be74706264fec3a2b24168fbbdb17 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -662,6 +662,7 @@ struct intel_csr {
        func(has_rc6p) sep \
        func(has_dp_mst) sep \
        func(has_gmbus_irq) sep \
+       func(has_hw_contexts) sep \
        func(has_pipe_cxsr) sep \
        func(has_hotplug) sep \
        func(cursor_needs_physical) sep \
@@ -2746,7 +2747,7 @@ struct drm_i915_cmd_table {
                                 HAS_EDRAM(dev))
 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
 
-#define HAS_HW_CONTEXTS(dev)   (INTEL_INFO(dev)->gen >= 6)
+#define HAS_HW_CONTEXTS(dev)   (INTEL_INFO(dev)->has_hw_contexts)
 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
 #define USES_PPGTT(dev)                (i915.enable_ppgtt)
 #define USES_FULL_PPGTT(dev)   (i915.enable_ppgtt >= 2)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index ca83e6790877b6cee20ebecac01144d17ba43403..0b3b28d8af25b11caa4f33df6727dada81b0ac41 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -193,6 +193,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
        .has_rc6 = 1, \
        .has_rc6p = 1, \
        .has_gmbus_irq = 1, \
+       .has_hw_contexts = 1, \
        GEN_DEFAULT_PIPEOFFSETS, \
        CURSOR_OFFSETS
 
@@ -214,6 +215,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
        .has_rc6 = 1, \
        .has_rc6p = 1, \
        .has_gmbus_irq = 1, \
+       .has_hw_contexts = 1, \
        GEN_DEFAULT_PIPEOFFSETS, \
        IVB_CURSOR_OFFSETS
 
@@ -240,6 +242,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
        .has_runtime_pm = 1, \
        .has_rc6 = 1, \
        .has_gmbus_irq = 1, \
+       .has_hw_contexts = 1, \
        .need_gfx_hws = 1, .has_hotplug = 1, \
        .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
        .display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -294,6 +297,7 @@ static const struct intel_device_info intel_cherryview_info = {
        .has_resource_streamer = 1,
        .has_rc6 = 1,
        .has_gmbus_irq = 1,
+       .has_hw_contexts = 1,
        .display_mmio_offset = VLV_DISPLAY_BASE,
        GEN_CHV_PIPEOFFSETS,
        CURSOR_OFFSETS,
@@ -331,6 +335,7 @@ static const struct intel_device_info intel_broxton_info = {
        .has_rc6 = 1,
        .has_dp_mst = 1,
        .has_gmbus_irq = 1,
+       .has_hw_contexts = 1,
        GEN_DEFAULT_PIPEOFFSETS,
        IVB_CURSOR_OFFSETS,
        BDW_COLORS,