MAC_REG_BBREGCTL - MAC_REG_PSCFG);
/* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
- VNSvOutPortD(io_base + MAC_REG_TXDMAPTR0,
- *(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0));
- VNSvOutPortD(io_base + MAC_REG_AC0DMAPTR,
- *(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR));
- VNSvOutPortD(io_base + MAC_REG_BCNDMAPTR,
- *(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR));
-
- VNSvOutPortD(io_base + MAC_REG_RXDMAPTR0,
- *(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0));
-
- VNSvOutPortD(io_base + MAC_REG_RXDMAPTR1,
- *(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1));
+ iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
+ io_base + MAC_REG_TXDMAPTR0);
+ iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
+ io_base + MAC_REG_AC0DMAPTR);
+ iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
+ io_base + MAC_REG_BCNDMAPTR);
+ iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
+ io_base + MAC_REG_RXDMAPTR0);
+ iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
+ io_base + MAC_REG_RXDMAPTR1);
}
/*
/* turn off wow temp for turn off Rx safely */
/* Clear RX DMA0,1 */
- VNSvOutPortD(io_base + MAC_REG_RXDMACTL0, DMACTL_CLRRUN);
- VNSvOutPortD(io_base + MAC_REG_RXDMACTL1, DMACTL_CLRRUN);
+ iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
+ iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
break;
/* Clear TX DMA */
/* Tx0 */
- VNSvOutPortD(io_base + MAC_REG_TXDMACTL0, DMACTL_CLRRUN);
+ iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
/* AC0 */
- VNSvOutPortD(io_base + MAC_REG_AC0DMACTL, DMACTL_CLRRUN);
+ iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
break;
}
- VNSvOutPortD(io_base + MAC_REG_RXDMAPTR0, dwCurrDescAddr);
+ iowrite32(dwCurrDescAddr, io_base + MAC_REG_RXDMAPTR0);
if (byOrgDMACtl & DMACTL_RUN)
VNSvOutPortB(io_base + MAC_REG_RXDMACTL0, DMACTL_RUN);
}
break;
}
- VNSvOutPortD(io_base + MAC_REG_RXDMAPTR1, dwCurrDescAddr);
+ iowrite32(dwCurrDescAddr, io_base + MAC_REG_RXDMAPTR1);
if (byOrgDMACtl & DMACTL_RUN)
VNSvOutPortB(io_base + MAC_REG_RXDMACTL1, DMACTL_RUN);
break;
}
- VNSvOutPortD(io_base + MAC_REG_TXDMAPTR0, dwCurrDescAddr);
+ iowrite32(dwCurrDescAddr, io_base + MAC_REG_TXDMAPTR0);
if (byOrgDMACtl & DMACTL_RUN)
VNSvOutPortB(io_base + MAC_REG_TXDMACTL0, DMACTL_RUN);
}
}
if (ww == W_MAX_TIMEOUT)
pr_debug(" DBG_PORT80(0x26)\n");
- VNSvOutPortD(io_base + MAC_REG_AC0DMAPTR, dwCurrDescAddr);
+ iowrite32(dwCurrDescAddr, io_base + MAC_REG_AC0DMAPTR);
if (byOrgDMACtl & DMACTL_RUN)
VNSvOutPortB(io_base + MAC_REG_AC0DMACTL, DMACTL_RUN);
}
unsigned int uu, ii;
VNSvOutPortB(io_base + MAC_REG_TMCTL0, 0);
- VNSvOutPortD(io_base + MAC_REG_TMDATA0, uDelay);
+ iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
VNSvOutPortB(io_base + MAC_REG_TMCTL0, (TMCTL_TMD | TMCTL_TE));
for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */
for (uu = 0; uu < uDelay; uu++) {
void __iomem *io_base = priv->PortOffset;
VNSvOutPortB(io_base + MAC_REG_TMCTL1, 0);
- VNSvOutPortD(io_base + MAC_REG_TMDATA1, uDelayTime);
+ iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
VNSvOutPortB(io_base + MAC_REG_TMCTL1, (TMCTL_TMD | TMCTL_TE));
}
if (wOffset > 273)
return;
VNSvOutPortW(io_base + MAC_REG_MISCFFNDEX, wOffset);
- VNSvOutPortD(io_base + MAC_REG_MISCFFDATA, dwData);
+ iowrite32(dwData, io_base + MAC_REG_MISCFFDATA);
VNSvOutPortW(io_base + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
}
wOffset, dwData, wKeyCtl);
VNSvOutPortW(io_base + MAC_REG_MISCFFNDEX, wOffset);
- VNSvOutPortD(io_base + MAC_REG_MISCFFDATA, dwData);
+ iowrite32(dwData, io_base + MAC_REG_MISCFFDATA);
VNSvOutPortW(io_base + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
wOffset++;
pr_debug("2. wOffset: %d, Data: %X\n", wOffset, dwData);
VNSvOutPortW(io_base + MAC_REG_MISCFFNDEX, wOffset);
- VNSvOutPortD(io_base + MAC_REG_MISCFFDATA, dwData);
+ iowrite32(dwData, io_base + MAC_REG_MISCFFDATA);
VNSvOutPortW(io_base + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
wOffset++;
pr_debug("3.(%d) wOffset: %d, Data: %X\n",
ii, wOffset+ii, *pdwKey);
VNSvOutPortW(io_base + MAC_REG_MISCFFNDEX, wOffset+ii);
- VNSvOutPortD(io_base + MAC_REG_MISCFFDATA, *pdwKey++);
+ iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
VNSvOutPortW(io_base + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
}
}
wOffset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
VNSvOutPortW(io_base + MAC_REG_MISCFFNDEX, wOffset);
- VNSvOutPortD(io_base + MAC_REG_MISCFFDATA, 0);
+ iowrite32(0, io_base + MAC_REG_MISCFFDATA);
VNSvOutPortW(io_base + MAC_REG_MISCFFCTL, MISCFFCTL_WRITE);
}