BRCMF_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
-/* Core reg address translation */
+/*
+ * Core reg address translation.
+ * Both macro's returns a 32 bits byte address on the backplane bus.
+ */
#define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
#define CORE_BUS_REG(base, field) \
(base + offsetof(struct sdpcmd_regs, field))
u32 cccorebase;
u32 ccrev;
u32 cccaps;
- u32 buscorebase;
+ u32 buscorebase; /* 32 bits backplane bus address */
u32 buscorerev;
u32 buscoretype;
u32 ramcorebase;
uint varsz; /* Size of variables buffer */
u32 sbaddr; /* Current SB window pointer (-1, invalid) */
- struct sdpcmd_regs *regs; /* SDIO core */
+ /* SDIO core, 32 bit address on the backplane bus: */
+ struct sdpcmd_regs *regs;
uint sdpcmrev; /* SDIO core revision */
uint armrev; /* CPU core revision */
uint ramrev; /* SOCRAM core revision */
(((u8)(bus->tx_max - bus->tx_seq) != 0) && \
(((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
-/* Macros to get register read/write status */
-/* NOTE: these assume a local dhdsdio_bus_t *bus! */
-#define R_SDREG(regvar, regaddr, retryvar, typ) \
-do { \
- retryvar = 0; \
- do { \
- regvar = R_REG((u32)(regaddr), typ); \
- } while (brcmf_sdcard_regfail(bus->card) && \
- (++retryvar <= retry_limit)); \
- if (retryvar) { \
- bus->regfails += (retryvar-1); \
- if (retryvar > retry_limit) { \
- DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
- __func__, __LINE__)); \
- regvar = 0; \
- } \
- } \
-} while (0)
+/*
+ * Reads a register in the SDIO hardware block. This block occupies a series of
+ * adresses on the 32 bit backplane bus.
+ */
+static void
+r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
+{
+ *retryvar = 0;
+ do {
+ *regvar = R_REG(bus->ci->buscorebase + reg_offset, u32);
+ } while (brcmf_sdcard_regfail(bus->card) &&
+ (++(*retryvar) <= retry_limit));
+ if (*retryvar) {
+ bus->regfails += (*retryvar-1);
+ if (*retryvar > retry_limit) {
+ DHD_ERROR(("FAILED READ %Xh\n", reg_offset));
+ *regvar = 0;
+ }
+ }
+}
#define W_SDREG(regval, regaddr, retryvar, typ) \
do { \
if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
&& (bus->ci->buscorerev == 9))) {
u32 dummy, retries;
- R_SDREG(dummy, &bus->regs->clockctlstatus, retries,
- u32);
+ r_sdreg32(bus, &dummy,
+ offsetof(struct sdpcmd_regs, clockctlstatus),
+ &retries);
}
/* Check current status */
u8 tx_prec_map;
struct brcmf_pub *drvr = bus->drvr;
- struct sdpcmd_regs *regs = bus->regs;
DHD_TRACE(("%s: Enter\n", __func__));
/* In poll mode, need to check for other events */
if (!bus->intr && cnt) {
/* Check device status, signal pending interrupt */
- R_SDREG(intstatus, ®s->intstatus, retries, u32);
+ r_sdreg32(bus, &intstatus,
+ offsetof(struct sdpcmd_regs, intstatus),
+ &retries);
bus->f2txdata++;
if (brcmf_sdcard_regfail(bus->card))
break;
DHD_TRACE(("%s: Enter\n", __func__));
/* Read mailbox data and ack that we did so */
- R_SDREG(hmb_data, ®s->tohostmailboxdata, retries, u32);
+ r_sdreg32(bus, &hmb_data,
+ offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
+
if (retries <= retry_limit)
W_SDREG(SMB_INT_ACK, ®s->tosbmailbox, retries, u32);
bus->f1regdata += 2;
/* Pending interrupt indicates new device status */
if (bus->ipend) {
bus->ipend = false;
- R_SDREG(newstatus, ®s->intstatus, retries, u32);
+ r_sdreg32(bus, &newstatus,
+ offsetof(struct sdpcmd_regs, intstatus), &retries);
bus->f1regdata++;
if (brcmf_sdcard_regfail(bus->card))
newstatus = 0;
if (intstatus & I_HMB_FC_CHANGE) {
intstatus &= ~I_HMB_FC_CHANGE;
W_SDREG(I_HMB_FC_CHANGE, ®s->intstatus, retries, u32);
- R_SDREG(newstatus, ®s->intstatus, retries, u32);
+ r_sdreg32(bus, &newstatus,
+ offsetof(struct sdpcmd_regs, intstatus), &retries);
bus->f1regdata += 2;
bus->fcstate =
!!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));