#define MX6Q_SABREAUTO_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
#define MX6Q_SABREAUTO_SD3_CD IMX_GPIO_NR(6, 11)
#define MX6Q_SABREAUTO_SD3_WP IMX_GPIO_NR(6, 14)
+#define MX6Q_SABREAUTO_MAX7310_1_BASE_ADDR IMX_GPIO_NR(8, 0)
+#define MX6Q_SABREAUTO_CAP_TCH_INT IMX_GPIO_NR(3, 31)
void __init early_console_setup(unsigned long base, struct clk *clk);
MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
MX6Q_PAD_EIM_D17__ECSPI1_MISO,
MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
+
+ /* I2C2 */
+ MX6Q_PAD_KEY_COL3__I2C2_SCL,
+ MX6Q_PAD_KEY_ROW3__I2C2_SDA,
+
+ /* I2C3 */
+ MX6Q_PAD_GPIO_5__I2C3_SCL,
+ MX6Q_PAD_GPIO_16__I2C3_SDA,
};
static const struct esdhc_platform_data mx6q_sabreauto_sd3_data __initconst = {
.num_chipselect = ARRAY_SIZE(mx6q_sabreauto_spi_cs),
};
+static int max7310_1_setup(struct i2c_client *client,
+ unsigned gpio_base, unsigned ngpio,
+ void *context)
+{
+ static int max7310_gpio_value[] = {
+ 0, 1, 0, 0, 0, 0, 0, 0,
+ };
+
+ int n;
+
+ for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) {
+ gpio_request(gpio_base + n, "MAX7310 1 GPIO Expander");
+ if (max7310_gpio_value[n] < 0)
+ gpio_direction_input(gpio_base + n);
+ else
+ gpio_direction_output(gpio_base + n,
+ max7310_gpio_value[n]);
+ gpio_export(gpio_base + n, 0);
+ }
+
+ return 0;
+}
+
+static struct pca953x_platform_data max7310_platdata = {
+ .gpio_base = MX6Q_SABREAUTO_MAX7310_1_BASE_ADDR,
+ .invert = 0,
+ .setup = max7310_1_setup,
+};
+
+static struct imxi2c_platform_data mx6q_sabreauto_i2c_data = {
+ .bitrate = 400000,
+};
+
+static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
+ {
+ I2C_BOARD_INFO("max7310", 0x1F),
+ .platform_data = &max7310_platdata,
+ },
+};
+
/*!
* Board specific initialization.
*/
ARRAY_SIZE(mx6q_sabreauto_pads));
mx6q_sabreauto_init_uart();
+ imx6q_add_imx_i2c(1, &mx6q_sabreauto_i2c_data);
+ imx6q_add_imx_i2c(2, &mx6q_sabreauto_i2c_data);
+ i2c_register_board_info(2, mxc_i2c2_board_info,
+ ARRAY_SIZE(mxc_i2c2_board_info));
imx6q_add_sdhci_usdhc_imx(3, &mx6q_sabreauto_sd4_data);
}
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define MX6Q_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_HYS | PAD_CTL_SPEED_MED)
+
#define _MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 \
IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 \
#define _MX6Q_PAD_EIM_EB2__GPIO_2_30 \
IOMUX_PAD(0x03A0, 0x008C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_EB2__I2C2_SCL \
- IOMUX_PAD(0x03A0, 0x008C, 6, 0x08A0, 0, 0)
+ IOMUX_PAD(0x03A0, 0x008C, 6 | IOMUX_CONFIG_SION, 0x08A0, 0, 0)
#define _MX6Q_PAD_EIM_EB2__SRC_BT_CFG_30 \
IOMUX_PAD(0x03A0, 0x008C, 7, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D16__GPIO_3_16 \
IOMUX_PAD(0x03A4, 0x0090, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D16__I2C2_SDA \
- IOMUX_PAD(0x03A4, 0x0090, 6, 0x08A4, 0, 0)
+ IOMUX_PAD(0x03A4, 0x0090, 6 | IOMUX_CONFIG_SION, 0x08A4, 0, 0)
#define _MX6Q_PAD_EIM_D17__WEIM_WEIM_D_17 \
IOMUX_PAD(0x03A8, 0x0094, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D17__GPIO_3_17 \
IOMUX_PAD(0x03A8, 0x0094, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D17__I2C3_SCL \
- IOMUX_PAD(0x03A8, 0x0094, 6, 0x08A8, 0, 0)
+ IOMUX_PAD(0x03A8, 0x0094, 6 | IOMUX_CONFIG_SION, 0x08A8, 0, 0)
#define _MX6Q_PAD_EIM_D17__PL301_MX6QPER1_HBURST_1 \
IOMUX_PAD(0x03A8, 0x0094, 7, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D18__GPIO_3_18 \
IOMUX_PAD(0x03AC, 0x0098, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D18__I2C3_SDA \
- IOMUX_PAD(0x03AC, 0x0098, 6, 0x08AC, 0, 0)
+ IOMUX_PAD(0x03AC, 0x0098, 6 | IOMUX_CONFIG_SION, 0x08AC, 0, 0)
#define _MX6Q_PAD_EIM_D18__PL301_MX6QPER1_HBURST_2 \
IOMUX_PAD(0x03AC, 0x0098, 7, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D21__GPIO_3_21 \
IOMUX_PAD(0x03B8, 0x00A4, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D21__I2C1_SCL \
- IOMUX_PAD(0x03B8, 0x00A4, 6, 0x0898, 0, 0)
+ IOMUX_PAD(0x03B8, 0x00A4, 6 | IOMUX_CONFIG_SION, 0x0898, 0, 0)
#define _MX6Q_PAD_EIM_D21__SPDIF_IN1 \
IOMUX_PAD(0x03B8, 0x00A4, 7, 0x0914, 0, 0)
#define _MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \
IOMUX_PAD(0x03D8, 0x00C4, 0, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D28__I2C1_SDA \
- IOMUX_PAD(0x03D8, 0x00C4, 1, 0x089C, 0, 0)
+ IOMUX_PAD(0x03D8, 0x00C4, 1 | IOMUX_CONFIG_SION, 0x089C, 0, 0)
#define _MX6Q_PAD_EIM_D28__ECSPI4_MOSI \
IOMUX_PAD(0x03D8, 0x00C4, 2, 0x0000, 0, 0)
#define _MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \
#define _MX6Q_PAD_KEY_COL3__KPP_COL_3 \
IOMUX_PAD(0x05E0, 0x0210, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL3__I2C2_SCL \
- IOMUX_PAD(0x05E0, 0x0210, 4, 0x08A0, 1, 0)
+ IOMUX_PAD(0x05E0, 0x0210, 4 | IOMUX_CONFIG_SION, 0x08A0, 1, 0)
#define _MX6Q_PAD_KEY_COL3__GPIO_4_12 \
IOMUX_PAD(0x05E0, 0x0210, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
#define _MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
IOMUX_PAD(0x05E4, 0x0214, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW3__I2C2_SDA \
- IOMUX_PAD(0x05E4, 0x0214, 4, 0x08A4, 1, 0)
+ IOMUX_PAD(0x05E4, 0x0214, 4 | IOMUX_CONFIG_SION, 0x08A4, 1, 0)
#define _MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
IOMUX_PAD(0x05E4, 0x0214, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
#define _MX6Q_PAD_GPIO_3__OBSERVE_MUX_OBSRV_INT_OUT0 \
IOMUX_PAD(0x05FC, 0x022C, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_3__I2C3_SCL \
- IOMUX_PAD(0x05FC, 0x022C, 2, 0x08A8, 1, 0)
+ IOMUX_PAD(0x05FC, 0x022C, 2 | IOMUX_CONFIG_SION, 0x08A8, 1, 0)
#define _MX6Q_PAD_GPIO_3__ANATOP_ANATOP_24M_OUT \
IOMUX_PAD(0x05FC, 0x022C, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_3__CCM_CLKO2 \
#define _MX6Q_PAD_GPIO_6__OBSERVE_MUX_OBSRV_INT_OUT1 \
IOMUX_PAD(0x0600, 0x0230, 1, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_6__I2C3_SDA \
- IOMUX_PAD(0x0600, 0x0230, 2, 0x08AC, 1, 0)
+ IOMUX_PAD(0x0600, 0x0230, 2 | IOMUX_CONFIG_SION, 0x08AC, 1, 0)
#define _MX6Q_PAD_GPIO_6__CCM_CCM_OUT_0 \
IOMUX_PAD(0x0600, 0x0230, 3, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_6__CSU_CSU_INT_DEB \
#define _MX6Q_PAD_GPIO_5__GPIO_1_5 \
IOMUX_PAD(0x060C, 0x023C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_5__I2C3_SCL \
- IOMUX_PAD(0x060C, 0x023C, 6, 0x08A8, 2, 0)
+ IOMUX_PAD(0x060C, 0x023C, 6 | IOMUX_CONFIG_SION, 0x08A8, 2, 0)
#define _MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
IOMUX_PAD(0x060C, 0x023C, 7, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_16__GPIO_7_11 \
IOMUX_PAD(0x0618, 0x0248, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_GPIO_16__I2C3_SDA \
- IOMUX_PAD(0x0618, 0x0248, 6, 0x08AC, 2, 0)
+ IOMUX_PAD(0x0618, 0x0248, 6 | IOMUX_CONFIG_SION, 0x08AC, 2, 0)
#define _MX6Q_PAD_GPIO_16__SJC_DE_B \
IOMUX_PAD(0x0618, 0x0248, 7, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT8__KPP_COL_7 \
IOMUX_PAD(0x0648, 0x0278, 3, 0x08F0, 2, 0)
#define _MX6Q_PAD_CSI0_DAT8__I2C1_SDA \
- IOMUX_PAD(0x0648, 0x0278, 4, 0x089C, 1, 0)
+ IOMUX_PAD(0x0648, 0x0278, 4 | IOMUX_CONFIG_SION, 0x089C, 1, 0)
#define _MX6Q_PAD_CSI0_DAT8__GPIO_5_26 \
IOMUX_PAD(0x0648, 0x0278, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT8__MMDC_MMDC_DEBUG_47 \
#define _MX6Q_PAD_CSI0_DAT9__KPP_ROW_7 \
IOMUX_PAD(0x064C, 0x027C, 3, 0x08FC, 2, 0)
#define _MX6Q_PAD_CSI0_DAT9__I2C1_SCL \
- IOMUX_PAD(0x064C, 0x027C, 4, 0x0898, 1, 0)
+ IOMUX_PAD(0x064C, 0x027C, 4 | IOMUX_CONFIG_SION, 0x0898, 1, 0)
#define _MX6Q_PAD_CSI0_DAT9__GPIO_5_27 \
IOMUX_PAD(0x064C, 0x027C, 5, 0x0000, 0, 0)
#define _MX6Q_PAD_CSI0_DAT9__MMDC_MMDC_DEBUG_48 \
#define MX6Q_PAD_KEY_COL3__KPP_COL_3 \
(_MX6Q_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_KEY_COL3__I2C2_SCL \
- (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define MX6Q_PAD_KEY_COL3__GPIO_4_12 \
(_MX6Q_PAD_KEY_COL3__GPIO_4_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_KEY_COL3__SPDIF_IN1 \
#define MX6Q_PAD_KEY_ROW3__KPP_ROW_3 \
(_MX6Q_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_KEY_ROW3__I2C2_SDA \
- (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define MX6Q_PAD_KEY_ROW3__GPIO_4_13 \
(_MX6Q_PAD_KEY_ROW3__GPIO_4_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_KEY_ROW3__USDHC1_VSELECT \
#define MX6Q_PAD_GPIO_5__GPIO_1_5 \
(_MX6Q_PAD_GPIO_5__GPIO_1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_GPIO_5__I2C3_SCL \
- (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_GPIO_5__I2C3_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define MX6Q_PAD_GPIO_5__CHEETAH_EVENTI \
(_MX6Q_PAD_GPIO_5__CHEETAH_EVENTI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_GPIO_16__GPIO_7_11 \
(_MX6Q_PAD_GPIO_16__GPIO_7_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX6Q_PAD_GPIO_16__I2C3_SDA \
- (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
+ (_MX6Q_PAD_GPIO_16__I2C3_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL))
#define MX6Q_PAD_GPIO_16__SJC_DE_B \
(_MX6Q_PAD_GPIO_16__SJC_DE_B | MUX_PAD_CTRL(NO_PAD_CTRL))