powerpc: Name xpn & x fields in HW Hash PTE format

Previously, the 36-bit code was using these bits, but they had
never been named in the pte format definition.  This patch just
gives those fields their proper names and adds a comment that
they are only present on some processors.

There is no functional code change.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/include/asm/mmu-hash32.h b/arch/powerpc/include/asm/mmu-hash32.h
index 382fc689f204340ee60c1dd58b32ee9e0f621c78..16f513e5cbd74f2cc42460ba3c7d28524bb86e81 100644 (file)
--- a/arch/powerpc/include/asm/mmu-hash32.h
+++ b/arch/powerpc/include/asm/mmu-hash32.h
@@ -55,21 +55,25 @@ struct ppc_bat {
 
 #ifndef __ASSEMBLY__
 
-/* Hardware Page Table Entry */
+/*
+ * Hardware Page Table Entry
+ * Note that the xpn and x bitfields are used only by processors that
+ * support extended addressing; otherwise, those bits are reserved.
+ */
 struct hash_pte {
        unsigned long v:1;      /* Entry is valid */
        unsigned long vsid:24;  /* Virtual segment identifier */
        unsigned long h:1;      /* Hash algorithm indicator */
        unsigned long api:6;    /* Abbreviated page index */
        unsigned long rpn:20;   /* Real (physical) page number */
-       unsigned long    :3;    /* Unused */
+       unsigned long xpn:3;    /* Real page number bits 0-2, optional */
        unsigned long r:1;      /* Referenced */
        unsigned long c:1;      /* Changed */
        unsigned long w:1;      /* Write-thru cache mode */
        unsigned long i:1;      /* Cache inhibited */
        unsigned long m:1;      /* Memory coherence */
        unsigned long g:1;      /* Guarded */
-       unsigned long  :1;      /* Unused */
+       unsigned long x:1;      /* Real page number bit 3, optional */
        unsigned long pp:2;     /* Page protection */
 };