mmc: dw_mmc: correct the calculation for CLKDIV

In case of "host->bus_hz < slot->clock", divider value is
miscalculated. And clock divider register value is multiple of 2. If
calculated divider value is odd number, result can be over-clocking.

Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Acked-by: Will Newton <will.newton@gmail.com>
Signed-off-by: Chris Ball <cjb@laptop.org>

diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index b070ee542c8ee501934b5618423442cb02e5e1b2..1ca5e72ceb651e84544a8cc451698ea54de6aafd 100644 (file)
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -617,14 +617,15 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot)
        u32 div;
 
        if (slot->clock != host->current_speed) {
-               if (host->bus_hz % slot->clock)
+               div = host->bus_hz / slot->clock;
+               if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
                        /*
                         * move the + 1 after the divide to prevent
                         * over-clocking the card.
                         */
-                       div = ((host->bus_hz / slot->clock) >> 1) + 1;
-               else
-                       div = (host->bus_hz  / slot->clock) >> 1;
+                       div += 1;
+
+               div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
 
                dev_info(&slot->mmc->class_dev,
                         "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"