drm/i915: Don't multiply the watermark latency values too early

The LP1+ watermark latency values need to be multiplied by 5 to
make them suitable for watermark calculations. However on pre-HSW
platforms we're going to need the raw value later when we have to
write it to the WM_LPn registers' latency field. So delay the
multiplication until it's needed.

Note: Paulo complains that the units of wm (now in 100ns) aren't
really clear and I agree. But that can be fixed later on ...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Add a comment about the unit obfuscation.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b8ec1433531dec0a51cf8b86eb99688c1fa4576c..b6430bacc7dc142d8e607dbf5f64b480ae4b0a81 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2361,10 +2361,10 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
                wm[0] = (sskpd >> 56) & 0xFF;
                if (wm[0] == 0)
                        wm[0] = sskpd & 0xF;
-               wm[1] = ((sskpd >> 4) & 0xFF) * 5;
-               wm[2] = ((sskpd >> 12) & 0xFF) * 5;
-               wm[3] = ((sskpd >> 20) & 0x1FF) * 5;
-               wm[4] = ((sskpd >> 32) & 0x1FF) * 5;
+               wm[1] = (sskpd >> 4) & 0xFF;
+               wm[2] = (sskpd >> 12) & 0xFF;
+               wm[3] = (sskpd >> 20) & 0x1FF;
+               wm[4] = (sskpd >> 32) & 0x1FF;
        }
 }
 
@@ -2442,7 +2442,7 @@ static void hsw_compute_wm_results(struct drm_device *dev,
        int level, max_level, wm_lp;
 
        for (level = 1; level <= 4; level++)
-               if (!hsw_compute_lp_wm(wm[level], lp_maximums, params,
+               if (!hsw_compute_lp_wm(wm[level] * 5, lp_maximums, params,
                                       &lp_results[level - 1]))
                        break;
        max_level = level - 1;