ARC: No-op full icache flush if !CONFIG_ARC_HAS_ICACHE

Also remove extraneous irq disabling in flush_cache_all() callstack

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

diff --git a/arch/arc/include/asm/pgtable.h b/arch/arc/include/asm/pgtable.h
index f31dc817fe120d35fc4e8ecea0a2bf1d5f75d94c..fd57524c0b5ba0ab673a6cd2bf02f6ce08578cfa 100644 (file)
--- a/arch/arc/include/asm/pgtable.h
+++ b/arch/arc/include/asm/pgtable.h
@@ -136,10 +136,9 @@
 #define PAGE_KERNEL_NO_CACHE __pgprot(_K_PAGE_PERMS)
 
 /* Masks for actual TLB "PD"s */
-#define PTE_BITS_IN_PD0        (_PAGE_GLOBAL | _PAGE_PRESENT)
-#define PTE_BITS_IN_PD1        (PAGE_MASK | _PAGE_CACHEABLE | \
-                        _PAGE_U_EXECUTE | _PAGE_U_WRITE | _PAGE_U_READ | \
-                        _PAGE_K_EXECUTE | _PAGE_K_WRITE | _PAGE_K_READ)
+#define PTE_BITS_IN_PD0                (_PAGE_GLOBAL | _PAGE_PRESENT)
+#define PTE_BITS_RWX           (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ)
+#define PTE_BITS_NON_RWX_IN_PD1        (PAGE_MASK | _PAGE_CACHEABLE)
 
 /**************************************************************************
  * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)

diff --git a/arch/arc/mm/cache_arc700.c b/arch/arc/mm/cache_arc700.c
index 0a56682e0c9456ce6d6f253afce3a78318a5ed4d..03012a27d590e74dd1b4114a355ffbdc5fc4ffae 100644 (file)
--- a/arch/arc/mm/cache_arc700.c
+++ b/arch/arc/mm/cache_arc700.c
@@ -261,11 +261,9 @@ static inline void wait_for_flush(void)
  */
 static inline void __dc_entire_op(const int cacheop)
 {
-       unsigned long flags, tmp = tmp;
+       unsigned int tmp = tmp;
        int aux;
 
-       local_irq_save(flags);
-
        if (cacheop == OP_FLUSH_N_INV) {
                /* Dcache provides 2 cmd: FLUSH or INV
                 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
@@ -289,8 +287,6 @@ static inline void __dc_entire_op(const int cacheop)
        /* Switch back the DISCARD ONLY Invalidate mode */
        if (cacheop == OP_FLUSH_N_INV)
                write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
-
-       local_irq_restore(flags);
 }
 
 /*
@@ -481,8 +477,15 @@ static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr,
        local_irq_restore(flags);
 }
 
+static inline void __ic_entire_inv(void)
+{
+       write_aux_reg(ARC_REG_IC_IVIC, 1);
+       read_aux_reg(ARC_REG_IC_CTRL);  /* blocks */
+}
+
 #else
 
+#define __ic_entire_inv()
 #define __ic_line_inv_vaddr(pstart, vstart, sz)
 
 #endif /* CONFIG_ARC_HAS_ICACHE */
@@ -651,26 +654,13 @@ void ___flush_dcache_page(unsigned long paddr, unsigned long vaddr)
        __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV);
 }
 
-void flush_icache_all(void)
-{
-       unsigned long flags;
-
-       local_irq_save(flags);
-
-       write_aux_reg(ARC_REG_IC_IVIC, 1);
-
-       /* lr will not complete till the icache inv operation is not over */
-       read_aux_reg(ARC_REG_IC_CTRL);
-       local_irq_restore(flags);
-}
-
 noinline void flush_cache_all(void)
 {
        unsigned long flags;
 
        local_irq_save(flags);
 
-       flush_icache_all();
+       __ic_entire_inv();
        __dc_entire_op(OP_FLUSH_N_INV);
 
        local_irq_restore(flags);