]> git.karo-electronics.de Git - linux-beck.git/commitdiff
ARM: dts: imx: ventana: Allow HDMI and LVDS to work simultaneously
authorTim Harvey <tharvey@gateworks.com>
Fri, 6 Nov 2015 22:40:32 +0000 (14:40 -0800)
committerShawn Guo <shawnguo@kernel.org>
Tue, 22 Dec 2015 12:42:23 +0000 (20:42 +0800)
Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.

Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.

With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the displays supported by the Ventana boards.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
arch/arm/boot/dts/imx6qdl-gw54xx.dtsi

index 18cd4114a23e85a82f724c3b8773c04399826129..5478ab6b078eb7082bb45d5ce8c4fca0039cb2b0 100644 (file)
        status = "okay";
 };
 
+&clks {
+       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+                         <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
 &fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
index efef049c9a0b6829a7fadc0b7730599dc2d30cf4..8ccf5e4f32ead5697b2650514bdbf13756c8d4f0 100644 (file)
        status = "okay";
 };
 
+&clks {
+       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+                         <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
 &fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
index fe71d36c1b66481e4cdf31aabb94a33f1754a91c..7b50b1e552801b93bb808e96038d9a6bd998da11 100644 (file)
        status = "okay";
 };
 
+&clks {
+       assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+                         <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+       assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
+                         <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
+};
+
 &fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;