serial: 8250_pci: all known Braswell ports are 1 channel

There is no need to have channel offset defined since all BayTrail and Braswell
ports are 1 channel. Remove unneeded definition.

While here, remove comment which has no value.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/8250/8250_pci.c b/drivers/tty/serial/8250/8250_pci.c
index 4a8b1078ada75aca9c5a33aafe09260cf4933bb9..fb64c74c4256a12f838753697f52491d6b6ada64 100644 (file)
--- a/drivers/tty/serial/8250/8250_pci.c
+++ b/drivers/tty/serial/8250/8250_pci.c
@@ -3698,15 +3698,10 @@ static struct pciserial_board pci_boards[] = {
                .base_baud      = 921600,
                .reg_shift      = 2,
        },
-       /*
-        * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
-        * but is overridden by byt_set_termios.
-        */
        [pbn_byt] = {
                .flags          = FL_BASE0,
                .num_ports      = 1,
                .base_baud      = 2764800,
-               .uart_offset    = 0x80,
                .reg_shift      = 2,
        },
        [pbn_qrk] = {