x86, xsave: Support eager-only xsave features, add MPX support

Some features, like Intel MPX, work only if the kernel uses eagerfpu
model.  So we should force eagerfpu on unless the user has explicitly
disabled it.

Add definitions for Intel MPX and add it to the supported list.

[ hpa: renamed XSTATE_FLEXIBLE to XSTATE_LAZY and added comments ]

Signed-off-by: Qiaowei Ren <qiaowei.ren@intel.com>
Link: http://lkml.kernel.org/r/9E0BE1322F2F2246BD820DA9FC397ADE014A6115@SHSMSX102.ccr.corp.intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 7b034a4057f93c7cf01a5bc65204e723fff137e8..b7845a1267920fca8b2053bc1eb0e8726040949b 100644 (file)
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -370,6 +370,26 @@ struct ymmh_struct {
        u32 ymmh_space[64];
 };
 
+struct lwp_struct {
+       u64 lwpcb_addr;
+       u32 flags;
+       u32 buf_head_offset;
+       u64 buf_base;
+       u32 buf_size;
+       u32 filters;
+       u64 saved_event_record[4];
+       u32 event_counter[16];
+};
+
+struct bndregs_struct {
+       u64 bndregs[8];
+} __packed;
+
+struct bndcsr_struct {
+       u64 cfg_reg_u;
+       u64 status_reg;
+} __packed;
+
 struct xsave_hdr_struct {
        u64 xstate_bv;
        u64 reserved1[2];
@@ -380,6 +400,9 @@ struct xsave_struct {
        struct i387_fxsave_struct i387;
        struct xsave_hdr_struct xsave_hdr;
        struct ymmh_struct ymmh;
+       struct lwp_struct lwp;
+       struct bndregs_struct bndregs;
+       struct bndcsr_struct bndcsr;
        /* new processor state extensions will go here */
 } __attribute__ ((packed, aligned (64)));
 

diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 0415cdabb5a663d1684284525a3fe24b7b3cd359..554738963b28cf47dd76fa9947338bb1eae5a0d0 100644 (file)
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -9,6 +9,8 @@
 #define XSTATE_FP      0x1
 #define XSTATE_SSE     0x2
 #define XSTATE_YMM     0x4
+#define XSTATE_BNDREGS 0x8
+#define XSTATE_BNDCSR  0x10
 
 #define XSTATE_FPSSE   (XSTATE_FP | XSTATE_SSE)
 
@@ -20,10 +22,14 @@
 #define XSAVE_YMM_SIZE     256
 #define XSAVE_YMM_OFFSET    (XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET)
 
-/*
- * These are the features that the OS can handle currently.
- */
-#define XCNTXT_MASK    (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
+/* Supported features which support lazy state saving */
+#define XSTATE_LAZY    (XSTATE_FP | XSTATE_SSE | XSTATE_YMM)
+
+/* Supported features which require eager state saving */
+#define XSTATE_EAGER   (XSTATE_BNDREGS | XSTATE_BNDCSR)
+
+/* All currently supported features */
+#define XCNTXT_MASK    (XSTATE_LAZY | XSTATE_EAGER)
 
 #ifdef CONFIG_X86_64
 #define REX_PREFIX     "0x48, "

diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c
index 422fd82234700fe46f7ac12fe150665d0977e3b9..a4b451c6addfb7085a22c70b408614a58bf0ad7b 100644 (file)
--- a/arch/x86/kernel/xsave.c
+++ b/arch/x86/kernel/xsave.c
@@ -562,6 +562,16 @@ static void __init xstate_enable_boot_cpu(void)
        if (cpu_has_xsaveopt && eagerfpu != DISABLE)
                eagerfpu = ENABLE;
 
+       if (pcntxt_mask & XSTATE_EAGER) {
+               if (eagerfpu == DISABLE) {
+                       pr_err("eagerfpu not present, disabling some xstate features: 0x%llx\n",
+                                       pcntxt_mask & XSTATE_EAGER);
+                       pcntxt_mask &= ~XSTATE_EAGER;
+               } else {
+                       eagerfpu = ENABLE;
+               }
+       }
+
        pr_info("enabled xstate_bv 0x%llx, cntxt size 0x%x\n",
                pcntxt_mask, xstate_size);
 }