arm64: dts: exynos: Add DECON_TV node to Exynos5433

DECON_TV is 2nd display controller on Exynos5433, used in HDMI path
or 2nd DSI path.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index abaf6b4d599deeb29c9ccff83f9aacfa7338c80c..80dc0e8344b2ced5629497ff4c5e7a2d8b27570a 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -751,6 +751,29 @@
                        };
                };
 
+               decon_tv: decon@13880000 {
+                       compatible = "samsung,exynos5433-decon-tv";
+                       reg = <0x13880000 0x20b8>;
+                       clocks = <&cmu_disp CLK_PCLK_DECON_TV>,
+                                <&cmu_disp CLK_ACLK_DECON_TV>,
+                                <&cmu_disp CLK_ACLK_SMMU_TV0X>,
+                                <&cmu_disp CLK_ACLK_XIU_TV0X>,
+                                <&cmu_disp CLK_PCLK_SMMU_TV0X>,
+                                <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
+                                <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
+                       clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
+                                     "aclk_xiu_decon0x", "pclk_smmu_decon0x",
+                                     "sclk_decon_vclk", "sclk_decon_eclk";
+                       samsung,disp-sysreg = <&syscon_disp>;
+                       interrupt-names = "fifo", "vsync", "lcd_sys";
+                       interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+                       iommus = <&sysmmu_tv0x>, <&sysmmu_tv1x>;
+                       iommu-names = "m0", "m1";
+               };
+
                dsi: dsi@13900000 {
                        compatible = "samsung,exynos5433-mipi-dsi";
                        reg = <0x13900000 0xC0>;
@@ -912,6 +935,26 @@
                        #iommu-cells = <0>;
                };
 
+               sysmmu_tv0x: sysmmu@13a20000 {
+                       compatible = "samsung,exynos-sysmmu";
+                       reg = <0x13a20000 0x1000>;
+                       interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "pclk", "aclk";
+                       clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
+                               <&cmu_disp CLK_ACLK_SMMU_TV0X>;
+                       #iommu-cells = <0>;
+               };
+
+               sysmmu_tv1x: sysmmu@13a30000 {
+                       compatible = "samsung,exynos-sysmmu";
+                       reg = <0x13a30000 0x1000>;
+                       interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "pclk", "aclk";
+                       clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
+                               <&cmu_disp CLK_ACLK_SMMU_TV1X>;
+                       #iommu-cells = <0>;
+               };
+
                sysmmu_gscl0: sysmmu@13c80000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13C80000 0x1000>;