Merge tag 'drm-intel-next-fixes-2016-08-05' of git://anongit.freedesktop.org/drm...

3 intel fixes.

* tag 'drm-intel-next-fixes-2016-08-05' of git://anongit.freedesktop.org/drm-intel:
  drm/i915/fbdev: Check for the framebuffer before use
  drm/i915: Never fully mask the the EI up rps interrupt on SNB/IVB
  drm/i915: Wait up to 3ms for the pcu to ack the cdclk change request on SKL

diff --combined drivers/gpu/drm/i915/intel_display.c
index c457eed76f1f7a1fca441d4714c2aebf95534d05,e5c46a6ec65bfa3197967b0c4a83b703afd1c985..baeb75388dbe5da96c3f8e4aa0c86266415d7808
--- 1/drivers/gpu/drm/i915/intel_display.c
--- 2/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -5691,15 -5691,7 +5691,7 @@@ static bool skl_cdclk_pcu_ready(struct 
  
  static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
  {
-       unsigned int i;
- 
-       for (i = 0; i < 15; i++) {
-               if (skl_cdclk_pcu_ready(dev_priv))
-                       return true;
-               udelay(10);
-       }
- 
-       return false;
+       return _wait_for(skl_cdclk_pcu_ready(dev_priv), 3000, 10) == 0;
  }
  
  static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
@@@ -12016,12 -12008,6 +12008,12 @@@ static int intel_crtc_atomic_check(stru
                ret = intel_color_check(crtc, crtc_state);
                if (ret)
                        return ret;
 +
 +              /*
 +               * Changing color management on Intel hardware is
 +               * handled as part of planes update.
 +               */
 +              crtc_state->planes_changed = true;
        }
  
        ret = 0;

diff --combined drivers/gpu/drm/i915/intel_pm.c
index f4f3fcc8b3becb59c0ed5d6bdd5dd27a177f3731,5ca68d2ed7d4057fb8e6f51e4313644b751e0183..97ba6c8cf907862197a42bbd9935030df0e16856
--- 1/drivers/gpu/drm/i915/intel_pm.c
--- 2/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@@ -57,7 -57,7 +57,7 @@@
  
  static void gen9_init_clock_gating(struct drm_device *dev)
  {
 -      struct drm_i915_private *dev_priv = to_i915(dev);
 +      struct drm_i915_private *dev_priv = dev->dev_private;
  
        /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
        I915_WRITE(CHICKEN_PAR1_1,
@@@ -4892,7 -4892,8 +4892,8 @@@ void gen6_rps_idle(struct drm_i915_priv
                else
                        gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
                dev_priv->rps.last_adj = 0;
-               I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
+               I915_WRITE(GEN6_PMINTRMSK,
+                          gen6_sanitize_rps_pm_mask(dev_priv, ~0));
        }
        mutex_unlock(&dev_priv->rps.hw_lock);
  
@@@ -7046,7 -7047,7 +7047,7 @@@ static void gen8_set_l3sqc_credits(stru
  
  static void kabylake_init_clock_gating(struct drm_device *dev)
  {
 -      struct drm_i915_private *dev_priv = to_i915(dev);
 +      struct drm_i915_private *dev_priv = dev->dev_private;
  
        gen9_init_clock_gating(dev);
  
@@@ -7067,7 -7068,7 +7068,7 @@@
  
  static void skylake_init_clock_gating(struct drm_device *dev)
  {
 -      struct drm_i915_private *dev_priv = to_i915(dev);
 +      struct drm_i915_private *dev_priv = dev->dev_private;
  
        gen9_init_clock_gating(dev);