]> git.karo-electronics.de Git - linux-beck.git/commitdiff
sh: Track the CPU family in sh_cpuinfo.
authorPaul Mundt <lethal@linux-sh.org>
Sat, 15 Aug 2009 01:48:13 +0000 (10:48 +0900)
committerPaul Mundt <lethal@linux-sh.org>
Sat, 15 Aug 2009 01:48:13 +0000 (10:48 +0900)
This adds a family member to struct sh_cpuinfo, which allows us to fall
back more on the probe routines to work out what sort of subtype we are
running on. This will be used by the CPU cache initialization code in
order to first do family-level initialization, followed by subtype-level
optimizations.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
arch/sh/include/asm/bugs.h
arch/sh/include/asm/processor.h
arch/sh/kernel/cpu/sh2/probe.c
arch/sh/kernel/cpu/sh2a/probe.c
arch/sh/kernel/cpu/sh3/probe.c
arch/sh/kernel/cpu/sh4/probe.c
arch/sh/kernel/cpu/sh5/probe.c
arch/sh/kernel/setup.c

index 4924ff6f543948138ef835f400eb282780e3093d..46260fcbdf4bab4208bb871b89b355e73c31b49b 100644 (file)
@@ -21,25 +21,25 @@ static void __init check_bugs(void)
 
        current_cpu_data.loops_per_jiffy = loops_per_jiffy;
 
-       switch (current_cpu_data.type) {
-       case CPU_SH7619:
+       switch (current_cpu_data.family) {
+       case CPU_FAMILY_SH2:
                *p++ = '2';
                break;
-       case CPU_SH7201 ... CPU_MXG:
+       case CPU_FAMILY_SH2A:
                *p++ = '2';
                *p++ = 'a';
                break;
-       case CPU_SH7705 ... CPU_SH7729:
+       case CPU_FAMILY_SH3:
                *p++ = '3';
                break;
-       case CPU_SH7750 ... CPU_SH4_501:
+       case CPU_FAMILY_SH4:
                *p++ = '4';
                break;
-       case CPU_SH7763 ... CPU_SHX3:
+       case CPU_FAMILY_SH4A:
                *p++ = '4';
                *p++ = 'a';
                break;
-       case CPU_SH7343 ... CPU_SH7366:
+       case CPU_FAMILY_SH4AL_DSP:
                *p++ = '4';
                *p++ = 'a';
                *p++ = 'l';
@@ -48,15 +48,15 @@ static void __init check_bugs(void)
                *p++ = 's';
                *p++ = 'p';
                break;
-       case CPU_SH5_101 ... CPU_SH5_103:
+       case CPU_FAMILY_SH5:
                *p++ = '6';
                *p++ = '4';
                break;
-       case CPU_SH_NONE:
+       case CPU_FAMILY_UNKNOWN:
                /*
-                * Specifically use CPU_SH_NONE rather than default:,
-                * so we're able to have the compiler whine about
-                * unhandled enumerations.
+                * Specifically use CPU_FAMILY_UNKNOWN rather than
+                * default:, so we're able to have the compiler whine
+                * about unhandled enumerations.
                 */
                break;
        }
index ff7daaf9a620216ee41ddc0ce1487b1d4af127b3..db1a4f3a755f16cffade058969a5c06e07ec4518 100644 (file)
@@ -44,6 +44,17 @@ enum cpu_type {
        CPU_SH_NONE
 };
 
+enum cpu_family {
+       CPU_FAMILY_SH2,
+       CPU_FAMILY_SH2A,
+       CPU_FAMILY_SH3,
+       CPU_FAMILY_SH4,
+       CPU_FAMILY_SH4A,
+       CPU_FAMILY_SH4AL_DSP,
+       CPU_FAMILY_SH5,
+       CPU_FAMILY_UNKNOWN,
+};
+
 /*
  * TLB information structure
  *
@@ -61,7 +72,7 @@ struct tlb_info {
 };
 
 struct sh_cpuinfo {
-       unsigned int type;
+       unsigned int type, family;
        int cut_major, cut_minor;
        unsigned long loops_per_jiffy;
        unsigned long asid_cache;
index 5916d9096b9935c7bbf946c4a3a6efdb9b015e9b..1db6d88838888a3ba2435d46498b099efdcec792 100644 (file)
@@ -29,6 +29,7 @@ int __init detect_cpu_and_cache_system(void)
         */
        boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
        boot_cpu_data.icache = boot_cpu_data.dcache;
+       boot_cpu_data.family = CPU_FAMILY_SH2;
 
        return 0;
 }
index e098e2f6aa087bd43b88c72f147464413c6fb497..6825d6507164a271024c5614dd8510fbe8053ac3 100644 (file)
@@ -15,6 +15,8 @@
 
 int __init detect_cpu_and_cache_system(void)
 {
+       boot_cpu_data.family                    = CPU_FAMILY_SH2A;
+
        /* All SH-2A CPUs have support for 16 and 32-bit opcodes.. */
        boot_cpu_data.flags                     |= CPU_HAS_OP32;
 
index 10f2a760c5ee07ae6c2d71503070bea664733602..f9c7df64eb010ed7dc5e80b26d2ee635e41cd56c 100644 (file)
@@ -107,5 +107,7 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
        boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
        boot_cpu_data.icache = boot_cpu_data.dcache;
 
+       boot_cpu_data.family = CPU_FAMILY_SH3;
+
        return 0;
 }
index 6c78d0a9c857ba2e8e8fef19f3ae89ff6e670209..1148607c36bf5622d44f14cebbd5684939bb3533 100644 (file)
@@ -57,8 +57,12 @@ int __init detect_cpu_and_cache_system(void)
         * Setup some generic flags we can probe on SH-4A parts
         */
        if (((pvr >> 16) & 0xff) == 0x10) {
-               if ((cvr & 0x10000000) == 0)
+               boot_cpu_data.family = CPU_FAMILY_SH4A;
+
+               if ((cvr & 0x10000000) == 0) {
                        boot_cpu_data.flags |= CPU_HAS_DSP;
+                       boot_cpu_data.family = CPU_FAMILY_SH4AL_DSP;
+               }
 
                boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER;
                boot_cpu_data.cut_major = pvr & 0x7f;
@@ -68,6 +72,7 @@ int __init detect_cpu_and_cache_system(void)
        } else {
                /* And some SH-4 defaults.. */
                boot_cpu_data.flags |= CPU_HAS_PTEA;
+               boot_cpu_data.family = CPU_FAMILY_SH4;
        }
 
        /* FPU detection works for everyone */
@@ -174,7 +179,7 @@ int __init detect_cpu_and_cache_system(void)
 
                break;
        default:
-               boot_cpu_data.type = CPU_SH_NONE;
+               boot_cpu_data.type = boot_cpu_data.family = CPU_SH_NONE;
                break;
        }
 
index 92ad844b5c1220a349944f474d881767715aab1a..521d05b3f7ba1d528acda149330fe6e3818f1280 100644 (file)
@@ -34,6 +34,8 @@ int __init detect_cpu_and_cache_system(void)
                /* CPU.VCR aliased at CIR address on SH5-101 */
                boot_cpu_data.type = CPU_SH5_101;
 
+       boot_cpu_data.family = CPU_FAMILY_SH5;
+
        /*
         * First, setup some sane values for the I-cache.
         */
index ceb409bf7741433bf5fd2c720a39ed0613eb4686..dc403e42bcabfc3bbb89b33e8b559dc7f6e932f2 100644 (file)
@@ -49,6 +49,7 @@
 struct sh_cpuinfo cpu_data[NR_CPUS] __read_mostly = {
        [0] = {
                .type                   = CPU_SH_NONE,
+               .family                 = CPU_FAMILY_UNKNOWN,
                .loops_per_jiffy        = 10000000,
        },
 };