ARM: dts: APQ8064: Add iommu

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Srinivas Kandagatla [updated with latest generic IOMMU changes from Sricharan]

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index da1132116ca6e50bd0a04c94d6c6dd373827daf5..3813b1bf0682ac460ca7726432b8d83c42345303 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -874,6 +874,12 @@
                            <&mmcc GFX3D_AXI_CLK>,
                            <&mmcc MMSS_IMEM_AHB_CLK>;
                        qcom,chipid = <0x03020002>;
+
+                        iommus = <&gfx3d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+                                  &gfx3d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+                                  &gfx3d1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
+                                  &gfx3d1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
+
                        qcom,gpu-pwrlevels {
                                compatible = "qcom,gpu-pwrlevels";
                                qcom,gpu-pwrlevel@0 {
@@ -907,6 +913,73 @@
                            <&mmcc HDMI_TV_CLK>,
                            <&mmcc MDP_TV_CLK>,
                            <&mmcc MDP_AXI_CLK>;
+
+                       iommus = <&mdp_port0 0 2
+                                 &mdp_port1 0 2>;
+               };
+
+               mdp_port0: qcom,iommu@7500000 {
+                       compatible = "qcom,iommu-v0";
+                       #iommu-cells = <2>;
+                       clock-names =
+                           "smmu_pclk",
+                           "iommu_clk";
+                       clocks =
+                           <&mmcc SMMU_AHB_CLK>,
+                           <&mmcc MDP_AXI_CLK>;
+                       reg = <0x07500000 0x100000>;
+                       interrupts =
+                           <GIC_SPI 63 0>,
+                           <GIC_SPI 64 0>;
+                       ncb = <2>;
+               };
+
+               mdp_port1: qcom,iommu@7600000 {
+                       compatible = "qcom,iommu";
+                       #iommu-cells = <2>;
+                       clock-names =
+                           "smmu_pclk",
+                           "iommu_clk";
+                       clocks =
+                           <&mmcc SMMU_AHB_CLK>,
+                           <&mmcc MDP_AXI_CLK>;
+                       reg = <0x07600000 0x100000>;
+                       interrupts =
+                           <GIC_SPI 61 0>,
+                           <GIC_SPI 62 0>;
+                       ncb = <2>;
+               };
+
+               gfx3d: qcom,iommu@7c00000 {
+                       compatible = "qcom,iommu-v0";
+                       #iommu-cells = <16>;
+                       clock-names =
+                           "smmu_pclk",
+                           "iommu_clk";
+                       clocks =
+                           <&mmcc SMMU_AHB_CLK>,
+                           <&mmcc GFX3D_AXI_CLK>;
+                       reg = <0x07c00000 0x100000>;
+                       interrupts =
+                           <GIC_SPI 69 0>,
+                           <GIC_SPI 70 0>;
+                       ncb = <3>;
+               };
+
+               gfx3d1: qcom,iommu@7d00000 {
+                       compatible = "qcom,iommu-v0";
+                       #iommu-cells = <16>;
+                       clock-names =
+                           "smmu_pclk",
+                           "iommu_clk";
+                       clocks =
+                           <&mmcc SMMU_AHB_CLK>,
+                           <&mmcc GFX3D_AXI_CLK>;
+                       reg = <0x07d00000 0x100000>;
+                       interrupts =
+                           <GIC_SPI 210 0>,
+                           <GIC_SPI 211 0>;
+                       ncb = <3>;
                };
        };
 };