]> git.karo-electronics.de Git - mv-sheeva.git/commitdiff
OMAP clock: make the fixed divisor clock code available for all OMAPs
authorPaul Walmsley <paul@pwsan.com>
Wed, 27 Jan 2010 03:12:57 +0000 (20:12 -0700)
committerPaul Walmsley <paul@pwsan.com>
Wed, 27 Jan 2010 03:12:57 +0000 (20:12 -0700)
One of the OMAP1 clocks can use the fixed divisor recalculation code
introduced in the OMAP2 clock code, so rename the
omap2_fixed_divisor_recalc() function to omap_fixed_divisor_recalc()
and make it available to all OMAPs.  A followup patch converts the OMAP1
clock.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
arch/arm/mach-omap2/clock.c
arch/arm/mach-omap2/clock.h
arch/arm/mach-omap2/clock2xxx_data.c
arch/arm/mach-omap2/clock34xx_data.c
arch/arm/plat-omap/clock.c
arch/arm/plat-omap/include/plat/clock.h

index 759c72a48f7f188c5232919df2702edaabf562cd..7565f8e40a0e8d18b2f492e09420570f563d8117 100644 (file)
@@ -300,17 +300,6 @@ u32 omap2_get_dpll_rate(struct clk *clk)
        return dpll_clk;
 }
 
-/*
- * Used for clocks that have the same value as the parent clock,
- * divided by some factor
- */
-unsigned long omap2_fixed_divisor_recalc(struct clk *clk)
-{
-       WARN_ON(!clk->fixed_div);
-
-       return clk->parent->rate / clk->fixed_div;
-}
-
 /**
  * omap2_clk_dflt_find_companion - find companion clock to @clk
  * @clk: struct clk * to find the companion clock of
index 93c48df3b5b1f864587e23474731ed9f4399c5fb..0d70dc09370b8a2ef371af9c07f9e92809909a59 100644 (file)
@@ -78,7 +78,6 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
                                u32 *new_div);
 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val);
 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div);
-unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 u32 omap2_get_dpll_rate(struct clk *clk);
index 97dc7cf7751d6248e7491134fe54841a44aba377..402115fa9c124e549187a19e8c356512be4a51d1 100644 (file)
@@ -261,7 +261,7 @@ static struct clk func_12m_ck = {
        .parent         = &func_48m_ck,
        .fixed_div      = 4,
        .clkdm_name     = "wkup_clkdm",
-       .recalc         = &omap2_fixed_divisor_recalc,
+       .recalc         = &omap_fixed_divisor_recalc,
 };
 
 /* Secure timer, only available in secure mode */
@@ -557,7 +557,7 @@ static struct clk iva1_mpu_int_ifck = {
        .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
        .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
        .fixed_div      = 2,
-       .recalc         = &omap2_fixed_divisor_recalc,
+       .recalc         = &omap_fixed_divisor_recalc,
 };
 
 /*
index cbb421a45763fcfac4625322a344a8975b7e47ae..9e7f68a8fca22f5f7de494de424283fa4a60564a 100644 (file)
@@ -735,7 +735,7 @@ static struct clk omap_12m_fck = {
        .ops            = &clkops_null,
        .parent         = &omap_48m_fck,
        .fixed_div      = 4,
-       .recalc         = &omap2_fixed_divisor_recalc,
+       .recalc         = &omap_fixed_divisor_recalc,
 };
 
 /* This virstual clock is the source for dpll4_m4x2_ck */
@@ -1588,7 +1588,7 @@ static struct clk ssi_sst_fck_3430es1 = {
        .ops            = &clkops_null,
        .parent         = &ssi_ssr_fck_3430es1,
        .fixed_div      = 2,
-       .recalc         = &omap2_fixed_divisor_recalc,
+       .recalc         = &omap_fixed_divisor_recalc,
 };
 
 static struct clk ssi_sst_fck_3430es2 = {
@@ -1596,7 +1596,7 @@ static struct clk ssi_sst_fck_3430es2 = {
        .ops            = &clkops_null,
        .parent         = &ssi_ssr_fck_3430es2,
        .fixed_div      = 2,
-       .recalc         = &omap2_fixed_divisor_recalc,
+       .recalc         = &omap_fixed_divisor_recalc,
 };
 
 
index d9f8c844c385fa18f7b92aa88431296df9f75140..e0f72f48b8b191245b6e399f8a8e86377c1557ce 100644 (file)
@@ -199,6 +199,17 @@ unsigned long followparent_recalc(struct clk *clk)
        return clk->parent->rate;
 }
 
+/*
+ * Used for clocks that have the same value as the parent clock,
+ * divided by some factor
+ */
+unsigned long omap_fixed_divisor_recalc(struct clk *clk)
+{
+       WARN_ON(!clk->fixed_div);
+
+       return clk->parent->rate / clk->fixed_div;
+}
+
 void clk_reparent(struct clk *child, struct clk *parent)
 {
        list_del_init(&child->sibling);
index 94fe2a0ce40a8502f6cf2a2006717300d1818163..896cedc923a7f1c51aeabc96bfc4dab5412e5742 100644 (file)
@@ -88,9 +88,9 @@ struct clk {
        void                    (*init)(struct clk *);
        __u8                    enable_bit;
        __s8                    usecount;
+       u8                      fixed_div;
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
                defined(CONFIG_ARCH_OMAP4)
-       u8                      fixed_div;
        void __iomem            *clksel_reg;
        u32                     clksel_mask;
        const struct clksel     *clksel;
@@ -134,6 +134,7 @@ extern void propagate_rate(struct clk *clk);
 extern void recalculate_root_clocks(void);
 extern unsigned long followparent_recalc(struct clk *clk);
 extern void clk_enable_init_clocks(void);
+unsigned long omap_fixed_divisor_recalc(struct clk *clk);
 #ifdef CONFIG_CPU_FREQ
 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);