__INIT_CLK_DEBUG(caam_ipg_clk)
.id = 2,
.enable_reg = MXC_CCM_CCGR0,
- .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
+ .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
.enable = _clk_enable,
.disable = _clk_disable,
.parent = &mmdc_ch0_axi_clk[0],
clk_debug_register(lookups[i].clk);
}
- /* Lower the ipg_perclk frequency to 6MHz. */
- clk_set_rate(&ipg_perclk, 6000000);
+ /* Lower the ipg_perclk frequency to 22MHz.
+ * I2C needs a minimum of 12.8MHz as its source
+ * to acheive 400KHz speed. IPG_PERCLK sources
+ * I2C. 22MHz when divided by the I2C divider gives the
+ * freq closest to 400KHz.
+ */
+ clk_set_rate(&ipg_perclk, 22000000);
/* Timer needs to be initialized first as the
* the WAIT routines use GPT counter as
* should be from OSC24M */
clk_set_parent(&ipg_perclk, &osc_clk);
- /* Need to set IPG_PERCLK to 3MHz, so that we can
- * satisfy the 2.5:1 AHB:IPG_PERCLK ratio. Since AHB
- * can be dropped to as low as 8MHz in low power mode.
+
+ /*IPG_PERCLK sources I2C.
+ * I2C needs a minimum of 12.8MHz as its source
+ * to acheive 400KHz speed.
+ * Hence set ipg_perclk to 24MHz.
*/
- clk_set_rate(&ipg_perclk, 3000000);
+
+ clk_set_rate(&ipg_perclk, 24000000);
gpt_clk[0].parent = &ipg_perclk;
gpt_clk[0].get_rate = NULL;