<entry>Event data for event V4L2_EVENT_CTRL.
</entry>
</row>
+ <row>
+ <entry></entry>
+ <entry>&v4l2-event-frame-sync;</entry>
+ <entry><structfield>frame</structfield></entry>
+ <entry>Event data for event V4L2_EVENT_FRAME_SYNC.</entry>
+ </row>
<row>
<entry></entry>
<entry>__u8</entry>
</tgroup>
</table>
+ <table frame="none" pgwide="1" id="v4l2-event-frame-sync">
+ <title>struct <structname>v4l2_event_frame_sync</structname></title>
+ <tgroup cols="3">
+ &cs-str;
+ <tbody valign="top">
+ <row>
+ <entry>__u32</entry>
+ <entry><structfield>frame_sequence</structfield></entry>
+ <entry>
+ The sequence number of the frame being received.
+ </entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </table>
+
<table pgwide="1" frame="none" id="changes-flags">
<title>Changes</title>
<tgroup cols="3">
field of the oldest event.</para>
</entry>
</row>
+ <row>
+ <entry><constant>V4L2_EVENT_FRAME_SYNC</constant></entry>
+ <entry>4</entry>
+ <entry>
+ <para>Triggered immediately when the reception of a
+ frame has begun. This event has a
+ &v4l2-event-frame-sync; associated with it.</para>
+
+ <para>If the hardware needs to be stopped in the case of a
+ buffer underrun it might not be able to generate this event.
+ In such cases the <structfield>frame_sequence</structfield>
+ field in &v4l2-event-frame-sync; will not be incremented. This
+ causes two consecutive frame sequence numbers to have n times
+ frame interval in between them.</para>
+ </entry>
+ </row>
<row>
<entry><constant>V4L2_EVENT_PRIVATE_START</constant></entry>
<entry>0x08000000</entry>
#define V4L2_EVENT_VSYNC 1
#define V4L2_EVENT_EOS 2
#define V4L2_EVENT_CTRL 3
+#define V4L2_EVENT_FRAME_SYNC 4
#define V4L2_EVENT_PRIVATE_START 0x08000000
/* Payload for V4L2_EVENT_VSYNC */
__s32 default_value;
};
+struct v4l2_event_frame_sync {
+ __u32 frame_sequence;
+};
+
struct v4l2_event {
__u32 type;
union {
- struct v4l2_event_vsync vsync;
- struct v4l2_event_ctrl ctrl;
- __u8 data[64];
+ struct v4l2_event_vsync vsync;
+ struct v4l2_event_ctrl ctrl;
+ struct v4l2_event_frame_sync frame_sync;
+ __u8 data[64];
} u;
__u32 pending;
__u32 sequence;