The offset of output clock prescaler and divider were swapped, so reverse them.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <b42378@freescale.com>
(cherry picked from commit
4cda1ac12a8fdef84082212fb8fc5590c6c22fe7)
#define AOCDB 21 /* Output Clock Prescaler B Offset */
#define AICPC 0 /* Input Clock Divider C Offset */
#define AICDC 3 /* Input Clock Prescaler C Offset */
-#define AOCDC 6 /* Output Clock Prescaler C Offset */
-#define AOCPC 9 /* Output Clock Divider C Offset */
+#define AOCPC 6 /* Output Clock Prescaler C Offset */
+#define AOCDC 9 /* Output Clock Divider C Offset */
char *asrc_pair_id[] = {
[0] = "ASRC RX PAIR A",