]> git.karo-electronics.de Git - linux-beck.git/commitdiff
ARM: shmobile: r8a7790: Add PCIEC clock device tree node
authorPhil Edworthy <phil.edworthy@renesas.com>
Fri, 13 Jun 2014 09:37:15 +0000 (10:37 +0100)
committerSimon Horman <horms+renesas@verge.net.au>
Tue, 17 Jun 2014 10:58:28 +0000 (19:58 +0900)
This patch adds the device tree clock node for the PCIe Controller

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7790.dtsi
include/dt-bindings/clock/r8a7790-clock.h

index 29907c9d8e5b4caefe5611907cdec029d6d44e9e..9df57122e9c05d74948a2026b2e933e2bcb3eac2 100644 (file)
                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
                        clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
                                 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
-                                <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
+                                <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
                                R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
                                R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
-                               R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
+                               R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
                        >;
                        clock-output-names =
                                "iic2", "tpu0", "mmcif1", "sdhi3",
                                "sdhi2", "sdhi1", "sdhi0", "mmcif0",
-                               "iic0", "iic1", "ssusb", "cmt1";
+                               "iic0", "pciec", "iic1", "ssusb", "cmt1";
                };
                mstp5_clks: mstp5_clks@e6150144 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
index a16df68ac97d45df0f5c61c519ad74f27671b79a..f929a79e69987fd44a0d8bb8c2f91b40ccb3f4f2 100644 (file)
@@ -59,6 +59,7 @@
 #define R8A7790_CLK_SDHI0              14
 #define R8A7790_CLK_MMCIF0             15
 #define R8A7790_CLK_IIC0               18
+#define R8A7790_CLK_PCIEC              19
 #define R8A7790_CLK_IIC1               23
 #define R8A7790_CLK_SSUSB              28
 #define R8A7790_CLK_CMT1               29