MIPS: Lantiq: Change ltq_request_gpio() call signature

ltq_request_gpio() was using alt0/1 to multiplex the function of GPIO pins.
This was XWAY specific. In order to also accomodate SoCs that require more
bits we use a 32bit mask instead. This way the call signature is consistent
between XWAY and FALC-ON.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3252/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
index 001bf2e75dad9585fff7f5364e83c566ca423337..b6e0a3601c480c2aa8cbc59470d8388e1499ddc8 100644 (file)
--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
@@ -157,8 +157,8 @@ static inline void ltq_cgu_w32_mask(u32 c, u32 s, u32 r)
 }
 
 /* request a non-gpio and set the PIO config */
-extern int  ltq_gpio_request(unsigned int pin, unsigned int alt0,
-       unsigned int alt1, unsigned int dir, const char *name);
+extern int  ltq_gpio_request(unsigned int pin, unsigned int mux,
+                               unsigned int dir, const char *name);
 extern void ltq_pmu_enable(unsigned int module);
 extern void ltq_pmu_disable(unsigned int module);
 extern void ltq_cgu_enable(unsigned int clk);

diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
index d2fa98f3c78d8185d6bfec384b88e23720829b88..f204f6cdbd6a620f13ce4b56f0f8ca81d4d7b1e9 100644 (file)
--- a/arch/mips/lantiq/xway/gpio.c
+++ b/arch/mips/lantiq/xway/gpio.c
@@ -48,8 +48,8 @@ int irq_to_gpio(unsigned int gpio)
 }
 EXPORT_SYMBOL(irq_to_gpio);
 
-int ltq_gpio_request(unsigned int pin, unsigned int alt0,
-       unsigned int alt1, unsigned int dir, const char *name)
+int ltq_gpio_request(unsigned int pin, unsigned int mux,
+                       unsigned int dir, const char *name)
 {
        int id = 0;
 
@@ -67,13 +67,13 @@ int ltq_gpio_request(unsigned int pin, unsigned int alt0,
                pin -= PINS_PER_PORT;
                id++;
        }
-       if (alt0)
+       if (mux & 0x2)
                ltq_gpio_setbit(ltq_gpio_port[id].membase,
                        LTQ_GPIO_ALTSEL0, pin);
        else
                ltq_gpio_clearbit(ltq_gpio_port[id].membase,
                        LTQ_GPIO_ALTSEL0, pin);
-       if (alt1)
+       if (mux & 0x1)
                ltq_gpio_setbit(ltq_gpio_port[id].membase,
                        LTQ_GPIO_ALTSEL1, pin);
        else

diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
index ff9991cddeaa8c3fd6e44048730b09b6d24efb1f..2c786605c345a47ae194bd16d4f997832b8edfe6 100644 (file)
--- a/arch/mips/lantiq/xway/gpio_stp.c
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -79,9 +79,9 @@ static struct gpio_chip ltq_stp_chip = {
 static int ltq_stp_hw_init(void)
 {
        /* the 3 pins used to control the external stp */
-       ltq_gpio_request(4, 1, 0, 1, "stp-st");
-       ltq_gpio_request(5, 1, 0, 1, "stp-d");
-       ltq_gpio_request(6, 1, 0, 1, "stp-sh");
+       ltq_gpio_request(4, 2, 1, "stp-st");
+       ltq_gpio_request(5, 2, 1, "stp-d");
+       ltq_gpio_request(6, 2, 1, "stp-sh");
 
        /* sane defaults */
        ltq_stp_w32(0, LTQ_STP_AR);

diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index 030c77e7926e5395111913da53ef884e5ac64899..0496f8f0f8f3f9428487f8a24c5527fe16e66a28 100644 (file)
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -69,29 +69,28 @@
 #define ltq_pci_cfg_r32(x)     ltq_r32(ltq_pci_mapped_cfg + (x))
 
 struct ltq_pci_gpio_map {
-       int pin;
-       int alt0;
-       int alt1;
-       int dir;
+       unsigned int pin;
+       unsigned int mux;
+       unsigned char dir;
        char *name;
 };
 
 /* the pci core can make use of the following gpios */
 static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
-       { 0, 1, 0, 0, "pci-exin0" },
-       { 1, 1, 0, 0, "pci-exin1" },
-       { 2, 1, 0, 0, "pci-exin2" },
-       { 39, 1, 0, 0, "pci-exin3" },
-       { 10, 1, 0, 0, "pci-exin4" },
-       { 9, 1, 0, 0, "pci-exin5" },
-       { 30, 1, 0, 1, "pci-gnt1" },
-       { 23, 1, 0, 1, "pci-gnt2" },
-       { 19, 1, 0, 1, "pci-gnt3" },
-       { 38, 1, 0, 1, "pci-gnt4" },
-       { 29, 1, 0, 0, "pci-req1" },
-       { 31, 1, 0, 0, "pci-req2" },
-       { 3, 1, 0, 0, "pci-req3" },
-       { 37, 1, 0, 0, "pci-req4" },
+       { .pin = 0, .mux = 2, .dir = 0, .name = "pci-exin0" },
+       { .pin = 1, .mux = 2, .dir = 0, .name = "pci-exin1" },
+       { .pin = 2, .mux = 2, .dir = 0, .name = "pci-exin2" },
+       { .pin = 39, .mux = 2, .dir = 0, .name = "pci-exin3" },
+       { .pin = 10, .mux = 2, .dir = 0, .name = "pci-exin4" },
+       { .pin = 9, .mux = 2, .dir = 0, .name = "pci-exin5" },
+       { .pin = 30, .mux = 2, .dir = 1, .name = "pci-gnt1" },
+       { .pin = 23, .mux = 2, .dir = 1, .name = "pci-gnt2" },
+       { .pin = 19, .mux = 2, .dir = 1, .name = "pci-gnt3" },
+       { .pin = 38, .mux = 2, .dir = 1, .name = "pci-gnt4" },
+       { .pin = 29, .mux = 2, .dir = 0, .name = "pci-req1" },
+       { .pin = 31, .mux = 2, .dir = 0, .name = "pci-req2" },
+       { .pin = 3, .mux = 2, .dir = 0, .name = "pci-req3" },
+       { .pin = 37, .mux = 2, .dir = 0, .name = "pci-req4" },
 };
 
 __iomem void *ltq_pci_mapped_cfg;
@@ -157,13 +156,12 @@ static void ltq_pci_setup_gpio(int gpio)
        for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
                if (gpio & (1 << i)) {
                        ltq_gpio_request(ltq_pci_gpio_map[i].pin,
-                               ltq_pci_gpio_map[i].alt0,
-                               ltq_pci_gpio_map[i].alt1,
+                               ltq_pci_gpio_map[i].mux,
                                ltq_pci_gpio_map[i].dir,
                                ltq_pci_gpio_map[i].name);
                }
        }
-       ltq_gpio_request(21, 0, 0, 1, "pci-reset");
+       ltq_gpio_request(21, 0, 1, "pci-reset");
        ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
 }