powerpc: Replaced tlbilx with tlbwe in the initialization code

On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor
state can execute TLB management instructions. If EPCR[DGTMI]=0
tlbwe and tlbilx are allowed to execute normally in the guest state.

A hypervisor may choose to virtualize TLB1 and for this purpose it
may use IPROT to protect the entries for being invalidated by the
guest. However, because tlbwe and tlbilx execution in the guest state
are sharing the same bit, it is not possible to have a scenario where
tlbwe is allowed to be executed in guest state and tlbilx traps. When
guest TLB management instructions are allowed to be executed in guest
state the guest cannot use tlbilx to invalidate TLB1 guest entries.

Linux is using tlbilx in the boot code to invalidate the temporary
entries it creates when initializing the MMU. The patch is replacing
the usage of tlbilx in initialization code with tlbwe with VALID bit
cleared.

Linux is also using tlbilx in other contexts (like huge pages or
indirect entries) but removing the tlbilx from the initialization code
offers the possibility to have scenarios under hypervisor which are
not using huge pages or indirect entries.

Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>

diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 4d5a0b1034e8647348a08a9eb652051e6e1e7c93..063b65dd4f27a256106d34da4fda70c17859752f 100644 (file)
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -1068,12 +1068,9 @@ skpinv:  addi    r6,r6,1                         /* Increment */
        mtspr   SPRN_MAS0,r3
        tlbre
        mfspr   r6,SPRN_MAS1
-       rlwinm  r6,r6,0,2,0     /* clear IPROT */
+       rlwinm  r6,r6,0,2,31    /* clear IPROT and VALID */
        mtspr   SPRN_MAS1,r6
        tlbwe
-
-       /* Invalidate TLB1 */
-       PPC_TLBILX_ALL(0,R0)
        sync
        isync
 
@@ -1127,12 +1124,9 @@ skpinv:  addi    r6,r6,1                         /* Increment */
        mtspr   SPRN_MAS0,r4
        tlbre
        mfspr   r5,SPRN_MAS1
-       rlwinm  r5,r5,0,2,0     /* clear IPROT */
+       rlwinm  r5,r5,0,2,31    /* clear IPROT and VALID */
        mtspr   SPRN_MAS1,r5
        tlbwe
-
-       /* Invalidate TLB1 */
-       PPC_TLBILX_ALL(0,R0)
        sync
        isync