clk: gxbb: expose MPLL2 clock for use by DT

This exposes the MPLL2 clock as this is one of the input clocks of the
ethernet controller's internal mux.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>

diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index ae461b16af75cc0a1dd8618b9ecd9fa2e767f163..a05b5f62e5804f9db9db8033f72f8ab7d4a5bc3c 100644 (file)
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -183,7 +183,7 @@
 /* CLKID_CLK81 */
 #define CLKID_MPLL0              13
 #define CLKID_MPLL1              14
-#define CLKID_MPLL2              15
+/* CLKID_MPLL2 */
 #define CLKID_DDR                16
 #define CLKID_DOS                17
 #define CLKID_ISA                18

diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index ce4ad637083da9dba0928268abbc6a26ddbeb4cb..ccef0283173b5a47b3dee9dceec4394cf1db39ed 100644 (file)
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -11,6 +11,7 @@
 #define CLKID_FCLK_DIV3                5
 #define CLKID_FCLK_DIV4                6
 #define CLKID_CLK81            12
+#define CLKID_MPLL2            15
 #define CLKID_ETH              36
 #define CLKID_SD_EMMC_A                94
 #define CLKID_SD_EMMC_B                95