/* struct drm_i915_master_private *master_priv; */
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
- struct psb_intel_mode_device *mode_dev = psb_intel_crtc->mode_dev;
int pipe = psb_intel_crtc->pipe;
- unsigned long Start, Offset;
+ unsigned long start, offset;
/* FIXME: check if we need this surely MRST is pipe 0 only */
int dspbase = (pipe == 0 ? DSPALINOFF : DSPBBASE);
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
if (!gma_power_begin(dev, true))
return 0;
- Start = mode_dev->bo_offset(dev, psbfb);
- Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
+ start = psbfb->gtt->offset;
+ offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
REG_WRITE(dspstride, crtc->fb->pitch);
}
REG_WRITE(dspcntr_reg, dspcntr);
- DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
+ DRM_DEBUG("Writing base %08lX %08lX %d %d\n", start, offset, x, y);
if (0 /* FIXMEAC - check what PSB needs */) {
- REG_WRITE(dspbase, Offset);
+ REG_WRITE(dspbase, offset);
REG_READ(dspbase);
- REG_WRITE(dspsurf, Start);
+ REG_WRITE(dspsurf, start);
REG_READ(dspsurf);
} else {
- REG_WRITE(dspbase, Start + Offset);
+ REG_WRITE(dspbase, start + offset);
REG_READ(dspbase);
}
if (!fb)
return;
- offset = psbfb->offset;
+ offset = psbfb->gtt->offset;
stride = fb->pitch;
switch (fb->depth) {
if (!fb)
return;
- offset = psbfb->offset;
+ offset = psbfb->gtt->offset;
stride = fb->pitch;
switch (fb->depth) {
u32 subpicture_disable_mask;
};
-struct psb_gtt_mapping_arg {
- void *hKernelMemInfo;
- u32 offset_pages;
-};
-
-struct drm_psb_getpageaddrs_arg {
- u32 handle;
- unsigned long *page_addrs;
- unsigned long gtt_offset;
-};
-
/* Controlling the kernel modesetting buffers */
#define DRM_PSB_KMS_OFF 0x00
psb_fb = to_psb_fb(drm_fb);
if (gma_power_begin(dev, 0)) {
- REG_WRITE(DSPASURF, psb_fb->offset);
+ REG_WRITE(DSPASURF, psb_fb->gtt->offset);
REG_READ(DSPASURF);
gma_power_end(dev);
} else {
- dev_priv->saveDSPASURF = psb_fb->offset;
+ dev_priv->saveDSPASURF = psb_fb->gtt->offset;
}
return 0;
/*Append new drm mode definition here, align with libdrm definition*/
#define DRM_MODE_SCALE_NO_SCALE 2
-extern struct ttm_bo_driver psb_ttm_bo_driver;
-
enum {
CHIP_PSB_8108 = 0,
CHIP_PSB_8109 = 1,
static struct drm_framebuffer *psb_framebuffer_create
(struct drm_device *dev, struct drm_mode_fb_cmd *r,
- void *mm_private)
+ struct gtt_range *gt)
{
struct psb_framebuffer *fb;
int ret;
drm_helper_mode_fill_fb_struct(&fb->base, r);
- fb->mem = mm_private;
+ fb->gtt = gt;
return &fb->base;
goto out_err1;
}
psbfb = to_psb_fb(fb);
- psbfb->size = size;
info = framebuffer_alloc(sizeof(struct psb_fbdev), device);
if (!info) {
if (fbdev->psb_fb_helper.fbdev) {
info = fbdev->psb_fb_helper.fbdev;
- psb_gtt_free_range(dev, psbfb->mem);
+ psb_gtt_free_range(dev, psbfb->gtt);
unregister_framebuffer(info);
iounmap(info->screen_base);
framebuffer_release(info);
unsigned int *handle)
{
struct psb_framebuffer *psbfb = to_psb_fb(fb);
- struct gtt_range *r = psbfb->mem;
+ struct gtt_range *r = psbfb->gtt;
return drm_gem_handle_create(file_priv, &r->gem, handle);
}
{
struct drm_device *dev = fb->dev;
struct psb_framebuffer *psbfb = to_psb_fb(fb);
- struct gtt_range *r = psbfb->mem;
+ struct gtt_range *r = psbfb->gtt;
if (psbfb->fbdev)
psbfb_remove(dev, fb);
}
}
-/* FIXME: rewrite this in terms of the gtt_range and GEM objects
- rather than faking them as we do now */
-
-static size_t psb_bo_offset(struct drm_device *dev, void *obj)
-{
- struct psb_framebuffer *psbfb
- = (struct psb_framebuffer *)obj;
-
- return (size_t)psbfb->offset;
-}
-
void psb_modeset_init(struct drm_device *dev)
{
struct drm_psb_private *dev_priv =
int i;
PSB_DEBUG_ENTRY("\n");
- /* Init mm functions */
- mode_dev->bo_offset = psb_bo_offset;
drm_mode_config_init(dev);
struct drm_framebuffer base;
struct address_space *addr_space;
struct fb_info *fbdev;
- struct gtt_range *mem;
- void * hKernelMemInfo;
- uint32_t size;
- uint32_t offset;
+ struct gtt_range *gtt;
};
struct psb_fbdev {
struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
struct psb_intel_mode_device *mode_dev = psb_intel_crtc->mode_dev;
int pipe = psb_intel_crtc->pipe;
- unsigned long Start, Offset;
+ unsigned long start, offset;
int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
if (!gma_power_begin(dev, true))
return 0;
- Start = mode_dev->bo_offset(dev, psbfb);
- Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
+ start = psbfb->gtt->offset;
+ offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
REG_WRITE(dspstride, crtc->fb->pitch);
}
REG_WRITE(dspcntr_reg, dspcntr);
- DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
+ DRM_DEBUG("Writing base %08lX %08lX %d %d\n", start, offset, x, y);
if (0 /* FIXMEAC - check what PSB needs */) {
- REG_WRITE(dspbase, Offset);
+ REG_WRITE(dspbase, offset);
REG_READ(dspbase);
- REG_WRITE(dspsurf, Start);
+ REG_WRITE(dspsurf, start);
REG_READ(dspsurf);
} else {
- REG_WRITE(dspbase, Start + Offset);
+ REG_WRITE(dspbase, start + offset);
REG_READ(dspbase);
}