]> git.karo-electronics.de Git - karo-tx-linux.git/commitdiff
ENGR00141558-8 ARM: add gpmi device for mx508
authorHuang Shijie <b32955@freescale.com>
Tue, 26 Apr 2011 08:27:29 +0000 (16:27 +0800)
committerOliver Wendt <ow@karo-electronics.de>
Mon, 30 Sep 2013 12:09:04 +0000 (14:09 +0200)
add the gpmi device for mx508.

Signed-off-by: Huang Shijie <b32955@freescale.com>
arch/arm/mach-mx5/board-mx50_rdp.c
arch/arm/mach-mx5/clock_mx50.c
arch/arm/mach-mx5/devices-imx50.h
arch/arm/plat-mxc/devices/Kconfig
arch/arm/plat-mxc/devices/Makefile
arch/arm/plat-mxc/devices/platform-imx-gpmi-nfc.c [new file with mode: 0644]
arch/arm/plat-mxc/include/mach/devices-common.h

index 5cac95aae1fe456007286bece53e6804408bfa61..bbaeef79029d7988b0e915f38e91138ad0ba44e5 100755 (executable)
@@ -207,6 +207,42 @@ static const struct spi_imx_master mx50_rdp_spi_pdata __initconst = {
        .num_chipselect = ARRAY_SIZE(mx50_rdp_spi_cs),
 };
 
+/* The GPMI is conflicted with SD3, so init this in the driver. */
+static iomux_v3_cfg_t mx50_gpmi_nand[] __initdata = {
+       MX50_PIN_EIM_DA8__NANDF_CLE,
+       MX50_PIN_EIM_DA9__NANDF_ALE,
+       MX50_PIN_EIM_DA10__NANDF_CE0,
+       MX50_PIN_EIM_DA11__NANDF_CE1,
+       MX50_PIN_EIM_DA12__NANDF_CE2,
+       MX50_PIN_EIM_DA13__NANDF_CE3,
+       MX50_PAD_EIM_DA14__NANDF_READY,
+       MX50_PIN_EIM_DA15__NANDF_DQS,
+       MX50_PIN_SD3_D4__NANDF_D0,
+       MX50_PIN_SD3_D5__NANDF_D1,
+       MX50_PIN_SD3_D6__NANDF_D2,
+       MX50_PIN_SD3_D7__NANDF_D3,
+       MX50_PIN_SD3_D0__NANDF_D4,
+       MX50_PIN_SD3_D1__NANDF_D5,
+       MX50_PIN_SD3_D2__NANDF_D6,
+       MX50_PIN_SD3_D3__NANDF_D7,
+       MX50_PIN_SD3_CLK__NANDF_RDN,
+       MX50_PIN_SD3_CMD__NANDF_WRN,
+       MX50_PIN_SD3_WP__NANDF_RESETN,
+};
+
+static int gpmi_nfc_platform_init(void)
+{
+       return mxc_iomux_v3_setup_multiple_pads(mx50_gpmi_nand,
+                                       ARRAY_SIZE(mx50_gpmi_nand));
+}
+
+static struct gpmi_nfc_platform_data  mx50_gpmi_nfc_platform_data __initdata = {
+       .platform_init           = gpmi_nfc_platform_init,
+       .min_prop_delay_in_ns    = 5,
+       .max_prop_delay_in_ns    = 9,
+       .max_chip_count          = 1,
+};
+
 /*
  * Board specific initialization.
  */
@@ -228,6 +264,7 @@ static void __init mx50_rdp_board_init(void)
        imx50_add_srtc();
        mx50_rdp_fec_reset();
        imx50_add_fec(&fec_data);
+       imx50_add_gpmi(&mx50_gpmi_nfc_platform_data);
        imx50_add_imx_i2c(0, &i2c_data);
        imx50_add_imx_i2c(1, &i2c_data);
        imx50_add_imx_i2c(2, &i2c_data);
index 670a6ccde3c08a91641a720ad27e8a2c7e1b5509..48f9de5520790846fd8e0f92431f7463b5d996cd 100755 (executable)
@@ -3324,7 +3324,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("fec.0", NULL, fec_clk[0]),
        _REGISTER_CLOCK(NULL, "fec_sec1_clk", fec_clk[1]),
        _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk),
-       _REGISTER_CLOCK(NULL, "gpmi-nfc", gpmi_nfc_clk[0]),
+       _REGISTER_CLOCK("imx50-gpmi-nfc.0", NULL, gpmi_nfc_clk[0]),
        _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nfc_clk[1]),
        _REGISTER_CLOCK(NULL, "bch", gpmi_nfc_clk[2]),
        _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nfc_clk[3]),
index fdce2832258f1f943496bdb1aa9b66c54bd24462..18c9609e5789ecf734e495778929819ea68d3f80 100755 (executable)
@@ -57,6 +57,8 @@ extern const struct imx_rngb_data imx50_rngb_data __initconst;
 extern const struct imx_perfmon_data imx50_perfmon_data __initconst;
 #define imx50_add_perfmon() \
        imx_add_perfmon(&imx50_perfmon_data);
+#define imx50_add_gpmi(platform_data)  imx_add_gpmi(platform_data);
+
 extern const struct imx_perfmon_data imx50_perfmon_data __initconst;
 #define imx50_add_perfmon() \
        imx_add_perfmon(&imx50_perfmon_data);
index f2ee8a5be730ed61a57a63c10eb2be4c18e01332..d3b1350037f4074770d09a168a22024fdcff0a35 100755 (executable)
@@ -13,6 +13,9 @@ config IMX_HAVE_PLATFORM_GPIO_KEYS
        bool
        default y if SOC_IMX51
 
+config IMX_HAVE_PLATFORM_GPMI_NFC
+       bool
+
 config IMX_HAVE_PLATFORM_IMX21_HCD
        bool
 
index 76baca67c0f28c44cb20d2d3e50067565ec1506a..e3dd8d8b75da6f40f9b08475319fde7c48b17020 100755 (executable)
@@ -2,6 +2,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_GPMI_NFC) += platform-imx-gpmi-nfc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
diff --git a/arch/arm/plat-mxc/devices/platform-imx-gpmi-nfc.c b/arch/arm/plat-mxc/devices/platform-imx-gpmi-nfc.c
new file mode 100644 (file)
index 0000000..0d5ffeb
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <asm/sizes.h>
+#include <mach/hardware.h>
+#include <mach/gpmi-nfc.h>
+#include <mach/devices-common.h>
+
+#ifdef CONFIG_SOC_IMX50
+struct platform_device *__init
+imx_add_gpmi(const struct gpmi_nfc_platform_data *platform_data)
+{
+       struct resource res[] = {
+       { /* GPMI */
+                .name  = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
+                .flags = IORESOURCE_MEM,
+                .start = MX50_GPMI_BASE_ADDR,
+                .end   = MX50_GPMI_BASE_ADDR + SZ_8K - 1,
+       }, {
+                .name  = GPMI_NFC_GPMI_INTERRUPT_RES_NAME,
+                .flags = IORESOURCE_IRQ,
+                .start = MX50_INT_RAWNAND_GPMI,
+                .end   = MX50_INT_RAWNAND_GPMI,
+       }, { /* BCH */
+                .name  = GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
+                .flags = IORESOURCE_MEM,
+                .start = MX50_BCH_BASE_ADDR,
+                .end   = MX50_BCH_BASE_ADDR + SZ_8K - 1,
+       }, {
+                .name  = GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+                .flags = IORESOURCE_IRQ,
+                .start = MX50_INT_RAWNAND_BCH,
+                .end   = MX50_INT_RAWNAND_BCH,
+       }, { /* DMA */
+                .name  = GPMI_NFC_DMA_CHANNELS_RES_NAME,
+                .flags = IORESOURCE_DMA,
+                .start = MX50_DMA_CHANNEL_AHB_APBH_GPMI0,
+                .end   = MX50_DMA_CHANNEL_AHB_APBH_GPMI7,
+       }, {
+                .name  = GPMI_NFC_DMA_INTERRUPT_RES_NAME,
+                .flags = IORESOURCE_IRQ,
+                .start = MX50_INT_APBHDMA_CHAN0,
+                .end   = MX50_INT_APBHDMA_CHAN7,
+       }, };
+
+       return imx_add_platform_device_dmamask("imx50-gpmi-nfc", 0,
+                       res, ARRAY_SIZE(res), platform_data,
+                       sizeof(*platform_data), DMA_BIT_MASK(32));
+}
+#endif /* ifdef CONFIG_SOC_IMX50 */
index 6c28bc59a91519b1621e78a3f412bca4c3e6dcbd..56f26ac3a45c66bc4579ecbe4a8b1aae42ab39a2 100755 (executable)
@@ -424,6 +424,11 @@ struct imx_dcp_data {
 struct platform_device *__init imx_add_dcp(
                const struct imx_dcp_data *data);
 
+/* gpmi-nfc */
+#include <mach/gpmi-nfc.h>
+struct platform_device *__init imx_add_gpmi(
+               const struct gpmi_nfc_platform_data *data);
+
 struct imx_rngb_data {
        resource_size_t iobase;
        resource_size_t irq;