clk: tegra: dpaux and dpaux1 are fixed factor clocks

The dpaux (on Tegra124 and Tegra210) and dpaux1 (on Tegra210) are fixed
factor clocks (1:17) and derived from pll_p_out0 (pll_p). They also have
a gate bit in the peripheral clock registers.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index c716b2885207fe610412ec7aa1e33f14f65b3423..29d04c663abfbbb3eabad5e07c29d578354d8934 100644 (file)
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -821,8 +821,6 @@ static struct tegra_periph_init_data gate_clks[] = {
        GATE("ispb", "clk_m", 3, 0, tegra_clk_ispb, 0),
        GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
        GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
-       GATE("dpaux", "pll_p", 181, 0, tegra_clk_dpaux, 0),
-       GATE("dpaux1", "pll_p", 207, 0, tegra_clk_dpaux1, 0),
        GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
        GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
        GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index 1627258292d238ad038c7e4f30ac2305bd4fb257..f4fbbf16a056fe6d394782fbc37d1de49509f4ad 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1155,6 +1155,10 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
                                        1, 2);
        clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
 
+       clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
+                                             1, 17, 181);
+       clks[TEGRA124_CLK_DPAUX] = clk;
+
        clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
                                clk_base + PLLD_MISC, 30, 0, &pll_d_lock);
        clks[TEGRA124_CLK_PLL_D_DSI_OUT] = clk;

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 4f72d1a4347ba059bb80ee43e9d4f86007444011..8133f92361fcc1a951bc6cc009128775aa897ae5 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2462,6 +2462,14 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base,
                                        1, 2);
        clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
 
+       clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
+                                             1, 17, 181);
+       clks[TEGRA210_CLK_DPAUX] = clk;
+
+       clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base,
+                                             1, 17, 207);
+       clks[TEGRA210_CLK_DPAUX1] = clk;
+
        /* pll_d_dsi_out */
        clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0,
                                clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);