ARM: OMAP3: clock: use clk_features flags for omap3 DPLL4 checks

DPLL4 can't be reprogrammed on OMAP3430 ES1.0 due to hardware limitation.
Currently, the code does runtime omap_rev() check to see the chip it is
being executed on, instead, change this to use clk_features flags.
This avoids need for runtime omap_rev() checks.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>

diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 500530d1364a384859a6720c783ef1394545b983..c2b239857cc470b9176e6dff369b7b9376795091 100644 (file)
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -771,4 +771,8 @@ void __init ti_clk_init_features(void)
                ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
        else if (cpu_is_omap34xx())
                ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
+
+       /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
+       if (omap_rev() == OMAP3430_REV_ES1_0)
+               ti_clk_features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
 }

diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 4592a2762592fef88c69be32aa1ce42cc6f18a4a..641337c6cde9a43fdfb24e589b9946464924ec01 100644 (file)
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -234,6 +234,7 @@ struct ti_clk_features {
 };
 
 #define TI_CLK_DPLL_HAS_FREQSEL                (1 << 0)
+#define TI_CLK_DPLL4_DENY_REPROGRAM    (1 << 1)
 
 extern struct ti_clk_features ti_clk_features;
 

diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 0b02b4161d71f9806fd10acea364d3dbfe005505..9a2560181909c93e05842f01723699a5aba7024a 100644 (file)
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -46,7 +46,7 @@ int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
         * on 3430ES1 prevents us from changing DPLL multipliers or dividers
         * on DPLL4.
         */
-       if (omap_rev() == OMAP3430_REV_ES1_0) {
+       if (ti_clk_features.flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
                pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
                return -EINVAL;
        }