const void *tx;
void *rx;
u8 *tmp_buf;
- int count;
struct davinci_spi_dma *dma_channels;
struct davinci_spi_platform_data *pdata;
/* convert len to words based on bits_per_word */
conv = davinci_spi->bytes_per_word[spi->chip_select];
- davinci_spi->count = t->len / conv;
-
data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
INIT_COMPLETION(davinci_spi->done);
/* Enable SPI */
set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
- count = davinci_spi->count;
+ count = t->len / conv;
/* Determine the command to execute READ or WRITE */
if (t->tx_buf) {
} else { /* Receive in Interrupt mode */
int i;
- for (i = 0; i < davinci_spi->count; i++) {
+ for (i = 0; i < count; i++) {
set_io_bits(davinci_spi->base + SPIINT,
SPIINT_BITERR_INTR
| SPIINT_OVRRUN_INTR
/* convert len to words based on bits_per_word */
data_type = davinci_spi->bytes_per_word[spi->chip_select];
- davinci_spi->count = t->len / data_type;
data1_reg_val = ioread32(davinci_spi->base + SPIDAT1);
if (ret)
return ret;
- count = davinci_spi->count; /* the number of elements */
+ count = t->len / data_type; /* the number of elements */
/* disable all interrupts for dma transfers */
clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);