MIPS: math-emu: Don't needlessly pass a struct around.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/branch.h b/arch/mips/include/asm/branch.h
index de781cf54bc7a22b4ae81f506ff1a869c6b1cc32..0171ffc80eb01e51bd58ec8ecf2e71e2696cee36 100644 (file)
--- a/arch/mips/include/asm/branch.h
+++ b/arch/mips/include/asm/branch.h
@@ -28,10 +28,10 @@ extern int __MIPS16e_compute_return_epc(struct pt_regs *regs);
 #define MM_MIPS32_COND_FC      0x30
 
 extern int __mm_isBranchInstr(struct pt_regs *regs,
-       struct mm_decoded_insn dec_insn, unsigned long *contpc);
+       const struct mm_decoded_insn * const dec_insn, unsigned long *contpc);
 
 static inline int mm_isBranchInstr(struct pt_regs *regs,
-       struct mm_decoded_insn dec_insn, unsigned long *contpc)
+       const struct mm_decoded_insn * const dec_insn, unsigned long *contpc)
 {
        if (!cpu_has_mmips)
                return 0;

diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 84888d9332b921b46c059abceb415ff7f0b0aea2..8af8b7769e597ddc13722363d5c266b70691fa64 100644 (file)
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -51,10 +51,10 @@ int __isa_exception_epc(struct pt_regs *regs)
 /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
 static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
 
-int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
-                      unsigned long *contpc)
+int __mm_isBranchInstr(struct pt_regs *regs,
+       const struct mm_decoded_insn * const dec_insn, unsigned long *contpc)
 {
-       union mips_instruction insn = (union mips_instruction)dec_insn.insn;
+       union mips_instruction insn = (union mips_instruction)dec_insn->insn;
        int bc_false = 0;
        unsigned int fcr31;
        unsigned int bit;
@@ -75,8 +75,8 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                                if (insn.mm_i_format.rt != 0)   /* Not mm_jr */
                                        regs->regs[insn.mm_i_format.rt] =
                                                regs->cp0_epc +
-                                               dec_insn.pc_inc +
-                                               dec_insn.next_pc_inc;
+                                               dec_insn->pc_inc +
+                                               dec_insn->next_pc_inc;
                                *contpc = regs->regs[insn.mm_i_format.rs];
                                return 1;
                        }
@@ -87,54 +87,54 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                case mm_bltzals_op:
                case mm_bltzal_op:
                        regs->regs[31] = regs->cp0_epc +
-                               dec_insn.pc_inc +
-                               dec_insn.next_pc_inc;
+                               dec_insn->pc_inc +
+                               dec_insn->next_pc_inc;
                        /* Fall through */
                case mm_bltz_op:
                        if ((long)regs->regs[insn.mm_i_format.rs] < 0)
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
+                                       dec_insn->pc_inc +
                                        (insn.mm_i_format.simmediate << 1);
                        else
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
-                                       dec_insn.next_pc_inc;
+                                       dec_insn->pc_inc +
+                                       dec_insn->next_pc_inc;
                        return 1;
                case mm_bgezals_op:
                case mm_bgezal_op:
                        regs->regs[31] = regs->cp0_epc +
-                                       dec_insn.pc_inc +
-                                       dec_insn.next_pc_inc;
+                                       dec_insn->pc_inc +
+                                       dec_insn->next_pc_inc;
                        /* Fall through */
                case mm_bgez_op:
                        if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
+                                       dec_insn->pc_inc +
                                        (insn.mm_i_format.simmediate << 1);
                        else
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
-                                       dec_insn.next_pc_inc;
+                                       dec_insn->pc_inc +
+                                       dec_insn->next_pc_inc;
                        return 1;
                case mm_blez_op:
                        if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
+                                       dec_insn->pc_inc +
                                        (insn.mm_i_format.simmediate << 1);
                        else
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
-                                       dec_insn.next_pc_inc;
+                                       dec_insn->pc_inc +
+                                       dec_insn->next_pc_inc;
                        return 1;
                case mm_bgtz_op:
                        if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
+                                       dec_insn->pc_inc +
                                        (insn.mm_i_format.simmediate << 1);
                        else
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
-                                       dec_insn.next_pc_inc;
+                                       dec_insn->pc_inc +
+                                       dec_insn->next_pc_inc;
                        return 1;
                case mm_bc2f_op:
                case mm_bc1f_op:
@@ -157,11 +157,11 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                        bit += 23;
                        if (fcr31 & (1 << bit))
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
+                                       dec_insn->pc_inc +
                                        (insn.mm_i_format.simmediate << 1);
                        else
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc + dec_insn.next_pc_inc;
+                                       dec_insn->pc_inc + dec_insn->next_pc_inc;
                        return 1;
                }
                break;
@@ -170,7 +170,7 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                case mm_jalr16_op:
                case mm_jalrs16_op:
                        regs->regs[31] = regs->cp0_epc +
-                               dec_insn.pc_inc + dec_insn.next_pc_inc;
+                               dec_insn->pc_inc + dec_insn->next_pc_inc;
                        /* Fall through */
                case mm_jr16_op:
                        *contpc = regs->regs[insn.mm_i_format.rs];
@@ -180,50 +180,50 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
        case mm_beqz16_op:
                if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
+                               dec_insn->pc_inc +
                                (insn.mm_b1_format.simmediate << 1);
                else
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc + dec_insn.next_pc_inc;
+                               dec_insn->pc_inc + dec_insn->next_pc_inc;
                return 1;
        case mm_bnez16_op:
                if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
+                               dec_insn->pc_inc +
                                (insn.mm_b1_format.simmediate << 1);
                else
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc + dec_insn.next_pc_inc;
+                               dec_insn->pc_inc + dec_insn->next_pc_inc;
                return 1;
        case mm_b16_op:
-               *contpc = regs->cp0_epc + dec_insn.pc_inc +
+               *contpc = regs->cp0_epc + dec_insn->pc_inc +
                         (insn.mm_b0_format.simmediate << 1);
                return 1;
        case mm_beq32_op:
                if (regs->regs[insn.mm_i_format.rs] ==
                    regs->regs[insn.mm_i_format.rt])
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
+                               dec_insn->pc_inc +
                                (insn.mm_i_format.simmediate << 1);
                else
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
-                               dec_insn.next_pc_inc;
+                               dec_insn->pc_inc +
+                               dec_insn->next_pc_inc;
                return 1;
        case mm_bne32_op:
                if (regs->regs[insn.mm_i_format.rs] !=
                    regs->regs[insn.mm_i_format.rt])
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
+                               dec_insn->pc_inc +
                                (insn.mm_i_format.simmediate << 1);
                else
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc + dec_insn.next_pc_inc;
+                               dec_insn->pc_inc + dec_insn->next_pc_inc;
                return 1;
        case mm_jalx32_op:
                regs->regs[31] = regs->cp0_epc +
-                       dec_insn.pc_inc + dec_insn.next_pc_inc;
-               *contpc = regs->cp0_epc + dec_insn.pc_inc;
+                       dec_insn->pc_inc + dec_insn->next_pc_inc;
+               *contpc = regs->cp0_epc + dec_insn->pc_inc;
                *contpc >>= 28;
                *contpc <<= 28;
                *contpc |= (insn.j_format.target << 2);
@@ -231,10 +231,10 @@ int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
        case mm_jals32_op:
        case mm_jal32_op:
                regs->regs[31] = regs->cp0_epc +
-                       dec_insn.pc_inc + dec_insn.next_pc_inc;
+                       dec_insn->pc_inc + dec_insn->next_pc_inc;
                /* Fall through */
        case mm_j32_op:
-               *contpc = regs->cp0_epc + dec_insn.pc_inc;
+               *contpc = regs->cp0_epc + dec_insn->pc_inc;
                *contpc >>= 27;
                *contpc <<= 27;
                *contpc |= (insn.j_format.target << 1);
@@ -291,7 +291,7 @@ int __microMIPS_compute_return_epc(struct pt_regs *regs)
        }
        mminsn.next_insn = word;
 
-       mm_isBranchInstr(regs, mminsn, &contpc);
+       mm_isBranchInstr(regs, &mminsn, &contpc);
 
        regs->cp0_epc = contpc;
 

diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 2b3517214d6d8cbdbe6a7bbc31187e1abcc893a5..27ceff224805a1dfe174afe91d2499f6955c3c27 100644 (file)
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -825,7 +825,7 @@ static void emulate_load_store_microMIPS(struct pt_regs *regs,
        mminsn.next_insn = word;
 
        insn = (union mips_instruction)(mminsn.insn);
-       if (mm_isBranchInstr(regs, mminsn, &contpc))
+       if (mm_isBranchInstr(regs, &mminsn, &contpc))
                insn = (union mips_instruction)(mminsn.next_insn);
 
        /*  Parse instruction to find what to do */

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 9609d5b3f548deca22e5dae0120dbf8e61d0318f..4d784dc393cf26fc81794e47683f95b6d3f5af88 100644 (file)
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -85,10 +85,10 @@ static const unsigned int fpucondbit[8] = {
  * a single subroutine should be used across both
  * modules.
  */
-static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
-                        unsigned long *contpc)
+static int isBranchInstr(struct pt_regs *regs,
+       const struct mm_decoded_insn * const dec_insn, unsigned long *contpc)
 {
-       union mips_instruction insn = (union mips_instruction)dec_insn.insn;
+       union mips_instruction insn = (union mips_instruction)dec_insn->insn;
        unsigned int fcr31;
        unsigned int bit = 0;
 
@@ -97,8 +97,8 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                switch (insn.r_format.func) {
                case jalr_op:
                        regs->regs[insn.r_format.rd] =
-                               regs->cp0_epc + dec_insn.pc_inc +
-                               dec_insn.next_pc_inc;
+                               regs->cp0_epc + dec_insn->pc_inc +
+                               dec_insn->next_pc_inc;
                        /* Fall through */
                case jr_op:
                        *contpc = regs->regs[insn.r_format.rs];
@@ -110,36 +110,36 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                case bltzal_op:
                case bltzall_op:
                        regs->regs[31] = regs->cp0_epc +
-                               dec_insn.pc_inc +
-                               dec_insn.next_pc_inc;
+                               dec_insn->pc_inc +
+                               dec_insn->next_pc_inc;
                        /* Fall through */
                case bltz_op:
                case bltzl_op:
                        if ((long)regs->regs[insn.i_format.rs] < 0)
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
+                                       dec_insn->pc_inc +
                                        (insn.i_format.simmediate << 2);
                        else
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
-                                       dec_insn.next_pc_inc;
+                                       dec_insn->pc_inc +
+                                       dec_insn->next_pc_inc;
                        return 1;
                case bgezal_op:
                case bgezall_op:
                        regs->regs[31] = regs->cp0_epc +
-                               dec_insn.pc_inc +
-                               dec_insn.next_pc_inc;
+                               dec_insn->pc_inc +
+                               dec_insn->next_pc_inc;
                        /* Fall through */
                case bgez_op:
                case bgezl_op:
                        if ((long)regs->regs[insn.i_format.rs] >= 0)
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
+                                       dec_insn->pc_inc +
                                        (insn.i_format.simmediate << 2);
                        else
                                *contpc = regs->cp0_epc +
-                                       dec_insn.pc_inc +
-                                       dec_insn.next_pc_inc;
+                                       dec_insn->pc_inc +
+                                       dec_insn->next_pc_inc;
                        return 1;
                }
                break;
@@ -147,11 +147,11 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                set_isa16_mode(bit);
        case jal_op:
                regs->regs[31] = regs->cp0_epc +
-                       dec_insn.pc_inc +
-                       dec_insn.next_pc_inc;
+                       dec_insn->pc_inc +
+                       dec_insn->next_pc_inc;
                /* Fall through */
        case j_op:
-               *contpc = regs->cp0_epc + dec_insn.pc_inc;
+               *contpc = regs->cp0_epc + dec_insn->pc_inc;
                *contpc >>= 28;
                *contpc <<= 28;
                *contpc |= (insn.j_format.target << 2);
@@ -163,46 +163,46 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                if (regs->regs[insn.i_format.rs] ==
                    regs->regs[insn.i_format.rt])
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
+                               dec_insn->pc_inc +
                                (insn.i_format.simmediate << 2);
                else
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
-                               dec_insn.next_pc_inc;
+                               dec_insn->pc_inc +
+                               dec_insn->next_pc_inc;
                return 1;
        case bne_op:
        case bnel_op:
                if (regs->regs[insn.i_format.rs] !=
                    regs->regs[insn.i_format.rt])
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
+                               dec_insn->pc_inc +
                                (insn.i_format.simmediate << 2);
                else
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
-                               dec_insn.next_pc_inc;
+                               dec_insn->pc_inc +
+                               dec_insn->next_pc_inc;
                return 1;
        case blez_op:
        case blezl_op:
                if ((long)regs->regs[insn.i_format.rs] <= 0)
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
+                               dec_insn->pc_inc +
                                (insn.i_format.simmediate << 2);
                else
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
-                               dec_insn.next_pc_inc;
+                               dec_insn->pc_inc +
+                               dec_insn->next_pc_inc;
                return 1;
        case bgtz_op:
        case bgtzl_op:
                if ((long)regs->regs[insn.i_format.rs] > 0)
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
+                               dec_insn->pc_inc +
                                (insn.i_format.simmediate << 2);
                else
                        *contpc = regs->cp0_epc +
-                               dec_insn.pc_inc +
-                               dec_insn.next_pc_inc;
+                               dec_insn->pc_inc +
+                               dec_insn->next_pc_inc;
                return 1;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
        case lwc2_op: /* This is bbit0 on Octeon */
@@ -250,23 +250,23 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                        case 2: /* bc1fl */
                                if (~fcr31 & (1 << bit))
                                        *contpc = regs->cp0_epc +
-                                               dec_insn.pc_inc +
+                                               dec_insn->pc_inc +
                                                (insn.i_format.simmediate << 2);
                                else
                                        *contpc = regs->cp0_epc +
-                                               dec_insn.pc_inc +
-                                               dec_insn.next_pc_inc;
+                                               dec_insn->pc_inc +
+                                               dec_insn->next_pc_inc;
                                return 1;
                        case 1: /* bc1t */
                        case 3: /* bc1tl */
                                if (fcr31 & (1 << bit))
                                        *contpc = regs->cp0_epc +
-                                               dec_insn.pc_inc +
+                                               dec_insn->pc_inc +
                                                (insn.i_format.simmediate << 2);
                                else
                                        *contpc = regs->cp0_epc +
-                                               dec_insn.pc_inc +
-                                               dec_insn.next_pc_inc;
+                                               dec_insn->pc_inc +
+                                               dec_insn->next_pc_inc;
                                return 1;
                        }
                }
@@ -365,10 +365,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
        /* XXX NEC Vr54xx bug workaround */
        if (delay_slot(xcp)) {
                if (dec_insn.micro_mips_mode) {
-                       if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
+                       if (!mm_isBranchInstr(xcp, &dec_insn, &contpc))
                                clear_delay_slot(xcp);
                } else {
-                       if (!isBranchInstr(xcp, dec_insn, &contpc))
+                       if (!isBranchInstr(xcp, &dec_insn, &contpc))
                                clear_delay_slot(xcp);
                }
        }