ARM: EXYNOS4: Add a alias for pdma clocks

PDMA controllers when instantiated from device tree are registered using
amba_device_register(). The registration process enables clock to the
controllers to read the peripheral id of the PDMA amba device.

In case of Exynos4, the clocks to the PDMA controllers are named as 'dma'
but amba_device_register() looks up the clock using the name 'apb_pclk'.
Hence, alias clocks with name 'apb_pclk' clock are created for clocks
with name 'dma'.

Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 9f50e334314a0a07db85745b431e2af22f5bacb5..2d6a4d4413ca265f015a44c3cf4c41804160c98c 100644 (file)
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -557,16 +557,6 @@ static struct clk init_clocks_off[] = {
                .parent         = &clk_aclk_133.clk,
                .enable         = exynos4_clk_ip_fsys_ctrl,
                .ctrlbit        = (1 << 10),
-       }, {
-               .name           = "dma",
-               .devname        = "dma-pl330.0",
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 0),
-       }, {
-               .name           = "dma",
-               .devname        = "dma-pl330.1",
-               .enable         = exynos4_clk_ip_fsys_ctrl,
-               .ctrlbit        = (1 << 1),
        }, {
                .name           = "adc",
                .enable         = exynos4_clk_ip_peril_ctrl,
@@ -783,6 +773,20 @@ static struct clk init_clocks[] = {
        }
 };
 
+static struct clk clk_pdma0 = {
+       .name           = "dma",
+       .devname        = "dma-pl330.0",
+       .enable         = exynos4_clk_ip_fsys_ctrl,
+       .ctrlbit        = (1 << 0),
+};
+
+static struct clk clk_pdma1 = {
+       .name           = "dma",
+       .devname        = "dma-pl330.1",
+       .enable         = exynos4_clk_ip_fsys_ctrl,
+       .ctrlbit        = (1 << 1),
+};
+
 struct clk *clkset_group_list[] = {
        [0] = &clk_ext_xtal_mux,
        [1] = &clk_xusbxti,
@@ -1284,6 +1288,11 @@ static struct clksrc_clk *sysclks[] = {
        &clk_mout_mfc1,
 };
 
+static struct clk *clk_cdev[] = {
+       &clk_pdma0,
+       &clk_pdma1,
+};
+
 static struct clksrc_clk *clksrc_cdev[] = {
        &clk_sclk_uart0,
        &clk_sclk_uart1,
@@ -1296,6 +1305,8 @@ static struct clk_lookup exynos4_clk_lookup[] = {
        CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
        CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
        CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
+       CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
+       CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
 };
 
 static int xtal_rate;
@@ -1511,6 +1522,10 @@ void __init exynos4_register_clocks(void)
        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
+       s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
+       for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
+               s3c_disable_clocks(clk_cdev[ptr], 1);
+
        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
        clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));