return d;
}
-static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write)
-{/* return input_f */
+/*static unsigned int f_calc(unsigned int pfs, unsigned int bpp, unsigned int *write)
+{[> return input_f <]
unsigned int f_calculated = 0;
switch (pfs) {
case IPU_PIX_FMT_YVU422P:
}
return m_calculated;
-}
+}*/
/* Stripe parameters calculator */
* wait for BG channel EOF then disable FG-IDMAC,
* it avoid FG NFB4EOF error.
*/
- if (channel == MEM_FG_SYNC) {
+ if ((channel == MEM_FG_SYNC) && (ipu_is_channel_busy(ipu, MEM_BG_SYNC))) {
int timeout = 50;
ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_BG_SYNC_EOF),
irq = in_dma;
if (irq == 0xffffffff) {
- dev_err(ipu->dev, "warning: no channel busy, break\n");
+ dev_dbg(ipu->dev, "warning: no channel busy, break\n");
break;
}
- dev_err(ipu->dev, "warning: channel %d busy, need wait\n", irq);
-
ipu_cm_write(ipu, IPUIRQ_2_MASK(irq),
IPUIRQ_2_STATREG(irq));
- while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq)) &
- IPUIRQ_2_MASK(irq)) == 0) {
+
+ dev_dbg(ipu->dev, "warning: channel %d busy, need wait\n", irq);
+
+ while (((ipu_cm_read(ipu, IPUIRQ_2_STATREG(irq))
+ & IPUIRQ_2_MASK(irq)) == 0) &&
+ (idma_is_set(ipu, IDMAC_CHA_BUSY, irq))) {
msleep(10);
timeout -= 10;
if (timeout <= 0) {
reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8;
ipu_cm_write(ipu, reg, IPU_SRM_PRI2);
- ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END),
- IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END));
- while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)) &
- IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) {
- msleep(2);
- timeout -= 2;
- if (timeout <= 0)
- break;
+ if (ipu_is_channel_busy(ipu, MEM_BG_SYNC)) {
+ ipu_cm_write(ipu, IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END),
+ IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END));
+ while ((ipu_cm_read(ipu, IPUIRQ_2_STATREG(IPU_IRQ_DP_SF_END)) &
+ IPUIRQ_2_MASK(IPU_IRQ_DP_SF_END)) == 0) {
+ msleep(2);
+ timeout -= 2;
+ if (timeout <= 0)
+ break;
+ }
}
return;
} else {