For the design which the phy is no power (no 5v for VBUS), the
PHY can't get dp/dm correctly, so it the port change interrpt
is enabled or the host enters low power mode, the unexpected
interrupt will occur.
This commit will make the dp/dm as zero at otg configuration.
For gadget-only, the same function is existed at probe.
For host-only, the vbus will be on before port change interrupt
is enabled.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
/*
- * Copyright (C) 2005-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
*
* Author: Li Yang <LeoLi@freescale.com>
* Jerry Huang <Chang-Ming.Huang@freescale.com>
if (otg_dev->fsm.id) {
otg_dev->host_first_call = true;
+ /* The discharge will be false when the controller
+ * is ready to use.
+ */
+ if (pdata->dr_discharge_line)
+ pdata->dr_discharge_line(true);
schedule_otg_work(&otg_dev->otg_event, 100);
}
else {