et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
®ister18);
et131x_mii_write(adapter, phydev->addr,
- PHY_MPHY_CONTROL_REG, register18 | 0x4);
+ PHY_MPHY_CONTROL_REG,
+ register18 | 0x4);
et131x_mii_write(adapter, phydev->addr, PHY_INDEX_REG,
register18 | 0x8402);
et131x_mii_write(adapter, phydev->addr, PHY_DATA_REG,
et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
®ister18);
et131x_mii_write(adapter, phydev->addr,
- PHY_MPHY_CONTROL_REG, register18 | 0x4);
+ PHY_MPHY_CONTROL_REG,
+ register18 | 0x4);
et131x_mii_write(adapter, phydev->addr,
PHY_INDEX_REG, register18 | 0x8402);
et131x_mii_write(adapter, phydev->addr,
*/
/* TRAP();*/
- dev_warn(&adapter->pdev->dev,
- "RxDMA_ERR interrupt, error %x\n",
+ dev_warn(&adapter->pdev->dev, "RxDMA_ERR interrupt, error %x\n",
readl(&iomem->txmac.tx_test));
}
* occur. In a nutshell, the whole Tx path will have to be reset
* and re-configured afterwards.
*/
- dev_warn(&adapter->pdev->dev,
- "TXMAC interrupt, error 0x%08x\n",
+ dev_warn(&adapter->pdev->dev, "TXMAC interrupt, error 0x%08x\n",
err);
/* If we are debugging, we want to see this error, otherwise we