ENGR00173869-3: i.mx6: add the cpu_is_mx6dl() support

In order to support one image for i.mx6q and i.mx6dl, we introduce
the below functions by diff the value reading from ANATOP ID register.
cpu_is_mx6q() and cpu_is_mx6dl()

The layout for the register defines:
               Major  Minor
i.MX6Q1.1:       6300     01
i.MX6Q1.0:       6300     00
i.MX6DL1.0:      6100     00

For the common bits shared across all i.mx6 ports, we can use:
cpu_is_mx6() for it.

Signed-off-by: Jason Liu <r64343@freescale.com>

diff --git a/arch/arm/mach-mx6/mm.c b/arch/arm/mach-mx6/mm.c
index fa1c78be532f47ed2876d6f2d380580496598b14..e4daaf1fb4155869a194586cbd2efa34e6b0d3fc 100644 (file)
--- a/arch/arm/mach-mx6/mm.c
+++ b/arch/arm/mach-mx6/mm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -57,6 +57,19 @@ static struct map_desc mx6_io_desc[] __initdata = {
        .type = MT_DEVICE},
 };
 
+static void mx6_set_cpu_type(void)
+{
+       u32 cpu_type = readl(IO_ADDRESS(ANATOP_BASE_ADDR + 0x260));
+
+       cpu_type >>= 16;
+       if (cpu_type == 0x63)
+               mxc_set_cpu_type(MXC_CPU_MX6Q);
+       else if (cpu_type == 0x61)
+               mxc_set_cpu_type(MXC_CPU_MX6DL);
+       else
+               pr_err("Unknown CPU type: %x\n", cpu_type);
+}
+
 /*!
  * This function initializes the memory map. It is called during the
  * system startup to create static physical to virtual memory map for
@@ -67,6 +80,7 @@ void __init mx6_map_io(void)
        iotable_init(mx6_io_desc, ARRAY_SIZE(mx6_io_desc));
        mxc_iomux_v3_init(IO_ADDRESS(MX6Q_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(IO_ADDRESS(MX6Q_WDOG1_BASE_ADDR));
+       mx6_set_cpu_type();
 }
 #ifdef CONFIG_CACHE_L2X0
 int mxc_init_l2x0(void)

diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 15a82a2a988ec6ffe8e0ef83a20c4848057143e4..c8f18052c6af3937dc16c5a6d94680cff27bd8d9 100755 (executable)
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
+ * Copyright 2004-2007, 2011-2012 Freescale Semiconductor, Inc.
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
  *
  * This program is free software; you can redistribute it and/or
@@ -36,6 +36,8 @@
 #define MXC_CPU_MX50           50
 #define MXC_CPU_MX51           51
 #define MXC_CPU_MX53           53
+#define MXC_CPU_MX6Q           63
+#define MXC_CPU_MX6DL          61
 
 #define IMX_CHIP_REVISION_1_0          0x10
 #define IMX_CHIP_REVISION_1_1          0x11
@@ -218,22 +220,20 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx53()         (0)
 #endif
 
-#ifndef __ASSEMBLY__
-
 #ifdef CONFIG_SOC_IMX6Q
-#define cpu_is_mx6q()          (1)
+#  define mxc_cpu_type __mxc_cpu_type
+# define cpu_is_mx6q()         (mxc_cpu_type == MXC_CPU_MX6Q)
+# define cpu_is_mx6dl()                (mxc_cpu_type == MXC_CPU_MX6DL)
+#else
+# define cpu_is_mx6q()         (0)
+# define cpu_is_mx6dl()                (0)
+#endif
 
 #ifndef __ASSEMBLY__
+#ifdef CONFIG_SOC_IMX6Q
 extern int mx6q_revision(void);
-#endif
-
 #else
-#define cpu_is_mx6q()          (0)
-
-#ifndef __ASSEMBLY__
-#define mx6q_revision(void)    (0)
-#endif
-
+#define mx6q_revision(void)    (0)
 #endif
 
 struct cpu_op {
@@ -274,6 +274,7 @@ extern int tzic_enable_wake(int is_idle);
 #define cpu_is_mx5()    (cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx50())
 #define cpu_is_mx3()   (cpu_is_mx31() || cpu_is_mx35())
 #define cpu_is_mx2()   (cpu_is_mx21() || cpu_is_mx27())
+#define cpu_is_mx6()   (cpu_is_mx6q() || cpu_is_mx6dl())
 
 #define MXC_PGCR_PCR           1
 #define MXC_SRPGCR_PCR         1