arm/tegra: Remove code that's ifndef CONFIG_ARM_GIC

entry-macro.S contains some stale code for chips before Tegra20 that
apparently didn't use an ARM GIC. All chips supported by mainline use
an ARM GIC, so rip out the stale code.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
index dd165c53889de61d499731f8e5b6da8fc88d5d55..485a11eeaceb6f469d5078e9775e2070a98d109a 100644 (file)
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -15,7 +15,6 @@
 #include <mach/iomap.h>
 #include <mach/io.h>
 
-#if defined(CONFIG_ARM_GIC)
 #define HAVE_GET_IRQNR_PREAMBLE
 #include <asm/hardware/entry-macro-gic.S>
 
@@ -32,25 +31,3 @@
 
        .macro  arch_ret_to_user, tmp1, tmp2
        .endm
-#else
-       /* legacy interrupt controller for AP16 */
-       .macro  disable_fiq
-       .endm
-
-       .macro  get_irqnr_preamble, base, tmp
-       @ enable imprecise aborts
-       cpsie   a
-       @ EVP base at 0xf010f000
-       mov \base, #0xf0000000
-       orr \base, #0x00100000
-       orr \base, #0x0000f000
-       .endm
-
-       .macro  arch_ret_to_user, tmp1, tmp2
-       .endm
-
-       .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-       ldr \irqnr, [\base, #0x20]      @ EVT_IRQ_STS
-       cmp \irqnr, #0x80
-       .endm
-#endif