ARM: dts: imx6qdl-sabrelite: move USDHC3 CD/WP to pinctrl_usdhc3

This patch moves pin SD3_DAT5/4 (CD/WP) from pinctrl_hog to pinctrl_usdhc3.
It also explicitly sets the pad SD3_DAT5 to 0x1b0b0, which is also the value
that it has before this patch if using mainline u-boot.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 8bb910b275b408f5d930892a055b2a82fcb92362..96c39024c17cf8136b56466480c9d91f704a303d 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -117,8 +117,6 @@
                                MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x80000000
                                MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x80000000
                                MX6QDL_PAD_EIM_D23__GPIO3_IO23  0x80000000
-                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
-                               MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
                                MX6QDL_PAD_GPIO_0__CCM_CLKO1    0x80000000
                        >;
                };
@@ -152,7 +150,11 @@
                };
 
                pinctrl_usdhc3: usdhc3grp {
-                       fsl,pins = <MX6QDL_USDHC3_PINGRP_D4>;
+                       fsl,pins = <
+                               MX6QDL_USDHC3_PINGRP_D4
+                               MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
+                               MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
+                       >;
                };
 
                pinctrl_usdhc4: usdhc4grp {