sata_clk[0].disable(&sata_clk[0]);
pcie_clk[0].disable(&pcie_clk[0]);
- /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
- clk_set_rate(&pll4_audio_main_clk, 650000000);
+ /* Initialize Audio and Video PLLs to valid frequency. */
+ clk_set_rate(&pll4_audio_main_clk, 176000000);
clk_set_rate(&pll5_video_main_clk, 650000000);
clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
clk_set_parent(&clko2_clk, &osc_clk);
clk_set_rate(&clko2_clk, 2400000);
- clk_set_parent(&clko_clk, &ipg_clk);
+ clk_set_parent(&clko_clk, &pll4_audio_main_clk);
/*
* FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample
* rate convertion and this clock frequency can not be too high, set