Merge branch 'clk-fixes' into clk-next

* clk-fixes:
  clk: mediatek: mt8173: Fix enabling of critical clocks
  drivers: clk: st: Fix mux bit-setting for Cortex A9 clocks
  drivers: clk: st: Add CLK_GET_RATE_NOCACHE flag to clocks
  drivers: clk: st: Fix flexgen lock init
  drivers: clk: st: Fix FSYN channel values
  drivers: clk: st: Remove unused code
  clk: qcom: Use parent rate when set rate to pixel RCG clock
  clk: at91: do not leak resources
  clk: stm32: Fix out-by-one error path in the index lookup
  clk: iproc: fix bit manipulation arithmetic
  clk: iproc: fix memory leak from clock name

diff --combined drivers/clk/at91/clk-pll.c
index cbbe40377ad622a7f9d38aca5651916dda549e54,23163be24b6f1adbded64f41b045470a8799edf1..18b60f4895a68477a74ebe99a8b64542bd7057c9
--- 1/drivers/clk/at91/clk-pll.c
--- 2/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@@ -173,7 -173,8 +173,7 @@@ static long clk_pll_get_best_div_mul(st
        int i = 0;
  
        /* Check if parent_rate is a valid input rate */
 -      if (parent_rate < characteristics->input.min ||
 -          parent_rate > characteristics->input.max)
 +      if (parent_rate < characteristics->input.min)
                return -ERANGE;
  
        /*
@@@ -186,15 -187,6 +186,15 @@@
        if (!mindiv)
                mindiv = 1;
  
 +      if (parent_rate > characteristics->input.max) {
 +              tmpdiv = DIV_ROUND_UP(parent_rate, characteristics->input.max);
 +              if (tmpdiv > PLL_DIV_MAX)
 +                      return -ERANGE;
 +
 +              if (tmpdiv > mindiv)
 +                      mindiv = tmpdiv;
 +      }
 +
        /*
         * Calculate the maximum divider which is limited by PLL register
         * layout (limited by the MUL or DIV field size).
@@@ -346,12 -338,16 +346,16 @@@ at91_clk_register_pll(struct at91_pmc *
        irq_set_status_flags(pll->irq, IRQ_NOAUTOEN);
        ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH,
                          id ? "clk-pllb" : "clk-plla", pll);
-       if (ret)
+       if (ret) {
+               kfree(pll);
                return ERR_PTR(ret);
+       }
  
        clk = clk_register(NULL, &pll->hw);
-       if (IS_ERR(clk))
+       if (IS_ERR(clk)) {
+               free_irq(pll->irq, pll);
                kfree(pll);
+       }
  
        return clk;
  }