ENGR00160874 Enable SSI audio support on the MX6

The MX6 Sabre-lite board uses the SGTL codec through
SSI to play audio. Add support for SSI audio on the MX6

Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>

diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig
index d9f6894688820728855a48d70c494f59a95ee77c..c1fdd01cc7ce3601abad6515eb6e480fc10755d0 100644 (file)
--- a/arch/arm/mach-mx6/Kconfig
+++ b/arch/arm/mach-mx6/Kconfig
@@ -4,6 +4,7 @@ config ARCH_MX6Q
        bool
        select USB_ARCH_HAS_EHCI
        select ARCH_MXC_IOMUX_V3
+       select ARCH_MXC_AUDMUX_V2
        select ARM_GIC
        select ARCH_HAS_CPUFREQ
        select IMX_HAVE_PLATFORM_IMX_UART

diff --git a/arch/arm/mach-mx6/devices-imx6q.h b/arch/arm/mach-mx6/devices-imx6q.h
index 98c94cbabf18d805f29997cd27a6517989f4dd61..dd83e095b6a707a3a493de2d998c72d57bbccb1c 100644 (file)
--- a/arch/arm/mach-mx6/devices-imx6q.h
+++ b/arch/arm/mach-mx6/devices-imx6q.h
@@ -88,6 +88,10 @@ extern const struct imx_ahci_data imx6q_ahci_data __initconst;
 #define imx6q_add_ahci(id, pdata)   \
        imx_add_ahci(&imx6q_ahci_data, pdata)
 
+extern const struct imx_imx_ssi_data imx6_imx_ssi_data[] __initconst;
+#define imx6q_add_imx_ssi(id, pdata)            \
+       imx_add_imx_ssi(&imx6_imx_ssi_data[id], pdata)
+
 extern const struct imx_ipuv3_data imx6q_ipuv3_data[] __initconst;
 #define imx6q_add_ipuv3(id, pdata)     imx_add_ipuv3(id, &imx6q_ipuv3_data[id], pdata)
 #define imx6q_add_ipuv3fb(id, pdata)   imx_add_ipuv3_fb(id, pdata)

diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
index 5467c3b913832ec676676370af24e195e74d289d..2ce504fed8bf1897803e99aafdb988c159e4663d 100755 (executable)
--- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
@@ -86,6 +86,16 @@ const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_SOC_IMX53 */
 
+#ifdef CONFIG_SOC_IMX6Q
+const struct imx_imx_ssi_data imx6_imx_ssi_data[] __initconst = {
+#define imx6q_imx_ssi_data_entry(_id, _hwid)                           \
+       imx_imx_ssi_data_entry(MX6Q, _id, _hwid, SZ_4K)
+       imx6q_imx_ssi_data_entry(0, 1),
+       imx6q_imx_ssi_data_entry(1, 2),
+       imx6q_imx_ssi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
 struct platform_device *__init imx_add_imx_ssi(
                const struct imx_imx_ssi_data *data,
                const struct imx_ssi_platform_data *pdata)

diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h
index 284c529f56c41a042ee7fc91ed16688a682d161f..d4e100df78a9646d9d35e929f69781044a50d39f 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx6.h
+++ b/arch/arm/plat-mxc/include/mach/mx6.h
@@ -138,9 +138,9 @@
 #define MX6Q_ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000) /* slot 6 */
 #define UART1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x20000) /* slot 8 */
 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000) /* slot 9 */
-#define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000) /* slot 10 */
-#define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000) /* slot 11 */
-#define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000) /* slot 12 */
+#define MX6Q_SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000) /* slot 10 */
+#define MX6Q_SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000) /* slot 11 */
+#define MX6Q_SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000) /* slot 12 */
 #define MX6Q_ASRC_BASE_ADDR        (ATZ1_BASE_ADDR + 0x34000) /* slot 13 */
 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000) /* slot 15 */
 #define MX6Q_VPU_BASE_ADDR          (ATZ1_BASE_ADDR + 0x40000) /* slot 33,
@@ -324,9 +324,9 @@
 #define MX6Q_INT_USB_OTG                               75
 #define MX6Q_INT_USB_PHY0                              76
 #define MX6Q_INT_USB_PHY1                              77
-#define MXC_INT_SSI1                               78
-#define MXC_INT_SSI2                               79
-#define MXC_INT_SSI3                               80
+#define MX6Q_INT_SSI1                               78
+#define MX6Q_INT_SSI2                               79
+#define MX6Q_INT_SSI3                               80
 #define MXC_INT_ANATOP_TEMPSNSR                    81
 #define MX6Q_INT_ASRC                               82
 #define MXC_INT_ESAI                              83