Modify devicetree to support LDO_BYPASS mode.
Signed-off-by: Robin Gong <b38343@freescale.com>
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
fsl,max_ddr_freq = <400000000>;
};
- gpu@00130000 {
+ gpu: gpu@00130000 {
compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
<0x0 0x0>;
"gpu3d_shader_clk";
resets = <&src 0>, <&src 3>;
reset-names = "gpu3d", "gpu2d";
+ pu-supply = <®_pu>;
};
ocram: sram@00900000 {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
fsl,max_ddr_freq = <528000000>;
};
- gpu@00130000 {
+ gpu: gpu@00130000 {
compatible = "fsl,imx6q-gpu";
reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
<0x02204000 0x4000>, <0x0 0x0>;
"gpu3d_clk", "gpu3d_shader_clk";
resets = <&src 0>, <&src 3>, <&src 3>;
reset-names = "gpu3d", "gpu2d", "gpuvg";
+ pu-supply = <®_pu>;
};
ocram: sram@00900000 {
status = "okay";
};
+&cpu0 {
+ arm-supply = <&sw1a_reg>;
+ soc-supply = <&sw1c_reg>;
+ pu-supply = <&pu_dummy>; /* use pu_dummy if VDDSOC share with VDDPU */
+};
+
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 9 0>;
fsl,cpu_pupscr_sw = <0xf>;
fsl,cpu_pdnscr_iso2sw = <0x1>;
fsl,cpu_pdnscr_iso = <0x1>;
+ fsl,ldo-bypass; /* use ldo-bypass, u-boot will check it and configure */
+ pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
+};
+
+&gpu {
+ pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
};
&hdmi_cec {
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
+ regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
wp-gpios = <&gpio2 1 0>;
status = "okay";
};
+
+&vpu {
+ pu-supply = <&pu_dummy>; /* ldo-bypass:use pu_dummy if VDDSOC share with VDDPU */
+};
};
};
+ pu_dummy: pudummy_reg {
+ compatible = "fsl,imx6-dummy-pureg"; /* only used in ldo-bypass */
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;