--- /dev/null
+What: /proc/diskstats
+Date: February 2008
+Contact: Jerome Marchand <jmarchan@redhat.com>
+Description:
+ The /proc/diskstats file displays the I/O statistics
+ of block devices. Each line contains the following 14
+ fields:
+ 1 - major number
+ 2 - minor mumber
+ 3 - device name
+ 4 - reads completed succesfully
+ 5 - reads merged
+ 6 - sectors read
+ 7 - time spent reading (ms)
+ 8 - writes completed
+ 9 - writes merged
+ 10 - sectors written
+ 11 - time spent writing (ms)
+ 12 - I/Os currently in progress
+ 13 - time spent doing I/Os (ms)
+ 14 - weighted time spent doing I/Os (ms)
+ For more details refer to Documentation/iostats.txt
--- /dev/null
+What: /sys/block/<disk>/stat
+Date: February 2008
+Contact: Jerome Marchand <jmarchan@redhat.com>
+Description:
+ The /sys/block/<disk>/stat files displays the I/O
+ statistics of disk <disk>. They contain 11 fields:
+ 1 - reads completed succesfully
+ 2 - reads merged
+ 3 - sectors read
+ 4 - time spent reading (ms)
+ 5 - writes completed
+ 6 - writes merged
+ 7 - sectors written
+ 8 - time spent writing (ms)
+ 9 - I/Os currently in progress
+ 10 - time spent doing I/Os (ms)
+ 11 - weighted time spent doing I/Os (ms)
+ For more details refer Documentation/iostats.txt
+
+
+What: /sys/block/<disk>/<part>/stat
+Date: February 2008
+Contact: Jerome Marchand <jmarchan@redhat.com>
+Description:
+ The /sys/block/<disk>/<part>/stat files display the
+ I/O statistics of partition <part>. The format is the
+ same as the above-written /sys/block/<disk>/stat
+ format.
char buf[256];
} ans;
- int id, rc;
+ int id = 0, rc;
struct nlattr *na;
int rep_len;
void task_context_switch_counts(struct taskstats *t)
{
printf("\n\nTask %15s%15s\n"
- " %15lu%15lu\n",
+ " %15llu%15llu\n",
"voluntary", "nonvoluntary",
t->nvcsw, t->nivcsw);
}
goto done;
}
- PRINTF("nlmsghdr size=%d, nlmsg_len=%d, rep_len=%d\n",
+ PRINTF("nlmsghdr size=%zu, nlmsg_len=%d, rep_len=%d\n",
sizeof(struct nlmsghdr), msg.n.nlmsg_len, rep_len);
mknod -m 0200 $dir/interfaces c $MAJOR 4
rm -f $dir/revalidate
mknod -m 0200 $dir/revalidate c $MAJOR 5
+rm -f $dir/flush
+mknod -m 0200 $dir/flush c $MAJOR 6
export n_partitions
mkshelf=`echo $0 | sed 's!mkdevs!mkshelf!'`
# /etc/udev/rules.d
#
rules_d="`sed -n '/^udev_rules=/{ s!udev_rules=!!; s!\"!!g; p; }' $conf`"
-if test -z "$rules_d" || test ! -d "$rules_d"; then
+if test -z "$rules_d" ; then
+ rules_d=/etc/udev/rules.d
+fi
+if test ! -d "$rules_d"; then
echo "$me Error: cannot find udev rules directory" 1>&2
exit 1
fi
# These rules tell udev what device nodes to create for aoe support.
-# They may be installed along the following lines (adjusted to what
-# you see on your system).
+# They may be installed along the following lines. Check the section
+# 8 udev manpage to see whether your udev supports SUBSYSTEM, and
+# whether it uses one or two equal signs for SUBSYSTEM and KERNEL.
#
# ecashin@makki ~$ su
# Password:
#
# aoe char devices
-SUBSYSTEM="aoe", KERNEL="discover", NAME="etherd/%k", GROUP="disk", MODE="0220"
-SUBSYSTEM="aoe", KERNEL="err", NAME="etherd/%k", GROUP="disk", MODE="0440"
-SUBSYSTEM="aoe", KERNEL="interfaces", NAME="etherd/%k", GROUP="disk", MODE="0220"
-SUBSYSTEM="aoe", KERNEL="revalidate", NAME="etherd/%k", GROUP="disk", MODE="0220"
+SUBSYSTEM=="aoe", KERNEL=="discover", NAME="etherd/%k", GROUP="disk", MODE="0220"
+SUBSYSTEM=="aoe", KERNEL=="err", NAME="etherd/%k", GROUP="disk", MODE="0440"
+SUBSYSTEM=="aoe", KERNEL=="interfaces", NAME="etherd/%k", GROUP="disk", MODE="0220"
+SUBSYSTEM=="aoe", KERNEL=="revalidate", NAME="etherd/%k", GROUP="disk", MODE="0220"
+SUBSYSTEM=="aoe", KERNEL=="flush", NAME="etherd/%k", GROUP="disk", MODE="0220"
# aoe block devices
-KERNEL="etherd*", NAME="%k", GROUP="disk"
+KERNEL=="etherd*", NAME="%k", GROUP="disk"
---------------------------
-What: a.out interpreter support for ELF executables
-When: 2.6.25
-Files: fs/binfmt_elf.c
-Why: Using a.out interpreters for ELF executables was a feature for
- transition from a.out to ELF. But now it is unlikely to be still
- needed anymore and removing it would simplify the hairy ELF
- loader code.
-Who: Andi Kleen <ak@suse.de>
-
----------------------------
-
What: remove EXPORT_SYMBOL(kernel_thread)
When: August 2006
Files: arch/*/kernel/*_ksyms.c
---------------------------
-What: 'time' kernel boot parameter
-When: January 2008
-Why: replaced by 'printk.time=<value>' so that printk timestamps can be
- enabled or disabled as needed
-Who: Randy Dunlap <randy.dunlap@oracle.com>
-
----------------------------
-
What: libata spindown skipping and warning
When: Dec 2008
Why: Some halt(8) implementations synchronize caches for and spin
map=normal Map non-Rock Ridge filenames to lower case
map=acorn As map=normal but also apply Acorn extensions if present
mode=xxx Sets the permissions on files to xxx
+ dmode=xxx Sets the permissions on directories to xxx
nojoliet Ignore Joliet extensions if they are present.
norock Ignore Rock Ridge extensions if they are present.
hide Completely strip hidden files from the file system.
const char *dev_name: the device name we are mounting.
void *data: arbitrary mount options, usually comes as an ASCII
- string
+ string (see "Mount Options" section)
struct vfsmount *mnt: a vfs-internal representation of a mount point
must initialize this properly.
void *data: arbitrary mount options, usually comes as an ASCII
- string
+ string (see "Mount Options" section)
int silent: whether or not to be silent on error
umount_begin: called when the VFS is unmounting a filesystem.
- show_options: called by the VFS to show mount options for /proc/<pid>/mounts.
+ show_options: called by the VFS to show mount options for
+ /proc/<pid>/mounts. (see "Mount Options" section)
quota_read: called by the VFS to read from filesystem quota file.
For further information on dentry locking, please refer to the document
Documentation/filesystems/dentry-locking.txt.
+Mount Options
+=============
+
+Parsing options
+---------------
+
+On mount and remount the filesystem is passed a string containing a
+comma separated list of mount options. The options can have either of
+these forms:
+
+ option
+ option=value
+
+The <linux/parser.h> header defines an API that helps parse these
+options. There are plenty of examples on how to use it in existing
+filesystems.
+
+Showing options
+---------------
+
+If a filesystem accepts mount options, it must define show_options()
+to show all the currently active options. The rules are:
+
+ - options MUST be shown which are not default or their values differ
+ from the default
+
+ - options MAY be shown which are enabled by default or have their
+ default value
+
+Options used only internally between a mount helper and the kernel
+(such as file descriptors), or which only have an effect during the
+mounting (such as ones controlling the creation of a journal) are exempt
+from the above rules.
+
+The underlying reason for the above rules is to make sure, that a
+mount can be accurately replicated (e.g. umounting and mounting again)
+based on the information found in /proc/mounts.
+
+A simple method of saving options at mount/remount time and showing
+them is provided with the save_mount_options() and
+generic_show_options() helper functions. Please note, that using
+these may have drawbacks. For more info see header comments for these
+functions in fs/namespace.c.
Resources
=========
Each set of stats only applies to the indicated device; if you want
system-wide stats you'll have to find all the devices and sum them all up.
-Field 1 -- # of reads issued
+Field 1 -- # of reads completed
This is the total number of reads completed successfully.
Field 2 -- # of reads merged, field 6 -- # of writes merged
Reads and writes which are adjacent to each other may be merged for
of queuing for partitions, and at completion for whole disks. This is
a subtle distinction that is probably uninteresting for most cases.
+More significant is the error induced by counting the numbers of
+reads/writes before merges for partitions and after for disks. Since a
+typical workload usually contains a lot of successive and adjacent requests,
+the number of reads/writes issued can be several times higher than the
+number of reads/writes completed.
+
+In 2.6.25, the full statistic set is again available for partitions and
+disk and partition statistics are consistent again. Since we still don't
+keep record of the partition-relative address, an operation is attributed to
+the partition which contains the first sector of the request after the
+eventual merges. As requests can be merged across partition, this could lead
+to some (probably insignificant) innacuracy.
+
Additional notes
----------------
<deci-seconds>: poll all this frequency
0: no polling (default)
- time Show timing data prefixed to each printk message line
- [deprecated, see 'printk.time']
-
tipar.timeout= [HW,PPT]
Set communications timeout in tenths of a second
(default 15).
--- /dev/null
+ =========================
+ MN10300 FUNCTION CALL ABI
+ =========================
+
+=======
+GENERAL
+=======
+
+The MN10300/AM33 kernel runs in little-endian mode; big-endian mode is not
+supported.
+
+The stack grows downwards, and should always be 32-bit aligned. There are
+separate stack pointer registers for userspace and the kernel.
+
+
+================
+ARGUMENT PASSING
+================
+
+The first two arguments (assuming up to 32-bits per argument) to a function are
+passed in the D0 and D1 registers respectively; all other arguments are passed
+on the stack.
+
+If 64-bit arguments are being passed, then they are never split between
+registers and the stack. If the first argument is a 64-bit value, it will be
+passed in D0:D1. If the first argument is not a 64-bit value, but the second
+is, the second will be passed entirely on the stack and D1 will be unused.
+
+Arguments smaller than 32-bits are not coelesced within a register or a stack
+word. For example, two byte-sized arguments will always be passed in separate
+registers or word-sized stack slots.
+
+
+=================
+CALLING FUNCTIONS
+=================
+
+The caller must allocate twelve bytes on the stack for the callee's use before
+it inserts a CALL instruction. The CALL instruction will write into the TOS
+word, but won't actually modify the stack pointer; similarly, the RET
+instruction reads from the TOS word of the stack, but doesn't move the stack
+pointer beyond it.
+
+
+ Stack:
+ | |
+ | |
+ |---------------| SP+20
+ | 4th Arg |
+ |---------------| SP+16
+ | 3rd Arg |
+ |---------------| SP+12
+ | D1 Save Slot |
+ |---------------| SP+8
+ | D0 Save Slot |
+ |---------------| SP+4
+ | Return Addr |
+ |---------------| SP
+ | |
+ | |
+
+
+The caller must leave space on the stack (hence an allocation of twelve bytes)
+in which the callee may store the first two arguments.
+
+
+============
+RETURN VALUE
+============
+
+The return value is passed in D0 for an integer (or D0:D1 for a 64-bit value),
+or A0 for a pointer.
+
+If the return value is a value larger than 64-bits, or is a structure or an
+array, then a hidden first argument will be passed to the callee by the caller:
+this will point to a piece of memory large enough to hold the result of the
+function. In this case, the callee will return the value in that piece of
+memory, and no value will be returned in D0 or A0.
+
+
+===================
+REGISTER CLOBBERING
+===================
+
+The values in certain registers may be clobbered by the callee, and other
+values must be saved:
+
+ Clobber: D0-D1, A0-A1, E0-E3
+ Save: D2-D3, A2-A3, E4-E7, SP
+
+All other non-supervisor-only registers are clobberable (such as MDR, MCRL,
+MCRH).
+
+
+=================
+SPECIAL REGISTERS
+=================
+
+Certain ordinary registers may carry special usage for the compiler:
+
+ A3: Frame pointer
+ E2: TLS pointer
+
+
+==========
+KERNEL ABI
+==========
+
+The kernel may use a slightly different ABI internally.
+
+ (*) E2
+
+ If CONFIG_MN10300_CURRENT_IN_E2 is defined, then the current task pointer
+ will be kept in the E2 register, and that register will be marked
+ unavailable for the compiler to use as a scratch register.
+
+ Normally the kernel uses something like:
+
+ MOV SP,An
+ AND 0xFFFFE000,An
+ MOV (An),Rm // Rm holds current
+ MOV (yyy,Rm) // Access current->yyy
+
+ To find the address of current; but since this option permits current to
+ be carried globally in an register, it can use:
+
+ MOV (yyy,E2) // Access current->yyy
+
+ instead.
+
+
+===============
+SYSTEM CALL ABI
+===============
+
+System calls are called with the following convention:
+
+ REGISTER ENTRY EXIT
+ =============== ======================= =======================
+ D0 Syscall number Return value
+ A0 1st syscall argument Saved
+ D1 2nd syscall argument Saved
+ A3 3rd syscall argument Saved
+ A2 4th syscall argument Saved
+ D3 5th syscall argument Saved
+ D2 6th syscall argument Saved
+
+All other registers are saved. The layout is a consequence of the way the MOVM
+instruction stores registers onto the stack.
--- /dev/null
+ =========================================
+ PART-SPECIFIC SOURCE COMPARTMENTALISATION
+ =========================================
+
+The sources for various parts are compartmentalised at two different levels:
+
+ (1) Processor level
+
+ The "processor level" is a CPU core plus the other on-silicon
+ peripherals.
+
+ Processor-specific header files are divided among directories in a similar
+ way to the CPU level:
+
+ (*) include/asm-mn10300/proc-mn103e010/
+
+ Support for the AM33v2 CPU core.
+
+ The appropriate processor is selected by a CONFIG_MN10300_PROC_YYYY option
+ from the "Processor support" choice menu in the arch/mn10300/Kconfig file.
+
+
+ (2) Unit level
+
+ The "unit level" is a processor plus all the external peripherals
+ controlled by that processor.
+
+ Unit-specific header files are divided among directories in a similar way
+ to the CPU level; not only that, but specific sources may also be
+ segregated into separate directories under the arch directory:
+
+ (*) include/asm-mn10300/unit-asb2303/
+ (*) arch/mn10300/unit-asb2303/
+
+ Support for the ASB2303 board with an ASB2308 daughter board.
+
+ (*) include/asm-mn10300/unit-asb2305/
+ (*) arch/mn10300/unit-asb2305/
+
+ Support for the ASB2305 board.
+
+ The appropriate processor is selected by a CONFIG_MN10300_UNIT_ZZZZ option
+ from the "Unit type" choice menu in the arch/mn10300/Kconfig file.
+
+
+============
+COMPILE TIME
+============
+
+When the kernel is compiled, symbolic links will be made in the asm header file
+directory for this arch:
+
+ include/asm-mn10300/proc => include/asm-mn10300/proc-YYYY/
+ include/asm-mn10300/unit => include/asm-mn10300/unit-ZZZZ/
+
+So that the header files contained in those directories can be accessed without
+lots of #ifdef-age.
+
+The appropriate arch/mn10300/unit-ZZZZ directory will also be entered by the
+compilation process; all other unit-specific directories will be ignored.
and thermal cooling devices (fan, processor...) to register with the thermal management
solution and to be a part of it.
-This how-to focusses on enabling new thermal zone and cooling devices to participate
+This how-to focuses on enabling new thermal zone and cooling devices to participate
in thermal management.
This solution is platform independent and any type of thermal zone devices and
cooling devices should be able to make use of the infrastructure.
name: the thermal zone name.
trips: the total number of trip points this thermal zone supports.
devdata: device private data
- ops: thermal zone device callbacks.
+ ops: thermal zone device call-backs.
.bind: bind the thermal zone device with a thermal cooling device.
- .unbind: unbing the thermal zone device with a thermal cooling device.
+ .unbind: unbind the thermal zone device with a thermal cooling device.
.get_temp: get the current temperature of the thermal zone.
.get_mode: get the current mode (user/kernel) of the thermal zone.
"kernel" means thermal management is done in kernel.
It tries to bind itself to all the thermal zone devices register at the same time.
name: the cooling device name.
devdata: device private data.
- ops: thermal cooling devices callbacks.
+ ops: thermal cooling devices call-backs.
.get_max_state: get the Maximum throttle state of the cooling device.
.get_cur_state: get the Current throttle state of the cooling device.
.set_cur_state: set the Current throttle state of the cooling device.
RW read/write value
All thermal sysfs attributes will be represented under /sys/class/thermal
-/sys/class/thermal/
Thermal zone device sys I/F, created once it's registered:
|thermal_zone[0-*]:
These two dynamic attributes are created/removed in pairs.
They represent the relationship between a thermal zone and its associated cooling device.
They are created/removed for each
-thermal_zone_bind_cooling_device/thermal_zone_unbind_cooling_device successful exection.
+thermal_zone_bind_cooling_device/thermal_zone_unbind_cooling_device successful execution.
|thermal_zone[0-*]
|-----cdev[0-*]: The [0-*]th cooling device in the current thermal zone
Optional
temp Current temperature as reported by thermal zone (sensor)
- Unit: degree celsius
+ Unit: degree Celsius
RO
Required
-mode One of the predifned values in [kernel, user]
+mode One of the predefined values in [kernel, user]
This file gives information about the algorithm
that is currently managing the thermal zone.
It can be either default kernel based algorithm
charge of the thermal management.
trip_point_[0-*]_temp The temperature above which trip point will be fired
- Unit: degree celsius
+ Unit: degree Celsius
RO
Optional
trip_point_[0-*]_type Strings which indicate the type of the trip point
- Eg. it can be one of critical, hot, passive,
+ E.g. it can be one of critical, hot, passive,
active[0-*] for ACPI thermal zone.
RO
Optional
RO
Optional
-cdev[0-*]_trip_point The trip point with which cdev[0-*] is assocated in this thermal zone
+cdev[0-*]_trip_point The trip point with which cdev[0-*] is associated in this thermal zone
-1 means the cooling device is not associated with any trip point.
RO
Optional
ACPI thermal zone may support multiple trip points like critical/hot/passive/active.
If an ACPI thermal zone supports critical, passive, active[0] and active[1] at the same time,
-it may register itself as a thermale_zone_device (thermal_zone1) with 4 trip points in all.
+it may register itself as a thermal_zone_device (thermal_zone1) with 4 trip points in all.
It has one processor and one fan, which are both registered as thermal_cooling_device.
If the processor is listed in _PSL method, and the fan is listed in _AL0 method,
the sys I/F structure will be built like this:
W: http://www.at91.com/
S: Maintained
+ATMEL AT91 / AT32 SERIAL DRIVER
+P: Haavard Skinnemoen
+M: hskinnemoen@atmel.com
+L: linux-kernel@vger.kernel.org
+S: Supported
+
ATMEL LCDFB DRIVER
P: Nicolas Ferre
M: nicolas.ferre@atmel.com
CRIS PORT
P: Mikael Starvik
M: starvik@axis.com
+P: Jesper Nilsson
+M: jesper.nilsson@axis.com
L: dev-etrax@axis.com
W: http://developer.axis.com
S: Maintained
W: http://www.linux-mm.org
S: Maintained
+MEI MN10300/AM33 PORT
+P: David Howells
+M: dhowells@redhat.com
+P: Koichi Yasutake
+M: yasutake.koichi@jp.panasonic.com
+L: linux-am33-list@redhat.com
+W: ftp://ftp.redhat.com/pub/redhat/gnupro/AM33/
+S: Maintained
+
MEMORY TECHNOLOGY DEVICES (MTD)
P: David Woodhouse
M: dwmw2@infradead.org
S: Maintained
F: drivers/net/wireless/rt2x00/
+RAMDISK RAM BLOCK DEVICE DRIVER
+P: Nick Piggin
+M: npiggin@suse.de
+S: Maintained
+
RANDOM NUMBER DRIVER
P: Matt Mackall
M: mpm@selenic.com
S: Maintained
UDF FILESYSTEM
-P: Ben Fennema
-M: bfennema@falcon.csc.calpoly.edu
+P: Jan Kara
+M: jack@suse.cz
W: http://linux-udf.sourceforge.net
S: Maintained
depends on SMP
default y
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
source "init/Kconfig"
Take the default (1) unless you want more control or more info.
+config HZ
+ int
+ default 1200 if ALPHA_RAWHIDE
+ default 1024
+
source "drivers/pci/Kconfig"
source "drivers/eisa/Kconfig"
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/utsname.h>
#include <linux/time.h>
#include <linux/timex.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/utsname.h>
#include <linux/time.h>
#include <linux/major.h>
return 0;
}
-/*
- * Fill in the user structure for an ECOFF core dump.
- */
-void
-dump_thread(struct pt_regs * pt, struct user * dump)
-{
- /* switch stack follows right below pt_regs: */
- struct switch_stack * sw = ((struct switch_stack *) pt) - 1;
-
- dump->magic = CMAGIC;
- dump->start_code = current->mm->start_code;
- dump->start_data = current->mm->start_data;
- dump->start_stack = rdusp() & ~(PAGE_SIZE - 1);
- dump->u_tsize = ((current->mm->end_code - dump->start_code)
- >> PAGE_SHIFT);
- dump->u_dsize = ((current->mm->brk + PAGE_SIZE-1 - dump->start_data)
- >> PAGE_SHIFT);
- dump->u_ssize = (current->mm->start_stack - dump->start_stack
- + PAGE_SIZE-1) >> PAGE_SHIFT;
-
- /*
- * We store the registers in an order/format that is
- * compatible with DEC Unix/OSF/1 as this makes life easier
- * for gdb.
- */
- dump->regs[EF_V0] = pt->r0;
- dump->regs[EF_T0] = pt->r1;
- dump->regs[EF_T1] = pt->r2;
- dump->regs[EF_T2] = pt->r3;
- dump->regs[EF_T3] = pt->r4;
- dump->regs[EF_T4] = pt->r5;
- dump->regs[EF_T5] = pt->r6;
- dump->regs[EF_T6] = pt->r7;
- dump->regs[EF_T7] = pt->r8;
- dump->regs[EF_S0] = sw->r9;
- dump->regs[EF_S1] = sw->r10;
- dump->regs[EF_S2] = sw->r11;
- dump->regs[EF_S3] = sw->r12;
- dump->regs[EF_S4] = sw->r13;
- dump->regs[EF_S5] = sw->r14;
- dump->regs[EF_S6] = sw->r15;
- dump->regs[EF_A3] = pt->r19;
- dump->regs[EF_A4] = pt->r20;
- dump->regs[EF_A5] = pt->r21;
- dump->regs[EF_T8] = pt->r22;
- dump->regs[EF_T9] = pt->r23;
- dump->regs[EF_T10] = pt->r24;
- dump->regs[EF_T11] = pt->r25;
- dump->regs[EF_RA] = pt->r26;
- dump->regs[EF_T12] = pt->r27;
- dump->regs[EF_AT] = pt->r28;
- dump->regs[EF_SP] = rdusp();
- dump->regs[EF_PS] = pt->ps;
- dump->regs[EF_PC] = pt->pc;
- dump->regs[EF_GP] = pt->gp;
- dump->regs[EF_A0] = pt->r16;
- dump->regs[EF_A1] = pt->r17;
- dump->regs[EF_A2] = pt->r18;
- memcpy((char *)dump->regs + EF_SIZE, sw->fp, 32 * 8);
-}
-EXPORT_SYMBOL(dump_thread);
-
/*
* Fill in the user structure for a ELF core dump.
*/
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/screen_info.h>
#include <linux/delay.h>
#include <linux/mc146818rtc.h>
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
bool
default y
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
config ARCH_MAY_HAVE_PC_FDC
bool
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24-rc3
-# Wed Nov 28 15:13:57 2007
+# Linux kernel version: 2.6.24
+# Thu Feb 7 14:10:30 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_PREEMPT_RCU is not set
#
# System Type
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM7X00A is not set
#
# Orion Implementations
CONFIG_CMDLINE=""
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
+# CONFIG_ATAGS_PROC is not set
#
# Floating point emulation
# Power management options
#
# CONFIG_PM is not set
-CONFIG_SUSPEND_UP_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
#
# Networking
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
# CONFIG_NET_KEY is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
#
CONFIG_NET_PKTGEN=m
# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
CONFIG_SCSI_DMA=y
# CONFIG_SCSI_TGT is not set
# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
+# CONFIG_SCSI_PROC_FS is not set
#
# SCSI support type (disk, tape, CD-ROM)
CONFIG_BLK_DEV_SD=y
# CONFIG_CHR_DEV_ST is not set
# CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR=m
# CONFIG_BLK_DEV_SR_VENDOR is not set
-CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SG=m
# CONFIG_CHR_DEV_SCH is not set
#
# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
#
-CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_MULTI_LUN is not set
# CONFIG_SCSI_CONSTANTS is not set
# CONFIG_SCSI_LOGGING is not set
# CONFIG_SCSI_SCAN_ASYNC is not set
# CONFIG_SCSI_INITIO is not set
# CONFIG_SCSI_INIA100 is not set
# CONFIG_SCSI_STEX is not set
-CONFIG_SCSI_MVSATA=y
-
-#
-# Sata options
-#
-# CONFIG_MV_SATA_SUPPORT_ATAPI is not set
-# CONFIG_MV_SATA_ENABLE_1MB_IOS is not set
-CONFIG_SATA_NO_DEBUG=y
-# CONFIG_SATA_DEBUG_ON_ERROR is not set
-# CONFIG_SATA_FULL_DEBUG is not set
# CONFIG_SCSI_SYM53C8XX_2 is not set
# CONFIG_SCSI_IPR is not set
# CONFIG_SCSI_QLOGIC_1280 is not set
# CONFIG_SCSI_NSP32 is not set
# CONFIG_SCSI_DEBUG is not set
# CONFIG_SCSI_SRP is not set
-CONFIG_ATA=m
+CONFIG_ATA=y
# CONFIG_ATA_NONSTANDARD is not set
# CONFIG_SATA_AHCI is not set
# CONFIG_SATA_SVW is not set
# CONFIG_ATA_PIIX is not set
-# CONFIG_SATA_MV is not set
+CONFIG_SATA_MV=y
# CONFIG_SATA_NV is not set
# CONFIG_PDC_ADMA is not set
# CONFIG_SATA_QSTOR is not set
# CONFIG_PATA_MPIIX is not set
# CONFIG_PATA_OLDPIIX is not set
# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
# CONFIG_PATA_NS87410 is not set
# CONFIG_PATA_NS87415 is not set
# CONFIG_PATA_OPTI is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
-# CONFIG_IP1000 is not set
# CONFIG_ARCNET is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
# CONFIG_NE2K_PCI is not set
# CONFIG_8139CP is not set
# CONFIG_8139TOO is not set
+# CONFIG_R6040 is not set
# CONFIG_SIS900 is not set
# CONFIG_EPIC100 is not set
# CONFIG_SUNDANCE is not set
CONFIG_E1000_NAPI=y
# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
# CONFIG_E1000E is not set
+# CONFIG_E1000E_ENABLED is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
# CONFIG_NS83820 is not set
# CONFIG_HAMACHI is not set
# CONFIG_YELLOWFIN is not set
# CONFIG_NIU is not set
# CONFIG_MLX4_CORE is not set
# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
# CONFIG_TR is not set
#
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NET_FC is not set
-# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
#
# Serial drivers
#
# Miscellaneous I2C Chip support
#
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
# CONFIG_DS1682 is not set
# CONFIG_SENSORS_EEPROM is not set
# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_PCF8575 is not set
# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_TPS65010 is not set
# CONFIG_SENSORS_MAX6875 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_I2C_DEBUG_CORE is not set
CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_USB=y
# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
#
# Miscellaneous USB options
# USB Host Controller Drivers
#
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_SPLIT_ISO=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_UHCI_HCD=y
-CONFIG_USB_SL811_HCD=y
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
#
#
# USB port drivers
#
-
-#
-# USB Serial Converter support
-#
# CONFIG_USB_SERIAL is not set
#
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
# CONFIG_USB_GADGET is not set
# CONFIG_MMC is not set
CONFIG_NEW_LEDS=y
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_V3020 is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_UTF8 is not set
# CONFIG_DLM is not set
-CONFIG_INSTRUMENTATION=y
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
#
# Kernel hacking
CONFIG_CRYPTO=y
CONFIG_CRYPTO_ALGAPI=m
CONFIG_CRYPTO_BLKCIPHER=m
+# CONFIG_CRYPTO_SEQIV is not set
CONFIG_CRYPTO_MANAGER=m
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_XCBC is not set
CONFIG_CRYPTO_PCBC=m
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_XTS is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_TEST is not set
# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_LZO is not set
CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
#
# Library routines
#include <linux/unistd.h>
#include <linux/slab.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/delay.h>
#include <linux/reboot.h>
#include <linux/interrupt.h>
}
EXPORT_SYMBOL(dump_fpu);
-/*
- * fill in the user structure for a core dump..
- */
-void dump_thread(struct pt_regs * regs, struct user * dump)
-{
- struct task_struct *tsk = current;
-
- dump->magic = CMAGIC;
- dump->start_code = tsk->mm->start_code;
- dump->start_stack = regs->ARM_sp & ~(PAGE_SIZE - 1);
-
- dump->u_tsize = (tsk->mm->end_code - tsk->mm->start_code) >> PAGE_SHIFT;
- dump->u_dsize = (tsk->mm->brk - tsk->mm->start_data + PAGE_SIZE - 1) >> PAGE_SHIFT;
- dump->u_ssize = 0;
-
- dump->u_debugreg[0] = tsk->thread.debug.bp[0].address;
- dump->u_debugreg[1] = tsk->thread.debug.bp[1].address;
- dump->u_debugreg[2] = tsk->thread.debug.bp[0].insn.arm;
- dump->u_debugreg[3] = tsk->thread.debug.bp[1].insn.arm;
- dump->u_debugreg[4] = tsk->thread.debug.nsaved;
-
- if (dump->start_stack < 0x04000000)
- dump->u_ssize = (0x04000000 - dump->start_stack) >> PAGE_SHIFT;
-
- dump->regs = *regs;
- dump->u_fpvalid = dump_fpu (regs, &dump->u_fp);
-}
-EXPORT_SYMBOL(dump_thread);
-
/*
* Shuffle the argument into the correct register before calling the
* thread function. r1 is the thread argument, r2 is the pointer to
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
EXPORT_SYMBOL(clk_set_parent);
/* establish PCK0..PCK3 parentage and rate */
-static void init_programmable_clock(struct clk *clk)
+static void __init init_programmable_clock(struct clk *clk)
{
struct clk *parent;
u32 pckr;
return 0;
}
-static struct seq_operations davinci_ck_op = {
+static const struct seq_operations davinci_ck_op = {
.start = davinci_ck_start,
.next = davinci_ck_next,
.stop = davinci_ck_stop,
return seq_open(file, &davinci_ck_op);
}
-static struct file_operations proc_davinci_ck_operations = {
+static const struct file_operations proc_davinci_ck_operations = {
.open = davinci_ck_open,
.read = seq_read,
.llseek = seq_lseek,
}
/*
- * Setup windows for PCI+PCIE IO+MAM space
+ * Setup windows for PCI+PCIe IO+MEM space.
*/
- orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_BASE,
- ORION_PCIE_IO_SIZE, ORION_PCIE_IO_REMAP);
- orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_BASE,
- ORION_PCI_IO_SIZE, ORION_PCI_IO_REMAP);
- orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_BASE,
+ orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
+ ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
+ orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
+ ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
+ orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
ORION_PCIE_MEM_SIZE, -1);
- orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_BASE,
+ orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
ORION_PCI_MEM_SIZE, -1);
}
#include <asm/page.h>
#include <asm/timex.h>
#include <asm/mach/map.h>
-#include <asm/arch/orion.h>
+#include <asm/arch/hardware.h>
#include "common.h"
/*****************************************************************************
****************************************************************************/
static struct map_desc orion_io_desc[] __initdata = {
{
- .virtual = ORION_REGS_BASE,
- .pfn = __phys_to_pfn(ORION_REGS_BASE),
+ .virtual = ORION_REGS_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION_REGS_PHYS_BASE),
.length = ORION_REGS_SIZE,
.type = MT_DEVICE
},
{
- .virtual = ORION_PCIE_IO_BASE,
- .pfn = __phys_to_pfn(ORION_PCIE_IO_BASE),
+ .virtual = ORION_PCIE_IO_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION_PCIE_IO_PHYS_BASE),
.length = ORION_PCIE_IO_SIZE,
.type = MT_DEVICE
},
{
- .virtual = ORION_PCI_IO_BASE,
- .pfn = __phys_to_pfn(ORION_PCI_IO_BASE),
+ .virtual = ORION_PCI_IO_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION_PCI_IO_PHYS_BASE),
.length = ORION_PCI_IO_SIZE,
.type = MT_DEVICE
},
{
- .virtual = ORION_PCIE_WA_BASE,
- .pfn = __phys_to_pfn(ORION_PCIE_WA_BASE),
+ .virtual = ORION_PCIE_WA_VIRT_BASE,
+ .pfn = __phys_to_pfn(ORION_PCIE_WA_PHYS_BASE),
.length = ORION_PCIE_WA_SIZE,
.type = MT_DEVICE
},
static struct resource orion_uart_resources[] = {
{
- .start = UART0_BASE,
- .end = UART0_BASE + 0xff,
+ .start = UART0_PHYS_BASE,
+ .end = UART0_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
.flags = IORESOURCE_IRQ,
},
{
- .start = UART1_BASE,
- .end = UART1_BASE + 0xff,
+ .start = UART1_PHYS_BASE,
+ .end = UART1_PHYS_BASE + 0xff,
.flags = IORESOURCE_MEM,
},
{
static struct plat_serial8250_port orion_uart_data[] = {
{
- .mapbase = UART0_BASE,
- .membase = (char *)UART0_BASE,
+ .mapbase = UART0_PHYS_BASE,
+ .membase = (char *)UART0_VIRT_BASE,
.irq = IRQ_ORION_UART0,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
.uartclk = ORION_TCLK,
},
{
- .mapbase = UART1_BASE,
- .membase = (char *)UART1_BASE,
+ .mapbase = UART1_PHYS_BASE,
+ .membase = (char *)UART1_VIRT_BASE,
.irq = IRQ_ORION_UART1,
.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
.iotype = UPIO_MEM,
static struct resource orion_ehci0_resources[] = {
{
- .start = ORION_USB0_REG_BASE,
- .end = ORION_USB0_REG_BASE + SZ_4K,
+ .start = ORION_USB0_PHYS_BASE,
+ .end = ORION_USB0_PHYS_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
static struct resource orion_ehci1_resources[] = {
{
- .start = ORION_USB1_REG_BASE,
- .end = ORION_USB1_REG_BASE + SZ_4K,
+ .start = ORION_USB1_PHYS_BASE,
+ .end = ORION_USB1_PHYS_BASE + SZ_4K,
.flags = IORESOURCE_MEM,
},
{
static struct resource orion_eth_shared_resources[] = {
{
- .start = ORION_ETH_REG_BASE,
- .end = ORION_ETH_REG_BASE + 0xffff,
+ .start = ORION_ETH_PHYS_BASE,
+ .end = ORION_ETH_PHYS_BASE + 0xffff,
.flags = IORESOURCE_MEM,
},
};
static struct resource orion_i2c_resources[] = {
{
.name = "i2c base",
- .start = I2C_BASE,
- .end = I2C_BASE + 0x20 -1,
+ .start = I2C_PHYS_BASE,
+ .end = I2C_PHYS_BASE + 0x20 -1,
.flags = IORESOURCE_MEM,
},
{
},
};
+/*****************************************************************************
+ * Sata port
+ ****************************************************************************/
+static struct resource orion_sata_resources[] = {
+ {
+ .name = "sata base",
+ .start = ORION_SATA_PHYS_BASE,
+ .end = ORION_SATA_PHYS_BASE + 0x5000 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "sata irq",
+ .start = IRQ_ORION_SATA,
+ .end = IRQ_ORION_SATA,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device orion_sata = {
+ .name = "sata_mv",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(orion_sata_resources),
+ .resource = orion_sata_resources,
+};
+
+void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
+{
+ orion_sata.dev.platform_data = sata_data;
+ platform_device_register(&orion_sata);
+}
+
/*****************************************************************************
* General
****************************************************************************/
void __init orion_eth_init(struct mv643xx_eth_platform_data *eth_data);
+/*
+ * Orion Sata platform_data, used by machine-setup
+ */
+
+struct mv_sata_platform_data;
+
+void __init orion_sata_init(struct mv_sata_platform_data *sata_data);
+
#endif /* __ARCH_ORION_COMMON_H__ */
MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
/* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
- .phys_io = ORION_REGS_BASE,
- .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xfffc,
+ .phys_io = ORION_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.init_machine = db88f5281_init,
.map_io = orion_map_io,
*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
- orion_write(ORION_REGS_BASE | 0x20070,
+ orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
+ orion_write(ORION_REGS_VIRT_BASE | 0x20070,
(0x7941 | (((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
MACHINE_START(DNS323, "D-Link DNS-323")
/* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
- .phys_io = ORION_REGS_BASE,
- .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = dns323_init,
.map_io = orion_map_io,
#include <linux/mtd/nand.h>
#include <linux/mv643xx_eth.h>
#include <linux/i2c.h>
+#include <linux/ata_platform.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/mach/arch.h>
.addr = 0x32,
};
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct mv_sata_platform_data kurobox_pro_sata_data = {
+ .n_ports = 2,
+};
+
/*****************************************************************************
* General Setup
****************************************************************************/
/*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
- orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
+ orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
+ orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
platform_add_devices(kurobox_pro_devices, ARRAY_SIZE(kurobox_pro_devices));
i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
orion_eth_init(&kurobox_pro_eth_data);
+ orion_sata_init(&kurobox_pro_sata_data);
}
MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
- .phys_io = ORION_REGS_BASE,
- .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = kurobox_pro_init,
.map_io = orion_map_io,
orion_pcie_id(&dev, &rev);
if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
/* extended register space */
- pcie_addr = ORION_PCIE_WA_BASE;
+ pcie_addr = ORION_PCIE_WA_VIRT_BASE;
pcie_addr |= PCIE_CONF_BUS(bus->number) |
PCIE_CONF_DEV(PCI_SLOT(devfn)) |
PCIE_CONF_FUNC(PCI_FUNC(devfn)) |
*/
res[0].name = "PCI-EX I/O Space";
res[0].flags = IORESOURCE_IO;
- res[0].start = ORION_PCIE_IO_REMAP;
+ res[0].start = ORION_PCIE_IO_BUS_BASE;
res[0].end = res[0].start + ORION_PCIE_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCIE IO resource failed\n");
*/
res[1].name = "PCI-EX Memory Space";
res[1].flags = IORESOURCE_MEM;
- res[1].start = ORION_PCIE_MEM_BASE;
+ res[1].start = ORION_PCIE_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION_PCIE_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCIE Memory resource failed\n");
*/
res[0].name = "PCI I/O Space";
res[0].flags = IORESOURCE_IO;
- res[0].start = ORION_PCI_IO_REMAP;
+ res[0].start = ORION_PCI_IO_BUS_BASE;
res[0].end = res[0].start + ORION_PCI_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCI IO resource failed\n");
*/
res[1].name = "PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
- res[1].start = ORION_PCI_MEM_BASE;
+ res[1].start = ORION_PCI_MEM_PHYS_BASE;
res[1].end = res[1].start + ORION_PCI_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCI Memory resource failed\n");
#include <linux/irq.h>
#include <linux/mtd/physmap.h>
#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
.addr = 0x68,
};
+/*****************************************************************************
+ * Sata
+ ****************************************************************************/
+static struct mv_sata_platform_data rd88f5182_sata_data = {
+ .n_ports = 2,
+};
+
/*****************************************************************************
* General Setup
****************************************************************************/
/*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
- orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
+ orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
+ orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
orion_eth_init(&rd88f5182_eth_data);
+ orion_sata_init(&rd88f5182_sata_data);
}
MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
/* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
- .phys_io = ORION_REGS_BASE,
- .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = rd88f5182_init,
.map_io = orion_map_io,
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/serial_reg.h>
+#include <linux/ata_platform.h>
#include <asm/mach-types.h>
#include <asm/gpio.h>
#include <asm/mach/arch.h>
};
/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct mv_sata_platform_data qnap_ts209_sata_data = {
+ .n_ports = 2,
+};
+
+/*****************************************************************************
+
* General Setup
****************************************************************************/
* QNAP TS-[12]09 specific power off method via UART1-attached PIC
*/
-#define UART1_REG(x) (UART1_BASE + ((UART_##x) << 2))
+#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
static void qnap_ts209_power_off(void)
{
/*
* Open a special address decode windows for the PCIE WA.
*/
- orion_write(ORION_REGS_BASE | 0x20074, ORION_PCIE_WA_BASE);
- orion_write(ORION_REGS_BASE | 0x20070, (0x7941 |
+ orion_write(ORION_REGS_VIRT_BASE | 0x20074, ORION_PCIE_WA_PHYS_BASE);
+ orion_write(ORION_REGS_VIRT_BASE | 0x20070, (0x7941 |
(((ORION_PCIE_WA_SIZE >> 16) - 1)) << 16));
/*
ARRAY_SIZE(qnap_ts209_devices));
i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
orion_eth_init(&qnap_ts209_eth_data);
+ orion_sata_init(&qnap_ts209_sata_data);
}
MACHINE_START(TS209, "QNAP TS-109/TS-209")
/* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
- .phys_io = ORION_REGS_BASE,
- .io_pg_offst = ((ORION_REGS_BASE) >> 18) & 0xFFFC,
+ .phys_io = ORION_REGS_PHYS_BASE,
+ .io_pg_offst = ((ORION_REGS_VIRT_BASE) >> 18) & 0xFFFC,
.boot_params = 0x00000100,
.init_machine = qnap_ts209_init,
.map_io = orion_map_io,
AD2D0ER = 0;
AD2D1ER = 0;
-
- printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
}
/*
int i, ret = 0;
if (cpu_is_pxa3xx()) {
+ /*
+ * clear RDH bit every time after reset
+ *
+ * Note: the last 3 bits DxS are write-1-to-clear so carefully
+ * preserve them here in case they will be referenced later
+ */
+ ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
+
clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
if ((ret = pxa_init_dma(32)))
static struct dentry *ocd_debugfs_DS;
static struct dentry *ocd_debugfs_count;
-static u64 ocd_DC_get(void *data)
+static int ocd_DC_get(void *data, u64 *val)
{
- return ocd_read(DC);
+ *val = ocd_read(DC);
+ return 0;
}
-static void ocd_DC_set(void *data, u64 val)
+static int ocd_DC_set(void *data, u64 val)
{
ocd_write(DC, val);
+ return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_DC, ocd_DC_get, ocd_DC_set, "0x%08llx\n");
-static u64 ocd_DS_get(void *data)
+static int ocd_DS_get(void *data, u64 *val)
{
- return ocd_read(DS);
+ *val = ocd_read(DS);
+ return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_DS, ocd_DS_get, NULL, "0x%08llx\n");
-static u64 ocd_count_get(void *data)
+static int ocd_count_get(void *data, u64 *val)
{
- return ocd_count;
+ *val = ocd_count;
+ return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_count, ocd_count_get, NULL, "%lld\n");
}
#endif
+/* --------------------------------------------------------------------
+ * PWM
+ * -------------------------------------------------------------------- */
+static struct resource atmel_pwm0_resource[] __initdata = {
+ PBMEM(0xfff01400),
+ IRQ(24),
+};
+static struct clk atmel_pwm0_mck = {
+ .name = "mck",
+ .parent = &pbb_clk,
+ .mode = pbb_clk_mode,
+ .get_rate = pbb_clk_get_rate,
+ .index = 5,
+};
+
+struct platform_device *__init at32_add_device_pwm(u32 mask)
+{
+ struct platform_device *pdev;
+
+ if (!mask)
+ return NULL;
+
+ pdev = platform_device_alloc("atmel_pwm", 0);
+ if (!pdev)
+ return NULL;
+
+ if (platform_device_add_resources(pdev, atmel_pwm0_resource,
+ ARRAY_SIZE(atmel_pwm0_resource)))
+ goto out_free_pdev;
+
+ if (platform_device_add_data(pdev, &mask, sizeof(mask)))
+ goto out_free_pdev;
+
+ if (mask & (1 << 0))
+ select_peripheral(PA(28), PERIPH_A, 0);
+ if (mask & (1 << 1))
+ select_peripheral(PA(29), PERIPH_A, 0);
+ if (mask & (1 << 2))
+ select_peripheral(PA(21), PERIPH_B, 0);
+ if (mask & (1 << 3))
+ select_peripheral(PA(22), PERIPH_B, 0);
+
+ atmel_pwm0_mck.dev = &pdev->dev;
+
+ platform_device_add(pdev);
+
+ return pdev;
+
+out_free_pdev:
+ platform_device_put(pdev);
+ return NULL;
+}
+
/* --------------------------------------------------------------------
* SSC
* -------------------------------------------------------------------- */
&atmel_usart1_usart,
&atmel_usart2_usart,
&atmel_usart3_usart,
+ &atmel_pwm0_mck,
#if defined(CONFIG_CPU_AT32AP7000)
&macb0_hclk,
&macb0_pclk,
default y
help
If enabled, the entire ASM lowlevel exception and interrupt entry code
- (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
+ (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
(less latency)
config DO_IRQ_L1
depends on !SMP
choice
- prompt "Select PM Wakeup Event Source"
- default PM_WAKEUP_GPIO_BY_SIC_IWR
+ prompt "Default Power Saving Mode"
depends on PM
- help
- If you have a GPIO already configured as input with the corresponding PORTx_MASK
- bit set - "Specify Wakeup Event by SIC_IWR value"
+ default PM_BFIN_SLEEP_DEEPER
+config PM_BFIN_SLEEP_DEEPER
+ bool "Sleep Deeper"
+ help
+ Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
+ power dissipation by disabling the clock to the processor core (CCLK).
+ Furthermore, Standby sets the internal power supply voltage (VDDINT)
+ to 0.85 V to provide the greatest power savings, while preserving the
+ processor state.
+ The PLL and system clock (SCLK) continue to operate at a very low
+ frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
+ the SDRAM is put into Self Refresh Mode. Typically an external event
+ such as GPIO interrupt or RTC activity wakes up the processor.
+ Various Peripherals such as UART, SPORT, PPI may not function as
+ normal during Sleep Deeper, due to the reduced SCLK frequency.
+ When in the sleep mode, system DMA access to L1 memory is not supported.
+
+config PM_BFIN_SLEEP
+ bool "Sleep"
+ help
+ Sleep Mode (High Power Savings) - The sleep mode reduces power
+ dissipation by disabling the clock to the processor core (CCLK).
+ The PLL and system clock (SCLK), however, continue to operate in
+ this mode. Typically an external event or RTC activity will wake
+ up the processor. When in the sleep mode,
+ system DMA access to L1 memory is not supported.
+endchoice
-config PM_WAKEUP_GPIO_BY_SIC_IWR
- bool "Specify Wakeup Event by SIC_IWR value"
config PM_WAKEUP_BY_GPIO
bool "Cause Wakeup Event by GPIO"
-config PM_WAKEUP_GPIO_API
- bool "Configure Wakeup Event by PM GPIO API"
-
-endchoice
-
-config PM_WAKEUP_SIC_IWR
- hex "Wakeup Events (SIC_IWR)"
- depends on PM_WAKEUP_GPIO_BY_SIC_IWR
- default 0x8 if (BF537 || BF536 || BF534)
- default 0x80 if (BF533 || BF532 || BF531)
- default 0x80 if (BF54x)
- default 0x80 if (BF52x)
config PM_WAKEUP_GPIO_NUMBER
int "Wakeup GPIO number"
config CPLB_INFO
bool "Display the CPLB information"
help
- Display the CPLB information.
+ Display the CPLB information via /proc/cplbinfo.
config ACCESS_CHECK
bool "Check the user pointer address"
$(Q)$(MAKE) $(clean)=$(boot)
+INSTALL_PATH ?= /tftpboot
boot := arch/$(ARCH)/boot
BOOT_TARGETS = vmImage
PHONY += $(BOOT_TARGETS) install
CONFIG_MEM_ADD_WIDTH=11
CONFIG_ENET_FLASH_PIN=0
CONFIG_BOOT_LOAD=0x1000
-
-
CONFIG_BFIN_SCRATCH_REG_RETN=y
# CONFIG_BFIN_SCRATCH_REG_RETE is not set
# CONFIG_BFIN_SCRATCH_REG_CYCLES is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
#
# User Modules And Translation Layers
#
# RAM/ROM/Flash chip drivers
#
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_CFI=m
+# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=m
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
-# CONFIG_MTD_CFI_AMDSTD is not set
+CONFIG_MTD_CFI_AMDSTD=m
# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=m
CONFIG_MTD_RAM=y
CONFIG_MTD_ROM=m
# CONFIG_MTD_ABSENT is not set
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_BF5xx=m
+CONFIG_BFIN_FLASH_BANK_0=0x7BB0
+CONFIG_BFIN_FLASH_BANK_1=0x7BB0
+CONFIG_BFIN_FLASH_BANK_2=0x7BB0
+CONFIG_BFIN_FLASH_BANK_3=0x7BB0
# CONFIG_MTD_UCLINUX is not set
# CONFIG_MTD_PLATRAM is not set
mutex_unlock(&(dma_ch[channel].dmalock));
+#ifdef CONFIG_BF54x
+ if (channel >= CH_UART2_RX && channel <= CH_UART3_TX &&
+ strncmp(device_id, "BFIN_UART", 9) == 0)
+ dma_ch[channel].regs->peripheral_map |=
+ (channel - CH_UART2_RX + 0xC);
+ else
+ dma_ch[channel].regs->peripheral_map |=
+ (channel - CH_UART2_RX + 0x6);
+#endif
+
dma_ch[channel].device_id = device_id;
dma_ch[channel].irq_callback = NULL;
char name[RESOURCE_LABEL_SIZE];
} str_ident[MAX_RESOURCES];
-#ifdef CONFIG_PM
+#if defined(CONFIG_PM) && !defined(CONFIG_BF54x)
static unsigned short wakeup_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
static unsigned char wakeup_flags_map[MAX_BLACKFIN_GPIOS];
static struct gpio_port_s gpio_bank_saved[gpio_bank(MAX_BLACKFIN_GPIOS)];
return 0;
}
-u32 gpio_pm_setup(void)
+u32 bfin_pm_setup(void)
{
- u32 sic_iwr = 0;
u16 bank, mask, i, gpio;
for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
gpio = i;
while (mask) {
- if (mask & 1) {
+ if ((mask & 1) && (wakeup_flags_map[gpio] !=
+ PM_WAKE_IGNORE)) {
reserved_gpio_map[gpio_bank(gpio)] |=
gpio_bit(gpio);
bfin_gpio_wakeup_type(gpio,
mask >>= 1;
}
- sic_iwr |= 1 <<
- (sic_iwr_irqs[bank] - (IRQ_CORETMR + 1));
+ bfin_internal_set_wake(sic_iwr_irqs[bank], 1);
gpio_bankb[bank]->maskb_set = wakeup_map[gpio_bank(i)];
}
}
AWA_DUMMY_READ(maskb_set);
- if (sic_iwr)
- return sic_iwr;
- else
- return IWR_ENABLE_ALL;
+ return 0;
}
-void gpio_pm_restore(void)
+void bfin_pm_restore(void)
{
u16 bank, mask, i;
reserved_gpio_map[bank] =
gpio_bank_saved[bank].reserved;
-
+ bfin_internal_set_wake(sic_iwr_irqs[bank], 0);
}
gpio_bankb[bank]->maskb = gpio_bank_saved[bank].maskb;
#include <asm/cplb.h>
#include <asm/cplbinit.h>
+#if ANOMALY_05000263
+# error the MPU will not function safely while Anomaly 05000263 applies
+#endif
+
struct cplb_entry icplb_tbl[MAX_CPLBS];
struct cplb_entry dcplb_tbl[MAX_CPLBS];
* "init_task" linker map entry.
*/
union thread_union init_thread_union
- __attribute__ ((__section__(".data.init_task"))) = {
+ __attribute__ ((__section__(".init_task.data"))) = {
INIT_THREAD_INFO(init_task)};
#include <linux/smp_lock.h>
#include <linux/unistd.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/uaccess.h>
#include <linux/fs.h>
#include <linux/err.h>
/*
- * File: arch/blackfin/kernel/setup.c
- * Based on:
- * Author:
+ * arch/blackfin/kernel/setup.c
*
- * Created:
- * Description:
+ * Copyright 2004-2006 Analog Devices Inc.
*
- * Modified:
- * Copyright 2004-2006 Analog Devices Inc.
+ * Enter bugs at http://blackfin.uclinux.org/
*
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * Licensed under the GPL-2 or later.
*/
#include <linux/delay.h>
#include <linux/cpu.h>
#include <linux/module.h>
#include <linux/tty.h>
+#include <linux/pfn.h>
#include <linux/ext2_fs.h>
#include <linux/cramfs_fs.h>
#include <asm/fixed_code.h>
#include <asm/early_printk.h>
+static DEFINE_PER_CPU(struct cpu, cpu_devices);
+
u16 _bfin_swrst;
unsigned long memory_start, memory_end, physical_mem_end;
char __initdata command_line[COMMAND_LINE_SIZE];
+/* boot memmap, for parsing "memmap=" */
+#define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
+#define BFIN_MEMMAP_RAM 1
+#define BFIN_MEMMAP_RESERVED 2
+struct bfin_memmap {
+ int nr_map;
+ struct bfin_memmap_entry {
+ unsigned long long addr; /* start of memory segment */
+ unsigned long long size;
+ unsigned long type;
+ } map[BFIN_MEMMAP_MAX];
+} bfin_memmap __initdata;
+
+/* for memmap sanitization */
+struct change_member {
+ struct bfin_memmap_entry *pentry; /* pointer to original entry */
+ unsigned long long addr; /* address for this change point */
+};
+static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
+static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
+static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
+static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
+
void __init bf53x_cache_init(void)
{
#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
}
+/* add_memory_region to memmap */
+static void __init add_memory_region(unsigned long long start,
+ unsigned long long size, int type)
+{
+ int i;
+
+ i = bfin_memmap.nr_map;
+
+ if (i == BFIN_MEMMAP_MAX) {
+ printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
+ return;
+ }
+
+ bfin_memmap.map[i].addr = start;
+ bfin_memmap.map[i].size = size;
+ bfin_memmap.map[i].type = type;
+ bfin_memmap.nr_map++;
+}
+
+/*
+ * Sanitize the boot memmap, removing overlaps.
+ */
+static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
+{
+ struct change_member *change_tmp;
+ unsigned long current_type, last_type;
+ unsigned long long last_addr;
+ int chgidx, still_changing;
+ int overlap_entries;
+ int new_entry;
+ int old_nr, new_nr, chg_nr;
+ int i;
+
+ /*
+ Visually we're performing the following (1,2,3,4 = memory types)
+
+ Sample memory map (w/overlaps):
+ ____22__________________
+ ______________________4_
+ ____1111________________
+ _44_____________________
+ 11111111________________
+ ____________________33__
+ ___________44___________
+ __________33333_________
+ ______________22________
+ ___________________2222_
+ _________111111111______
+ _____________________11_
+ _________________4______
+
+ Sanitized equivalent (no overlap):
+ 1_______________________
+ _44_____________________
+ ___1____________________
+ ____22__________________
+ ______11________________
+ _________1______________
+ __________3_____________
+ ___________44___________
+ _____________33_________
+ _______________2________
+ ________________1_______
+ _________________4______
+ ___________________2____
+ ____________________33__
+ ______________________4_
+ */
+ /* if there's only one memory region, don't bother */
+ if (*pnr_map < 2)
+ return -1;
+
+ old_nr = *pnr_map;
+
+ /* bail out if we find any unreasonable addresses in memmap */
+ for (i = 0; i < old_nr; i++)
+ if (map[i].addr + map[i].size < map[i].addr)
+ return -1;
+
+ /* create pointers for initial change-point information (for sorting) */
+ for (i = 0; i < 2*old_nr; i++)
+ change_point[i] = &change_point_list[i];
+
+ /* record all known change-points (starting and ending addresses),
+ omitting those that are for empty memory regions */
+ chgidx = 0;
+ for (i = 0; i < old_nr; i++) {
+ if (map[i].size != 0) {
+ change_point[chgidx]->addr = map[i].addr;
+ change_point[chgidx++]->pentry = &map[i];
+ change_point[chgidx]->addr = map[i].addr + map[i].size;
+ change_point[chgidx++]->pentry = &map[i];
+ }
+ }
+ chg_nr = chgidx; /* true number of change-points */
+
+ /* sort change-point list by memory addresses (low -> high) */
+ still_changing = 1;
+ while (still_changing) {
+ still_changing = 0;
+ for (i = 1; i < chg_nr; i++) {
+ /* if <current_addr> > <last_addr>, swap */
+ /* or, if current=<start_addr> & last=<end_addr>, swap */
+ if ((change_point[i]->addr < change_point[i-1]->addr) ||
+ ((change_point[i]->addr == change_point[i-1]->addr) &&
+ (change_point[i]->addr == change_point[i]->pentry->addr) &&
+ (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
+ ) {
+ change_tmp = change_point[i];
+ change_point[i] = change_point[i-1];
+ change_point[i-1] = change_tmp;
+ still_changing = 1;
+ }
+ }
+ }
+
+ /* create a new memmap, removing overlaps */
+ overlap_entries = 0; /* number of entries in the overlap table */
+ new_entry = 0; /* index for creating new memmap entries */
+ last_type = 0; /* start with undefined memory type */
+ last_addr = 0; /* start with 0 as last starting address */
+ /* loop through change-points, determining affect on the new memmap */
+ for (chgidx = 0; chgidx < chg_nr; chgidx++) {
+ /* keep track of all overlapping memmap entries */
+ if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
+ /* add map entry to overlap list (> 1 entry implies an overlap) */
+ overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
+ } else {
+ /* remove entry from list (order independent, so swap with last) */
+ for (i = 0; i < overlap_entries; i++) {
+ if (overlap_list[i] == change_point[chgidx]->pentry)
+ overlap_list[i] = overlap_list[overlap_entries-1];
+ }
+ overlap_entries--;
+ }
+ /* if there are overlapping entries, decide which "type" to use */
+ /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
+ current_type = 0;
+ for (i = 0; i < overlap_entries; i++)
+ if (overlap_list[i]->type > current_type)
+ current_type = overlap_list[i]->type;
+ /* continue building up new memmap based on this information */
+ if (current_type != last_type) {
+ if (last_type != 0) {
+ new_map[new_entry].size =
+ change_point[chgidx]->addr - last_addr;
+ /* move forward only if the new size was non-zero */
+ if (new_map[new_entry].size != 0)
+ if (++new_entry >= BFIN_MEMMAP_MAX)
+ break; /* no more space left for new entries */
+ }
+ if (current_type != 0) {
+ new_map[new_entry].addr = change_point[chgidx]->addr;
+ new_map[new_entry].type = current_type;
+ last_addr = change_point[chgidx]->addr;
+ }
+ last_type = current_type;
+ }
+ }
+ new_nr = new_entry; /* retain count for new entries */
+
+ /* copy new mapping into original location */
+ memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
+ *pnr_map = new_nr;
+
+ return 0;
+}
+
+static void __init print_memory_map(char *who)
+{
+ int i;
+
+ for (i = 0; i < bfin_memmap.nr_map; i++) {
+ printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
+ bfin_memmap.map[i].addr,
+ bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
+ switch (bfin_memmap.map[i].type) {
+ case BFIN_MEMMAP_RAM:
+ printk("(usable)\n");
+ break;
+ case BFIN_MEMMAP_RESERVED:
+ printk("(reserved)\n");
+ break;
+ default: printk("type %lu\n", bfin_memmap.map[i].type);
+ break;
+ }
+ }
+}
+
+static __init int parse_memmap(char *arg)
+{
+ unsigned long long start_at, mem_size;
+
+ if (!arg)
+ return -EINVAL;
+
+ mem_size = memparse(arg, &arg);
+ if (*arg == '@') {
+ start_at = memparse(arg+1, &arg);
+ add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
+ } else if (*arg == '$') {
+ start_at = memparse(arg+1, &arg);
+ add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
+ }
+
+ return 0;
+}
+
/*
* Initial parsing of the command line. Currently, we support:
* - Controlling the linux memory size: mem=xxx[KMG]
* - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
* $ -> reserved memory is dcacheable
* # -> reserved memory is icacheable
+ * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
+ * @ from <start> to <start>+<mem>, type RAM
+ * $ from <start> to <start>+<mem>, type RESERVED
+ *
*/
static __init void parse_cmdline_early(char *cmdline_p)
{
unsigned int memsize;
for (;;) {
if (c == ' ') {
-
if (!memcmp(to, "mem=", 4)) {
to += 4;
memsize = memparse(to, &to);
} else if (!memcmp(to, "earlyprintk=", 12)) {
to += 12;
setup_early_printk(to);
+ } else if (!memcmp(to, "memmap=", 7)) {
+ to += 7;
+ parse_memmap(to);
}
}
c = *(to++);
}
}
-void __init setup_arch(char **cmdline_p)
+/*
+ * Setup memory defaults from user config.
+ * The physical memory layout looks like:
+ *
+ * [_rambase, _ramstart]: kernel image
+ * [memory_start, memory_end]: dynamic memory managed by kernel
+ * [memory_end, _ramend]: reserved memory
+ * [meory_mtd_start(memory_end),
+ * memory_mtd_start + mtd_size]: rootfs (if any)
+ * [_ramend - DMA_UNCACHED_REGION,
+ * _ramend]: uncached DMA region
+ * [_ramend, physical_mem_end]: memory not managed by kernel
+ *
+ */
+static __init void memory_setup(void)
{
- int bootmap_size;
- unsigned long l1_length, sclk, cclk;
#ifdef CONFIG_MTD_UCLINUX
unsigned long mtd_phys = 0;
#endif
-#ifdef CONFIG_DUMMY_CONSOLE
- conswitchp = &dummy_con;
-#endif
-
-#if defined(CONFIG_CMDLINE_BOOL)
- strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
- command_line[sizeof(command_line) - 1] = 0;
-#endif
-
- /* Keep a copy of command line */
- *cmdline_p = &command_line[0];
- memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
- boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
-
- /* setup memory defaults from the user config */
- physical_mem_end = 0;
- _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
-
- parse_cmdline_early(&command_line[0]);
-
- cclk = get_cclk();
- sclk = get_sclk();
-
-#if !defined(CONFIG_BFIN_KERNEL_CLOCK)
- if (ANOMALY_05000273 && cclk == sclk)
- panic("ANOMALY 05000273, SCLK can not be same as CCLK");
-#endif
+ _rambase = (unsigned long)_stext;
+ _ramstart = (unsigned long)_end;
-#ifdef BF561_FAMILY
- if (ANOMALY_05000266) {
- bfin_read_IMDMA_D0_IRQ_STATUS();
- bfin_read_IMDMA_D1_IRQ_STATUS();
+ if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
+ console_init();
+ panic("DMA region exceeds memory limit: %lu.\n",
+ _ramend - _ramstart);
}
-#endif
-
- printk(KERN_INFO "Hardware Trace ");
- if (bfin_read_TBUFCTL() & 0x1 )
- printk("Active ");
- else
- printk("Off ");
- if (bfin_read_TBUFCTL() & 0x2)
- printk("and Enabled\n");
- else
- printk("and Disabled\n");
-
-
-#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
- /* we need to initialize the Flashrom device here since we might
- * do things with flash early on in the boot
- */
- flash_probe();
-#endif
-
- if (physical_mem_end == 0)
- physical_mem_end = _ramend;
-
- /* by now the stack is part of the init task */
memory_end = _ramend - DMA_UNCACHED_REGION;
- _ramstart = (unsigned long)__bss_stop;
- _rambase = (unsigned long)_stext;
#ifdef CONFIG_MPU
/* Round up to multiple of 4MB. */
memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
}
/* Relocate MTD image to the top of memory after the uncached memory area */
- dma_memcpy((char *)memory_end, __bss_stop, mtd_size);
+ dma_memcpy((char *)memory_end, _end, mtd_size);
memory_mtd_start = memory_end;
_ebss = memory_mtd_start; /* define _ebss for compatible */
#endif
#if !defined(CONFIG_MTD_UCLINUX)
- memory_end -= SIZE_4K; /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
+ /*In case there is no valid CPLB behind memory_end make sure we don't get to close*/
+ memory_end -= SIZE_4K;
#endif
+
init_mm.start_code = (unsigned long)_stext;
init_mm.end_code = (unsigned long)_etext;
init_mm.end_data = (unsigned long)_edata;
init_mm.brk = (unsigned long)0;
+ printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
+ printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
+
+ printk(KERN_INFO "Memory map:\n"
+ KERN_INFO " text = 0x%p-0x%p\n"
+ KERN_INFO " rodata = 0x%p-0x%p\n"
+ KERN_INFO " bss = 0x%p-0x%p\n"
+ KERN_INFO " data = 0x%p-0x%p\n"
+ KERN_INFO " stack = 0x%p-0x%p\n"
+ KERN_INFO " init = 0x%p-0x%p\n"
+ KERN_INFO " available = 0x%p-0x%p\n"
+#ifdef CONFIG_MTD_UCLINUX
+ KERN_INFO " rootfs = 0x%p-0x%p\n"
+#endif
+#if DMA_UNCACHED_REGION > 0
+ KERN_INFO " DMA Zone = 0x%p-0x%p\n"
+#endif
+ , _stext, _etext,
+ __start_rodata, __end_rodata,
+ __bss_start, __bss_stop,
+ _sdata, _edata,
+ (void *)&init_thread_union,
+ (void *)((int)(&init_thread_union) + 0x2000),
+ __init_begin, __init_end,
+ (void *)_ramstart, (void *)memory_end
+#ifdef CONFIG_MTD_UCLINUX
+ , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
+#endif
+#if DMA_UNCACHED_REGION > 0
+ , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
+#endif
+ );
+}
+
+static __init void setup_bootmem_allocator(void)
+{
+ int bootmap_size;
+ int i;
+ unsigned long min_pfn, max_pfn;
+ unsigned long curr_pfn, last_pfn, size;
+
+ /* mark memory between memory_start and memory_end usable */
+ add_memory_region(memory_start,
+ memory_end - memory_start, BFIN_MEMMAP_RAM);
+ /* sanity check for overlap */
+ sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
+ print_memory_map("boot memmap");
+
+ min_pfn = PAGE_OFFSET >> PAGE_SHIFT;
+ max_pfn = memory_end >> PAGE_SHIFT;
+
+ /*
+ * give all the memory to the bootmap allocator, tell it to put the
+ * boot mem_map at the start of memory.
+ */
+ bootmap_size = init_bootmem_node(NODE_DATA(0),
+ memory_start >> PAGE_SHIFT, /* map goes here */
+ min_pfn, max_pfn);
+
+ /* register the memmap regions with the bootmem allocator */
+ for (i = 0; i < bfin_memmap.nr_map; i++) {
+ /*
+ * Reserve usable memory
+ */
+ if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
+ continue;
+ /*
+ * We are rounding up the start address of usable memory:
+ */
+ curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
+ if (curr_pfn >= max_pfn)
+ continue;
+ /*
+ * ... and at the end of the usable range downwards:
+ */
+ last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
+ bfin_memmap.map[i].size);
+
+ if (last_pfn > max_pfn)
+ last_pfn = max_pfn;
+
+ /*
+ * .. finally, did all the rounding and playing
+ * around just make the area go away?
+ */
+ if (last_pfn <= curr_pfn)
+ continue;
+
+ size = last_pfn - curr_pfn;
+ free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
+ }
+
+ /* reserve memory before memory_start, including bootmap */
+ reserve_bootmem(PAGE_OFFSET,
+ memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
+ BOOTMEM_DEFAULT);
+}
+
+void __init setup_arch(char **cmdline_p)
+{
+ unsigned long l1_length, sclk, cclk;
+
+#ifdef CONFIG_DUMMY_CONSOLE
+ conswitchp = &dummy_con;
+#endif
+
+#if defined(CONFIG_CMDLINE_BOOL)
+ strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
+ command_line[sizeof(command_line) - 1] = 0;
+#endif
+
+ /* Keep a copy of command line */
+ *cmdline_p = &command_line[0];
+ memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
+ boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
+
+ /* setup memory defaults from the user config */
+ physical_mem_end = 0;
+ _ramend = CONFIG_MEM_SIZE * 1024 * 1024;
+
+ memset(&bfin_memmap, 0, sizeof(bfin_memmap));
+
+ parse_cmdline_early(&command_line[0]);
+
+ if (physical_mem_end == 0)
+ physical_mem_end = _ramend;
+
+ memory_setup();
+
+ cclk = get_cclk();
+ sclk = get_sclk();
+
+#if !defined(CONFIG_BFIN_KERNEL_CLOCK)
+ if (ANOMALY_05000273 && cclk == sclk)
+ panic("ANOMALY 05000273, SCLK can not be same as CCLK");
+#endif
+
+#ifdef BF561_FAMILY
+ if (ANOMALY_05000266) {
+ bfin_read_IMDMA_D0_IRQ_STATUS();
+ bfin_read_IMDMA_D1_IRQ_STATUS();
+ }
+#endif
+ printk(KERN_INFO "Hardware Trace ");
+ if (bfin_read_TBUFCTL() & 0x1)
+ printk("Active ");
+ else
+ printk("Off ");
+ if (bfin_read_TBUFCTL() & 0x2)
+ printk("and Enabled\n");
+ else
+ printk("and Disabled\n");
+
+#if defined(CONFIG_CHR_DEV_FLASH) || defined(CONFIG_BLK_DEV_FLASH)
+ /* we need to initialize the Flashrom device here since we might
+ * do things with flash early on in the boot
+ */
+ flash_probe();
+#endif
+
_bfin_swrst = bfin_read_SWRST();
if (_bfin_swrst & RESET_DOUBLE)
else if (_bfin_swrst & RESET_SOFTWARE)
printk(KERN_NOTICE "Reset caused by Software reset\n");
- printk(KERN_INFO "Blackfin support (C) 2004-2007 Analog Devices, Inc.\n");
+ printk(KERN_INFO "Blackfin support (C) 2004-2008 Analog Devices, Inc.\n");
if (bfin_compiled_revid() == 0xffff)
printk(KERN_INFO "Compiled for ADSP-%s Rev any\n", CPU);
else if (bfin_compiled_revid() == -1)
if (ANOMALY_05000273 && (cclk >> 1) <= sclk)
printk("\n\n\nANOMALY_05000273: CCLK must be >= 2*SCLK !!!\n\n\n");
- printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
- printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
-
- printk(KERN_INFO "Memory map:\n"
- KERN_INFO " text = 0x%p-0x%p\n"
- KERN_INFO " rodata = 0x%p-0x%p\n"
- KERN_INFO " data = 0x%p-0x%p\n"
- KERN_INFO " stack = 0x%p-0x%p\n"
- KERN_INFO " init = 0x%p-0x%p\n"
- KERN_INFO " bss = 0x%p-0x%p\n"
- KERN_INFO " available = 0x%p-0x%p\n"
-#ifdef CONFIG_MTD_UCLINUX
- KERN_INFO " rootfs = 0x%p-0x%p\n"
-#endif
-#if DMA_UNCACHED_REGION > 0
- KERN_INFO " DMA Zone = 0x%p-0x%p\n"
-#endif
- , _stext, _etext,
- __start_rodata, __end_rodata,
- _sdata, _edata,
- (void *)&init_thread_union, (void *)((int)(&init_thread_union) + 0x2000),
- __init_begin, __init_end,
- __bss_start, __bss_stop,
- (void *)_ramstart, (void *)memory_end
-#ifdef CONFIG_MTD_UCLINUX
- , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
-#endif
-#if DMA_UNCACHED_REGION > 0
- , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
-#endif
- );
+ setup_bootmem_allocator();
- /*
- * give all the memory to the bootmap allocator, tell it to put the
- * boot mem_map at the start of memory
- */
- bootmap_size = init_bootmem_node(NODE_DATA(0), memory_start >> PAGE_SHIFT, /* map goes here */
- PAGE_OFFSET >> PAGE_SHIFT,
- memory_end >> PAGE_SHIFT);
- /*
- * free the usable memory, we have to make sure we do not free
- * the bootmem bitmap so we then reserve it after freeing it :-)
- */
- free_bootmem(memory_start, memory_end - memory_start);
-
- reserve_bootmem(memory_start, bootmap_size, BOOTMEM_DEFAULT);
- /*
- * get kmalloc into gear
- */
paging_init();
/* check the size of the l1 area */
static int __init topology_init(void)
{
-#if defined (CONFIG_BF561)
- static struct cpu cpu[2];
- register_cpu(&cpu[0], 0);
- register_cpu(&cpu[1], 1);
+ int cpu;
+
+ for_each_possible_cpu(cpu) {
+ struct cpu *c = &per_cpu(cpu_devices, cpu);
+
+ register_cpu(c, cpu);
+ }
+
return 0;
-#else
- static struct cpu cpu[1];
- return register_cpu(cpu, 0);
-#endif
}
subsys_initcall(topology_init);
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
if (context & 0x0020 && (fp->seqstat & SEQSTAT_EXCAUSE) == VEC_HWERR)
printk(KERN_NOTICE "HW Error context\n");
else if (context & 0x0020)
- printk(KERN_NOTICE "Defered Exception context\n");
+ printk(KERN_NOTICE "Deferred Exception context\n");
else if (context & 0x3FC0)
printk(KERN_NOTICE "Interrupt context\n");
else if (context & 0x4000)
SECTIONS
{
. = CONFIG_BOOT_LOAD;
+ /* Neither the text, ro_data or bss section need to be aligned
+ * So pack them back to back
+ */
.text :
{
__text = .;
*(__ex_table)
___stop___ex_table = .;
- . = ALIGN(4);
__etext = .;
}
- RO_DATA(PAGE_SIZE)
+ /* Just in case the first read only is a 32-bit access */
+ RO_DATA(4)
+
+ .bss :
+ {
+ . = ALIGN(4);
+ ___bss_start = .;
+ *(.bss .bss.*)
+ *(COMMON)
+ ___bss_stop = .;
+ }
.data :
{
- /* make sure the init_task is aligned to the
- * kernel thread size so we can locate the kernel
- * stack properly and quickly.
- */
__sdata = .;
- . = ALIGN(THREAD_SIZE);
- *(.data.init_task)
-
+ /* This gets done first, so the glob doesn't suck it in */
. = ALIGN(32);
*(.data.cacheline_aligned)
*(.data.*)
CONSTRUCTORS
+ /* make sure the init_task is aligned to the
+ * kernel thread size so we can locate the kernel
+ * stack properly and quickly.
+ */
. = ALIGN(THREAD_SIZE);
+ *(.init_task.data)
+
__edata = .;
}
+ /* The init section should be last, so when we free it, it goes into
+ * the general memory pool, and (hopefully) will decrease fragmentation
+ * a tiny bit. The init section has a _requirement_ that it be
+ * PAGE_SIZE aligned
+ */
+ . = ALIGN(PAGE_SIZE);
___init_begin = .;
.init.text :
. = ALIGN(PAGE_SIZE);
___init_end = .;
- .bss :
- {
- . = ALIGN(4);
- ___bss_start = .;
- *(.bss .bss.*)
- *(COMMON)
- . = ALIGN(4);
- ___bss_stop = .;
- __end = .;
- }
+ __end =.;
STABS_DEBUG
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/usb/sl811.h>
+#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
#include <linux/usb/musb.h>
+#endif
#include <asm/cplb.h>
#include <asm/dma.h>
#include <asm/bfin5xx_spi.h>
.bits_per_word = 16,
};
#endif
+
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct bfin5xx_spi_chip spidev_chip_info = {
+ .enable_dma = 0,
+ .bits_per_word = 8,
+};
+#endif
+
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
.mode = SPI_MODE_0,
},
#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+ {
+ .modalias = "spidev",
+ .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
+ .bus_num = 0,
+ .chip_select = 1,
+ .controller_data = &spidev_chip_info,
+ },
+#endif
};
/* SPI controller data */
#include <linux/mtd/partitions.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
+#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
#include <linux/usb/isp1362.h>
+#endif
#include <linux/ata_platform.h>
#include <linux/irq.h>
#include <asm/dma.h>
};
#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct bfin5xx_spi_chip spidev_chip_info = {
+ .enable_dma = 0,
+ .bits_per_word = 8,
+};
+#endif
+
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
{
.controller_data = &ad1836_spi_chip_info,
},
#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+ {
+ .modalias = "spidev",
+ .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
+ .bus_num = 0,
+ .chip_select = 1,
+ .controller_data = &spidev_chip_info,
+ },
+#endif
};
/* SPI (0) */
};
#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct bfin5xx_spi_chip spidev_chip_info = {
+ .enable_dma = 0,
+ .bits_per_word = 8,
+};
+#endif
+
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
{
.mode = SPI_MODE_2,
},
#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+ {
+ .modalias = "spidev",
+ .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
+ .bus_num = 0,
+ .chip_select = 1,
+ .controller_data = &spidev_chip_info,
+ },
+#endif
};
/* SPI (0) */
#include <linux/gpio_keys.h>
static struct gpio_keys_button bfin_gpio_keys_table[] = {
- {BTN_0, GPIO_PF5, 1, "gpio-keys: BTN0"},
- {BTN_1, GPIO_PF6, 1, "gpio-keys: BTN1"},
- {BTN_2, GPIO_PF8, 1, "gpio-keys: BTN2"},
+ {BTN_0, GPIO_PF5, 0, "gpio-keys: BTN0"},
+ {BTN_1, GPIO_PF6, 0, "gpio-keys: BTN1"},
+ {BTN_2, GPIO_PF8, 0, "gpio-keys: BTN2"},
};
static struct gpio_keys_platform_data bfin_gpio_keys_data = {
};
#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct bfin5xx_spi_chip spidev_chip_info = {
+ .enable_dma = 0,
+ .bits_per_word = 8,
+};
+#endif
+
static struct spi_board_info bfin_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
.controller_data = &spi_ad7877_chip_info,
},
#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+ {
+ .modalias = "spidev",
+ .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
+ .bus_num = 0,
+ .chip_select = 1,
+ .controller_data = &spidev_chip_info,
+ },
+#endif
};
/* SPI controller data */
#include <linux/spi/flash.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
+#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
#include <linux/usb/musb.h>
+#endif
#include <asm/bfin5xx_spi.h>
#include <asm/cplb.h>
#include <asm/dma.h>
};
#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct bfin5xx_spi_chip spidev_chip_info = {
+ .enable_dma = 0,
+ .bits_per_word = 8,
+};
+#endif
+
static struct spi_board_info bf54x_spi_board_info[] __initdata = {
#if defined(CONFIG_MTD_M25P80) \
|| defined(CONFIG_MTD_M25P80_MODULE)
.controller_data = &spi_ad7877_chip_info,
},
#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+ {
+ .modalias = "spidev",
+ .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
+ .bus_num = 0,
+ .chip_select = 1,
+ .controller_data = &spidev_chip_info,
+ },
+#endif
};
/* SPI (0) */
&ezkit_flash_device,
};
-static int __init stamp_init(void)
+static int __init ezkit_init(void)
{
printk(KERN_INFO "%s(): registering device resources\n", __FUNCTION__);
platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices));
return 0;
}
-arch_initcall(stamp_init);
+arch_initcall(ezkit_init);
/*
- * File: arch/blackfin/mach-bf561/dma.c
+ * File: arch/blackfin/mach-bf548/dma.c
* Based on:
* Author:
*
* Description: This file contains the simple DMA Implementation for Blackfin
*
* Modified:
- * Copyright 2004-2007 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
arch_initcall(bfin_isp1761_init);
#endif
+#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+#include <linux/usb/isp1362.h>
+
+static struct resource isp1362_hcd_resources[] = {
+ {
+ .start = 0x2c060000,
+ .end = 0x2c060000,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = 0x2c060004,
+ .end = 0x2c060004,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_PF8,
+ .end = IRQ_PF8,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct isp1362_platform_data isp1362_priv = {
+ .sel15Kres = 1,
+ .clknotstop = 0,
+ .oc_enable = 0,
+ .int_act_high = 0,
+ .int_edge_triggered = 0,
+ .remote_wakeup_connected = 0,
+ .no_power_switching = 1,
+ .power_switching_mode = 0,
+};
+
+static struct platform_device isp1362_hcd_device = {
+ .name = "isp1362-hcd",
+ .id = 0,
+ .dev = {
+ .platform_data = &isp1362_priv,
+ },
+ .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
+ .resource = isp1362_hcd_resources,
+};
+#endif
+
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+static struct resource net2272_bfin_resources[] = {
+ {
+ .start = 0x2C000000,
+ .end = 0x2C000000 + 0x7F,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_PF10,
+ .end = IRQ_PF10,
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+ },
+};
+
+static struct platform_device net2272_bfin_device = {
+ .name = "net2272",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(net2272_bfin_resources),
+ .resource = net2272_bfin_resources,
+};
+#endif
+
/*
* USB-LAN EzExtender board
* Driver needs to know address, irq and flag pin.
.bits_per_word = 16,
};
#endif
+
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+static struct bfin5xx_spi_chip spidev_chip_info = {
+ .enable_dma = 0,
+ .bits_per_word = 8,
+};
+#endif
#endif
/* SPI (0) */
.controller_data = &ad1836_spi_chip_info,
},
#endif
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+ {
+ .modalias = "spidev",
+ .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
+ .bus_num = 0,
+ .chip_select = 1,
+ .controller_data = &spidev_chip_info,
+ },
+#endif
};
#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
&ax88180_device,
#endif
+#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
+ &net2272_bfin_device,
+#endif
+
#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
&bfin_spi0_device,
#endif
#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
&i2c_gpio_device,
#endif
+
+#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
+ &isp1362_hcd_device,
+#endif
+
&ezkit_flash_device,
};
obj-y := \
cache.o cacheinit.o entry.o \
- interrupt.o lock.o irqpanic.o arch_checks.o
+ interrupt.o lock.o irqpanic.o arch_checks.o ints-priority.o
-obj-$(CONFIG_BFIN_SINGLE_CORE) += ints-priority-sc.o
-obj-$(CONFIG_BFIN_DUAL_CORE) += ints-priority-dc.o
obj-$(CONFIG_PM) += pm.o dpmc.o
call _test_pll_locked;
R0 = IWR_ENABLE(0);
+ R1 = IWR_DISABLE_ALL;
+ R2 = IWR_DISABLE_ALL;
+
call _set_sic_iwr;
P0.H = hi(PLL_CTL);
CLI R4;
+ R0 = IWR_ENABLE(0);
+ R1 = IWR_DISABLE_ALL;
+ R2 = IWR_DISABLE_ALL;
+
call _set_sic_iwr;
call _set_dram_srfs;
call _test_pll_locked;
R0 = IWR_ENABLE(0);
+ R1 = IWR_DISABLE_ALL;
+ R2 = IWR_DISABLE_ALL;
+
call _set_sic_iwr;
P0.H = hi(PLL_CTL);
CLI R4;
P3 = R0;
+ P4 = R1;
+ P5 = R2;
+
R0 = IWR_ENABLE(0);
+ R1 = IWR_DISABLE_ALL;
+ R2 = IWR_DISABLE_ALL;
+
call _set_sic_iwr;
call _set_dram_srfs; /* Set SDRAM Self Refresh */
call _test_pll_locked;
R0 = P3;
+ R1 = P4;
+ R3 = P5;
call _set_sic_iwr; /* Set Awake from IDLE */
P0.H = hi(PLL_CTL);
call _test_pll_locked;
R0 = IWR_ENABLE(0);
+ R1 = IWR_DISABLE_ALL;
+ R2 = IWR_DISABLE_ALL;
+
call _set_sic_iwr; /* Set Awake from IDLE PLL */
P0.H = hi(VR_CTL);
RTS;
ENTRY(_set_sic_iwr)
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
P0.H = hi(SIC_IWR0);
P0.L = lo(SIC_IWR0);
+ P1.H = hi(SIC_IWR1);
+ P1.L = lo(SIC_IWR1);
+ [P1] = R1;
+#if defined(CONFIG_BF54x)
+ P1.H = hi(SIC_IWR2);
+ P1.L = lo(SIC_IWR2);
+ [P1] = R2;
+#endif
#else
P0.H = hi(SIC_IWR);
P0.L = lo(SIC_IWR);
#endif
[P0] = R0;
+
SSYNC;
RTS;
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
SAVE_ALL_SYS
+ DEBUG_HWTRACE_SAVE(p5, r7)
#ifdef CONFIG_MPU
R0 = SEQSTAT;
R1 = SP;
#else
call __cplb_hdr;
#endif
- DEBUG_START_HWTRACE(p5, r7)
+ DEBUG_HWTRACE_RESTORE(p5, r7)
RESTORE_ALL_SYS
SP = EX_SCRATCH_REG;
rtx;
ENDPROC(_ex_icplb_miss)
ENTRY(_ex_syscall)
- DEBUG_START_HWTRACE(p5, r7)
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
raise 15; /* invoked by TRAP #0, for sys call */
ENDPROC(_ex_single_step)
ENTRY(_bfin_return_from_exception)
- DEBUG_START_HWTRACE(p5, r7)
#if ANOMALY_05000257
R7=LC0;
LC0=R7;
* need to make a CPLB exception look like a normal exception
*/
- DEBUG_START_HWTRACE(p5, r7)
RESTORE_ALL_SYS
[--sp] = ASTAT;
- [--sp] = (R7:6, P5:4);
+ [--sp] = (R7:6,P5:4);
ENTRY(_ex_replaceable)
nop;
R6 = SEQSTAT;
[P5] = R6;
- DEBUG_START_HWTRACE(p5, r7)
(R7:6,P5:4) = [sp++];
ASTAT = [sp++];
SP = EX_SCRATCH_REG;
sp.h = _exception_stack_top;
/* Try to deal with syscalls quickly. */
[--sp] = ASTAT;
- [--sp] = (R7:6, P5:4);
- DEBUG_STOP_HWTRACE(p5, r7)
+ [--sp] = (R7:6,P5:4);
r7 = SEQSTAT; /* reason code is in bit 5:0 */
r6.l = lo(SEQSTAT_EXCAUSE);
r6.h = hi(SEQSTAT_EXCAUSE);
+++ /dev/null
-/*
- * File: arch/blackfin/mach-common/ints-priority-dc.c
- * Based on:
- * Author:
- *
- * Created: ?
- * Description: Set up the interrupt priorities
- *
- * Modified:
- * 1996 Roman Zippel
- * 1999 D. Jeff Dionne <jeff@uclinux.org>
- * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * 2003 Metrowerks/Motorola
- * 2003 Bas Vermeulen <bas@buyways.nl>
- * Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <linux/module.h>
-#include <linux/kernel_stat.h>
-#include <linux/seq_file.h>
-#include <linux/irq.h>
-#ifdef CONFIG_KGDB
-#include <linux/kgdb.h>
-#endif
-#include <asm/traps.h>
-#include <asm/blackfin.h>
-#include <asm/gpio.h>
-#include <asm/irq_handler.h>
-
-/*
- * NOTES:
- * - we have separated the physical Hardware interrupt from the
- * levels that the LINUX kernel sees (see the description in irq.h)
- * -
- */
-
-/* Initialize this to an actual value to force it into the .data
- * section so that we know it is properly initialized at entry into
- * the kernel but before bss is initialized to zero (which is where
- * it would live otherwise). The 0x1f magic represents the IRQs we
- * cannot actually mask out in hardware.
- */
-unsigned long irq_flags = 0x1f;
-
-/* The number of spurious interrupts */
-atomic_t num_spurious;
-
-struct ivgx {
- /* irq number for request_irq, available in mach-bf561/irq.h */
- int irqno;
- /* corresponding bit in the SICA_ISR0 register */
- int isrflag0;
- /* corresponding bit in the SICA_ISR1 register */
- int isrflag1;
-} ivg_table[NR_PERI_INTS];
-
-struct ivg_slice {
- /* position of first irq in ivg_table for given ivg */
- struct ivgx *ifirst;
- struct ivgx *istop;
-} ivg7_13[IVG13 - IVG7 + 1];
-
-static void search_IAR(void);
-
-/*
- * Search SIC_IAR and fill tables with the irqvalues
- * and their positions in the SIC_ISR register.
- */
-static void __init search_IAR(void)
-{
- unsigned ivg, irq_pos = 0;
- for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
- int irqn;
-
- ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
-
- for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
- int iar_shift = (irqn & 7) * 4;
- if (ivg ==
- (0xf &
- bfin_read32((unsigned long *)SICA_IAR0 +
- (irqn >> 3)) >> iar_shift)) {
- ivg_table[irq_pos].irqno = IVG7 + irqn;
- ivg_table[irq_pos].isrflag0 =
- (irqn < 32 ? (1 << irqn) : 0);
- ivg_table[irq_pos].isrflag1 =
- (irqn < 32 ? 0 : (1 << (irqn - 32)));
- ivg7_13[ivg].istop++;
- irq_pos++;
- }
- }
- }
-}
-
-/*
- * This is for BF561 internal IRQs
- */
-
-static void ack_noop(unsigned int irq)
-{
- /* Dummy function. */
-}
-
-static void bf561_core_mask_irq(unsigned int irq)
-{
- irq_flags &= ~(1 << irq);
- if (!irqs_disabled())
- local_irq_enable();
-}
-
-static void bf561_core_unmask_irq(unsigned int irq)
-{
- irq_flags |= 1 << irq;
- /*
- * If interrupts are enabled, IMASK must contain the same value
- * as irq_flags. Make sure that invariant holds. If interrupts
- * are currently disabled we need not do anything; one of the
- * callers will take care of setting IMASK to the proper value
- * when reenabling interrupts.
- * local_irq_enable just does "STI irq_flags", so it's exactly
- * what we need.
- */
- if (!irqs_disabled())
- local_irq_enable();
- return;
-}
-
-static void bf561_internal_mask_irq(unsigned int irq)
-{
- unsigned long irq_mask;
- if ((irq - (IRQ_CORETMR + 1)) < 32) {
- irq_mask = (1 << (irq - (IRQ_CORETMR + 1)));
- bfin_write_SICA_IMASK0(bfin_read_SICA_IMASK0() & ~irq_mask);
- } else {
- irq_mask = (1 << (irq - (IRQ_CORETMR + 1) - 32));
- bfin_write_SICA_IMASK1(bfin_read_SICA_IMASK1() & ~irq_mask);
- }
-}
-
-static void bf561_internal_unmask_irq(unsigned int irq)
-{
- unsigned long irq_mask;
-
- if ((irq - (IRQ_CORETMR + 1)) < 32) {
- irq_mask = (1 << (irq - (IRQ_CORETMR + 1)));
- bfin_write_SICA_IMASK0(bfin_read_SICA_IMASK0() | irq_mask);
- } else {
- irq_mask = (1 << (irq - (IRQ_CORETMR + 1) - 32));
- bfin_write_SICA_IMASK1(bfin_read_SICA_IMASK1() | irq_mask);
- }
- SSYNC();
-}
-
-static struct irq_chip bf561_core_irqchip = {
- .ack = ack_noop,
- .mask = bf561_core_mask_irq,
- .unmask = bf561_core_unmask_irq,
-};
-
-static struct irq_chip bf561_internal_irqchip = {
- .ack = ack_noop,
- .mask = bf561_internal_mask_irq,
- .unmask = bf561_internal_unmask_irq,
-};
-
-static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
-static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
-
-static void bf561_gpio_ack_irq(unsigned int irq)
-{
- u16 gpionr = irq - IRQ_PF0;
-
- if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
- set_gpio_data(gpionr, 0);
- SSYNC();
- }
-}
-
-static void bf561_gpio_mask_ack_irq(unsigned int irq)
-{
- u16 gpionr = irq - IRQ_PF0;
-
- if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
- set_gpio_data(gpionr, 0);
- SSYNC();
- }
-
- set_gpio_maska(gpionr, 0);
- SSYNC();
-}
-
-static void bf561_gpio_mask_irq(unsigned int irq)
-{
- set_gpio_maska(irq - IRQ_PF0, 0);
- SSYNC();
-}
-
-static void bf561_gpio_unmask_irq(unsigned int irq)
-{
- set_gpio_maska(irq - IRQ_PF0, 1);
- SSYNC();
-}
-
-static unsigned int bf561_gpio_irq_startup(unsigned int irq)
-{
- unsigned int ret;
- char buf[8];
- u16 gpionr = irq - IRQ_PF0;
-
- if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
- snprintf(buf, sizeof buf, "IRQ %d", irq);
- ret = gpio_request(gpionr, buf);
- if (ret)
- return ret;
-
- }
-
- gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
- bf561_gpio_unmask_irq(irq);
-
- return ret;
-
-}
-
-static void bf561_gpio_irq_shutdown(unsigned int irq)
-{
- bf561_gpio_mask_irq(irq);
- gpio_free(irq - IRQ_PF0);
- gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
-}
-
-static int bf561_gpio_irq_type(unsigned int irq, unsigned int type)
-{
-
- unsigned int ret;
- char buf[8];
- u16 gpionr = irq - IRQ_PF0;
-
-
- if (type == IRQ_TYPE_PROBE) {
- /* only probe unenabled GPIO interrupt lines */
- if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
- return 0;
- type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
-
- }
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
- IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-
- if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
- snprintf(buf, sizeof buf, "IRQ %d", irq);
- ret = gpio_request(gpionr, buf);
- if (ret)
- return ret;
-
- }
-
- gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
- } else {
- gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
- return 0;
- }
-
-
- set_gpio_dir(gpionr, 0);
- set_gpio_inen(gpionr, 1);
-
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
- gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
- set_gpio_edge(gpionr, 1);
- } else {
- set_gpio_edge(gpionr, 0);
- gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
- }
-
- if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- set_gpio_both(gpionr, 1);
- else
- set_gpio_both(gpionr, 0);
-
- if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
- set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
- else
- set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
-
- SSYNC();
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- set_irq_handler(irq, handle_edge_irq);
- else
- set_irq_handler(irq, handle_level_irq);
-
- return 0;
-}
-
-static struct irq_chip bf561_gpio_irqchip = {
- .ack = bf561_gpio_ack_irq,
- .mask = bf561_gpio_mask_irq,
- .mask_ack = bf561_gpio_mask_ack_irq,
- .unmask = bf561_gpio_unmask_irq,
- .set_type = bf561_gpio_irq_type,
- .startup = bf561_gpio_irq_startup,
- .shutdown = bf561_gpio_irq_shutdown
-};
-
-static void bf561_demux_gpio_irq(unsigned int inta_irq,
- struct irq_desc *intb_desc)
-{
- int irq, flag_d, mask;
- u16 gpio;
-
- switch (inta_irq) {
- case IRQ_PROG0_INTA:
- irq = IRQ_PF0;
- break;
- case IRQ_PROG1_INTA:
- irq = IRQ_PF16;
- break;
- case IRQ_PROG2_INTA:
- irq = IRQ_PF32;
- break;
- default:
- dump_stack();
- return;
- }
-
- gpio = irq - IRQ_PF0;
-
- flag_d = get_gpiop_data(gpio);
- mask = flag_d & (gpio_enabled[gpio_bank(gpio)] &
- get_gpiop_maska(gpio));
-
- do {
- if (mask & 1) {
- struct irq_desc *desc = irq_desc + irq;
- desc->handle_irq(irq, desc);
- }
- irq++;
- mask >>= 1;
- } while (mask);
-
-
-}
-
-void __init init_exception_vectors(void)
-{
- SSYNC();
-
- /* cannot program in software:
- * evt0 - emulation (jtag)
- * evt1 - reset
- */
- bfin_write_EVT2(evt_nmi);
- bfin_write_EVT3(trap);
- bfin_write_EVT5(evt_ivhw);
- bfin_write_EVT6(evt_timer);
- bfin_write_EVT7(evt_evt7);
- bfin_write_EVT8(evt_evt8);
- bfin_write_EVT9(evt_evt9);
- bfin_write_EVT10(evt_evt10);
- bfin_write_EVT11(evt_evt11);
- bfin_write_EVT12(evt_evt12);
- bfin_write_EVT13(evt_evt13);
- bfin_write_EVT14(evt14_softirq);
- bfin_write_EVT15(evt_system_call);
- CSYNC();
-}
-
-/*
- * This function should be called during kernel startup to initialize
- * the BFin IRQ handling routines.
- */
-int __init init_arch_irq(void)
-{
- int irq;
- unsigned long ilat = 0;
- /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
- bfin_write_SICA_IMASK0(SIC_UNMASK_ALL);
- bfin_write_SICA_IMASK1(SIC_UNMASK_ALL);
- SSYNC();
-
- bfin_write_SICA_IWR0(IWR_ENABLE_ALL);
- bfin_write_SICA_IWR1(IWR_ENABLE_ALL);
-
- local_irq_disable();
-
- init_exception_buff();
-
- for (irq = 0; irq <= SYS_IRQS; irq++) {
- if (irq <= IRQ_CORETMR)
- set_irq_chip(irq, &bf561_core_irqchip);
- else
- set_irq_chip(irq, &bf561_internal_irqchip);
-
- if ((irq != IRQ_PROG0_INTA) &&
- (irq != IRQ_PROG1_INTA) &&
- (irq != IRQ_PROG2_INTA))
- set_irq_handler(irq, handle_simple_irq);
- else
- set_irq_chained_handler(irq, bf561_demux_gpio_irq);
- }
-
- for (irq = IRQ_PF0; irq <= IRQ_PF47; irq++) {
- set_irq_chip(irq, &bf561_gpio_irqchip);
- /* if configured as edge, then will be changed to do_edge_IRQ */
- set_irq_handler(irq, handle_level_irq);
- }
-
- bfin_write_IMASK(0);
- CSYNC();
- ilat = bfin_read_ILAT();
- CSYNC();
- bfin_write_ILAT(ilat);
- CSYNC();
-
- printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
- /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
- * local_irq_enable()
- */
- program_IAR();
- /* Therefore it's better to setup IARs before interrupts enabled */
- search_IAR();
-
- /* Enable interrupts IVG7-15 */
- irq_flags = irq_flags | IMASK_IVG15 |
- IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
- IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-
- return 0;
-}
-
-#ifdef CONFIG_DO_IRQ_L1
-__attribute__((l1_text))
-#endif
-void do_irq(int vec, struct pt_regs *fp)
-{
- if (vec == EVT_IVTMR_P) {
- vec = IRQ_CORETMR;
- } else {
- struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
- struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
- unsigned long sic_status0, sic_status1;
-
- SSYNC();
- sic_status0 = bfin_read_SICA_IMASK0() & bfin_read_SICA_ISR0();
- sic_status1 = bfin_read_SICA_IMASK1() & bfin_read_SICA_ISR1();
-
- for (;; ivg++) {
- if (ivg >= ivg_stop) {
- atomic_inc(&num_spurious);
- return;
- } else if ((sic_status0 & ivg->isrflag0) ||
- (sic_status1 & ivg->isrflag1))
- break;
- }
- vec = ivg->irqno;
- }
- asm_do_IRQ(vec, fp);
-
-#ifdef CONFIG_KGDB
- kgdb_process_breakpoint();
-#endif
-}
/*
- * File: arch/blackfin/mach-common/ints-priority-sc.c
+ * File: arch/blackfin/mach-common/ints-priority.c
* Based on:
* Author:
*
* 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
* 2003 Metrowerks/Motorola
* 2003 Bas Vermeulen <bas@buyways.nl>
- * Copyright 2004-2007 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
/* The number of spurious interrupts */
atomic_t num_spurious;
+#ifdef CONFIG_PM
+unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
+#endif
+
struct ivgx {
/* irq number for request_irq, available in mach-bf533/irq.h */
unsigned int irqno;
for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
int iar_shift = (irqn & 7) * 4;
- if (ivg ==
- (0xf &
+ if (ivg == (0xf &
#ifndef CONFIG_BF52x
bfin_read32((unsigned long *)SIC_IAR0 +
(irqn >> 3)) >> iar_shift)) {
SSYNC();
}
+#ifdef CONFIG_PM
+int bfin_internal_set_wake(unsigned int irq, unsigned int state)
+{
+ unsigned bank, bit;
+ unsigned long flags;
+ bank = (irq - (IRQ_CORETMR + 1)) / 32;
+ bit = (irq - (IRQ_CORETMR + 1)) % 32;
+
+ local_irq_save(flags);
+
+ if (state)
+ bfin_sic_iwr[bank] |= (1 << bit);
+ else
+ bfin_sic_iwr[bank] &= ~(1 << bit);
+
+ local_irq_restore(flags);
+
+ return 0;
+}
+#endif
+
static struct irq_chip bfin_core_irqchip = {
.ack = ack_noop,
.mask = bfin_core_mask_irq,
.ack = ack_noop,
.mask = bfin_internal_mask_irq,
.unmask = bfin_internal_unmask_irq,
+#ifdef CONFIG_PM
+ .set_wake = bfin_internal_set_wake,
+#endif
};
#ifdef BF537_GENERIC_ERROR_INT_DEMUX
if (!error_int_mask) {
local_irq_disable();
bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
- ~(1 <<
- (IRQ_GENERIC_ERROR -
+ ~(1 << (IRQ_GENERIC_ERROR -
(IRQ_CORETMR + 1))));
SSYNC();
local_irq_enable();
};
static void bfin_demux_error_irq(unsigned int int_err_irq,
- struct irq_desc *intb_desc)
+ struct irq_desc *inta_desc)
{
int irq = 0;
return 0;
}
+ set_gpio_inen(gpionr, 0);
set_gpio_dir(gpionr, 0);
- set_gpio_inen(gpionr, 1);
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
- gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
- set_gpio_edge(gpionr, 1);
- } else {
- set_gpio_edge(gpionr, 0);
- gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
- }
if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
== (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
else
set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
+ set_gpio_edge(gpionr, 1);
+ set_gpio_inen(gpionr, 1);
+ gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
+ set_gpio_data(gpionr, 0);
+
+ } else {
+ set_gpio_edge(gpionr, 0);
+ gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
+ set_gpio_inen(gpionr, 1);
+ }
+
SSYNC();
if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
return 0;
}
+#ifdef CONFIG_PM
+int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
+{
+ unsigned gpio = irq_to_gpio(irq);
+
+ if (state)
+ gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
+ else
+ gpio_pm_wakeup_free(gpio);
+
+ return 0;
+}
+#endif
+
static struct irq_chip bfin_gpio_irqchip = {
.ack = bfin_gpio_ack_irq,
.mask = bfin_gpio_mask_irq,
.unmask = bfin_gpio_unmask_irq,
.set_type = bfin_gpio_irq_type,
.startup = bfin_gpio_irq_startup,
- .shutdown = bfin_gpio_irq_shutdown
+ .shutdown = bfin_gpio_irq_shutdown,
+#ifdef CONFIG_PM
+ .set_wake = bfin_gpio_set_wake,
+#endif
};
-static void bfin_demux_gpio_irq(unsigned int intb_irq,
- struct irq_desc *intb_desc)
+static void bfin_demux_gpio_irq(unsigned int inta_irq,
+ struct irq_desc *desc)
{
- u16 i;
- struct irq_desc *desc;
+ unsigned int i, gpio, mask, irq, search = 0;
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) {
- int irq = IRQ_PF0 + i;
- int flag_d = get_gpiop_data(i);
- int mask =
- flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i));
+ switch (inta_irq) {
+#if defined(CONFIG_BF53x)
+ case IRQ_PROG_INTA:
+ irq = IRQ_PF0;
+ search = 1;
+ break;
+# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
+ case IRQ_MAC_RX:
+ irq = IRQ_PH0;
+ break;
+# endif
+#elif defined(CONFIG_BF52x)
+ case IRQ_PORTF_INTA:
+ irq = IRQ_PF0;
+ break;
+ case IRQ_PORTG_INTA:
+ irq = IRQ_PG0;
+ break;
+ case IRQ_PORTH_INTA:
+ irq = IRQ_PH0;
+ break;
+#elif defined(CONFIG_BF561)
+ case IRQ_PROG0_INTA:
+ irq = IRQ_PF0;
+ break;
+ case IRQ_PROG1_INTA:
+ irq = IRQ_PF16;
+ break;
+ case IRQ_PROG2_INTA:
+ irq = IRQ_PF32;
+ break;
+#endif
+ default:
+ BUG();
+ return;
+ }
- while (mask) {
- if (mask & 1) {
- desc = irq_desc + irq;
- desc->handle_irq(irq, desc);
+ if (search) {
+ for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
+ irq += i;
+
+ mask = get_gpiop_data(i) &
+ (gpio_enabled[gpio_bank(i)] &
+ get_gpiop_maska(i));
+
+ while (mask) {
+ if (mask & 1) {
+ desc = irq_desc + irq;
+ desc->handle_irq(irq, desc);
+ }
+ irq++;
+ mask >>= 1;
}
- irq++;
- mask >>= 1;
}
+ } else {
+ gpio = irq_to_gpio(irq);
+ mask = get_gpiop_data(gpio) &
+ (gpio_enabled[gpio_bank(gpio)] &
+ get_gpiop_maska(gpio));
+
+ do {
+ if (mask & 1) {
+ desc = irq_desc + irq;
+ desc->handle_irq(irq, desc);
+ }
+ irq++;
+ mask >>= 1;
+ } while (mask);
}
+
}
#else /* CONFIG_BF54x */
return 0;
}
+#ifdef CONFIG_PM
+u32 pint_saved_masks[NR_PINT_SYS_IRQS];
+u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
+
+int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
+{
+ u32 pint_irq;
+ u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
+ u32 bank = PINT_2_BANK(pint_val);
+ u32 pintbit = PINT_BIT(pint_val);
+
+ switch (bank) {
+ case 0:
+ pint_irq = IRQ_PINT0;
+ break;
+ case 2:
+ pint_irq = IRQ_PINT2;
+ break;
+ case 3:
+ pint_irq = IRQ_PINT3;
+ break;
+ case 1:
+ pint_irq = IRQ_PINT1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ bfin_internal_set_wake(pint_irq, state);
+
+ if (state)
+ pint_wakeup_masks[bank] |= pintbit;
+ else
+ pint_wakeup_masks[bank] &= ~pintbit;
+
+ return 0;
+}
+
+u32 bfin_pm_setup(void)
+{
+ u32 val, i;
+
+ for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
+ val = pint[i]->mask_clear;
+ pint_saved_masks[i] = val;
+ if (val ^ pint_wakeup_masks[i]) {
+ pint[i]->mask_clear = val;
+ pint[i]->mask_set = pint_wakeup_masks[i];
+ }
+ }
+
+ return 0;
+}
+
+void bfin_pm_restore(void)
+{
+ u32 i, val;
+
+ for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
+ val = pint_saved_masks[i];
+ if (val ^ pint_wakeup_masks[i]) {
+ pint[i]->mask_clear = pint[i]->mask_clear;
+ pint[i]->mask_set = val;
+ }
+ }
+}
+#endif
+
static struct irq_chip bfin_gpio_irqchip = {
.ack = bfin_gpio_ack_irq,
.mask = bfin_gpio_mask_irq,
.unmask = bfin_gpio_unmask_irq,
.set_type = bfin_gpio_irq_type,
.startup = bfin_gpio_irq_startup,
- .shutdown = bfin_gpio_irq_shutdown
+ .shutdown = bfin_gpio_irq_shutdown,
+#ifdef CONFIG_PM
+ .set_wake = bfin_gpio_set_wake,
+#endif
};
-static void bfin_demux_gpio_irq(unsigned int intb_irq,
- struct irq_desc *intb_desc)
+static void bfin_demux_gpio_irq(unsigned int inta_irq,
+ struct irq_desc *desc)
{
u8 bank, pint_val;
u32 request, irq;
- struct irq_desc *desc;
- switch (intb_irq) {
+ switch (inta_irq) {
case IRQ_PINT0:
bank = 0;
break;
int irq;
unsigned long ilat = 0;
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
local_irq_disable();
+ init_exception_buff();
+
#ifdef CONFIG_BF54x
# ifdef CONFIG_PINTx_REASSIGN
pint[0]->assign = CONFIG_PINT0_ASSIGN;
set_irq_chained_handler(irq,
bfin_demux_gpio_irq);
break;
+#elif defined(CONFIG_BF561)
+ case IRQ_PROG0_INTA:
+ set_irq_chained_handler(irq,
+ bfin_demux_gpio_irq);
+ break;
+ case IRQ_PROG1_INTA:
+ set_irq_chained_handler(irq,
+ bfin_demux_gpio_irq);
+ break;
+ case IRQ_PROG2_INTA:
+ set_irq_chained_handler(irq,
+ bfin_demux_gpio_irq);
+ break;
#endif
default:
set_irq_handler(irq, handle_simple_irq);
}
#endif
-#ifndef CONFIG_BF54x
- for (irq = IRQ_PF0; irq < NR_IRQS; irq++) {
-#else
- for (irq = IRQ_PA0; irq < NR_IRQS; irq++) {
-#endif
+ for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) {
+
set_irq_chip(irq, &bfin_gpio_irqchip);
/* if configured as edge, then will be changed to do_edge_IRQ */
set_irq_handler(irq, handle_level_irq);
} else {
struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
unsigned long sic_status[3];
SSYNC();
* Author: Cliff Brake <cbrake@accelent.com> Copyright (c) 2001
*
* Created: 2001
- * Description: Power management for the bfin
+ * Description: Blackfin power management
*
* Modified: Nicolas Pitre - PXA250 support
* Copyright (c) 2002 Monta Vista Software, Inc.
* Copyright (c) 2002 Monta Vista Software, Inc.
* Dirk Behme <dirk.behme@de.bosch.com> - OMAP1510/1610
* Copyright 2004
- * Copyright 2004-2006 Analog Devices Inc.
+ * Copyright 2004-2008 Analog Devices Inc.
*
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
#endif
-#if defined(CONFIG_PM_WAKEUP_BY_GPIO) || defined(CONFIG_PM_WAKEUP_GPIO_API)
- {
- u32 flags;
+ u32 flags;
- local_irq_save(flags);
+ local_irq_save(flags);
+ bfin_pm_setup();
- sleep_deeper(gpio_pm_setup()); /*Goto Sleep*/
-
- gpio_pm_restore();
-
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
- bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
- bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
-# ifdef CONFIG_BF54x
- bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
-# endif
+#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
+ sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
#else
- bfin_write_SIC_IWR(IWR_ENABLE_ALL);
+ sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
#endif
- local_irq_restore(flags);
- }
-#endif
+ bfin_pm_restore();
-#if defined(CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR)
- sleep_deeper(CONFIG_PM_WAKEUP_SIC_IWR);
-# if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)
+#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
-# ifdef CONFIG_BF54x
+# ifdef CONFIG_BF54x
bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
-# endif
-# else
- bfin_write_SIC_IWR(IWR_ENABLE_ALL);
# endif
-#endif /* CONFIG_PM_WAKEUP_GPIO_BY_SIC_IWR */
+#else
+ bfin_write_SIC_IWR(IWR_ENABLE_ALL);
+#endif
+
+ local_irq_restore(flags);
}
/*
start_mem = PAGE_ALIGN(start_mem);
max_mapnr = num_physpages = MAP_NR(high_memory);
- printk(KERN_INFO "Kernel managed physical pages: %lu\n",
- num_physpages);
+ printk(KERN_DEBUG "Kernel managed physical pages: %lu\n", num_physpages);
/* This will put all memory onto the freelists. */
totalram_pages = free_all_bootmem();
/* do not count in kernel image between _rambase and _ramstart */
reservedpages -= (_ramstart - _rambase) >> PAGE_SHIFT;
#if (defined(CONFIG_BFIN_ICACHE) && ANOMALY_05000263)
- reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >>
- PAGE_SHIFT;
+ reservedpages += (_ramend - memory_end - DMA_UNCACHED_REGION) >> PAGE_SHIFT;
#endif
codek = (_etext - _stext) >> 10;
printk(KERN_INFO
"Memory available: %luk/%luk RAM, "
- "(%uk init code, %uk kernel code, "
- "%uk data, %uk dma, %uk reserved)\n",
+ "(%uk init code, %uk kernel code, %uk data, %uk dma, %uk reserved)\n",
(unsigned long) freepages << (PAGE_SHIFT-10), _ramend >> 10,
- initk, codek, datak, DMA_UNCACHED_REGION >> 10,
- (reservedpages << (PAGE_SHIFT-10)));
+ initk, codek, datak, DMA_UNCACHED_REGION >> 10, (reservedpages << (PAGE_SHIFT-10)));
/* Initialize the blackfin L1 Memory. */
l1sram_init();
bool
default y
-config NO_DMA
- bool
- default y
-
config RWSEM_GENERIC_SPINLOCK
bool
default y
config RWSEM_XCHGADD_ALGORITHM
bool
+config GENERIC_IOMAP
+ bool
+ default y
+
config ARCH_HAS_ILOG2_U32
bool
default n
bool
default y
-config IRQ_PER_CPU
- bool
- default y
-
config NO_IOPORT
def_bool y
+config FORCE_MAX_ZONEORDER
+ int
+ default 6
+
config CRIS
bool
default y
+config HZ
+ int
+ default 100
+
source "init/Kconfig"
menu "General setup"
timers).
This is needed if CONFIG_ETRAX_SERIAL_FAST_TIMER is enabled.
-config PREEMPT
- bool "Preemptible Kernel"
+config ETRAX_KMALLOCED_MODULES
+ bool "Enable module allocation with kmalloc"
help
- This option reduces the latency of the kernel when reacting to
- real-time or interactive events by allowing a low priority process to
- be preempted even if it is in kernel mode executing a system call.
- This allows applications to run more reliably even when the system is
- under load.
+ Enable module allocation with kmalloc instead of vmalloc.
+
+config OOM_REBOOT
+ bool "Enable reboot at out of memory"
- Say Y here if you are building a kernel for a desktop, embedded
- or real-time system. Say N if you are unsure.
+source "kernel/Kconfig.preempt"
source mm/Kconfig
help
Support the xsim ETRAX Simulator.
+config ETRAXFS
+ bool "ETRAX-FS-V32"
+ help
+ Support CRIS V32.
+
+config CRIS_MACH_ARTPEC3
+ bool "ARTPEC-3"
+ help
+ Support Axis ARTPEC-3.
+
endchoice
+config ETRAX_VCS_SIM
+ bool "VCS Simulator"
+ help
+ Setup hardware to be run in the VCS simulator.
+
config ETRAX_ARCH_V10
bool
default y if ETRAX100LX || ETRAX100LX_V2
default n if !(ETRAX100LX || ETRAX100LX_V2)
+config ETRAX_ARCH_V32
+ bool
+ default y if (ETRAXFS || CRIS_MACH_ARTPEC3)
+ default n if !(ETRAXFS || CRIS_MACH_ARTPEC3)
+
config ETRAX_DRAM_SIZE
int "DRAM size (dec, in MB)"
default "8"
help
Size of DRAM (decimal in MB) typically 2, 8 or 16.
+config ETRAX_VMEM_SIZE
+ int "Video memory size (dec, in MB)"
+ depends on ETRAX_ARCH_V32 && !ETRAXFS
+ default 8 if !ETRAXFS
+ help
+ Size of Video accessible memory (decimal, in MB).
+
config ETRAX_FLASH_BUSWIDTH
- int "Buswidth of flash in bytes"
+ int "Buswidth of NOR flash in bytes"
default "2"
help
- Width in bytes of the Flash bus (1, 2 or 4). Is usually 2.
+ Width in bytes of the NOR Flash bus (1, 2 or 4). Is usually 2.
+
+config ETRAX_NANDFLASH_BUSWIDTH
+ int "Buswidth of NAND flash in bytes"
+ default "1"
+ help
+ Width in bytes of the NAND flash (1 or 2).
+
+config ETRAX_FLASH1_SIZE
+ int "FLASH1 size (dec, in MB. 0 = Unknown)"
+ default "0"
+
+choice
+ prompt "Product debug-port"
+ default ETRAX_DEBUG_PORT0
+
+config ETRAX_DEBUG_PORT0
+ bool "Serial-0"
+ help
+ Choose a serial port for the ETRAX debug console. Default to
+ port 0.
+
+config ETRAX_DEBUG_PORT1
+ bool "Serial-1"
+ help
+ Use serial port 1 for the console.
+
+config ETRAX_DEBUG_PORT2
+ bool "Serial-2"
+ help
+ Use serial port 2 for the console.
+
+config ETRAX_DEBUG_PORT3
+ bool "Serial-3"
+ help
+ Use serial port 3 for the console.
+
+config ETRAX_DEBUG_PORT_NULL
+ bool "disabled"
+ help
+ Disable serial-port debugging.
+
+endchoice
+
+choice
+ prompt "Kernel GDB port"
+ depends on ETRAX_KGDB
+ default ETRAX_KGDB_PORT0
+ help
+ Choose a serial port for kernel debugging. NOTE: This port should
+ not be enabled under Drivers for built-in interfaces (as it has its
+ own initialization code) and should not be the same as the debug port.
+
+config ETRAX_KGDB_PORT0
+ bool "Serial-0"
+ help
+ Use serial port 0 for kernel debugging.
+
+config ETRAX_KGDB_PORT1
+ bool "Serial-1"
+ help
+ Use serial port 1 for kernel debugging.
+
+config ETRAX_KGDB_PORT2
+ bool "Serial-2"
+ help
+ Use serial port 2 for kernel debugging.
+
+config ETRAX_KGDB_PORT3
+ bool "Serial-3"
+ help
+ Use serial port 3 for kernel debugging.
+
+endchoice
source arch/cris/arch-v10/Kconfig
source arch/cris/arch-v32/Kconfig
source arch/cris/arch-v10/drivers/Kconfig
source arch/cris/arch-v32/drivers/Kconfig
+config ETRAX_AXISFLASHMAP
+ bool "Axis flash-map support"
+ select MTD
+ select MTD_CFI
+ select MTD_CFI_AMDSTD
+ select MTD_JEDECPROBE if ETRAX_ARCH_V32
+ select MTD_CHAR
+ select MTD_BLOCK
+ select MTD_PARTITIONS
+ select MTD_CONCAT
+ select MTD_COMPLEX_MAPPINGS
+ help
+ This option enables MTD mapping of flash devices. Needed to use
+ flash memories. If unsure, say Y.
+
+config ETRAX_RTC
+ bool "Real Time Clock support"
+ depends on ETRAX_I2C
+ help
+ Enables drivers for the Real-Time Clock battery-backed chips on
+ some products. The kernel reads the time when booting, and
+ the date can be set using ioctl(fd, RTC_SET_TIME, &rt) with rt a
+ rtc_time struct (see <file:include/asm-cris/rtc.h>) on the /dev/rtc
+ device. You can check the time with cat /proc/rtc, but
+ normal time reading should be done using libc function time and
+ friends.
+
+choice
+ prompt "RTC chip"
+ depends on ETRAX_RTC
+ default ETRAX_PCF8563 if ETRAX_ARCH_V32
+ default ETRAX_DS1302 if ETRAX_ARCH_V10
+
+config ETRAX_DS1302
+ depends on ETRAX_ARCH_V10
+ bool "DS1302"
+ help
+ Enables the driver for the DS1302 Real-Time Clock battery-backed
+ chip on some products.
+
+config ETRAX_PCF8563
+ bool "PCF8563"
+ help
+ Enables the driver for the PCF8563 Real-Time Clock battery-backed
+ chip on some products.
+
+endchoice
+
+config ETRAX_SYNCHRONOUS_SERIAL
+ bool "Synchronous serial-port support"
+ help
+ Select this to enable the synchronous serial port driver.
+
+config ETRAX_SYNCHRONOUS_SERIAL_PORT0
+ bool "Synchronous serial port 0 enabled"
+ depends on ETRAX_SYNCHRONOUS_SERIAL
+ help
+ Enabled synchronous serial port 0.
+
+config ETRAX_SYNCHRONOUS_SERIAL0_DMA
+ bool "Enable DMA on synchronous serial port 0."
+ depends on ETRAX_SYNCHRONOUS_SERIAL_PORT0
+ help
+ A synchronous serial port can run in manual or DMA mode.
+ Selecting this option will make it run in DMA mode.
+
+config ETRAX_SYNCHRONOUS_SERIAL_PORT1
+ bool "Synchronous serial port 1 enabled"
+ depends on ETRAX_SYNCHRONOUS_SERIAL && (ETRAXFS || ETRAX_ARCH_V10)
+ help
+ Enabled synchronous serial port 1.
+
+config ETRAX_SYNCHRONOUS_SERIAL1_DMA
+ bool "Enable DMA on synchronous serial port 1."
+ depends on ETRAX_SYNCHRONOUS_SERIAL_PORT1
+ help
+ A synchronous serial port can run in manual or DMA mode.
+ Selecting this option will make it run in DMA mode.
+
+choice
+ prompt "Network LED behavior"
+ depends on ETRAX_ETHERNET
+ default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
+
+config ETRAX_NETWORK_LED_ON_WHEN_LINK
+ bool "LED_on_when_link"
+ help
+ Selecting LED_on_when_link will light the LED when there is a
+ connection and will flash off when there is activity.
+
+ Selecting LED_on_when_activity will light the LED only when
+ there is activity.
+
+ This setting will also affect the behaviour of other activity LEDs
+ e.g. Bluetooth.
+
+config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
+ bool "LED_on_when_activity"
+ help
+ Selecting LED_on_when_link will light the LED when there is a
+ connection and will flash off when there is activity.
+
+ Selecting LED_on_when_activity will light the LED only when
+ there is activity.
+
+ This setting will also affect the behaviour of other activity LEDs
+ e.g. Bluetooth.
+
+endchoice
+
+choice
+ prompt "Ser0 DMA out channel"
+ depends on ETRAX_SERIAL_PORT0
+ default ETRAX_SERIAL_PORT0_DMA6_OUT if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT0_NO_DMA_OUT if ETRAX_ARCH_V10
+
+config ETRAX_SERIAL_PORT0_NO_DMA_OUT
+ bool "Ser0 uses no DMA for output"
+ help
+ Do not use DMA for ser0 output.
+
+config ETRAX_SERIAL_PORT0_DMA6_OUT
+ bool "Ser0 uses DMA6 for output"
+ depends on ETRAXFS
+ help
+ Enables the DMA6 output channel for ser0 (ttyS0).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT0_DMA0_OUT
+ bool "Ser0 uses DMA0 for output"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA0 output channel for ser0 (ttyS0).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser0 DMA in channel "
+ depends on ETRAX_SERIAL_PORT0
+ default ETRAX_SERIAL_PORT0_NO_DMA_IN if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT0_DMA7_IN if ETRAX_ARCH_V10
+ help
+ What DMA channel to use for ser0.
+
+config ETRAX_SERIAL_PORT0_NO_DMA_IN
+ bool "Ser0 uses no DMA for input"
+ help
+ Do not use DMA for ser0 input.
+
+config ETRAX_SERIAL_PORT0_DMA7_IN
+ bool "Ser0 uses DMA7 for input"
+ depends on ETRAXFS
+ help
+ Enables the DMA7 input channel for ser0 (ttyS0).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiving data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT0_DMA1_IN
+ bool "Ser0 uses DMA1 for input"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA1 input channel for ser0 (ttyS0).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiveing data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser1 DMA in channel "
+ depends on ETRAX_SERIAL_PORT1
+ default ETRAX_SERIAL_PORT1_NO_DMA_IN if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT1_DMA9_IN if ETRAX_ARCH_V10
+ help
+ What DMA channel to use for ser1.
+
+config ETRAX_SERIAL_PORT1_NO_DMA_IN
+ bool "Ser1 uses no DMA for input"
+ help
+ Do not use DMA for ser1 input.
+
+config ETRAX_SERIAL_PORT1_DMA5_IN
+ bool "Ser1 uses DMA5 for input"
+ depends on ETRAX_ARCH_V32
+ help
+ Enables the DMA5 input channel for ser1 (ttyS1).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiving data.
+ Normally you want this on, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT1_DMA9_IN
+ depends on ETRAX_ARCH_V10
+ bool "Ser1 uses DMA9 for input"
+
+endchoice
+
+
+choice
+ prompt "Ser1 DMA out channel"
+ depends on ETRAX_SERIAL_PORT1
+ default ETRAX_SERIAL_PORT1_NO_DMA_OUT if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT1_DMA8_OUT if ETRAX_ARCH_V10
+ help
+ What DMA channel to use for ser1.
+
+config ETRAX_SERIAL_PORT1_NO_DMA_OUT
+ bool "Ser1 uses no DMA for output"
+ help
+ Do not use DMA for ser1 output.
+
+config ETRAX_SERIAL_PORT1_DMA8_OUT
+ depends on ETRAX_ARCH_V10
+ bool "Ser1 uses DMA8 for output"
+
+config ETRAX_SERIAL_PORT1_DMA4_OUT
+ depends on ETRAX_ARCH_V32
+ bool "Ser1 uses DMA4 for output"
+ help
+ Enables the DMA4 output channel for ser1 (ttyS1).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want this on, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser2 DMA out channel"
+ depends on ETRAX_SERIAL_PORT2
+ default ETRAX_SERIAL_PORT2_NO_DMA_OUT if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT2_DMA2_OUT if ETRAX_ARCH_V10
+
+config ETRAX_SERIAL_PORT2_NO_DMA_OUT
+ bool "Ser2 uses no DMA for output"
+ help
+ Do not use DMA for ser2 output.
+
+config ETRAX_SERIAL_PORT2_DMA2_OUT
+ bool "Ser2 uses DMA2 for output"
+ depends on ETRAXFS || ETRAX_ARCH_V10
+ help
+ Enables the DMA2 output channel for ser2 (ttyS2).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT2_DMA6_OUT
+ bool "Ser2 uses DMA6 for output"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA6 output channel for ser2 (ttyS2).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser2 DMA in channel"
+ depends on ETRAX_SERIAL_PORT2
+ default ETRAX_SERIAL_PORT2_NO_DMA_IN if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT2_DMA3_IN if ETRAX_ARCH_V10
+ help
+ What DMA channel to use for ser2.
+
+config ETRAX_SERIAL_PORT2_NO_DMA_IN
+ bool "Ser2 uses no DMA for input"
+ help
+ Do not use DMA for ser2 input.
+
+config ETRAX_SERIAL_PORT2_DMA3_IN
+ bool "Ser2 uses DMA3 for input"
+ depends on ETRAXFS || ETRAX_ARCH_V10
+ help
+ Enables the DMA3 input channel for ser2 (ttyS2).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiving data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT2_DMA7_IN
+ bool "Ser2 uses DMA7 for input"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA7 input channel for ser2 (ttyS2).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiveing data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser3 DMA in channel"
+ depends on ETRAX_SERIAL_PORT3
+ default ETRAX_SERIAL_PORT3_NO_DMA_IN if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT3_DMA5_IN if ETRAX_ARCH_V10
+ help
+ What DMA channel to use for ser3.
+
+config ETRAX_SERIAL_PORT3_NO_DMA_IN
+ bool "Ser3 uses no DMA for input"
+ help
+ Do not use DMA for ser3 input.
+
+config ETRAX_SERIAL_PORT3_DMA5_IN
+ depends on ETRAX_ARCH_V10
+ bool "DMA 5"
+
+config ETRAX_SERIAL_PORT3_DMA9_IN
+ bool "Ser3 uses DMA9 for input"
+ depends on ETRAXFS
+ help
+ Enables the DMA9 input channel for ser3 (ttyS3).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiving data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT3_DMA3_IN
+ bool "Ser3 uses DMA3 for input"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA3 input channel for ser3 (ttyS3).
+ If you do not enable DMA, an interrupt for each character will be
+ used when receiveing data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice
+
+choice
+ prompt "Ser3 DMA out channel"
+ depends on ETRAX_SERIAL_PORT3
+ default ETRAX_SERIAL_PORT3_NO_DMA_OUT if ETRAX_ARCH_V32
+ default ETRAX_SERIAL_PORT3_DMA4_OUT if ETRAX_ARCH_V10
+
+config ETRAX_SERIAL_PORT3_NO_DMA_OUT
+ bool "Ser3 uses no DMA for output"
+ help
+ Do not use DMA for ser3 output.
+
+config ETRAX_SERIAL_PORT3_DMA4_OUT
+ depends on ETRAX_ARCH_V10
+ bool "DMA 4"
+
+config ETRAX_SERIAL_PORT3_DMA8_OUT
+ bool "Ser3 uses DMA8 for output"
+ depends on ETRAXFS
+ help
+ Enables the DMA8 output channel for ser3 (ttyS3).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+config ETRAX_SERIAL_PORT3_DMA2_OUT
+ bool "Ser3 uses DMA2 for output"
+ depends on CRIS_MACH_ARTPEC3
+ help
+ Enables the DMA2 output channel for ser3 (ttyS3).
+ If you do not enable DMA, an interrupt for each character will be
+ used when transmitting data.
+ Normally you want to use DMA, unless you use the DMA channel for
+ something else.
+
+endchoice
+
endmenu
source "drivers/base/Kconfig"
source "drivers/block/Kconfig"
-source "drivers/md/Kconfig"
-
source "drivers/ide/Kconfig"
-source "drivers/scsi/Kconfig"
-
-source "drivers/ieee1394/Kconfig"
-
-source "drivers/message/i2o/Kconfig"
-
source "drivers/net/Kconfig"
-source "drivers/isdn/Kconfig"
-
-source "drivers/telephony/Kconfig"
-
source "drivers/i2c/Kconfig"
source "drivers/rtc/Kconfig"
source "drivers/char/Kconfig"
-#source drivers/misc/Config.in
-source "drivers/media/Kconfig"
-
source "fs/Kconfig"
-source "sound/Kconfig"
-
-source "drivers/pcmcia/Kconfig"
-
-source "drivers/pci/Kconfig"
-
source "drivers/usb/Kconfig"
source "arch/cris/Kconfig.debug"
-# $Id: Makefile,v 1.28 2005/03/17 10:44:37 larsv Exp $
+#
# cris/Makefile
#
# This file is included by the global makefile so that you can add your own
# License. See the file "COPYING" in the main directory of this archive
# for more details.
-# A bug in ld prevents us from having a (constant-value) symbol in a
-# "ORIGIN =" or "LENGTH =" expression.
-
arch-y := v10
arch-$(CONFIG_ETRAX_ARCH_V10) := v10
arch-$(CONFIG_ETRAX_ARCH_V32) := v32
-# No config avaiable for make clean etc
+# No config available for make clean etc
+mach-y := fs
+mach-$(CONFIG_CRIS_MACH_ARTPEC3) := a3
+mach-$(CONFIG_ETRAXFS) := fs
+
ifneq ($(arch-y),)
SARCH := arch-$(arch-y)
else
SARCH :=
endif
+ifneq ($(mach-y),)
+MACH := mach-$(mach-y)
+else
+MACH :=
+endif
+
LD = $(CROSS_COMPILE)ld -mcrislinux
OBJCOPYFLAGS := -O binary -R .note -R .comment -S
CPPFLAGS_vmlinux.lds = -DDRAM_VIRTUAL_BASE=0x$(CONFIG_ETRAX_DRAM_VIRTUAL_BASE)
-KBUILD_AFLAGS += -mlinux
-KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe
+KBUILD_AFLAGS += -mlinux -march=$(arch-y) -Iinclude/asm/arch/mach -Iinclude/asm/arch
+
+KBUILD_CFLAGS += -mlinux -march=$(arch-y) -pipe -Iinclude/asm/arch/mach -Iinclude/asm/arch
ifdef CONFIG_FRAME_POINTER
KBUILD_CFLAGS := $(subst -fomit-frame-pointer,,$(KBUILD_CFLAGS)) -g
core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/
core-y += arch/$(ARCH)/$(SARCH)/kernel/ arch/$(ARCH)/$(SARCH)/mm/
+ifdef CONFIG_ETRAX_ARCH_V32
+core-y += arch/$(ARCH)/$(SARCH)/$(MACH)/
+endif
drivers-y += arch/$(ARCH)/$(SARCH)/drivers/
libs-y += arch/$(ARCH)/$(SARCH)/lib/ $(LIBGCC)
# cris object files path
OBJ_ARCH = $(objtree)/arch/$(ARCH)
-target_boot_arch_dir = $(OBJ_ARCH)/$(SARCH)/boot
-target_boot_dir = $(OBJ_ARCH)/boot
-src_boot_dir = $(SRC_ARCH)/boot
-target_compressed_dir = $(OBJ_ARCH)/boot/compressed
-src_compressed_dir = $(SRC_ARCH)/boot/compressed
-target_rescue_dir = $(OBJ_ARCH)/boot/rescue
-src_rescue_dir = $(SRC_ARCH)/boot/rescue
-
-export target_boot_arch_dir target_boot_dir src_boot_dir target_compressed_dir src_compressed_dir target_rescue_dir src_rescue_dir
-
-vmlinux.bin: vmlinux
- $(OBJCOPY) $(OBJCOPYFLAGS) vmlinux vmlinux.bin
-
-timage: vmlinux.bin
- cat vmlinux.bin cramfs.img >timage
-
-simimage: timage
- cp vmlinux.bin simvmlinux.bin
-
-# the following will remake timage without compiling the kernel
-# it does of course require that all object files exist...
-
-cramfs:
-## cramfs - Creates a cramfs image
- mkcramfs -b 8192 -m romfs_meta.txt root cramfs.img
- cat vmlinux.bin cramfs.img >timage
+boot := arch/$(ARCH)/boot
+MACHINE := arch/$(ARCH)/$(SARCH)
-clinux: vmlinux.bin decompress.bin rescue.bin
+all: zImage
-decompress.bin: $(target_boot_dir)
- @$(MAKE) -f $(src_compressed_dir)/Makefile $(target_compressed_dir)/decompress.bin
+zImage Image: vmlinux
+ $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
-$(target_rescue_dir)/rescue.bin: $(target_boot_dir)
- @$(MAKE) -f $(src_rescue_dir)/Makefile $(target_rescue_dir)/rescue.bin
-
-zImage: $(target_boot_dir) vmlinux.bin $(target_rescue_dir)/rescue.bin
-## zImage - Compressed kernel (gzip)
- @$(MAKE) -f $(src_boot_dir)/Makefile zImage
-
-$(target_boot_dir): $(target_boot_arch_dir)
- ln -sfn $< $@
-
-$(target_boot_arch_dir):
- mkdir -p $@
-
-compressed: zImage
-
-archmrproper:
-archclean:
- @if [ -d arch/$(ARCH)/boot ]; then \
- $(MAKE) $(clean)=arch/$(ARCH)/boot ; \
- fi
- rm -f timage vmlinux.bin decompress.bin rescue.bin cramfs.img
- rm -rf $(LD_SCRIPT).tmp
-
-archprepare: $(SRC_ARCH)/.links $(srctree)/include/asm-$(ARCH)/.arch
+archprepare: $(SRC_ARCH)/.links $(srctree)/include/asm-$(ARCH)/.arch FORCE
# Create some links to make all tools happy
$(SRC_ARCH)/.links:
@rm -rf $(SRC_ARCH)/drivers
- @ln -sfn $(SRC_ARCH)/$(SARCH)/drivers $(SRC_ARCH)/drivers
+ @ln -sfn $(SARCH)/drivers $(SRC_ARCH)/drivers
@rm -rf $(SRC_ARCH)/boot
- @ln -sfn $(SRC_ARCH)/$(SARCH)/boot $(SRC_ARCH)/boot
+ @ln -sfn $(SARCH)/boot $(SRC_ARCH)/boot
@rm -rf $(SRC_ARCH)/lib
- @ln -sfn $(SRC_ARCH)/$(SARCH)/lib $(SRC_ARCH)/lib
- @ln -sfn $(SRC_ARCH)/$(SARCH) $(SRC_ARCH)/arch
- @ln -sfn $(SRC_ARCH)/$(SARCH)/vmlinux.lds.S $(SRC_ARCH)/kernel/vmlinux.lds.S
- @ln -sfn $(SRC_ARCH)/$(SARCH)/kernel/asm-offsets.c $(SRC_ARCH)/kernel/asm-offsets.c
+ @ln -sfn $(SARCH)/lib $(SRC_ARCH)/lib
+ @rm -f $(SRC_ARCH)/arch/mach
+ @rm -rf $(SRC_ARCH)/arch
+ @ln -sfn $(SARCH) $(SRC_ARCH)/arch
+ifdef CONFIG_ETRAX_ARCH_V32
+ @ln -sfn ../$(SARCH)/$(MACH) $(SRC_ARCH)/arch/mach
+endif
+ @rm -rf $(SRC_ARCH)/kernel/vmlinux.lds.S
+ @ln -sfn ../$(SARCH)/vmlinux.lds.S $(SRC_ARCH)/kernel/vmlinux.lds.S
+ @rm -rf $(SRC_ARCH)/kernel/asm-offsets.c
+ @ln -sfn ../$(SARCH)/kernel/asm-offsets.c $(SRC_ARCH)/kernel/asm-offsets.c
@touch $@
# Create link to sub arch includes
$(srctree)/include/asm-$(ARCH)/.arch: $(wildcard include/config/arch/*.h)
- @echo ' Making $(srctree)/include/asm-$(ARCH)/arch -> $(srctree)/include/asm-$(ARCH)/$(SARCH) symlink'
- @rm -f include/asm-$(ARCH)/arch
- @ln -sf $(srctree)/include/asm-$(ARCH)/$(SARCH) $(srctree)/include/asm-$(ARCH)/arch
+ @echo ' SYMLINK include/asm-$(ARCH)/arch -> include/asm-$(ARCH)/$(SARCH)'
+ @rm -f $(srctree)/include/asm-$(ARCH)/arch/mach
+ @rm -f $(srctree)/include/asm-$(ARCH)/arch
+ @ln -sf $(SARCH) $(srctree)/include/asm-$(ARCH)/arch
+ifdef CONFIG_ETRAX_ARCH_V32
+ @ln -sf $(MACH) $(srctree)/include/asm-$(ARCH)/arch/mach
+endif
@touch $@
+
+archclean:
+ $(Q)if [ -e arch/$(ARCH)/boot ]; then \
+ $(MAKE) $(clean)=arch/$(ARCH)/boot; \
+ fi
+
+CLEAN_FILES += \
+ $(MACHINE)/boot/zImage \
+ $(MACHINE)/boot/compressed/decompress.bin \
+ $(MACHINE)/boot/compressed/piggy.gz \
+ $(MACHINE)/boot/rescue/rescue.bin \
+ $(SRC_ARCH)/.links \
+ $(srctree)/include/asm-$(ARCH)/.arch
+
+MRPROPER_FILES += \
+ $(SRC_ARCH)/drivers \
+ $(SRC_ARCH)/boot \
+ $(SRC_ARCH)/lib \
+ $(SRC_ARCH)/arch \
+ $(SRC_ARCH)/kernel/vmlinux.lds.S \
+ $(SRC_ARCH)/kernel/asm-offsets.c
+
+define archhelp
+ echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
+ echo '* Image - Uncompressed kernel image (arch/$(ARCH)/boot/Image)'
+endef
if ETRAX_ARCH_V10
+menu "CRIS v10 options"
+
# ETRAX 100LX v1 has a MMU "feature" requiring a low mapping
config CRIS_LOW_MAP
bool
For products with only one or two controllable LEDs,
set this to same as CONFIG_ETRAX_LED1G (normally 2).
-choice
- prompt "Product debug-port"
- depends on ETRAX_ARCH_V10
- default ETRAX_DEBUG_PORT0
-
-config ETRAX_DEBUG_PORT0
- bool "Serial-0"
- help
- Choose a serial port for the ETRAX debug console. Default to
- port 0.
-
-config ETRAX_DEBUG_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for the console.
-
-config ETRAX_DEBUG_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for the console.
-
-config ETRAX_DEBUG_PORT3
- bool "Serial-3"
- help
- Use serial port 3 for the console.
-
-config ETRAX_DEBUG_PORT_NULL
- bool "disabled"
- help
- Disable serial-port debugging.
-
-endchoice
-
-choice
- prompt "Kernel GDB port"
- depends on ETRAX_KGDB
- default ETRAX_KGDB_PORT0
- help
- Choose a serial port for kernel debugging. NOTE: This port should
- not be enabled under Drivers for built-in interfaces (as it has its
- own initialization code) and should not be the same as the debug port.
-
-config ETRAX_KGDB_PORT0
- bool "Serial-0"
- help
- Use serial port 0 for kernel debugging.
-
-config ETRAX_KGDB_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for kernel debugging.
-
-config ETRAX_KGDB_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for kernel debugging.
-
-config ETRAX_KGDB_PORT3
- bool "Serial-3"
- help
- Use serial port 3 for kernel debugging.
-
-endchoice
choice
prompt "Product rescue-port"
help
Configure where power button is connected.
+endmenu
+
endif
#
-# arch/cris/boot/Makefile
+# arch/cris/arch-v10/boot/Makefile
#
-target = $(target_boot_dir)
-src = $(src_boot_dir)
-zImage: compressed/vmlinuz
+OBJCOPY = objcopy-cris
+OBJCOPYFLAGS = -O binary --remove-section=.bss
-compressed/vmlinuz:
- @$(MAKE) -f $(src)/compressed/Makefile $(target_compressed_dir)/vmlinuz
+subdir- := compressed rescue
+targets := Image
-clean:
- @$(MAKE) -f $(src)/compressed/Makefile clean
+$(obj)/Image: vmlinux FORCE
+ $(call if_changed,objcopy)
+ @echo ' Kernel: $@ is ready'
+
+$(obj)/compressed/vmlinux: $(obj)/Image FORCE
+ $(Q)$(MAKE) $(build)=$(obj)/compressed $@
+ $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin
+
+$(obj)/zImage: $(obj)/compressed/vmlinux
+ @cp $< $@
+ @echo ' Kernel: $@ is ready'
#
-# create a compressed vmlinuz image from the binary vmlinux.bin file
+# arch/cris/arch-v10/boot/compressed/Makefile
#
-target = $(target_compressed_dir)
-src = $(src_compressed_dir)
CC = gcc-cris -melf $(LINUXINCLUDE)
-CFLAGS = -O2
+ccflags-y += -O2
LD = ld-cris
+ldflags-y += -T $(obj)/decompress.ld
+OBJECTS = $(obj)/head.o $(obj)/misc.o
OBJCOPY = objcopy-cris
OBJCOPYFLAGS = -O binary --remove-section=.bss
-OBJECTS = $(target)/head.o $(target)/misc.o
-# files to compress
-SYSTEM = $(objtree)/vmlinux.bin
+quiet_cmd_image = BUILD $@
+cmd_image = cat $(obj)/decompress.bin $(obj)/piggy.gz > $@
-all: $(target_compressed_dir)/vmlinuz
+targets := vmlinux piggy.gz decompress.o decompress.bin
-$(target)/decompress.bin: $(OBJECTS)
- $(LD) -T $(src)/decompress.ld -o $(target)/decompress.o $(OBJECTS)
- $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/decompress.o $(target)/decompress.bin
+$(obj)/decompress.o: $(OBJECTS) FORCE
+ $(call if_changed,ld)
-# Create vmlinuz image in top-level build directory
-$(target_compressed_dir)/vmlinuz: $(target) piggy.img $(target)/decompress.bin
- @echo " COMPR vmlinux.bin --> vmlinuz"
- @cat $(target)/decompress.bin piggy.img > $(target_compressed_dir)/vmlinuz
- @rm -f piggy.img
+$(obj)/decompress.bin: $(obj)/decompress.o FORCE
+ $(call if_changed,objcopy)
-$(target)/head.o: $(src)/head.S
- $(CC) -D__ASSEMBLY__ -traditional -c $< -o $@
+$(obj)/head.o: $(obj)/head.S .config
+ @$(CC) -D__ASSEMBLY__ -traditional -c $< -o $@
-$(target)/misc.o: $(src)/misc.c
- $(CC) -D__KERNEL__ -c $< -o $@
+$(obj)/misc.o: $(obj)/misc.c .config
+ @$(CC) -D__KERNEL__ -c $< -o $@
-# gzip the kernel image
+$(obj)/vmlinux: $(obj)/piggy.gz $(obj)/decompress.bin FORCE
+ $(call if_changed,image)
-piggy.img: $(SYSTEM)
- @cat $(SYSTEM) | gzip -f -9 > piggy.img
-
-$(target):
- mkdir -p $(target)
-
-clean:
- rm -f piggy.img $(objtree)/vmlinuz
+$(obj)/piggy.gz: $(obj)/../Image FORCE
+ $(call if_changed,gzip)
/*
* misc.c
*
- * $Id: misc.c,v 1.6 2003/10/27 08:04:31 starvik Exp $
- *
- * This is a collection of several routines from gzip-1.0.3
+ * This is a collection of several routines from gzip-1.0.3
* adapted for Linux.
*
* malloc by Hannu Savolainen 1993 and Matthias Urlichs 1994
* puts by Nick Holloway 1993, better puts by Martin Mares 1995
* adaptation for Linux/CRIS Axis Communications AB, 1999
- *
+ *
*/
/* where the piggybacked kernel image expects itself to live.
#
-# Makefile for rescue code
+# Makefile for rescue (bootstrap) code
#
-target = $(target_rescue_dir)
-src = $(src_rescue_dir)
CC = gcc-cris -mlinux $(LINUXINCLUDE)
-CFLAGS = -O2
+ccflags-y += -O2
+asflags-y += -traditional
LD = gcc-cris -mlinux -nostdlib
+ldflags-y += -T $(obj)/rescue.ld
OBJCOPY = objcopy-cris
OBJCOPYFLAGS = -O binary --remove-section=.bss
+obj-$(CONFIG_ETRAX_AXISFLASHMAP) = head.o
+OBJECT := $(obj)/head.o
-all: $(target)/rescue.bin $(target)/testrescue.bin $(target)/kimagerescue.bin
+targets := rescue.o rescue.bin
-$(target)/rescue.bin: $(target) $(target)/head.o
- $(LD) -T $(src)/rescue.ld -o $(target)/rescue.o $(target)/head.o
- $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/rescue.o $(target)/rescue.bin
-# Place a copy in top-level build directory
- cp -p $(target)/rescue.bin $(objtree)
+$(obj)/rescue.o: $(OBJECT) FORCE
+ $(call if_changed,ld)
-$(target)/testrescue.bin: $(target) $(target)/testrescue.o
- $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/testrescue.o tr.bin
+$(obj)/rescue.bin: $(obj)/rescue.o FORCE
+ $(call if_changed,objcopy)
+ cp -p $(obj)/rescue.bin $(objtree)
+
+$(obj)/testrescue.bin: $(obj)/testrescue.o
+ $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/testrescue.o tr.bin
# Pad it to 784 bytes
dd if=/dev/zero of=tmp2423 bs=1 count=784
cat tr.bin tmp2423 >testrescue_tmp.bin
- dd if=testrescue_tmp.bin of=$(target)/testrescue.bin bs=1 count=784
+ dd if=testrescue_tmp.bin of=$(obj)/testrescue.bin bs=1 count=784
rm tr.bin tmp2423 testrescue_tmp.bin
-$(target)/kimagerescue.bin: $(target) $(target)/kimagerescue.o
- $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/kimagerescue.o ktr.bin
+$(obj)/kimagerescue.bin: $(obj)/kimagerescue.o
+ $(OBJCOPY) $(OBJCOPYFLAGS) $(obj)/kimagerescue.o ktr.bin
# Pad it to 784 bytes, that's what the rescue loader expects
dd if=/dev/zero of=tmp2423 bs=1 count=784
cat ktr.bin tmp2423 >kimagerescue_tmp.bin
- dd if=kimagerescue_tmp.bin of=$(target)/kimagerescue.bin bs=1 count=784
+ dd if=kimagerescue_tmp.bin of=$(obj)/kimagerescue.bin bs=1 count=784
rm ktr.bin tmp2423 kimagerescue_tmp.bin
-
-$(target):
- mkdir -p $(target)
-
-$(target)/head.o: $(src)/head.S
- $(CC) -D__ASSEMBLY__ -traditional -c $< -o $*.o
-
-$(target)/testrescue.o: $(src)/testrescue.S
- $(CC) -D__ASSEMBLY__ -traditional -c $< -o $*.o
-
-$(target)/kimagerescue.o: $(src)/kimagerescue.S
- $(CC) -D__ASSEMBLY__ -traditional -c $< -o $*.o
-
-clean:
- rm -f $(target)/*.o $(target)/*.bin
-
-fastdep:
-
-modules:
-
-modules-install:
-/* $Id: head.S,v 1.7 2005/03/07 12:11:06 starvik Exp $
- *
+/*
* Rescue code, made to reside at the beginning of the
* flash-memory. when it starts, it checks a partition
* table at the first sector after the rescue sector.
* Partition table format:
*
* Code transparency:
- *
+ *
* 2 bytes [opcode 'nop']
* 2 bytes [opcode 'di']
* 4 bytes [opcode 'ba <offset>', 8-bit or 16-bit version]
* 2 bytes [opcode 'nop', delay slot]
*
- * Table validation (at +10):
- *
+ * Table validation (at +10):
+ *
* 2 bytes [magic/version word for partitiontable - 0xef, 0xbe]
* 2 bytes [length of all entries plus the end marker]
* 4 bytes [checksum for the partitiontable itself]
*
- * Entries, each with the following format, last has offset -1:
- *
+ * Entries, each with the following format, last has offset -1:
+ *
* 4 bytes [offset in bytes, from start of flash]
* 4 bytes [length in bytes of partition]
* 4 bytes [checksum, simple longword sum]
* End marker
*
* 4 bytes [-1]
- *
+ *
* 10 bytes [0, padding]
- *
+ *
* Bit 0 in flags signifies RW or RO. The rescue code only bothers
* to check the checksum for RO partitions, since the others will
* change their data without updating the checksums. A 1 in bit 0
*
* During the wait for serial input, the status LED will flash so the
* user knows something went wrong.
- *
- * Copyright (C) 1999, 2000, 2001, 2002, 2003 Axis Communications AB
+ *
+ * Copyright (C) 1999-2007 Axis Communications AB
*/
+#ifdef CONFIG_ETRAX_AXISFLASHMAP
+
#define ASSEMBLER_MACROS_ONLY
#include <asm/arch/sv_addr_ag.h>
;; The partitiontable is looked for at the first sector after the boot
;; sector. Sector size is 65536 bytes in all flashes we use.
-
+
#define PTABLE_START CONFIG_ETRAX_PTABLE_SECTOR
#define PTABLE_MAGIC 0xbeef
;; The normal Etrax100 on-chip boot ROM does serial boot at 0x380000f0.
- ;; That is not where we put our downloaded serial boot-code. The length is
- ;; enough for downloading code that loads the rest of itself (after
- ;; having setup the DRAM etc). It is the same length as the on-chip
- ;; ROM loads, so the same host loader can be used to load a rescued
- ;; product as well as one booted through the Etrax serial boot code.
-
+ ;; That is not where we put our downloaded serial boot-code.
+ ;; The length is enough for downloading code that loads the rest
+ ;; of itself (after having setup the DRAM etc).
+ ;; It is the same length as the on-chip ROM loads, so the same
+ ;; host loader can be used to load a rescued product as well as
+ ;; one booted through the Etrax serial boot code.
+
#define CODE_START 0x40000000
#define CODE_LENGTH 784
#define SERRECC R_SERIAL2_REC_CTRL
#define SERRDAT R_SERIAL2_REC_DATA
#define SERSTAT R_SERIAL2_STATUS
-#endif
+#endif
#ifdef CONFIG_ETRAX_RESCUE_SER3
#define SERXOFF R_SERIAL3_XOFF
#define SERBAUD R_SERIAL3_BAUD
#define RAM_INIT_MAGIC 0x56902387
.text
-
+
;; This is the entry point of the rescue code
;; 0x80000000 if loaded in flash (as it should be)
- ;; since etrax actually starts at address 2 when booting from flash, we
+ ;; Since etrax actually starts at address 2 when booting from flash, we
;; put a nop (2 bytes) here first so we dont accidentally skip the di
- nop
+ nop
di
jump in_cache ; enter cached area instead
in_cache:
- ;; first put a jump test to give a possibility of upgrading the rescue code
- ;; without erasing/reflashing the sector. we put a longword of -1 here and if
- ;; it is not -1, we jump using the value as jump target. since we can always
- ;; change 1's to 0's without erasing the sector, it is possible to add new
+ ;; First put a jump test to give a possibility of upgrading the
+ ;; rescue code without erasing/reflashing the sector.
+ ;; We put a longword of -1 here and if it is not -1, we jump using
+ ;; the value as jump target. Since we can always change 1's to 0's
+ ;; without erasing the sector, it is possible to add new
;; code after this and altering the jumptarget in an upgrade.
jtcd: move.d [jumptarget], $r0
cmp.d 0xffffffff, $r0
beq no_newjump
nop
-
+
jump [$r0]
-jumptarget:
+jumptarget:
.dword 0xffffffff ; can be overwritten later to insert new code
-
+
no_newjump:
-#ifdef CONFIG_ETRAX_ETHERNET
+#ifdef CONFIG_ETRAX_ETHERNET
;; Start MII clock to make sure it is running when tranceiver is reset
move.d 0x3, $r0 ; enable = on, phy = mii_clk
move.d $r0, [R_NETWORK_GEN_CONFIG]
#endif
-
+
;; We need to setup the bus registers before we start using the DRAM
#include "../../lib/dram_init.S"
;; we now should go through the checksum-table and check the listed
;; partitions for errors.
-
+
move.d PTABLE_START, $r3
move.d [$r3], $r0
cmp.d NOP_DI, $r0 ; make sure the nop/di is there...
bne do_rescue
nop
-
+
;; skip the code transparency block (10 bytes).
addq 10, $r3
-
+
;; check for correct magic
-
+
move.w [$r3+], $r0
cmp.w PTABLE_MAGIC, $r0
bne do_rescue ; didn't recognize - trig rescue
cmp.d $r0, $r4
bne do_rescue ; didn't match - trig rescue
nop
-
+
;; ptable is ok. validate each entry.
moveq -1, $r7
-
+
ploop: move.d [$r3+], $r1 ; partition offset (from ptable start)
bne notfirst ; check if it is the partition containing ptable
nop ; yes..
sub.d $r8, $r2 ; minus the ptable length
ba bosse
nop
-notfirst:
+notfirst:
cmp.d -1, $r1 ; the end of the ptable ?
beq flash_ok ; if so, the flash is validated
move.d [$r3+], $r2 ; partition length
bpl 1f
nop
move.d $r1, $r7 ; remember boot partition offset
-1:
-
+1:
add.d PTABLE_START, $r1
-
+
jsr checksum ; checksum the partition
-
+
cmp.d $r0, $r5
beq ploop ; checksums matched, go to next entry
nop
;; otherwise fall through to the rescue code.
-
+
do_rescue:
;; setup port PA and PB default initial directions and data
;; (so we can flash LEDs, and so that DTR and others are set)
-
+
move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0
move.b $r0, [R_PORT_PA_DIR]
move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0
move.b $r0, [R_PORT_PA_DATA]
-
+
move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0
move.b $r0, [R_PORT_PB_DIR]
move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0
move.b $r0, [R_PORT_PB_DATA]
;; setup the serial port at 115200 baud
-
+
moveq 0, $r0
- move.d $r0, [SERXOFF]
+ move.d $r0, [SERXOFF]
move.b 0x99, $r0
- move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit and receive
+ move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit and receive
- move.b 0x40, $r0 ; rec enable
- move.b $r0, [SERRECC]
+ move.b 0x40, $r0 ; rec enable
+ move.b $r0, [SERRECC]
moveq 0, $r1 ; "timer" to clock out a LED red flash
move.d CODE_START, $r3 ; destination counter
movu.w CODE_LENGTH, $r4; length
-
+
wait_ser:
addq 1, $r1
#ifndef CONFIG_ETRAX_NO_LEDS
nop
1: not $r0 ; clear bit
and.d $r0, $r2
-2:
+2:
#ifdef CONFIG_ETRAX_PA_LEDS
- move.b $r2, [R_PORT_PA_DATA]
-#endif
+ move.b $r2, [R_PORT_PA_DATA]
+#endif
#ifdef CONFIG_ETRAX_PB_LEDS
- move.b $r2, [R_PORT_PB_DATA]
+ move.b $r2, [R_PORT_PB_DATA]
#endif
#ifdef CONFIG_ETRAX_90000000_LEDS
move.b $r2, [0x90000000]
#endif
#endif
-
+
;; check if we got something on the serial port
-
+
move.b [SERSTAT], $r0
btstq 0, $r0 ; data_avail
bpl wait_ser
move.b [SERRDAT], $r0
move.b $r0, [$r3+]
-
+
subq 1, $r4 ; decrease length
bne wait_ser
nop
;; jump into downloaded code
- move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is initialized
+ move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is
+ ; initialized
jump CODE_START
flash_ok:
nop
move.d PTABLE_START, $r7; otherwise use the ptable start
1:
- move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is initialized
+ move.d RAM_INIT_MAGIC, $r8 ; Tell next product that DRAM is
+ ; initialized
jump $r7 ; boot!
moveq 0, $r0
moveq CONFIG_ETRAX_FLASH1_SIZE, $r6
- ;; If the first physical flash memory is exceeded wrap to the second one.
+ ;; If the first physical flash memory is exceeded wrap to the
+ ;; second one
btstq 26, $r1 ; Are we addressing first flash?
bpl 1f
nop
3: move.d MEM_CSE1_START, $r1 ; wrap to second flash
ba 2b
nop
+
+#endif
-/* $Id: kimagerescue.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
- *
+/*
* Rescue code to be prepended on a kimage and copied to the
* rescue serial port.
* This is called from the rescue code, it will copy received data to
*/
#define ASSEMBLER_MACROS_ONLY
-#include <asm/sv_addr_ag.h>
+#include <asm/arch/sv_addr_ag.h>
#define CODE_START 0x40004000
#define CODE_LENGTH 784
#define TIMEOUT_VALUE 1000
-
-
+
+
#ifdef CONFIG_ETRAX_RESCUE_SER0
#define SERXOFF R_SERIAL0_XOFF
#define SERBAUD R_SERIAL0_BAUD
#define SERRECC R_SERIAL2_REC_CTRL
#define SERRDAT R_SERIAL2_REC_DATA
#define SERSTAT R_SERIAL2_STATUS
-#endif
+#endif
#ifdef CONFIG_ETRAX_RESCUE_SER3
#define SERXOFF R_SERIAL3_XOFF
#define SERBAUD R_SERIAL3_BAUD
;; 0x80000000 if loaded in flash (as it should be)
;; since etrax actually starts at address 2 when booting from flash, we
;; put a nop (2 bytes) here first so we dont accidentally skip the di
-
- nop
+
+ nop
di
-#ifndef CONFIG_SVINTO_SIM
+#ifndef CONFIG_SVINTO_SIM
;; setup port PA and PB default initial directions and data
;; (so we can flash LEDs, and so that DTR and others are set)
-
+
move.b CONFIG_ETRAX_DEF_R_PORT_PA_DIR, $r0
move.b $r0, [R_PORT_PA_DIR]
move.b CONFIG_ETRAX_DEF_R_PORT_PA_DATA, $r0
move.b $r0, [R_PORT_PA_DATA]
-
+
move.b CONFIG_ETRAX_DEF_R_PORT_PB_DIR, $r0
move.b $r0, [R_PORT_PB_DIR]
move.b CONFIG_ETRAX_DEF_R_PORT_PB_DATA, $r0
move.b $r0, [R_PORT_PB_DATA]
-
+
;; We need to setup the bus registers before we start using the DRAM
#include "../../lib/dram_init.S"
-
+
#endif
;; Setup the stack to a suitably high address.
;; We assume 8 MB is the minimum DRAM in an eLinux
;; product and put the sp at the top for now.
move.d 0x40800000, $sp
-
+
;; setup the serial port at 115200 baud
-
+
moveq 0, $r0
- move.d $r0, [SERXOFF]
+ move.d $r0, [SERXOFF]
move.b 0x99, $r0
- move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit and receive
+ move.b $r0, [SERBAUD] ; 115.2kbaud for both transmit
+ ; and receive
move.b 0x40, $r0 ; rec enable
- move.b $r0, [SERRECC]
+ move.b $r0, [SERRECC]
- moveq 0, $r1 ; "timer" to clock out a LED red flash
- move.d CODE_START, $r3 ; destination counter
+ moveq 0, $r1 ; "timer" to clock out a LED red flash
+ move.d CODE_START, $r3 ; destination counter
move.d CODE_LENGTH, $r4 ; length
move.d TIMEOUT_VALUE, $r5 ; "timeout" until jump
wait_ser:
addq 1, $r1
- subq 1, $r5 ; decrease timeout
- beq jump_start ; timed out
+ subq 1, $r5 ; decrease timeout
+ beq jump_start ; timed out
nop
#ifndef CONFIG_ETRAX_NO_LEDS
#ifdef CONFIG_ETRAX_PA_LEDS
or.d $r0, $r2 ; set bit
ba 2f
nop
-1: not $r0 ; clear bit
+1: not $r0 ; clear bit
and.d $r0, $r2
-2:
+2:
#ifdef CONFIG_ETRAX_PA_LEDS
move.b $r2, [R_PORT_PA_DATA]
-#endif
+#endif
#ifdef CONFIG_ETRAX_PB_LEDS
move.b $r2, [R_PORT_PB_DATA]
#endif
#endif
-
+
;; check if we got something on the serial port
-
+
move.b [SERSTAT], $r0
- btstq 0, $r0 ; data_avail
+ btstq 0, $r0 ; data_avail
bpl wait_ser
nop
move.b [SERRDAT], $r0
move.b $r0, [$r3+]
move.d TIMEOUT_VALUE, $r5 ; reset "timeout"
- subq 1, $r4 ; decrease length
+ subq 1, $r4 ; decrease length
bne wait_ser
nop
jump_start:
-/* $Id: testrescue.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
- *
+/*
* Simple testcode to download by the rescue block.
- * Just lits some LEDs to show it was downloaded correctly.
- *
+ * Just lights some LEDs to show it was downloaded correctly.
+ *
* Copyright (C) 1999 Axis Communications AB
*/
#define ASSEMBLER_MACROS_ONLY
-#include <asm/sv_addr_ag.h>
+#include <asm/arch/sv_addr_ag.h>
.text
moveq -1, $r2
move.b $r2, [R_PORT_PA_DIR]
moveq 0, $r2
- move.b $r2, [R_PORT_PA_DATA]
+ move.b $r2, [R_PORT_PA_DATA]
endless:
nop
ba endless
nop
-
This option enables the ETRAX 100LX built-in 10/100Mbit Ethernet
controller.
-choice
- prompt "Network LED behavior"
- depends on ETRAX_ETHERNET
- default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
-
-config ETRAX_NETWORK_LED_ON_WHEN_LINK
- bool "LED_on_when_link"
- help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
-
- Selecting LED_on_when_activity will light the LED only when
- there is activity.
-
- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
-
-config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
- bool "LED_on_when_activity"
- help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
-
- Selecting LED_on_when_activity will light the LED only when
- there is activity.
-
- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
-
-endchoice
-
config ETRAX_SERIAL
bool "Serial-port support"
depends on ETRAX_ARCH_V10
Normally you want this on, unless you use external DMA 1 that uses
the same DMA channels.
-choice
- prompt "Ser0 DMA out assignment"
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_DMA6_OUT
-
-config ETRAX_SERIAL_PORT0_NO_DMA_OUT
- bool "No DMA out"
-
-config ETRAX_SERIAL_PORT0_DMA6_OUT
- bool "DMA 6"
-
-endchoice
-
-choice
- prompt "Ser0 DMA in assignment"
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_DMA7_IN
-
-config ETRAX_SERIAL_PORT0_NO_DMA_IN
- bool "No DMA in"
-
-config ETRAX_SERIAL_PORT0_DMA7_IN
- bool "DMA 7"
-
-endchoice
-
choice
prompt "Ser0 DTR, RI, DSR and CD assignment"
depends on ETRAX_SERIAL_PORT0
help
Enables the ETRAX 100 serial driver for ser1 (ttyS1).
-choice
- prompt "Ser1 DMA out assignment"
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_DMA8_OUT
-
-config ETRAX_SERIAL_PORT1_NO_DMA_OUT
- bool "No DMA out"
-
-config ETRAX_SERIAL_PORT1_DMA8_OUT
- bool "DMA 8"
-
-endchoice
-
-choice
- prompt "Ser1 DMA in assignment"
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_DMA9_IN
-
-config ETRAX_SERIAL_PORT1_NO_DMA_IN
- bool "No DMA in"
-
-config ETRAX_SERIAL_PORT1_DMA9_IN
- bool "DMA 9"
-
-endchoice
-
choice
prompt "Ser1 DTR, RI, DSR and CD assignment"
depends on ETRAX_SERIAL_PORT1
help
Enables the ETRAX 100 serial driver for ser2 (ttyS2).
-choice
- prompt "Ser2 DMA out assignment"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_DMA2_OUT
-
-config ETRAX_SERIAL_PORT2_NO_DMA_OUT
- bool "No DMA out"
-
-config ETRAX_SERIAL_PORT2_DMA2_OUT
- bool "DMA 2"
-
-endchoice
-
-choice
- prompt "Ser2 DMA in assignment"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_DMA3_IN
-
-config ETRAX_SERIAL_PORT2_NO_DMA_IN
- bool "No DMA in"
-
-config ETRAX_SERIAL_PORT2_DMA3_IN
- bool "DMA 3"
-
-endchoice
-
choice
prompt "Ser2 DTR, RI, DSR and CD assignment"
depends on ETRAX_SERIAL_PORT2
help
Enables the ETRAX 100 serial driver for ser3 (ttyS3).
-choice
- prompt "Ser3 DMA out assignment"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_DMA4_OUT
-
-config ETRAX_SERIAL_PORT3_NO_DMA_OUT
- bool "No DMA out"
-
-config ETRAX_SERIAL_PORT3_DMA4_OUT
- bool "DMA 4"
-
-endchoice
-
-choice
- prompt "Ser3 DMA in assignment"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_DMA5_IN
-
-config ETRAX_SERIAL_PORT3_NO_DMA_IN
- bool "No DMA in"
-
-config ETRAX_SERIAL_PORT3_DMA5_IN
- bool "DMA 5"
-
-endchoice
-
choice
prompt "Ser3 DTR, RI, DSR and CD assignment"
depends on ETRAX_SERIAL_PORT3
depends on ETRAX_USB_HOST
default n
-config ETRAX_AXISFLASHMAP
- bool "Axis flash-map support"
- depends on ETRAX_ARCH_V10
- select MTD
- select MTD_CFI
- select MTD_CFI_AMDSTD
- select MTD_CHAR
- select MTD_BLOCK
- select MTD_PARTITIONS
- select MTD_CONCAT
- select MTD_COMPLEX_MAPPINGS
- help
- This option enables MTD mapping of flash devices. Needed to use
- flash memories. If unsure, say Y.
-
config ETRAX_PTABLE_SECTOR
int "Byte-offset of partition table sector"
depends on ETRAX_AXISFLASHMAP
Bit set = changeable.
You probably want 00 here.
-config ETRAX_RTC
- bool "Real Time Clock support"
- depends on ETRAX_ARCH_V10
- help
- Enables drivers for the Real-Time Clock battery-backed chips on
- some products. The kernel reads the time when booting, and
- the date can be set using ioctl(fd, RTC_SET_TIME, &rt) with rt a
- rtc_time struct (see <file:include/asm-cris/rtc.h>) on the /dev/rtc
- device, major 121. You can check the time with cat /proc/rtc, but
- normal time reading should be done using libc function time and
- friends.
-
-choice
- prompt "RTC chip"
- depends on ETRAX_RTC
- default ETRAX_DS1302
-
-config ETRAX_DS1302
- bool "DS1302"
- help
- Enables the driver for the DS1302 Real-Time Clock battery-backed
- chip on some products.
-
-config ETRAX_PCF8563
- bool "PCF8563"
- help
- Enables the driver for the PCF8563 Real-Time Clock battery-backed
- chip on some products.
-
-endchoice
-
config ETRAX_DS1302_RST_ON_GENERIC_PORT
bool "DS1302 RST on Generic Port"
depends on ETRAX_DS1302
# Makefile for Etrax-specific drivers
#
-obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o
-obj-$(CONFIG_ETRAX_I2C) += i2c.o
-obj-$(CONFIG_ETRAX_I2C_EEPROM) += eeprom.o
-obj-$(CONFIG_ETRAX_GPIO) += gpio.o
-obj-$(CONFIG_ETRAX_DS1302) += ds1302.o
+obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o
+obj-$(CONFIG_ETRAX_I2C) += i2c.o
+obj-$(CONFIG_ETRAX_I2C_EEPROM) += eeprom.o
+obj-$(CONFIG_ETRAX_GPIO) += gpio.o
+obj-$(CONFIG_ETRAX_DS1302) += ds1302.o
obj-$(CONFIG_ETRAX_PCF8563) += pcf8563.o
-
+obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o
* tells us what other partitions to define. If there isn't, we use a default
* partition split defined below.
*
- * $Log: axisflashmap.c,v $
- * Revision 1.11 2004/11/15 10:27:14 starvik
- * Corrected typo (Thanks to Milton Miller <miltonm@bga.com>).
- *
- * Revision 1.10 2004/08/16 12:37:22 starvik
- * Merge of Linux 2.6.8
- *
- * Revision 1.8 2004/05/14 07:58:03 starvik
- * Merge of changes from 2.4
- *
- * Revision 1.6 2003/07/04 08:27:37 starvik
- * Merge of Linux 2.5.74
- *
- * Revision 1.5 2002/12/11 13:13:57 starvik
- * Added arch/ to v10 specific includes
- * Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
- *
- * Revision 1.4 2002/11/20 11:56:10 starvik
- * Merge of Linux 2.5.48
- *
- * Revision 1.3 2002/11/13 14:54:13 starvik
- * Copied from linux 2.4
- *
- * Revision 1.28 2002/10/01 08:08:43 jonashg
- * The first partition ends at the start of the partition table.
- *
- * Revision 1.27 2002/08/21 09:23:13 jonashg
- * Speling.
- *
- * Revision 1.26 2002/08/21 08:35:20 jonashg
- * Cosmetic change to printouts.
- *
- * Revision 1.25 2002/08/21 08:15:42 jonashg
- * Made it compile even without CONFIG_MTD_CONCAT defined.
- *
- * Revision 1.24 2002/08/20 13:12:35 jonashg
- * * New approach to probing. Probe cse0 and cse1 separately and (mtd)concat
- * the results.
- * * Removed compile time tests concerning how the mtdram driver has been
- * configured. The user will know about the misconfiguration at runtime
- * instead. (The old approach made it impossible to use mtdram for anything
- * else than RAM boot).
- *
- * Revision 1.23 2002/05/13 12:12:28 johana
- * Allow compile without CONFIG_MTD_MTDRAM but warn at compiletime and
- * be informative at runtime.
- *
- * Revision 1.22 2002/05/13 10:24:44 johana
- * Added #if checks on MTDRAM CONFIG
- *
- * Revision 1.21 2002/05/06 16:05:20 johana
- * Removed debug printout.
- *
- * Revision 1.20 2002/05/06 16:03:00 johana
- * No more cramfs as root hack in generic code.
- * It's handled by axisflashmap using mtdram.
- *
- * Revision 1.19 2002/03/15 17:10:28 bjornw
- * Changed comment about cached access since we changed this before
- *
- * Revision 1.18 2002/03/05 17:06:15 jonashg
- * Try amd_flash probe before cfi_probe since amd_flash driver can handle two
- * (or more) flash chips of different model and the cfi driver cannot.
- *
- * Revision 1.17 2001/11/12 19:42:38 pkj
- * Fixed compiler warnings.
- *
- * Revision 1.16 2001/11/08 11:18:58 jonashg
- * Always read from uncached address to avoid problems with flushing
- * cachelines after write and MTD-erase. No performance loss have been
- * seen yet.
- *
- * Revision 1.15 2001/10/19 12:41:04 jonashg
- * Name of probe has changed in MTD.
- *
- * Revision 1.14 2001/09/21 07:14:10 jonashg
- * Made root filesystem (cramfs) use mtdblock driver when booting from flash.
- *
- * Revision 1.13 2001/08/15 13:57:35 jonashg
- * Entire MTD updated to the linux 2.4.7 version.
- *
- * Revision 1.12 2001/06/11 09:50:30 jonashg
- * Oops, 2MB is 0x200000 bytes.
- *
- * Revision 1.11 2001/06/08 11:39:44 jonashg
- * Changed sizes and offsets in axis_default_partitions to use
- * CONFIG_ETRAX_PTABLE_SECTOR.
- *
- * Revision 1.10 2001/05/29 09:42:03 jonashg
- * Use macro for end marker length instead of sizeof.
- *
- * Revision 1.9 2001/05/29 08:52:52 jonashg
- * Gave names to the magic fours (size of the ptable end marker).
- *
- * Revision 1.8 2001/05/28 15:36:20 jonashg
- * * Removed old comment about ptable location in flash (it's a CONFIG_ option).
- * * Variable ptable was initialized twice to the same value.
- *
- * Revision 1.7 2001/04/05 13:41:46 markusl
- * Updated according to review remarks
- *
- * Revision 1.6 2001/03/07 09:21:21 bjornw
- * No need to waste .data
- *
- * Revision 1.5 2001/03/06 16:27:01 jonashg
- * Probe the entire flash area for flash devices.
- *
- * Revision 1.4 2001/02/23 12:47:15 bjornw
- * Uncached flash in LOW_MAP moved from 0xe to 0x8
- *
- * Revision 1.3 2001/02/16 12:11:45 jonashg
- * MTD driver amd_flash is now included in MTD CVS repository.
- * (It's now in drivers/mtd).
- *
- * Revision 1.2 2001/02/09 11:12:22 jonashg
- * Support for AMD compatible non-CFI flash chips.
- * Only tested with Toshiba TC58FVT160 so far.
- *
- * Revision 1.1 2001/01/12 17:01:18 bjornw
- * * Added axisflashmap.c, a physical mapping for MTD that reads and understands
- * Axis partition-table format.
- *
- *
*/
#include <linux/module.h>
};
/* If no partition-table was found, we use this default-set. */
-#define MAX_PARTITIONS 7
+#define MAX_PARTITIONS 7
#define NUM_DEFAULT_PARTITIONS 3
/*
},
};
+#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
+/* Main flash device */
+static struct mtd_partition main_partition = {
+ .name = "main",
+ .size = 0,
+ .offset = 0
+};
+#endif
+
/*
* Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash
* chips in that order (because the amd_flash-driver is faster).
mtd_cs = do_map_probe("cfi_probe", map_cs);
#endif
#ifdef CONFIG_MTD_JEDECPROBE
- if (!mtd_cs) {
+ if (!mtd_cs)
mtd_cs = do_map_probe("jedec_probe", map_cs);
- }
#endif
return mtd_cs;
}
-/*
+/*
* Probe each chip select individually for flash chips. If there are chips on
* both cse0 and cse1, the mtd_info structs will be concatenated to one struct
* so that MTD partitions can cross chip boundries.
if (mtd_cse0 && mtd_cse1) {
#ifdef CONFIG_MTD_CONCAT
struct mtd_info *mtds[] = { mtd_cse0, mtd_cse1 };
-
+
/* Since the concatenation layer adds a small overhead we
* could try to figure out if the chips in cse0 and cse1 are
* identical and reprobe the whole cse0+cse1 window. But since
/* The best we can do now is to only use what we found
* at cse0.
- */
+ */
mtd_cse = mtd_cse0;
map_destroy(mtd_cse1);
}
struct partitiontable_head *ptable_head = NULL;
struct partitiontable_entry *ptable;
int use_default_ptable = 1; /* Until proven otherwise. */
- const char *pmsg = " /dev/flash%d at 0x%08x, size 0x%08x\n";
+ const char pmsg[] = " /dev/flash%d at 0x%08x, size 0x%08x\n";
if (!(mymtd = flash_probe())) {
/* There's no reason to use this module if no flash chip can
unsigned long offset = CONFIG_ETRAX_PTABLE_SECTOR;
unsigned char *p;
unsigned long csum = 0;
-
+
ptable = (struct partitiontable_entry *)
((unsigned long)ptable_head + sizeof(*ptable_head));
pidx++;
}
+#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
+ if (mymtd) {
+ main_partition.size = mymtd->size;
+ err = add_mtd_partitions(mymtd, &main_partition, 1);
+ if (err)
+ panic("axisflashmap: Could not initialize "
+ "partition for whole main mtd device!\n");
+ }
+#endif
+
if (mymtd) {
if (use_default_ptable) {
printk(KERN_INFO " Using default partition table.\n");
err = add_mtd_partitions(mymtd, axis_partitions, pidx);
}
- if (err) {
+ if (err)
panic("axisflashmap could not add MTD partitions!\n");
- }
}
if (!romfs_in_flash) {
#else
struct mtd_info *mtd_ram;
- mtd_ram = kmalloc(sizeof(struct mtd_info),
- GFP_KERNEL);
- if (!mtd_ram) {
+ mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
+ if (!mtd_ram)
panic("axisflashmap couldn't allocate memory for "
"mtd_info!\n");
- }
printk(KERN_INFO " Adding RAM partition for romfs image:\n");
- printk(pmsg, pidx, romfs_start, romfs_length);
-
- err = mtdram_init_device(mtd_ram, (void*)romfs_start,
- romfs_length, "romfs");
- if (err) {
+ printk(pmsg, pidx, (unsigned)romfs_start,
+ (unsigned)romfs_length);
+
+ err = mtdram_init_device(mtd_ram,
+ (void *)romfs_start,
+ romfs_length,
+ "romfs");
+ if (err)
panic("axisflashmap could not initialize MTD RAM "
"device!\n");
- }
#endif
}
-
return err;
}
ds1302_writereg(RTC_TRICKLECHARGER, tcs_val);
return 0;
}
- case RTC_VLOW_RD:
+ case RTC_VL_READ:
{
/* TODO:
* Implement voltage low detection support
" is not supported\n");
return 0;
}
- case RTC_VLOW_SET:
+ case RTC_VL_CLR:
{
/* TODO:
* Nothing to do since Voltage Low detection is not supported
*! Sep 03 1999 Edgar Iglesias Added bail-out stuff if we get interrupted
*! in the spin-lock.
*!
-*! $Log: eeprom.c,v $
-*! Revision 1.12 2005/06/19 17:06:46 starvik
-*! Merge of Linux 2.6.12.
-*!
-*! Revision 1.11 2005/01/26 07:14:46 starvik
-*! Applied diff from kernel janitors (Nish Aravamudan).
-*!
-*! Revision 1.10 2003/09/11 07:29:48 starvik
-*! Merge of Linux 2.6.0-test5
-*!
-*! Revision 1.9 2003/07/04 08:27:37 starvik
-*! Merge of Linux 2.5.74
-*!
-*! Revision 1.8 2003/04/09 05:20:47 starvik
-*! Merge of Linux 2.5.67
-*!
-*! Revision 1.6 2003/02/10 07:19:28 starvik
-*! Removed misplaced ;
-*!
-*! Revision 1.5 2002/12/11 13:13:57 starvik
-*! Added arch/ to v10 specific includes
-*! Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
-*!
-*! Revision 1.4 2002/11/20 11:56:10 starvik
-*! Merge of Linux 2.5.48
-*!
-*! Revision 1.3 2002/11/18 13:16:06 starvik
-*! Linux 2.5 port of latest 2.4 drivers
-*!
-*! Revision 1.8 2001/06/15 13:24:29 jonashg
-*! * Added verification of pointers from userspace in read and write.
-*! * Made busy counter volatile.
-*! * Added define for initial write delay.
-*! * Removed warnings by using loff_t instead of unsigned long.
-*!
-*! Revision 1.7 2001/06/14 15:26:54 jonashg
-*! Removed test because condition is always true.
-*!
-*! Revision 1.6 2001/06/14 15:18:20 jonashg
-*! Kb -> kB (makes quite a difference if you don't know if you have 2k or 16k).
-*!
-*! Revision 1.5 2001/06/14 14:39:51 jonashg
-*! Forgot to use name when registering the driver.
-*!
-*! Revision 1.4 2001/06/14 14:35:47 jonashg
-*! * Gave driver a name and used it in printk's.
-*! * Cleanup.
-*!
-*! Revision 1.3 2001/03/19 16:04:46 markusl
-*! Fixed init of fops struct
-*!
-*! Revision 1.2 2001/03/19 10:35:07 markusl
-*! 2.4 port of eeprom driver
-*!
-*! Revision 1.8 2000/05/18 10:42:25 edgar
-*! Make sure to end write cycle on _every_ write
-*!
-*! Revision 1.7 2000/01/17 17:41:01 johana
-*! Adjusted probing and return -ENOSPC when writing outside EEPROM
-*!
-*! Revision 1.6 2000/01/17 15:50:36 johana
-*! Added adaptive timing adjustments and fixed autoprobing for 2k and 16k(?)
-*! EEPROMs
-*!
-*! Revision 1.5 1999/09/03 15:07:37 edgar
-*! Added bail-out check to the spinlock
-*!
-*! Revision 1.4 1999/09/03 12:11:17 bjornw
-*! Proper atomicity (need to use spinlocks, not if's). users -> busy.
-*!
-*!
*! (c) 1999 Axis Communications AB, Lund, Sweden
*!*****************************************************************************/
#include <asm/uaccess.h>
#include "i2c.h"
-#define D(x)
+#define D(x)
/* If we should use adaptive timing or not: */
-//#define EEPROM_ADAPTIVE_TIMING
+/* #define EEPROM_ADAPTIVE_TIMING */
#define EEPROM_MAJOR_NR 122 /* use a LOCAL/EXPERIMENTAL major for now */
#define EEPROM_MINOR_NR 0
-/* $Id: gpio.c,v 1.17 2005/06/19 17:06:46 starvik Exp $
- *
+/*
* Etrax general port I/O device
*
- * Copyright (c) 1999, 2000, 2001, 2002 Axis Communications AB
+ * Copyright (c) 1999-2007 Axis Communications AB
*
* Authors: Bjorn Wesen (initial version)
* Ola Knutsson (LED handling)
* Johan Adolfsson (read/set directions, write, port G)
- *
- * $Log: gpio.c,v $
- * Revision 1.17 2005/06/19 17:06:46 starvik
- * Merge of Linux 2.6.12.
- *
- * Revision 1.16 2005/03/07 13:02:29 starvik
- * Protect driver global states with spinlock
- *
- * Revision 1.15 2005/01/05 06:08:55 starvik
- * No need to do local_irq_disable after local_irq_save.
- *
- * Revision 1.14 2004/12/13 12:21:52 starvik
- * Added I/O and DMA allocators from Linux 2.4
- *
- * Revision 1.12 2004/08/24 07:19:59 starvik
- * Whitespace cleanup
- *
- * Revision 1.11 2004/05/14 07:58:03 starvik
- * Merge of changes from 2.4
- *
- * Revision 1.9 2003/09/11 07:29:48 starvik
- * Merge of Linux 2.6.0-test5
- *
- * Revision 1.8 2003/07/04 08:27:37 starvik
- * Merge of Linux 2.5.74
- *
- * Revision 1.7 2003/01/10 07:44:07 starvik
- * init_ioremap is now called by kernel before drivers are initialized
- *
- * Revision 1.6 2002/12/11 13:13:57 starvik
- * Added arch/ to v10 specific includes
- * Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
- *
- * Revision 1.5 2002/11/20 11:56:11 starvik
- * Merge of Linux 2.5.48
- *
- * Revision 1.4 2002/11/18 10:10:05 starvik
- * Linux 2.5 port of latest gpio.c from Linux 2.4
- *
- * Revision 1.20 2002/10/16 21:16:24 johana
- * Added support for PA high level interrupt.
- * That gives 2ms response time with iodtest for high levels and 2-12 ms
- * response time on low levels if the check is not made in
- * process.c:cpu_idle() as well.
- *
- * Revision 1.19 2002/10/14 18:27:33 johana
- * Implemented alarm handling so select() now works.
- * Latency is around 6-9 ms with a etrax_gpio_wake_up_check() in
- * cpu_idle().
- * Otherwise I get 15-18 ms (same as doing the poll in userspace -
- * but less overhead).
- * TODO? Perhaps we should add the check in IMMEDIATE_BH (or whatever it
- * is in 2.4) as well?
- * TODO? Perhaps call request_irq()/free_irq() only when needed?
- * Increased version to 2.5
- *
- * Revision 1.18 2002/10/11 15:02:00 johana
- * Mask inverted 8 bit value in setget_input().
- *
- * Revision 1.17 2002/06/17 15:53:01 johana
- * Added IO_READ_INBITS, IO_READ_OUTBITS, IO_SETGET_INPUT and IO_SETGET_OUTPUT
- * that take a pointer as argument and thus can handle 32 bit ports (G)
- * correctly.
- * These should be used instead of IO_READBITS, IO_SETINPUT and IO_SETOUTPUT.
- * (especially if Port G bit 31 is used)
- *
- * Revision 1.16 2002/06/17 09:59:51 johana
- * Returning 32 bit values in the ioctl return value doesn't work if bit
- * 31 is set (could happen for port G), so mask it of with 0x7FFFFFFF.
- * A new set of ioctl's will be added.
- *
- * Revision 1.15 2002/05/06 13:19:13 johana
- * IO_SETINPUT returns mask with bit set = inputs for PA and PB as well.
- *
- * Revision 1.14 2002/04/12 12:01:53 johana
- * Use global r_port_g_data_shadow.
- * Moved gpio_init_port_g() closer to gpio_init() and marked it __init.
- *
- * Revision 1.13 2002/04/10 12:03:55 johana
- * Added support for port G /dev/gpiog (minor 3).
- * Changed indentation on switch cases.
- * Fixed other spaces to tabs.
- *
- * Revision 1.12 2001/11/12 19:42:15 pkj
- * * Corrected return values from gpio_leds_ioctl().
- * * Fixed compiler warnings.
- *
- * Revision 1.11 2001/10/30 14:39:12 johana
- * Added D() around gpio_write printk.
- *
- * Revision 1.10 2001/10/25 10:24:42 johana
- * Added IO_CFG_WRITE_MODE ioctl and write method that can do fast
- * bittoggling in the kernel. (This speeds up programming an FPGA with 450kB
- * from ~60 seconds to 4 seconds).
- * Added save_flags/cli/restore_flags in ioctl.
- *
- * Revision 1.9 2001/05/04 14:16:07 matsfg
- * Corrected spelling error
- *
- * Revision 1.8 2001/04/27 13:55:26 matsfg
- * Moved initioremap.
- * Turns off all LEDS on init.
- * Added support for shutdown and powerbutton.
- *
- * Revision 1.7 2001/04/04 13:30:08 matsfg
- * Added bitset and bitclear for leds. Calls init_ioremap to set up memmapping
- *
- * Revision 1.6 2001/03/26 16:03:06 bjornw
- * Needs linux/config.h
- *
- * Revision 1.5 2001/03/26 14:22:03 bjornw
- * Namechange of some config options
- *
- * Revision 1.4 2001/02/27 13:52:48 bjornw
- * malloc.h -> slab.h
- *
- * Revision 1.3 2001/01/24 15:06:48 bjornw
- * gpio_wq correct type
- *
- * Revision 1.2 2001/01/18 16:07:30 bjornw
- * 2.4 port
- *
- * Revision 1.1 2001/01/18 15:55:16 bjornw
- * Verbatim copy of etraxgpio.c from elinux 2.0 added
- *
- *
*/
#else
#define DP(x)
#endif
-
+
static char gpio_name[] = "etrax gpio";
#if 0
#endif
static int gpio_ioctl(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg);
-static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
- loff_t *off);
+ unsigned int cmd, unsigned long arg);
+static ssize_t gpio_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *off);
static int gpio_open(struct inode *inode, struct file *filp);
static int gpio_release(struct inode *inode, struct file *filp);
static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait);
/* linked list of alarms to check for */
-static struct gpio_private *alarmlist = 0;
+static struct gpio_private *alarmlist;
-static int gpio_some_alarms = 0; /* Set if someone uses alarm */
-static unsigned long gpio_pa_irq_enabled_mask = 0;
+static int gpio_some_alarms; /* Set if someone uses alarm */
+static unsigned long gpio_pa_irq_enabled_mask;
static DEFINE_SPINLOCK(gpio_lock); /* Protect directions etc */
/* Port A and B use 8 bit access, but Port G is 32 bit */
#define NUM_PORTS (GPIO_MINOR_B+1)
-static volatile unsigned char *ports[NUM_PORTS] = {
- R_PORT_PA_DATA,
+static volatile unsigned char *ports[NUM_PORTS] = {
+ R_PORT_PA_DATA,
R_PORT_PB_DATA,
};
static volatile unsigned char *shads[NUM_PORTS] = {
- &port_pa_data_shadow,
+ &port_pa_data_shadow,
&port_pb_data_shadow
};
#endif
-static unsigned char changeable_dir[NUM_PORTS] = {
+static unsigned char changeable_dir[NUM_PORTS] = {
CONFIG_ETRAX_PA_CHANGEABLE_DIR,
- CONFIG_ETRAX_PB_CHANGEABLE_DIR
+ CONFIG_ETRAX_PB_CHANGEABLE_DIR
};
-static unsigned char changeable_bits[NUM_PORTS] = {
+static unsigned char changeable_bits[NUM_PORTS] = {
CONFIG_ETRAX_PA_CHANGEABLE_BITS,
- CONFIG_ETRAX_PB_CHANGEABLE_BITS
+ CONFIG_ETRAX_PB_CHANGEABLE_BITS
};
-static volatile unsigned char *dir[NUM_PORTS] = {
- R_PORT_PA_DIR,
- R_PORT_PB_DIR
+static volatile unsigned char *dir[NUM_PORTS] = {
+ R_PORT_PA_DIR,
+ R_PORT_PB_DIR
};
static volatile unsigned char *dir_shadow[NUM_PORTS] = {
- &port_pa_dir_shadow,
- &port_pb_dir_shadow
+ &port_pa_dir_shadow,
+ &port_pb_dir_shadow
};
/* All bits in port g that can change dir. */
static const unsigned long int changeable_dir_g_mask = 0x01FFFF01;
-/* Port G is 32 bit, handle it special, some bits are both inputs
+/* Port G is 32 bit, handle it special, some bits are both inputs
and outputs at the same time, only some of the bits can change direction
and some of them in groups of 8 bit. */
static unsigned long changeable_dir_g;
#define USE_PORTS(priv) ((priv)->minor <= GPIO_MINOR_B)
-
-static unsigned int
-gpio_poll(struct file *file,
- poll_table *wait)
+static unsigned int gpio_poll(struct file *file, poll_table *wait)
{
unsigned int mask = 0;
- struct gpio_private *priv = (struct gpio_private *)file->private_data;
+ struct gpio_private *priv = file->private_data;
unsigned long data;
- spin_lock(&gpio_lock);
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+
poll_wait(file, &priv->alarm_wq, wait);
if (priv->minor == GPIO_MINOR_A) {
- unsigned long flags;
unsigned long tmp;
data = *R_PORT_PA_DATA;
/* PA has support for high level interrupt -
*/
tmp = ~data & priv->highalarm & 0xFF;
tmp = (tmp << R_IRQ_MASK1_SET__pa0__BITNR);
- local_irq_save(flags);
+
gpio_pa_irq_enabled_mask |= tmp;
*R_IRQ_MASK1_SET = tmp;
- local_irq_restore(flags);
-
} else if (priv->minor == GPIO_MINOR_B)
data = *R_PORT_PB_DATA;
else if (priv->minor == GPIO_MINOR_G)
data = *R_PORT_G_DATA;
else {
- spin_unlock(&gpio_lock);
- return 0;
+ mask = 0;
+ goto out;
}
-
+
if ((data & priv->highalarm) ||
(~data & priv->lowalarm)) {
mask = POLLIN|POLLRDNORM;
}
- spin_unlock(&gpio_lock);
-
+out:
+ spin_unlock_irqrestore(&gpio_lock, flags);
DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
return mask;
int etrax_gpio_wake_up_check(void)
{
- struct gpio_private *priv = alarmlist;
+ struct gpio_private *priv;
unsigned long data = 0;
int ret = 0;
- spin_lock(&gpio_lock);
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+ priv = alarmlist;
while (priv) {
- if (USE_PORTS(priv)) {
+ if (USE_PORTS(priv))
data = *priv->port;
- } else if (priv->minor == GPIO_MINOR_G) {
+ else if (priv->minor == GPIO_MINOR_G)
data = *R_PORT_G_DATA;
- }
+
if ((data & priv->highalarm) ||
(~data & priv->lowalarm)) {
DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
}
priv = priv->next;
}
- spin_unlock(&gpio_lock);
+ spin_unlock_irqrestore(&gpio_lock, flags);
return ret;
}
static irqreturn_t
-gpio_poll_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+gpio_poll_timer_interrupt(int irq, void *dev_id)
{
if (gpio_some_alarms) {
etrax_gpio_wake_up_check();
}
static irqreturn_t
-gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+gpio_interrupt(int irq, void *dev_id)
{
unsigned long tmp;
- spin_lock(&gpio_lock);
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+
/* Find what PA interrupts are active */
tmp = (*R_IRQ_READ1);
*R_IRQ_MASK1_CLR = tmp;
gpio_pa_irq_enabled_mask &= ~tmp;
- spin_unlock(&gpio_lock);
+ spin_unlock_irqrestore(&gpio_lock, flags);
- if (gpio_some_alarms) {
+ if (gpio_some_alarms)
return IRQ_RETVAL(etrax_gpio_wake_up_check());
- }
+
return IRQ_NONE;
}
+static void gpio_write_bit(struct gpio_private *priv,
+ unsigned char data, int bit)
+{
+ *priv->port = *priv->shadow &= ~(priv->clk_mask);
+ if (data & 1 << bit)
+ *priv->port = *priv->shadow |= priv->data_mask;
+ else
+ *priv->port = *priv->shadow &= ~(priv->data_mask);
+
+ /* For FPGA: min 5.0ns (DCC) before CCLK high */
+ *priv->port = *priv->shadow |= priv->clk_mask;
+}
-static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
- loff_t *off)
+static void gpio_write_byte(struct gpio_private *priv, unsigned char data)
{
- struct gpio_private *priv = (struct gpio_private *)file->private_data;
- unsigned char data, clk_mask, data_mask, write_msb;
- unsigned long flags;
+ int i;
- spin_lock(&gpio_lock);
+ if (priv->write_msb)
+ for (i = 7; i >= 0; i--)
+ gpio_write_bit(priv, data, i);
+ else
+ for (i = 0; i <= 7; i++)
+ gpio_write_bit(priv, data, i);
+}
+static ssize_t gpio_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *off)
+{
+ struct gpio_private *priv = file->private_data;
+ unsigned long flags;
ssize_t retval = count;
- if (priv->minor !=GPIO_MINOR_A && priv->minor != GPIO_MINOR_B) {
- retval = -EFAULT;
- goto out;
- }
-
- if (!access_ok(VERIFY_READ, buf, count)) {
- retval = -EFAULT;
- goto out;
- }
- clk_mask = priv->clk_mask;
- data_mask = priv->data_mask;
+
+ if (priv->minor != GPIO_MINOR_A && priv->minor != GPIO_MINOR_B)
+ return -EFAULT;
+
+ if (!access_ok(VERIFY_READ, buf, count))
+ return -EFAULT;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+
/* It must have been configured using the IO_CFG_WRITE_MODE */
/* Perhaps a better error code? */
- if (clk_mask == 0 || data_mask == 0) {
+ if (priv->clk_mask == 0 || priv->data_mask == 0) {
retval = -EPERM;
goto out;
}
- write_msb = priv->write_msb;
- D(printk("gpio_write: %lu to data 0x%02X clk 0x%02X msb: %i\n",count, data_mask, clk_mask, write_msb));
- while (count--) {
- int i;
- data = *buf++;
- if (priv->write_msb) {
- for (i = 7; i >= 0;i--) {
- local_irq_save(flags);
- *priv->port = *priv->shadow &= ~clk_mask;
- if (data & 1<<i)
- *priv->port = *priv->shadow |= data_mask;
- else
- *priv->port = *priv->shadow &= ~data_mask;
- /* For FPGA: min 5.0ns (DCC) before CCLK high */
- *priv->port = *priv->shadow |= clk_mask;
- local_irq_restore(flags);
- }
- } else {
- for (i = 0; i <= 7;i++) {
- local_irq_save(flags);
- *priv->port = *priv->shadow &= ~clk_mask;
- if (data & 1<<i)
- *priv->port = *priv->shadow |= data_mask;
- else
- *priv->port = *priv->shadow &= ~data_mask;
- /* For FPGA: min 5.0ns (DCC) before CCLK high */
- *priv->port = *priv->shadow |= clk_mask;
- local_irq_restore(flags);
- }
- }
- }
+
+ D(printk(KERN_DEBUG "gpio_write: %02X to data 0x%02X "
+ "clk 0x%02X msb: %i\n",
+ count, priv->data_mask, priv->clk_mask, priv->write_msb));
+
+ while (count--)
+ gpio_write_byte(priv, *buf++);
+
out:
- spin_unlock(&gpio_lock);
+ spin_unlock_irqrestore(&gpio_lock, flags);
return retval;
}
{
struct gpio_private *priv;
int p = iminor(inode);
+ unsigned long flags;
if (p > GPIO_MINOR_LAST)
return -EINVAL;
- priv = kmalloc(sizeof(struct gpio_private),
- GFP_KERNEL);
+ priv = kzalloc(sizeof(struct gpio_private), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->minor = p;
- /* initialize the io/alarm struct and link it into our alarmlist */
+ /* initialize the io/alarm struct */
- priv->next = alarmlist;
- alarmlist = priv;
if (USE_PORTS(priv)) { /* A and B */
priv->port = ports[p];
priv->shadow = shads[p];
priv->data_mask = 0;
init_waitqueue_head(&priv->alarm_wq);
- filp->private_data = (void *)priv;
+ filp->private_data = priv;
+
+ /* link it into our alarmlist */
+ spin_lock_irqsave(&gpio_lock, flags);
+ priv->next = alarmlist;
+ alarmlist = priv;
+ spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
}
{
struct gpio_private *p;
struct gpio_private *todel;
+ unsigned long flags;
- spin_lock(&gpio_lock);
+ spin_lock_irqsave(&gpio_lock, flags);
- p = alarmlist;
- todel = (struct gpio_private *)filp->private_data;
+ p = alarmlist;
+ todel = filp->private_data;
/* unlink from alarmlist and free the private structure */
while (p) {
if (p->highalarm | p->lowalarm) {
gpio_some_alarms = 1;
- spin_unlock(&gpio_lock);
- return 0;
+ goto out;
}
p = p->next;
}
gpio_some_alarms = 0;
- spin_unlock(&gpio_lock);
+out:
+ spin_unlock_irqrestore(&gpio_lock, flags);
return 0;
}
-/* Main device API. ioctl's to read/set/clear bits, as well as to
+/* Main device API. ioctl's to read/set/clear bits, as well as to
* set alarms to wait for using a subsequent select().
*/
-
unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
{
- /* Set direction 0=unchanged 1=input,
- * return mask with 1=input
- */
- unsigned long flags;
+ /* Set direction 0=unchanged 1=input,
+ * return mask with 1=input */
if (USE_PORTS(priv)) {
- local_irq_save(flags);
- *priv->dir = *priv->dir_shadow &=
+ *priv->dir = *priv->dir_shadow &=
~((unsigned char)arg & priv->changeable_dir);
- local_irq_restore(flags);
return ~(*priv->dir_shadow) & 0xFF; /* Only 8 bits */
- } else if (priv->minor == GPIO_MINOR_G) {
- /* We must fiddle with R_GEN_CONFIG to change dir */
- local_irq_save(flags);
- if (((arg & dir_g_in_bits) != arg) &&
- (arg & changeable_dir_g)) {
- arg &= changeable_dir_g;
- /* Clear bits in genconfig to set to input */
- if (arg & (1<<0)) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g0dir);
- dir_g_in_bits |= (1<<0);
- dir_g_out_bits &= ~(1<<0);
- }
- if ((arg & 0x0000FF00) == 0x0000FF00) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g8_15dir);
- dir_g_in_bits |= 0x0000FF00;
- dir_g_out_bits &= ~0x0000FF00;
- }
- if ((arg & 0x00FF0000) == 0x00FF0000) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g16_23dir);
- dir_g_in_bits |= 0x00FF0000;
- dir_g_out_bits &= ~0x00FF0000;
- }
- if (arg & (1<<24)) {
- genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG,g24dir);
- dir_g_in_bits |= (1<<24);
- dir_g_out_bits &= ~(1<<24);
- }
- D(printk(KERN_INFO "gpio: SETINPUT on port G set "
- "genconfig to 0x%08lX "
- "in_bits: 0x%08lX "
- "out_bits: 0x%08lX\n",
- (unsigned long)genconfig_shadow,
- dir_g_in_bits, dir_g_out_bits));
- *R_GEN_CONFIG = genconfig_shadow;
- /* Must be a >120 ns delay before writing this again */
-
+ }
+
+ if (priv->minor != GPIO_MINOR_G)
+ return 0;
+
+ /* We must fiddle with R_GEN_CONFIG to change dir */
+ if (((arg & dir_g_in_bits) != arg) &&
+ (arg & changeable_dir_g)) {
+ arg &= changeable_dir_g;
+ /* Clear bits in genconfig to set to input */
+ if (arg & (1<<0)) {
+ genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g0dir);
+ dir_g_in_bits |= (1<<0);
+ dir_g_out_bits &= ~(1<<0);
}
- local_irq_restore(flags);
- return dir_g_in_bits;
+ if ((arg & 0x0000FF00) == 0x0000FF00) {
+ genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g8_15dir);
+ dir_g_in_bits |= 0x0000FF00;
+ dir_g_out_bits &= ~0x0000FF00;
+ }
+ if ((arg & 0x00FF0000) == 0x00FF0000) {
+ genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g16_23dir);
+ dir_g_in_bits |= 0x00FF0000;
+ dir_g_out_bits &= ~0x00FF0000;
+ }
+ if (arg & (1<<24)) {
+ genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, g24dir);
+ dir_g_in_bits |= (1<<24);
+ dir_g_out_bits &= ~(1<<24);
+ }
+ D(printk(KERN_DEBUG "gpio: SETINPUT on port G set "
+ "genconfig to 0x%08lX "
+ "in_bits: 0x%08lX "
+ "out_bits: 0x%08lX\n",
+ (unsigned long)genconfig_shadow,
+ dir_g_in_bits, dir_g_out_bits));
+ *R_GEN_CONFIG = genconfig_shadow;
+ /* Must be a >120 ns delay before writing this again */
+
}
- return 0;
+ return dir_g_in_bits;
} /* setget_input */
unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
{
- unsigned long flags;
if (USE_PORTS(priv)) {
- local_irq_save(flags);
- *priv->dir = *priv->dir_shadow |=
- ((unsigned char)arg & priv->changeable_dir);
- local_irq_restore(flags);
+ *priv->dir = *priv->dir_shadow |=
+ ((unsigned char)arg & priv->changeable_dir);
return *priv->dir_shadow;
- } else if (priv->minor == GPIO_MINOR_G) {
- /* We must fiddle with R_GEN_CONFIG to change dir */
- local_irq_save(flags);
- if (((arg & dir_g_out_bits) != arg) &&
- (arg & changeable_dir_g)) {
- /* Set bits in genconfig to set to output */
- if (arg & (1<<0)) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g0dir);
- dir_g_out_bits |= (1<<0);
- dir_g_in_bits &= ~(1<<0);
- }
- if ((arg & 0x0000FF00) == 0x0000FF00) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g8_15dir);
- dir_g_out_bits |= 0x0000FF00;
- dir_g_in_bits &= ~0x0000FF00;
- }
- if ((arg & 0x00FF0000) == 0x00FF0000) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g16_23dir);
- dir_g_out_bits |= 0x00FF0000;
- dir_g_in_bits &= ~0x00FF0000;
- }
- if (arg & (1<<24)) {
- genconfig_shadow |= IO_MASK(R_GEN_CONFIG,g24dir);
- dir_g_out_bits |= (1<<24);
- dir_g_in_bits &= ~(1<<24);
- }
- D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
- "genconfig to 0x%08lX "
- "in_bits: 0x%08lX "
- "out_bits: 0x%08lX\n",
- (unsigned long)genconfig_shadow,
- dir_g_in_bits, dir_g_out_bits));
- *R_GEN_CONFIG = genconfig_shadow;
- /* Must be a >120 ns delay before writing this again */
+ }
+ if (priv->minor != GPIO_MINOR_G)
+ return 0;
+
+ /* We must fiddle with R_GEN_CONFIG to change dir */
+ if (((arg & dir_g_out_bits) != arg) &&
+ (arg & changeable_dir_g)) {
+ /* Set bits in genconfig to set to output */
+ if (arg & (1<<0)) {
+ genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g0dir);
+ dir_g_out_bits |= (1<<0);
+ dir_g_in_bits &= ~(1<<0);
}
- local_irq_restore(flags);
- return dir_g_out_bits & 0x7FFFFFFF;
+ if ((arg & 0x0000FF00) == 0x0000FF00) {
+ genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g8_15dir);
+ dir_g_out_bits |= 0x0000FF00;
+ dir_g_in_bits &= ~0x0000FF00;
+ }
+ if ((arg & 0x00FF0000) == 0x00FF0000) {
+ genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g16_23dir);
+ dir_g_out_bits |= 0x00FF0000;
+ dir_g_in_bits &= ~0x00FF0000;
+ }
+ if (arg & (1<<24)) {
+ genconfig_shadow |= IO_MASK(R_GEN_CONFIG, g24dir);
+ dir_g_out_bits |= (1<<24);
+ dir_g_in_bits &= ~(1<<24);
+ }
+ D(printk(KERN_INFO "gpio: SETOUTPUT on port G set "
+ "genconfig to 0x%08lX "
+ "in_bits: 0x%08lX "
+ "out_bits: 0x%08lX\n",
+ (unsigned long)genconfig_shadow,
+ dir_g_in_bits, dir_g_out_bits));
+ *R_GEN_CONFIG = genconfig_shadow;
+ /* Must be a >120 ns delay before writing this again */
}
- return 0;
+ return dir_g_out_bits & 0x7FFFFFFF;
} /* setget_output */
static int
unsigned long val;
int ret = 0;
- struct gpio_private *priv = (struct gpio_private *)file->private_data;
- if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) {
+ struct gpio_private *priv = file->private_data;
+ if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
return -EINVAL;
- }
- spin_lock(&gpio_lock);
+ spin_lock_irqsave(&gpio_lock, flags);
switch (_IOC_NR(cmd)) {
case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
}
break;
case IO_SETBITS:
- local_irq_save(flags);
// set changeable bits with a 1 in arg
if (USE_PORTS(priv)) {
*priv->port = *priv->shadow |=
} else if (priv->minor == GPIO_MINOR_G) {
*R_PORT_G_DATA = port_g_data_shadow |= (arg & dir_g_out_bits);
}
- local_irq_restore(flags);
break;
case IO_CLRBITS:
- local_irq_save(flags);
// clear changeable bits with a 1 in arg
if (USE_PORTS(priv)) {
*priv->port = *priv->shadow &=
} else if (priv->minor == GPIO_MINOR_G) {
*R_PORT_G_DATA = port_g_data_shadow &= ~((unsigned long)arg & dir_g_out_bits);
}
- local_irq_restore(flags);
break;
case IO_HIGHALARM:
// set alarm when bits with 1 in arg go high
/* Must update gpio_some_alarms */
struct gpio_private *p = alarmlist;
int some_alarms;
+ spin_lock_irq(&gpio_lock);
+ p = alarmlist;
some_alarms = 0;
while (p) {
if (p->highalarm | p->lowalarm) {
p = p->next;
}
gpio_some_alarms = some_alarms;
+ spin_unlock_irq(&gpio_lock);
}
break;
case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
} else if (priv->minor == GPIO_MINOR_G) {
val = *R_PORT_G_DATA;
}
- if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
ret = -EFAULT;
break;
case IO_READ_OUTBITS:
} else if (priv->minor == GPIO_MINOR_G) {
val = port_g_data_shadow;
}
- if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
ret = -EFAULT;
break;
case IO_SETGET_INPUT:
/* bits set in *arg is set to input,
* *arg updated with current input pins.
*/
- if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
+ if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
{
ret = -EFAULT;
break;
}
val = setget_input(priv, val);
- if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
ret = -EFAULT;
break;
case IO_SETGET_OUTPUT:
/* bits set in *arg is set to output,
* *arg updated with current output pins.
*/
- if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
- {
+ if (copy_from_user(&val, (void __user *)arg, sizeof(val))) {
ret = -EFAULT;
break;
}
val = setget_output(priv, val);
- if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
ret = -EFAULT;
break;
default:
ret = -EINVAL;
} /* switch */
- spin_unlock(&gpio_lock);
+ spin_unlock_irqrestore(&gpio_lock, flags);
return ret;
}
switch (_IOC_NR(cmd)) {
case IO_LEDACTIVE_SET:
- green = ((unsigned char) arg) & 1;
- red = (((unsigned char) arg) >> 1) & 1;
- LED_ACTIVE_SET_G(green);
- LED_ACTIVE_SET_R(red);
+ green = ((unsigned char)arg) & 1;
+ red = (((unsigned char)arg) >> 1) & 1;
+ CRIS_LED_ACTIVE_SET_G(green);
+ CRIS_LED_ACTIVE_SET_R(red);
break;
case IO_LED_SETBIT:
- LED_BIT_SET(arg);
+ CRIS_LED_BIT_SET(arg);
break;
case IO_LED_CLRBIT:
- LED_BIT_CLR(arg);
+ CRIS_LED_BIT_CLR(arg);
break;
default:
return 0;
}
-const struct file_operations gpio_fops = {
+static const struct file_operations gpio_fops = {
.owner = THIS_MODULE,
.poll = gpio_poll,
.ioctl = gpio_ioctl,
.release = gpio_release,
};
-
-void ioif_watcher(const unsigned int gpio_in_available,
- const unsigned int gpio_out_available,
- const unsigned char pa_available,
- const unsigned char pb_available)
+static void ioif_watcher(const unsigned int gpio_in_available,
+ const unsigned int gpio_out_available,
+ const unsigned char pa_available,
+ const unsigned char pb_available)
{
unsigned long int flags;
- D(printk("gpio.c: ioif_watcher called\n"));
- D(printk("gpio.c: G in: 0x%08x G out: 0x%08x PA: 0x%02x PB: 0x%02x\n",
- gpio_in_available, gpio_out_available, pa_available, pb_available));
+
+ D(printk(KERN_DEBUG "gpio.c: ioif_watcher called\n"));
+ D(printk(KERN_DEBUG "gpio.c: G in: 0x%08x G out: 0x%08x "
+ "PA: 0x%02x PB: 0x%02x\n",
+ gpio_in_available, gpio_out_available,
+ pa_available, pb_available));
spin_lock_irqsave(&gpio_lock, flags);
/* Initialise the dir_g_shadow etc. depending on genconfig */
/* 0=input 1=output */
- if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out))
+ if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out))
dir_g_shadow |= (1 << 0);
if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out))
dir_g_shadow |= 0x0000FF00;
changeable_dir_g = changeable_dir_g_mask;
changeable_dir_g &= dir_g_out_bits;
changeable_dir_g &= dir_g_in_bits;
- /* Correct the bits that can change direction */
+
+ /* Correct the bits that can change direction */
dir_g_out_bits &= ~changeable_dir_g;
dir_g_out_bits |= dir_g_shadow;
dir_g_in_bits &= ~changeable_dir_g;
spin_unlock_irqrestore(&gpio_lock, flags);
- printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX val: %08lX\n",
+ printk(KERN_INFO "GPIO port G: in_bits: 0x%08lX out_bits: 0x%08lX "
+ "val: %08lX\n",
dir_g_in_bits, dir_g_out_bits, (unsigned long)*R_PORT_G_DATA);
printk(KERN_INFO "GPIO port G: dir: %08lX changeable: %08lX\n",
dir_g_shadow, changeable_dir_g);
/* main driver initialization routine, called from mem.c */
-static __init int
-gpio_init(void)
+static int __init gpio_init(void)
{
int res;
#if defined (CONFIG_ETRAX_CSP0_LEDS)
int i;
#endif
- printk("gpio init\n");
-
- /* do the formalities */
res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
if (res < 0) {
/* Clear all leds */
#if defined (CONFIG_ETRAX_CSP0_LEDS) || defined (CONFIG_ETRAX_PA_LEDS) || defined (CONFIG_ETRAX_PB_LEDS)
- LED_NETWORK_SET(0);
- LED_ACTIVE_SET(0);
- LED_DISK_READ(0);
- LED_DISK_WRITE(0);
+ CRIS_LED_NETWORK_SET(0);
+ CRIS_LED_ACTIVE_SET(0);
+ CRIS_LED_DISK_READ(0);
+ CRIS_LED_DISK_WRITE(0);
#if defined (CONFIG_ETRAX_CSP0_LEDS)
- for (i = 0; i < 32; i++) {
- LED_BIT_SET(i);
- }
+ for (i = 0; i < 32; i++)
+ CRIS_LED_BIT_SET(i);
#endif
#endif
/* The I/O interface allocation watcher will be called when
* registering it. */
if (cris_io_interface_register_watcher(ioif_watcher)){
- printk(KERN_WARNING "gpio_init: Failed to install IO if allocator watcher\n");
+ printk(KERN_WARNING "gpio_init: Failed to install IO "
+ "if allocator watcher\n");
}
- printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001, 2002, 2003, 2004 Axis Communications AB\n");
+ printk(KERN_INFO "ETRAX 100LX GPIO driver v2.5, (c) 2001-2008 "
+ "Axis Communications AB\n");
/* We call etrax_gpio_wake_up_check() from timer interrupt and
* from cpu_idle() in kernel/process.c
* The check in cpu_idle() reduces latency from ~15 ms to ~6 ms
* in some tests.
- */
- if (request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
- IRQF_SHARED | IRQF_DISABLED,"gpio poll", NULL)) {
+ */
+ res = request_irq(TIMER0_IRQ_NBR, gpio_poll_timer_interrupt,
+ IRQF_SHARED | IRQF_DISABLED, "gpio poll", gpio_name);
+ if (res) {
printk(KERN_CRIT "err: timer0 irq for gpio\n");
+ return res;
}
- if (request_irq(PA_IRQ_NBR, gpio_pa_interrupt,
- IRQF_SHARED | IRQF_DISABLED,"gpio PA", NULL)) {
+ res = request_irq(PA_IRQ_NBR, gpio_interrupt,
+ IRQF_SHARED | IRQF_DISABLED, "gpio PA", gpio_name);
+ if (res)
printk(KERN_CRIT "err: PA irq for gpio\n");
- }
-
return res;
}
/* this makes sure that gpio_init is called during kernel boot */
-
module_init(gpio_init);
+
*! kernel modules (i2c_writereg/readreg) and from userspace using
*! ioctl()'s
*!
-*! Nov 30 1998 Torbjorn Eliasson Initial version.
-*! Bjorn Wesen Elinux kernel version.
-*! Jan 14 2000 Johan Adolfsson Fixed PB shadow register stuff -
-*! don't use PB_I2C if DS1302 uses same bits,
-*! use PB.
-*! $Log: i2c.c,v $
-*! Revision 1.13 2005/03/07 13:13:07 starvik
-*! Added spinlocks to protect states etc
-*!
-*! Revision 1.12 2005/01/05 06:11:22 starvik
-*! No need to do local_irq_disable after local_irq_save.
-*!
-*! Revision 1.11 2004/12/13 12:21:52 starvik
-*! Added I/O and DMA allocators from Linux 2.4
-*!
-*! Revision 1.9 2004/08/24 06:49:14 starvik
-*! Whitespace cleanup
-*!
-*! Revision 1.8 2004/06/08 08:48:26 starvik
-*! Removed unused code
-*!
-*! Revision 1.7 2004/05/28 09:26:59 starvik
-*! Modified I2C initialization to work in 2.6.
-*!
-*! Revision 1.6 2004/05/14 07:58:03 starvik
-*! Merge of changes from 2.4
-*!
-*! Revision 1.4 2002/12/11 13:13:57 starvik
-*! Added arch/ to v10 specific includes
-*! Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
-*!
-*! Revision 1.3 2002/11/20 11:56:11 starvik
-*! Merge of Linux 2.5.48
-*!
-*! Revision 1.2 2002/11/18 13:16:06 starvik
-*! Linux 2.5 port of latest 2.4 drivers
-*!
-*! Revision 1.9 2002/10/31 15:32:26 starvik
-*! Update Port B register and shadow even when running with hardware support
-*! to avoid glitches when reading bits
-*! Never set direction to out in i2c_inbyte
-*! Removed incorrect clock toggling at end of i2c_inbyte
-*!
-*! Revision 1.8 2002/08/13 06:31:53 starvik
-*! Made SDA and SCL line configurable
-*! Modified i2c_inbyte to work with PCF8563
-*!
-*! Revision 1.7 2001/04/04 13:11:36 markusl
-*! Updated according to review remarks
-*!
-*! Revision 1.6 2001/03/19 12:43:00 markusl
-*! Made some symbols unstatic (used by the eeprom driver)
-*!
-*! Revision 1.5 2001/02/27 13:52:48 bjornw
-*! malloc.h -> slab.h
-*!
-*! Revision 1.4 2001/02/15 07:17:40 starvik
-*! Corrected usage if port_pb_i2c_shadow
-*!
-*! Revision 1.3 2001/01/26 17:55:13 bjornw
-*! * Made I2C_USES_PB_NOT_PB_I2C a CONFIG option instead of assigning it
-*! magically. Config.in needs to set it for the options that need it, like
-*! Dallas 1302 support. Actually, it should be default since it screws up
-*! the PB bits even if you don't use I2C..
-*! * Include linux/config.h to get the above
-*!
-*! Revision 1.2 2001/01/18 15:49:30 bjornw
-*! 2.4 port of I2C including some cleanups (untested of course)
-*!
-*! Revision 1.1 2001/01/18 15:35:25 bjornw
-*! Verbatim copy of the Etrax i2c driver, 2.0 elinux version
-*!
-*!
-*! ---------------------------------------------------------------------------
-*!
-*! (C) Copyright 1999-2002 Axis Communications AB, LUND, SWEDEN
+*! (C) Copyright 1999-2007 Axis Communications AB, LUND, SWEDEN
*!
*!***************************************************************************/
-/* $Id: i2c.c,v 1.13 2005/03/07 13:13:07 starvik Exp $ */
/****************** INCLUDE FILES SECTION ***********************************/
* last received byte needs to be nacked
* instead of acked
*/
- i2c_sendack();
+ i2c_sendnack();
/*
* end sequence
*/
if (!first) {
return res;
}
+ first = 0;
/* Setup and enable the Port B I2C interface */
* low detector are also provided. All address and data are transferred
* serially via two-line bidirectional I2C-bus. Maximum bus speed is
* 400 kbits/s. The built-in word address register is incremented
- * automatically after each written or read bute.
+ * automatically after each written or read byte.
*
- * Copyright (c) 2002, Axis Communications AB
+ * Copyright (c) 2002-2007, Axis Communications AB
* All rights reserved.
*
* Author: Tobias Anderberg <tobiasa@axis.com>.
*
- * $Id: pcf8563.c,v 1.11 2005/03/07 13:13:07 starvik Exp $
*/
#include <linux/module.h>
#include <linux/ioctl.h>
#include <linux/delay.h>
#include <linux/bcd.h>
-#include <linux/capability.h>
+#include <linux/mutex.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include <asm/io.h>
-#include <asm/arch/svinto.h>
#include <asm/rtc.h>
+
#include "i2c.h"
-#define PCF8563_MAJOR 121 /* Local major number. */
-#define DEVICE_NAME "rtc" /* Name which is registered in /proc/devices. */
+#define PCF8563_MAJOR 121 /* Local major number. */
+#define DEVICE_NAME "rtc" /* Name which is registered in /proc/devices. */
#define PCF8563_NAME "PCF8563"
-#define DRIVER_VERSION "$Revision: 1.11 $"
+#define DRIVER_VERSION "$Revision: 1.24 $"
/* I2C bus slave registers. */
#define RTC_I2C_READ 0xa3
#define rtc_read(x) i2c_readreg(RTC_I2C_READ, x)
#define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y)
-static DEFINE_SPINLOCK(rtc_lock); /* Protect state etc */
-
+static DEFINE_MUTEX(rtc_lock); /* Protect state etc */
+
static const unsigned char days_in_month[] =
{ 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
+/* Cache VL bit value read at driver init since writing the RTC_SECOND
+ * register clears the VL status.
+ */
+static int voltage_low;
+
static const struct file_operations pcf8563_fops = {
.owner = THIS_MODULE,
.ioctl = pcf8563_ioctl,
};
unsigned char
-pcf8563_readreg(int reg)
+pcf8563_readreg(int reg)
{
- unsigned char res = i2c_readreg(RTC_I2C_READ, reg);
-
- /* The PCF8563 does not return 0 for unimplemented bits */
- switch(reg)
- {
- case RTC_SECONDS:
- case RTC_MINUTES:
- res &= 0x7f;
- break;
- case RTC_HOURS:
- case RTC_DAY_OF_MONTH:
- res &= 0x3f;
- break;
- case RTC_MONTH:
- res = (res & 0x1f) - 1; /* PCF8563 returns month in range 1-12 */
- break;
+ unsigned char res = rtc_read(reg);
+
+ /* The PCF8563 does not return 0 for unimplemented bits. */
+ switch (reg) {
+ case RTC_SECONDS:
+ case RTC_MINUTES:
+ res &= 0x7F;
+ break;
+ case RTC_HOURS:
+ case RTC_DAY_OF_MONTH:
+ res &= 0x3F;
+ break;
+ case RTC_WEEKDAY:
+ res &= 0x07;
+ break;
+ case RTC_MONTH:
+ res &= 0x1F;
+ break;
+ case RTC_CONTROL1:
+ res &= 0xA8;
+ break;
+ case RTC_CONTROL2:
+ res &= 0x1F;
+ break;
+ case RTC_CLOCKOUT_FREQ:
+ case RTC_TIMER_CONTROL:
+ res &= 0x83;
+ break;
}
return res;
}
void
-pcf8563_writereg(int reg, unsigned char val)
+pcf8563_writereg(int reg, unsigned char val)
{
-#ifdef CONFIG_ETRAX_RTC_READONLY
- if (reg == RTC_CONTROL1 || (reg >= RTC_SECONDS && reg <= RTC_YEAR))
- return;
-#endif
-
rtc_write(reg, val);
}
void
get_rtc_time(struct rtc_time *tm)
{
- tm->tm_sec = rtc_read(RTC_SECONDS);
- tm->tm_min = rtc_read(RTC_MINUTES);
+ tm->tm_sec = rtc_read(RTC_SECONDS);
+ tm->tm_min = rtc_read(RTC_MINUTES);
tm->tm_hour = rtc_read(RTC_HOURS);
tm->tm_mday = rtc_read(RTC_DAY_OF_MONTH);
- tm->tm_mon = rtc_read(RTC_MONTH);
+ tm->tm_wday = rtc_read(RTC_WEEKDAY);
+ tm->tm_mon = rtc_read(RTC_MONTH);
tm->tm_year = rtc_read(RTC_YEAR);
- if (tm->tm_sec & 0x80)
- printk(KERN_WARNING "%s: RTC Low Voltage - date/time is not reliable!\n", PCF8563_NAME);
+ if (tm->tm_sec & 0x80) {
+ printk(KERN_ERR "%s: RTC Voltage Low - reliable date/time "
+ "information is no longer guaranteed!\n", PCF8563_NAME);
+ }
- tm->tm_year = BCD_TO_BIN(tm->tm_year) + ((tm->tm_mon & 0x80) ? 100 : 0);
- tm->tm_sec &= 0x7f;
- tm->tm_min &= 0x7f;
- tm->tm_hour &= 0x3f;
- tm->tm_mday &= 0x3f;
- tm->tm_mon &= 0x1f;
+ tm->tm_year = BCD_TO_BIN(tm->tm_year) +
+ ((tm->tm_mon & 0x80) ? 100 : 0);
+ tm->tm_sec &= 0x7F;
+ tm->tm_min &= 0x7F;
+ tm->tm_hour &= 0x3F;
+ tm->tm_mday &= 0x3F;
+ tm->tm_wday &= 0x07; /* Not coded in BCD. */
+ tm->tm_mon &= 0x1F;
BCD_TO_BIN(tm->tm_sec);
BCD_TO_BIN(tm->tm_min);
int __init
pcf8563_init(void)
{
- int ret;
-
- if ((ret = i2c_init())) {
- printk(KERN_CRIT "pcf8563_init: failed to init i2c\n");
- return ret;
+ static int res;
+ static int first = 1;
+
+ if (!first)
+ return res;
+ first = 0;
+
+ /* Initiate the i2c protocol. */
+ res = i2c_init();
+ if (res < 0) {
+ printk(KERN_CRIT "pcf8563_init: Failed to init i2c.\n");
+ return res;
}
/*
* First of all we need to reset the chip. This is done by
- * clearing control1, control2 and clk freq, clear the
- * Voltage Low bit, and resetting all alarms.
+ * clearing control1, control2 and clk freq and resetting
+ * all alarms.
*/
if (rtc_write(RTC_CONTROL1, 0x00) < 0)
goto err;
if (rtc_write(RTC_CLOCKOUT_FREQ, 0x00) < 0)
goto err;
- /* Clear the VL bit in the seconds register. */
- ret = rtc_read(RTC_SECONDS);
-
- if (rtc_write(RTC_SECONDS, (ret & 0x7f)) < 0)
+ if (rtc_write(RTC_TIMER_CONTROL, 0x03) < 0)
goto err;
-
+
/* Reset the alarms. */
- if (rtc_write(RTC_MINUTE_ALARM, 0x00) < 0)
+ if (rtc_write(RTC_MINUTE_ALARM, 0x80) < 0)
goto err;
-
- if (rtc_write(RTC_HOUR_ALARM, 0x00) < 0)
+
+ if (rtc_write(RTC_HOUR_ALARM, 0x80) < 0)
goto err;
-
- if (rtc_write(RTC_DAY_ALARM, 0x00) < 0)
+
+ if (rtc_write(RTC_DAY_ALARM, 0x80) < 0)
goto err;
-
- if (rtc_write(RTC_WEEKDAY_ALARM, 0x00) < 0)
+
+ if (rtc_write(RTC_WEEKDAY_ALARM, 0x80) < 0)
goto err;
-
- /* Check for low voltage, and warn about it.. */
- if (rtc_read(RTC_SECONDS) & 0x80)
- printk(KERN_WARNING "%s: RTC Low Voltage - date/time is not reliable!\n", PCF8563_NAME);
-
- return 0;
+
+ /* Check for low voltage, and warn about it. */
+ if (rtc_read(RTC_SECONDS) & 0x80) {
+ voltage_low = 1;
+ printk(KERN_WARNING "%s: RTC Voltage Low - reliable "
+ "date/time information is no longer guaranteed!\n",
+ PCF8563_NAME);
+ }
+
+ return res;
err:
printk(KERN_INFO "%s: Error initializing chip.\n", PCF8563_NAME);
- return -1;
+ res = -1;
+ return res;
}
void __exit
* ioctl calls for this driver. Why return -ENOTTY upon error? Because
* POSIX says so!
*/
-int
-pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
+ unsigned long arg)
{
/* Some sanity checks. */
if (_IOC_TYPE(cmd) != RTC_MAGIC)
return -ENOTTY;
switch (cmd) {
- case RTC_RD_TIME:
- {
- struct rtc_time tm;
-
- spin_lock(&rtc_lock);
- get_rtc_time(&tm);
-
- if (copy_to_user((struct rtc_time *) arg, &tm, sizeof(struct rtc_time))) {
- spin_unlock(&rtc_lock);
- return -EFAULT;
- }
-
- spin_unlock(&rtc_lock);
- return 0;
- }
- break;
- case RTC_SET_TIME:
- {
-#ifdef CONFIG_ETRAX_RTC_READONLY
- return -EPERM;
-#else
- int leap;
- int century;
- struct rtc_time tm;
-
- memset(&tm, 0, sizeof (struct rtc_time));
- if (!capable(CAP_SYS_TIME))
- return -EPERM;
-
- if (copy_from_user(&tm, (struct rtc_time *) arg, sizeof(struct rtc_time)))
- return -EFAULT;
-
- /* Convert from struct tm to struct rtc_time. */
- tm.tm_year += 1900;
- tm.tm_mon += 1;
-
- leap = ((tm.tm_mon == 2) && ((tm.tm_year % 4) == 0)) ? 1 : 0;
-
- /* Perform some sanity checks. */
- if ((tm.tm_year < 1970) ||
- (tm.tm_mon > 12) ||
- (tm.tm_mday == 0) ||
- (tm.tm_mday > days_in_month[tm.tm_mon] + leap) ||
- (tm.tm_hour >= 24) ||
- (tm.tm_min >= 60) ||
- (tm.tm_sec >= 60))
- return -EINVAL;
-
- century = (tm.tm_year >= 2000) ? 0x80 : 0;
- tm.tm_year = tm.tm_year % 100;
-
- BIN_TO_BCD(tm.tm_year);
- BIN_TO_BCD(tm.tm_mday);
- BIN_TO_BCD(tm.tm_hour);
- BIN_TO_BCD(tm.tm_min);
- BIN_TO_BCD(tm.tm_sec);
- tm.tm_mon |= century;
-
- spin_lock(&rtc_lock);
-
- rtc_write(RTC_YEAR, tm.tm_year);
- rtc_write(RTC_MONTH, tm.tm_mon);
- rtc_write(RTC_DAY_OF_MONTH, tm.tm_mday);
- rtc_write(RTC_HOURS, tm.tm_hour);
- rtc_write(RTC_MINUTES, tm.tm_min);
- rtc_write(RTC_SECONDS, tm.tm_sec);
-
- spin_unlock(&rtc_lock);
-
- return 0;
-#endif /* !CONFIG_ETRAX_RTC_READONLY */
- }
-
- case RTC_VLOW_RD:
- {
- int vl_bit = 0;
-
- if (rtc_read(RTC_SECONDS) & 0x80) {
- vl_bit = 1;
- printk(KERN_WARNING "%s: RTC Voltage Low - reliable "
- "date/time information is no longer guaranteed!\n",
- PCF8563_NAME);
- }
- if (copy_to_user((int *) arg, &vl_bit, sizeof(int)))
- return -EFAULT;
-
- return 0;
- }
+ case RTC_RD_TIME:
+ {
+ struct rtc_time tm;
- case RTC_VLOW_SET:
- {
- /* Clear the VL bit in the seconds register */
- int ret = rtc_read(RTC_SECONDS);
+ mutex_lock(&rtc_lock);
+ memset(&tm, 0, sizeof tm);
+ get_rtc_time(&tm);
- rtc_write(RTC_SECONDS, (ret & 0x7F));
+ if (copy_to_user((struct rtc_time *) arg, &tm,
+ sizeof tm)) {
+ spin_unlock(&rtc_lock);
+ return -EFAULT;
+ }
+
+ mutex_unlock(&rtc_lock);
- return 0;
+ return 0;
+ }
+ case RTC_SET_TIME:
+ {
+ int leap;
+ int year;
+ int century;
+ struct rtc_time tm;
+
+ memset(&tm, 0, sizeof tm);
+ if (!capable(CAP_SYS_TIME))
+ return -EPERM;
+
+ if (copy_from_user(&tm, (struct rtc_time *) arg, sizeof tm))
+ return -EFAULT;
+
+ /* Convert from struct tm to struct rtc_time. */
+ tm.tm_year += 1900;
+ tm.tm_mon += 1;
+
+ /*
+ * Check if tm.tm_year is a leap year. A year is a leap
+ * year if it is divisible by 4 but not 100, except
+ * that years divisible by 400 _are_ leap years.
+ */
+ year = tm.tm_year;
+ leap = (tm.tm_mon == 2) &&
+ ((year % 4 == 0 && year % 100 != 0) || year % 400 == 0);
+
+ /* Perform some sanity checks. */
+ if ((tm.tm_year < 1970) ||
+ (tm.tm_mon > 12) ||
+ (tm.tm_mday == 0) ||
+ (tm.tm_mday > days_in_month[tm.tm_mon] + leap) ||
+ (tm.tm_wday >= 7) ||
+ (tm.tm_hour >= 24) ||
+ (tm.tm_min >= 60) ||
+ (tm.tm_sec >= 60))
+ return -EINVAL;
+
+ century = (tm.tm_year >= 2000) ? 0x80 : 0;
+ tm.tm_year = tm.tm_year % 100;
+
+ BIN_TO_BCD(tm.tm_year);
+ BIN_TO_BCD(tm.tm_mon);
+ BIN_TO_BCD(tm.tm_mday);
+ BIN_TO_BCD(tm.tm_hour);
+ BIN_TO_BCD(tm.tm_min);
+ BIN_TO_BCD(tm.tm_sec);
+ tm.tm_mon |= century;
+
+ mutex_lock(&rtc_lock);
+
+ rtc_write(RTC_YEAR, tm.tm_year);
+ rtc_write(RTC_MONTH, tm.tm_mon);
+ rtc_write(RTC_WEEKDAY, tm.tm_wday); /* Not coded in BCD. */
+ rtc_write(RTC_DAY_OF_MONTH, tm.tm_mday);
+ rtc_write(RTC_HOURS, tm.tm_hour);
+ rtc_write(RTC_MINUTES, tm.tm_min);
+ rtc_write(RTC_SECONDS, tm.tm_sec);
+
+ mutex_unlock(&rtc_lock);
+
+ return 0;
+ }
+ case RTC_VL_READ:
+ if (voltage_low) {
+ printk(KERN_ERR "%s: RTC Voltage Low - "
+ "reliable date/time information is no "
+ "longer guaranteed!\n", PCF8563_NAME);
}
- default:
- return -ENOTTY;
+ if (copy_to_user((int *) arg, &voltage_low, sizeof(int)))
+ return -EFAULT;
+ return 0;
+
+ case RTC_VL_CLR:
+ {
+ /* Clear the VL bit in the seconds register in case
+ * the time has not been set already (which would
+ * have cleared it). This does not really matter
+ * because of the cached voltage_low value but do it
+ * anyway for consistency. */
+
+ int ret = rtc_read(RTC_SECONDS);
+
+ rtc_write(RTC_SECONDS, (ret & 0x7F));
+
+ /* Clear the cached value. */
+ voltage_low = 0;
+
+ return 0;
+ }
+ default:
+ return -ENOTTY;
}
return 0;
}
-static int __init
-pcf8563_register(void)
+static int __init pcf8563_register(void)
{
- pcf8563_init();
+ if (pcf8563_init() < 0) {
+ printk(KERN_INFO "%s: Unable to initialize Real-Time Clock "
+ "Driver, %s\n", PCF8563_NAME, DRIVER_VERSION);
+ return -1;
+ }
+
if (register_chrdev(PCF8563_MAJOR, DEVICE_NAME, &pcf8563_fops) < 0) {
printk(KERN_INFO "%s: Unable to get major number %d for RTC device.\n",
PCF8563_NAME, PCF8563_MAJOR);
return -1;
}
- printk(KERN_INFO "%s Real-Time Clock Driver, %s\n", PCF8563_NAME, DRIVER_VERSION);
- return 0;
+ printk(KERN_INFO "%s Real-Time Clock Driver, %s\n", PCF8563_NAME,
+ DRIVER_VERSION);
+
+ /* Check for low voltage, and warn about it. */
+ if (voltage_low) {
+ printk(KERN_WARNING "%s: RTC Voltage Low - reliable date/time "
+ "information is no longer guaranteed!\n", PCF8563_NAME);
+ }
+
+ return 0;
}
module_init(pcf8563_register);
--- /dev/null
+/*
+ * Simple synchronous serial port driver for ETRAX 100LX.
+ *
+ * Synchronous serial ports are used for continuous streamed data like audio.
+ * The default setting for this driver is compatible with the STA 013 MP3
+ * decoder. The driver can easily be tuned to fit other audio encoder/decoders
+ * and SPI
+ *
+ * Copyright (c) 2001-2008 Axis Communications AB
+ *
+ * Author: Mikael Starvik, Johan Adolfsson
+ *
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/major.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/poll.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <asm/irq.h>
+#include <asm/dma.h>
+#include <asm/io.h>
+#include <asm/arch/svinto.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/sync_serial.h>
+#include <asm/arch/io_interface_mux.h>
+
+/* The receiver is a bit tricky beacuse of the continuous stream of data.*/
+/* */
+/* Three DMA descriptors are linked together. Each DMA descriptor is */
+/* responsible for port->bufchunk of a common buffer. */
+/* */
+/* +---------------------------------------------+ */
+/* | +----------+ +----------+ +----------+ | */
+/* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */
+/* +----------+ +----------+ +----------+ */
+/* | | | */
+/* v v v */
+/* +-------------------------------------+ */
+/* | BUFFER | */
+/* +-------------------------------------+ */
+/* |<- data_avail ->| */
+/* readp writep */
+/* */
+/* If the application keeps up the pace readp will be right after writep.*/
+/* If the application can't keep the pace we have to throw away data. */
+/* The idea is that readp should be ready with the data pointed out by */
+/* Descr[i] when the DMA has filled in Descr[i+1]. */
+/* Otherwise we will discard */
+/* the rest of the data pointed out by Descr1 and set readp to the start */
+/* of Descr2 */
+
+#define SYNC_SERIAL_MAJOR 125
+
+/* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
+/* words can be handled */
+#define IN_BUFFER_SIZE 12288
+#define IN_DESCR_SIZE 256
+#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE)
+#define OUT_BUFFER_SIZE 4096
+
+#define DEFAULT_FRAME_RATE 0
+#define DEFAULT_WORD_RATE 7
+
+/* NOTE: Enabling some debug will likely cause overrun or underrun,
+ * especially if manual mode is use.
+ */
+#define DEBUG(x)
+#define DEBUGREAD(x)
+#define DEBUGWRITE(x)
+#define DEBUGPOLL(x)
+#define DEBUGRXINT(x)
+#define DEBUGTXINT(x)
+
+/* Define some macros to access ETRAX 100 registers */
+#define SETF(var, reg, field, val) \
+ do { \
+ var = (var & ~IO_MASK_(reg##_, field##_)) | \
+ IO_FIELD_(reg##_, field##_, val); \
+ } while (0)
+
+#define SETS(var, reg, field, val) \
+ do { \
+ var = (var & ~IO_MASK_(reg##_, field##_)) | \
+ IO_STATE_(reg##_, field##_, _##val); \
+ } while (0)
+
+struct sync_port {
+ /* Etrax registers and bits*/
+ const volatile unsigned *const status;
+ volatile unsigned *const ctrl_data;
+ volatile unsigned *const output_dma_first;
+ volatile unsigned char *const output_dma_cmd;
+ volatile unsigned char *const output_dma_clr_irq;
+ volatile unsigned *const input_dma_first;
+ volatile unsigned char *const input_dma_cmd;
+ volatile unsigned *const input_dma_descr;
+ /* 8*4 */
+ volatile unsigned char *const input_dma_clr_irq;
+ volatile unsigned *const data_out;
+ const volatile unsigned *const data_in;
+ char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
+ char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
+ char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */
+
+ char output_dma_bit; /* In R_IRQ_MASK2_RD */
+ /* End of fields initialised in array */
+ char started; /* 1 if port has been started */
+ char port_nbr; /* Port 0 or 1 */
+ char busy; /* 1 if port is busy */
+
+ char enabled; /* 1 if port is enabled */
+ char use_dma; /* 1 if port uses dma */
+ char tr_running;
+
+ char init_irqs;
+
+ /* Register shadow */
+ unsigned int ctrl_data_shadow;
+ /* Remaining bytes for current transfer */
+ volatile unsigned int out_count;
+ /* Current position in out_buffer */
+ unsigned char *outp;
+ /* 16*4 */
+ /* Next byte to be read by application */
+ volatile unsigned char *volatile readp;
+ /* Next byte to be written by etrax */
+ volatile unsigned char *volatile writep;
+
+ unsigned int in_buffer_size;
+ unsigned int inbufchunk;
+ struct etrax_dma_descr out_descr __attribute__ ((aligned(32)));
+ struct etrax_dma_descr in_descr[NUM_IN_DESCR] __attribute__ ((aligned(32)));
+ unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32)));
+ unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32)));
+ unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32)));
+ struct etrax_dma_descr *next_rx_desc;
+ struct etrax_dma_descr *prev_rx_desc;
+ int full;
+
+ wait_queue_head_t out_wait_q;
+ wait_queue_head_t in_wait_q;
+};
+
+
+static int etrax_sync_serial_init(void);
+static void initialize_port(int portnbr);
+static inline int sync_data_avail(struct sync_port *port);
+
+static int sync_serial_open(struct inode *inode, struct file *file);
+static int sync_serial_release(struct inode *inode, struct file *file);
+static unsigned int sync_serial_poll(struct file *filp, poll_table *wait);
+
+static int sync_serial_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg);
+static ssize_t sync_serial_write(struct file *file, const char *buf,
+ size_t count, loff_t *ppos);
+static ssize_t sync_serial_read(struct file *file, char *buf,
+ size_t count, loff_t *ppos);
+
+#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
+ defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
+ (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
+ defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
+#define SYNC_SER_DMA
+#endif
+
+static void send_word(struct sync_port *port);
+static void start_dma(struct sync_port *port, const char *data, int count);
+static void start_dma_in(struct sync_port *port);
+#ifdef SYNC_SER_DMA
+static irqreturn_t tr_interrupt(int irq, void *dev_id);
+static irqreturn_t rx_interrupt(int irq, void *dev_id);
+#endif
+#if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
+ !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
+ (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
+ !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
+#define SYNC_SER_MANUAL
+#endif
+#ifdef SYNC_SER_MANUAL
+static irqreturn_t manual_interrupt(int irq, void *dev_id);
+#endif
+
+/* The ports */
+static struct sync_port ports[] = {
+ {
+ .status = R_SYNC_SERIAL1_STATUS,
+ .ctrl_data = R_SYNC_SERIAL1_CTRL,
+ .output_dma_first = R_DMA_CH8_FIRST,
+ .output_dma_cmd = R_DMA_CH8_CMD,
+ .output_dma_clr_irq = R_DMA_CH8_CLR_INTR,
+ .input_dma_first = R_DMA_CH9_FIRST,
+ .input_dma_cmd = R_DMA_CH9_CMD,
+ .input_dma_descr = R_DMA_CH9_DESCR,
+ .input_dma_clr_irq = R_DMA_CH9_CLR_INTR,
+ .data_out = R_SYNC_SERIAL1_TR_DATA,
+ .data_in = R_SYNC_SERIAL1_REC_DATA,
+ .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_data),
+ .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready),
+ .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr),
+ .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop),
+ .init_irqs = 1,
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
+ .use_dma = 1,
+#else
+ .use_dma = 0,
+#endif
+ },
+ {
+ .status = R_SYNC_SERIAL3_STATUS,
+ .ctrl_data = R_SYNC_SERIAL3_CTRL,
+ .output_dma_first = R_DMA_CH4_FIRST,
+ .output_dma_cmd = R_DMA_CH4_CMD,
+ .output_dma_clr_irq = R_DMA_CH4_CLR_INTR,
+ .input_dma_first = R_DMA_CH5_FIRST,
+ .input_dma_cmd = R_DMA_CH5_CMD,
+ .input_dma_descr = R_DMA_CH5_DESCR,
+ .input_dma_clr_irq = R_DMA_CH5_CLR_INTR,
+ .data_out = R_SYNC_SERIAL3_TR_DATA,
+ .data_in = R_SYNC_SERIAL3_REC_DATA,
+ .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_data),
+ .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready),
+ .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr),
+ .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop),
+ .init_irqs = 1,
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
+ .use_dma = 1,
+#else
+ .use_dma = 0,
+#endif
+ }
+};
+
+/* Register shadows */
+static unsigned sync_serial_prescale_shadow;
+
+#define NUMBER_OF_PORTS 2
+
+static struct file_operations sync_serial_fops = {
+ .owner = THIS_MODULE,
+ .write = sync_serial_write,
+ .read = sync_serial_read,
+ .poll = sync_serial_poll,
+ .ioctl = sync_serial_ioctl,
+ .open = sync_serial_open,
+ .release = sync_serial_release
+};
+
+static int __init etrax_sync_serial_init(void)
+{
+ ports[0].enabled = 0;
+ ports[1].enabled = 0;
+
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
+ if (cris_request_io_interface(if_sync_serial_1, "sync_ser1")) {
+ printk(KERN_CRIT "ETRAX100LX sync_serial: "
+ "Could not allocate IO group for port %d\n", 0);
+ return -EBUSY;
+ }
+#endif
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
+ if (cris_request_io_interface(if_sync_serial_3, "sync_ser3")) {
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
+ cris_free_io_interface(if_sync_serial_1);
+#endif
+ printk(KERN_CRIT "ETRAX100LX sync_serial: "
+ "Could not allocate IO group for port %d\n", 1);
+ return -EBUSY;
+ }
+#endif
+
+ if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial",
+ &sync_serial_fops) < 0) {
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
+ cris_free_io_interface(if_sync_serial_3);
+#endif
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
+ cris_free_io_interface(if_sync_serial_1);
+#endif
+ printk("unable to get major for synchronous serial port\n");
+ return -EBUSY;
+ }
+
+ /* Deselect synchronous serial ports while configuring. */
+ SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
+ SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
+ *R_GEN_CONFIG_II = gen_config_ii_shadow;
+
+ /* Initialize Ports */
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
+ ports[0].enabled = 1;
+ SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra);
+ SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
+ ports[0].use_dma = 1;
+#else
+ ports[0].use_dma = 0;
+#endif
+ initialize_port(0);
+#endif
+
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
+ ports[1].enabled = 1;
+ SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra);
+ SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
+#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
+ ports[1].use_dma = 1;
+#else
+ ports[1].use_dma = 0;
+#endif
+ initialize_port(1);
+#endif
+
+ *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */
+
+ /* Set up timing */
+ *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = (
+ IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) |
+ IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) |
+ IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) |
+ IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) |
+ IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) |
+ IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate,
+ DEFAULT_FRAME_RATE) |
+ IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) |
+ IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal));
+
+ /* Select synchronous ports */
+ *R_GEN_CONFIG_II = gen_config_ii_shadow;
+
+ printk(KERN_INFO "ETRAX 100LX synchronous serial port driver\n");
+ return 0;
+}
+
+static void __init initialize_port(int portnbr)
+{
+ struct sync_port *port = &ports[portnbr];
+
+ DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr));
+
+ port->started = 0;
+ port->port_nbr = portnbr;
+ port->busy = 0;
+ port->tr_running = 0;
+
+ port->out_count = 0;
+ port->outp = port->out_buffer;
+
+ port->readp = port->flip;
+ port->writep = port->flip;
+ port->in_buffer_size = IN_BUFFER_SIZE;
+ port->inbufchunk = IN_DESCR_SIZE;
+ port->next_rx_desc = &port->in_descr[0];
+ port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1];
+ port->prev_rx_desc->ctrl = d_eol;
+
+ init_waitqueue_head(&port->out_wait_q);
+ init_waitqueue_head(&port->in_wait_q);
+
+ port->ctrl_data_shadow =
+ IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)|
+ IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)|
+ IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) |
+ IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)|
+ IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high);
+
+ if (port->use_dma)
+ port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
+ dma_enable, on);
+ else
+ port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
+ dma_enable, off);
+
+ *port->ctrl_data = port->ctrl_data_shadow;
+}
+
+static inline int sync_data_avail(struct sync_port *port)
+{
+ int avail;
+ unsigned char *start;
+ unsigned char *end;
+
+ start = (unsigned char *)port->readp; /* cast away volatile */
+ end = (unsigned char *)port->writep; /* cast away volatile */
+ /* 0123456789 0123456789
+ * ----- - -----
+ * ^rp ^wp ^wp ^rp
+ */
+ if (end >= start)
+ avail = end - start;
+ else
+ avail = port->in_buffer_size - (start - end);
+ return avail;
+}
+
+static inline int sync_data_avail_to_end(struct sync_port *port)
+{
+ int avail;
+ unsigned char *start;
+ unsigned char *end;
+
+ start = (unsigned char *)port->readp; /* cast away volatile */
+ end = (unsigned char *)port->writep; /* cast away volatile */
+ /* 0123456789 0123456789
+ * ----- -----
+ * ^rp ^wp ^wp ^rp
+ */
+
+ if (end >= start)
+ avail = end - start;
+ else
+ avail = port->flip + port->in_buffer_size - start;
+ return avail;
+}
+
+
+static int sync_serial_open(struct inode *inode, struct file *file)
+{
+ int dev = MINOR(inode->i_rdev);
+ struct sync_port *port;
+ int mode;
+
+ DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev));
+
+ if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
+ DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
+ return -ENODEV;
+ }
+ port = &ports[dev];
+ /* Allow open this device twice (assuming one reader and one writer) */
+ if (port->busy == 2) {
+ DEBUG(printk(KERN_DEBUG "Device is busy.. \n"));
+ return -EBUSY;
+ }
+ if (port->init_irqs) {
+ if (port->use_dma) {
+ if (port == &ports[0]) {
+#ifdef SYNC_SER_DMA
+ if (request_irq(24, tr_interrupt, 0,
+ "synchronous serial 1 dma tr",
+ &ports[0])) {
+ printk(KERN_CRIT "Can't alloc "
+ "sync serial port 1 IRQ");
+ return -EBUSY;
+ } else if (request_irq(25, rx_interrupt, 0,
+ "synchronous serial 1 dma rx",
+ &ports[0])) {
+ free_irq(24, &port[0]);
+ printk(KERN_CRIT "Can't alloc "
+ "sync serial port 1 IRQ");
+ return -EBUSY;
+ } else if (cris_request_dma(8,
+ "synchronous serial 1 dma tr",
+ DMA_VERBOSE_ON_ERROR,
+ dma_ser1)) {
+ free_irq(24, &port[0]);
+ free_irq(25, &port[0]);
+ printk(KERN_CRIT "Can't alloc "
+ "sync serial port 1 "
+ "TX DMA channel");
+ return -EBUSY;
+ } else if (cris_request_dma(9,
+ "synchronous serial 1 dma rec",
+ DMA_VERBOSE_ON_ERROR,
+ dma_ser1)) {
+ cris_free_dma(8, NULL);
+ free_irq(24, &port[0]);
+ free_irq(25, &port[0]);
+ printk(KERN_CRIT "Can't alloc "
+ "sync serial port 1 "
+ "RX DMA channel");
+ return -EBUSY;
+ }
+#endif
+ RESET_DMA(8); WAIT_DMA(8);
+ RESET_DMA(9); WAIT_DMA(9);
+ *R_DMA_CH8_CLR_INTR =
+ IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop,
+ do) |
+ IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr,
+ do);
+ *R_DMA_CH9_CLR_INTR =
+ IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop,
+ do) |
+ IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr,
+ do);
+ *R_IRQ_MASK2_SET =
+ IO_STATE(R_IRQ_MASK2_SET, dma8_eop,
+ set) |
+ IO_STATE(R_IRQ_MASK2_SET, dma9_descr,
+ set);
+ } else if (port == &ports[1]) {
+#ifdef SYNC_SER_DMA
+ if (request_irq(20, tr_interrupt, 0,
+ "synchronous serial 3 dma tr",
+ &ports[1])) {
+ printk(KERN_CRIT "Can't alloc "
+ "sync serial port 3 IRQ");
+ return -EBUSY;
+ } else if (request_irq(21, rx_interrupt, 0,
+ "synchronous serial 3 dma rx",
+ &ports[1])) {
+ free_irq(20, &ports[1]);
+ printk(KERN_CRIT "Can't alloc "
+ "sync serial port 3 IRQ");
+ return -EBUSY;
+ } else if (cris_request_dma(4,
+ "synchronous serial 3 dma tr",
+ DMA_VERBOSE_ON_ERROR,
+ dma_ser3)) {
+ free_irq(21, &ports[1]);
+ free_irq(20, &ports[1]);
+ printk(KERN_CRIT "Can't alloc "
+ "sync serial port 3 "
+ "TX DMA channel");
+ return -EBUSY;
+ } else if (cris_request_dma(5,
+ "synchronous serial 3 dma rec",
+ DMA_VERBOSE_ON_ERROR,
+ dma_ser3)) {
+ cris_free_dma(4, NULL);
+ free_irq(21, &ports[1]);
+ free_irq(20, &ports[1]);
+ printk(KERN_CRIT "Can't alloc "
+ "sync serial port 3 "
+ "RX DMA channel");
+ return -EBUSY;
+ }
+#endif
+ RESET_DMA(4); WAIT_DMA(4);
+ RESET_DMA(5); WAIT_DMA(5);
+ *R_DMA_CH4_CLR_INTR =
+ IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop,
+ do) |
+ IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr,
+ do);
+ *R_DMA_CH5_CLR_INTR =
+ IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop,
+ do) |
+ IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr,
+ do);
+ *R_IRQ_MASK2_SET =
+ IO_STATE(R_IRQ_MASK2_SET, dma4_eop,
+ set) |
+ IO_STATE(R_IRQ_MASK2_SET, dma5_descr,
+ set);
+ }
+ start_dma_in(port);
+ port->init_irqs = 0;
+ } else { /* !port->use_dma */
+#ifdef SYNC_SER_MANUAL
+ if (port == &ports[0]) {
+ if (request_irq(8,
+ manual_interrupt,
+ IRQF_SHARED | IRQF_DISABLED,
+ "synchronous serial manual irq",
+ &ports[0])) {
+ printk(KERN_CRIT "Can't alloc "
+ "sync serial manual irq");
+ return -EBUSY;
+ }
+ } else if (port == &ports[1]) {
+ if (request_irq(8,
+ manual_interrupt,
+ IRQF_SHARED | IRQF_DISABLED,
+ "synchronous serial manual irq",
+ &ports[1])) {
+ printk(KERN_CRIT "Can't alloc "
+ "sync serial manual irq");
+ return -EBUSY;
+ }
+ }
+ port->init_irqs = 0;
+#else
+ panic("sync_serial: Manual mode not supported.\n");
+#endif /* SYNC_SER_MANUAL */
+ }
+ } /* port->init_irqs */
+
+ port->busy++;
+ /* Start port if we use it as input */
+ mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow);
+ if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) ||
+ mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) ||
+ mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) ||
+ mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) {
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
+ running);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
+ enable);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
+ enable);
+ port->started = 1;
+ *port->ctrl_data = port->ctrl_data_shadow;
+ if (!port->use_dma)
+ *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
+ DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev));
+ }
+ return 0;
+}
+
+static int sync_serial_release(struct inode *inode, struct file *file)
+{
+ int dev = MINOR(inode->i_rdev);
+ struct sync_port *port;
+
+ if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
+ DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
+ return -ENODEV;
+ }
+ port = &ports[dev];
+ if (port->busy)
+ port->busy--;
+ if (!port->busy)
+ *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) |
+ (1 << port->transmitter_ready_bit));
+
+ return 0;
+}
+
+
+
+static unsigned int sync_serial_poll(struct file *file, poll_table *wait)
+{
+ int dev = MINOR(file->f_dentry->d_inode->i_rdev);
+ unsigned int mask = 0;
+ struct sync_port *port;
+ DEBUGPOLL(static unsigned int prev_mask = 0);
+
+ port = &ports[dev];
+ poll_wait(file, &port->out_wait_q, wait);
+ poll_wait(file, &port->in_wait_q, wait);
+ /* Some room to write */
+ if (port->out_count < OUT_BUFFER_SIZE)
+ mask |= POLLOUT | POLLWRNORM;
+ /* At least an inbufchunk of data */
+ if (sync_data_avail(port) >= port->inbufchunk)
+ mask |= POLLIN | POLLRDNORM;
+
+ DEBUGPOLL(if (mask != prev_mask)
+ printk(KERN_DEBUG "sync_serial_poll: mask 0x%08X %s %s\n",
+ mask,
+ mask & POLLOUT ? "POLLOUT" : "",
+ mask & POLLIN ? "POLLIN" : "");
+ prev_mask = mask;
+ );
+ return mask;
+}
+
+static int sync_serial_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ int return_val = 0;
+ unsigned long flags;
+
+ int dev = MINOR(file->f_dentry->d_inode->i_rdev);
+ struct sync_port *port;
+
+ if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
+ DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
+ return -1;
+ }
+ port = &ports[dev];
+
+ local_irq_save(flags);
+ /* Disable port while changing config */
+ if (dev) {
+ if (port->use_dma) {
+ RESET_DMA(4); WAIT_DMA(4);
+ port->tr_running = 0;
+ port->out_count = 0;
+ port->outp = port->out_buffer;
+ *R_DMA_CH4_CLR_INTR =
+ IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |
+ IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do);
+ }
+ SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
+ } else {
+ if (port->use_dma) {
+ RESET_DMA(8); WAIT_DMA(8);
+ port->tr_running = 0;
+ port->out_count = 0;
+ port->outp = port->out_buffer;
+ *R_DMA_CH8_CLR_INTR =
+ IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |
+ IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do);
+ }
+ SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
+ }
+ *R_GEN_CONFIG_II = gen_config_ii_shadow;
+ local_irq_restore(flags);
+
+ switch (cmd) {
+ case SSP_SPEED:
+ if (GET_SPEED(arg) == CODEC) {
+ if (dev)
+ SETS(sync_serial_prescale_shadow,
+ R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
+ codec);
+ else
+ SETS(sync_serial_prescale_shadow,
+ R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
+ codec);
+
+ SETF(sync_serial_prescale_shadow,
+ R_SYNC_SERIAL_PRESCALE, prescaler,
+ GET_FREQ(arg));
+ SETF(sync_serial_prescale_shadow,
+ R_SYNC_SERIAL_PRESCALE, frame_rate,
+ GET_FRAME_RATE(arg));
+ SETF(sync_serial_prescale_shadow,
+ R_SYNC_SERIAL_PRESCALE, word_rate,
+ GET_WORD_RATE(arg));
+ } else {
+ SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ tr_baud, GET_SPEED(arg));
+ if (dev)
+ SETS(sync_serial_prescale_shadow,
+ R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
+ baudrate);
+ else
+ SETS(sync_serial_prescale_shadow,
+ R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
+ baudrate);
+ }
+ break;
+ case SSP_MODE:
+ if (arg > 5)
+ return -EINVAL;
+ if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT)
+ *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit;
+ else if (!port->use_dma)
+ *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
+ SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg);
+ break;
+ case SSP_FRAME_SYNC:
+ if (arg & NORMAL_SYNC)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ f_synctype, normal);
+ else if (arg & EARLY_SYNC)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ f_synctype, early);
+
+ if (arg & BIT_SYNC)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ f_syncsize, bit);
+ else if (arg & WORD_SYNC)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ f_syncsize, word);
+ else if (arg & EXTENDED_SYNC)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ f_syncsize, extended);
+
+ if (arg & SYNC_ON)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ f_sync, on);
+ else if (arg & SYNC_OFF)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ f_sync, off);
+
+ if (arg & WORD_SIZE_8)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ wordsize, size8bit);
+ else if (arg & WORD_SIZE_12)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ wordsize, size12bit);
+ else if (arg & WORD_SIZE_16)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ wordsize, size16bit);
+ else if (arg & WORD_SIZE_24)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ wordsize, size24bit);
+ else if (arg & WORD_SIZE_32)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ wordsize, size32bit);
+
+ if (arg & BIT_ORDER_MSB)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ bitorder, msb);
+ else if (arg & BIT_ORDER_LSB)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ bitorder, lsb);
+
+ if (arg & FLOW_CONTROL_ENABLE)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ flow_ctrl, enabled);
+ else if (arg & FLOW_CONTROL_DISABLE)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ flow_ctrl, disabled);
+
+ if (arg & CLOCK_NOT_GATED)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ clk_mode, normal);
+ else if (arg & CLOCK_GATED)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ clk_mode, gated);
+
+ break;
+ case SSP_IPOLARITY:
+ /* NOTE!! negedge is considered NORMAL */
+ if (arg & CLOCK_NORMAL)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ clk_polarity, neg);
+ else if (arg & CLOCK_INVERT)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ clk_polarity, pos);
+
+ if (arg & FRAME_NORMAL)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ frame_polarity, normal);
+ else if (arg & FRAME_INVERT)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ frame_polarity, inverted);
+
+ if (arg & STATUS_NORMAL)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ status_polarity, normal);
+ else if (arg & STATUS_INVERT)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ status_polarity, inverted);
+ break;
+ case SSP_OPOLARITY:
+ if (arg & CLOCK_NORMAL)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ clk_driver, normal);
+ else if (arg & CLOCK_INVERT)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ clk_driver, inverted);
+
+ if (arg & FRAME_NORMAL)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ frame_driver, normal);
+ else if (arg & FRAME_INVERT)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ frame_driver, inverted);
+
+ if (arg & STATUS_NORMAL)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ status_driver, normal);
+ else if (arg & STATUS_INVERT)
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ status_driver, inverted);
+ break;
+ case SSP_SPI:
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl,
+ disabled);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder,
+ msb);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize,
+ size8bit);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize,
+ word);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype,
+ normal);
+ if (arg & SPI_SLAVE) {
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ frame_polarity, inverted);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ clk_polarity, neg);
+ SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ mode, SLAVE_INPUT);
+ } else {
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ frame_driver, inverted);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ clk_driver, inverted);
+ SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
+ mode, MASTER_OUTPUT);
+ }
+ break;
+ case SSP_INBUFCHUNK:
+#if 0
+ if (arg > port->in_buffer_size/NUM_IN_DESCR)
+ return -EINVAL;
+ port->inbufchunk = arg;
+ /* Make sure in_buffer_size is a multiple of inbufchunk */
+ port->in_buffer_size =
+ (port->in_buffer_size/port->inbufchunk) *
+ port->inbufchunk;
+ DEBUG(printk(KERN_DEBUG "inbufchunk %i in_buffer_size: %i\n",
+ port->inbufchunk, port->in_buffer_size));
+ if (port->use_dma) {
+ if (port->port_nbr == 0) {
+ RESET_DMA(9);
+ WAIT_DMA(9);
+ } else {
+ RESET_DMA(5);
+ WAIT_DMA(5);
+ }
+ start_dma_in(port);
+ }
+#endif
+ break;
+ default:
+ return_val = -1;
+ }
+ /* Make sure we write the config without interruption */
+ local_irq_save(flags);
+ /* Set config and enable port */
+ *port->ctrl_data = port->ctrl_data_shadow;
+ nop(); nop(); nop(); nop();
+ *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow;
+ nop(); nop(); nop(); nop();
+ if (dev)
+ SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
+ else
+ SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
+
+ *R_GEN_CONFIG_II = gen_config_ii_shadow;
+ /* Reset DMA. At readout from serial port the data could be shifted
+ * one byte if not resetting DMA.
+ */
+ if (port->use_dma) {
+ if (port->port_nbr == 0) {
+ RESET_DMA(9);
+ WAIT_DMA(9);
+ } else {
+ RESET_DMA(5);
+ WAIT_DMA(5);
+ }
+ start_dma_in(port);
+ }
+ local_irq_restore(flags);
+ return return_val;
+}
+
+
+static ssize_t sync_serial_write(struct file *file, const char *buf,
+ size_t count, loff_t *ppos)
+{
+ int dev = MINOR(file->f_dentry->d_inode->i_rdev);
+ DECLARE_WAITQUEUE(wait, current);
+ struct sync_port *port;
+ unsigned long flags;
+ unsigned long c, c1;
+ unsigned long free_outp;
+ unsigned long outp;
+ unsigned long out_buffer;
+
+ if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
+ DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
+ return -ENODEV;
+ }
+ port = &ports[dev];
+
+ DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu (%d/%d)\n",
+ port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE));
+ /* Space to end of buffer */
+ /*
+ * out_buffer <c1>012345<- c ->OUT_BUFFER_SIZE
+ * outp^ +out_count
+ * ^free_outp
+ * out_buffer 45<- c ->0123OUT_BUFFER_SIZE
+ * +out_count outp^
+ * free_outp
+ *
+ */
+
+ /* Read variables that may be updated by interrupts */
+ local_irq_save(flags);
+ if (count > OUT_BUFFER_SIZE - port->out_count)
+ count = OUT_BUFFER_SIZE - port->out_count;
+
+ outp = (unsigned long)port->outp;
+ free_outp = outp + port->out_count;
+ local_irq_restore(flags);
+ out_buffer = (unsigned long)port->out_buffer;
+
+ /* Find out where and how much to write */
+ if (free_outp >= out_buffer + OUT_BUFFER_SIZE)
+ free_outp -= OUT_BUFFER_SIZE;
+ if (free_outp >= outp)
+ c = out_buffer + OUT_BUFFER_SIZE - free_outp;
+ else
+ c = outp - free_outp;
+ if (c > count)
+ c = count;
+
+ DEBUGWRITE(printk(KERN_DEBUG "w op %08lX fop %08lX c %lu\n",
+ outp, free_outp, c));
+ if (copy_from_user((void *)free_outp, buf, c))
+ return -EFAULT;
+
+ if (c != count) {
+ buf += c;
+ c1 = count - c;
+ DEBUGWRITE(printk(KERN_DEBUG "w2 fi %lu c %lu c1 %lu\n",
+ free_outp-out_buffer, c, c1));
+ if (copy_from_user((void *)out_buffer, buf, c1))
+ return -EFAULT;
+ }
+ local_irq_save(flags);
+ port->out_count += count;
+ local_irq_restore(flags);
+
+ /* Make sure transmitter/receiver is running */
+ if (!port->started) {
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
+ running);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
+ enable);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
+ enable);
+ port->started = 1;
+ }
+
+ *port->ctrl_data = port->ctrl_data_shadow;
+
+ if (file->f_flags & O_NONBLOCK) {
+ local_irq_save(flags);
+ if (!port->tr_running) {
+ if (!port->use_dma) {
+ /* Start sender by writing data */
+ send_word(port);
+ /* and enable transmitter ready IRQ */
+ *R_IRQ_MASK1_SET = 1 <<
+ port->transmitter_ready_bit;
+ } else
+ start_dma(port,
+ (unsigned char *volatile)port->outp, c);
+ }
+ local_irq_restore(flags);
+ DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu NB\n",
+ port->port_nbr, count));
+ return count;
+ }
+
+ /* Sleep until all sent */
+ add_wait_queue(&port->out_wait_q, &wait);
+ set_current_state(TASK_INTERRUPTIBLE);
+ local_irq_save(flags);
+ if (!port->tr_running) {
+ if (!port->use_dma) {
+ /* Start sender by writing data */
+ send_word(port);
+ /* and enable transmitter ready IRQ */
+ *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit;
+ } else
+ start_dma(port, port->outp, c);
+ }
+ local_irq_restore(flags);
+ schedule();
+ set_current_state(TASK_RUNNING);
+ remove_wait_queue(&port->out_wait_q, &wait);
+ if (signal_pending(current))
+ return -EINTR;
+
+ DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", port->port_nbr, count));
+ return count;
+}
+
+static ssize_t sync_serial_read(struct file *file, char *buf,
+ size_t count, loff_t *ppos)
+{
+ int dev = MINOR(file->f_dentry->d_inode->i_rdev);
+ int avail;
+ struct sync_port *port;
+ unsigned char *start;
+ unsigned char *end;
+ unsigned long flags;
+
+ if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
+ DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
+ return -ENODEV;
+ }
+ port = &ports[dev];
+
+ DEBUGREAD(printk(KERN_DEBUG "R%d c %d ri %lu wi %lu /%lu\n",
+ dev, count, port->readp - port->flip,
+ port->writep - port->flip, port->in_buffer_size));
+
+ if (!port->started) {
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
+ running);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
+ enable);
+ SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
+ enable);
+ port->started = 1;
+ }
+ *port->ctrl_data = port->ctrl_data_shadow;
+
+ /* Calculate number of available bytes */
+ /* Save pointers to avoid that they are modified by interrupt */
+ local_irq_save(flags);
+ start = (unsigned char *)port->readp; /* cast away volatile */
+ end = (unsigned char *)port->writep; /* cast away volatile */
+ local_irq_restore(flags);
+ while (start == end && !port->full) {
+ /* No data */
+ if (file->f_flags & O_NONBLOCK)
+ return -EAGAIN;
+
+ interruptible_sleep_on(&port->in_wait_q);
+ if (signal_pending(current))
+ return -EINTR;
+
+ local_irq_save(flags);
+ start = (unsigned char *)port->readp; /* cast away volatile */
+ end = (unsigned char *)port->writep; /* cast away volatile */
+ local_irq_restore(flags);
+ }
+
+ /* Lazy read, never return wrapped data. */
+ if (port->full)
+ avail = port->in_buffer_size;
+ else if (end > start)
+ avail = end - start;
+ else
+ avail = port->flip + port->in_buffer_size - start;
+
+ count = count > avail ? avail : count;
+ if (copy_to_user(buf, start, count))
+ return -EFAULT;
+ /* Disable interrupts while updating readp */
+ local_irq_save(flags);
+ port->readp += count;
+ if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
+ port->readp = port->flip;
+ port->full = 0;
+ local_irq_restore(flags);
+ DEBUGREAD(printk(KERN_DEBUG "r %d\n", count));
+ return count;
+}
+
+static void send_word(struct sync_port *port)
+{
+ switch (IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize,
+ port->ctrl_data_shadow)) {
+ case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
+ port->out_count--;
+ *port->data_out = *port->outp++;
+ if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+ port->outp = port->out_buffer;
+ break;
+ case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
+ {
+ int data = (*port->outp++) << 8;
+ data |= *port->outp++;
+ port->out_count -= 2;
+ *port->data_out = data;
+ if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+ port->outp = port->out_buffer;
+ break;
+ }
+ case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
+ port->out_count -= 2;
+ *port->data_out = *(unsigned short *)port->outp;
+ port->outp += 2;
+ if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+ port->outp = port->out_buffer;
+ break;
+ case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
+ port->out_count -= 3;
+ *port->data_out = *(unsigned int *)port->outp;
+ port->outp += 3;
+ if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+ port->outp = port->out_buffer;
+ break;
+ case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
+ port->out_count -= 4;
+ *port->data_out = *(unsigned int *)port->outp;
+ port->outp += 4;
+ if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+ port->outp = port->out_buffer;
+ break;
+ }
+}
+
+
+static void start_dma(struct sync_port *port, const char *data, int count)
+{
+ port->tr_running = 1;
+ port->out_descr.hw_len = 0;
+ port->out_descr.next = 0;
+ port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */
+ port->out_descr.sw_len = count;
+ port->out_descr.buf = virt_to_phys(data);
+ port->out_descr.status = 0;
+
+ *port->output_dma_first = virt_to_phys(&port->out_descr);
+ *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
+ DEBUGTXINT(printk(KERN_DEBUG "dma %08lX c %d\n",
+ (unsigned long)data, count));
+}
+
+static void start_dma_in(struct sync_port *port)
+{
+ int i;
+ unsigned long buf;
+ port->writep = port->flip;
+
+ if (port->writep > port->flip + port->in_buffer_size) {
+ panic("Offset too large in sync serial driver\n");
+ return;
+ }
+ buf = virt_to_phys(port->in_buffer);
+ for (i = 0; i < NUM_IN_DESCR; i++) {
+ port->in_descr[i].sw_len = port->inbufchunk;
+ port->in_descr[i].ctrl = d_int;
+ port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]);
+ port->in_descr[i].buf = buf;
+ port->in_descr[i].hw_len = 0;
+ port->in_descr[i].status = 0;
+ port->in_descr[i].fifo_len = 0;
+ buf += port->inbufchunk;
+ prepare_rx_descriptor(&port->in_descr[i]);
+ }
+ /* Link the last descriptor to the first */
+ port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]);
+ port->in_descr[i-1].ctrl |= d_eol;
+ port->next_rx_desc = &port->in_descr[0];
+ port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1];
+ *port->input_dma_first = virt_to_phys(port->next_rx_desc);
+ *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
+}
+
+#ifdef SYNC_SER_DMA
+static irqreturn_t tr_interrupt(int irq, void *dev_id)
+{
+ unsigned long ireg = *R_IRQ_MASK2_RD;
+ struct etrax_dma_descr *descr;
+ unsigned int sentl;
+ int handled = 0;
+ int i;
+
+ for (i = 0; i < NUMBER_OF_PORTS; i++) {
+ struct sync_port *port = &ports[i];
+ if (!port->enabled || !port->use_dma)
+ continue;
+
+ /* IRQ active for the port? */
+ if (!(ireg & (1 << port->output_dma_bit)))
+ continue;
+
+ handled = 1;
+
+ /* Clear IRQ */
+ *port->output_dma_clr_irq =
+ IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) |
+ IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do);
+
+ descr = &port->out_descr;
+ if (!(descr->status & d_stop))
+ sentl = descr->sw_len;
+ else
+ /* Otherwise find amount of data sent here */
+ sentl = descr->hw_len;
+
+ port->out_count -= sentl;
+ port->outp += sentl;
+ if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
+ port->outp = port->out_buffer;
+ if (port->out_count) {
+ int c = port->out_buffer + OUT_BUFFER_SIZE - port->outp;
+ if (c > port->out_count)
+ c = port->out_count;
+ DEBUGTXINT(printk(KERN_DEBUG
+ "tx_int DMAWRITE %i %i\n", sentl, c));
+ start_dma(port, port->outp, c);
+ } else {
+ DEBUGTXINT(printk(KERN_DEBUG
+ "tx_int DMA stop %i\n", sentl));
+ port->tr_running = 0;
+ }
+ /* wake up the waiting process */
+ wake_up_interruptible(&port->out_wait_q);
+ }
+ return IRQ_RETVAL(handled);
+} /* tr_interrupt */
+
+static irqreturn_t rx_interrupt(int irq, void *dev_id)
+{
+ unsigned long ireg = *R_IRQ_MASK2_RD;
+ int i;
+ int handled = 0;
+
+ for (i = 0; i < NUMBER_OF_PORTS; i++) {
+ struct sync_port *port = &ports[i];
+
+ if (!port->enabled || !port->use_dma)
+ continue;
+
+ if (!(ireg & (1 << port->input_dma_descr_bit)))
+ continue;
+
+ /* Descriptor interrupt */
+ handled = 1;
+ while (*port->input_dma_descr !=
+ virt_to_phys(port->next_rx_desc)) {
+ if (port->writep + port->inbufchunk > port->flip +
+ port->in_buffer_size) {
+ int first_size = port->flip +
+ port->in_buffer_size - port->writep;
+ memcpy(port->writep,
+ phys_to_virt(port->next_rx_desc->buf),
+ first_size);
+ memcpy(port->flip,
+ phys_to_virt(port->next_rx_desc->buf +
+ first_size),
+ port->inbufchunk - first_size);
+ port->writep = port->flip +
+ port->inbufchunk - first_size;
+ } else {
+ memcpy(port->writep,
+ phys_to_virt(port->next_rx_desc->buf),
+ port->inbufchunk);
+ port->writep += port->inbufchunk;
+ if (port->writep >= port->flip
+ + port->in_buffer_size)
+ port->writep = port->flip;
+ }
+ if (port->writep == port->readp)
+ port->full = 1;
+ prepare_rx_descriptor(port->next_rx_desc);
+ port->next_rx_desc->ctrl |= d_eol;
+ port->prev_rx_desc->ctrl &= ~d_eol;
+ port->prev_rx_desc = phys_to_virt((unsigned)
+ port->next_rx_desc);
+ port->next_rx_desc = phys_to_virt((unsigned)
+ port->next_rx_desc->next);
+ /* Wake up the waiting process */
+ wake_up_interruptible(&port->in_wait_q);
+ *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD,
+ cmd, restart);
+ /* DMA has reached end of descriptor */
+ *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR,
+ clr_descr, do);
+ }
+ }
+ return IRQ_RETVAL(handled);
+} /* rx_interrupt */
+#endif /* SYNC_SER_DMA */
+
+#ifdef SYNC_SER_MANUAL
+static irqreturn_t manual_interrupt(int irq, void *dev_id)
+{
+ int i;
+ int handled = 0;
+
+ for (i = 0; i < NUMBER_OF_PORTS; i++) {
+ struct sync_port *port = &ports[i];
+
+ if (!port->enabled || port->use_dma)
+ continue;
+
+ /* Data received? */
+ if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) {
+ handled = 1;
+ /* Read data */
+ switch (port->ctrl_data_shadow &
+ IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize)) {
+ case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
+ *port->writep++ =
+ *(volatile char *)port->data_in;
+ break;
+ case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
+ {
+ int data = *(unsigned short *)port->data_in;
+ *port->writep = (data & 0x0ff0) >> 4;
+ *(port->writep + 1) = data & 0x0f;
+ port->writep += 2;
+ break;
+ }
+ case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
+ *(unsigned short *)port->writep =
+ *(volatile unsigned short *)port->data_in;
+ port->writep += 2;
+ break;
+ case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
+ *(unsigned int *)port->writep = *port->data_in;
+ port->writep += 3;
+ break;
+ case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
+ *(unsigned int *)port->writep = *port->data_in;
+ port->writep += 4;
+ break;
+ }
+
+ /* Wrap? */
+ if (port->writep >= port->flip + port->in_buffer_size)
+ port->writep = port->flip;
+ if (port->writep == port->readp) {
+ /* Receive buffer overrun, discard oldest */
+ port->readp++;
+ /* Wrap? */
+ if (port->readp >= port->flip +
+ port->in_buffer_size)
+ port->readp = port->flip;
+ }
+ if (sync_data_avail(port) >= port->inbufchunk) {
+ /* Wake up application */
+ wake_up_interruptible(&port->in_wait_q);
+ }
+ }
+
+ /* Transmitter ready? */
+ if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) {
+ if (port->out_count > 0) {
+ /* More data to send */
+ send_word(port);
+ } else {
+ /* Transmission finished */
+ /* Turn off IRQ */
+ *R_IRQ_MASK1_CLR = 1 <<
+ port->transmitter_ready_bit;
+ /* Wake up application */
+ wake_up_interruptible(&port->out_wait_q);
+ }
+ }
+ }
+ return IRQ_RETVAL(handled);
+}
+#endif
+
+module_init(etrax_sync_serial_init);
/* Serialport functions for debugging
*
- * Copyright (c) 2000 Axis Communications AB
+ * Copyright (c) 2000-2007 Axis Communications AB
*
* Authors: Bjorn Wesen
*
* enableDebugIRQ()
* init_etrax_debug()
*
- * $Log: debugport.c,v $
- * Revision 1.27 2005/06/10 10:34:14 starvik
- * Real console support
- *
- * Revision 1.26 2005/06/07 07:06:07 starvik
- * Added LF->CR translation to make ETRAX customers happy.
- *
- * Revision 1.25 2005/03/08 08:56:47 mikaelam
- * Do only set index as port->index if port is defined, otherwise use the index from the command line
- *
- * Revision 1.24 2005/01/19 10:26:33 mikaelam
- * Return the cris serial driver in console device driver callback function
- *
- * Revision 1.23 2005/01/14 10:12:17 starvik
- * KGDB on separate port.
- * Console fixes from 2.4.
- *
- * Revision 1.22 2005/01/11 16:06:13 starvik
- * typo
- *
- * Revision 1.21 2005/01/11 13:49:14 starvik
- * Added raw_printk to be used where we don't trust the console.
- *
- * Revision 1.20 2004/12/27 11:18:32 starvik
- * Merge of Linux 2.6.10 (not functional yet).
- *
- * Revision 1.19 2004/10/21 07:26:16 starvik
- * Made it possible to specify console settings on kernel command line.
- *
- * Revision 1.18 2004/10/19 13:07:37 starvik
- * Merge of Linux 2.6.9
- *
- * Revision 1.17 2004/09/29 10:33:46 starvik
- * Resolved a dealock when printing debug from kernel.
- *
- * Revision 1.16 2004/08/24 06:12:19 starvik
- * Whitespace cleanup
- *
- * Revision 1.15 2004/08/16 12:37:19 starvik
- * Merge of Linux 2.6.8
- *
- * Revision 1.14 2004/05/17 13:11:29 starvik
- * Disable DMA until real serial driver is up
- *
- * Revision 1.13 2004/05/14 07:58:01 starvik
- * Merge of changes from 2.4
- *
- * Revision 1.12 2003/09/11 07:29:49 starvik
- * Merge of Linux 2.6.0-test5
- *
- * Revision 1.11 2003/07/07 09:53:36 starvik
- * Revert all the 2.5.74 merge changes to make the console work again
- *
- * Revision 1.9 2003/02/17 17:07:23 starvik
- * Solved the problem with corrupted debug output (from Linux 2.4)
- * * Wait until DMA, FIFO and pipe is empty before and after transmissions
- * * Buffer data until a FIFO flush can be triggered.
- *
- * Revision 1.8 2003/01/22 06:48:36 starvik
- * Fixed warnings issued by GCC 3.2.1
- *
- * Revision 1.7 2002/12/12 08:26:32 starvik
- * Don't use C-comments inside CVS comments
- *
- * Revision 1.6 2002/12/11 15:42:02 starvik
- * Extracted v10 (ETRAX 100LX) specific stuff from arch/cris/kernel/
- *
- * Revision 1.5 2002/11/20 06:58:03 starvik
- * Compiles with kgdb
- *
- * Revision 1.4 2002/11/19 14:35:24 starvik
- * Changes from linux 2.4
- * Changed struct initializer syntax to the currently preferred notation
- *
- * Revision 1.3 2002/11/06 09:47:03 starvik
- * Modified for new interrupt macros
- *
- * Revision 1.2 2002/01/21 15:21:50 bjornw
- * Update for kdev_t changes
- *
- * Revision 1.6 2001/04/17 13:58:39 orjanf
- * * Renamed CONFIG_KGDB to CONFIG_ETRAX_KGDB.
- *
- * Revision 1.5 2001/03/26 14:22:05 bjornw
- * Namechange of some config options
- *
- * Revision 1.4 2000/10/06 12:37:26 bjornw
- * Use physical addresses when talking to DMA
- *
- *
*/
#include <linux/console.h>
#include <asm/arch/svinto.h>
#include <asm/io.h> /* Get SIMCOUT. */
+extern void reset_watchdog(void);
+
struct dbg_port
{
unsigned int index;
}
};
+#ifdef CONFIG_ETRAX_SERIAL
extern struct tty_driver *serial_driver;
+#endif
struct dbg_port* port =
#if defined(CONFIG_ETRAX_DEBUG_PORT0)
{
int i;
unsigned long flags;
- local_irq_save(flags);
if (!port)
return;
+ local_irq_save(flags);
+
/* Send data */
for (i = 0; i < len; i++) {
/* LF -> CRLF */
;
*port->write = buf[i];
}
- local_irq_restore(flags);
-}
-int raw_printk(const char *fmt, ...)
-{
- static char buf[1024];
- int printed_len;
- static int first = 1;
- if (first) {
- /* Force reinitialization of the port to get manual mode. */
- port->started = 0;
- start_port(port);
- first = 0;
- }
- va_list args;
- va_start(args, fmt);
- printed_len = vsnprintf(buf, sizeof(buf), fmt, args);
- va_end(args);
- console_write_direct(NULL, buf, strlen(buf));
- return printed_len;
+ /*
+ * Feed the watchdog, otherwise it will reset the chip during boot.
+ * The time to send an ordinary boot message line (10-90 chars)
+ * varies between 1-8ms at 115200. What makes up for the additional
+ * 90ms that allows the watchdog to bite?
+ */
+ reset_watchdog();
+
+ local_irq_restore(flags);
}
static void
return 0;
}
+
/* This is a dummy serial device that throws away anything written to it.
* This is used when no debug output is wanted.
*/
{
if (port)
*index = port->index;
+ else
+ *index = 0;
+#ifdef CONFIG_ETRAX_SERIAL
return port ? serial_driver : &dummy_driver;
+#else
+ return &dummy_driver;
+#endif
}
static struct console sercons = {
/* Wrapper for DMA channel allocator that updates DMA client muxing.
- * Copyright 2004, Axis Communications AB
- * $Id: dma.c,v 1.1 2004/12/13 12:21:51 starvik Exp $
+ * Copyright 2004-2007, Axis Communications AB
*/
#include <linux/kernel.h>
-/* $Id: entry.S,v 1.28 2005/06/20 05:06:30 starvik Exp $
- *
+/*
* linux/arch/cris/entry.S
*
* Copyright (C) 2000, 2001, 2002 Axis Communications AB
*
* Authors: Bjorn Wesen (bjornw@axis.com)
- *
- * $Log: entry.S,v $
- * Revision 1.28 2005/06/20 05:06:30 starvik
- * Remove unnecessary diff to kernel.org tree
- *
- * Revision 1.27 2005/03/04 08:16:16 starvik
- * Merge of Linux 2.6.11.
- *
- * Revision 1.26 2005/01/11 13:49:47 starvik
- * Added NMI handler.
- *
- * Revision 1.25 2004/12/27 11:18:32 starvik
- * Merge of Linux 2.6.10 (not functional yet).
- *
- * Revision 1.24 2004/12/22 10:41:23 starvik
- * Updates to make v10 compile with the latest SMP aware generic code (even
- * though v10 will never have SMP).
- *
- * Revision 1.23 2004/10/19 13:07:37 starvik
- * Merge of Linux 2.6.9
- *
- * Revision 1.22 2004/06/21 10:29:55 starvik
- * Merge of Linux 2.6.7
- *
- * Revision 1.21 2004/06/09 05:30:27 starvik
- * Clean up multiple interrupt handling.
- * Prevent interrupts from interrupting each other.
- * Handle all active interrupts.
- *
- * Revision 1.20 2004/06/08 08:55:32 starvik
- * Removed unused code
- *
- * Revision 1.19 2004/06/04 11:56:15 starvik
- * Implemented page table lookup for refills in assembler for improved performance.
- *
- * Revision 1.18 2004/05/11 12:28:25 starvik
- * Merge of Linux 2.6.6
- *
- * Revision 1.17 2003/09/11 07:29:49 starvik
- * Merge of Linux 2.6.0-test5
- *
- * Revision 1.16 2003/07/04 08:27:41 starvik
- * Merge of Linux 2.5.74
- *
- * Revision 1.15 2003/04/09 07:32:55 starvik
- * resume should return task_struct, not thread_info
- *
- * Revision 1.14 2003/04/09 05:20:44 starvik
- * Merge of Linux 2.5.67
- *
- * Revision 1.13 2002/12/11 15:42:02 starvik
- * Extracted v10 (ETRAX 100LX) specific stuff from arch/cris/kernel/*.c
- *
- * Revision 1.12 2002/12/10 09:00:10 starvik
- * Merge of Linux 2.5.51
- *
- * Revision 1.11 2002/12/05 07:53:10 starvik
- * Corrected constants used with btstq
- *
- * Revision 1.10 2002/11/27 08:45:10 starvik
- * pid is in task_struct, not thread_info
- *
- * Revision 1.9 2002/11/26 09:52:05 starvik
- * Added preemptive kernel scheduling (if CONFIG_PREEMPT)
- *
- * Revision 1.8 2002/11/20 11:56:11 starvik
- * Merge of Linux 2.5.48
- *
- * Revision 1.7 2002/11/18 13:02:42 starvik
- * Added fourth parameter to do_notify_resume
- * Minor cleanup
- *
- * Revision 1.6 2002/11/11 10:37:50 starvik
- * Use new asm-offset defines
- * Modified for new location of current->work etc
- * Removed SYMBOL_NAME from syscalls
- * Added some new syscalls
- *
- * Revision 1.5 2002/11/05 06:45:11 starvik
- * Merge of Linux 2.5.45
- *
- * Revision 1.4 2002/02/05 15:41:31 bjornw
- * Rewritten to conform better to current 2.5 code (similar to arch/i386)
- *
- * Revision 1.3 2002/01/21 15:22:20 bjornw
- * NICE_DOGGY fix from 2.4 arch/cris
- *
- * Revision 1.37 2001/12/07 17:03:55 bjornw
- * Call a c-hook called watchdog_bite_hook instead of show_registers directly
- *
- * Revision 1.36 2001/11/22 13:36:36 bjornw
- * * In ret_from_intr, check regs->dccr for usermode reentrance instead of
- * DCCR explicitly (because the latter might not reflect current reality)
- * * In mmu_bus_fault, set $r9 _after_ calling the C-code instead of before
- * since $r9 is call-clobbered and is potentially needed afterwards
- *
- * Revision 1.35 2001/10/30 17:10:15 bjornw
- * Add some syscalls
- *
- * Revision 1.34 2001/10/01 14:45:03 bjornw
- * Removed underscores and added register prefixes
- *
- * Revision 1.33 2001/08/21 13:48:01 jonashg
- * Added fix by HP to avoid oops when doing a hard_reset_now.
- *
- * Revision 1.32 2001/08/14 04:32:02 hp
- * In _resume, add comment why R9 is saved; don't sound like it's call-saved.
- *
- * Revision 1.31 2001/07/25 16:07:42 bjornw
- * softirq_active/mask -> softirq_pending only
- *
- * Revision 1.30 2001/07/05 01:03:32 hp
- * - include asm/errno.h to get ENOSYS.
- * - Use ENOSYS, not local constant LENOSYS; tweak comments.
- * - Explain why .include, not #include is used.
- * - Make oops-register-dump if watchdog bits and it's not expected.
- * - Don't jsr, use jump _hard_reset_now, and skip spurious nop.
- * - Use correct section attribute for section .rodata.
- * - Adjust sys_ni_syscall fill number.
- *
- * Revision 1.29 2001/06/25 14:07:00 hp
- * Fix review comment.
- * * head.S: Use IO_STATE, IO_FIELD and IO_MASK constructs instead of
- * magic numbers. Add comment that -traditional must not be used.
- * * entry.S (SYMBOL_NAME): Change redefinition to use ## concatenation.
- * Correct and update comment.
- * * Makefile (.S.o): Don't use -traditional. Add comment why the
- * toplevel rule can't be used (now that there's a reason).
- *
- * Revision 1.28 2001/06/21 02:00:40 hp
- * * entry.S: Include asm/unistd.h.
- * (_sys_call_table): Use section .rodata, not .data.
- * (_kernel_thread): Move from...
- * * process.c: ... here.
- * * entryoffsets.c (VAL): Break out from...
- * (OF): Use VAL.
- * (LCLONE_VM): New asmified value from CLONE_VM.
- *
- * Revision 1.27 2001/05/29 11:25:27 markusl
- * In case of "spurious_interrupt", do hard_reset instead of hanging system in a loop...
- *
- * Revision 1.26 2001/05/15 15:46:03 bjornw
- * Include config.h now that we use some CONFIG_ options
- *
- * Revision 1.25 2001/05/15 05:38:47 hp
- * Tweaked code in _ret_from_sys_call
- *
- * Revision 1.24 2001/05/15 05:27:49 hp
- * Save r9 in r1 over function call rather than on stack.
- *
- * Revision 1.23 2001/05/15 05:10:00 hp
- * Generate entry.S structure offsets from C
- *
- * Revision 1.22 2001/04/17 13:58:39 orjanf
- * * Renamed CONFIG_KGDB to CONFIG_ETRAX_KGDB.
- *
- * Revision 1.21 2001/04/17 11:33:29 orjanf
- * Updated according to review:
- * * Included asm/sv_addr_ag.h to get macro for internal register.
- * * Corrected comment regarding system call argument passing.
- * * Removed comment about instruction being in a delay slot.
- * * Added comment about SYMBOL_NAME macro.
- *
- * Revision 1.20 2001/04/12 08:51:07 hp
- * - Add entry for sys_fcntl64. In fact copy last piece from i386 including ...
- * - .rept to fill table to safe state with sys_ni_syscall.
- *
- * Revision 1.19 2001/04/04 09:43:32 orjanf
- * * Moved do_sigtrap from traps.c to entry.S.
- * * LTASK_PID need not be global anymore.
- *
- * Revision 1.18 2001/03/26 09:25:02 markusl
- * Updated after review, should now handle USB interrupts correctly.
- *
- * Revision 1.17 2001/03/21 16:12:55 bjornw
- * * Always make room for the cpu status record in the frame, in order to
- * use the same framelength and layout for both mmu busfaults and normal
- * irqs. No need to check for the explicit CRIS_FRAME_FIXUP type anymore.
- * * Fixed bug with using addq for popping the stack in the epilogue - it
- * destroyed the flag register. Use instructions that don't affect the
- * flag register instead.
- * * Removed write to R_PORT_PA_DATA during spurious_interrupt
- *
- * Revision 1.16 2001/03/20 19:43:02 bjornw
- * * Get rid of esp0 setting
- * * Give a 7th argument to a systemcall - the stackframe
- *
- * Revision 1.15 2001/03/05 13:14:30 bjornw
- * Spelling fix
- *
- * Revision 1.14 2001/02/23 08:36:36 perf
- * New ABI; syscallnr=r9, arg5=mof, arg6=srp.
- * Corrected tracesys call check.
- *
- * Revision 1.13 2001/02/15 08:40:55 perf
- * H-P by way of perf;
- * - (_system_call): Don't read system call function address into r1.
- * - (RBFExit): There is no such thing as a null pop. Adjust sp by addq.
- * - (_system_call): Don't use r10 and don't save and restore it.
- * - (THREAD_ESP0): New constant.
- * - (_system_call): Inline set_esp0.
- *
- * Revision 1.12 2001/01/31 17:56:25 orjanf
- * Added definition of LTASK_PID and made it global.
- *
- * Revision 1.11 2001/01/10 21:13:29 bjornw
- * SYMBOL_NAME is defined incorrectly for the compiler options we currently use
- *
- * Revision 1.10 2000/12/18 23:47:56 bjornw
- * * Added syscall trace support (ptrace), completely untested of course
- * * Removed redundant check for NULL entries in syscall_table
- *
- * Revision 1.9 2000/11/21 16:40:51 bjornw
- * * New frame type used when an SBFS frame needs to be popped without
- * actually restarting the instruction
- * * Enable interrupts in signal_return (they did so in x86, I hope it's a good
- * idea)
- *
- * Revision 1.8 2000/11/17 16:53:35 bjornw
- * Added detection of frame-type in Rexit, so that mmu_bus_fault can
- * use ret_from_intr in the return-path to check for signals (like SEGV)
- * and other foul things that might have occurred during the fault.
- *
- * Revision 1.7 2000/10/06 15:04:28 bjornw
- * Include mof in register savings
- *
- * Revision 1.6 2000/09/12 16:02:44 bjornw
- * Linux-2.4.0-test7 derived updates
- *
- * Revision 1.5 2000/08/17 15:35:15 bjornw
- * 2.4.0-test6 changed local_irq_count and friends API
- *
- * Revision 1.4 2000/08/02 13:59:30 bjornw
- * Removed olduname and uname from the syscall list
- *
- * Revision 1.3 2000/07/31 13:32:58 bjornw
- * * Export ret_from_intr
- * * _resume updated (prev/last tjohejsan)
- * * timer_interrupt obsolete
- * * SIGSEGV detection in mmu_bus_fault temporarily disabled
- *
- *
*/
/*
.long sys_epoll_pwait
.long sys_utimensat /* 320 */
.long sys_signalfd
- .long sys_ni_syscall
+ .long sys_timerfd_create
.long sys_eventfd
.long sys_fallocate
+ .long sys_timerfd_settime /* 325 */
+ .long sys_timerfd_gettime
/*
* NOTE!! This doesn't have to be exact - we just have
#define DEBUG_LOG_INCLUDED
#define FAST_TIMER_LOG
-//#define FAST_TIMER_TEST
+/* #define FAST_TIMER_TEST */
#define FAST_TIMER_SANITY_CHECKS
#ifdef FAST_TIMER_SANITY_CHECKS
-#define SANITYCHECK(x) x
static int sanity_failed;
-#else
-#define SANITYCHECK(x)
#endif
#define D1(x)
do_gettimeofday_fast(&t->tv_set);
tmp = fast_timer_list;
- SANITYCHECK({ /* Check so this is not in the list already... */
- while (tmp != NULL)
- {
- if (tmp == t)
- {
- printk(KERN_WARNING
- "timer name: %s data: 0x%08lX already in list!\n", name, data);
- sanity_failed++;
- goto done;
- }
- else
- {
- tmp = tmp->next;
- }
- }
- tmp = fast_timer_list;
- });
+#ifdef FAST_TIMER_SANITY_CHECKS
+ /* Check so this is not in the list already... */
+ while (tmp != NULL) {
+ if (tmp == t) {
+ printk(KERN_WARNING "timer name: %s data: "
+ "0x%08lX already in list!\n", name, data);
+ sanity_failed++;
+ goto done;
+ } else
+ tmp = tmp->next;
+ }
+ tmp = fast_timer_list;
+#endif
t->delay_us = delay_us;
t->function = function;
-/* $Id: head.S,v 1.10 2005/06/20 05:12:54 starvik Exp $
- *
+/*
* Head of the kernel - alter with care
*
* Copyright (C) 2000, 2001 Axis Communications AB
*
* Authors: Bjorn Wesen (bjornw@axis.com)
*
- * $Log: head.S,v $
- * Revision 1.10 2005/06/20 05:12:54 starvik
- * Remove unnecessary diff to kernel.org tree
- *
- * Revision 1.9 2004/12/13 12:21:51 starvik
- * Added I/O and DMA allocators from Linux 2.4
- *
- * Revision 1.8 2004/11/22 11:41:14 starvik
- * Kernel command line may be supplied to kernel. Not used by Axis but may
- * be used by customers.
- *
- * Revision 1.7 2004/05/14 07:58:01 starvik
- * Merge of changes from 2.4
- *
- * Revision 1.6 2003/04/28 05:31:46 starvik
- * Added section attributes
- *
- * Revision 1.5 2002/12/11 15:42:02 starvik
- * Extracted v10 (ETRAX 100LX) specific stuff from arch/cris/kernel/*.c
- *
- * Revision 1.4 2002/11/07 09:00:44 starvik
- * Names changed for init sections
- * init_task_union -> init_thread_union
- *
- * Revision 1.3 2002/02/05 15:38:23 bjornw
- * Oops.. non-CRAMFS_MAGIC should jump over the copying, not into it...
- *
- * Revision 1.2 2001/12/18 13:35:19 bjornw
- * Applied the 2.4.13->2.4.16 CRIS patch to 2.5.1 (is a copy of 2.4.15).
- *
- * Revision 1.43 2001/11/08 15:09:43 starvik
- * Only start MII clock if Ethernet is configured
- *
- * Revision 1.42 2001/11/08 14:37:34 starvik
- * Start MII clock early to make sure that it is running at tranceiver reset
- *
- * Revision 1.41 2001/10/29 14:55:58 pkj
- * Corrected pa$r0 to par0.
- *
- * Revision 1.40 2001/10/03 14:59:57 pkj
- * Added support for resetting the Bluetooth hardware.
- *
- * Revision 1.39 2001/10/01 14:45:03 bjornw
- * Removed underscores and added register prefixes
- *
- * Revision 1.38 2001/09/21 07:14:11 jonashg
- * Made root filesystem (cramfs) use mtdblock driver when booting from flash.
- *
- * Revision 1.37 2001/09/11 13:44:29 orjanf
- * Decouple usage of serial ports for debug and kgdb.
- *
- * Revision 1.36 2001/06/29 12:39:31 pkj
- * Added support for mirroring the first flash to just below the
- * second one, to make them look consecutive to cramfs.
- *
- * Revision 1.35 2001/06/25 14:07:00 hp
- * Fix review comment.
- * * head.S: Use IO_STATE, IO_FIELD and IO_MASK constructs instead of
- * magic numbers. Add comment that -traditional must not be used.
- * * entry.S (SYMBOL_NAME): Change redefinition to use ## concatenation.
- * Correct and update comment.
- * * Makefile (.S.o): Don't use -traditional. Add comment why the
- * toplevel rule can't be used (now that there's a reason).
- *
- * Revision 1.34 2001/05/15 07:08:14 hp
- * Tweak "notice" to reflect that both r8 r9 are used
- *
- * Revision 1.33 2001/05/15 06:40:05 hp
- * Put bulk of code in .text.init, data in .data.init
- *
- * Revision 1.32 2001/05/15 06:18:56 hp
- * Execute review comment: s/bcc/bhs/g; s/bcs/blo/g
- *
- * Revision 1.31 2001/05/15 06:08:40 hp
- * Add sentence about autodetecting the bit31-MMU-bug
- *
- * Revision 1.30 2001/05/15 06:00:05 hp
- * Update comment: LOW_MAP is not forced on xsim anymore.
- *
- * Revision 1.29 2001/04/18 12:51:59 orjanf
- * * Reverted review change regarding the use of bcs/bcc.
- * * Removed non-working LED-clearing code.
- *
- * Revision 1.28 2001/04/17 13:58:39 orjanf
- * * Renamed CONFIG_KGDB to CONFIG_ETRAX_KGDB.
- *
- * Revision 1.27 2001/04/17 11:42:35 orjanf
- * Changed according to review:
- * * Added comment explaining memory map bug.
- * * Changed bcs and bcc to blo and bhs, respectively.
- * * Removed mentioning of Stallone and Olga boards.
- *
- * Revision 1.26 2001/04/06 12:31:07 jonashg
- * Check for cramfs in flash before RAM instead of RAM before flash.
- *
- * Revision 1.25 2001/04/04 06:23:53 starvik
- * Initialize DRAM if not already initialized
- *
- * Revision 1.24 2001/04/03 11:12:00 starvik
- * Removed dram init (done by rescue or etrax100boot
- * Corrected include
- *
- * Revision 1.23 2001/04/03 09:53:03 starvik
- * Include hw_settings.S
- *
- * Revision 1.22 2001/03/26 14:23:26 bjornw
- * Namechange of some config options
- *
- * Revision 1.21 2001/03/08 12:14:41 bjornw
- * * Config name for ETRAX IDE was renamed
- * * Removed G27 auto-setting when JULIETTE is chosen (need to make this
- * a new config option later)
- *
- * Revision 1.20 2001/02/23 12:47:56 bjornw
- * MMU regs during LOW_MAP updated to reflect a newer reality
- *
- * Revision 1.19 2001/02/19 11:12:07 bjornw
- * Changed comment header format
- *
- * Revision 1.18 2001/02/15 07:25:38 starvik
- * Added support for synchronous serial ports
- *
- * Revision 1.17 2001/02/08 15:53:13 starvik
- * Last commit removed some important ifdefs
- *
- * Revision 1.16 2001/02/08 15:20:38 starvik
- * Include dram_init.S as inline
- *
- * Revision 1.15 2001/01/29 18:12:01 bjornw
- * Corrected some comments
- *
- * Revision 1.14 2001/01/29 13:11:29 starvik
- * Include dram_init.S (with DRAM/SDRAM initialization)
- *
- * Revision 1.13 2001/01/23 14:54:57 markusl
- * Updated for USB
- * i.e. added r_gen_config settings
- *
- * Revision 1.12 2001/01/19 16:16:29 perf
- * Added temporary mapping of 0x0c->0x0c to avoid flash loading confusion.
- * Renamed serial options from ETRAX100 to ETRAX.
- *
- * Revision 1.11 2001/01/16 16:31:38 bjornw
- * * Changed name and semantics of running_from_flash to romfs_in_flash,
- * set by head.S to indicate to setup.c whether there is a cramfs image
- * after the kernels BSS or not. Should work for all three boot-cases
- * (DRAM with cramfs in DRAM, DRAM with cramfs in flash (compressed boot),
- * and flash with cramfs in flash)
- *
- * Revision 1.10 2001/01/16 14:12:21 bjornw
- * * Check for cramfs start passed in r9 from the decompressor, if all other
- * cramfs options fail (if we boot from DRAM but don't find a cramfs image
- * after the kernel in DRAM, it is probably still in the flash)
- * * Check magic in cramfs detection when booting from flash directly
- *
- * Revision 1.9 2001/01/15 17:17:02 bjornw
- * * Corrected the code that detects the cramfs lengths
- * * Added a comment saying that the above does not work due to other
- * reasons..
- *
- * Revision 1.8 2001/01/15 16:27:51 jonashg
- * Made boot after flashing work.
- * * end destination is __vmlinux_end in RAM.
- * * _romfs_start moved because of virtual memory.
- *
- * Revision 1.7 2000/11/21 13:55:29 bjornw
- * Use CONFIG_CRIS_LOW_MAP for the low VM map instead of explicit CPU type
- *
- * Revision 1.6 2000/10/06 12:36:55 bjornw
- * Forgot swapper_pg_dir when changing memory map..
- *
- * Revision 1.5 2000/10/04 16:49:30 bjornw
- * * Fixed memory mapping in LX
- * * Check for cramfs instead of romfs
- *
*/
#define ASSEMBLER_MACROS_ONLY
moveq 0,$r0
+ ;; Select or disable serial port 2
+#ifdef CONFIG_ETRAX_SERIAL_PORT2
+ or.d IO_STATE (R_GEN_CONFIG, ser2, select),$r0
+#else
+ or.d IO_STATE (R_GEN_CONFIG, ser2, disable),$r0
+#endif
+
;; Init interfaces (disable them).
or.d IO_STATE (R_GEN_CONFIG, scsi0, disable) \
| IO_STATE (R_GEN_CONFIG, ata, disable) \
| IO_STATE (R_GEN_CONFIG, par0, disable) \
- | IO_STATE (R_GEN_CONFIG, ser2, disable) \
| IO_STATE (R_GEN_CONFIG, mio, disable) \
| IO_STATE (R_GEN_CONFIG, scsi1, disable) \
| IO_STATE (R_GEN_CONFIG, scsi0w, disable) \
| IO_STATE (R_SERIAL1_TR_CTRL, tr_bitnr, tr_8bit),$r0
move.b $r0,[R_SERIAL1_TR_CTRL]
+#ifdef CONFIG_ETRAX_SERIAL_PORT2
+ ;; setup the serial port 2 at 115200 baud for debug purposes
+
+ moveq IO_STATE (R_SERIAL2_XOFF, tx_stop, enable) \
+ | IO_STATE (R_SERIAL2_XOFF, auto_xoff, disable) \
+ | IO_FIELD (R_SERIAL2_XOFF, xoff_char, 0),$r0
+ move.d $r0,[R_SERIAL2_XOFF]
+
+ ; 115.2kbaud for both transmit and receive
+ move.b IO_STATE (R_SERIAL2_BAUD, tr_baud, c115k2Hz) \
+ | IO_STATE (R_SERIAL2_BAUD, rec_baud, c115k2Hz),$r0
+ move.b $r0,[R_SERIAL2_BAUD]
+
+ ; Set up and enable the serial2 receiver.
+ move.b IO_STATE (R_SERIAL2_REC_CTRL, dma_err, stop) \
+ | IO_STATE (R_SERIAL2_REC_CTRL, rec_enable, enable) \
+ | IO_STATE (R_SERIAL2_REC_CTRL, rts_, active) \
+ | IO_STATE (R_SERIAL2_REC_CTRL, sampling, middle) \
+ | IO_STATE (R_SERIAL2_REC_CTRL, rec_stick_par, normal) \
+ | IO_STATE (R_SERIAL2_REC_CTRL, rec_par, even) \
+ | IO_STATE (R_SERIAL2_REC_CTRL, rec_par_en, disable) \
+ | IO_STATE (R_SERIAL2_REC_CTRL, rec_bitnr, rec_8bit),$r0
+ move.b $r0,[R_SERIAL2_REC_CTRL]
+
+ ; Set up and enable the serial2 transmitter.
+ move.b IO_FIELD (R_SERIAL2_TR_CTRL, txd, 0) \
+ | IO_STATE (R_SERIAL2_TR_CTRL, tr_enable, enable) \
+ | IO_STATE (R_SERIAL2_TR_CTRL, auto_cts, disabled) \
+ | IO_STATE (R_SERIAL2_TR_CTRL, stop_bits, one_bit) \
+ | IO_STATE (R_SERIAL2_TR_CTRL, tr_stick_par, normal) \
+ | IO_STATE (R_SERIAL2_TR_CTRL, tr_par, even) \
+ | IO_STATE (R_SERIAL2_TR_CTRL, tr_par_en, disable) \
+ | IO_STATE (R_SERIAL2_TR_CTRL, tr_bitnr, tr_8bit),$r0
+ move.b $r0,[R_SERIAL2_TR_CTRL]
+#endif
#ifdef CONFIG_ETRAX_SERIAL_PORT3
;; setup the serial port 3 at 115200 baud for debug purposes
/* IO interface mux allocator for ETRAX100LX.
- * Copyright 2004, Axis Communications AB
- * $Id: io_interface_mux.c,v 1.2 2004/12/21 12:08:38 starvik Exp $
+ * Copyright 2004-2007, Axis Communications AB
*/
-/* C.f. ETRAX100LX Designer's Reference 20.9 */
+/* C.f. ETRAX100LX Designer's Reference chapter 19.9 */
#include <linux/kernel.h>
#include <linux/slab.h>
struct if_group
{
enum io_if_group group;
- unsigned char used;
- enum cris_io_interface owner;
+ /* name - the name of the group 'A' to 'F' */
+ char *name;
+ /* used - a bit mask of all pins in the group in the order listed
+ * in the tables in 19.9.1 to 19.9.6. Note that no
+ * distinction is made between in, out and in/out pins. */
+ unsigned int used;
};
struct interface
{
enum cris_io_interface ioif;
+ /* name - the name of the interface */
+ char *name;
+ /* groups - OR'ed together io_if_group flags describing what pin groups
+ * the interface uses pins in. */
unsigned char groups;
+ /* used - set when the interface is allocated. */
unsigned char used;
char *owner;
+ /* group_a through group_f - bit masks describing what pins in the
+ * pin groups the interface uses. */
+ unsigned int group_a;
+ unsigned int group_b;
+ unsigned int group_c;
+ unsigned int group_d;
+ unsigned int group_e;
+ unsigned int group_f;
+
+ /* gpio_g_in, gpio_g_out, gpio_b - bit masks telling what pins in the
+ * GPIO ports the interface uses. This could be reconstucted using
+ * the group_X masks and a table of what pins the GPIO ports use,
+ * but that would be messy. */
unsigned int gpio_g_in;
unsigned int gpio_g_out;
unsigned char gpio_b;
static struct if_group if_groups[6] = {
{
.group = group_a,
+ .name = "A",
.used = 0,
},
{
.group = group_b,
+ .name = "B",
.used = 0,
},
{
.group = group_c,
+ .name = "C",
.used = 0,
},
{
.group = group_d,
+ .name = "D",
.used = 0,
},
{
.group = group_e,
+ .name = "E",
.used = 0,
},
{
.group = group_f,
+ .name = "F",
.used = 0,
}
};
/* Begin Non-multiplexed interfaces */
{
.ioif = if_eth,
+ .name = "ethernet",
.groups = 0,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0,
.gpio_g_out = 0,
.gpio_b = 0
},
{
.ioif = if_serial_0,
+ .name = "serial_0",
.groups = 0,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0,
.gpio_g_out = 0,
.gpio_b = 0
/* End Non-multiplexed interfaces */
{
.ioif = if_serial_1,
+ .name = "serial_1",
.groups = group_e,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0x0f,
+ .group_f = 0,
+
.gpio_g_in = 0x00000000,
.gpio_g_out = 0x00000000,
.gpio_b = 0x00
},
{
.ioif = if_serial_2,
+ .name = "serial_2",
.groups = group_b,
+
+ .group_a = 0,
+ .group_b = 0x0f,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0x000000c0,
.gpio_g_out = 0x000000c0,
.gpio_b = 0x00
},
{
.ioif = if_serial_3,
+ .name = "serial_3",
.groups = group_c,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0x0f,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0xc0000000,
.gpio_g_out = 0xc0000000,
.gpio_b = 0x00
},
{
.ioif = if_sync_serial_1,
- .groups = group_e | group_f, /* if_sync_serial_1 and if_sync_serial_3
- can be used simultaneously */
+ .name = "sync_serial_1",
+ .groups = group_e | group_f,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0x0f,
+ .group_f = 0x10,
+
.gpio_g_in = 0x00000000,
.gpio_g_out = 0x00000000,
.gpio_b = 0x10
},
{
.ioif = if_sync_serial_3,
+ .name = "sync_serial_3",
.groups = group_c | group_f,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0x0f,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0x80,
+
.gpio_g_in = 0xc0000000,
.gpio_g_out = 0xc0000000,
.gpio_b = 0x80
},
{
.ioif = if_shared_ram,
+ .name = "shared_ram",
.groups = group_a,
+
+ .group_a = 0x7f8ff,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0x0000ff3e,
.gpio_g_out = 0x0000ff38,
.gpio_b = 0x00
},
{
.ioif = if_shared_ram_w,
+ .name = "shared_ram_w",
.groups = group_a | group_d,
+
+ .group_a = 0x7f8ff,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0xff,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0x00ffff3e,
.gpio_g_out = 0x00ffff38,
.gpio_b = 0x00
},
{
.ioif = if_par_0,
+ .name = "par_0",
.groups = group_a,
+
+ .group_a = 0x7fbff,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0x0000ff3e,
.gpio_g_out = 0x0000ff3e,
.gpio_b = 0x00
},
{
.ioif = if_par_1,
+ .name = "par_1",
.groups = group_d,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0x7feff,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0x3eff0000,
.gpio_g_out = 0x3eff0000,
.gpio_b = 0x00
},
{
.ioif = if_par_w,
+ .name = "par_w",
.groups = group_a | group_d,
+
+ .group_a = 0x7fbff,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0xff,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0x00ffff3e,
.gpio_g_out = 0x00ffff3e,
.gpio_b = 0x00
},
{
.ioif = if_scsi8_0,
- .groups = group_a | group_b | group_f, /* if_scsi8_0 and if_scsi8_1
- can be used simultaneously */
+ .name = "scsi8_0",
+ .groups = group_a | group_b | group_f,
+
+ .group_a = 0x7ffff,
+ .group_b = 0x0f,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0x10,
+
.gpio_g_in = 0x0000ffff,
.gpio_g_out = 0x0000ffff,
.gpio_b = 0x10
},
{
.ioif = if_scsi8_1,
- .groups = group_c | group_d | group_f, /* if_scsi8_0 and if_scsi8_1
- can be used simultaneously */
+ .name = "scsi8_1",
+ .groups = group_c | group_d | group_f,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0x0f,
+ .group_d = 0x7ffff,
+ .group_e = 0,
+ .group_f = 0x80,
+
.gpio_g_in = 0xffff0000,
.gpio_g_out = 0xffff0000,
.gpio_b = 0x80
},
{
.ioif = if_scsi_w,
+ .name = "scsi_w",
.groups = group_a | group_b | group_d | group_f,
+
+ .group_a = 0x7ffff,
+ .group_b = 0x0f,
+ .group_c = 0,
+ .group_d = 0x601ff,
+ .group_e = 0,
+ .group_f = 0x90,
+
.gpio_g_in = 0x01ffffff,
.gpio_g_out = 0x07ffffff,
.gpio_b = 0x80
},
{
.ioif = if_ata,
+ .name = "ata",
.groups = group_a | group_b | group_c | group_d,
+
+ .group_a = 0x7ffff,
+ .group_b = 0x0f,
+ .group_c = 0x0f,
+ .group_d = 0x7cfff,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0xf9ffffff,
.gpio_g_out = 0xffffffff,
.gpio_b = 0x80
},
{
.ioif = if_csp,
- .groups = group_f, /* if_csp and if_i2c can be used simultaneously */
+ .name = "csp",
+ .groups = group_f,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0xfc,
+
.gpio_g_in = 0x00000000,
.gpio_g_out = 0x00000000,
.gpio_b = 0xfc
},
{
.ioif = if_i2c,
- .groups = group_f, /* if_csp and if_i2c can be used simultaneously */
+ .name = "i2c",
+ .groups = group_f,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0x03,
+
.gpio_g_in = 0x00000000,
.gpio_g_out = 0x00000000,
.gpio_b = 0x03
},
{
.ioif = if_usb_1,
+ .name = "usb_1",
.groups = group_e | group_f,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0x0f,
+ .group_f = 0x2c,
+
.gpio_g_in = 0x00000000,
.gpio_g_out = 0x00000000,
.gpio_b = 0x2c
},
{
.ioif = if_usb_2,
+ .name = "usb_2",
.groups = group_d,
- .gpio_g_in = 0x0e000000,
- .gpio_g_out = 0x3c000000,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0x33e00,
+ .group_f = 0,
+
+ .gpio_g_in = 0x3e000000,
+ .gpio_g_out = 0x0c000000,
.gpio_b = 0x00
},
/* GPIO pins */
{
.ioif = if_gpio_grp_a,
+ .name = "gpio_a",
.groups = group_a,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0x0000ff3f,
.gpio_g_out = 0x0000ff3f,
.gpio_b = 0x00
},
{
.ioif = if_gpio_grp_b,
+ .name = "gpio_b",
.groups = group_b,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0x000000c0,
.gpio_g_out = 0x000000c0,
.gpio_b = 0x00
},
{
.ioif = if_gpio_grp_c,
+ .name = "gpio_c",
.groups = group_c,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0xc0000000,
.gpio_g_out = 0xc0000000,
.gpio_b = 0x00
},
{
.ioif = if_gpio_grp_d,
+ .name = "gpio_d",
.groups = group_d,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0x3fff0000,
.gpio_g_out = 0x3fff0000,
.gpio_b = 0x00
},
{
.ioif = if_gpio_grp_e,
+ .name = "gpio_e",
.groups = group_e,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0x00000000,
.gpio_g_out = 0x00000000,
.gpio_b = 0x00
},
{
.ioif = if_gpio_grp_f,
+ .name = "gpio_f",
.groups = group_f,
+
+ .group_a = 0,
+ .group_b = 0,
+ .group_c = 0,
+ .group_d = 0,
+ .group_e = 0,
+ .group_f = 0,
+
.gpio_g_in = 0x00000000,
.gpio_g_out = 0x00000000,
.gpio_b = 0xff
static struct watcher *watchers = NULL;
+/* The pins that are free to use in the GPIO ports. */
static unsigned int gpio_in_pins = 0xffffffff;
static unsigned int gpio_out_pins = 0xffffffff;
static unsigned char gpio_pb_pins = 0xff;
static unsigned char gpio_pa_pins = 0xff;
+/* Identifiers for the owners of the GPIO pins. */
static enum cris_io_interface gpio_pa_owners[8];
static enum cris_io_interface gpio_pb_owners[8];
static enum cris_io_interface gpio_pg_owners[32];
struct if_group *grp;
unsigned char group_set;
unsigned long flags;
+ int res = 0;
(void)cris_io_interface_init();
DBG(printk("cris_request_io_interface(%d, \"%s\")\n", ioif, device_id));
if ((ioif >= if_max_interfaces) || (ioif < 0)) {
- printk(KERN_CRIT "cris_request_io_interface: Bad interface %u submitted for %s\n",
+ printk(KERN_CRIT "cris_request_io_interface: Bad interface "
+ "%u submitted for %s\n",
ioif,
device_id);
return -EINVAL;
local_irq_save(flags);
if (interfaces[ioif].used) {
- local_irq_restore(flags);
- printk(KERN_CRIT "cris_io_interface: Cannot allocate interface for %s, in use by %s\n",
+ printk(KERN_CRIT "cris_io_interface: Cannot allocate interface "
+ "%s for %s, in use by %s\n",
+ interfaces[ioif].name,
device_id,
interfaces[ioif].owner);
- return -EBUSY;
+ res = -EBUSY;
+ goto exit;
}
- /* Check that all required groups are free before allocating, */
+ /* Check that all required pins in the used groups are free
+ * before allocating. */
group_set = interfaces[ioif].groups;
while (NULL != (grp = get_group(group_set))) {
- if (grp->used) {
- if (grp->group == group_f) {
- if ((if_sync_serial_1 == ioif) ||
- (if_sync_serial_3 == ioif)) {
- if ((grp->owner != if_sync_serial_1) &&
- (grp->owner != if_sync_serial_3)) {
- local_irq_restore(flags);
- return -EBUSY;
- }
- } else if ((if_scsi8_0 == ioif) ||
- (if_scsi8_1 == ioif)) {
- if ((grp->owner != if_scsi8_0) &&
- (grp->owner != if_scsi8_1)) {
- local_irq_restore(flags);
- return -EBUSY;
- }
- }
- } else {
- local_irq_restore(flags);
- return -EBUSY;
- }
+ unsigned int if_group_use = 0;
+
+ switch (grp->group) {
+ case group_a:
+ if_group_use = interfaces[ioif].group_a;
+ break;
+ case group_b:
+ if_group_use = interfaces[ioif].group_b;
+ break;
+ case group_c:
+ if_group_use = interfaces[ioif].group_c;
+ break;
+ case group_d:
+ if_group_use = interfaces[ioif].group_d;
+ break;
+ case group_e:
+ if_group_use = interfaces[ioif].group_e;
+ break;
+ case group_f:
+ if_group_use = interfaces[ioif].group_f;
+ break;
+ default:
+ BUG_ON(1);
}
+
+ if (if_group_use & grp->used) {
+ printk(KERN_INFO "cris_request_io_interface: group "
+ "%s needed by %s not available\n",
+ grp->name, interfaces[ioif].name);
+ res = -EBUSY;
+ goto exit;
+ }
+
group_set = clear_group_from_set(group_set, grp);
}
/* Are the required GPIO pins available too? */
- if (((interfaces[ioif].gpio_g_in & gpio_in_pins) != interfaces[ioif].gpio_g_in) ||
- ((interfaces[ioif].gpio_g_out & gpio_out_pins) != interfaces[ioif].gpio_g_out) ||
- ((interfaces[ioif].gpio_b & gpio_pb_pins) != interfaces[ioif].gpio_b)) {
- local_irq_restore(flags);
- printk(KERN_CRIT "cris_request_io_interface: Could not get required pins for interface %u\n",
- ioif);
- return -EBUSY;
- }
-
- /* All needed I/O pins and pin groups are free, allocate. */
- group_set = interfaces[ioif].groups;
- while (NULL != (grp = get_group(group_set))) {
- grp->used = 1;
- grp->owner = ioif;
- group_set = clear_group_from_set(group_set, grp);
+ if (((interfaces[ioif].gpio_g_in & gpio_in_pins) !=
+ interfaces[ioif].gpio_g_in) ||
+ ((interfaces[ioif].gpio_g_out & gpio_out_pins) !=
+ interfaces[ioif].gpio_g_out) ||
+ ((interfaces[ioif].gpio_b & gpio_pb_pins) !=
+ interfaces[ioif].gpio_b)) {
+ printk(KERN_CRIT "cris_request_io_interface: Could not get "
+ "required pins for interface %u\n", ioif);
+ res = -EBUSY;
+ goto exit;
}
+ /* Check which registers need to be reconfigured. */
gens = genconfig_shadow;
gens_ii = gen_config_ii_shadow;
set_gen_config = 0;
break;
default:
- panic("cris_request_io_interface: Bad interface %u submitted for %s\n",
- ioif,
- device_id);
+ printk(KERN_INFO "cris_request_io_interface: Bad interface "
+ "%u submitted for %s\n",
+ ioif, device_id);
+ res = -EBUSY;
+ goto exit;
+ }
+
+ /* All needed I/O pins and pin groups are free, allocate. */
+ group_set = interfaces[ioif].groups;
+ while (NULL != (grp = get_group(group_set))) {
+ unsigned int if_group_use = 0;
+
+ switch (grp->group) {
+ case group_a:
+ if_group_use = interfaces[ioif].group_a;
+ break;
+ case group_b:
+ if_group_use = interfaces[ioif].group_b;
+ break;
+ case group_c:
+ if_group_use = interfaces[ioif].group_c;
+ break;
+ case group_d:
+ if_group_use = interfaces[ioif].group_d;
+ break;
+ case group_e:
+ if_group_use = interfaces[ioif].group_e;
+ break;
+ case group_f:
+ if_group_use = interfaces[ioif].group_f;
+ break;
+ default:
+ BUG_ON(1);
+ }
+ grp->used |= if_group_use;
+
+ group_set = clear_group_from_set(group_set, grp);
}
interfaces[ioif].used = 1;
*R_GEN_CONFIG_II = gen_config_ii_shadow;
}
- DBG(printk("GPIO pins: available before: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- gpio_in_pins, gpio_out_pins, gpio_pb_pins));
- DBG(printk("grabbing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- interfaces[ioif].gpio_g_in,
- interfaces[ioif].gpio_g_out,
- interfaces[ioif].gpio_b));
+ DBG(printk(KERN_DEBUG "GPIO pins: available before: "
+ "g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
+ gpio_in_pins, gpio_out_pins, gpio_pb_pins));
+ DBG(printk(KERN_DEBUG
+ "grabbing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
+ interfaces[ioif].gpio_g_in,
+ interfaces[ioif].gpio_g_out,
+ interfaces[ioif].gpio_b));
gpio_in_pins &= ~interfaces[ioif].gpio_g_in;
gpio_out_pins &= ~interfaces[ioif].gpio_g_out;
gpio_pb_pins &= ~interfaces[ioif].gpio_b;
- DBG(printk("GPIO pins: available after: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
- gpio_in_pins, gpio_out_pins, gpio_pb_pins));
+ DBG(printk(KERN_DEBUG "GPIO pins: available after: "
+ "g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
+ gpio_in_pins, gpio_out_pins, gpio_pb_pins));
+exit:
local_irq_restore(flags);
-
- notify_watchers();
-
- return 0;
+ if (res == 0)
+ notify_watchers();
+ return res;
}
}
group_set = interfaces[ioif].groups;
while (NULL != (grp = get_group(group_set))) {
- if (grp->group == group_f) {
- switch (ioif)
- {
- case if_sync_serial_1:
- if ((grp->owner == if_sync_serial_1) &&
- interfaces[if_sync_serial_3].used) {
- grp->owner = if_sync_serial_3;
- } else
- grp->used = 0;
- break;
- case if_sync_serial_3:
- if ((grp->owner == if_sync_serial_3) &&
- interfaces[if_sync_serial_1].used) {
- grp->owner = if_sync_serial_1;
- } else
- grp->used = 0;
- break;
- case if_scsi8_0:
- if ((grp->owner == if_scsi8_0) &&
- interfaces[if_scsi8_1].used) {
- grp->owner = if_scsi8_1;
- } else
- grp->used = 0;
- break;
- case if_scsi8_1:
- if ((grp->owner == if_scsi8_1) &&
- interfaces[if_scsi8_0].used) {
- grp->owner = if_scsi8_0;
- } else
- grp->used = 0;
- break;
- default:
- grp->used = 0;
- }
- } else {
- grp->used = 0;
+ unsigned int if_group_use = 0;
+
+ switch (grp->group) {
+ case group_a:
+ if_group_use = interfaces[ioif].group_a;
+ break;
+ case group_b:
+ if_group_use = interfaces[ioif].group_b;
+ break;
+ case group_c:
+ if_group_use = interfaces[ioif].group_c;
+ break;
+ case group_d:
+ if_group_use = interfaces[ioif].group_d;
+ break;
+ case group_e:
+ if_group_use = interfaces[ioif].group_e;
+ break;
+ case group_f:
+ if_group_use = interfaces[ioif].group_f;
+ break;
+ default:
+ BUG_ON(1);
}
+
+ if ((grp->used & if_group_use) != if_group_use)
+ BUG_ON(1);
+ grp->used = grp->used & ~if_group_use;
+
group_set = clear_group_from_set(group_set, grp);
}
interfaces[ioif].used = 0;
-/* $Id: irq.c,v 1.4 2005/01/04 12:22:28 starvik Exp $
- *
+/*
* linux/arch/cris/kernel/irq.c
*
* Copyright (c) 2000-2002 Axis Communications AB
#include <linux/kernel.h>
#include <linux/init.h>
-/* From kgdb.c. */
-extern void kgdb_init(void);
-extern void breakpoint(void);
-
#define mask_irq(irq_nr) (*R_VECT_MASK_CLR = 1 << (irq_nr));
#define unmask_irq(irq_nr) (*R_VECT_MASK_SET = 1 << (irq_nr));
*! Jun 17 1999 Hendrik Ruijter Added gdb 4.18 support. 'X', 'qC' and 'qL'.
*! Jul 21 1999 Bjorn Wesen eLinux port
*!
-*! $Log: kgdb.c,v $
-*! Revision 1.6 2005/01/14 10:12:17 starvik
-*! KGDB on separate port.
-*! Console fixes from 2.4.
-*!
-*! Revision 1.5 2004/10/07 13:59:08 starvik
-*! Corrected call to set_int_vector
-*!
-*! Revision 1.4 2003/04/09 05:20:44 starvik
-*! Merge of Linux 2.5.67
-*!
-*! Revision 1.3 2003/01/21 19:11:08 starvik
-*! Modified include path for new dir layout
-*!
-*! Revision 1.2 2002/11/19 14:35:24 starvik
-*! Changes from linux 2.4
-*! Changed struct initializer syntax to the currently preferred notation
-*!
-*! Revision 1.1 2001/12/17 13:59:27 bjornw
-*! Initial revision
-*!
-*! Revision 1.6 2001/10/09 13:10:03 matsfg
-*! Added $ on registers and removed some underscores
-*!
-*! Revision 1.5 2001/04/17 13:58:39 orjanf
-*! * Renamed CONFIG_KGDB to CONFIG_ETRAX_KGDB.
-*!
-*! Revision 1.4 2001/02/23 13:45:19 bjornw
-*! config.h check
-*!
-*! Revision 1.3 2001/01/31 18:08:23 orjanf
-*! Removed kgdb_handle_breakpoint from being the break 8 handler.
-*!
-*! Revision 1.2 2001/01/12 14:22:25 orjanf
-*! Updated kernel debugging support to work with ETRAX 100LX.
-*!
-*! Revision 1.1 2000/07/10 16:25:21 bjornw
-*! Initial revision
-*!
-*! Revision 1.1.1.1 1999/12/03 14:57:31 bjornw
-*! * Initial version of arch/cris, the latest CRIS architecture with an MMU.
-*! Mostly copied from arch/etrax100 with appropriate renames of files.
-*! The mm/ subdir is copied from arch/i386.
-*! This does not compile yet at all.
-*!
-*!
-*! Revision 1.4 1999/07/22 17:25:25 bjornw
-*! Dont wait for + in putpacket if we havent hit the initial breakpoint yet. Added a kgdb_init function which sets up the break and irq vectors.
-*!
-*! Revision 1.3 1999/07/21 19:51:18 bjornw
-*! Check if the interrupting char is a ctrl-C, ignore otherwise.
-*!
-*! Revision 1.2 1999/07/21 18:09:39 bjornw
-*! Ported to eLinux architecture, and added some kgdb documentation.
-*!
-*!
*!---------------------------------------------------------------------------
*!
-*! $Id: kgdb.c,v 1.6 2005/01/14 10:12:17 starvik Exp $
-*!
*! (C) Copyright 1999, Axis Communications AB, LUND, SWEDEN
*!
*!**************************************************************************/
-/* $Id: process.c,v 1.12 2004/12/27 11:18:32 starvik Exp $
- *
+/*
* linux/arch/cris/kernel/process.c
*
* Copyright (C) 1995 Linus Torvalds
ptrace_disable(struct task_struct *child)
{
/* Todo - pending singlesteps? */
+ clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
}
/*
-/* $Id: shadows.c,v 1.2 2004/12/13 12:21:51 starvik Exp $
- *
+/*
* Various shadow registers. Defines for these are in include/asm-etrax100/io.h
*/
-/* $Id: traps.c,v 1.4 2005/04/24 18:47:55 starvik Exp $
+/*
+ * Helper functions for trap handlers
*
- * linux/arch/cris/arch-v10/traps.c
+ * Copyright (C) 2000-2007, Axis Communications AB.
*
- * Heler functions for trap handlers
- *
- * Copyright (C) 2000-2002 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- * Hans-Peter Nilsson
+ * Authors: Bjorn Wesen
+ * Hans-Peter Nilsson
*
*/
#include <asm/uaccess.h>
#include <asm/arch/sv_addr_ag.h>
-extern int raw_printk(const char *fmt, ...);
-
-void
-show_registers(struct pt_regs * regs)
+void
+show_registers(struct pt_regs *regs)
{
- /* We either use rdusp() - the USP register, which might not
- correspond to the current process for all cases we're called,
- or we use the current->thread.usp, which is not up to date for
- the current process. Experience shows we want the USP
- register. */
+ /*
+ * It's possible to use either the USP register or current->thread.usp.
+ * USP might not correspond to the current process for all cases this
+ * function is called, and current->thread.usp isn't up to date for the
+ * current process. Experience shows that using USP is the way to go.
+ */
unsigned long usp = rdusp();
- raw_printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n",
- regs->irp, regs->srp, regs->dccr, usp, regs->mof );
- raw_printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
+ printk("IRP: %08lx SRP: %08lx DCCR: %08lx USP: %08lx MOF: %08lx\n",
+ regs->irp, regs->srp, regs->dccr, usp, regs->mof);
+
+ printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
regs->r0, regs->r1, regs->r2, regs->r3);
- raw_printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
+
+ printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
regs->r4, regs->r5, regs->r6, regs->r7);
- raw_printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
+
+ printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
regs->r8, regs->r9, regs->r10, regs->r11);
- raw_printk("r12: %08lx r13: %08lx oR10: %08lx sp: %08lx\n",
- regs->r12, regs->r13, regs->orig_r10, regs);
- raw_printk("R_MMU_CAUSE: %08lx\n", (unsigned long)*R_MMU_CAUSE);
- raw_printk("Process %s (pid: %d, stackpage=%08lx)\n",
+
+ printk("r12: %08lx r13: %08lx oR10: %08lx sp: %08lx\n",
+ regs->r12, regs->r13, regs->orig_r10, (long unsigned)regs);
+
+ printk("R_MMU_CAUSE: %08lx\n", (unsigned long)*R_MMU_CAUSE);
+
+ printk("Process %s (pid: %d, stackpage=%08lx)\n",
current->comm, current->pid, (unsigned long)current);
/*
- * When in-kernel, we also print out the stack and code at the
- * time of the fault..
- */
- if (! user_mode(regs)) {
- int i;
+ * When in-kernel, we also print out the stack and code at the
+ * time of the fault..
+ */
+ if (!user_mode(regs)) {
+ int i;
- show_stack(NULL, (unsigned long*)usp);
+ show_stack(NULL, (unsigned long *)usp);
- /* Dump kernel stack if the previous dump wasn't one. */
+ /*
+ * If the previous stack-dump wasn't a kernel one, dump the
+ * kernel stack now.
+ */
if (usp != 0)
- show_stack (NULL, NULL);
-
- raw_printk("\nCode: ");
- if(regs->irp < PAGE_OFFSET)
- goto bad;
-
- /* Often enough the value at regs->irp does not point to
- the interesting instruction, which is most often the
- _previous_ instruction. So we dump at an offset large
- enough that instruction decoding should be in sync at
- the interesting point, but small enough to fit on a row
- (sort of). We point out the regs->irp location in a
- ksymoops-friendly way by wrapping the byte for that
- address in parentheses. */
- for(i = -12; i < 12; i++)
- {
- unsigned char c;
- if(__get_user(c, &((unsigned char*)regs->irp)[i])) {
-bad:
- raw_printk(" Bad IP value.");
- break;
- }
+ show_stack(NULL, NULL);
+
+ printk("\nCode: ");
+
+ if (regs->irp < PAGE_OFFSET)
+ goto bad_value;
+
+ /*
+ * Quite often the value at regs->irp doesn't point to the
+ * interesting instruction, which often is the previous
+ * instruction. So dump at an offset large enough that the
+ * instruction decoding should be in sync at the interesting
+ * point, but small enough to fit on a row. The regs->irp
+ * location is pointed out in a ksymoops-friendly way by
+ * wrapping the byte for that address in parenthesises.
+ */
+ for (i = -12; i < 12; i++) {
+ unsigned char c;
+
+ if (__get_user(c, &((unsigned char *)regs->irp)[i])) {
+bad_value:
+ printk(" Bad IP value.");
+ break;
+ }
if (i == 0)
- raw_printk("(%02x) ", c);
+ printk("(%02x) ", c);
else
- raw_printk("%02x ", c);
- }
- raw_printk("\n");
- }
+ printk("%02x ", c);
+ }
+ printk("\n");
+ }
}
-/* Called from entry.S when the watchdog has bitten
- * We print out something resembling an oops dump, and if
- * we have the nice doggy development flag set, we halt here
- * instead of rebooting.
- */
-
-extern void reset_watchdog(void);
-extern void stop_watchdog(void);
-
-
void
-watchdog_bite_hook(struct pt_regs *regs)
+arch_enable_nmi(void)
{
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- local_irq_disable();
- stop_watchdog();
- show_registers(regs);
- while(1) /* nothing */;
-#else
- show_registers(regs);
-#endif
+ asm volatile ("setf m");
}
-/* This is normally the 'Oops' routine */
-void
-die_if_kernel(const char * str, struct pt_regs * regs, long err)
+extern void (*nmi_handler)(struct pt_regs *);
+void handle_nmi(struct pt_regs *regs)
{
- if(user_mode(regs))
- return;
-
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- /* This printout might take too long and trigger the
- * watchdog normally. If we're in the nice doggy
- * development mode, stop the watchdog during printout.
- */
- stop_watchdog();
-#endif
-
- raw_printk("%s: %04lx\n", str, err & 0xffff);
-
- show_registers(regs);
-
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- reset_watchdog();
-#endif
- do_exit(SIGSEGV);
+ if (nmi_handler)
+ nmi_handler(regs);
+
+ /* Wait until nmi is no longer active. (We enable NMI immediately after
+ returning from this function, and we don't want it happening while
+ exiting from the NMI interrupt handler.) */
+ while (*R_IRQ_MASK0_RD & IO_STATE(R_IRQ_MASK0_RD, nmi_pin, active))
+ ;
}
-void arch_enable_nmi(void)
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+void
+handle_BUG(struct pt_regs *regs)
{
- asm volatile("setf m");
+ struct bug_frame f;
+ unsigned char c;
+ unsigned long irp = regs->irp;
+
+ if (__copy_from_user(&f, (const void __user *)(irp - 8), sizeof f))
+ return;
+ if (f.prefix != BUG_PREFIX || f.magic != BUG_MAGIC)
+ return;
+ if (__get_user(c, f.filename))
+ f.filename = "<bad filename>";
+
+ printk("kernel BUG at %s:%d!\n", f.filename, f.line);
}
+#endif
-/* $Id: checksum.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
+/*
* A fast checksum routine using movem
* Copyright (c) 1998-2001 Axis Communications AB
*
ax
addq 0,$r12
- ax ; do it again, since we might have generated a carry
- addq 0,$r12
subq 10*4,$r11
bge _mloop
lsrq 16,$r13 ; r13 = checksum >> 16
and.d $r9,$r12 ; checksum = checksum & 0xffff
add.d $r13,$r12 ; checksum += r13
- move.d $r12,$r13 ; do the same again, maybe we got a carry last add
- lsrq 16,$r13
- and.d $r9,$r12
- add.d $r13,$r12
_no_fold:
cmpq 2,$r11
-/* $Id: checksumcopy.S,v 1.1 2001/12/17 13:59:27 bjornw Exp $
+/*
* A fast checksum+copy routine using movem
* Copyright (c) 1998, 2001 Axis Communications AB
*
ax
addq 0,$r13
- ax ; do it again, since we might have generated a carry
- addq 0,$r13
subq 10*4,$r12
bge _mloop
lsrq 16,$r9 ; r0 = checksum >> 16
and.d 0xffff,$r13 ; checksum = checksum & 0xffff
add.d $r9,$r13 ; checksum += r0
- move.d $r13,$r9 ; do the same again, maybe we got a carry last add
- lsrq 16,$r9
- and.d 0xffff,$r13
- add.d $r9,$r13
_no_fold:
cmpq 2,$r12
-/* $Id: dram_init.S,v 1.4 2003/09/22 09:21:59 starvik Exp $
- *
+/*
* DRAM/SDRAM initialization - alter with care
* This file is intended to be included from other assembler files
*
*
* Copyright (C) 2000, 2001 Axis Communications AB
*
- * Authors: Mikael Starvik (starvik@axis.com)
- *
- * $Log: dram_init.S,v $
- * Revision 1.4 2003/09/22 09:21:59 starvik
- * Decompresser is linked to 0x407xxxxx and sdram commands are at 0x000xxxxx
- * so we need to mask off 12 bits.
- *
- * Revision 1.3 2003/03/31 09:38:37 starvik
- * Corrected calculation of end of sdram init commands
- *
- * Revision 1.2 2002/11/19 13:33:29 starvik
- * Changes from Linux 2.4
- *
- * Revision 1.13 2002/10/30 07:42:28 starvik
- * Always read SDRAM command sequence from flash
- *
- * Revision 1.12 2002/08/09 11:37:37 orjanf
- * Added double initialization work-around for Samsung SDRAMs.
- *
- * Revision 1.11 2002/06/04 11:43:21 starvik
- * Check if mrs_data is specified in kernelconfig (necessary for MCM)
- *
- * Revision 1.10 2001/10/04 12:00:21 martinnn
- * Added missing underscores.
- *
- * Revision 1.9 2001/10/01 14:47:35 bjornw
- * Added register prefixes and removed underscores
- *
- * Revision 1.8 2001/05/15 07:12:45 hp
- * Copy warning from head.S about r8 and r9
- *
- * Revision 1.7 2001/04/18 12:05:39 bjornw
- * Fixed comments, and explicitly include config.h to be sure its there
- *
- * Revision 1.6 2001/04/10 06:20:16 starvik
- * Delay should be 200us, not 200ns
- *
- * Revision 1.5 2001/04/09 06:01:13 starvik
- * Added support for 100 MHz SDRAMs
- *
- * Revision 1.4 2001/03/26 14:24:01 bjornw
- * Namechange of some config options
- *
- * Revision 1.3 2001/03/23 08:29:41 starvik
- * Corrected calculation of mrs_data
- *
- * Revision 1.2 2001/02/08 15:20:00 starvik
- * Corrected SDRAM initialization
- * Should now be included as inline
- *
- * Revision 1.1 2001/01/29 13:08:02 starvik
- * Initial version
- * This file should be included from all assembler files that needs to
- * initialize DRAM/SDRAM.
+ * Authors: Mikael Starvik (starvik@axis.com)
*
*/
-/* $Id: old_checksum.c,v 1.3 2003/10/27 08:04:32 starvik Exp $
- *
+/*
* INET An implementation of the TCP/IP protocol suite for the LINUX
* operating system. INET is implemented using the BSD Socket
* interface as the means of communication with the user level.
* Low level bus fault handler
*
*
- * Copyright (C) 2000, 2001 Axis Communications AB
+ * Copyright (C) 2000-2007 Axis Communications AB
+ *
+ * Authors: Bjorn Wesen
*
- * Authors: Bjorn Wesen
- *
*/
#include <linux/mm.h>
#ifdef DEBUG
page_id = IO_EXTRACT(R_MMU_CAUSE, page_id, cause);
acc = IO_EXTRACT(R_MMU_CAUSE, acc_excp, cause);
- inv = IO_EXTRACT(R_MMU_CAUSE, inv_excp, cause);
+ inv = IO_EXTRACT(R_MMU_CAUSE, inv_excp, cause);
index = IO_EXTRACT(R_TLB_SELECT, index, select);
#endif
miss = IO_EXTRACT(R_MMU_CAUSE, miss_excp, cause);
local_irq_disable();
pmd = (pmd_t *)(pgd + pgd_index(address));
if (pmd_none(*pmd))
- return;
+ goto exit;
pte = *pte_offset_kernel(pmd, address);
if (!pte_present(pte))
- return;
+ goto exit;
*R_TLB_SELECT = select;
*R_TLB_HI = cause;
*R_TLB_LO = pte_val(pte);
+exit:
local_irq_restore(flags);
}
* Low level TLB handling
*
*
- * Copyright (C) 2000-2002 Axis Communications AB
- *
+ * Copyright (C) 2000-2007 Axis Communications AB
+ *
* Authors: Bjorn Wesen (bjornw@axis.com)
*
*/
unsigned long flags;
/* the vpn of i & 0xf is so we dont write similar TLB entries
- * in the same 4-way entry group. details..
+ * in the same 4-way entry group. details...
*/
local_irq_save(flags);
*R_TLB_SELECT = ( IO_FIELD(R_TLB_SELECT, index, i) );
*R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
IO_FIELD(R_TLB_HI, vpn, i & 0xf ) );
-
+
*R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
IO_STATE(R_TLB_LO, valid, no ) |
IO_STATE(R_TLB_LO, kernel,no ) |
if(page_id == NO_CONTEXT)
return;
-
+
/* mark the TLB entries that match the page_id as invalid.
* here we could also check the _PAGE_GLOBAL bit and NOT flush
- * global pages. is it worth the extra I/O ?
+ * global pages. is it worth the extra I/O ?
*/
local_irq_save(flags);
if (IO_EXTRACT(R_TLB_HI, page_id, *R_TLB_HI) == page_id) {
*R_TLB_HI = ( IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
IO_FIELD(R_TLB_HI, vpn, i & 0xf ) );
-
+
*R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
IO_STATE(R_TLB_LO, valid, no ) |
IO_STATE(R_TLB_LO, kernel,no ) |
/* invalidate a single page */
-void
-flush_tlb_page(struct vm_area_struct *vma,
- unsigned long addr)
+void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
{
struct mm_struct *mm = vma->vm_mm;
int page_id = mm->context.page_id;
addr &= PAGE_MASK; /* perhaps not necessary */
/* invalidate those TLB entries that match both the mm context
- * and the virtual address requested
+ * and the virtual address requested
*/
local_irq_save(flags);
(tlb_hi & PAGE_MASK) == addr) {
*R_TLB_HI = IO_FIELD(R_TLB_HI, page_id, INVALID_PAGEID ) |
addr; /* same addr as before works. */
-
+
*R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) |
IO_STATE(R_TLB_LO, valid, no ) |
IO_STATE(R_TLB_LO, kernel,no ) |
{
int i;
unsigned long flags;
-
+
printk("TLB dump. LO is: pfn | reserved | global | valid | kernel | we |\n");
local_save_flags(flags);
/* called in schedule() just before actually doing the switch_to */
-void
-switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
+void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+ struct task_struct *tsk)
{
- /* make sure we have a context */
+ if (prev != next) {
+ /* make sure we have a context */
+ get_mmu_context(next);
- get_mmu_context(next);
+ /* remember the pgd for the fault handlers
+ * this is similar to the pgd register in some other CPU's.
+ * we need our own copy of it because current and active_mm
+ * might be invalid at points where we still need to derefer
+ * the pgd.
+ */
- /* remember the pgd for the fault handlers
- * this is similar to the pgd register in some other CPU's.
- * we need our own copy of it because current and active_mm
- * might be invalid at points where we still need to derefer
- * the pgd.
- */
+ per_cpu(current_pgd, smp_processor_id()) = next->pgd;
- per_cpu(current_pgd, smp_processor_id()) = next->pgd;
+ /* switch context in the MMU */
- /* switch context in the MMU */
-
- D(printk("switching mmu_context to %d (%p)\n", next->context, next));
+ D(printk(KERN_DEBUG "switching mmu_context to %d (%p)\n",
+ next->context, next));
- *R_MMU_CONTEXT = IO_FIELD(R_MMU_CONTEXT, page_id, next->context.page_id);
+ *R_MMU_CONTEXT = IO_FIELD(R_MMU_CONTEXT,
+ page_id, next->context.page_id);
+ }
}
if ETRAX_ARCH_V32
+source arch/cris/arch-v32/mach-fs/Kconfig
+source arch/cris/arch-v32/mach-a3/Kconfig
+
+source drivers/cpufreq/Kconfig
+
config ETRAX_DRAM_VIRTUAL_BASE
hex
depends on ETRAX_ARCH_V32
default "c0000000"
-config ETRAX_LED1G
- string "First green LED bit"
+choice
+ prompt "Nbr of Ethernet LED groups"
depends on ETRAX_ARCH_V32
+ default ETRAX_NBR_LED_GRP_ONE
+ help
+ Select how many Ethernet LED groups that can be used. Usually one per Ethernet
+ interface is a good choice.
+
+config ETRAX_NBR_LED_GRP_ZERO
+ bool "Use zero LED groups"
+ help
+ Select this if you do not want any Ethernet LEDs.
+
+config ETRAX_NBR_LED_GRP_ONE
+ bool "Use one LED group"
+ help
+ Select this if you want one Ethernet LED group. This LED group
+ can be used for one or more Ethernet interfaces. However, it is
+ recomended that each Ethernet interface use a dedicated LED group.
+
+config ETRAX_NBR_LED_GRP_TWO
+ bool "Use two LED groups"
+ help
+ Select this if you want two Ethernet LED groups. This is the
+ best choice if you have more than one Ethernet interface and
+ would like to have separate LEDs for the interfaces.
+
+endchoice
+
+config ETRAX_LED_G_NET0
+ string "Ethernet LED group 0 green LED bit"
+ depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
default "PA3"
help
- Bit to use for the first green LED (network LED).
- Most Axis products use bit A3 here.
+ Bit to use for the green LED in Ethernet LED group 0.
-config ETRAX_LED1R
- string "First red LED bit"
- depends on ETRAX_ARCH_V32
+config ETRAX_LED_R_NET0
+ string "Ethernet LED group 0 red LED bit"
+ depends on ETRAX_ARCH_V32 && (ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO)
default "PA4"
help
- Bit to use for the first red LED (network LED).
- Most Axis products use bit A4 here.
+ Bit to use for the red LED in Ethernet LED group 0.
-config ETRAX_LED2G
+config ETRAX_LED_G_NET1
+ string "Ethernet group 1 green LED bit"
+ depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
+ default ""
+ help
+ Bit to use for the green LED in Ethernet LED group 1.
+
+config ETRAX_LED_R_NET1
+ string "Ethernet group 1 red LED bit"
+ depends on ETRAX_ARCH_V32 && ETRAX_NBR_LED_GRP_TWO
+ default ""
+ help
+ Bit to use for the red LED in Ethernet LED group 1.
+
+config ETRAX_V32_LED2G
string "Second green LED bit"
depends on ETRAX_ARCH_V32
default "PA5"
Bit to use for the first green LED (status LED).
Most Axis products use bit A5 here.
-config ETRAX_LED2R
+config ETRAX_V32_LED2R
string "Second red LED bit"
depends on ETRAX_ARCH_V32
default "PA6"
Bit to use for the first red LED (network LED).
Most Axis products use bit A6 here.
-config ETRAX_LED3G
+config ETRAX_V32_LED3G
string "Third green LED bit"
depends on ETRAX_ARCH_V32
default "PA7"
Bit to use for the first green LED (drive/power LED).
Most Axis products use bit A7 here.
-config ETRAX_LED3R
+config ETRAX_V32_LED3R
string "Third red LED bit"
depends on ETRAX_ARCH_V32
default "PA7"
Bit to use for the first red LED (drive/power LED).
Most Axis products use bit A7 here.
-choice
- prompt "Product debug-port"
- depends on ETRAX_ARCH_V32
- default ETRAX_DEBUG_PORT0
-
-config ETRAX_DEBUG_PORT0
- bool "Serial-0"
- help
- Choose a serial port for the ETRAX debug console. Default to
- port 0.
-
-config ETRAX_DEBUG_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for the console.
-
-config ETRAX_DEBUG_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for the console.
-
-config ETRAX_DEBUG_PORT3
- bool "Serial-3"
- help
- Use serial port 3 for the console.
-
-config ETRAX_DEBUG_PORT_NULL
- bool "disabled"
- help
- Disable serial-port debugging.
-
-endchoice
-
choice
prompt "Kernel GDB port"
depends on ETRAX_KGDB
not be enabled under Drivers for built-in interfaces (as it has its
own initialization code) and should not be the same as the debug port.
-config ETRAX_KGDB_PORT0
- bool "Serial-0"
- help
- Use serial port 0 for kernel debugging.
-
-config ETRAX_KGDB_PORT1
- bool "Serial-1"
- help
- Use serial port 1 for kernel debugging.
-
-config ETRAX_KGDB_PORT2
- bool "Serial-2"
- help
- Use serial port 2 for kernel debugging.
-
-config ETRAX_KGDB_PORT3
- bool "Serial-3"
+config ETRAX_KGDB_PORT4
+ bool "Serial-4"
+ depends on ETRAX_SERIAL_PORTS = 5
help
- Use serial port 3 for kernel debugging.
+ Use serial port 4 for kernel debugging.
endchoice
#
# arch/cris/arch-v32/boot/Makefile
#
-target = $(target_boot_dir)
-src = $(src_boot_dir)
-zImage: compressed/vmlinuz
+OBJCOPY = objcopy-cris
+OBJCOPYFLAGS = -O binary -R .note -R .comment
-compressed/vmlinuz: $(objtree)/vmlinux
- @$(MAKE) -f $(src)/compressed/Makefile $(objtree)/vmlinuz
+subdir- := compressed rescue
+targets := Image
-clean:
- rm -f zImage tools/build compressed/vmlinux.out
- @$(MAKE) -f $(src)/compressed/Makefile clean
+$(obj)/Image: vmlinux FORCE
+ $(call if_changed,objcopy)
+ @echo ' Kernel: $@ is ready'
+
+$(obj)/compressed/vmlinux: $(obj)/Image FORCE
+ $(Q)$(MAKE) $(build)=$(obj)/compressed $@
+ $(Q)$(MAKE) $(build)=$(obj)/rescue $(obj)/rescue/rescue.bin
+
+$(obj)/zImage: $(obj)/compressed/vmlinux
+ @cp $< $@
+ @echo ' Kernel: $@ is ready'
#
-# lx25/arch/cris/arch-v32/boot/compressed/Makefile
+# arch/cris/arch-v32/boot/compressed/Makefile
#
-# create a compressed vmlinux image from the original vmlinux files and romfs
-#
-
-target = $(target_compressed_dir)
-src = $(src_compressed_dir)
CC = gcc-cris -mlinux -march=v32 $(LINUXINCLUDE)
-CFLAGS = -O2
+asflags-y += -I $(srctree)/include/asm/mach/ -I $(srctree)/include/asm/arch
+ccflags-y += -O2 -I $(srctree)/include/asm/mach/ -I $(srctree)/include/asm/arch
LD = gcc-cris -mlinux -march=v32 -nostdlib
+ldflags-y += -T $(obj)/decompress.ld
+obj-y = head.o misc.o
+OBJECTS = $(obj)/head.o $(obj)/misc.o
OBJCOPY = objcopy-cris
OBJCOPYFLAGS = -O binary --remove-section=.bss
-OBJECTS = $(target)/head.o $(target)/misc.o
-
-# files to compress
-SYSTEM = $(objtree)/vmlinux.bin
-
-all: vmlinuz
-
-$(target)/decompress.bin: $(OBJECTS)
- $(LD) -T $(src)/decompress.ld -o $(target)/decompress.o $(OBJECTS)
- $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/decompress.o $(target)/decompress.bin
-$(objtree)/vmlinuz: $(target) piggy.img $(target)/decompress.bin
- cat $(target)/decompress.bin piggy.img > $(objtree)/vmlinuz
- rm -f piggy.img
- cp $(objtree)/vmlinuz $(src)
+quiet_cmd_image = BUILD $@
+cmd_image = cat $(obj)/decompress.bin $(obj)/piggy.gz > $@
-$(target)/head.o: $(src)/head.S
- $(CC) -D__ASSEMBLY__ -c $< -o $@
+targets := vmlinux piggy.gz decompress.o decompress.bin
-# gzip the kernel image
+$(obj)/decompress.o: $(OBJECTS) FORCE
+ $(call if_changed,ld)
-piggy.img: $(SYSTEM)
- cat $(SYSTEM) | gzip -f -9 > piggy.img
+$(obj)/decompress.bin: $(obj)/decompress.o FORCE
+ $(call if_changed,objcopy)
-clean:
- rm -f piggy.img $(objtree)/vmlinuz vmlinuz.o decompress.o decompress.bin $(OBJECTS)
+$(obj)/vmlinux: $(obj)/piggy.gz $(obj)/decompress.bin FORCE
+ $(call if_changed,image)
+$(obj)/piggy.gz: $(obj)/../Image FORCE
+ $(call if_changed,gzip)
Creation of the self-extracting compressed kernel image (vmlinuz)
-----------------------------------------------------------------
-$Id: README,v 1.1 2003/08/21 09:37:03 johana Exp $
This can be slightly confusing because it's a process with many steps.
* Code that sets up the DRAM registers, calls the
* decompressor to unpack the piggybacked kernel, and jumps.
*
- * Copyright (C) 1999 - 2003, Axis Communications AB
+ * Copyright (C) 1999 - 2006, Axis Communications AB
*/
#define ASSEMBLER_MACROS_ONLY
-#include <asm/arch/hwregs/asm/reg_map_asm.h>
-#include <asm/arch/hwregs/asm/gio_defs_asm.h>
-#include <asm/arch/hwregs/asm/config_defs_asm.h>
+#include <hwregs/asm/reg_map_asm.h>
+#include <asm/arch/mach/startup.inc>
#define RAM_INIT_MAGIC 0x56902387
#define COMMAND_LINE_MAGIC 0x87109563
di
;; Start clocks for used blocks.
- move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
- move.d [$r1], $r0
- or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
- REG_STATE(config, rw_clk_ctrl, bif, yes) | \
- REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
- move.d $r0, [$r1]
-
- ;; If booting from NAND flash we first have to copy some
- ;; data from NAND flash to internal RAM to get the code
- ;; that initializes the SDRAM. Lets copy 20 KB. This
- ;; code executes at 0x38010000 if booting from NAND and
- ;; we are guaranted that at least 0x200 bytes are good so
- ;; lets start from there. The first 8192 bytes in the nand
- ;; flash is spliced with zeroes and is thus 16384 bytes.
- move.d 0x38010200, $r10
- move.d 0x14200, $r11 ; Start offset in NAND flash 0x10200 + 16384
- move.d 0x5000, $r12 ; Length of copy
-
- ;; Before this code the tools add a partitiontable so the PC
- ;; has an offset from the linked address.
-offset1:
- lapcq ., $r13 ; get PC
- add.d first_copy_complete-offset1, $r13
-
-#include "../../lib/nand_init.S"
-
-first_copy_complete:
- ;; Initialze the DRAM registers.
+ START_CLOCKS
+
+ ;; Initialize the DRAM registers.
cmp.d RAM_INIT_MAGIC, $r8 ; Already initialized?
beq dram_init_finished
nop
-#include "../../lib/dram_init.S"
+#include "../../mach/dram_init.S"
dram_init_finished:
- lapcq ., $r13 ; get PC
- add.d second_copy_complete-dram_init_finished, $r13
-
- move.d REG_ADDR(config, regi_config, r_bootsel), $r0
- move.d [$r0], $r0
- and.d REG_MASK(config, r_bootsel, boot_mode), $r0
- cmp.d REG_STATE(config, r_bootsel, boot_mode, nand), $r0
- bne second_copy_complete ; No NAND boot
- nop
-
- ;; Copy 2MB from NAND flash to SDRAM (at 2-4MB into the SDRAM)
- move.d 0x40204000, $r10
- move.d 0x8000, $r11
- move.d 0x200000, $r12
- ba copy_nand_to_ram
- nop
-second_copy_complete:
-
- ;; Initiate the PA port.
- move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
- move.d $r0, [$r1]
-
- move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
- move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
- move.d $r0, [$r1]
+ GIO_INIT
;; Setup the stack to a suitably high address.
;; We assume 8 MB is the minimum DRAM and put
;; the SP at the top for now.
move.d 0x40800000, $sp
- ;; Figure out where the compressed piggyback image is
- ;; in the flash (since we wont try to copy it to DRAM
- ;; before unpacking). It is at _edata, but in flash.
+ ;; Figure out where the compressed piggyback image is.
+ ;; It is either in [NOR] flash (we don't want to copy it
+ ;; to DRAM before unpacking), or copied to DRAM
+ ;; by the [NAND] flash boot loader.
+ ;; The piggyback image is at _edata, but relative to where the
+ ;; image is actually located in memory, not where it is linked
+ ;; (the decompressor is linked at 0x40700000+ and runs there).
;; Use (_edata - herami) as offset to the current PC.
- move.d REG_ADDR(config, regi_config, r_bootsel), $r0
- move.d [$r0], $r0
- and.d REG_MASK(config, r_bootsel, boot_mode), $r0
- cmp.d REG_STATE(config, r_bootsel, boot_mode, nand), $r0
- beq hereami2
- nop
hereami:
lapcq ., $r5 ; get PC
and.d 0x7fffffff, $r5 ; strip any non-cache bit
- move.d $r5, $r0 ; save for later - flash address of 'herami'
+ move.d $r5, $r0 ; source address of 'herami'
add.d _edata, $r5
sub.d hereami, $r5 ; r5 = flash address of '_edata'
move.d hereami, $r1 ; destination
- ba 2f
- nop
-hereami2:
- lapcq ., $r5 ; get PC
- and.d 0x00ffffff, $r5 ; strip any non-cache bit
- move.d $r5, $r6
- or.d 0x40200000, $r6
- move.d $r6, $r0 ; save for later - flash address of 'herami'
- add.d _edata, $r5
- sub.d hereami2, $r5 ; r5 = flash address of '_edata'
- add.d 0x40200000, $r5
- move.d hereami2, $r1 ; destination
-2:
+
;; Copy text+data to DRAM
move.d _edata, $r2 ; end destination
-1: move.w [$r0+], $r3
- move.w $r3, [$r1+]
- cmp.d $r2, $r1
+1: move.w [$r0+], $r3 ; from herami+ source
+ move.w $r3, [$r1+] ; to hereami+ destination (linked address)
+ cmp.d $r2, $r1 ; finish when destination == _edata
bcs 1b
nop
-
move.d input_data, $r0 ; for the decompressor
move.d $r5, [$r0] ; for the decompressor
nop
;; Save command line magic and address.
- move.d _cmd_line_magic, $r12
- move.d $r10, [$r12]
- move.d _cmd_line_addr, $r12
- move.d $r11, [$r12]
+ move.d _cmd_line_magic, $r0
+ move.d $r10, [$r0]
+ move.d _cmd_line_addr, $r0
+ move.d $r11, [$r0]
+
+ ;; Save boot source indicator
+ move.d _boot_source, $r0
+ move.d $r12, [$r0]
;; Do the decompression and save compressed size in _inptr
jsr decompress_kernel
nop
+ ;; Restore boot source indicator
+ move.d _boot_source, $r12
+ move.d [$r12], $r12
+
;; Restore command line magic and address.
move.d _cmd_line_magic, $r10
move.d [$r10], $r10
move.d [$r0], $r9 ; flash address of compressed kernel
move.d inptr, $r0
add.d [$r0], $r9 ; size of compressed kernel
- cmp.d 0x40200000, $r9
- blo enter_kernel
- nop
- sub.d 0x40200000, $r9
- add.d 0x4000, $r9
+ cmp.d 0x40000000, $r9 ; image in DRAM ?
+ blo enter_kernel ; no, must be [NOR] flash, jump
+ nop ; delay slot
+ and.d 0x001fffff, $r9 ; assume compressed kernel was < 2M
enter_kernel:
;; Enter the decompressed kernel
.dword 0
_cmd_line_addr:
.dword 0
-is_nand_boot:
- .dword 0
+_boot_source:
+ .dword 0
-#include "../../lib/hw_settings.S"
+#include "../../mach/hw_settings.S"
/*
* misc.c
*
- * $Id: misc.c,v 1.8 2005/04/24 18:34:29 starvik Exp $
- *
* This is a collection of several routines from gzip-1.0.3
* adapted for Linux.
*
#include <linux/types.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/ser_defs.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/ser_defs.h>
+#include <hwregs/pinmux_defs.h>
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+#include <hwregs/clkgen_defs.h>
+#endif
/*
* gzip declarations
# define Tracecv(c,x)
#endif
-static int fill_inbuf(void);
static void flush_window(void);
static void error(char *m);
static void gzip_mark(void **);
char *ss = (char*)s;
for (i=0;i<n;i++) ss[i] = c;
+
+ return s;
}
void*
char *d = (char *)__dest, *s = (char *)__src;
for (i=0;i<__n;i++) d[i] = s[i];
+
+ return __dest;
}
/* ===========================================================================
static void
error(char *x)
{
- puts("\n\n");
+ puts("\r\n\n");
puts(x);
- puts("\n\n -- System halted\n");
+ puts("\r\n\n -- System halted\n");
while(1); /* Halt */
}
void
-setup_normal_output_buffer()
+setup_normal_output_buffer(void)
{
output_data = (char *)KERNEL_LOAD_ADR;
}
rec_baud = REG_RD(ser, regi_ser, rw_rec_baud_div);
tr_ctrl.stop_bits = 1; /* 2 stop bits. */
+ tr_ctrl.en = 1; /* enable transmitter */
+ rec_ctrl.en = 1; /* enabler receiver */
/*
- * The baudrate setup is a bit fishy, but in the end the transceiver is
- * set to 4800 and the receiver to 115200. The magic value is
- * 29.493 MHz.
+ * The baudrate setup used to be a bit fishy, but now transmitter and
+ * receiver are both set to the intended baud rate, 115200.
+ * The magic value is 29.493 MHz.
*/
tr_ctrl.base_freq = regk_ser_f29_493;
rec_ctrl.base_freq = regk_ser_f29_493;
- tr_baud.div = (29493000 / 8) / 4800;
+ tr_baud.div = (29493000 / 8) / 115200;
rec_baud.div = (29493000 / 8) / 115200;
REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl);
}
void
-decompress_kernel()
+decompress_kernel(void)
{
char revision;
- /* input_data is set in head.S */
- inbuf = input_data;
+#if defined(CONFIG_ETRAX_DEBUG_PORT1) || \
+ defined(CONFIG_ETRAX_DEBUG_PORT2) || \
+ defined(CONFIG_ETRAX_DEBUG_PORT3)
+ reg_pinmux_rw_hwprot hwprot;
+
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+ reg_clkgen_rw_clk_ctrl clk_ctrl;
+
+ /* Enable corresponding clock region when serial 1..3 selected */
+
+ clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
+ clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
+ REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
+#endif
+
+ /* pinmux setup for ports 1..3 */
+ hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
+#endif
#ifdef CONFIG_ETRAX_DEBUG_PORT0
serial_setup(regi_ser0);
#endif
#ifdef CONFIG_ETRAX_DEBUG_PORT1
+ hwprot.ser1 = regk_pinmux_yes;
serial_setup(regi_ser1);
#endif
#ifdef CONFIG_ETRAX_DEBUG_PORT2
+ hwprot.ser2 = regk_pinmux_yes;
serial_setup(regi_ser2);
#endif
#ifdef CONFIG_ETRAX_DEBUG_PORT3
+ hwprot.ser3 = regk_pinmux_yes;
serial_setup(regi_ser3);
#endif
+#if defined(CONFIG_ETRAX_DEBUG_PORT1) || \
+ defined(CONFIG_ETRAX_DEBUG_PORT2) || \
+ defined(CONFIG_ETRAX_DEBUG_PORT3)
+ REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
+#endif
+
+ /* input_data is set in head.S */
+ inbuf = input_data;
setup_normal_output_buffer();
__asm__ volatile ("move $vr,%0" : "=rm" (revision));
if (revision < 32)
{
- puts("You need an ETRAX FS to run Linux 2.6/crisv32.\n");
+ puts("You need an ETRAX FS to run Linux 2.6/crisv32.\r\n");
while(1);
}
- puts("Uncompressing Linux...\n");
+ puts("Uncompressing Linux...\r\n");
gunzip();
- puts("Done. Now booting the kernel.\n");
+ puts("Done. Now booting the kernel.\r\n");
}
#
-# Makefile for rescue code
+# Makefile for rescue (bootstrap) code
#
-target = $(target_rescue_dir)
-src = $(src_rescue_dir)
CC = gcc-cris -mlinux -march=v32 $(LINUXINCLUDE)
-CFLAGS = -O2
+ccflags-y += -O2 -I $(srctree)/include/asm/arch/mach/ \
+ -I $(srctree)/include/asm/arch
+asflags-y += -I $(srctree)/include/asm/arch/mach/ -I $(srctree)/include/asm/arch
LD = gcc-cris -mlinux -march=v32 -nostdlib
+ldflags-y += -T $(obj)/rescue.ld
+LDPOSTFLAGS = -lgcc
OBJCOPY = objcopy-cris
OBJCOPYFLAGS = -O binary --remove-section=.bss
+obj-$(CONFIG_ETRAX_AXISFLASHMAP) = head.o
+OBJECT := $(obj)/head.o
-all: $(target)/rescue.bin
+targets := rescue.o rescue.bin
-rescue: rescue.bin
- # do nothing
+quiet_cmd_ldlibgcc = LD $@
+cmd_ldlibgcc = $(LD) $(LDFLAGS) $(filter-out FORCE,$^) $(LDPOSTFLAGS) -o $@
-$(target)/rescue.bin: $(target) $(target)/head.o
- $(LD) -T $(src)/rescue.ld -o $(target)/rescue.o $(target)/head.o
- $(OBJCOPY) $(OBJCOPYFLAGS) $(target)/rescue.o $(target)/rescue.bin
- cp -p $(target)/rescue.bin $(objtree)
+$(obj)/rescue.o: $(OBJECTS) FORCE
+ $(call if_changed,ldlibgcc)
-$(target):
- mkdir -p $(target)
-
-$(target)/head.o: $(src)/head.S
- $(CC) -D__ASSEMBLY__ -c $< -o $*.o
-
-clean:
- rm -f $(target)/*.o $(target)/*.bin
-
-fastdep:
-
-modules:
-
-modules-install:
+$(obj)/rescue.bin: $(obj)/rescue.o FORCE
+ $(call if_changed,objcopy)
+ cp -p $(obj)/rescue.bin $(objtree)
-/* $Id: head.S,v 1.4 2004/11/01 16:10:28 starvik Exp $
+/*
+ * Just get started by jumping to CONFIG_ETRAX_PTABLE_SECTOR to start
+ * kernel decompressor.
+ *
+ * In practice, this only works for NOR flash (or some convoluted RAM boot)
+ * and hence is not really useful for Artpec-3, so it's Etrax FS / NOR only.
*
- * This used to be the rescue code but now that is handled by the
- * RedBoot based RFL instead. Nothing to see here, move along.
*/
-#include <asm/arch/hwregs/reg_map_asm.h>
-#include <asm/arch/hwregs/config_defs_asm.h>
+#include <mach/startup.inc>
- .text
+#ifdef CONFIG_ETRAX_AXISFLASHMAP
- ;; Start clocks for used blocks.
- move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
- move.d [$r1], $r0
- or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
- REG_STATE(config, rw_clk_ctrl, bif, yes) | \
- REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
- move.d $r0, [$r1]
+;; Code
- ;; Copy 68KB NAND flash to Internal RAM (if NAND boot)
- move.d 0x38004000, $r10
- move.d 0x8000, $r11
- move.d 0x11000, $r12
- move.d copy_complete, $r13
- and.d 0x000fffff, $r13
- or.d 0x38000000, $r13
+ .text
+start:
-#include "../../lib/nand_init.S"
+ ;; Start clocks for used blocks.
+ START_CLOCKS
- ;; No NAND found
move.d CONFIG_ETRAX_PTABLE_SECTOR, $r10
- jump $r10 ; Jump to decompresser
+ jump $r10 ; Jump to decompressor
nop
-copy_complete:
- move.d 0x38000000 + CONFIG_ETRAX_PTABLE_SECTOR, $r10
- jump $r10 ; Jump to decompresser
- nop
+#endif
+/*#OUTPUT_FORMAT(elf32-us-cris) */
+OUTPUT_ARCH (crisv32)
+/* Now that NAND support has been stripped, this file could be simplified,
+ * but it doesn't do any harm on the other hand so why bother. */
+
MEMORY
{
- flash : ORIGIN = 0x00000000,
- LENGTH = 0x00100000
+ bootblk : ORIGIN = 0x38000000,
+ LENGTH = 0x00004000
+ intmem : ORIGIN = 0x38004000,
+ LENGTH = 0x00005000
}
SECTIONS
{
.text :
{
- stext = . ;
+ _stext = . ;
*(.text)
- etext = . ;
- } > flash
+ *(.init.text)
+ *(.rodata)
+ *(.rodata.*)
+ _etext = . ;
+ } > bootblk
.data :
{
*(.data)
- edata = . ;
- } > flash
+ _edata = . ;
+ } > bootblk
+ .bss :
+ {
+ _bss = . ;
+ *(.bss)
+ _end = ALIGN( 0x10 ) ;
+ } > intmem
+
+ /* Get rid of stuff from EXPORT_SYMBOL(foo). */
+ /DISCARD/ :
+ {
+ *(__ksymtab_strings)
+ *(__ksymtab)
+ }
}
bool "Ethernet support"
depends on ETRAX_ARCH_V32
select NET_ETHERNET
+ select MII
help
This option enables the ETRAX FS built-in 10/100Mbit Ethernet
controller.
-config ETRAX_ETHERNET_HW_CSUM
- bool "Hardware accelerated ethernet checksum and scatter/gather"
+config ETRAX_NO_PHY
+ bool "PHY not present"
depends on ETRAX_ETHERNET
- depends on ETRAX_STREAMCOPROC
- default y
+ default N
help
- Hardware acceleration of checksumming and scatter/gather
+ This option disables all MDIO communication with an ethernet
+ transceiver connected to the MII interface. This option shall
+ typically be enabled if the MII interface is connected to a
+ switch. This option should normally be disabled. If enabled,
+ speed and duplex will be locked to 100 Mbit and full duplex.
config ETRAX_ETHERNET_IFACE0
depends on ETRAX_ETHERNET
bool "Enable network interface 0"
config ETRAX_ETHERNET_IFACE1
- depends on ETRAX_ETHERNET
+ depends on (ETRAX_ETHERNET && ETRAXFS)
bool "Enable network interface 1 (uses DMA6 and DMA7)"
+config ETRAX_ETHERNET_GBIT
+ depends on (ETRAX_ETHERNET && CRIS_MACH_ARTPEC3)
+ bool "Enable gigabit Ethernet support"
+
choice
- prompt "Network LED behavior"
- depends on ETRAX_ETHERNET
- default ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
+ prompt "Eth0 led group"
+ depends on ETRAX_ETHERNET_IFACE0
+ default ETRAX_ETH0_USE_LEDGRP0
-config ETRAX_NETWORK_LED_ON_WHEN_LINK
- bool "LED_on_when_link"
+config ETRAX_ETH0_USE_LEDGRP0
+ bool "Use LED grp 0"
+ depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO
help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
+ Use LED grp 0 for eth0
- Selecting LED_on_when_activity will light the LED only when
- there is activity.
-
- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
+config ETRAX_ETH0_USE_LEDGRP1
+ bool "Use LED grp 1"
+ depends on ETRAX_NBR_LED_GRP_TWO
+ help
+ Use LED grp 1 for eth0
-config ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY
- bool "LED_on_when_activity"
+config ETRAX_ETH0_USE_LEDGRPNULL
+ bool "Use no LEDs for eth0"
help
- Selecting LED_on_when_link will light the LED when there is a
- connection and will flash off when there is activity.
+ Use no LEDs for eth0
+endchoice
- Selecting LED_on_when_activity will light the LED only when
- there is activity.
+choice
+ prompt "Eth1 led group"
+ depends on ETRAX_ETHERNET_IFACE1
+ default ETRAX_ETH1_USE_LEDGRP1
+
+config ETRAX_ETH1_USE_LEDGRP0
+ bool "Use LED grp 0"
+ depends on ETRAX_NBR_LED_GRP_ONE || ETRAX_NBR_LED_GRP_TWO
+ help
+ Use LED grp 0 for eth1
- This setting will also affect the behaviour of other activity LEDs
- e.g. Bluetooth.
+config ETRAX_ETH1_USE_LEDGRP1
+ bool "Use LED grp 1"
+ depends on ETRAX_NBR_LED_GRP_TWO
+ help
+ Use LED grp 1 for eth1
+config ETRAX_ETH1_USE_LEDGRPNULL
+ bool "Use no LEDs for eth1"
+ help
+ Use no LEDs for eth1
endchoice
config ETRAXFS_SERIAL
bool "Serial-port support"
depends on ETRAX_ARCH_V32
+ select SERIAL_CORE
+ select SERIAL_CORE_CONSOLE
help
Enables the ETRAX FS serial driver for ser0 (ttyS0)
You probably want this enabled.
+config ETRAX_RS485
+ bool "RS-485 support"
+ depends on ETRAXFS_SERIAL
+ help
+ Enables support for RS-485 serial communication.
+
+config ETRAX_RS485_DISABLE_RECEIVER
+ bool "Disable serial receiver"
+ depends on ETRAX_RS485
+ help
+ It is necessary to disable the serial receiver to avoid serial
+ loopback. Not all products are able to do this in software only.
+
config ETRAX_SERIAL_PORT0
bool "Serial port 0 enabled"
depends on ETRAXFS_SERIAL
ser0 can use dma4 or dma6 for output and dma5 or dma7 for input.
choice
- prompt "Ser0 DMA in channel "
+ prompt "Ser0 default port type "
depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_NO_DMA_IN
+ default ETRAX_SERIAL_PORT0_TYPE_232
help
- What DMA channel to use for ser0.
-
+ Type of serial port.
-config ETRAX_SERIAL_PORT0_NO_DMA_IN
- bool "Ser0 uses no DMA for input"
+config ETRAX_SERIAL_PORT0_TYPE_232
+ bool "Ser0 is a RS-232 port"
help
- Do not use DMA for ser0 input.
+ Configure serial port 0 to be a RS-232 port.
-config ETRAX_SERIAL_PORT0_DMA7_IN
- bool "Ser0 uses DMA7 for input"
- depends on ETRAX_SERIAL_PORT0
- help
- Enables the DMA7 input channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser0 DMA out channel"
- depends on ETRAX_SERIAL_PORT0
- default ETRAX_SERIAL_PORT0_NO_DMA_OUT
-
-config ETRAX_SERIAL_PORT0_NO_DMA_OUT
- bool "Ser0 uses no DMA for output"
+config ETRAX_SERIAL_PORT0_TYPE_485HD
+ bool "Ser0 is a half duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Do not use DMA for ser0 output.
+ Configure serial port 0 to be a half duplex (two wires) RS-485 port.
-config ETRAX_SERIAL_PORT0_DMA6_OUT
- bool "Ser0 uses DMA6 for output"
- depends on ETRAX_SERIAL_PORT0
+config ETRAX_SERIAL_PORT0_TYPE_485FD
+ bool "Ser0 is a full duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Enables the DMA6 output channel for ser0 (ttyS0).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
+ Configure serial port 0 to be a full duplex (four wires) RS-485 port.
endchoice
config ETRAX_SER0_DTR_BIT
Enables the ETRAX FS serial driver for ser1 (ttyS1).
choice
- prompt "Ser1 DMA in channel "
+ prompt "Ser1 default port type"
depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_NO_DMA_IN
- help
- What DMA channel to use for ser1.
-
-
-config ETRAX_SERIAL_PORT1_NO_DMA_IN
- bool "Ser1 uses no DMA for input"
+ default ETRAX_SERIAL_PORT1_TYPE_232
help
- Do not use DMA for ser1 input.
+ Type of serial port.
-config ETRAX_SERIAL_PORT1_DMA5_IN
- bool "Ser1 uses DMA5 for input"
- depends on ETRAX_SERIAL_PORT1
+config ETRAX_SERIAL_PORT1_TYPE_232
+ bool "Ser1 is a RS-232 port"
help
- Enables the DMA5 input channel for ser1 (ttyS1).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want this on, unless you use the DMA channel for
- something else.
-
-endchoice
+ Configure serial port 1 to be a RS-232 port.
-choice
- prompt "Ser1 DMA out channel "
- depends on ETRAX_SERIAL_PORT1
- default ETRAX_SERIAL_PORT1_NO_DMA_OUT
- help
- What DMA channel to use for ser1.
-
-config ETRAX_SERIAL_PORT1_NO_DMA_OUT
- bool "Ser1 uses no DMA for output"
+config ETRAX_SERIAL_PORT1_TYPE_485HD
+ bool "Ser1 is a half duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Do not use DMA for ser1 output.
+ Configure serial port 1 to be a half duplex (two wires) RS-485 port.
-config ETRAX_SERIAL_PORT1_DMA4_OUT
- bool "Ser1 uses DMA4 for output"
- depends on ETRAX_SERIAL_PORT1
+config ETRAX_SERIAL_PORT1_TYPE_485FD
+ bool "Ser1 is a full duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Enables the DMA4 output channel for ser1 (ttyS1).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want this on, unless you use the DMA channel for
- something else.
-
+ Configure serial port 1 to be a full duplex (four wires) RS-485 port.
endchoice
config ETRAX_SER1_DTR_BIT
Enables the ETRAX FS serial driver for ser2 (ttyS2).
choice
- prompt "Ser2 DMA in channel "
+ prompt "Ser2 default port type"
depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_NO_DMA_IN
+ default ETRAX_SERIAL_PORT2_TYPE_232
help
- What DMA channel to use for ser2.
+ What DMA channel to use for ser2
-
-config ETRAX_SERIAL_PORT2_NO_DMA_IN
- bool "Ser2 uses no DMA for input"
+config ETRAX_SERIAL_PORT2_TYPE_232
+ bool "Ser2 is a RS-232 port"
help
- Do not use DMA for ser2 input.
+ Configure serial port 2 to be a RS-232 port.
-config ETRAX_SERIAL_PORT2_DMA3_IN
- bool "Ser2 uses DMA3 for input"
- depends on ETRAX_SERIAL_PORT2
- help
- Enables the DMA3 input channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
-endchoice
-
-choice
- prompt "Ser2 DMA out channel"
- depends on ETRAX_SERIAL_PORT2
- default ETRAX_SERIAL_PORT2_NO_DMA_OUT
-
-config ETRAX_SERIAL_PORT2_NO_DMA_OUT
- bool "Ser2 uses no DMA for output"
+config ETRAX_SERIAL_PORT2_TYPE_485HD
+ bool "Ser2 is a half duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Do not use DMA for ser2 output.
+ Configure serial port 2 to be a half duplex (two wires) RS-485 port.
-config ETRAX_SERIAL_PORT2_DMA2_OUT
- bool "Ser2 uses DMA2 for output"
- depends on ETRAX_SERIAL_PORT2
+config ETRAX_SERIAL_PORT2_TYPE_485FD
+ bool "Ser2 is a full duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Enables the DMA2 output channel for ser2 (ttyS2).
- If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
-
+ Configure serial port 2 to be a full duplex (four wires) RS-485 port.
endchoice
+
config ETRAX_SER2_DTR_BIT
string "Ser 2 DTR bit (empty = not used)"
depends on ETRAX_SERIAL_PORT2
Enables the ETRAX FS serial driver for ser3 (ttyS3).
choice
- prompt "Ser3 DMA in channel "
+ prompt "Ser3 default port type"
depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_NO_DMA_IN
+ default ETRAX_SERIAL_PORT3_TYPE_232
help
What DMA channel to use for ser3.
+config ETRAX_SERIAL_PORT3_TYPE_232
+ bool "Ser3 is a RS-232 port"
+ help
+ Configure serial port 3 to be a RS-232 port.
-config ETRAX_SERIAL_PORT3_NO_DMA_IN
- bool "Ser3 uses no DMA for input"
+config ETRAX_SERIAL_PORT3_TYPE_485HD
+ bool "Ser3 is a half duplex RS-485 port"
+ depends on ETRAX_RS485
help
- Do not use DMA for ser3 input.
+ Configure serial port 3 to be a half duplex (two wires) RS-485 port.
-config ETRAX_SERIAL_PORT3_DMA9_IN
- bool "Ser3 uses DMA9 for input"
+config ETRAX_SERIAL_PORT3_TYPE_485FD
+ bool "Ser3 is a full duplex RS-485 port"
+ depends on ETRAX_RS485
+ help
+ Configure serial port 3 to be a full duplex (four wires) RS-485 port.
+endchoice
+
+config ETRAX_SER3_DTR_BIT
+ string "Ser 3 DTR bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_SER3_RI_BIT
+ string "Ser 3 RI bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_SER3_DSR_BIT
+ string "Ser 3 DSR bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_SER3_CD_BIT
+ string "Ser 3 CD bit (empty = not used)"
depends on ETRAX_SERIAL_PORT3
+
+config ETRAX_SERIAL_PORT4
+ bool "Serial port 4 enabled"
+ depends on ETRAXFS_SERIAL && CRIS_MACH_ARTPEC3
help
- Enables the DMA9 input channel for ser3 (ttyS3).
- If you do not enable DMA, an interrupt for each character will be
- used when receiving data.
- Normally you want to use DMA, unless you use the DMA channel for
- something else.
+ Enables the ETRAX FS serial driver for ser4 (ttyS4).
+
+choice
+ prompt "Ser4 default port type"
+ depends on ETRAX_SERIAL_PORT4
+ default ETRAX_SERIAL_PORT4_TYPE_232
+ help
+ What DMA channel to use for ser4.
+config ETRAX_SERIAL_PORT4_TYPE_232
+ bool "Ser4 is a RS-232 port"
+ help
+ Configure serial port 4 to be a RS-232 port.
+
+config ETRAX_SERIAL_PORT4_TYPE_485HD
+ bool "Ser4 is a half duplex RS-485 port"
+ depends on ETRAX_RS485
+ help
+ Configure serial port 4 to be a half duplex (two wires) RS-485 port.
+
+config ETRAX_SERIAL_PORT4_TYPE_485FD
+ bool "Ser4 is a full duplex RS-485 port"
+ depends on ETRAX_RS485
+ help
+ Configure serial port 4 to be a full duplex (four wires) RS-485 port.
endchoice
choice
- prompt "Ser3 DMA out channel"
- depends on ETRAX_SERIAL_PORT3
- default ETRAX_SERIAL_PORT3_NO_DMA_OUT
+ prompt "Ser4 DMA in channel "
+ depends on ETRAX_SERIAL_PORT4
+ default ETRAX_SERIAL_PORT4_NO_DMA_IN
+ help
+ What DMA channel to use for ser4.
+
-config ETRAX_SERIAL_PORT3_NO_DMA_OUT
- bool "Ser3 uses no DMA for output"
+config ETRAX_SERIAL_PORT4_NO_DMA_IN
+ bool "Ser4 uses no DMA for input"
help
- Do not use DMA for ser3 output.
+ Do not use DMA for ser4 input.
-config ETRAX_SERIAL_PORT3_DMA8_OUT
- bool "Ser3 uses DMA8 for output"
- depends on ETRAX_SERIAL_PORT3
+config ETRAX_SERIAL_PORT4_DMA9_IN
+ bool "Ser4 uses DMA9 for input"
+ depends on ETRAX_SERIAL_PORT4
help
- Enables the DMA8 output channel for ser3 (ttyS3).
+ Enables the DMA9 input channel for ser4 (ttyS4).
If you do not enable DMA, an interrupt for each character will be
- used when transmitting data.
+ used when receiveing data.
Normally you want to use DMA, unless you use the DMA channel for
something else.
endchoice
-config ETRAX_SER3_DTR_BIT
- string "Ser 3 DTR bit (empty = not used)"
- depends on ETRAX_SERIAL_PORT3
+config ETRAX_SER4_DTR_BIT
+ string "Ser 4 DTR bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT4
-config ETRAX_SER3_RI_BIT
- string "Ser 3 RI bit (empty = not used)"
- depends on ETRAX_SERIAL_PORT3
+config ETRAX_SER4_RI_BIT
+ string "Ser 4 RI bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT4
-config ETRAX_SER3_DSR_BIT
- string "Ser 3 DSR bit (empty = not used)"
- depends on ETRAX_SERIAL_PORT3
+config ETRAX_SER4_DSR_BIT
+ string "Ser 4 DSR bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT4
config ETRAX_SER3_CD_BIT
- string "Ser 3 CD bit (empty = not used)"
- depends on ETRAX_SERIAL_PORT3
+ string "Ser 4 CD bit (empty = not used)"
+ depends on ETRAX_SERIAL_PORT4
config ETRAX_RS485
bool "RS-485 support"
- depends on ETRAX_SERIAL
+ depends on ETRAXFS_SERIAL
help
Enables support for RS-485 serial communication. For a primer on
RS-485, see <http://www.hw.cz/english/docs/rs485/rs485.html>.
help
It is necessary to disable the serial receiver to avoid serial
loopback. Not all products are able to do this in software only.
- Axis 2400/2401 must disable receiver.
-
-config ETRAX_AXISFLASHMAP
- bool "Axis flash-map support"
- depends on ETRAX_ARCH_V32
- select MTD
- select MTD_CFI
- select MTD_CFI_AMDSTD
- select MTD_CHAR
- select MTD_BLOCK
- select MTD_PARTITIONS
- select MTD_CONCAT
- select MTD_COMPLEX_MAPPINGS
- help
- This option enables MTD mapping of flash devices. Needed to use
- flash memories. If unsure, say Y.
config ETRAX_SYNCHRONOUS_SERIAL
bool "Synchronous serial-port support"
config ETRAX_SYNCHRONOUS_SERIAL_PORT1
bool "Synchronous serial port 1 enabled"
- depends on ETRAX_SYNCHRONOUS_SERIAL
+ depends on ETRAX_SYNCHRONOUS_SERIAL && ETRAXFS
help
Enabled synchronous serial port 1.
A synchronous serial port can run in manual or DMA mode.
Selecting this option will make it run in DMA mode.
+config ETRAX_AXISFLASHMAP
+ bool "Axis flash-map support"
+ depends on ETRAX_ARCH_V32
+ select MTD
+ select MTD_CFI
+ select MTD_CFI_AMDSTD
+ select MTD_JEDECPROBE
+ select MTD_CHAR
+ select MTD_BLOCK
+ select MTD_PARTITIONS
+ select MTD_CONCAT
+ select MTD_COMPLEX_MAPPINGS
+ help
+ This option enables MTD mapping of flash devices. Needed to use
+ flash memories. If unsure, say Y.
+
+config ETRAX_AXISFLASHMAP_MTD0WHOLE
+ bool "MTD0 is whole boot flash device"
+ depends on ETRAX_AXISFLASHMAP
+ default N
+ help
+ When this option is not set, mtd0 refers to the first partition
+ on the boot flash device. When set, mtd0 refers to the whole
+ device, with mtd1 referring to the first partition etc.
+
config ETRAX_PTABLE_SECTOR
int "Byte-offset of partition table sector"
depends on ETRAX_AXISFLASHMAP
This option enables MTD mapping of NAND flash devices. Needed to use
NAND flash memories. If unsure, say Y.
+config ETRAX_NANDBOOT
+ bool "Boot from NAND flash"
+ depends on ETRAX_NANDFLASH
+ help
+ This options enables booting from NAND flash devices.
+ Say Y if your boot code, kernel and root file system is in
+ NAND flash. Say N if they are in NOR flash.
+
config ETRAX_I2C
bool "I2C driver"
depends on ETRAX_ARCH_V32
help
- This option enabled the I2C driver used by e.g. the RTC driver.
+ This option enables the I2C driver used by e.g. the RTC driver.
-config ETRAX_I2C_DATA_PORT
+config ETRAX_V32_I2C_DATA_PORT
string "I2C data pin"
depends on ETRAX_I2C
help
The pin to use for I2C data.
-config ETRAX_I2C_CLK_PORT
+config ETRAX_V32_I2C_CLK_PORT
string "I2C clock pin"
depends on ETRAX_I2C
help
The pin to use for I2C clock.
-config ETRAX_RTC
- bool "Real Time Clock support"
- depends on ETRAX_ARCH_V32
- help
- Enabled RTC support.
-
-choice
- prompt "RTC chip"
- depends on ETRAX_RTC
- default ETRAX_PCF8563
-
-config ETRAX_PCF8563
- bool "PCF8563"
- help
- Philips PCF8563 RTC
-
-endchoice
-
config ETRAX_GPIO
bool "GPIO support"
depends on ETRAX_ARCH_V32
Remember that you need to setup the port directions appropriately in
the General configuration.
-config ETRAX_PA_BUTTON_BITMASK
- hex "PA-buttons bitmask"
+config ETRAX_VIRTUAL_GPIO
+ bool "Virtual GPIO support"
depends on ETRAX_GPIO
- default "0x02"
help
- This is a bitmask (8 bits) with information about what bits on PA
- that are used for buttons.
- Most products has a so called TEST button on PA1, if that is true
- use 0x02 here.
- Use 00 if there are no buttons on PA.
- If the bitmask is <> 00 a button driver will be included in the gpio
- driver. ETRAX general I/O support must be enabled.
+ Enables the virtual Etrax general port device (major 120, minor 6).
+ It uses an I/O expander for the I2C-bus.
+
+config ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN
+ int "Virtual GPIO interrupt pin on PA pin"
+ range 0 7
+ depends on ETRAX_VIRTUAL_GPIO
+ help
+ The pin to use on PA for virtual gpio interrupt.
config ETRAX_PA_CHANGEABLE_DIR
hex "PA user changeable dir mask"
depends on ETRAX_GPIO
- default "0x00"
+ default "0x00" if ETRAXFS
+ default "0x00000000" if !ETRAXFS
help
This is a bitmask (8 bits) with information of what bits in PA that a
user can change direction on using ioctl's.
Bit set = changeable.
- You probably want 0x00 here, but it depends on your hardware.
+ You probably want 0 here, but it depends on your hardware.
config ETRAX_PA_CHANGEABLE_BITS
hex "PA user changeable bits mask"
depends on ETRAX_GPIO
- default "0x00"
+ default "0x00" if ETRAXFS
+ default "0x00000000" if !ETRAXFS
help
This is a bitmask (8 bits) with information of what bits in PA
that a user can change the value on using ioctl's.
config ETRAX_PB_CHANGEABLE_DIR
hex "PB user changeable dir mask"
depends on ETRAX_GPIO
- default "0x00000"
+ default "0x00000" if ETRAXFS
+ default "0x00000000" if !ETRAXFS
help
This is a bitmask (18 bits) with information of what bits in PB
that a user can change direction on using ioctl's.
Bit set = changeable.
- You probably want 0x00000 here, but it depends on your hardware.
+ You probably want 0 here, but it depends on your hardware.
config ETRAX_PB_CHANGEABLE_BITS
hex "PB user changeable bits mask"
depends on ETRAX_GPIO
- default "0x00000"
+ default "0x00000" if ETRAXFS
+ default "0x00000000" if !ETRAXFS
help
This is a bitmask (18 bits) with information of what bits in PB
that a user can change the value on using ioctl's.
config ETRAX_PC_CHANGEABLE_DIR
hex "PC user changeable dir mask"
depends on ETRAX_GPIO
- default "0x00000"
+ default "0x00000" if ETRAXFS
+ default "0x00000000" if !ETRAXFS
help
This is a bitmask (18 bits) with information of what bits in PC
that a user can change direction on using ioctl's.
Bit set = changeable.
- You probably want 0x00000 here, but it depends on your hardware.
+ You probably want 0 here, but it depends on your hardware.
config ETRAX_PC_CHANGEABLE_BITS
hex "PC user changeable bits mask"
depends on ETRAX_GPIO
- default "0x00000"
+ default "0x00000" if ETRAXFS
+ default "0x00000000" if ETRAXFS
help
This is a bitmask (18 bits) with information of what bits in PC
that a user can change the value on using ioctl's.
config ETRAX_PD_CHANGEABLE_DIR
hex "PD user changeable dir mask"
- depends on ETRAX_GPIO
+ depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PD
config ETRAX_PD_CHANGEABLE_BITS
hex "PD user changeable bits mask"
- depends on ETRAX_GPIO
+ depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PD
config ETRAX_PE_CHANGEABLE_DIR
hex "PE user changeable dir mask"
- depends on ETRAX_GPIO
+ depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PE
config ETRAX_PE_CHANGEABLE_BITS
hex "PE user changeable bits mask"
- depends on ETRAX_GPIO
+ depends on ETRAX_GPIO && ETRAXFS
default "0x00000"
help
This is a bitmask (18 bits) with information of what bits in PE
that a user can change the value on using ioctl's.
Bit set = changeable.
+config ETRAX_PV_CHANGEABLE_DIR
+ hex "PV user changeable dir mask"
+ depends on ETRAX_VIRTUAL_GPIO
+ default "0x0000"
+ help
+ This is a bitmask (16 bits) with information of what bits in PV
+ that a user can change direction on using ioctl's.
+ Bit set = changeable.
+ You probably want 0x0000 here, but it depends on your hardware.
+
+config ETRAX_PV_CHANGEABLE_BITS
+ hex "PV user changeable bits mask"
+ depends on ETRAX_VIRTUAL_GPIO
+ default "0x0000"
+ help
+ This is a bitmask (16 bits) with information of what bits in PV
+ that a user can change the value on using ioctl's.
+ Bit set = changeable.
+
config ETRAX_CARDBUS
bool "Cardbus support"
depends on ETRAX_ARCH_V32
- select PCCARD
- select CARDBUS
select HOTPLUG
- select PCCARD_NONSTATIC
help
Enabled the ETRAX Cardbus driver.
This option enables a driver for the stream co-processor
for cryptographic operations.
+source drivers/mmc/Kconfig
+
+config ETRAX_MMC_IOP
+ tristate "MMC/SD host driver using IO-processor"
+ depends on ETRAX_ARCH_V32 && MMC
+ help
+ This option enables the SD/MMC host controller interface.
+ The host controller is implemented using the built in
+ IO-Processor. Only the SPU is used in this implementation.
+
+config ETRAX_SPI_MMC
+# Make this one of several "choices" (possible simultaneously but
+# suggested uniquely) when an IOP driver emerges for "real" MMC/SD
+# protocol support.
+ tristate
+ depends on !ETRAX_MMC_IOP
+ default MMC
+ select SPI
+ select MMC_SPI
+ select ETRAX_SPI_MMC_BOARD
+
+# For the parts that can't be a module (due to restrictions in
+# framework elsewhere).
+config ETRAX_SPI_MMC_BOARD
+ boolean
+ default n
+
+# While the board info is MMC_SPI only, the drivers are written to be
+# independent of MMC_SPI, so we'll keep SPI non-dependent on the
+# MMC_SPI config choices (well, except for a single depends-on-line
+# for the board-info file until a separate non-MMC SPI board file
+# emerges).
+# FIXME: When that happens, we'll need to be able to ask for and
+# configure non-MMC SPI ports together with MMC_SPI ports (if multiple
+# SPI ports are enabled).
+
+config SPI_ETRAX_SSER
+ tristate
+ depends on SPI_MASTER && ETRAX_ARCH_V32 && EXPERIMENTAL
+ select SPI_BITBANG
+ help
+ This enables using an synchronous serial (sser) port as a
+ SPI master controller on Axis ETRAX FS and later. The
+ driver can be configured to use any sser port.
+
+config SPI_ETRAX_GPIO
+ tristate
+ depends on SPI_MASTER && ETRAX_ARCH_V32 && EXPERIMENTAL
+ select SPI_BITBANG
+ help
+ This enables using GPIO pins port as a SPI master controller
+ on Axis ETRAX FS and later. The driver can be configured to
+ use any GPIO pins.
+
+config ETRAX_SPI_SSER0
+ tristate "SPI using synchronous serial port 0 (sser0)"
+ depends on ETRAX_SPI_MMC
+ default m if MMC_SPI=m
+ default y if MMC_SPI=y
+ default y if MMC_SPI=n
+ select SPI_ETRAX_SSER
+ help
+ Say Y for an MMC/SD socket connected to synchronous serial port 0,
+ or for devices using the SPI protocol on that port. Say m if you
+ want to build it as a module, which will be named spi_crisv32_sser.
+ (You need to select MMC separately.)
+
+config ETRAX_SPI_SSER0_DMA
+ bool "DMA for SPI on sser0 enabled"
+ depends on ETRAX_SPI_SSER0
+ depends on !ETRAX_SERIAL_PORT1_DMA4_OUT && !ETRAX_SERIAL_PORT1_DMA5_IN
+ default y
+ help
+ Say Y if using DMA (dma4/dma5) for SPI on synchronous serial port 0.
+
+config ETRAX_SPI_MMC_CD_SSER0_PIN
+ string "MMC/SD card detect pin for SPI on sser0"
+ depends on ETRAX_SPI_SSER0 && MMC_SPI
+ default "pd11"
+ help
+ The pin to use for SD/MMC card detect. This pin should be pulled up
+ and grounded when a card is present. If defined as " " (space), no
+ pin is selected. A card must then always be inserted for proper
+ action.
+
+config ETRAX_SPI_MMC_WP_SSER0_PIN
+ string "MMC/SD card write-protect pin for SPI on sser0"
+ depends on ETRAX_SPI_SSER0 && MMC_SPI
+ default "pd10"
+ help
+ The pin to use for the SD/MMC write-protect signal for a memory
+ card. If defined as " " (space), the card is considered writable.
+
+config ETRAX_SPI_SSER1
+ tristate "SPI using synchronous serial port 1 (sser1)"
+ depends on ETRAX_SPI_MMC
+ default m if MMC_SPI=m && ETRAX_SPI_SSER0=n
+ default y if MMC_SPI=y && ETRAX_SPI_SSER0=n
+ default y if MMC_SPI=n && ETRAX_SPI_SSER0=n
+ select SPI_ETRAX_SSER
+ help
+ Say Y for an MMC/SD socket connected to synchronous serial port 1,
+ or for devices using the SPI protocol on that port. Say m if you
+ want to build it as a module, which will be named spi_crisv32_sser.
+ (You need to select MMC separately.)
+
+config ETRAX_SPI_SSER1_DMA
+ bool "DMA for SPI on sser1 enabled"
+ depends on ETRAX_SPI_SSER1 && !ETRAX_ETHERNET_IFACE1
+ depends on !ETRAX_SERIAL_PORT0_DMA6_OUT && !ETRAX_SERIAL_PORT0_DMA7_IN
+ default y
+ help
+ Say Y if using DMA (dma6/dma7) for SPI on synchronous serial port 1.
+
+config ETRAX_SPI_MMC_CD_SSER1_PIN
+ string "MMC/SD card detect pin for SPI on sser1"
+ depends on ETRAX_SPI_SSER1 && MMC_SPI
+ default "pd12"
+ help
+ The pin to use for SD/MMC card detect. This pin should be pulled up
+ and grounded when a card is present. If defined as " " (space), no
+ pin is selected. A card must then always be inserted for proper
+ action.
+
+config ETRAX_SPI_MMC_WP_SSER1_PIN
+ string "MMC/SD card write-protect pin for SPI on sser1"
+ depends on ETRAX_SPI_SSER1 && MMC_SPI
+ default "pd9"
+ help
+ The pin to use for the SD/MMC write-protect signal for a memory
+ card. If defined as " " (space), the card is considered writable.
+
+config ETRAX_SPI_GPIO
+ tristate "Bitbanged SPI using gpio pins"
+ depends on ETRAX_SPI_MMC
+ select SPI_ETRAX_GPIO
+ default m if MMC_SPI=m && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
+ default y if MMC_SPI=y && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
+ default y if MMC_SPI=n && ETRAX_SPI_SSER0=n && ETRAX_SPI_SSER1=n
+ help
+ Say Y for an MMC/SD socket connected to general I/O pins (but not
+ a complete synchronous serial ports), or for devices using the SPI
+ protocol on general I/O pins. Slow and slows down the system.
+ Say m to build it as a module, which will be called spi_crisv32_gpio.
+ (You need to select MMC separately.)
+
+# The default match that of sser0, only because that's how it was tested.
+config ETRAX_SPI_CS_PIN
+ string "SPI chip select pin"
+ depends on ETRAX_SPI_GPIO
+ default "pc3"
+ help
+ The pin to use for SPI chip select.
+
+config ETRAX_SPI_CLK_PIN
+ string "SPI clock pin"
+ depends on ETRAX_SPI_GPIO
+ default "pc1"
+ help
+ The pin to use for the SPI clock.
+
+config ETRAX_SPI_DATAIN_PIN
+ string "SPI MISO (data in) pin"
+ depends on ETRAX_SPI_GPIO
+ default "pc16"
+ help
+ The pin to use for SPI data in from the device.
+
+config ETRAX_SPI_DATAOUT_PIN
+ string "SPI MOSI (data out) pin"
+ depends on ETRAX_SPI_GPIO
+ default "pc0"
+ help
+ The pin to use for SPI data out to the device.
+
+config ETRAX_SPI_MMC_CD_GPIO_PIN
+ string "MMC/SD card detect pin for SPI using gpio (space for none)"
+ depends on ETRAX_SPI_GPIO && MMC_SPI
+ default "pd11"
+ help
+ The pin to use for SD/MMC card detect. This pin should be pulled up
+ and grounded when a card is present. If defined as " " (space), no
+ pin is selected. A card must then always be inserted for proper
+ action.
+
+config ETRAX_SPI_MMC_WP_GPIO_PIN
+ string "MMC/SD card write-protect pin for SPI using gpio (space for none)"
+ depends on ETRAX_SPI_GPIO && MMC_SPI
+ default "pd10"
+ help
+ The pin to use for the SD/MMC write-protect signal for a memory
+ card. If defined as " " (space), the card is considered writable.
+
+# Avoid choices causing non-working configs by conditionalizing the inclusion.
+if ETRAX_SPI_MMC
+source drivers/spi/Kconfig
+endif
+
endif
obj-$(CONFIG_ETRAX_STREAMCOPROC) += cryptocop.o
obj-$(CONFIG_ETRAX_AXISFLASHMAP) += axisflashmap.o
-obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
-obj-$(CONFIG_ETRAX_GPIO) += gpio.o
+obj-$(CONFIG_ETRAXFS) += mach-fs/
+obj-$(CONFIG_CRIS_MACH_ARTPEC3) += mach-a3/
obj-$(CONFIG_ETRAX_IOP_FW_LOAD) += iop_fw_load.o
obj-$(CONFIG_ETRAX_PCF8563) += pcf8563.o
obj-$(CONFIG_ETRAX_I2C) += i2c.o
obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL) += sync_serial.o
obj-$(CONFIG_PCI) += pci/
+obj-$(CONFIG_ETRAX_SPI_MMC_BOARD) += board_mmcspi.o
/*
* Physical mapping layer for MTD using the Axis partitiontable format
*
- * Copyright (c) 2001, 2002, 2003 Axis Communications AB
+ * Copyright (c) 2001-2007 Axis Communications AB
*
* This file is under the GPL.
*
* tells us what other partitions to define. If there isn't, we use a default
* partition split defined below.
*
- * Copy of os/lx25/arch/cris/arch-v10/drivers/axisflashmap.c 1.5
- * with minor changes.
- *
*/
#include <linux/module.h>
#include <linux/mtd/mtdram.h>
#include <linux/mtd/partitions.h>
-#include <asm/arch/hwregs/config_defs.h>
+#include <linux/cramfs_fs.h>
+
#include <asm/axisflashmap.h>
#include <asm/mmu.h>
#define FLASH_UNCACHED_ADDR KSEG_E
#define FLASH_CACHED_ADDR KSEG_F
+#define PAGESIZE (512)
+
#if CONFIG_ETRAX_FLASH_BUSWIDTH==1
#define flash_data __u8
#elif CONFIG_ETRAX_FLASH_BUSWIDTH==2
#define flash_data __u16
#elif CONFIG_ETRAX_FLASH_BUSWIDTH==4
-#define flash_data __u16
+#define flash_data __u32
#endif
/* From head.S */
-extern unsigned long romfs_start, romfs_length, romfs_in_flash;
+extern unsigned long romfs_in_flash; /* 1 when romfs_start, _length in flash */
+extern unsigned long romfs_start, romfs_length;
+extern unsigned long nand_boot; /* 1 when booted from nand flash */
+
+struct partition_name {
+ char name[6];
+};
/* The master mtd for the entire flash. */
struct mtd_info* axisflash_mtd = NULL;
.map_priv_1 = FLASH_UNCACHED_ADDR + MEM_CSE0_SIZE
};
-/* If no partition-table was found, we use this default-set. */
-#define MAX_PARTITIONS 7
-#define NUM_DEFAULT_PARTITIONS 3
+#define MAX_PARTITIONS 7
+#ifdef CONFIG_ETRAX_NANDBOOT
+#define NUM_DEFAULT_PARTITIONS 4
+#define DEFAULT_ROOTFS_PARTITION_NO 2
+#define DEFAULT_MEDIA_SIZE 0x2000000 /* 32 megs */
+#else
+#define NUM_DEFAULT_PARTITIONS 3
+#define DEFAULT_ROOTFS_PARTITION_NO (-1)
+#define DEFAULT_MEDIA_SIZE 0x800000 /* 8 megs */
+#endif
-/*
- * Default flash size is 2MB. CONFIG_ETRAX_PTABLE_SECTOR is most likely the
- * size of one flash block and "filesystem"-partition needs 5 blocks to be able
- * to use JFFS.
- */
-static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = {
- {
- .name = "boot firmware",
- .size = CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0
- },
- {
- .name = "kernel",
- .size = 0x200000 - (6 * CONFIG_ETRAX_PTABLE_SECTOR),
- .offset = CONFIG_ETRAX_PTABLE_SECTOR
- },
- {
- .name = "filesystem",
- .size = 5 * CONFIG_ETRAX_PTABLE_SECTOR,
- .offset = 0x200000 - (5 * CONFIG_ETRAX_PTABLE_SECTOR)
- }
-};
+#if (MAX_PARTITIONS < NUM_DEFAULT_PARTITIONS)
+#error MAX_PARTITIONS must be >= than NUM_DEFAULT_PARTITIONS
+#endif
/* Initialize the ones normally used. */
static struct mtd_partition axis_partitions[MAX_PARTITIONS] = {
},
};
+
+/* If no partition-table was found, we use this default-set.
+ * Default flash size is 8MB (NOR). CONFIG_ETRAX_PTABLE_SECTOR is most
+ * likely the size of one flash block and "filesystem"-partition needs
+ * to be >=5 blocks to be able to use JFFS.
+ */
+static struct mtd_partition axis_default_partitions[NUM_DEFAULT_PARTITIONS] = {
+ {
+ .name = "boot firmware",
+ .size = CONFIG_ETRAX_PTABLE_SECTOR,
+ .offset = 0
+ },
+ {
+ .name = "kernel",
+ .size = 10 * CONFIG_ETRAX_PTABLE_SECTOR,
+ .offset = CONFIG_ETRAX_PTABLE_SECTOR
+ },
+#define FILESYSTEM_SECTOR (11 * CONFIG_ETRAX_PTABLE_SECTOR)
+#ifdef CONFIG_ETRAX_NANDBOOT
+ {
+ .name = "rootfs",
+ .size = 10 * CONFIG_ETRAX_PTABLE_SECTOR,
+ .offset = FILESYSTEM_SECTOR
+ },
+#undef FILESYSTEM_SECTOR
+#define FILESYSTEM_SECTOR (21 * CONFIG_ETRAX_PTABLE_SECTOR)
+#endif
+ {
+ .name = "rwfs",
+ .size = DEFAULT_MEDIA_SIZE - FILESYSTEM_SECTOR,
+ .offset = FILESYSTEM_SECTOR
+ }
+};
+
+#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
+/* Main flash device */
+static struct mtd_partition main_partition = {
+ .name = "main",
+ .size = 0,
+ .offset = 0
+};
+#endif
+
+/* Auxilliary partition if we find another flash */
+static struct mtd_partition aux_partition = {
+ .name = "aux",
+ .size = 0,
+ .offset = 0
+};
+
/*
* Probe a chip select for AMD-compatible (JEDEC) or CFI-compatible flash
* chips in that order (because the amd_flash-driver is faster).
map_cs->name, map_cs->size, map_cs->map_priv_1);
#ifdef CONFIG_MTD_CFI
- mtd_cs = do_map_probe("cfi_probe", map_cs);
+ mtd_cs = do_map_probe("cfi_probe", map_cs);
#endif
#ifdef CONFIG_MTD_JEDECPROBE
if (!mtd_cs)
/*
* Probe each chip select individually for flash chips. If there are chips on
* both cse0 and cse1, the mtd_info structs will be concatenated to one struct
- * so that MTD partitions can cross chip boundaries.
+ * so that MTD partitions can cross chip boundries.
*
* The only known restriction to how you can mount your chips is that each
* chip select must hold similar flash chips. But you need external hardware
{
struct mtd_info *mtd_cse0;
struct mtd_info *mtd_cse1;
- struct mtd_info *mtd_nand = NULL;
struct mtd_info *mtd_total;
- struct mtd_info *mtds[3];
+ struct mtd_info *mtds[2];
int count = 0;
if ((mtd_cse0 = probe_cs(&map_cse0)) != NULL)
if ((mtd_cse1 = probe_cs(&map_cse1)) != NULL)
mtds[count++] = mtd_cse1;
-#ifdef CONFIG_ETRAX_NANDFLASH
- if ((mtd_nand = crisv32_nand_flash_probe()) != NULL)
- mtds[count++] = mtd_nand;
-#endif
-
- if (!mtd_cse0 && !mtd_cse1 && !mtd_nand) {
+ if (!mtd_cse0 && !mtd_cse1) {
/* No chip found. */
return NULL;
}
* So we use the MTD concatenation layer instead of further
* complicating the probing procedure.
*/
- mtd_total = mtd_concat_create(mtds,
- count,
- "cse0+cse1+nand");
+ mtd_total = mtd_concat_create(mtds, count, "cse0+cse1");
#else
printk(KERN_ERR "%s and %s: Cannot concatenate due to kernel "
"(mis)configuration!\n", map_cse0.name, map_cse1.name);
#endif
if (!mtd_total) {
printk(KERN_ERR "%s and %s: Concatenation failed!\n",
- map_cse0.name, map_cse1.name);
+ map_cse0.name, map_cse1.name);
/* The best we can do now is to only use what we found
- * at cse0.
- */
+ * at cse0. */
mtd_total = mtd_cse0;
map_destroy(mtd_cse1);
}
- } else {
- mtd_total = mtd_cse0? mtd_cse0 : mtd_cse1 ? mtd_cse1 : mtd_nand;
-
- }
+ } else
+ mtd_total = mtd_cse0 ? mtd_cse0 : mtd_cse1;
return mtd_total;
}
-extern unsigned long crisv32_nand_boot;
-extern unsigned long crisv32_nand_cramfs_offset;
-
/*
* Probe the flash chip(s) and, if it succeeds, read the partition-table
* and register the partitions with MTD.
*/
static int __init init_axis_flash(void)
{
- struct mtd_info *mymtd;
+ struct mtd_info *main_mtd;
+ struct mtd_info *aux_mtd = NULL;
int err = 0;
int pidx = 0;
struct partitiontable_head *ptable_head = NULL;
struct partitiontable_entry *ptable;
- int use_default_ptable = 1; /* Until proven otherwise. */
- const char *pmsg = KERN_INFO " /dev/flash%d at 0x%08x, size 0x%08x\n";
- static char page[512];
+ int ptable_ok = 0;
+ static char page[PAGESIZE];
size_t len;
+ int ram_rootfs_partition = -1; /* -1 => no RAM rootfs partition */
+ int part;
+
+ /* We need a root fs. If it resides in RAM, we need to use an
+ * MTDRAM device, so it must be enabled in the kernel config,
+ * but its size must be configured as 0 so as not to conflict
+ * with our usage.
+ */
+#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0)
+ if (!romfs_in_flash && !nand_boot) {
+ printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM "
+ "device; configure CONFIG_MTD_MTDRAM with size = 0!\n");
+ panic("This kernel cannot boot from RAM!\n");
+ }
+#endif
+
+#ifndef CONFIG_ETRAX_VCS_SIM
+ main_mtd = flash_probe();
+ if (main_mtd)
+ printk(KERN_INFO "%s: 0x%08x bytes of NOR flash memory.\n",
+ main_mtd->name, main_mtd->size);
+
+#ifdef CONFIG_ETRAX_NANDFLASH
+ aux_mtd = crisv32_nand_flash_probe();
+ if (aux_mtd)
+ printk(KERN_INFO "%s: 0x%08x bytes of NAND flash memory.\n",
+ aux_mtd->name, aux_mtd->size);
+
+#ifdef CONFIG_ETRAX_NANDBOOT
+ {
+ struct mtd_info *tmp_mtd;
-#ifndef CONFIG_ETRAXFS_SIM
- mymtd = flash_probe();
- mymtd->read(mymtd, CONFIG_ETRAX_PTABLE_SECTOR, 512, &len, page);
- ptable_head = (struct partitiontable_head *)(page + PARTITION_TABLE_OFFSET);
+ printk(KERN_INFO "axisflashmap: Set to boot from NAND flash, "
+ "making NAND flash primary device.\n");
+ tmp_mtd = main_mtd;
+ main_mtd = aux_mtd;
+ aux_mtd = tmp_mtd;
+ }
+#endif /* CONFIG_ETRAX_NANDBOOT */
+#endif /* CONFIG_ETRAX_NANDFLASH */
- if (!mymtd) {
+ if (!main_mtd && !aux_mtd) {
/* There's no reason to use this module if no flash chip can
* be identified. Make sure that's understood.
*/
printk(KERN_INFO "axisflashmap: Found no flash chip.\n");
- } else {
- printk(KERN_INFO "%s: 0x%08x bytes of flash memory.\n",
- mymtd->name, mymtd->size);
- axisflash_mtd = mymtd;
}
- if (mymtd) {
- mymtd->owner = THIS_MODULE;
+#if 0 /* Dump flash memory so we can see what is going on */
+ if (main_mtd) {
+ int sectoraddr, i;
+ for (sectoraddr = 0; sectoraddr < 2*65536+4096;
+ sectoraddr += PAGESIZE) {
+ main_mtd->read(main_mtd, sectoraddr, PAGESIZE, &len,
+ page);
+ printk(KERN_INFO
+ "Sector at %d (length %d):\n",
+ sectoraddr, len);
+ for (i = 0; i < PAGESIZE; i += 16) {
+ printk(KERN_INFO
+ "%02x %02x %02x %02x "
+ "%02x %02x %02x %02x "
+ "%02x %02x %02x %02x "
+ "%02x %02x %02x %02x\n",
+ page[i] & 255, page[i+1] & 255,
+ page[i+2] & 255, page[i+3] & 255,
+ page[i+4] & 255, page[i+5] & 255,
+ page[i+6] & 255, page[i+7] & 255,
+ page[i+8] & 255, page[i+9] & 255,
+ page[i+10] & 255, page[i+11] & 255,
+ page[i+12] & 255, page[i+13] & 255,
+ page[i+14] & 255, page[i+15] & 255);
+ }
+ }
+ }
+#endif
+
+ if (main_mtd) {
+ main_mtd->owner = THIS_MODULE;
+ axisflash_mtd = main_mtd;
+
+ loff_t ptable_sector = CONFIG_ETRAX_PTABLE_SECTOR;
+
+ /* First partition (rescue) is always set to the default. */
+ pidx++;
+#ifdef CONFIG_ETRAX_NANDBOOT
+ /* We know where the partition table should be located,
+ * it will be in first good block after that.
+ */
+ int blockstat;
+ do {
+ blockstat = main_mtd->block_isbad(main_mtd,
+ ptable_sector);
+ if (blockstat < 0)
+ ptable_sector = 0; /* read error */
+ else if (blockstat)
+ ptable_sector += main_mtd->erasesize;
+ } while (blockstat && ptable_sector);
+#endif
+ if (ptable_sector) {
+ main_mtd->read(main_mtd, ptable_sector, PAGESIZE,
+ &len, page);
+ ptable_head = &((struct partitiontable *) page)->head;
+ }
+
+#if 0 /* Dump partition table so we can see what is going on */
+ printk(KERN_INFO
+ "axisflashmap: flash read %d bytes at 0x%08x, data: "
+ "%02x %02x %02x %02x %02x %02x %02x %02x\n",
+ len, CONFIG_ETRAX_PTABLE_SECTOR,
+ page[0] & 255, page[1] & 255,
+ page[2] & 255, page[3] & 255,
+ page[4] & 255, page[5] & 255,
+ page[6] & 255, page[7] & 255);
+ printk(KERN_INFO
+ "axisflashmap: partition table offset %d, data: "
+ "%02x %02x %02x %02x %02x %02x %02x %02x\n",
+ PARTITION_TABLE_OFFSET,
+ page[PARTITION_TABLE_OFFSET+0] & 255,
+ page[PARTITION_TABLE_OFFSET+1] & 255,
+ page[PARTITION_TABLE_OFFSET+2] & 255,
+ page[PARTITION_TABLE_OFFSET+3] & 255,
+ page[PARTITION_TABLE_OFFSET+4] & 255,
+ page[PARTITION_TABLE_OFFSET+5] & 255,
+ page[PARTITION_TABLE_OFFSET+6] & 255,
+ page[PARTITION_TABLE_OFFSET+7] & 255);
+#endif
}
- pidx++; /* First partition is always set to the default. */
if (ptable_head && (ptable_head->magic == PARTITION_TABLE_MAGIC)
&& (ptable_head->size <
/* Looks like a start, sane length and end of a
* partition table, lets check csum etc.
*/
- int ptable_ok = 0;
struct partitiontable_entry *max_addr =
(struct partitiontable_entry *)
((unsigned long)ptable_head + sizeof(*ptable_head) +
ptable_ok = (csum == ptable_head->checksum);
/* Read the entries and use/show the info. */
- printk(KERN_INFO " Found a%s partition table at 0x%p-0x%p.\n",
+ printk(KERN_INFO "axisflashmap: "
+ "Found a%s partition table at 0x%p-0x%p.\n",
(ptable_ok ? " valid" : "n invalid"), ptable_head,
max_addr);
/* We have found a working bootblock. Now read the
- * partition table. Scan the table. It ends when
- * there is 0xffffffff, that is, empty flash.
+ * partition table. Scan the table. It ends with 0xffffffff.
*/
while (ptable_ok
- && ptable->offset != 0xffffffff
+ && ptable->offset != PARTITIONTABLE_END_MARKER
&& ptable < max_addr
- && pidx < MAX_PARTITIONS) {
+ && pidx < MAX_PARTITIONS - 1) {
- axis_partitions[pidx].offset = offset + ptable->offset + (crisv32_nand_boot ? 16384 : 0);
- axis_partitions[pidx].size = ptable->size;
-
- printk(pmsg, pidx, axis_partitions[pidx].offset,
- axis_partitions[pidx].size);
+ axis_partitions[pidx].offset = offset + ptable->offset;
+#ifdef CONFIG_ETRAX_NANDFLASH
+ if (main_mtd->type == MTD_NANDFLASH) {
+ axis_partitions[pidx].size =
+ (((ptable+1)->offset ==
+ PARTITIONTABLE_END_MARKER) ?
+ main_mtd->size :
+ ((ptable+1)->offset + offset)) -
+ (ptable->offset + offset);
+
+ } else
+#endif /* CONFIG_ETRAX_NANDFLASH */
+ axis_partitions[pidx].size = ptable->size;
+#ifdef CONFIG_ETRAX_NANDBOOT
+ /* Save partition number of jffs2 ro partition.
+ * Needed if RAM booting or root file system in RAM.
+ */
+ if (!nand_boot &&
+ ram_rootfs_partition < 0 && /* not already set */
+ ptable->type == PARTITION_TYPE_JFFS2 &&
+ (ptable->flags & PARTITION_FLAGS_READONLY_MASK) ==
+ PARTITION_FLAGS_READONLY)
+ ram_rootfs_partition = pidx;
+#endif /* CONFIG_ETRAX_NANDBOOT */
pidx++;
ptable++;
}
- use_default_ptable = !ptable_ok;
}
- if (romfs_in_flash) {
- /* Add an overlapping device for the root partition (romfs). */
+ /* Decide whether to use default partition table. */
+ /* Only use default table if we actually have a device (main_mtd) */
- axis_partitions[pidx].name = "romfs";
- if (crisv32_nand_boot) {
- char* data = kmalloc(1024, GFP_KERNEL);
- int len;
- int offset = crisv32_nand_cramfs_offset & ~(1024-1);
- char* tmp;
-
- mymtd->read(mymtd, offset, 1024, &len, data);
- tmp = &data[crisv32_nand_cramfs_offset % 512];
- axis_partitions[pidx].size = *(unsigned*)(tmp + 4);
- axis_partitions[pidx].offset = crisv32_nand_cramfs_offset;
- kfree(data);
- } else {
- axis_partitions[pidx].size = romfs_length;
- axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR;
- }
+ struct mtd_partition *partition = &axis_partitions[0];
+ if (main_mtd && !ptable_ok) {
+ memcpy(axis_partitions, axis_default_partitions,
+ sizeof(axis_default_partitions));
+ pidx = NUM_DEFAULT_PARTITIONS;
+ ram_rootfs_partition = DEFAULT_ROOTFS_PARTITION_NO;
+ }
+ /* Add artificial partitions for rootfs if necessary */
+ if (romfs_in_flash) {
+ /* rootfs is in directly accessible flash memory = NOR flash.
+ Add an overlapping device for the rootfs partition. */
+ printk(KERN_INFO "axisflashmap: Adding partition for "
+ "overlapping root file system image\n");
+ axis_partitions[pidx].size = romfs_length;
+ axis_partitions[pidx].offset = romfs_start - FLASH_CACHED_ADDR;
+ axis_partitions[pidx].name = "romfs";
axis_partitions[pidx].mask_flags |= MTD_WRITEABLE;
-
- printk(KERN_INFO
- " Adding readonly flash partition for romfs image:\n");
- printk(pmsg, pidx, axis_partitions[pidx].offset,
- axis_partitions[pidx].size);
+ ram_rootfs_partition = -1;
pidx++;
- }
-
- if (mymtd) {
- if (use_default_ptable) {
- printk(KERN_INFO " Using default partition table.\n");
- err = add_mtd_partitions(mymtd, axis_default_partitions,
- NUM_DEFAULT_PARTITIONS);
- } else {
- err = add_mtd_partitions(mymtd, axis_partitions, pidx);
+ } else if (romfs_length && !nand_boot) {
+ /* romfs exists in memory, but not in flash, so must be in RAM.
+ * Configure an MTDRAM partition. */
+ if (ram_rootfs_partition < 0) {
+ /* None set yet, put it at the end */
+ ram_rootfs_partition = pidx;
+ pidx++;
}
+ printk(KERN_INFO "axisflashmap: Adding partition for "
+ "root file system image in RAM\n");
+ axis_partitions[ram_rootfs_partition].size = romfs_length;
+ axis_partitions[ram_rootfs_partition].offset = romfs_start;
+ axis_partitions[ram_rootfs_partition].name = "romfs";
+ axis_partitions[ram_rootfs_partition].mask_flags |=
+ MTD_WRITEABLE;
+ }
- if (err) {
- panic("axisflashmap could not add MTD partitions!\n");
- }
+#ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
+ if (main_mtd) {
+ main_partition.size = main_mtd->size;
+ err = add_mtd_partitions(main_mtd, &main_partition, 1);
+ if (err)
+ panic("axisflashmap: Could not initialize "
+ "partition for whole main mtd device!\n");
}
-/* CONFIG_EXTRAXFS_SIM */
#endif
- if (!romfs_in_flash) {
- /* Create an RAM device for the root partition (romfs). */
+ /* Now, register all partitions with mtd.
+ * We do this one at a time so we can slip in an MTDRAM device
+ * in the proper place if required. */
+
+ for (part = 0; part < pidx; part++) {
+ if (part == ram_rootfs_partition) {
+ /* add MTDRAM partition here */
+ struct mtd_info *mtd_ram;
+
+ mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
+ if (!mtd_ram)
+ panic("axisflashmap: Couldn't allocate memory "
+ "for mtd_info!\n");
+ printk(KERN_INFO "axisflashmap: Adding RAM partition "
+ "for rootfs image.\n");
+ err = mtdram_init_device(mtd_ram,
+ (void *)partition[part].offset,
+ partition[part].size,
+ partition[part].name);
+ if (err)
+ panic("axisflashmap: Could not initialize "
+ "MTD RAM device!\n");
+ /* JFFS2 likes to have an erasesize. Keep potential
+ * JFFS2 rootfs happy by providing one. Since image
+ * was most likely created for main mtd, use that
+ * erasesize, if available. Otherwise, make a guess. */
+ mtd_ram->erasesize = (main_mtd ? main_mtd->erasesize :
+ CONFIG_ETRAX_PTABLE_SECTOR);
+ } else {
+ err = add_mtd_partitions(main_mtd, &partition[part], 1);
+ if (err)
+ panic("axisflashmap: Could not add mtd "
+ "partition %d\n", part);
+ }
+ }
+#endif /* CONFIG_EXTRAX_VCS_SIM */
+
+#ifdef CONFIG_ETRAX_VCS_SIM
+ /* For simulator, always use a RAM partition.
+ * The rootfs will be found after the kernel in RAM,
+ * with romfs_start and romfs_end indicating location and size.
+ */
+ struct mtd_info *mtd_ram;
+
+ mtd_ram = kmalloc(sizeof(struct mtd_info), GFP_KERNEL);
+ if (!mtd_ram) {
+ panic("axisflashmap: Couldn't allocate memory for "
+ "mtd_info!\n");
+ }
-#if !defined(CONFIG_MTD_MTDRAM) || (CONFIG_MTDRAM_TOTAL_SIZE != 0) || (CONFIG_MTDRAM_ABS_POS != 0)
- /* No use trying to boot this kernel from RAM. Panic! */
- printk(KERN_EMERG "axisflashmap: Cannot create an MTD RAM "
- "device due to kernel (mis)configuration!\n");
- panic("This kernel cannot boot from RAM!\n");
-#else
- struct mtd_info *mtd_ram;
+ printk(KERN_INFO "axisflashmap: Adding RAM partition for romfs, "
+ "at %u, size %u\n",
+ (unsigned) romfs_start, (unsigned) romfs_length);
- mtd_ram = kmalloc(sizeof(struct mtd_info),
- GFP_KERNEL);
- if (!mtd_ram) {
- panic("axisflashmap couldn't allocate memory for "
- "mtd_info!\n");
- }
+ err = mtdram_init_device(mtd_ram, (void *)romfs_start,
+ romfs_length, "romfs");
+ if (err) {
+ panic("axisflashmap: Could not initialize MTD RAM "
+ "device!\n");
+ }
+#endif /* CONFIG_EXTRAX_VCS_SIM */
- printk(KERN_INFO " Adding RAM partition for romfs image:\n");
- printk(pmsg, pidx, romfs_start, romfs_length);
+#ifndef CONFIG_ETRAX_VCS_SIM
+ if (aux_mtd) {
+ aux_partition.size = aux_mtd->size;
+ err = add_mtd_partitions(aux_mtd, &aux_partition, 1);
+ if (err)
+ panic("axisflashmap: Could not initialize "
+ "aux mtd device!\n");
- err = mtdram_init_device(mtd_ram, (void*)romfs_start,
- romfs_length, "romfs");
- if (err) {
- panic("axisflashmap could not initialize MTD RAM "
- "device!\n");
- }
-#endif
}
+#endif /* CONFIG_EXTRAX_VCS_SIM */
return err;
}
-/* $Id: cryptocop.c,v 1.13 2005/04/21 17:27:55 henriken Exp $
- *
+/*
* Stream co-processor driver for the ETRAX FS
*
- * Copyright (C) 2003-2005 Axis Communications AB
+ * Copyright (C) 2003-2007 Axis Communications AB
*/
#include <linux/init.h>
#include <asm/signal.h>
#include <asm/irq.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/hwregs/dma.h>
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/intr_vect_defs.h>
-
-#include <asm/arch/hwregs/strcop.h>
-#include <asm/arch/hwregs/strcop_defs.h>
-#include <asm/arch/cryptocop.h>
-
-
+#include <dma.h>
+#include <hwregs/dma.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/intr_vect_defs.h>
+
+#include <hwregs/strcop.h>
+#include <hwregs/strcop_defs.h>
+#include <cryptocop.h>
+
+#ifdef CONFIG_ETRAXFS
+#define IN_DMA 9
+#define OUT_DMA 8
+#define IN_DMA_INST regi_dma9
+#define OUT_DMA_INST regi_dma8
+#define DMA_IRQ DMA9_INTR_VECT
+#else
+#define IN_DMA 3
+#define OUT_DMA 2
+#define IN_DMA_INST regi_dma3
+#define OUT_DMA_INST regi_dma2
+#define DMA_IRQ DMA3_INTR_VECT
+#endif
#define DESCR_ALLOC_PAD (31)
}
static irqreturn_t
-dma_done_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+dma_done_interrupt(int irq, void *dev_id)
{
struct cryptocop_prio_job *done_job;
reg_dma_rw_ack_intr ack_intr = {
.data = 1,
};
- REG_WR (dma, regi_dma9, rw_ack_intr, ack_intr);
+ REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr);
DEBUG(printk("cryptocop DMA done\n"));
static int init_cryptocop(void)
{
unsigned long flags;
- reg_intr_vect_rw_mask intr_mask;
reg_dma_rw_cfg dma_cfg = {.en = 1};
reg_dma_rw_intr_mask intr_mask_in = {.data = regk_dma_yes}; /* Only want descriptor interrupts from the DMA in channel. */
reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 };
.en = 1
};
- if (request_irq(DMA9_INTR_VECT, dma_done_interrupt, 0, "stream co-processor DMA", NULL)) panic("request_irq stream co-processor irq dma9");
+ if (request_irq(DMA_IRQ, dma_done_interrupt, 0,
+ "stream co-processor DMA", NULL))
+ panic("request_irq stream co-processor irq dma9");
- (void)crisv32_request_dma(8, "strcop", DMA_PANIC_ON_ERROR, 0, dma_strp);
- (void)crisv32_request_dma(9, "strcop", DMA_PANIC_ON_ERROR, 0, dma_strp);
+ (void)crisv32_request_dma(OUT_DMA, "strcop", DMA_PANIC_ON_ERROR,
+ 0, dma_strp);
+ (void)crisv32_request_dma(IN_DMA, "strcop", DMA_PANIC_ON_ERROR,
+ 0, dma_strp);
local_irq_save(flags);
strcop_cfg.en = 1;
REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg);
- /* Enable DMA9 interrupt */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.dma9 = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
-
/* Enable DMAs. */
- REG_WR(dma, regi_dma9, rw_cfg, dma_cfg); /* input DMA */
- REG_WR(dma, regi_dma8, rw_cfg, dma_cfg); /* output DMA */
+ REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */
+ REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */
/* Set up wordsize = 4 for DMAs. */
- DMA_WR_CMD (regi_dma8, regk_dma_set_w_size4);
- DMA_WR_CMD (regi_dma9, regk_dma_set_w_size4);
+ DMA_WR_CMD(OUT_DMA_INST, regk_dma_set_w_size4);
+ DMA_WR_CMD(IN_DMA_INST, regk_dma_set_w_size4);
/* Enable interrupts. */
- REG_WR(dma, regi_dma9, rw_intr_mask, intr_mask_in);
+ REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in);
/* Clear intr ack. */
- REG_WR(dma, regi_dma9, rw_ack_intr, ack_intr);
+ REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr);
local_irq_restore(flags);
static void release_cryptocop(void)
{
unsigned long flags;
- reg_intr_vect_rw_mask intr_mask;
reg_dma_rw_cfg dma_cfg = {.en = 0};
reg_dma_rw_intr_mask intr_mask_in = {0};
reg_dma_rw_ack_intr ack_intr = {.data = 1,.in_eop = 1 };
local_irq_save(flags);
/* Clear intr ack. */
- REG_WR(dma, regi_dma9, rw_ack_intr, ack_intr);
-
- /* Disable DMA9 interrupt */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.dma9 = 0;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
+ REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr);
/* Disable DMAs. */
- REG_WR(dma, regi_dma9, rw_cfg, dma_cfg); /* input DMA */
- REG_WR(dma, regi_dma8, rw_cfg, dma_cfg); /* output DMA */
+ REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */
+ REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */
/* Disable interrupts. */
- REG_WR(dma, regi_dma9, rw_intr_mask, intr_mask_in);
+ REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in);
local_irq_restore(flags);
- free_irq(DMA9_INTR_VECT, NULL);
+ free_irq(DMA_IRQ, NULL);
- (void)crisv32_free_dma(8);
- (void)crisv32_free_dma(9);
+ (void)crisv32_free_dma(OUT_DMA);
+ (void)crisv32_free_dma(IN_DMA);
}
reg_dma_rw_cfg dma_out_cfg, dma_in_cfg;
/* Stop DMA. */
- dma_out_cfg = REG_RD(dma, regi_dma8, rw_cfg);
+ dma_out_cfg = REG_RD(dma, OUT_DMA_INST, rw_cfg);
dma_out_cfg.en = regk_dma_no;
- REG_WR(dma, regi_dma8, rw_cfg, dma_out_cfg);
+ REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_out_cfg);
- dma_in_cfg = REG_RD(dma, regi_dma9, rw_cfg);
+ dma_in_cfg = REG_RD(dma, IN_DMA_INST, rw_cfg);
dma_in_cfg.en = regk_dma_no;
- REG_WR(dma, regi_dma9, rw_cfg, dma_in_cfg);
+ REG_WR(dma, IN_DMA_INST, rw_cfg, dma_in_cfg);
/* Disble the cryptocop. */
rw_cfg = REG_RD(strcop, regi_strcop, rw_cfg);
&pj->iop->ctx_out, (char*)virt_to_phys(&pj->iop->ctx_out)));
/* Start input DMA. */
- DMA_START_CONTEXT(regi_dma9, virt_to_phys(&pj->iop->ctx_in));
+ flush_dma_context(&pj->iop->ctx_in);
+ DMA_START_CONTEXT(IN_DMA_INST, virt_to_phys(&pj->iop->ctx_in));
/* Start output DMA. */
- DMA_START_CONTEXT(regi_dma8, virt_to_phys(&pj->iop->ctx_out));
+ DMA_START_CONTEXT(OUT_DMA_INST, virt_to_phys(&pj->iop->ctx_out));
spin_unlock_irqrestore(&running_job_lock, running_job_flags);
DEBUG(printk("cryptocop_start_job: exiting\n"));
*!
*! ---------------------------------------------------------------------------
*!
-*! (C) Copyright 1999-2002 Axis Communications AB, LUND, SWEDEN
+*! (C) Copyright 1999-2007 Axis Communications AB, LUND, SWEDEN
*!
*!***************************************************************************/
-/* $Id: i2c.c,v 1.2 2005/05/09 15:29:49 starvik Exp $ */
+
/****************** INCLUDE FILES SECTION ***********************************/
#include <linux/module.h>
#define i2c_delay(usecs) udelay(usecs)
+static DEFINE_SPINLOCK(i2c_lock); /* Protect directions etc */
+
/****************** VARIABLE SECTION ************************************/
static struct crisv32_iopin cris_i2c_clk;
* generate ACK clock pulse
*/
i2c_clk(I2C_CLOCK_HIGH);
+#if 0
/*
* Use PORT PB instead of I2C
* for input. (I2C not working)
i2c_data(1);
i2c_disable();
i2c_dir_in();
+#endif
+
/*
* now wait for ack
*/
/*
* check for ack
*/
- if(i2c_getbit())
+ if (i2c_getbit())
ack = 0;
i2c_delay(CLOCK_HIGH_TIME/2);
- if(!ack){
- if(!i2c_getbit()) /* receiver pulled SDA low */
+ if (!ack) {
+ if (!i2c_getbit()) /* receiver pulld SDA low */
ack = 1;
i2c_delay(CLOCK_HIGH_TIME/2);
}
* before we enable our output. If we keep data high
* and enable output, we would generate a stop condition.
*/
+#if 0
i2c_data(I2C_DATA_LOW);
/*
*/
i2c_enable();
i2c_dir_out();
+#endif
i2c_clk(I2C_CLOCK_LOW);
i2c_delay(CLOCK_HIGH_TIME/4);
/*
i2c_dir_in();
}
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: i2c_write
+*#
+*# DESCRIPTION : Writes a value to an I2C device
+*#
+*#--------------------------------------------------------------------------*/
+int
+i2c_write(unsigned char theSlave, void *data, size_t nbytes)
+{
+ int error, cntr = 3;
+ unsigned char bytes_wrote = 0;
+ unsigned char value;
+ unsigned long flags;
+
+ spin_lock_irqsave(&i2c_lock, flags);
+
+ do {
+ error = 0;
+
+ i2c_start();
+ /*
+ * send slave address
+ */
+ i2c_outbyte((theSlave & 0xfe));
+ /*
+ * wait for ack
+ */
+ if (!i2c_getack())
+ error = 1;
+ /*
+ * send data
+ */
+ for (bytes_wrote = 0; bytes_wrote < nbytes; bytes_wrote++) {
+ memcpy(&value, data + bytes_wrote, sizeof value);
+ i2c_outbyte(value);
+ /*
+ * now it's time to wait for ack
+ */
+ if (!i2c_getack())
+ error |= 4;
+ }
+ /*
+ * end byte stream
+ */
+ i2c_stop();
+
+ } while (error && cntr--);
+
+ i2c_delay(CLOCK_LOW_TIME);
+
+ spin_unlock_irqrestore(&i2c_lock, flags);
+
+ return -error;
+}
+
+/*#---------------------------------------------------------------------------
+*#
+*# FUNCTION NAME: i2c_read
+*#
+*# DESCRIPTION : Reads a value from an I2C device
+*#
+*#--------------------------------------------------------------------------*/
+int
+i2c_read(unsigned char theSlave, void *data, size_t nbytes)
+{
+ unsigned char b = 0;
+ unsigned char bytes_read = 0;
+ int error, cntr = 3;
+ unsigned long flags;
+
+ spin_lock_irqsave(&i2c_lock, flags);
+
+ do {
+ error = 0;
+ memset(data, 0, nbytes);
+ /*
+ * generate start condition
+ */
+ i2c_start();
+ /*
+ * send slave address
+ */
+ i2c_outbyte((theSlave | 0x01));
+ /*
+ * wait for ack
+ */
+ if (!i2c_getack())
+ error = 1;
+ /*
+ * fetch data
+ */
+ for (bytes_read = 0; bytes_read < nbytes; bytes_read++) {
+ b = i2c_inbyte();
+ memcpy(data + bytes_read, &b, sizeof b);
+
+ if (bytes_read < (nbytes - 1))
+ i2c_sendack();
+ }
+ /*
+ * last received byte needs to be nacked
+ * instead of acked
+ */
+ i2c_sendnack();
+ /*
+ * end sequence
+ */
+ i2c_stop();
+ } while (error && cntr--);
+
+ spin_unlock_irqrestore(&i2c_lock, flags);
+
+ return -error;
+}
+
/*#---------------------------------------------------------------------------
*#
*# FUNCTION NAME: i2c_writereg
int error, cntr = 3;
unsigned long flags;
+ spin_lock_irqsave(&i2c_lock, flags);
+
do {
error = 0;
- /*
- * we don't like to be interrupted
- */
- local_irq_save(flags);
i2c_start();
/*
* end byte stream
*/
i2c_stop();
- /*
- * enable interrupt again
- */
- local_irq_restore(flags);
-
} while(error && cntr--);
i2c_delay(CLOCK_LOW_TIME);
+ spin_unlock_irqrestore(&i2c_lock, flags);
+
return -error;
}
int error, cntr = 3;
unsigned long flags;
+ spin_lock_irqsave(&i2c_lock, flags);
+
do {
error = 0;
- /*
- * we don't like to be interrupted
- */
- local_irq_save(flags);
/*
* generate start condition
*/
* now it's time to wait for ack
*/
if(!i2c_getack())
- error = 1;
+ error |= 2;
/*
* repeat start condition
*/
* wait for ack
*/
if(!i2c_getack())
- error = 1;
+ error |= 4;
/*
* fetch register
*/
* end sequence
*/
i2c_stop();
- /*
- * enable interrupt again
- */
- local_irq_restore(flags);
} while(error && cntr--);
+ spin_unlock_irqrestore(&i2c_lock, flags);
+
return b;
}
unsigned int cmd, unsigned long arg)
{
if(_IOC_TYPE(cmd) != ETRAXI2C_IOCTYPE) {
- return -EINVAL;
+ return -ENOTTY;
}
switch (_IOC_NR(cmd)) {
.release = i2c_release,
};
-int __init
-i2c_init(void)
+static int __init i2c_init(void)
{
- int res;
+ static int res;
+ static int first = 1;
- /* Setup and enable the Port B I2C interface */
+ if (!first)
+ return res;
- crisv32_io_get_name(&cris_i2c_data, CONFIG_ETRAX_I2C_DATA_PORT);
- crisv32_io_get_name(&cris_i2c_clk, CONFIG_ETRAX_I2C_CLK_PORT);
+ first = 0;
+
+ /* Setup and enable the DATA and CLK pins */
+
+ res = crisv32_io_get_name(&cris_i2c_data,
+ CONFIG_ETRAX_V32_I2C_DATA_PORT);
+ if (res < 0)
+ return res;
+
+ res = crisv32_io_get_name(&cris_i2c_clk, CONFIG_ETRAX_V32_I2C_CLK_PORT);
+ crisv32_io_set_dir(&cris_i2c_clk, crisv32_io_dir_out);
+
+ return res;
+}
+
+
+static int __init i2c_register(void)
+{
+ int res;
+
+ res = i2c_init();
+ if (res < 0)
+ return res;
/* register char device */
res = register_chrdev(I2C_MAJOR, i2c_name, &i2c_fops);
- if(res < 0) {
+ if (res < 0) {
printk(KERN_ERR "i2c: couldn't get a major number.\n");
return res;
}
- printk(KERN_INFO "I2C driver v2.2, (c) 1999-2001 Axis Communications AB\n");
+ printk(KERN_INFO
+ "I2C driver v2.2, (c) 1999-2007 Axis Communications AB\n");
return 0;
}
-
/* this makes sure that i2c_init is called during boot */
-
-module_init(i2c_init);
+module_init(i2c_register);
/****************** END OF FILE i2c.c ********************************/
/* High level I2C actions */
int __init i2c_init(void);
+int i2c_write(unsigned char theSlave, void *data, size_t nbytes);
+int i2c_read(unsigned char theSlave, void *data, size_t nbytes);
int i2c_writereg(unsigned char theSlave, unsigned char theReg, unsigned char theValue);
unsigned char i2c_readreg(unsigned char theSlave, unsigned char theReg);
-/* $Id: iop_fw_load.c,v 1.4 2005/04/07 09:27:46 larsv Exp $
- *
+/*
* Firmware loader for ETRAX FS IO-Processor
*
* Copyright (C) 2004 Axis Communications AB
#include <linux/device.h>
#include <linux/firmware.h>
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/iop/iop_reg_space.h>
-#include <asm/arch/hwregs/iop/iop_mpu_macros.h>
-#include <asm/arch/hwregs/iop/iop_mpu_defs.h>
-#include <asm/arch/hwregs/iop/iop_spu_defs.h>
-#include <asm/arch/hwregs/iop/iop_sw_cpu_defs.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/iop/iop_reg_space.h>
+#include <hwregs/iop/iop_mpu_macros.h>
+#include <hwregs/iop/iop_mpu_defs.h>
+#include <hwregs/iop/iop_spu_defs.h>
+#include <hwregs/iop/iop_sw_cpu_defs.h>
#define IOP_TIMEOUT 100
--- /dev/null
+#
+# Makefile for Etrax-specific drivers
+#
+
+obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
+obj-$(CONFIG_ETRAX_GPIO) += gpio.o
--- /dev/null
+/*
+ * Artec-3 general port I/O device
+ *
+ * Copyright (c) 2007 Axis Communications AB
+ *
+ * Authors: Bjorn Wesen (initial version)
+ * Ola Knutsson (LED handling)
+ * Johan Adolfsson (read/set directions, write, port G,
+ * port to ETRAX FS.
+ * Ricard Wanderlof (PWM for Artpec-3)
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/ioport.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/poll.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+
+#include <asm/etraxgpio.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/gio_defs.h>
+#include <hwregs/intr_vect_defs.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <asm/arch/mach/pinmux.h>
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+#include "../i2c.h"
+
+#define VIRT_I2C_ADDR 0x40
+#endif
+
+/* The following gio ports on ARTPEC-3 is available:
+ * pa 32 bits
+ * pb 32 bits
+ * pc 16 bits
+ * each port has a rw_px_dout, r_px_din and rw_px_oe register.
+ */
+
+#define GPIO_MAJOR 120 /* experimental MAJOR number */
+
+#define I2C_INTERRUPT_BITS 0x300 /* i2c0_done and i2c1_done bits */
+
+#define D(x)
+
+#if 0
+static int dp_cnt;
+#define DP(x) \
+ do { \
+ dp_cnt++; \
+ if (dp_cnt % 1000 == 0) \
+ x; \
+ } while (0)
+#else
+#define DP(x)
+#endif
+
+static char gpio_name[] = "etrax gpio";
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
+ unsigned long arg);
+#endif
+static int gpio_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg);
+static ssize_t gpio_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *off);
+static int gpio_open(struct inode *inode, struct file *filp);
+static int gpio_release(struct inode *inode, struct file *filp);
+static unsigned int gpio_poll(struct file *filp,
+ struct poll_table_struct *wait);
+
+/* private data per open() of this driver */
+
+struct gpio_private {
+ struct gpio_private *next;
+ /* The IO_CFG_WRITE_MODE_VALUE only support 8 bits: */
+ unsigned char clk_mask;
+ unsigned char data_mask;
+ unsigned char write_msb;
+ unsigned char pad1;
+ /* These fields are generic */
+ unsigned long highalarm, lowalarm;
+ wait_queue_head_t alarm_wq;
+ int minor;
+};
+
+static void gpio_set_alarm(struct gpio_private *priv);
+static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg);
+static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd,
+ unsigned long arg);
+
+
+/* linked list of alarms to check for */
+
+static struct gpio_private *alarmlist;
+
+static int wanted_interrupts;
+
+static DEFINE_SPINLOCK(gpio_lock);
+
+#define NUM_PORTS (GPIO_MINOR_LAST+1)
+#define GIO_REG_RD_ADDR(reg) \
+ (unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
+#define GIO_REG_WR_ADDR(reg) \
+ (unsigned long *)(regi_gio + REG_WR_ADDR_gio_##reg)
+static unsigned long led_dummy;
+static unsigned long port_d_dummy; /* Only input on Artpec-3 */
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static unsigned long port_e_dummy; /* Non existent on Artpec-3 */
+static unsigned long virtual_dummy;
+static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
+static unsigned short cached_virtual_gpio_read;
+#endif
+
+static unsigned long *data_out[NUM_PORTS] = {
+ GIO_REG_WR_ADDR(rw_pa_dout),
+ GIO_REG_WR_ADDR(rw_pb_dout),
+ &led_dummy,
+ GIO_REG_WR_ADDR(rw_pc_dout),
+ &port_d_dummy,
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ &port_e_dummy,
+ &virtual_dummy,
+#endif
+};
+
+static unsigned long *data_in[NUM_PORTS] = {
+ GIO_REG_RD_ADDR(r_pa_din),
+ GIO_REG_RD_ADDR(r_pb_din),
+ &led_dummy,
+ GIO_REG_RD_ADDR(r_pc_din),
+ GIO_REG_RD_ADDR(r_pd_din),
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ &port_e_dummy,
+ &virtual_dummy,
+#endif
+};
+
+static unsigned long changeable_dir[NUM_PORTS] = {
+ CONFIG_ETRAX_PA_CHANGEABLE_DIR,
+ CONFIG_ETRAX_PB_CHANGEABLE_DIR,
+ 0,
+ CONFIG_ETRAX_PC_CHANGEABLE_DIR,
+ 0,
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ 0,
+ CONFIG_ETRAX_PV_CHANGEABLE_DIR,
+#endif
+};
+
+static unsigned long changeable_bits[NUM_PORTS] = {
+ CONFIG_ETRAX_PA_CHANGEABLE_BITS,
+ CONFIG_ETRAX_PB_CHANGEABLE_BITS,
+ 0,
+ CONFIG_ETRAX_PC_CHANGEABLE_BITS,
+ 0,
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ 0,
+ CONFIG_ETRAX_PV_CHANGEABLE_BITS,
+#endif
+};
+
+static unsigned long *dir_oe[NUM_PORTS] = {
+ GIO_REG_WR_ADDR(rw_pa_oe),
+ GIO_REG_WR_ADDR(rw_pb_oe),
+ &led_dummy,
+ GIO_REG_WR_ADDR(rw_pc_oe),
+ &port_d_dummy,
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ &port_e_dummy,
+ &virtual_rw_pv_oe,
+#endif
+};
+
+static void gpio_set_alarm(struct gpio_private *priv)
+{
+ int bit;
+ int intr_cfg;
+ int mask;
+ int pins;
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+ intr_cfg = REG_RD_INT(gio, regi_gio, rw_intr_cfg);
+ pins = REG_RD_INT(gio, regi_gio, rw_intr_pins);
+ mask = REG_RD_INT(gio, regi_gio, rw_intr_mask) & I2C_INTERRUPT_BITS;
+
+ for (bit = 0; bit < 32; bit++) {
+ int intr = bit % 8;
+ int pin = bit / 8;
+ if (priv->minor < GPIO_MINOR_LEDS)
+ pin += priv->minor * 4;
+ else
+ pin += (priv->minor - 1) * 4;
+
+ if (priv->highalarm & (1<<bit)) {
+ intr_cfg |= (regk_gio_hi << (intr * 3));
+ mask |= 1 << intr;
+ wanted_interrupts = mask & 0xff;
+ pins |= pin << (intr * 4);
+ } else if (priv->lowalarm & (1<<bit)) {
+ intr_cfg |= (regk_gio_lo << (intr * 3));
+ mask |= 1 << intr;
+ wanted_interrupts = mask & 0xff;
+ pins |= pin << (intr * 4);
+ }
+ }
+
+ REG_WR_INT(gio, regi_gio, rw_intr_cfg, intr_cfg);
+ REG_WR_INT(gio, regi_gio, rw_intr_pins, pins);
+ REG_WR_INT(gio, regi_gio, rw_intr_mask, mask);
+
+ spin_unlock_irqrestore(&gpio_lock, flags);
+}
+
+static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait)
+{
+ unsigned int mask = 0;
+ struct gpio_private *priv = file->private_data;
+ unsigned long data;
+ unsigned long tmp;
+
+ if (priv->minor >= GPIO_MINOR_PWM0 &&
+ priv->minor <= GPIO_MINOR_LAST_PWM)
+ return 0;
+
+ poll_wait(file, &priv->alarm_wq, wait);
+ if (priv->minor <= GPIO_MINOR_D) {
+ data = readl(data_in[priv->minor]);
+ REG_WR_INT(gio, regi_gio, rw_ack_intr, wanted_interrupts);
+ tmp = REG_RD_INT(gio, regi_gio, rw_intr_mask);
+ tmp &= I2C_INTERRUPT_BITS;
+ tmp |= wanted_interrupts;
+ REG_WR_INT(gio, regi_gio, rw_intr_mask, tmp);
+ } else
+ return 0;
+
+ if ((data & priv->highalarm) || (~data & priv->lowalarm))
+ mask = POLLIN|POLLRDNORM;
+
+ DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
+ return mask;
+}
+
+static irqreturn_t gpio_interrupt(int irq, void *dev_id)
+{
+ reg_gio_rw_intr_mask intr_mask;
+ reg_gio_r_masked_intr masked_intr;
+ reg_gio_rw_ack_intr ack_intr;
+ unsigned long flags;
+ unsigned long tmp;
+ unsigned long tmp2;
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ unsigned char enable_gpiov_ack = 0;
+#endif
+
+ /* Find what PA interrupts are active */
+ masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
+ tmp = REG_TYPE_CONV(unsigned long, reg_gio_r_masked_intr, masked_intr);
+
+ /* Find those that we have enabled */
+ spin_lock_irqsave(&gpio_lock, flags);
+ tmp &= wanted_interrupts;
+ spin_unlock_irqrestore(&gpio_lock, flags);
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ /* Something changed on virtual GPIO. Interrupt is acked by
+ * reading the device.
+ */
+ if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
+ i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
+ sizeof(cached_virtual_gpio_read));
+ enable_gpiov_ack = 1;
+ }
+#endif
+
+ /* Ack them */
+ ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
+ REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
+
+ /* Disable those interrupts.. */
+ intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
+ tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
+ tmp2 &= ~tmp;
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ /* Do not disable interrupt on virtual GPIO. Changes on virtual
+ * pins are only noticed by an interrupt.
+ */
+ if (enable_gpiov_ack)
+ tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
+#endif
+ intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
+ REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
+
+ return IRQ_RETVAL(tmp);
+}
+
+static void gpio_write_bit(unsigned long *port, unsigned char data, int bit,
+ unsigned char clk_mask, unsigned char data_mask)
+{
+ unsigned long shadow = readl(port) & ~clk_mask;
+ writel(shadow, port);
+ if (data & 1 << bit)
+ shadow |= data_mask;
+ else
+ shadow &= ~data_mask;
+ writel(shadow, port);
+ /* For FPGA: min 5.0ns (DCC) before CCLK high */
+ shadow |= clk_mask;
+ writel(shadow, port);
+}
+
+static void gpio_write_byte(struct gpio_private *priv, unsigned long *port,
+ unsigned char data)
+{
+ int i;
+
+ if (priv->write_msb)
+ for (i = 7; i >= 0; i--)
+ gpio_write_bit(port, data, i, priv->clk_mask,
+ priv->data_mask);
+ else
+ for (i = 0; i <= 7; i++)
+ gpio_write_bit(port, data, i, priv->clk_mask,
+ priv->data_mask);
+}
+
+
+static ssize_t gpio_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *off)
+{
+ struct gpio_private *priv = file->private_data;
+ unsigned long flags;
+ ssize_t retval = count;
+ /* Only bits 0-7 may be used for write operations but allow all
+ devices except leds... */
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ if (priv->minor == GPIO_MINOR_V)
+ return -EFAULT;
+#endif
+ if (priv->minor == GPIO_MINOR_LEDS)
+ return -EFAULT;
+
+ if (priv->minor >= GPIO_MINOR_PWM0 &&
+ priv->minor <= GPIO_MINOR_LAST_PWM)
+ return -EFAULT;
+
+ if (!access_ok(VERIFY_READ, buf, count))
+ return -EFAULT;
+
+ /* It must have been configured using the IO_CFG_WRITE_MODE */
+ /* Perhaps a better error code? */
+ if (priv->clk_mask == 0 || priv->data_mask == 0)
+ return -EPERM;
+
+ D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
+ "msb: %i\n",
+ count, priv->data_mask, priv->clk_mask, priv->write_msb));
+
+ spin_lock_irqsave(&gpio_lock, flags);
+
+ while (count--)
+ gpio_write_byte(priv, data_out[priv->minor], *buf++);
+
+ spin_unlock_irqrestore(&gpio_lock, flags);
+ return retval;
+}
+
+static int gpio_open(struct inode *inode, struct file *filp)
+{
+ struct gpio_private *priv;
+ int p = iminor(inode);
+
+ if (p > GPIO_MINOR_LAST_PWM ||
+ (p > GPIO_MINOR_LAST && p < GPIO_MINOR_PWM0))
+ return -EINVAL;
+
+ priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
+
+ if (!priv)
+ return -ENOMEM;
+ memset(priv, 0, sizeof(*priv));
+
+ priv->minor = p;
+ filp->private_data = priv;
+
+ /* initialize the io/alarm struct, not for PWM ports though */
+ if (p <= GPIO_MINOR_LAST) {
+
+ priv->clk_mask = 0;
+ priv->data_mask = 0;
+ priv->highalarm = 0;
+ priv->lowalarm = 0;
+
+ init_waitqueue_head(&priv->alarm_wq);
+
+ /* link it into our alarmlist */
+ spin_lock_irq(&gpio_lock);
+ priv->next = alarmlist;
+ alarmlist = priv;
+ spin_unlock_irq(&gpio_lock);
+ }
+
+ return 0;
+}
+
+static int gpio_release(struct inode *inode, struct file *filp)
+{
+ struct gpio_private *p;
+ struct gpio_private *todel;
+ /* local copies while updating them: */
+ unsigned long a_high, a_low;
+
+ /* prepare to free private structure */
+ todel = filp->private_data;
+
+ /* unlink from alarmlist - only for non-PWM ports though */
+ if (todel->minor <= GPIO_MINOR_LAST) {
+ spin_lock_irq(&gpio_lock);
+ p = alarmlist;
+
+ if (p == todel)
+ alarmlist = todel->next;
+ else {
+ while (p->next != todel)
+ p = p->next;
+ p->next = todel->next;
+ }
+
+ /* Check if there are still any alarms set */
+ p = alarmlist;
+ a_high = 0;
+ a_low = 0;
+ while (p) {
+ if (p->minor == GPIO_MINOR_A) {
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
+#endif
+ a_high |= p->highalarm;
+ a_low |= p->lowalarm;
+ }
+
+ p = p->next;
+ }
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ /* Variable 'a_low' needs to be set here again
+ * to ensure that interrupt for virtual GPIO is handled.
+ */
+ a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
+#endif
+
+ spin_unlock_irq(&gpio_lock);
+ }
+ kfree(todel);
+
+ return 0;
+}
+
+/* Main device API. ioctl's to read/set/clear bits, as well as to
+ * set alarms to wait for using a subsequent select().
+ */
+
+inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
+{
+ /* Set direction 0=unchanged 1=input,
+ * return mask with 1=input
+ */
+ unsigned long flags;
+ unsigned long dir_shadow;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+
+ dir_shadow = readl(dir_oe[priv->minor]) &
+ ~(arg & changeable_dir[priv->minor]);
+ writel(dir_shadow, dir_oe[priv->minor]);
+
+ spin_unlock_irqrestore(&gpio_lock, flags);
+
+ if (priv->minor == GPIO_MINOR_C)
+ dir_shadow ^= 0xFFFF; /* Only 16 bits */
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ else if (priv->minor == GPIO_MINOR_V)
+ dir_shadow ^= 0xFFFF; /* Only 16 bits */
+#endif
+ else
+ dir_shadow ^= 0xFFFFFFFF; /* PA, PB and PD 32 bits */
+
+ return dir_shadow;
+
+} /* setget_input */
+
+static inline unsigned long setget_output(struct gpio_private *priv,
+ unsigned long arg)
+{
+ unsigned long flags;
+ unsigned long dir_shadow;
+
+ spin_lock_irqsave(&gpio_lock, flags);
+
+ dir_shadow = readl(dir_oe[priv->minor]) |
+ (arg & changeable_dir[priv->minor]);
+ writel(dir_shadow, dir_oe[priv->minor]);
+
+ spin_unlock_irqrestore(&gpio_lock, flags);
+ return dir_shadow;
+} /* setget_output */
+
+static int gpio_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ unsigned long flags;
+ unsigned long val;
+ unsigned long shadow;
+ struct gpio_private *priv = file->private_data;
+
+ if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
+ return -ENOTTY;
+
+ /* Check for special ioctl handlers first */
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ if (priv->minor == GPIO_MINOR_V)
+ return virtual_gpio_ioctl(file, cmd, arg);
+#endif
+
+ if (priv->minor == GPIO_MINOR_LEDS)
+ return gpio_leds_ioctl(cmd, arg);
+
+ if (priv->minor >= GPIO_MINOR_PWM0 &&
+ priv->minor <= GPIO_MINOR_LAST_PWM)
+ return gpio_pwm_ioctl(priv, cmd, arg);
+
+ switch (_IOC_NR(cmd)) {
+ case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
+ /* Read the port. */
+ return readl(data_in[priv->minor]);
+ case IO_SETBITS:
+ spin_lock_irqsave(&gpio_lock, flags);
+ /* Set changeable bits with a 1 in arg. */
+ shadow = readl(data_out[priv->minor]) |
+ (arg & changeable_bits[priv->minor]);
+ writel(shadow, data_out[priv->minor]);
+ spin_unlock_irqrestore(&gpio_lock, flags);
+ break;
+ case IO_CLRBITS:
+ spin_lock_irqsave(&gpio_lock, flags);
+ /* Clear changeable bits with a 1 in arg. */
+ shadow = readl(data_out[priv->minor]) &
+ ~(arg & changeable_bits[priv->minor]);
+ writel(shadow, data_out[priv->minor]);
+ spin_unlock_irqrestore(&gpio_lock, flags);
+ break;
+ case IO_HIGHALARM:
+ /* Set alarm when bits with 1 in arg go high. */
+ priv->highalarm |= arg;
+ gpio_set_alarm(priv);
+ break;
+ case IO_LOWALARM:
+ /* Set alarm when bits with 1 in arg go low. */
+ priv->lowalarm |= arg;
+ gpio_set_alarm(priv);
+ break;
+ case IO_CLRALARM:
+ /* Clear alarm for bits with 1 in arg. */
+ priv->highalarm &= ~arg;
+ priv->lowalarm &= ~arg;
+ gpio_set_alarm(priv);
+ break;
+ case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
+ /* Read direction 0=input 1=output */
+ return readl(dir_oe[priv->minor]);
+
+ case IO_SETINPUT: /* Use IO_SETGET_INPUT instead! */
+ /* Set direction 0=unchanged 1=input,
+ * return mask with 1=input
+ */
+ return setget_input(priv, arg);
+
+ case IO_SETOUTPUT: /* Use IO_SETGET_OUTPUT instead! */
+ /* Set direction 0=unchanged 1=output,
+ * return mask with 1=output
+ */
+ return setget_output(priv, arg);
+
+ case IO_CFG_WRITE_MODE:
+ {
+ int res = -EPERM;
+ unsigned long dir_shadow, clk_mask, data_mask, write_msb;
+
+ clk_mask = arg & 0xFF;
+ data_mask = (arg >> 8) & 0xFF;
+ write_msb = (arg >> 16) & 0x01;
+
+ /* Check if we're allowed to change the bits and
+ * the direction is correct
+ */
+ spin_lock_irqsave(&gpio_lock, flags);
+ dir_shadow = readl(dir_oe[priv->minor]);
+ if ((clk_mask & changeable_bits[priv->minor]) &&
+ (data_mask & changeable_bits[priv->minor]) &&
+ (clk_mask & dir_shadow) &&
+ (data_mask & dir_shadow)) {
+ priv->clk_mask = clk_mask;
+ priv->data_mask = data_mask;
+ priv->write_msb = write_msb;
+ res = 0;
+ }
+ spin_unlock_irqrestore(&gpio_lock, flags);
+
+ return res;
+ }
+ case IO_READ_INBITS:
+ /* *arg is result of reading the input pins */
+ val = readl(data_in[priv->minor]);
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ return 0;
+ case IO_READ_OUTBITS:
+ /* *arg is result of reading the output shadow */
+ val = *data_out[priv->minor];
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ case IO_SETGET_INPUT:
+ /* bits set in *arg is set to input,
+ * *arg updated with current input pins.
+ */
+ if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
+ return -EFAULT;
+ val = setget_input(priv, val);
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ case IO_SETGET_OUTPUT:
+ /* bits set in *arg is set to output,
+ * *arg updated with current output pins.
+ */
+ if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
+ return -EFAULT;
+ val = setget_output(priv, val);
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ default:
+ return -EINVAL;
+ } /* switch */
+
+ return 0;
+}
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
+ unsigned long arg)
+{
+ unsigned long flags;
+ unsigned short val;
+ unsigned short shadow;
+ struct gpio_private *priv = file->private_data;
+
+ switch (_IOC_NR(cmd)) {
+ case IO_SETBITS:
+ spin_lock_irqsave(&gpio_lock, flags);
+ /* Set changeable bits with a 1 in arg. */
+ i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ shadow |= ~readl(dir_oe[priv->minor]) |
+ (arg & changeable_bits[priv->minor]);
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ spin_lock_irqrestore(&gpio_lock, flags);
+ break;
+ case IO_CLRBITS:
+ spin_lock_irqsave(&gpio_lock, flags);
+ /* Clear changeable bits with a 1 in arg. */
+ i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ shadow |= ~readl(dir_oe[priv->minor]) &
+ ~(arg & changeable_bits[priv->minor]);
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ spin_lock_irqrestore(&gpio_lock, flags);
+ break;
+ case IO_HIGHALARM:
+ /* Set alarm when bits with 1 in arg go high. */
+ priv->highalarm |= arg;
+ break;
+ case IO_LOWALARM:
+ /* Set alarm when bits with 1 in arg go low. */
+ priv->lowalarm |= arg;
+ break;
+ case IO_CLRALARM:
+ /* Clear alarm for bits with 1 in arg. */
+ priv->highalarm &= ~arg;
+ priv->lowalarm &= ~arg;
+ break;
+ case IO_CFG_WRITE_MODE:
+ {
+ unsigned long dir_shadow;
+ dir_shadow = readl(dir_oe[priv->minor]);
+
+ priv->clk_mask = arg & 0xFF;
+ priv->data_mask = (arg >> 8) & 0xFF;
+ priv->write_msb = (arg >> 16) & 0x01;
+ /* Check if we're allowed to change the bits and
+ * the direction is correct
+ */
+ if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
+ (priv->data_mask & changeable_bits[priv->minor]) &&
+ (priv->clk_mask & dir_shadow) &&
+ (priv->data_mask & dir_shadow))) {
+ priv->clk_mask = 0;
+ priv->data_mask = 0;
+ return -EPERM;
+ }
+ break;
+ }
+ case IO_READ_INBITS:
+ /* *arg is result of reading the input pins */
+ val = cached_virtual_gpio_read & ~readl(dir_oe[priv->minor]);
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ return 0;
+
+ case IO_READ_OUTBITS:
+ /* *arg is result of reading the output shadow */
+ i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
+ val &= readl(dir_oe[priv->minor]);
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ case IO_SETGET_INPUT:
+ {
+ /* bits set in *arg is set to input,
+ * *arg updated with current input pins.
+ */
+ unsigned short input_mask = ~readl(dir_oe[priv->minor]);
+ if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
+ return -EFAULT;
+ val = setget_input(priv, val);
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ if ((input_mask & val) != input_mask) {
+ /* Input pins changed. All ports desired as input
+ * should be set to logic 1.
+ */
+ unsigned short change = input_mask ^ val;
+ i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
+ sizeof(shadow));
+ shadow &= ~change;
+ shadow |= val;
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
+ sizeof(shadow));
+ }
+ break;
+ }
+ case IO_SETGET_OUTPUT:
+ /* bits set in *arg is set to output,
+ * *arg updated with current output pins.
+ */
+ if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
+ return -EFAULT;
+ val = setget_output(priv, val);
+ if (copy_to_user((void __user *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ default:
+ return -EINVAL;
+ } /* switch */
+ return 0;
+}
+#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
+
+static int gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
+{
+ unsigned char green;
+ unsigned char red;
+
+ switch (_IOC_NR(cmd)) {
+ case IO_LEDACTIVE_SET:
+ green = ((unsigned char) arg) & 1;
+ red = (((unsigned char) arg) >> 1) & 1;
+ CRIS_LED_ACTIVE_SET_G(green);
+ CRIS_LED_ACTIVE_SET_R(red);
+ break;
+
+ default:
+ return -EINVAL;
+ } /* switch */
+
+ return 0;
+}
+
+static int gpio_pwm_set_mode(unsigned long arg, int pwm_port)
+{
+ int pinmux_pwm = pinmux_pwm0 + pwm_port;
+ int mode;
+ reg_gio_rw_pwm0_ctrl rw_pwm_ctrl = {
+ .ccd_val = 0,
+ .ccd_override = regk_gio_no,
+ .mode = regk_gio_no
+ };
+ int allocstatus;
+
+ if (get_user(mode, &((struct io_pwm_set_mode *) arg)->mode))
+ return -EFAULT;
+ rw_pwm_ctrl.mode = mode;
+ if (mode != PWM_OFF)
+ allocstatus = crisv32_pinmux_alloc_fixed(pinmux_pwm);
+ else
+ allocstatus = crisv32_pinmux_dealloc_fixed(pinmux_pwm);
+ if (allocstatus)
+ return allocstatus;
+ REG_WRITE(reg_gio_rw_pwm0_ctrl, REG_ADDR(gio, regi_gio, rw_pwm0_ctrl) +
+ 12 * pwm_port, rw_pwm_ctrl);
+ return 0;
+}
+
+static int gpio_pwm_set_period(unsigned long arg, int pwm_port)
+{
+ struct io_pwm_set_period periods;
+ reg_gio_rw_pwm0_var rw_pwm_widths;
+
+ if (copy_from_user(&periods, (void __user *)arg, sizeof(periods)))
+ return -EFAULT;
+ if (periods.lo > 8191 || periods.hi > 8191)
+ return -EINVAL;
+ rw_pwm_widths.lo = periods.lo;
+ rw_pwm_widths.hi = periods.hi;
+ REG_WRITE(reg_gio_rw_pwm0_var, REG_ADDR(gio, regi_gio, rw_pwm0_var) +
+ 12 * pwm_port, rw_pwm_widths);
+ return 0;
+}
+
+static int gpio_pwm_set_duty(unsigned long arg, int pwm_port)
+{
+ unsigned int duty;
+ reg_gio_rw_pwm0_data rw_pwm_duty;
+
+ if (get_user(duty, &((struct io_pwm_set_duty *) arg)->duty))
+ return -EFAULT;
+ if (duty > 255)
+ return -EINVAL;
+ rw_pwm_duty.data = duty;
+ REG_WRITE(reg_gio_rw_pwm0_data, REG_ADDR(gio, regi_gio, rw_pwm0_data) +
+ 12 * pwm_port, rw_pwm_duty);
+ return 0;
+}
+
+static int gpio_pwm_ioctl(struct gpio_private *priv, unsigned int cmd,
+ unsigned long arg)
+{
+ int pwm_port = priv->minor - GPIO_MINOR_PWM0;
+
+ switch (_IOC_NR(cmd)) {
+ case IO_PWM_SET_MODE:
+ return gpio_pwm_set_mode(arg, pwm_port);
+ case IO_PWM_SET_PERIOD:
+ return gpio_pwm_set_period(arg, pwm_port);
+ case IO_PWM_SET_DUTY:
+ return gpio_pwm_set_duty(arg, pwm_port);
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static const struct file_operations gpio_fops = {
+ .owner = THIS_MODULE,
+ .poll = gpio_poll,
+ .ioctl = gpio_ioctl,
+ .write = gpio_write,
+ .open = gpio_open,
+ .release = gpio_release,
+};
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static void __init virtual_gpio_init(void)
+{
+ reg_gio_rw_intr_cfg intr_cfg;
+ reg_gio_rw_intr_mask intr_mask;
+ unsigned short shadow;
+
+ shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
+ shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+
+ /* Set interrupt mask and on what state the interrupt shall trigger.
+ * For virtual gpio the interrupt shall trigger on logic '0'.
+ */
+ intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
+ intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
+
+ switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
+ case 0:
+ intr_cfg.pa0 = regk_gio_lo;
+ intr_mask.pa0 = regk_gio_yes;
+ break;
+ case 1:
+ intr_cfg.pa1 = regk_gio_lo;
+ intr_mask.pa1 = regk_gio_yes;
+ break;
+ case 2:
+ intr_cfg.pa2 = regk_gio_lo;
+ intr_mask.pa2 = regk_gio_yes;
+ break;
+ case 3:
+ intr_cfg.pa3 = regk_gio_lo;
+ intr_mask.pa3 = regk_gio_yes;
+ break;
+ case 4:
+ intr_cfg.pa4 = regk_gio_lo;
+ intr_mask.pa4 = regk_gio_yes;
+ break;
+ case 5:
+ intr_cfg.pa5 = regk_gio_lo;
+ intr_mask.pa5 = regk_gio_yes;
+ break;
+ case 6:
+ intr_cfg.pa6 = regk_gio_lo;
+ intr_mask.pa6 = regk_gio_yes;
+ break;
+ case 7:
+ intr_cfg.pa7 = regk_gio_lo;
+ intr_mask.pa7 = regk_gio_yes;
+ break;
+ }
+
+ REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
+ REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
+}
+#endif
+
+/* main driver initialization routine, called from mem.c */
+
+static int __init gpio_init(void)
+{
+ int res;
+
+ printk(KERN_INFO "ETRAX FS GPIO driver v2.7, (c) 2003-2008 "
+ "Axis Communications AB\n");
+
+ /* do the formalities */
+
+ res = register_chrdev(GPIO_MAJOR, gpio_name, &gpio_fops);
+ if (res < 0) {
+ printk(KERN_ERR "gpio: couldn't get a major number.\n");
+ return res;
+ }
+
+ /* Clear all leds */
+ CRIS_LED_NETWORK_GRP0_SET(0);
+ CRIS_LED_NETWORK_GRP1_SET(0);
+ CRIS_LED_ACTIVE_SET(0);
+ CRIS_LED_DISK_READ(0);
+ CRIS_LED_DISK_WRITE(0);
+
+ int res2 = request_irq(GIO_INTR_VECT, gpio_interrupt,
+ IRQF_SHARED | IRQF_DISABLED, "gpio", &alarmlist);
+ if (res2) {
+ printk(KERN_ERR "err: irq for gpio\n");
+ return res2;
+ }
+
+ /* No IRQs by default. */
+ REG_WR_INT(gio, regi_gio, rw_intr_pins, 0);
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ virtual_gpio_init();
+#endif
+
+ return res;
+}
+
+/* this makes sure that gpio_init is called during kernel boot */
+
+module_init(gpio_init);
--- /dev/null
+/*
+ * arch/cris/arch-v32/drivers/nandflash.c
+ *
+ * Copyright (c) 2007
+ *
+ * Derived from drivers/mtd/nand/spia.c
+ * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/memmap.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/pio_defs.h>
+#include <pinmux.h>
+#include <asm/io.h>
+
+#define MANUAL_ALE_CLE_CONTROL 1
+
+#define regf_ALE a0
+#define regf_CLE a1
+#define regf_NCE ce0_n
+
+#define CLE_BIT 10
+#define ALE_BIT 11
+#define CE_BIT 12
+
+struct mtd_info_wrapper {
+ struct mtd_info info;
+ struct nand_chip chip;
+};
+
+/* Bitmask for control pins */
+#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
+
+static struct mtd_info *crisv32_mtd;
+/*
+ * hardware specific access to control-lines
+ */
+static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
+{
+ unsigned long flags;
+ reg_pio_rw_dout dout;
+ struct nand_chip *this = mtd->priv;
+
+ local_irq_save(flags);
+
+ /* control bits change */
+ if (ctrl & NAND_CTRL_CHANGE) {
+ dout = REG_RD(pio, regi_pio, rw_dout);
+ dout.regf_NCE = (ctrl & NAND_NCE) ? 0 : 1;
+
+#if !MANUAL_ALE_CLE_CONTROL
+ if (ctrl & NAND_ALE) {
+ /* A0 = ALE high */
+ this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
+ regi_pio, rw_io_access1);
+ } else if (ctrl & NAND_CLE) {
+ /* A1 = CLE high */
+ this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
+ regi_pio, rw_io_access2);
+ } else {
+ /* A1 = CLE and A0 = ALE low */
+ this->IO_ADDR_W = (void __iomem *)REG_ADDR(pio,
+ regi_pio, rw_io_access0);
+ }
+#else
+
+ dout.regf_CLE = (ctrl & NAND_CLE) ? 1 : 0;
+ dout.regf_ALE = (ctrl & NAND_ALE) ? 1 : 0;
+#endif
+ REG_WR(pio, regi_pio, rw_dout, dout);
+ }
+
+ /* command to chip */
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+
+ local_irq_restore(flags);
+}
+
+/*
+* read device ready pin
+*/
+static int crisv32_device_ready(struct mtd_info *mtd)
+{
+ reg_pio_r_din din = REG_RD(pio, regi_pio, r_din);
+ return din.rdy;
+}
+
+/*
+ * Main initialization routine
+ */
+struct mtd_info *__init crisv32_nand_flash_probe(void)
+{
+ void __iomem *read_cs;
+ void __iomem *write_cs;
+
+ struct mtd_info_wrapper *wrapper;
+ struct nand_chip *this;
+ int err = 0;
+
+ reg_pio_rw_man_ctrl man_ctrl = {
+ .regf_NCE = regk_pio_yes,
+#if MANUAL_ALE_CLE_CONTROL
+ .regf_ALE = regk_pio_yes,
+ .regf_CLE = regk_pio_yes
+#endif
+ };
+ reg_pio_rw_oe oe = {
+ .regf_NCE = regk_pio_yes,
+#if MANUAL_ALE_CLE_CONTROL
+ .regf_ALE = regk_pio_yes,
+ .regf_CLE = regk_pio_yes
+#endif
+ };
+ reg_pio_rw_dout dout = { .regf_NCE = 1 };
+
+ /* Allocate pio pins to pio */
+ crisv32_pinmux_alloc_fixed(pinmux_pio);
+ /* Set up CE, ALE, CLE (ce0_n, a0, a1) for manual control and output */
+ REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl);
+ REG_WR(pio, regi_pio, rw_dout, dout);
+ REG_WR(pio, regi_pio, rw_oe, oe);
+
+ /* Allocate memory for MTD device structure and private data */
+ wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL);
+ if (!wrapper) {
+ printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
+ "device structure.\n");
+ err = -ENOMEM;
+ return NULL;
+ }
+
+ read_cs = write_cs = (void __iomem *)REG_ADDR(pio, regi_pio,
+ rw_io_access0);
+
+ /* Get pointer to private data */
+ this = &wrapper->chip;
+ crisv32_mtd = &wrapper->info;
+
+ /* Link the private data with the MTD structure */
+ crisv32_mtd->priv = this;
+
+ /* Set address of NAND IO lines */
+ this->IO_ADDR_R = read_cs;
+ this->IO_ADDR_W = write_cs;
+ this->cmd_ctrl = crisv32_hwcontrol;
+ this->dev_ready = crisv32_device_ready;
+ /* 20 us command delay time */
+ this->chip_delay = 20;
+ this->ecc.mode = NAND_ECC_SOFT;
+
+ /* Enable the following for a flash based bad block table */
+ /* this->options = NAND_USE_FLASH_BBT; */
+
+ /* Scan to find existance of the device */
+ if (nand_scan(crisv32_mtd, 1)) {
+ err = -ENXIO;
+ goto out_mtd;
+ }
+
+ return crisv32_mtd;
+
+out_mtd:
+ kfree(wrapper);
+ return NULL;
+}
+
--- /dev/null
+#
+# Makefile for Etrax-specific drivers
+#
+
+obj-$(CONFIG_ETRAX_NANDFLASH) += nandflash.o
+obj-$(CONFIG_ETRAX_GPIO) += gpio.o
-/* $Id: gpio.c,v 1.16 2005/06/19 17:06:49 starvik Exp $
- *
+/*
* ETRAX CRISv32 general port I/O device
*
- * Copyright (c) 1999, 2000, 2001, 2002, 2003 Axis Communications AB
+ * Copyright (c) 1999-2006 Axis Communications AB
*
* Authors: Bjorn Wesen (initial version)
* Ola Knutsson (LED handling)
* Johan Adolfsson (read/set directions, write, port G,
* port to ETRAX FS.
*
- * $Log: gpio.c,v $
- * Revision 1.16 2005/06/19 17:06:49 starvik
- * Merge of Linux 2.6.12.
- *
- * Revision 1.15 2005/05/25 08:22:20 starvik
- * Changed GPIO port order to fit packages/devices/axis-2.4.
- *
- * Revision 1.14 2005/04/24 18:35:08 starvik
- * Updated with final register headers.
- *
- * Revision 1.13 2005/03/15 15:43:00 starvik
- * dev_id needs to be supplied for shared IRQs.
- *
- * Revision 1.12 2005/03/10 17:12:00 starvik
- * Protect alarm list with spinlock.
- *
- * Revision 1.11 2005/01/05 06:08:59 starvik
- * No need to do local_irq_disable after local_irq_save.
- *
- * Revision 1.10 2004/11/19 08:38:31 starvik
- * Removed old crap.
- *
- * Revision 1.9 2004/05/14 07:58:02 starvik
- * Merge of changes from 2.4
- *
- * Revision 1.8 2003/09/11 07:29:50 starvik
- * Merge of Linux 2.6.0-test5
- *
- * Revision 1.7 2003/07/10 13:25:46 starvik
- * Compiles for 2.5.74
- * Lindented ethernet.c
- *
- * Revision 1.6 2003/07/04 08:27:46 starvik
- * Merge of Linux 2.5.74
- *
- * Revision 1.5 2003/06/10 08:26:37 johana
- * Etrax -> ETRAX CRISv32
- *
- * Revision 1.4 2003/06/05 14:22:48 johana
- * Initialise some_alarms.
- *
- * Revision 1.3 2003/06/05 10:15:46 johana
- * New INTR_VECT macros.
- * Enable interrupts in global config.
- *
- * Revision 1.2 2003/06/03 15:52:50 johana
- * Initial CRIS v32 version.
- *
- * Revision 1.1 2003/06/03 08:53:15 johana
- * Copy of os/lx25/arch/cris/arch-v10/drivers/gpio.c version 1.7.
- *
*/
-
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <asm/etraxgpio.h>
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/gio_defs.h>
-#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/gio_defs.h>
+#include <hwregs/intr_vect_defs.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/irq.h>
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+#include "../i2c.h"
+
+#define VIRT_I2C_ADDR 0x40
+#endif
+
/* The following gio ports on ETRAX FS is available:
* pa 8 bits, supports interrupts off, hi, low, set, posedge, negedge anyedge
* pb 18 bits
#if 0
static int dp_cnt;
-#define DP(x) do { dp_cnt++; if (dp_cnt % 1000 == 0) x; }while(0)
+#define DP(x) \
+ do { \
+ dp_cnt++; \
+ if (dp_cnt % 1000 == 0) \
+ x; \
+ } while (0)
#else
#define DP(x)
#endif
static wait_queue_head_t *gpio_wq;
#endif
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static int virtual_gpio_ioctl(struct file *file, unsigned int cmd,
+ unsigned long arg);
+#endif
static int gpio_ioctl(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg);
-static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
- loff_t *off);
+ unsigned int cmd, unsigned long arg);
+static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
+ loff_t *off);
static int gpio_open(struct inode *inode, struct file *filp);
static int gpio_release(struct inode *inode, struct file *filp);
-static unsigned int gpio_poll(struct file *filp, struct poll_table_struct *wait);
+static unsigned int gpio_poll(struct file *filp,
+ struct poll_table_struct *wait);
/* private data per open() of this driver */
/* linked list of alarms to check for */
-static struct gpio_private *alarmlist = 0;
+static struct gpio_private *alarmlist;
-static int gpio_some_alarms = 0; /* Set if someone uses alarm */
-static unsigned long gpio_pa_high_alarms = 0;
-static unsigned long gpio_pa_low_alarms = 0;
+static int gpio_some_alarms; /* Set if someone uses alarm */
+static unsigned long gpio_pa_high_alarms;
+static unsigned long gpio_pa_low_alarms;
static DEFINE_SPINLOCK(alarm_lock);
#define NUM_PORTS (GPIO_MINOR_LAST+1)
-#define GIO_REG_RD_ADDR(reg) (volatile unsigned long*) (regi_gio + REG_RD_ADDR_gio_##reg )
-#define GIO_REG_WR_ADDR(reg) (volatile unsigned long*) (regi_gio + REG_RD_ADDR_gio_##reg )
+#define GIO_REG_RD_ADDR(reg) \
+ (volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
+#define GIO_REG_WR_ADDR(reg) \
+ (volatile unsigned long *)(regi_gio + REG_RD_ADDR_gio_##reg)
unsigned long led_dummy;
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static unsigned long virtual_dummy;
+static unsigned long virtual_rw_pv_oe = CONFIG_ETRAX_DEF_GIO_PV_OE;
+static unsigned short cached_virtual_gpio_read;
+#endif
static volatile unsigned long *data_out[NUM_PORTS] = {
GIO_REG_WR_ADDR(rw_pa_dout),
GIO_REG_WR_ADDR(rw_pc_dout),
GIO_REG_WR_ADDR(rw_pd_dout),
GIO_REG_WR_ADDR(rw_pe_dout),
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ &virtual_dummy,
+#endif
};
static volatile unsigned long *data_in[NUM_PORTS] = {
GIO_REG_RD_ADDR(r_pc_din),
GIO_REG_RD_ADDR(r_pd_din),
GIO_REG_RD_ADDR(r_pe_din),
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ &virtual_dummy,
+#endif
};
static unsigned long changeable_dir[NUM_PORTS] = {
CONFIG_ETRAX_PC_CHANGEABLE_DIR,
CONFIG_ETRAX_PD_CHANGEABLE_DIR,
CONFIG_ETRAX_PE_CHANGEABLE_DIR,
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ CONFIG_ETRAX_PV_CHANGEABLE_DIR,
+#endif
};
static unsigned long changeable_bits[NUM_PORTS] = {
CONFIG_ETRAX_PC_CHANGEABLE_BITS,
CONFIG_ETRAX_PD_CHANGEABLE_BITS,
CONFIG_ETRAX_PE_CHANGEABLE_BITS,
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ CONFIG_ETRAX_PV_CHANGEABLE_BITS,
+#endif
};
static volatile unsigned long *dir_oe[NUM_PORTS] = {
GIO_REG_WR_ADDR(rw_pc_oe),
GIO_REG_WR_ADDR(rw_pd_oe),
GIO_REG_WR_ADDR(rw_pe_oe),
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ &virtual_rw_pv_oe,
+#endif
};
-static unsigned int
-gpio_poll(struct file *file,
- poll_table *wait)
+static unsigned int gpio_poll(struct file *file, struct poll_table_struct *wait)
{
unsigned int mask = 0;
struct gpio_private *priv = (struct gpio_private *)file->private_data;
unsigned long flags;
local_irq_save(flags);
- data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din, REG_RD(gio, regi_gio, r_pa_din));
+ data = REG_TYPE_CONV(unsigned long, reg_gio_r_pa_din,
+ REG_RD(gio, regi_gio, r_pa_din));
/* PA has support for interrupt
* lets activate high for those low and with highalarm set
*/
intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
tmp = ~data & priv->highalarm & 0xFF;
- if (tmp & (1 << 0)) {
+ if (tmp & (1 << 0))
intr_cfg.pa0 = regk_gio_hi;
- }
- if (tmp & (1 << 1)) {
+ if (tmp & (1 << 1))
intr_cfg.pa1 = regk_gio_hi;
- }
- if (tmp & (1 << 2)) {
+ if (tmp & (1 << 2))
intr_cfg.pa2 = regk_gio_hi;
- }
- if (tmp & (1 << 3)) {
+ if (tmp & (1 << 3))
intr_cfg.pa3 = regk_gio_hi;
- }
- if (tmp & (1 << 4)) {
+ if (tmp & (1 << 4))
intr_cfg.pa4 = regk_gio_hi;
- }
- if (tmp & (1 << 5)) {
+ if (tmp & (1 << 5))
intr_cfg.pa5 = regk_gio_hi;
- }
- if (tmp & (1 << 6)) {
+ if (tmp & (1 << 6))
intr_cfg.pa6 = regk_gio_hi;
- }
- if (tmp & (1 << 7)) {
+ if (tmp & (1 << 7))
intr_cfg.pa7 = regk_gio_hi;
- }
/*
* lets activate low for those high and with lowalarm set
*/
tmp = data & priv->lowalarm & 0xFF;
- if (tmp & (1 << 0)) {
+ if (tmp & (1 << 0))
intr_cfg.pa0 = regk_gio_lo;
- }
- if (tmp & (1 << 1)) {
+ if (tmp & (1 << 1))
intr_cfg.pa1 = regk_gio_lo;
- }
- if (tmp & (1 << 2)) {
+ if (tmp & (1 << 2))
intr_cfg.pa2 = regk_gio_lo;
- }
- if (tmp & (1 << 3)) {
+ if (tmp & (1 << 3))
intr_cfg.pa3 = regk_gio_lo;
- }
- if (tmp & (1 << 4)) {
+ if (tmp & (1 << 4))
intr_cfg.pa4 = regk_gio_lo;
- }
- if (tmp & (1 << 5)) {
+ if (tmp & (1 << 5))
intr_cfg.pa5 = regk_gio_lo;
- }
- if (tmp & (1 << 6)) {
+ if (tmp & (1 << 6))
intr_cfg.pa6 = regk_gio_lo;
- }
- if (tmp & (1 << 7)) {
+ if (tmp & (1 << 7))
intr_cfg.pa7 = regk_gio_lo;
- }
REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
local_irq_restore(flags);
else
return 0;
- if ((data & priv->highalarm) ||
- (~data & priv->lowalarm)) {
+ if ((data & priv->highalarm) || (~data & priv->lowalarm))
mask = POLLIN|POLLRDNORM;
- }
- DP(printk("gpio_poll ready: mask 0x%08X\n", mask));
+ DP(printk(KERN_DEBUG "gpio_poll ready: mask 0x%08X\n", mask));
return mask;
}
int etrax_gpio_wake_up_check(void)
{
- struct gpio_private *priv = alarmlist;
+ struct gpio_private *priv;
unsigned long data = 0;
- int ret = 0;
+ unsigned long flags;
+ int ret = 0;
+ spin_lock_irqsave(&alarm_lock, flags);
+ priv = alarmlist;
while (priv) {
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ if (priv->minor == GPIO_MINOR_V)
+ data = (unsigned long)cached_virtual_gpio_read;
+ else {
+ data = *data_in[priv->minor];
+ if (priv->minor == GPIO_MINOR_A)
+ priv->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
+ }
+#else
data = *data_in[priv->minor];
+#endif
if ((data & priv->highalarm) ||
(~data & priv->lowalarm)) {
- DP(printk("etrax_gpio_wake_up_check %i\n",priv->minor));
+ DP(printk(KERN_DEBUG
+ "etrax_gpio_wake_up_check %i\n", priv->minor));
wake_up_interruptible(&priv->alarm_wq);
- ret = 1;
+ ret = 1;
}
priv = priv->next;
}
- return ret;
+ spin_unlock_irqrestore(&alarm_lock, flags);
+ return ret;
}
static irqreturn_t
-gpio_poll_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+gpio_poll_timer_interrupt(int irq, void *dev_id)
{
- if (gpio_some_alarms) {
+ if (gpio_some_alarms)
return IRQ_RETVAL(etrax_gpio_wake_up_check());
- }
- return IRQ_NONE;
+ return IRQ_NONE;
}
static irqreturn_t
-gpio_pa_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+gpio_pa_interrupt(int irq, void *dev_id)
{
reg_gio_rw_intr_mask intr_mask;
reg_gio_r_masked_intr masked_intr;
reg_gio_rw_ack_intr ack_intr;
unsigned long tmp;
unsigned long tmp2;
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ unsigned char enable_gpiov_ack = 0;
+#endif
/* Find what PA interrupts are active */
masked_intr = REG_RD(gio, regi_gio, r_masked_intr);
tmp &= (gpio_pa_high_alarms | gpio_pa_low_alarms);
spin_unlock(&alarm_lock);
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ /* Something changed on virtual GPIO. Interrupt is acked by
+ * reading the device.
+ */
+ if (tmp & (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN)) {
+ i2c_read(VIRT_I2C_ADDR, (void *)&cached_virtual_gpio_read,
+ sizeof(cached_virtual_gpio_read));
+ enable_gpiov_ack = 1;
+ }
+#endif
+
/* Ack them */
ack_intr = REG_TYPE_CONV(reg_gio_rw_ack_intr, unsigned long, tmp);
REG_WR(gio, regi_gio, rw_ack_intr, ack_intr);
intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
tmp2 = REG_TYPE_CONV(unsigned long, reg_gio_rw_intr_mask, intr_mask);
tmp2 &= ~tmp;
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ /* Do not disable interrupt on virtual GPIO. Changes on virtual
+ * pins are only noticed by an interrupt.
+ */
+ if (enable_gpiov_ack)
+ tmp2 |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
+#endif
intr_mask = REG_TYPE_CONV(reg_gio_rw_intr_mask, unsigned long, tmp2);
REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
- if (gpio_some_alarms) {
+ if (gpio_some_alarms)
return IRQ_RETVAL(etrax_gpio_wake_up_check());
- }
- return IRQ_NONE;
+ return IRQ_NONE;
}
-static ssize_t gpio_write(struct file * file, const char * buf, size_t count,
- loff_t *off)
+static ssize_t gpio_write(struct file *file, const char *buf, size_t count,
+ loff_t *off)
{
struct gpio_private *priv = (struct gpio_private *)file->private_data;
unsigned char data, clk_mask, data_mask, write_msb;
ssize_t retval = count;
/* Only bits 0-7 may be used for write operations but allow all
devices except leds... */
- if (priv->minor == GPIO_MINOR_LEDS) {
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ if (priv->minor == GPIO_MINOR_V)
+ return -EFAULT;
+#endif
+ if (priv->minor == GPIO_MINOR_LEDS)
return -EFAULT;
- }
- if (!access_ok(VERIFY_READ, buf, count)) {
+ if (!access_ok(VERIFY_READ, buf, count))
return -EFAULT;
- }
clk_mask = priv->clk_mask;
data_mask = priv->data_mask;
/* It must have been configured using the IO_CFG_WRITE_MODE */
/* Perhaps a better error code? */
- if (clk_mask == 0 || data_mask == 0) {
+ if (clk_mask == 0 || data_mask == 0)
return -EPERM;
- }
write_msb = priv->write_msb;
- D(printk("gpio_write: %lu to data 0x%02X clk 0x%02X msb: %i\n",count, data_mask, clk_mask, write_msb));
+ D(printk(KERN_DEBUG "gpio_write: %lu to data 0x%02X clk 0x%02X "
+ "msb: %i\n", count, data_mask, clk_mask, write_msb));
port = data_out[priv->minor];
while (count--) {
int i;
data = *buf++;
if (priv->write_msb) {
- for (i = 7; i >= 0;i--) {
+ for (i = 7; i >= 0; i--) {
local_irq_save(flags);
shadow = *port;
*port = shadow &= ~clk_mask;
local_irq_restore(flags);
}
} else {
- for (i = 0; i <= 7;i++) {
+ for (i = 0; i <= 7; i++) {
local_irq_save(flags);
shadow = *port;
*port = shadow &= ~clk_mask;
if (p > GPIO_MINOR_LAST)
return -EINVAL;
- priv = kmalloc(sizeof(struct gpio_private),
- GFP_KERNEL);
+ priv = kmalloc(sizeof(struct gpio_private), GFP_KERNEL);
if (!priv)
return -ENOMEM;
+ memset(priv, 0, sizeof(*priv));
priv->minor = p;
- /* initialize the io/alarm struct and link it into our alarmlist */
+ /* initialize the io/alarm struct */
- priv->next = alarmlist;
- alarmlist = priv;
priv->clk_mask = 0;
priv->data_mask = 0;
priv->highalarm = 0;
filp->private_data = (void *)priv;
+ /* link it into our alarmlist */
+ spin_lock_irq(&alarm_lock);
+ priv->next = alarmlist;
+ alarmlist = priv;
+ spin_unlock_irq(&alarm_lock);
+
return 0;
}
static int
gpio_release(struct inode *inode, struct file *filp)
{
- struct gpio_private *p = alarmlist;
- struct gpio_private *todel = (struct gpio_private *)filp->private_data;
+ struct gpio_private *p;
+ struct gpio_private *todel;
/* local copies while updating them: */
unsigned long a_high, a_low;
unsigned long some_alarms;
/* unlink from alarmlist and free the private structure */
+ spin_lock_irq(&alarm_lock);
+ p = alarmlist;
+ todel = (struct gpio_private *)filp->private_data;
+
if (p == todel) {
alarmlist = todel->next;
} else {
kfree(todel);
/* Check if there are still any alarms set */
p = alarmlist;
- some_alarms = 0;
+ some_alarms = 0;
a_high = 0;
a_low = 0;
while (p) {
if (p->minor == GPIO_MINOR_A) {
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ p->lowalarm |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
+#endif
a_high |= p->highalarm;
a_low |= p->lowalarm;
}
- if (p->highalarm | p->lowalarm) {
+ if (p->highalarm | p->lowalarm)
some_alarms = 1;
- }
p = p->next;
}
- spin_lock(&alarm_lock);
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ /* Variables 'some_alarms' and 'a_low' needs to be set here again
+ * to ensure that interrupt for virtual GPIO is handled.
+ */
+ some_alarms = 1;
+ a_low |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
+#endif
+
gpio_some_alarms = some_alarms;
gpio_pa_high_alarms = a_high;
gpio_pa_low_alarms = a_low;
- spin_unlock(&alarm_lock);
+ spin_unlock_irq(&alarm_lock);
return 0;
}
* set alarms to wait for using a subsequent select().
*/
-unsigned long inline setget_input(struct gpio_private *priv, unsigned long arg)
+inline unsigned long setget_input(struct gpio_private *priv, unsigned long arg)
{
/* Set direction 0=unchanged 1=input,
* return mask with 1=input
if (priv->minor == GPIO_MINOR_A)
dir_shadow ^= 0xFF; /* Only 8 bits */
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ else if (priv->minor == GPIO_MINOR_V)
+ dir_shadow ^= 0xFFFF; /* Only 16 bits */
+#endif
else
dir_shadow ^= 0x3FFFF; /* Only 18 bits */
return dir_shadow;
} /* setget_input */
-unsigned long inline setget_output(struct gpio_private *priv, unsigned long arg)
+inline unsigned long setget_output(struct gpio_private *priv, unsigned long arg)
{
unsigned long flags;
unsigned long dir_shadow;
unsigned long val;
unsigned long shadow;
struct gpio_private *priv = (struct gpio_private *)file->private_data;
- if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE) {
+ if (_IOC_TYPE(cmd) != ETRAXGPIO_IOCTYPE)
return -EINVAL;
- }
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ if (priv->minor == GPIO_MINOR_V)
+ return virtual_gpio_ioctl(file, cmd, arg);
+#endif
switch (_IOC_NR(cmd)) {
case IO_READBITS: /* Use IO_READ_INBITS and IO_READ_OUTBITS instead */
- // read the port
+ /* Read the port. */
return *data_in[priv->minor];
break;
case IO_SETBITS:
local_irq_save(flags);
- if (arg & 0x04)
- printk("GPIO SET 2\n");
- // set changeable bits with a 1 in arg
+ /* Set changeable bits with a 1 in arg. */
shadow = *data_out[priv->minor];
shadow |= (arg & changeable_bits[priv->minor]);
*data_out[priv->minor] = shadow;
break;
case IO_CLRBITS:
local_irq_save(flags);
- if (arg & 0x04)
- printk("GPIO CLR 2\n");
- // clear changeable bits with a 1 in arg
+ /* Clear changeable bits with a 1 in arg. */
shadow = *data_out[priv->minor];
shadow &= ~(arg & changeable_bits[priv->minor]);
*data_out[priv->minor] = shadow;
local_irq_restore(flags);
break;
case IO_HIGHALARM:
- // set alarm when bits with 1 in arg go high
+ /* Set alarm when bits with 1 in arg go high. */
priv->highalarm |= arg;
- spin_lock(&alarm_lock);
+ spin_lock_irqsave(&alarm_lock, flags);
gpio_some_alarms = 1;
- if (priv->minor == GPIO_MINOR_A) {
+ if (priv->minor == GPIO_MINOR_A)
gpio_pa_high_alarms |= arg;
- }
- spin_unlock(&alarm_lock);
+ spin_unlock_irqrestore(&alarm_lock, flags);
break;
case IO_LOWALARM:
- // set alarm when bits with 1 in arg go low
+ /* Set alarm when bits with 1 in arg go low. */
priv->lowalarm |= arg;
- spin_lock(&alarm_lock);
+ spin_lock_irqsave(&alarm_lock, flags);
gpio_some_alarms = 1;
- if (priv->minor == GPIO_MINOR_A) {
+ if (priv->minor == GPIO_MINOR_A)
gpio_pa_low_alarms |= arg;
- }
- spin_unlock(&alarm_lock);
+ spin_unlock_irqrestore(&alarm_lock, flags);
break;
case IO_CLRALARM:
- // clear alarm for bits with 1 in arg
+ /* Clear alarm for bits with 1 in arg. */
priv->highalarm &= ~arg;
priv->lowalarm &= ~arg;
- spin_lock(&alarm_lock);
+ spin_lock_irqsave(&alarm_lock, flags);
if (priv->minor == GPIO_MINOR_A) {
if (gpio_pa_high_alarms & arg ||
- gpio_pa_low_alarms & arg) {
+ gpio_pa_low_alarms & arg)
/* Must update the gpio_pa_*alarms masks */
- }
+ ;
}
- spin_unlock(&alarm_lock);
+ spin_unlock_irqrestore(&alarm_lock, flags);
break;
case IO_READDIR: /* Use IO_SETGET_INPUT/OUTPUT instead! */
/* Read direction 0=input 1=output */
if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
(priv->data_mask & changeable_bits[priv->minor]) &&
(priv->clk_mask & dir_shadow) &&
- (priv->data_mask & dir_shadow)))
- {
+ (priv->data_mask & dir_shadow))) {
priv->clk_mask = 0;
priv->data_mask = 0;
return -EPERM;
case IO_READ_INBITS:
/* *arg is result of reading the input pins */
val = *data_in[priv->minor];
- if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
return 0;
break;
case IO_READ_OUTBITS:
/* *arg is result of reading the output shadow */
val = *data_out[priv->minor];
- if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
break;
case IO_SETGET_INPUT:
/* bits set in *arg is set to input,
* *arg updated with current input pins.
*/
- if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
+ if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
return -EFAULT;
val = setget_input(priv, val);
- if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
break;
case IO_SETGET_OUTPUT:
/* bits set in *arg is set to output,
* *arg updated with current output pins.
*/
- if (copy_from_user(&val, (unsigned long*)arg, sizeof(val)))
+ if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
return -EFAULT;
val = setget_output(priv, val);
- if (copy_to_user((unsigned long*)arg, &val, sizeof(val)))
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
return -EFAULT;
break;
default:
return 0;
}
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static int
+virtual_gpio_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+ unsigned long flags;
+ unsigned short val;
+ unsigned short shadow;
+ struct gpio_private *priv = (struct gpio_private *)file->private_data;
+
+ switch (_IOC_NR(cmd)) {
+ case IO_SETBITS:
+ local_irq_save(flags);
+ /* Set changeable bits with a 1 in arg. */
+ i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ shadow |= ~*dir_oe[priv->minor];
+ shadow |= (arg & changeable_bits[priv->minor]);
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ local_irq_restore(flags);
+ break;
+ case IO_CLRBITS:
+ local_irq_save(flags);
+ /* Clear changeable bits with a 1 in arg. */
+ i2c_read(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ shadow |= ~*dir_oe[priv->minor];
+ shadow &= ~(arg & changeable_bits[priv->minor]);
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+ local_irq_restore(flags);
+ break;
+ case IO_HIGHALARM:
+ /* Set alarm when bits with 1 in arg go high. */
+ priv->highalarm |= arg;
+ spin_lock(&alarm_lock);
+ gpio_some_alarms = 1;
+ spin_unlock(&alarm_lock);
+ break;
+ case IO_LOWALARM:
+ /* Set alarm when bits with 1 in arg go low. */
+ priv->lowalarm |= arg;
+ spin_lock(&alarm_lock);
+ gpio_some_alarms = 1;
+ spin_unlock(&alarm_lock);
+ break;
+ case IO_CLRALARM:
+ /* Clear alarm for bits with 1 in arg. */
+ priv->highalarm &= ~arg;
+ priv->lowalarm &= ~arg;
+ spin_lock(&alarm_lock);
+ spin_unlock(&alarm_lock);
+ break;
+ case IO_CFG_WRITE_MODE:
+ {
+ unsigned long dir_shadow;
+ dir_shadow = *dir_oe[priv->minor];
+
+ priv->clk_mask = arg & 0xFF;
+ priv->data_mask = (arg >> 8) & 0xFF;
+ priv->write_msb = (arg >> 16) & 0x01;
+ /* Check if we're allowed to change the bits and
+ * the direction is correct
+ */
+ if (!((priv->clk_mask & changeable_bits[priv->minor]) &&
+ (priv->data_mask & changeable_bits[priv->minor]) &&
+ (priv->clk_mask & dir_shadow) &&
+ (priv->data_mask & dir_shadow))) {
+ priv->clk_mask = 0;
+ priv->data_mask = 0;
+ return -EPERM;
+ }
+ break;
+ }
+ case IO_READ_INBITS:
+ /* *arg is result of reading the input pins */
+ val = cached_virtual_gpio_read;
+ val &= ~*dir_oe[priv->minor];
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ return 0;
+ break;
+ case IO_READ_OUTBITS:
+ /* *arg is result of reading the output shadow */
+ i2c_read(VIRT_I2C_ADDR, (void *)&val, sizeof(val));
+ val &= *dir_oe[priv->minor];
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ case IO_SETGET_INPUT:
+ {
+ /* bits set in *arg is set to input,
+ * *arg updated with current input pins.
+ */
+ unsigned short input_mask = ~*dir_oe[priv->minor];
+ if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
+ return -EFAULT;
+ val = setget_input(priv, val);
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ if ((input_mask & val) != input_mask) {
+ /* Input pins changed. All ports desired as input
+ * should be set to logic 1.
+ */
+ unsigned short change = input_mask ^ val;
+ i2c_read(VIRT_I2C_ADDR, (void *)&shadow,
+ sizeof(shadow));
+ shadow &= ~change;
+ shadow |= val;
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow,
+ sizeof(shadow));
+ }
+ break;
+ }
+ case IO_SETGET_OUTPUT:
+ /* bits set in *arg is set to output,
+ * *arg updated with current output pins.
+ */
+ if (copy_from_user(&val, (unsigned long *)arg, sizeof(val)))
+ return -EFAULT;
+ val = setget_output(priv, val);
+ if (copy_to_user((unsigned long *)arg, &val, sizeof(val)))
+ return -EFAULT;
+ break;
+ default:
+ return -EINVAL;
+ } /* switch */
+ return 0;
+}
+#endif /* CONFIG_ETRAX_VIRTUAL_GPIO */
+
static int
gpio_leds_ioctl(unsigned int cmd, unsigned long arg)
{
case IO_LEDACTIVE_SET:
green = ((unsigned char) arg) & 1;
red = (((unsigned char) arg) >> 1) & 1;
- LED_ACTIVE_SET_G(green);
- LED_ACTIVE_SET_R(red);
+ CRIS_LED_ACTIVE_SET_G(green);
+ CRIS_LED_ACTIVE_SET_R(red);
break;
default:
return 0;
}
-const struct file_operations gpio_fops = {
+struct file_operations gpio_fops = {
.owner = THIS_MODULE,
.poll = gpio_poll,
.ioctl = gpio_ioctl,
.release = gpio_release,
};
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+static void
+virtual_gpio_init(void)
+{
+ reg_gio_rw_intr_cfg intr_cfg;
+ reg_gio_rw_intr_mask intr_mask;
+ unsigned short shadow;
+
+ shadow = ~virtual_rw_pv_oe; /* Input ports should be set to logic 1 */
+ shadow |= CONFIG_ETRAX_DEF_GIO_PV_OUT;
+ i2c_write(VIRT_I2C_ADDR, (void *)&shadow, sizeof(shadow));
+
+ /* Set interrupt mask and on what state the interrupt shall trigger.
+ * For virtual gpio the interrupt shall trigger on logic '0'.
+ */
+ intr_cfg = REG_RD(gio, regi_gio, rw_intr_cfg);
+ intr_mask = REG_RD(gio, regi_gio, rw_intr_mask);
+
+ switch (CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN) {
+ case 0:
+ intr_cfg.pa0 = regk_gio_lo;
+ intr_mask.pa0 = regk_gio_yes;
+ break;
+ case 1:
+ intr_cfg.pa1 = regk_gio_lo;
+ intr_mask.pa1 = regk_gio_yes;
+ break;
+ case 2:
+ intr_cfg.pa2 = regk_gio_lo;
+ intr_mask.pa2 = regk_gio_yes;
+ break;
+ case 3:
+ intr_cfg.pa3 = regk_gio_lo;
+ intr_mask.pa3 = regk_gio_yes;
+ break;
+ case 4:
+ intr_cfg.pa4 = regk_gio_lo;
+ intr_mask.pa4 = regk_gio_yes;
+ break;
+ case 5:
+ intr_cfg.pa5 = regk_gio_lo;
+ intr_mask.pa5 = regk_gio_yes;
+ break;
+ case 6:
+ intr_cfg.pa6 = regk_gio_lo;
+ intr_mask.pa6 = regk_gio_yes;
+ break;
+ case 7:
+ intr_cfg.pa7 = regk_gio_lo;
+ intr_mask.pa7 = regk_gio_yes;
+ break;
+ }
+
+ REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg);
+ REG_WR(gio, regi_gio, rw_intr_mask, intr_mask);
+
+ gpio_pa_low_alarms |= (1 << CONFIG_ETRAX_VIRTUAL_GPIO_INTERRUPT_PA_PIN);
+ gpio_some_alarms = 1;
+}
+#endif
/* main driver initialization routine, called from mem.c */
gpio_init(void)
{
int res;
- reg_intr_vect_rw_mask intr_mask;
/* do the formalities */
}
/* Clear all leds */
- LED_NETWORK_SET(0);
- LED_ACTIVE_SET(0);
- LED_DISK_READ(0);
- LED_DISK_WRITE(0);
-
- printk("ETRAX FS GPIO driver v2.5, (c) 2003-2005 Axis Communications AB\n");
+ CRIS_LED_NETWORK_GRP0_SET(0);
+ CRIS_LED_NETWORK_GRP1_SET(0);
+ CRIS_LED_ACTIVE_SET(0);
+ CRIS_LED_DISK_READ(0);
+ CRIS_LED_DISK_WRITE(0);
+
+ printk(KERN_INFO "ETRAX FS GPIO driver v2.5, (c) 2003-2007 "
+ "Axis Communications AB\n");
/* We call etrax_gpio_wake_up_check() from timer interrupt and
* from cpu_idle() in kernel/process.c
* The check in cpu_idle() reduces latency from ~15 ms to ~6 ms
* in some tests.
*/
- if (request_irq(TIMER_INTR_VECT, gpio_poll_timer_interrupt,
- IRQF_SHARED | IRQF_DISABLED,"gpio poll", &alarmlist)) {
- printk("err: timer0 irq for gpio\n");
- }
- if (request_irq(GEN_IO_INTR_VECT, gpio_pa_interrupt,
- IRQF_SHARED | IRQF_DISABLED,"gpio PA", &alarmlist)) {
- printk("err: PA irq for gpio\n");
- }
- /* enable the gio and timer irq in global config */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.timer = 1;
- intr_mask.gen_io = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
+ if (request_irq(TIMER0_INTR_VECT, gpio_poll_timer_interrupt,
+ IRQF_SHARED | IRQF_DISABLED, "gpio poll", &alarmlist))
+ printk(KERN_ERR "timer0 irq for gpio\n");
+
+ if (request_irq(GIO_INTR_VECT, gpio_pa_interrupt,
+ IRQF_SHARED | IRQF_DISABLED, "gpio PA", &alarmlist))
+ printk(KERN_ERR "PA irq for gpio\n");
+
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+ virtual_gpio_init();
+#endif
return res;
}
* Copyright (c) 2004
*
* Derived from drivers/mtd/nand/spia.c
- * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
- *
- * $Id: nandflash.c,v 1.3 2005/06/01 10:57:12 starvik Exp $
+ * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <asm/arch/memmap.h>
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/gio_defs.h>
-#include <asm/arch/hwregs/bif_core_defs.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/gio_defs.h>
+#include <hwregs/bif_core_defs.h>
#include <asm/io.h>
#define CE_BIT 4
#define ALE_BIT 6
#define BY_BIT 7
-static struct mtd_info *crisv32_mtd = NULL;
+struct mtd_info_wrapper {
+ struct mtd_info info;
+ struct nand_chip chip;
+};
+
+/* Bitmask for control pins */
+#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
+
+/* Bitmask for mtd nand control bits */
+#define CTRL_BITMASK (NAND_NCE | NAND_CLE | NAND_ALE)
+
+
+static struct mtd_info *crisv32_mtd;
/*
* hardware specific access to control-lines
-*/
-static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd)
+ */
+static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
{
unsigned long flags;
- reg_gio_rw_pa_dout dout = REG_RD(gio, regi_gio, rw_pa_dout);
+ reg_gio_rw_pa_dout dout;
+ struct nand_chip *this = mtd->priv;
local_irq_save(flags);
- switch(cmd){
- case NAND_CTL_SETCLE:
- dout.data |= (1<<CLE_BIT);
- break;
- case NAND_CTL_CLRCLE:
- dout.data &= ~(1<<CLE_BIT);
- break;
- case NAND_CTL_SETALE:
- dout.data |= (1<<ALE_BIT);
- break;
- case NAND_CTL_CLRALE:
- dout.data &= ~(1<<ALE_BIT);
- break;
- case NAND_CTL_SETNCE:
- dout.data |= (1<<CE_BIT);
- break;
- case NAND_CTL_CLRNCE:
- dout.data &= ~(1<<CE_BIT);
- break;
+
+ /* control bits change */
+ if (ctrl & NAND_CTRL_CHANGE) {
+ dout = REG_RD(gio, regi_gio, rw_pa_dout);
+ dout.data &= ~PIN_BITMASK;
+
+#if (CE_BIT == 4 && NAND_NCE == 1 && \
+ CLE_BIT == 5 && NAND_CLE == 2 && \
+ ALE_BIT == 6 && NAND_ALE == 4)
+ /* Pins in same order as control bits, but shifted.
+ * Optimize for this case; works for 2.6.18 */
+ dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT;
+#else
+ /* the slow way */
+ if (!(ctrl & NAND_NCE))
+ dout.data |= (1 << CE_BIT);
+ if (ctrl & NAND_CLE)
+ dout.data |= (1 << CLE_BIT);
+ if (ctrl & NAND_ALE)
+ dout.data |= (1 << ALE_BIT);
+#endif
+ REG_WR(gio, regi_gio, rw_pa_dout, dout);
}
- REG_WR(gio, regi_gio, rw_pa_dout, dout);
+
+ /* command to chip */
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, this->IO_ADDR_W);
+
local_irq_restore(flags);
}
/*
* read device ready pin
*/
-int crisv32_device_ready(struct mtd_info *mtd)
+static int crisv32_device_ready(struct mtd_info *mtd)
{
reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din);
return ((din.data & (1 << BY_BIT)) >> BY_BIT);
/*
* Main initialization routine
*/
-struct mtd_info* __init crisv32_nand_flash_probe (void)
+struct mtd_info *__init crisv32_nand_flash_probe(void)
{
void __iomem *read_cs;
void __iomem *write_cs;
- reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core, rw_grp3_cfg);
+ reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core,
+ rw_grp3_cfg);
reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe);
+ struct mtd_info_wrapper *wrapper;
struct nand_chip *this;
int err = 0;
/* Allocate memory for MTD device structure and private data */
- crisv32_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip),
- GFP_KERNEL);
- if (!crisv32_mtd) {
- printk ("Unable to allocate CRISv32 NAND MTD device structure.\n");
+ wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL);
+ if (!wrapper) {
+ printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
+ "device structure.\n");
err = -ENOMEM;
return NULL;
}
write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192);
if (!read_cs || !write_cs) {
- printk("CRISv32 NAND ioremap failed\n");
+ printk(KERN_ERR "CRISv32 NAND ioremap failed\n");
err = -EIO;
goto out_mtd;
}
/* Get pointer to private data */
- this = (struct nand_chip *) (&crisv32_mtd[1]);
+ this = &wrapper->chip;
+ crisv32_mtd = &wrapper->info;
pa_oe.oe |= 1 << CE_BIT;
pa_oe.oe |= 1 << ALE_BIT;
pa_oe.oe |= 1 << CLE_BIT;
- pa_oe.oe &= ~ (1 << BY_BIT);
+ pa_oe.oe &= ~(1 << BY_BIT);
REG_WR(gio, regi_gio, rw_pa_oe, pa_oe);
bif_cfg.gated_csp0 = regk_bif_core_rd;
bif_cfg.gated_csp1 = regk_bif_core_wr;
REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);
- /* Initialize structures */
- memset((char *) crisv32_mtd, 0, sizeof(struct mtd_info));
- memset((char *) this, 0, sizeof(struct nand_chip));
-
/* Link the private data with the MTD structure */
crisv32_mtd->priv = this;
/* Set address of NAND IO lines */
this->IO_ADDR_R = read_cs;
this->IO_ADDR_W = write_cs;
- this->hwcontrol = crisv32_hwcontrol;
+ this->cmd_ctrl = crisv32_hwcontrol;
this->dev_ready = crisv32_device_ready;
/* 20 us command delay time */
this->chip_delay = 20;
- this->eccmode = NAND_ECC_SOFT;
+ this->ecc.mode = NAND_ECC_SOFT;
/* Enable the following for a flash based bad block table */
- this->options = NAND_USE_FLASH_BBT;
+ /* this->options = NAND_USE_FLASH_BBT; */
- /* Scan to find existence of the device */
- if (nand_scan (crisv32_mtd, 1)) {
+ /* Scan to find existance of the device */
+ if (nand_scan(crisv32_mtd, 1)) {
err = -ENXIO;
goto out_ior;
}
iounmap((void *)read_cs);
iounmap((void *)write_cs);
out_mtd:
- kfree (crisv32_mtd);
- return NULL;
+ kfree(wrapper);
+ return NULL;
}
* 400 kbits/s. The built-in word address register is incremented
* automatically after each written or read byte.
*
- * Copyright (c) 2002-2003, Axis Communications AB
+ * Copyright (c) 2002-2007, Axis Communications AB
* All rights reserved.
*
* Author: Tobias Anderberg <tobiasa@axis.com>.
#include <linux/ioctl.h>
#include <linux/delay.h>
#include <linux/bcd.h>
+#include <linux/mutex.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#define PCF8563_MAJOR 121 /* Local major number. */
#define DEVICE_NAME "rtc" /* Name which is registered in /proc/devices. */
#define PCF8563_NAME "PCF8563"
-#define DRIVER_VERSION "$Revision: 1.1 $"
+#define DRIVER_VERSION "$Revision: 1.17 $"
/* Two simple wrapper macros, saves a few keystrokes. */
#define rtc_read(x) i2c_readreg(RTC_I2C_READ, x)
#define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y)
+static DEFINE_MUTEX(rtc_lock); /* Protect state etc */
+
static const unsigned char days_in_month[] =
{ 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
int pcf8563_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
-int pcf8563_open(struct inode *, struct file *);
-int pcf8563_release(struct inode *, struct file *);
+
+/* Cache VL bit value read at driver init since writing the RTC_SECOND
+ * register clears the VL status.
+ */
+static int voltage_low;
static const struct file_operations pcf8563_fops = {
.owner = THIS_MODULE,
- .ioctl = pcf8563_ioctl,
- .open = pcf8563_open,
- .release = pcf8563_release,
+ .ioctl = pcf8563_ioctl
};
unsigned char
{
unsigned char res = rtc_read(reg);
- /* The PCF8563 does not return 0 for unimplemented bits */
+ /* The PCF8563 does not return 0 for unimplemented bits. */
switch (reg) {
case RTC_SECONDS:
case RTC_MINUTES:
void
pcf8563_writereg(int reg, unsigned char val)
{
-#ifdef CONFIG_ETRAX_RTC_READONLY
- if (reg == RTC_CONTROL1 || (reg >= RTC_SECONDS && reg <= RTC_YEAR))
- return;
-#endif
-
rtc_write(reg, val);
}
tm->tm_mon = rtc_read(RTC_MONTH);
tm->tm_year = rtc_read(RTC_YEAR);
- if (tm->tm_sec & 0x80)
- printk(KERN_WARNING "%s: RTC Voltage Low - reliable date/time "
+ if (tm->tm_sec & 0x80) {
+ printk(KERN_ERR "%s: RTC Voltage Low - reliable date/time "
"information is no longer guaranteed!\n", PCF8563_NAME);
+ }
- tm->tm_year = BCD_TO_BIN(tm->tm_year) + ((tm->tm_mon & 0x80) ? 100 : 0);
+ tm->tm_year = BCD_TO_BIN(tm->tm_year) +
+ ((tm->tm_mon & 0x80) ? 100 : 0);
tm->tm_sec &= 0x7F;
tm->tm_min &= 0x7F;
tm->tm_hour &= 0x3F;
int __init
pcf8563_init(void)
{
+ static int res;
+ static int first = 1;
+
+ if (!first)
+ return res;
+ first = 0;
+
/* Initiate the i2c protocol. */
- i2c_init();
+ res = i2c_init();
+ if (res < 0) {
+ printk(KERN_CRIT "pcf8563_init: Failed to init i2c.\n");
+ return res;
+ }
/*
* First of all we need to reset the chip. This is done by
if (rtc_write(RTC_WEEKDAY_ALARM, 0x80) < 0)
goto err;
- if (register_chrdev(PCF8563_MAJOR, DEVICE_NAME, &pcf8563_fops) < 0) {
- printk(KERN_INFO "%s: Unable to get major number %d for RTC device.\n",
- PCF8563_NAME, PCF8563_MAJOR);
- return -1;
+ /* Check for low voltage, and warn about it. */
+ if (rtc_read(RTC_SECONDS) & 0x80) {
+ voltage_low = 1;
+ printk(KERN_WARNING "%s: RTC Voltage Low - reliable "
+ "date/time information is no longer guaranteed!\n",
+ PCF8563_NAME);
}
- printk(KERN_INFO "%s Real-Time Clock Driver, %s\n", PCF8563_NAME, DRIVER_VERSION);
-
- /* Check for low voltage, and warn about it.. */
- if (rtc_read(RTC_SECONDS) & 0x80)
- printk(KERN_WARNING "%s: RTC Voltage Low - reliable date/time "
- "information is no longer guaranteed!\n", PCF8563_NAME);
-
- return 0;
+ return res;
err:
printk(KERN_INFO "%s: Error initializing chip.\n", PCF8563_NAME);
- return -1;
+ res = -1;
+ return res;
}
void __exit
* ioctl calls for this driver. Why return -ENOTTY upon error? Because
* POSIX says so!
*/
-int
-pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg)
+int pcf8563_ioctl(struct inode *inode, struct file *filp, unsigned int cmd,
+ unsigned long arg)
{
/* Some sanity checks. */
if (_IOC_TYPE(cmd) != RTC_MAGIC)
return -ENOTTY;
switch (cmd) {
- case RTC_RD_TIME:
- {
- struct rtc_time tm;
-
- memset(&tm, 0, sizeof (struct rtc_time));
- get_rtc_time(&tm);
-
- if (copy_to_user((struct rtc_time *) arg, &tm, sizeof tm)) {
- return -EFAULT;
- }
-
- return 0;
+ case RTC_RD_TIME:
+ {
+ struct rtc_time tm;
+
+ mutex_lock(&rtc_lock);
+ memset(&tm, 0, sizeof tm);
+ get_rtc_time(&tm);
+
+ if (copy_to_user((struct rtc_time *) arg, &tm,
+ sizeof tm)) {
+ spin_unlock(&rtc_lock);
+ return -EFAULT;
}
- case RTC_SET_TIME:
- {
-#ifdef CONFIG_ETRAX_RTC_READONLY
+ mutex_unlock(&rtc_lock);
+
+ return 0;
+ }
+ case RTC_SET_TIME:
+ {
+ int leap;
+ int year;
+ int century;
+ struct rtc_time tm;
+
+ memset(&tm, 0, sizeof tm);
+ if (!capable(CAP_SYS_TIME))
return -EPERM;
-#else
- int leap;
- int year;
- int century;
- struct rtc_time tm;
-
- if (!capable(CAP_SYS_TIME))
- return -EPERM;
-
- if (copy_from_user(&tm, (struct rtc_time *) arg, sizeof tm))
- return -EFAULT;
-
- /* Convert from struct tm to struct rtc_time. */
- tm.tm_year += 1900;
- tm.tm_mon += 1;
-
- /*
- * Check if tm.tm_year is a leap year. A year is a leap
- * year if it is divisible by 4 but not 100, except
- * that years divisible by 400 _are_ leap years.
- */
- year = tm.tm_year;
- leap = (tm.tm_mon == 2) && ((year % 4 == 0 && year % 100 != 0) || year % 400 == 0);
-
- /* Perform some sanity checks. */
- if ((tm.tm_year < 1970) ||
- (tm.tm_mon > 12) ||
- (tm.tm_mday == 0) ||
- (tm.tm_mday > days_in_month[tm.tm_mon] + leap) ||
- (tm.tm_wday >= 7) ||
- (tm.tm_hour >= 24) ||
- (tm.tm_min >= 60) ||
- (tm.tm_sec >= 60))
- return -EINVAL;
-
- century = (tm.tm_year >= 2000) ? 0x80 : 0;
- tm.tm_year = tm.tm_year % 100;
-
- BIN_TO_BCD(tm.tm_year);
- BIN_TO_BCD(tm.tm_mday);
- BIN_TO_BCD(tm.tm_hour);
- BIN_TO_BCD(tm.tm_min);
- BIN_TO_BCD(tm.tm_sec);
- tm.tm_mon |= century;
-
- rtc_write(RTC_YEAR, tm.tm_year);
- rtc_write(RTC_MONTH, tm.tm_mon);
- rtc_write(RTC_WEEKDAY, tm.tm_wday); /* Not coded in BCD. */
- rtc_write(RTC_DAY_OF_MONTH, tm.tm_mday);
- rtc_write(RTC_HOURS, tm.tm_hour);
- rtc_write(RTC_MINUTES, tm.tm_min);
- rtc_write(RTC_SECONDS, tm.tm_sec);
-
- return 0;
-#endif /* !CONFIG_ETRAX_RTC_READONLY */
- }
- case RTC_VLOW_RD:
- {
- int vl_bit = 0;
+ if (copy_from_user(&tm, (struct rtc_time *) arg,
+ sizeof tm))
+ return -EFAULT;
+
+ /* Convert from struct tm to struct rtc_time. */
+ tm.tm_year += 1900;
+ tm.tm_mon += 1;
+
+ /*
+ * Check if tm.tm_year is a leap year. A year is a leap
+ * year if it is divisible by 4 but not 100, except
+ * that years divisible by 400 _are_ leap years.
+ */
+ year = tm.tm_year;
+ leap = (tm.tm_mon == 2) &&
+ ((year % 4 == 0 && year % 100 != 0) || year % 400 == 0);
+
+ /* Perform some sanity checks. */
+ if ((tm.tm_year < 1970) ||
+ (tm.tm_mon > 12) ||
+ (tm.tm_mday == 0) ||
+ (tm.tm_mday > days_in_month[tm.tm_mon] + leap) ||
+ (tm.tm_wday >= 7) ||
+ (tm.tm_hour >= 24) ||
+ (tm.tm_min >= 60) ||
+ (tm.tm_sec >= 60))
+ return -EINVAL;
+
+ century = (tm.tm_year >= 2000) ? 0x80 : 0;
+ tm.tm_year = tm.tm_year % 100;
+
+ BIN_TO_BCD(tm.tm_year);
+ BIN_TO_BCD(tm.tm_mon);
+ BIN_TO_BCD(tm.tm_mday);
+ BIN_TO_BCD(tm.tm_hour);
+ BIN_TO_BCD(tm.tm_min);
+ BIN_TO_BCD(tm.tm_sec);
+ tm.tm_mon |= century;
+
+ mutex_lock(&rtc_lock);
+
+ rtc_write(RTC_YEAR, tm.tm_year);
+ rtc_write(RTC_MONTH, tm.tm_mon);
+ rtc_write(RTC_WEEKDAY, tm.tm_wday); /* Not coded in BCD. */
+ rtc_write(RTC_DAY_OF_MONTH, tm.tm_mday);
+ rtc_write(RTC_HOURS, tm.tm_hour);
+ rtc_write(RTC_MINUTES, tm.tm_min);
+ rtc_write(RTC_SECONDS, tm.tm_sec);
+
+ mutex_unlock(&rtc_lock);
+
+ return 0;
+ }
+ case RTC_VL_READ:
+ if (voltage_low)
+ printk(KERN_ERR "%s: RTC Voltage Low - "
+ "reliable date/time information is no "
+ "longer guaranteed!\n", PCF8563_NAME);
- if (rtc_read(RTC_SECONDS) & 0x80) {
- vl_bit = 1;
- printk(KERN_WARNING "%s: RTC Voltage Low - reliable "
- "date/time information is no longer guaranteed!\n",
- PCF8563_NAME);
- }
- if (copy_to_user((int *) arg, &vl_bit, sizeof(int)))
- return -EFAULT;
+ if (copy_to_user((int *) arg, &voltage_low, sizeof(int)))
+ return -EFAULT;
+ return 0;
- return 0;
- }
+ case RTC_VL_CLR:
+ {
+ /* Clear the VL bit in the seconds register in case
+ * the time has not been set already (which would
+ * have cleared it). This does not really matter
+ * because of the cached voltage_low value but do it
+ * anyway for consistency. */
- case RTC_VLOW_SET:
- {
- /* Clear the VL bit in the seconds register */
- int ret = rtc_read(RTC_SECONDS);
+ int ret = rtc_read(RTC_SECONDS);
- rtc_write(RTC_SECONDS, (ret & 0x7F));
+ rtc_write(RTC_SECONDS, (ret & 0x7F));
- return 0;
- }
+ /* Clear the cached value. */
+ voltage_low = 0;
- default:
- return -ENOTTY;
+ return 0;
+ }
+ default:
+ return -ENOTTY;
}
return 0;
}
-int
-pcf8563_open(struct inode *inode, struct file *filp)
+static int __init pcf8563_register(void)
{
- return 0;
-}
+ if (pcf8563_init() < 0) {
+ printk(KERN_INFO "%s: Unable to initialize Real-Time Clock "
+ "Driver, %s\n", PCF8563_NAME, DRIVER_VERSION);
+ return -1;
+ }
+
+ if (register_chrdev(PCF8563_MAJOR, DEVICE_NAME, &pcf8563_fops) < 0) {
+ printk(KERN_INFO "%s: Unable to get major numer %d for RTC "
+ "device.\n", PCF8563_NAME, PCF8563_MAJOR);
+ return -1;
+ }
+
+ printk(KERN_INFO "%s Real-Time Clock Driver, %s\n", PCF8563_NAME,
+ DRIVER_VERSION);
+
+ /* Check for low voltage, and warn about it. */
+ if (voltage_low) {
+ printk(KERN_WARNING "%s: RTC Voltage Low - reliable date/time "
+ "information is no longer guaranteed!\n", PCF8563_NAME);
+ }
-int
-pcf8563_release(struct inode *inode, struct file *filp)
-{
return 0;
}
-module_init(pcf8563_init);
+module_init(pcf8563_register);
module_exit(pcf8563_exit);
/*
- * Simple synchronous serial port driver for ETRAX FS.
+ * Simple synchronous serial port driver for ETRAX FS and Artpec-3.
*
* Copyright (c) 2005 Axis Communications AB
*
#include <linux/spinlock.h>
#include <asm/io.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/sser_defs.h>
-#include <asm/arch/hwregs/dma_defs.h>
-#include <asm/arch/hwregs/dma.h>
-#include <asm/arch/hwregs/intr_vect_defs.h>
-#include <asm/arch/hwregs/intr_vect.h>
-#include <asm/arch/hwregs/reg_map.h>
+#include <dma.h>
+#include <pinmux.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/sser_defs.h>
+#include <hwregs/dma_defs.h>
+#include <hwregs/dma.h>
+#include <hwregs/intr_vect_defs.h>
+#include <hwregs/intr_vect.h>
+#include <hwregs/reg_map.h>
#include <asm/sync_serial.h>
+
/* The receiver is a bit tricky beacuse of the continuous stream of data.*/
/* */
/* Three DMA descriptors are linked together. Each DMA descriptor is */
/* words can be handled */
#define IN_BUFFER_SIZE 12288
#define IN_DESCR_SIZE 256
-#define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE)
-#define OUT_BUFFER_SIZE 4096
+#define NBR_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE)
+
+#define OUT_BUFFER_SIZE 1024*8
+#define NBR_OUT_DESCR 8
#define DEFAULT_FRAME_RATE 0
#define DEFAULT_WORD_RATE 7
#define DEBUGPOLL(x)
#define DEBUGRXINT(x)
#define DEBUGTXINT(x)
+#define DEBUGTRDMA(x)
+#define DEBUGOUTBUF(x)
typedef struct sync_port
{
int output;
int input;
- volatile unsigned int out_count; /* Remaining bytes for current transfer */
- unsigned char* outp; /* Current position in out_buffer */
- volatile unsigned char* volatile readp; /* Next byte to be read by application */
- volatile unsigned char* volatile writep; /* Next byte to be written by etrax */
+ /* Next byte to be read by application */
+ volatile unsigned char *volatile readp;
+ /* Next byte to be written by etrax */
+ volatile unsigned char *volatile writep;
+
unsigned int in_buffer_size;
unsigned int inbufchunk;
unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32)));
unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32)));
struct dma_descr_data* next_rx_desc;
struct dma_descr_data* prev_rx_desc;
+
+ /* Pointer to the first available descriptor in the ring,
+ * unless active_tr_descr == catch_tr_descr and a dma
+ * transfer is active */
+ struct dma_descr_data *active_tr_descr;
+
+ /* Pointer to the first allocated descriptor in the ring */
+ struct dma_descr_data *catch_tr_descr;
+
+ /* Pointer to the descriptor with the current end-of-list */
+ struct dma_descr_data *prev_tr_descr;
int full;
- dma_descr_data in_descr[NUM_IN_DESCR] __attribute__ ((__aligned__(16)));
+ /* Pointer to the first byte being read by DMA
+ * or current position in out_buffer if not using DMA. */
+ unsigned char *out_rd_ptr;
+
+ /* Number of bytes currently locked for being read by DMA */
+ int out_buf_count;
+
+ dma_descr_data in_descr[NBR_IN_DESCR] __attribute__ ((__aligned__(16)));
dma_descr_context in_context __attribute__ ((__aligned__(32)));
- dma_descr_data out_descr __attribute__ ((__aligned__(16)));
+ dma_descr_data out_descr[NBR_OUT_DESCR]
+ __attribute__ ((__aligned__(16)));
dma_descr_context out_context __attribute__ ((__aligned__(32)));
wait_queue_head_t out_wait_q;
wait_queue_head_t in_wait_q;
#endif
static void send_word(sync_port* port);
-static void start_dma(struct sync_port *port, const char* data, int count);
+static void start_dma_out(struct sync_port *port, const char *data, int count);
static void start_dma_in(sync_port* port);
#ifdef SYNC_SER_DMA
-static irqreturn_t tr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
-static irqreturn_t rx_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static irqreturn_t tr_interrupt(int irq, void *dev_id);
+static irqreturn_t rx_interrupt(int irq, void *dev_id);
#endif
#if (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
#define SYNC_SER_MANUAL
#endif
#ifdef SYNC_SER_MANUAL
-static irqreturn_t manual_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static irqreturn_t manual_interrupt(int irq, void *dev_id);
+#endif
+
+#ifdef CONFIG_ETRAXFS /* ETRAX FS */
+#define OUT_DMA_NBR 4
+#define IN_DMA_NBR 5
+#define PINMUX_SSER pinmux_sser0
+#define SYNCSER_INST regi_sser0
+#define SYNCSER_INTR_VECT SSER0_INTR_VECT
+#define OUT_DMA_INST regi_dma4
+#define IN_DMA_INST regi_dma5
+#define DMA_OUT_INTR_VECT DMA4_INTR_VECT
+#define DMA_IN_INTR_VECT DMA5_INTR_VECT
+#define REQ_DMA_SYNCSER dma_sser0
+#else /* Artpec-3 */
+#define OUT_DMA_NBR 6
+#define IN_DMA_NBR 7
+#define PINMUX_SSER pinmux_sser
+#define SYNCSER_INST regi_sser
+#define SYNCSER_INTR_VECT SSER_INTR_VECT
+#define OUT_DMA_INST regi_dma6
+#define IN_DMA_INST regi_dma7
+#define DMA_OUT_INTR_VECT DMA6_INTR_VECT
+#define DMA_IN_INTR_VECT DMA7_INTR_VECT
+#define REQ_DMA_SYNCSER dma_sser
#endif
/* The ports */
static struct sync_port ports[]=
{
{
- .regi_sser = regi_sser0,
- .regi_dmaout = regi_dma4,
- .regi_dmain = regi_dma5,
+ .regi_sser = SYNCSER_INST,
+ .regi_dmaout = OUT_DMA_INST,
+ .regi_dmain = IN_DMA_INST,
#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
.use_dma = 1,
#else
.use_dma = 0,
#endif
- },
+ }
+#ifdef CONFIG_ETRAXFS
+ ,
+
{
.regi_sser = regi_sser1,
.regi_dmaout = regi_dma6,
.use_dma = 0,
#endif
}
+#endif
};
-#define NUMBER_OF_PORTS ARRAY_SIZE(ports)
+#define NBR_PORTS ARRAY_SIZE(ports)
static const struct file_operations sync_serial_fops = {
.owner = THIS_MODULE,
static int __init etrax_sync_serial_init(void)
{
ports[0].enabled = 0;
+#ifdef CONFIG_ETRAXFS
ports[1].enabled = 0;
-
- if (register_chrdev(SYNC_SERIAL_MAJOR,"sync serial", &sync_serial_fops) <0 )
- {
- printk("unable to get major for synchronous serial port\n");
+#endif
+ if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial",
+ &sync_serial_fops) < 0) {
+ printk(KERN_WARNING
+ "Unable to get major for synchronous serial port\n");
return -EBUSY;
}
/* Initialize Ports */
#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
- if (crisv32_pinmux_alloc_fixed(pinmux_sser0))
- {
- printk("Unable to allocate pins for syncrhronous serial port 0\n");
+ if (crisv32_pinmux_alloc_fixed(PINMUX_SSER)) {
+ printk(KERN_WARNING
+ "Unable to alloc pins for synchronous serial port 0\n");
return -EIO;
}
ports[0].enabled = 1;
#endif
#if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
- if (crisv32_pinmux_alloc_fixed(pinmux_sser1))
- {
- printk("Unable to allocate pins for syncrhronous serial port 0\n");
+ if (crisv32_pinmux_alloc_fixed(pinmux_sser1)) {
+ printk(KERN_WARNING
+ "Unable to alloc pins for synchronous serial port 0\n");
return -EIO;
}
ports[1].enabled = 1;
initialize_port(1);
#endif
- printk("ETRAX FS synchronous serial port driver\n");
+#ifdef CONFIG_ETRAXFS
+ printk(KERN_INFO "ETRAX FS synchronous serial port driver\n");
+#else
+ printk(KERN_INFO "Artpec-3 synchronous serial port driver\n");
+#endif
return 0;
}
static void __init initialize_port(int portnbr)
{
- struct sync_port* port = &ports[portnbr];
+ int __attribute__((unused)) i;
+ struct sync_port *port = &ports[portnbr];
reg_sser_rw_cfg cfg = {0};
reg_sser_rw_frm_cfg frm_cfg = {0};
reg_sser_rw_tr_cfg tr_cfg = {0};
reg_sser_rw_rec_cfg rec_cfg = {0};
- DEBUG(printk("Init sync serial port %d\n", portnbr));
+ DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr));
port->port_nbr = portnbr;
port->init_irqs = 1;
- port->outp = port->out_buffer;
+ port->out_rd_ptr = port->out_buffer;
+ port->out_buf_count = 0;
+
port->output = 1;
port->input = 0;
port->in_buffer_size = IN_BUFFER_SIZE;
port->inbufchunk = IN_DESCR_SIZE;
port->next_rx_desc = &port->in_descr[0];
- port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1];
+ port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR-1];
port->prev_rx_desc->eol = 1;
init_waitqueue_head(&port->out_wait_q);
tr_cfg.sample_size = 7;
tr_cfg.sh_dir = regk_sser_msbfirst;
tr_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
+#if 0
tr_cfg.rate_ctrl = regk_sser_bulk;
tr_cfg.data_pin_use = regk_sser_dout;
+#else
+ tr_cfg.rate_ctrl = regk_sser_iso;
+ tr_cfg.data_pin_use = regk_sser_dout;
+#endif
tr_cfg.bulk_wspace = 1;
REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
rec_cfg.use_dma = port->use_dma ? regk_sser_yes : regk_sser_no;
rec_cfg.fifo_thr = regk_sser_inf;
REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
+
+#ifdef SYNC_SER_DMA
+ /* Setup the descriptor ring for dma out/transmit. */
+ for (i = 0; i < NBR_OUT_DESCR; i++) {
+ port->out_descr[i].wait = 0;
+ port->out_descr[i].intr = 1;
+ port->out_descr[i].eol = 0;
+ port->out_descr[i].out_eop = 0;
+ port->out_descr[i].next =
+ (dma_descr_data *)virt_to_phys(&port->out_descr[i+1]);
+ }
+
+ /* Create a ring from the list. */
+ port->out_descr[NBR_OUT_DESCR-1].next =
+ (dma_descr_data *)virt_to_phys(&port->out_descr[0]);
+
+ /* Setup context for traversing the ring. */
+ port->active_tr_descr = &port->out_descr[0];
+ port->prev_tr_descr = &port->out_descr[NBR_OUT_DESCR-1];
+ port->catch_tr_descr = &port->out_descr[0];
+#endif
}
static inline int sync_data_avail(struct sync_port *port)
* ^rp ^wp ^wp ^rp
*/
- if (end >= start)
+ if (end >= start)
avail = end - start;
else
avail = port->in_buffer_size - (start - end);
* ^rp ^wp ^wp ^rp
*/
- if (end >= start)
+ if (end >= start)
avail = end - start;
else
avail = port->flip + port->in_buffer_size - start;
static int sync_serial_open(struct inode *inode, struct file *file)
{
int dev = iminor(inode);
- sync_port* port;
+ sync_port *port;
reg_dma_rw_cfg cfg = {.en = regk_dma_yes};
reg_dma_rw_intr_mask intr_mask = {.data = regk_dma_yes};
- DEBUG(printk("Open sync serial port %d\n", dev));
+ DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev));
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
+ if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
{
- DEBUG(printk("Invalid minor %d\n", dev));
+ DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
return -ENODEV;
}
port = &ports[dev];
/* Allow open this device twice (assuming one reader and one writer) */
if (port->busy == 2)
{
- DEBUG(printk("Device is busy.. \n"));
+ DEBUG(printk(KERN_DEBUG "Device is busy.. \n"));
return -EBUSY;
}
+
+
if (port->init_irqs) {
if (port->use_dma) {
- if (port == &ports[0]){
+ if (port == &ports[0]) {
#ifdef SYNC_SER_DMA
- if(request_irq(DMA4_INTR_VECT,
- tr_interrupt,
- 0,
- "synchronous serial 0 dma tr",
- &ports[0])) {
+ if (request_irq(DMA_OUT_INTR_VECT,
+ tr_interrupt,
+ 0,
+ "synchronous serial 0 dma tr",
+ &ports[0])) {
printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ");
return -EBUSY;
- } else if(request_irq(DMA5_INTR_VECT,
- rx_interrupt,
- 0,
- "synchronous serial 1 dma rx",
- &ports[0])) {
- free_irq(DMA4_INTR_VECT, &port[0]);
+ } else if (request_irq(DMA_IN_INTR_VECT,
+ rx_interrupt,
+ 0,
+ "synchronous serial 1 dma rx",
+ &ports[0])) {
+ free_irq(DMA_OUT_INTR_VECT, &port[0]);
printk(KERN_CRIT "Can't allocate sync serial port 0 IRQ");
return -EBUSY;
- } else if (crisv32_request_dma(SYNC_SER0_TX_DMA_NBR,
- "synchronous serial 0 dma tr",
- DMA_VERBOSE_ON_ERROR,
- 0,
- dma_sser0)) {
- free_irq(DMA4_INTR_VECT, &port[0]);
- free_irq(DMA5_INTR_VECT, &port[0]);
+ } else if (crisv32_request_dma(OUT_DMA_NBR,
+ "synchronous serial 0 dma tr",
+ DMA_VERBOSE_ON_ERROR,
+ 0,
+ REQ_DMA_SYNCSER)) {
+ free_irq(DMA_OUT_INTR_VECT, &port[0]);
+ free_irq(DMA_IN_INTR_VECT, &port[0]);
printk(KERN_CRIT "Can't allocate sync serial port 0 TX DMA channel");
return -EBUSY;
- } else if (crisv32_request_dma(SYNC_SER0_RX_DMA_NBR,
- "synchronous serial 0 dma rec",
- DMA_VERBOSE_ON_ERROR,
- 0,
- dma_sser0)) {
- crisv32_free_dma(SYNC_SER0_TX_DMA_NBR);
- free_irq(DMA4_INTR_VECT, &port[0]);
- free_irq(DMA5_INTR_VECT, &port[0]);
+ } else if (crisv32_request_dma(IN_DMA_NBR,
+ "synchronous serial 0 dma rec",
+ DMA_VERBOSE_ON_ERROR,
+ 0,
+ REQ_DMA_SYNCSER)) {
+ crisv32_free_dma(OUT_DMA_NBR);
+ free_irq(DMA_OUT_INTR_VECT, &port[0]);
+ free_irq(DMA_IN_INTR_VECT, &port[0]);
printk(KERN_CRIT "Can't allocate sync serial port 1 RX DMA channel");
return -EBUSY;
}
#endif
}
- else if (port == &ports[1]){
+#ifdef CONFIG_ETRAXFS
+ else if (port == &ports[1]) {
#ifdef SYNC_SER_DMA
if (request_irq(DMA6_INTR_VECT,
tr_interrupt,
free_irq(DMA6_INTR_VECT, &ports[1]);
printk(KERN_CRIT "Can't allocate sync serial port 3 IRQ");
return -EBUSY;
- } else if (crisv32_request_dma(SYNC_SER1_TX_DMA_NBR,
- "synchronous serial 1 dma tr",
- DMA_VERBOSE_ON_ERROR,
- 0,
- dma_sser1)) {
- free_irq(21, &ports[1]);
- free_irq(20, &ports[1]);
+ } else if (crisv32_request_dma(
+ SYNC_SER1_TX_DMA_NBR,
+ "synchronous serial 1 dma tr",
+ DMA_VERBOSE_ON_ERROR,
+ 0,
+ dma_sser1)) {
+ free_irq(DMA6_INTR_VECT, &ports[1]);
+ free_irq(DMA7_INTR_VECT, &ports[1]);
printk(KERN_CRIT "Can't allocate sync serial port 3 TX DMA channel");
return -EBUSY;
- } else if (crisv32_request_dma(SYNC_SER1_RX_DMA_NBR,
- "synchronous serial 3 dma rec",
- DMA_VERBOSE_ON_ERROR,
- 0,
- dma_sser1)) {
+ } else if (crisv32_request_dma(
+ SYNC_SER1_RX_DMA_NBR,
+ "synchronous serial 3 dma rec",
+ DMA_VERBOSE_ON_ERROR,
+ 0,
+ dma_sser1)) {
crisv32_free_dma(SYNC_SER1_TX_DMA_NBR);
free_irq(DMA6_INTR_VECT, &ports[1]);
free_irq(DMA7_INTR_VECT, &ports[1]);
}
#endif
}
-
+#endif
/* Enable DMAs */
REG_WR(dma, port->regi_dmain, rw_cfg, cfg);
REG_WR(dma, port->regi_dmaout, rw_cfg, cfg);
/* Enable DMA IRQs */
REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask);
REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask);
- /* Set up wordsize = 2 for DMAs. */
+ /* Set up wordsize = 1 for DMAs. */
DMA_WR_CMD (port->regi_dmain, regk_dma_set_w_size1);
DMA_WR_CMD (port->regi_dmaout, regk_dma_set_w_size1);
} else { /* !port->use_dma */
#ifdef SYNC_SER_MANUAL
if (port == &ports[0]) {
- if (request_irq(SSER0_INTR_VECT,
+ if (request_irq(SYNCSER_INTR_VECT,
manual_interrupt,
0,
"synchronous serial manual irq",
printk("Can't allocate sync serial manual irq");
return -EBUSY;
}
- } else if (port == &ports[1]) {
+ }
+#ifdef CONFIG_ETRAXFS
+ else if (port == &ports[1]) {
if (request_irq(SSER1_INTR_VECT,
manual_interrupt,
0,
return -EBUSY;
}
}
+#endif
port->init_irqs = 0;
#else
panic("sync_serial: Manual mode not supported.\n");
#endif /* SYNC_SER_MANUAL */
}
+
} /* port->init_irqs */
port->busy++;
static int sync_serial_release(struct inode *inode, struct file *file)
{
int dev = iminor(inode);
- sync_port* port;
+ sync_port *port;
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
+ if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
{
DEBUG(printk("Invalid minor %d\n", dev));
return -ENODEV;
{
int dev = iminor(file->f_path.dentry->d_inode);
unsigned int mask = 0;
- sync_port* port;
+ sync_port *port;
DEBUGPOLL( static unsigned int prev_mask = 0; );
port = &ports[dev];
+
+ if (!port->started) {
+ reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
+ reg_sser_rw_rec_cfg rec_cfg =
+ REG_RD(sser, port->regi_sser, rw_rec_cfg);
+ cfg.en = regk_sser_yes;
+ rec_cfg.rec_en = port->input;
+ REG_WR(sser, port->regi_sser, rw_cfg, cfg);
+ REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
+ port->started = 1;
+ }
+
poll_wait(file, &port->out_wait_q, wait);
poll_wait(file, &port->in_wait_q, wait);
- /* Some room to write */
- if (port->out_count < OUT_BUFFER_SIZE)
+
+ /* No active transfer, descriptors are available */
+ if (port->output && !port->tr_running)
+ mask |= POLLOUT | POLLWRNORM;
+
+ /* Descriptor and buffer space available. */
+ if (port->output &&
+ port->active_tr_descr != port->catch_tr_descr &&
+ port->out_buf_count < OUT_BUFFER_SIZE)
mask |= POLLOUT | POLLWRNORM;
+
/* At least an inbufchunk of data */
- if (sync_data_avail(port) >= port->inbufchunk)
+ if (port->input && sync_data_avail(port) >= port->inbufchunk)
mask |= POLLIN | POLLRDNORM;
DEBUGPOLL(if (mask != prev_mask)
unsigned int cmd, unsigned long arg)
{
int return_val = 0;
+ int dma_w_size = regk_dma_set_w_size1;
int dev = iminor(file->f_path.dentry->d_inode);
- sync_port* port;
+ sync_port *port;
reg_sser_rw_tr_cfg tr_cfg;
reg_sser_rw_rec_cfg rec_cfg;
reg_sser_rw_frm_cfg frm_cfg;
reg_sser_rw_cfg gen_cfg;
reg_sser_rw_intr_mask intr_mask;
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
+ if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
{
DEBUG(printk("Invalid minor %d\n", dev));
return -1;
case SSP_SPEED:
if (GET_SPEED(arg) == CODEC)
{
+ unsigned int freq;
+
gen_cfg.base_freq = regk_sser_f32;
- /* FREQ = 0 => 4 MHz => clk_div = 7*/
- gen_cfg.clk_div = 6 + (1 << GET_FREQ(arg));
- }
- else
- {
+
+ /* Clock divider will internally be
+ * gen_cfg.clk_div + 1.
+ */
+
+ freq = GET_FREQ(arg);
+ switch (freq) {
+ case FREQ_32kHz:
+ case FREQ_64kHz:
+ case FREQ_128kHz:
+ case FREQ_256kHz:
+ gen_cfg.clk_div = 125 *
+ (1 << (freq - FREQ_256kHz)) - 1;
+ break;
+ case FREQ_512kHz:
+ gen_cfg.clk_div = 62;
+ break;
+ case FREQ_1MHz:
+ case FREQ_2MHz:
+ case FREQ_4MHz:
+ gen_cfg.clk_div = 8 * (1 << freq) - 1;
+ break;
+ }
+ } else {
gen_cfg.base_freq = regk_sser_f29_493;
- switch (GET_SPEED(arg))
- {
- case SSP150:
- gen_cfg.clk_div = 29493000 / (150 * 8) - 1;
- break;
- case SSP300:
- gen_cfg.clk_div = 29493000 / (300 * 8) - 1;
- break;
- case SSP600:
- gen_cfg.clk_div = 29493000 / (600 * 8) - 1;
- break;
- case SSP1200:
- gen_cfg.clk_div = 29493000 / (1200 * 8) - 1;
- break;
- case SSP2400:
- gen_cfg.clk_div = 29493000 / (2400 * 8) - 1;
- break;
- case SSP4800:
- gen_cfg.clk_div = 29493000 / (4800 * 8) - 1;
- break;
- case SSP9600:
- gen_cfg.clk_div = 29493000 / (9600 * 8) - 1;
- break;
- case SSP19200:
- gen_cfg.clk_div = 29493000 / (19200 * 8) - 1;
- break;
- case SSP28800:
- gen_cfg.clk_div = 29493000 / (28800 * 8) - 1;
- break;
- case SSP57600:
- gen_cfg.clk_div = 29493000 / (57600 * 8) - 1;
- break;
- case SSP115200:
- gen_cfg.clk_div = 29493000 / (115200 * 8) - 1;
- break;
- case SSP230400:
- gen_cfg.clk_div = 29493000 / (230400 * 8) - 1;
- break;
- case SSP460800:
- gen_cfg.clk_div = 29493000 / (460800 * 8) - 1;
- break;
- case SSP921600:
- gen_cfg.clk_div = 29493000 / (921600 * 8) - 1;
- break;
- case SSP3125000:
- gen_cfg.base_freq = regk_sser_f100;
- gen_cfg.clk_div = 100000000 / (3125000 * 8) - 1;
- break;
+ switch (GET_SPEED(arg)) {
+ case SSP150:
+ gen_cfg.clk_div = 29493000 / (150 * 8) - 1;
+ break;
+ case SSP300:
+ gen_cfg.clk_div = 29493000 / (300 * 8) - 1;
+ break;
+ case SSP600:
+ gen_cfg.clk_div = 29493000 / (600 * 8) - 1;
+ break;
+ case SSP1200:
+ gen_cfg.clk_div = 29493000 / (1200 * 8) - 1;
+ break;
+ case SSP2400:
+ gen_cfg.clk_div = 29493000 / (2400 * 8) - 1;
+ break;
+ case SSP4800:
+ gen_cfg.clk_div = 29493000 / (4800 * 8) - 1;
+ break;
+ case SSP9600:
+ gen_cfg.clk_div = 29493000 / (9600 * 8) - 1;
+ break;
+ case SSP19200:
+ gen_cfg.clk_div = 29493000 / (19200 * 8) - 1;
+ break;
+ case SSP28800:
+ gen_cfg.clk_div = 29493000 / (28800 * 8) - 1;
+ break;
+ case SSP57600:
+ gen_cfg.clk_div = 29493000 / (57600 * 8) - 1;
+ break;
+ case SSP115200:
+ gen_cfg.clk_div = 29493000 / (115200 * 8) - 1;
+ break;
+ case SSP230400:
+ gen_cfg.clk_div = 29493000 / (230400 * 8) - 1;
+ break;
+ case SSP460800:
+ gen_cfg.clk_div = 29493000 / (460800 * 8) - 1;
+ break;
+ case SSP921600:
+ gen_cfg.clk_div = 29493000 / (921600 * 8) - 1;
+ break;
+ case SSP3125000:
+ gen_cfg.base_freq = regk_sser_f100;
+ gen_cfg.clk_div = 100000000 / (3125000 * 8) - 1;
+ break;
}
}
case MASTER_OUTPUT:
port->output = 1;
port->input = 0;
+ frm_cfg.out_on = regk_sser_tr;
+ frm_cfg.frame_pin_dir = regk_sser_out;
gen_cfg.clk_dir = regk_sser_out;
break;
case SLAVE_OUTPUT:
port->output = 1;
port->input = 0;
+ frm_cfg.frame_pin_dir = regk_sser_in;
gen_cfg.clk_dir = regk_sser_in;
break;
case MASTER_INPUT:
port->output = 0;
port->input = 1;
+ frm_cfg.frame_pin_dir = regk_sser_out;
+ frm_cfg.out_on = regk_sser_intern_tb;
gen_cfg.clk_dir = regk_sser_out;
break;
case SLAVE_INPUT:
port->output = 0;
port->input = 1;
+ frm_cfg.frame_pin_dir = regk_sser_in;
gen_cfg.clk_dir = regk_sser_in;
break;
case MASTER_BIDIR:
port->output = 1;
port->input = 1;
+ frm_cfg.frame_pin_dir = regk_sser_out;
+ frm_cfg.out_on = regk_sser_intern_tb;
gen_cfg.clk_dir = regk_sser_out;
break;
case SLAVE_BIDIR:
port->output = 1;
port->input = 1;
+ frm_cfg.frame_pin_dir = regk_sser_in;
gen_cfg.clk_dir = regk_sser_in;
break;
default:
spin_unlock_irq(&port->lock);
return -EINVAL;
-
}
if (!port->use_dma || (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT))
intr_mask.rdav = regk_sser_yes;
break;
case SSP_FRAME_SYNC:
- if (arg & NORMAL_SYNC)
+ if (arg & NORMAL_SYNC) {
+ frm_cfg.rec_delay = 1;
frm_cfg.tr_delay = 1;
+ }
else if (arg & EARLY_SYNC)
- frm_cfg.tr_delay = 0;
+ frm_cfg.rec_delay = frm_cfg.tr_delay = 0;
+ else if (arg & SECOND_WORD_SYNC) {
+ frm_cfg.rec_delay = 7;
+ frm_cfg.tr_delay = 1;
+ }
tr_cfg.bulk_wspace = frm_cfg.tr_delay;
frm_cfg.early_wend = regk_sser_yes;
else if (arg & SYNC_OFF)
frm_cfg.frame_pin_use = regk_sser_gio0;
- if (arg & WORD_SIZE_8)
+ dma_w_size = regk_dma_set_w_size2;
+ if (arg & WORD_SIZE_8) {
rec_cfg.sample_size = tr_cfg.sample_size = 7;
- else if (arg & WORD_SIZE_12)
+ dma_w_size = regk_dma_set_w_size1;
+ } else if (arg & WORD_SIZE_12)
rec_cfg.sample_size = tr_cfg.sample_size = 11;
else if (arg & WORD_SIZE_16)
rec_cfg.sample_size = tr_cfg.sample_size = 15;
else if (arg & BIT_ORDER_LSB)
rec_cfg.sh_dir = tr_cfg.sh_dir = regk_sser_lsbfirst;
- if (arg & FLOW_CONTROL_ENABLE)
+ if (arg & FLOW_CONTROL_ENABLE) {
+ frm_cfg.status_pin_use = regk_sser_frm;
rec_cfg.fifo_thr = regk_sser_thr16;
- else if (arg & FLOW_CONTROL_DISABLE)
+ } else if (arg & FLOW_CONTROL_DISABLE) {
+ frm_cfg.status_pin_use = regk_sser_gio0;
rec_cfg.fifo_thr = regk_sser_inf;
+ }
if (arg & CLOCK_NOT_GATED)
gen_cfg.gate_clk = regk_sser_no;
break;
case SSP_OPOLARITY:
if (arg & CLOCK_NORMAL)
- gen_cfg.out_clk_pol = regk_sser_neg;
- else if (arg & CLOCK_INVERT)
gen_cfg.out_clk_pol = regk_sser_pos;
+ else if (arg & CLOCK_INVERT)
+ gen_cfg.out_clk_pol = regk_sser_neg;
if (arg & FRAME_NORMAL)
frm_cfg.level = regk_sser_pos_hi;
}
- if (port->started)
- {
- tr_cfg.tr_en = port->output;
+ if (port->started) {
rec_cfg.rec_en = port->input;
+ gen_cfg.en = (port->output | port->input);
}
REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
+
+ if (cmd == SSP_FRAME_SYNC && (arg & (WORD_SIZE_8 | WORD_SIZE_12 |
+ WORD_SIZE_16 | WORD_SIZE_24 | WORD_SIZE_32))) {
+ int en = gen_cfg.en;
+ gen_cfg.en = 0;
+ REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
+ /* ##### Should DMA be stoped before we change dma size? */
+ DMA_WR_CMD(port->regi_dmain, dma_w_size);
+ DMA_WR_CMD(port->regi_dmaout, dma_w_size);
+ gen_cfg.en = en;
+ REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg);
+ }
+
spin_unlock_irq(&port->lock);
return return_val;
}
-static ssize_t sync_serial_write(struct file * file, const char * buf,
- size_t count, loff_t *ppos)
+/* NOTE: sync_serial_write does not support concurrency */
+static ssize_t sync_serial_write(struct file *file, const char *buf,
+ size_t count, loff_t *ppos)
{
int dev = iminor(file->f_path.dentry->d_inode);
DECLARE_WAITQUEUE(wait, current);
- sync_port *port;
- unsigned long c, c1;
- unsigned long free_outp;
- unsigned long outp;
- unsigned long out_buffer;
+ struct sync_port *port;
+ int trunc_count;
unsigned long flags;
+ int bytes_free;
+ int out_buf_count;
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
- {
+ unsigned char *rd_ptr; /* First allocated byte in the buffer */
+ unsigned char *wr_ptr; /* First free byte in the buffer */
+ unsigned char *buf_stop_ptr; /* Last byte + 1 */
+
+ if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled) {
DEBUG(printk("Invalid minor %d\n", dev));
return -ENODEV;
}
port = &ports[dev];
- DEBUGWRITE(printk("W d%d c %lu (%d/%d)\n", port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE));
- /* Space to end of buffer */
- /*
- * out_buffer <c1>012345<- c ->OUT_BUFFER_SIZE
- * outp^ +out_count
- ^free_outp
- * out_buffer 45<- c ->0123OUT_BUFFER_SIZE
- * +out_count outp^
- * free_outp
- *
+ /* |<- OUT_BUFFER_SIZE ->|
+ * |<- out_buf_count ->|
+ * |<- trunc_count ->| ...->|
+ * ______________________________________________________
+ * | free | data | free |
+ * |_________|___________________|________________________|
+ * ^ rd_ptr ^ wr_ptr
*/
+ DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu a: %p c: %p\n",
+ port->port_nbr, count, port->active_tr_descr,
+ port->catch_tr_descr));
/* Read variables that may be updated by interrupts */
spin_lock_irqsave(&port->lock, flags);
- count = count > OUT_BUFFER_SIZE - port->out_count ? OUT_BUFFER_SIZE - port->out_count : count;
- outp = (unsigned long)port->outp;
- free_outp = outp + port->out_count;
+ rd_ptr = port->out_rd_ptr;
+ out_buf_count = port->out_buf_count;
spin_unlock_irqrestore(&port->lock, flags);
- out_buffer = (unsigned long)port->out_buffer;
- /* Find out where and how much to write */
- if (free_outp >= out_buffer + OUT_BUFFER_SIZE)
- free_outp -= OUT_BUFFER_SIZE;
- if (free_outp >= outp)
- c = out_buffer + OUT_BUFFER_SIZE - free_outp;
- else
- c = outp - free_outp;
- if (c > count)
- c = count;
+ /* Check if resources are available */
+ if (port->tr_running &&
+ ((port->use_dma && port->active_tr_descr == port->catch_tr_descr) ||
+ out_buf_count >= OUT_BUFFER_SIZE)) {
+ DEBUGWRITE(printk(KERN_DEBUG "sser%d full\n", dev));
+ return -EAGAIN;
+ }
+
+ buf_stop_ptr = port->out_buffer + OUT_BUFFER_SIZE;
+
+ /* Determine pointer to the first free byte, before copying. */
+ wr_ptr = rd_ptr + out_buf_count;
+ if (wr_ptr >= buf_stop_ptr)
+ wr_ptr -= OUT_BUFFER_SIZE;
-// DEBUGWRITE(printk("w op %08lX fop %08lX c %lu\n", outp, free_outp, c));
- if (copy_from_user((void*)free_outp, buf, c))
+ /* If we wrap the ring buffer, let the user space program handle it by
+ * truncating the data. This could be more elegant, small buffer
+ * fragments may occur.
+ */
+ bytes_free = OUT_BUFFER_SIZE - out_buf_count;
+ if (wr_ptr + bytes_free > buf_stop_ptr)
+ bytes_free = buf_stop_ptr - wr_ptr;
+ trunc_count = (count < bytes_free) ? count : bytes_free;
+
+ if (copy_from_user(wr_ptr, buf, trunc_count))
return -EFAULT;
- if (c != count) {
- buf += c;
- c1 = count - c;
- DEBUGWRITE(printk("w2 fi %lu c %lu c1 %lu\n", free_outp-out_buffer, c, c1));
- if (copy_from_user((void*)out_buffer, buf, c1))
- return -EFAULT;
- }
- spin_lock_irqsave(&port->lock, flags);
- port->out_count += count;
- spin_unlock_irqrestore(&port->lock, flags);
+ DEBUGOUTBUF(printk(KERN_DEBUG "%-4d + %-4d = %-4d %p %p %p\n",
+ out_buf_count, trunc_count,
+ port->out_buf_count, port->out_buffer,
+ wr_ptr, buf_stop_ptr));
/* Make sure transmitter/receiver is running */
- if (!port->started)
- {
+ if (!port->started) {
reg_sser_rw_cfg cfg = REG_RD(sser, port->regi_sser, rw_cfg);
- reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser, rw_tr_cfg);
reg_sser_rw_rec_cfg rec_cfg = REG_RD(sser, port->regi_sser, rw_rec_cfg);
cfg.en = regk_sser_yes;
- tr_cfg.tr_en = port->output;
rec_cfg.rec_en = port->input;
REG_WR(sser, port->regi_sser, rw_cfg, cfg);
- REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg);
port->started = 1;
}
- if (file->f_flags & O_NONBLOCK) {
- spin_lock_irqsave(&port->lock, flags);
- if (!port->tr_running) {
- if (!port->use_dma) {
- reg_sser_rw_intr_mask intr_mask;
- intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
- /* Start sender by writing data */
- send_word(port);
- /* and enable transmitter ready IRQ */
- intr_mask.trdy = 1;
- REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
- } else {
- start_dma(port, (unsigned char* volatile )port->outp, c);
- }
- }
- spin_unlock_irqrestore(&port->lock, flags);
- DEBUGWRITE(printk("w d%d c %lu NB\n",
- port->port_nbr, count));
- return count;
+ /* Setup wait if blocking */
+ if (!(file->f_flags & O_NONBLOCK)) {
+ add_wait_queue(&port->out_wait_q, &wait);
+ set_current_state(TASK_INTERRUPTIBLE);
}
- /* Sleep until all sent */
-
- add_wait_queue(&port->out_wait_q, &wait);
- set_current_state(TASK_INTERRUPTIBLE);
spin_lock_irqsave(&port->lock, flags);
- if (!port->tr_running) {
- if (!port->use_dma) {
- reg_sser_rw_intr_mask intr_mask;
- intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
- /* Start sender by writing data */
- send_word(port);
- /* and enable transmitter ready IRQ */
- intr_mask.trdy = 1;
- REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
- } else {
- start_dma(port, port->outp, c);
- }
+ port->out_buf_count += trunc_count;
+ if (port->use_dma) {
+ start_dma_out(port, wr_ptr, trunc_count);
+ } else if (!port->tr_running) {
+ reg_sser_rw_intr_mask intr_mask;
+ intr_mask = REG_RD(sser, port->regi_sser, rw_intr_mask);
+ /* Start sender by writing data */
+ send_word(port);
+ /* and enable transmitter ready IRQ */
+ intr_mask.trdy = 1;
+ REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask);
}
spin_unlock_irqrestore(&port->lock, flags);
+
+ /* Exit if non blocking */
+ if (file->f_flags & O_NONBLOCK) {
+ DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu %08x\n",
+ port->port_nbr, trunc_count,
+ REG_RD_INT(dma, port->regi_dmaout, r_intr)));
+ return trunc_count;
+ }
+
schedule();
set_current_state(TASK_RUNNING);
remove_wait_queue(&port->out_wait_q, &wait);
+
if (signal_pending(current))
- {
return -EINTR;
- }
- DEBUGWRITE(printk("w d%d c %lu\n", port->port_nbr, count));
- return count;
+
+ DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n",
+ port->port_nbr, trunc_count));
+ return trunc_count;
}
static ssize_t sync_serial_read(struct file * file, char * buf,
unsigned char* end;
unsigned long flags;
- if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled)
+ if (dev < 0 || dev >= NBR_PORTS || !ports[dev].enabled)
{
DEBUG(printk("Invalid minor %d\n", dev));
return -ENODEV;
port->started = 1;
}
-
/* Calculate number of available bytes */
/* Save pointers to avoid that they are modified by interrupt */
spin_lock_irqsave(&port->lock, flags);
spin_unlock_irqrestore(&port->lock, flags);
while ((start == end) && !port->full) /* No data */
{
+ DEBUGREAD(printk(KERN_DEBUG "&"));
if (file->f_flags & O_NONBLOCK)
- {
return -EAGAIN;
- }
interruptible_sleep_on(&port->in_wait_q);
if (signal_pending(current))
- {
return -EINTR;
- }
+
spin_lock_irqsave(&port->lock, flags);
start = (unsigned char*)port->readp; /* cast away volatile */
end = (unsigned char*)port->writep; /* cast away volatile */
switch(tr_cfg.sample_size)
{
case 8:
- port->out_count--;
- tr_data.data = *port->outp++;
+ port->out_buf_count--;
+ tr_data.data = *port->out_rd_ptr++;
REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
+ if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
+ port->out_rd_ptr = port->out_buffer;
break;
case 12:
{
- int data = (*port->outp++) << 8;
- data |= *port->outp++;
- port->out_count-=2;
+ int data = (*port->out_rd_ptr++) << 8;
+ data |= *port->out_rd_ptr++;
+ port->out_buf_count -= 2;
tr_data.data = data;
REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
+ if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
+ port->out_rd_ptr = port->out_buffer;
}
break;
case 16:
- port->out_count-=2;
- tr_data.data = *(unsigned short *)port->outp;
+ port->out_buf_count -= 2;
+ tr_data.data = *(unsigned short *)port->out_rd_ptr;
REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->outp+=2;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
+ port->out_rd_ptr += 2;
+ if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
+ port->out_rd_ptr = port->out_buffer;
break;
case 24:
- port->out_count-=3;
- tr_data.data = *(unsigned short *)port->outp;
+ port->out_buf_count -= 3;
+ tr_data.data = *(unsigned short *)port->out_rd_ptr;
REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->outp+=2;
- tr_data.data = *port->outp++;
+ port->out_rd_ptr += 2;
+ tr_data.data = *port->out_rd_ptr++;
REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
+ if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
+ port->out_rd_ptr = port->out_buffer;
break;
case 32:
- port->out_count-=4;
- tr_data.data = *(unsigned short *)port->outp;
+ port->out_buf_count -= 4;
+ tr_data.data = *(unsigned short *)port->out_rd_ptr;
REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->outp+=2;
- tr_data.data = *(unsigned short *)port->outp;
+ port->out_rd_ptr += 2;
+ tr_data.data = *(unsigned short *)port->out_rd_ptr;
REG_WR(sser, port->regi_sser, rw_tr_data, tr_data);
- port->outp+=2;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
+ port->out_rd_ptr += 2;
+ if (port->out_rd_ptr >= port->out_buffer + OUT_BUFFER_SIZE)
+ port->out_rd_ptr = port->out_buffer;
break;
}
}
-
-static void start_dma(struct sync_port* port, const char* data, int count)
+static void start_dma_out(struct sync_port *port,
+ const char *data, int count)
{
- port->tr_running = 1;
- port->out_descr.buf = (char*)virt_to_phys((char*)data);
- port->out_descr.after = port->out_descr.buf + count;
- port->out_descr.eol = port->out_descr.intr = 1;
+ port->active_tr_descr->buf = (char *) virt_to_phys((char *) data);
+ port->active_tr_descr->after = port->active_tr_descr->buf + count;
+ port->active_tr_descr->intr = 1;
+
+ port->active_tr_descr->eol = 1;
+ port->prev_tr_descr->eol = 0;
+
+ DEBUGTRDMA(printk(KERN_DEBUG "Inserting eolr:%p eol@:%p\n",
+ port->prev_tr_descr, port->active_tr_descr));
+ port->prev_tr_descr = port->active_tr_descr;
+ port->active_tr_descr = phys_to_virt((int) port->active_tr_descr->next);
+
+ if (!port->tr_running) {
+ reg_sser_rw_tr_cfg tr_cfg = REG_RD(sser, port->regi_sser,
+ rw_tr_cfg);
- port->out_context.saved_data = (dma_descr_data*)virt_to_phys(&port->out_descr);
- port->out_context.saved_data_buf = port->out_descr.buf;
+ port->out_context.next = 0;
+ port->out_context.saved_data =
+ (dma_descr_data *)virt_to_phys(port->prev_tr_descr);
+ port->out_context.saved_data_buf = port->prev_tr_descr->buf;
+
+ DMA_START_CONTEXT(port->regi_dmaout,
+ virt_to_phys((char *)&port->out_context));
+
+ tr_cfg.tr_en = regk_sser_yes;
+ REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
+ DEBUGTRDMA(printk(KERN_DEBUG "dma s\n"););
+ } else {
+ DMA_CONTINUE_DATA(port->regi_dmaout);
+ DEBUGTRDMA(printk(KERN_DEBUG "dma c\n"););
+ }
- DMA_START_CONTEXT(port->regi_dmaout, virt_to_phys((char*)&port->out_context));
- DEBUGTXINT(printk("dma %08lX c %d\n", (unsigned long)data, count));
+ port->tr_running = 1;
}
-static void start_dma_in(sync_port* port)
+static void start_dma_in(sync_port *port)
{
int i;
- char* buf;
+ char *buf;
port->writep = port->flip;
- if (port->writep > port->flip + port->in_buffer_size)
- {
+ if (port->writep > port->flip + port->in_buffer_size) {
panic("Offset too large in sync serial driver\n");
return;
}
buf = (char*)virt_to_phys(port->in_buffer);
- for (i = 0; i < NUM_IN_DESCR; i++) {
+ for (i = 0; i < NBR_IN_DESCR; i++) {
port->in_descr[i].buf = buf;
port->in_descr[i].after = buf + port->inbufchunk;
port->in_descr[i].intr = 1;
port->in_descr[i-1].next = (dma_descr_data*)virt_to_phys(&port->in_descr[0]);
port->in_descr[i-1].eol = regk_sser_yes;
port->next_rx_desc = &port->in_descr[0];
- port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1];
+ port->prev_rx_desc = &port->in_descr[NBR_IN_DESCR - 1];
port->in_context.saved_data = (dma_descr_data*)virt_to_phys(&port->in_descr[0]);
port->in_context.saved_data_buf = port->in_descr[0].buf;
DMA_START_CONTEXT(port->regi_dmain, virt_to_phys(&port->in_context));
}
#ifdef SYNC_SER_DMA
-static irqreturn_t tr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+static irqreturn_t tr_interrupt(int irq, void *dev_id)
{
reg_dma_r_masked_intr masked;
reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes};
+ reg_dma_rw_stat stat;
int i;
- struct dma_descr_data *descr;
- unsigned int sentl;
int found = 0;
+ int stop_sser = 0;
- for (i = 0; i < NUMBER_OF_PORTS; i++)
- {
+ for (i = 0; i < NBR_PORTS; i++) {
sync_port *port = &ports[i];
- if (!port->enabled || !port->use_dma )
+ if (!port->enabled || !port->use_dma)
continue;
+ /* IRQ active for the port? */
masked = REG_RD(dma, port->regi_dmaout, r_masked_intr);
+ if (!masked.data)
+ continue;
- if (masked.data) /* IRQ active for the port? */
- {
- found = 1;
- /* Clear IRQ */
- REG_WR(dma, port->regi_dmaout, rw_ack_intr, ack_intr);
- descr = &port->out_descr;
- sentl = descr->after - descr->buf;
- port->out_count -= sentl;
- port->outp += sentl;
- if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
- port->outp = port->out_buffer;
- if (port->out_count) {
- int c;
- c = port->out_buffer + OUT_BUFFER_SIZE - port->outp;
- if (c > port->out_count)
- c = port->out_count;
- DEBUGTXINT(printk("tx_int DMAWRITE %i %i\n", sentl, c));
- start_dma(port, port->outp, c);
- } else {
- DEBUGTXINT(printk("tx_int DMA stop %i\n", sentl));
- port->tr_running = 0;
+ found = 1;
+
+ /* Check if we should stop the DMA transfer */
+ stat = REG_RD(dma, port->regi_dmaout, rw_stat);
+ if (stat.list_state == regk_dma_data_at_eol)
+ stop_sser = 1;
+
+ /* Clear IRQ */
+ REG_WR(dma, port->regi_dmaout, rw_ack_intr, ack_intr);
+
+ if (!stop_sser) {
+ /* The DMA has completed a descriptor, EOL was not
+ * encountered, so step relevant descriptor and
+ * datapointers forward. */
+ int sent;
+ sent = port->catch_tr_descr->after -
+ port->catch_tr_descr->buf;
+ DEBUGTXINT(printk(KERN_DEBUG "%-4d - %-4d = %-4d\t"
+ "in descr %p (ac: %p)\n",
+ port->out_buf_count, sent,
+ port->out_buf_count - sent,
+ port->catch_tr_descr,
+ port->active_tr_descr););
+ port->out_buf_count -= sent;
+ port->catch_tr_descr =
+ phys_to_virt((int) port->catch_tr_descr->next);
+ port->out_rd_ptr =
+ phys_to_virt((int) port->catch_tr_descr->buf);
+ } else {
+ int i, sent;
+ /* EOL handler.
+ * Note that if an EOL was encountered during the irq
+ * locked section of sync_ser_write the DMA will be
+ * restarted and the eol flag will be cleared.
+ * The remaining descriptors will be traversed by
+ * the descriptor interrupts as usual.
+ */
+ i = 0;
+ while (!port->catch_tr_descr->eol) {
+ sent = port->catch_tr_descr->after -
+ port->catch_tr_descr->buf;
+ DEBUGOUTBUF(printk(KERN_DEBUG
+ "traversing descr %p -%d (%d)\n",
+ port->catch_tr_descr,
+ sent,
+ port->out_buf_count));
+ port->out_buf_count -= sent;
+ port->catch_tr_descr = phys_to_virt(
+ (int)port->catch_tr_descr->next);
+ i++;
+ if (i >= NBR_OUT_DESCR) {
+ /* TODO: Reset and recover */
+ panic("sync_serial: missing eol");
+ }
}
- wake_up_interruptible(&port->out_wait_q); /* wake up the waiting process */
+ sent = port->catch_tr_descr->after -
+ port->catch_tr_descr->buf;
+ DEBUGOUTBUF(printk(KERN_DEBUG
+ "eol at descr %p -%d (%d)\n",
+ port->catch_tr_descr,
+ sent,
+ port->out_buf_count));
+
+ port->out_buf_count -= sent;
+
+ /* Update read pointer to first free byte, we
+ * may already be writing data there. */
+ port->out_rd_ptr =
+ phys_to_virt((int) port->catch_tr_descr->after);
+ if (port->out_rd_ptr > port->out_buffer +
+ OUT_BUFFER_SIZE)
+ port->out_rd_ptr = port->out_buffer;
+
+ reg_sser_rw_tr_cfg tr_cfg =
+ REG_RD(sser, port->regi_sser, rw_tr_cfg);
+ DEBUGTXINT(printk(KERN_DEBUG
+ "tr_int DMA stop %d, set catch @ %p\n",
+ port->out_buf_count,
+ port->active_tr_descr));
+ if (port->out_buf_count != 0)
+ printk(KERN_CRIT "sync_ser: buffer not "
+ "empty after eol.\n");
+ port->catch_tr_descr = port->active_tr_descr;
+ port->tr_running = 0;
+ tr_cfg.tr_en = regk_sser_no;
+ REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg);
}
+ /* wake up the waiting process */
+ wake_up_interruptible(&port->out_wait_q);
}
return IRQ_RETVAL(found);
} /* tr_interrupt */
-static irqreturn_t rx_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+static irqreturn_t rx_interrupt(int irq, void *dev_id)
{
reg_dma_r_masked_intr masked;
reg_dma_rw_ack_intr ack_intr = {.data = regk_dma_yes};
int i;
int found = 0;
- for (i = 0; i < NUMBER_OF_PORTS; i++)
+ for (i = 0; i < NBR_PORTS; i++)
{
sync_port *port = &ports[i];
found = 1;
while (REG_RD(dma, port->regi_dmain, rw_data) !=
virt_to_phys(port->next_rx_desc)) {
-
+ DEBUGRXINT(printk(KERN_DEBUG "!"));
if (port->writep + port->inbufchunk > port->flip + port->in_buffer_size) {
int first_size = port->flip + port->in_buffer_size - port->writep;
memcpy((char*)port->writep, phys_to_virt((unsigned)port->next_rx_desc->buf), first_size);
port->full = 1;
}
- port->next_rx_desc->eol = 0;
- port->prev_rx_desc->eol = 1;
- port->prev_rx_desc = phys_to_virt((unsigned)port->next_rx_desc);
+ port->next_rx_desc->eol = 1;
+ port->prev_rx_desc->eol = 0;
+ /* Cache bug workaround */
+ flush_dma_descr(port->prev_rx_desc, 0);
+ port->prev_rx_desc = port->next_rx_desc;
port->next_rx_desc = phys_to_virt((unsigned)port->next_rx_desc->next);
- wake_up_interruptible(&port->in_wait_q); /* wake up the waiting process */
+ /* Cache bug workaround */
+ flush_dma_descr(port->prev_rx_desc, 1);
+ /* wake up the waiting process */
+ wake_up_interruptible(&port->in_wait_q);
DMA_CONTINUE(port->regi_dmain);
REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr);
#endif /* SYNC_SER_DMA */
#ifdef SYNC_SER_MANUAL
-static irqreturn_t manual_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+static irqreturn_t manual_interrupt(int irq, void *dev_id)
{
int i;
int found = 0;
reg_sser_r_masked_intr masked;
- for (i = 0; i < NUMBER_OF_PORTS; i++)
+ for (i = 0; i < NBR_PORTS; i++)
{
- sync_port* port = &ports[i];
+ sync_port *port = &ports[i];
if (!port->enabled || port->use_dma)
{
if (masked.trdy) /* Transmitter ready? */
{
found = 1;
- if (port->out_count > 0) /* More data to send */
+ if (port->out_buf_count > 0) /* More data to send */
send_word(port);
else /* transmission finished */
{
-# $Id: Makefile,v 1.11 2004/12/17 10:16:13 starvik Exp $
#
# Makefile for the linux kernel.
#
extra-y := head.o
-obj-y := entry.o traps.o irq.o debugport.o dma.o pinmux.o \
+obj-y := entry.o traps.o irq.o debugport.o \
process.o ptrace.o setup.o signal.o traps.o time.o \
- arbiter.o io.o
+ cache.o cacheflush.o
obj-$(CONFIG_ETRAXFS_SIM) += vcs_hook.o
+++ /dev/null
-/*
- * Memory arbiter functions. Allocates bandwidth through the
- * arbiter and sets up arbiter breakpoints.
- *
- * The algorithm first assigns slots to the clients that has specified
- * bandwidth (e.g. ethernet) and then the remaining slots are divided
- * on all the active clients.
- *
- * Copyright (c) 2004, 2005 Axis Communications AB.
- */
-
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/marb_defs.h>
-#include <asm/arch/arbiter.h>
-#include <asm/arch/hwregs/intr_vect.h>
-#include <linux/interrupt.h>
-#include <linux/signal.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <asm/io.h>
-
-struct crisv32_watch_entry
-{
- unsigned long instance;
- watch_callback* cb;
- unsigned long start;
- unsigned long end;
- int used;
-};
-
-#define NUMBER_OF_BP 4
-#define NBR_OF_CLIENTS 14
-#define NBR_OF_SLOTS 64
-#define SDRAM_BANDWIDTH 100000000 /* Some kind of expected value */
-#define INTMEM_BANDWIDTH 400000000
-#define NBR_OF_REGIONS 2
-
-static struct crisv32_watch_entry watches[NUMBER_OF_BP] =
-{
- {regi_marb_bp0},
- {regi_marb_bp1},
- {regi_marb_bp2},
- {regi_marb_bp3}
-};
-
-static int requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS];
-static int active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS];
-static int max_bandwidth[NBR_OF_REGIONS] = {SDRAM_BANDWIDTH, INTMEM_BANDWIDTH};
-
-DEFINE_SPINLOCK(arbiter_lock);
-
-static irqreturn_t
-crisv32_arbiter_irq(int irq, void* dev_id, struct pt_regs* regs);
-
-static void crisv32_arbiter_config(int region)
-{
- int slot;
- int client;
- int interval = 0;
- int val[NBR_OF_SLOTS];
-
- for (slot = 0; slot < NBR_OF_SLOTS; slot++)
- val[slot] = NBR_OF_CLIENTS + 1;
-
- for (client = 0; client < NBR_OF_CLIENTS; client++)
- {
- int pos;
- if (!requested_slots[region][client])
- continue;
- interval = NBR_OF_SLOTS / requested_slots[region][client];
- pos = 0;
- while (pos < NBR_OF_SLOTS)
- {
- if (val[pos] != NBR_OF_CLIENTS + 1)
- pos++;
- else
- {
- val[pos] = client;
- pos += interval;
- }
- }
- }
-
- client = 0;
- for (slot = 0; slot < NBR_OF_SLOTS; slot++)
- {
- if (val[slot] == NBR_OF_CLIENTS + 1)
- {
- int first = client;
- while(!active_clients[region][client]) {
- client = (client + 1) % NBR_OF_CLIENTS;
- if (client == first)
- break;
- }
- val[slot] = client;
- client = (client + 1) % NBR_OF_CLIENTS;
- }
- if (region == EXT_REGION)
- REG_WR_INT_VECT(marb, regi_marb, rw_ext_slots, slot, val[slot]);
- else if (region == INT_REGION)
- REG_WR_INT_VECT(marb, regi_marb, rw_int_slots, slot, val[slot]);
- }
-}
-
-extern char _stext, _etext;
-
-static void crisv32_arbiter_init(void)
-{
- static int initialized = 0;
-
- if (initialized)
- return;
-
- initialized = 1;
-
- /* CPU caches are active. */
- active_clients[EXT_REGION][10] = active_clients[EXT_REGION][11] = 1;
- crisv32_arbiter_config(EXT_REGION);
- crisv32_arbiter_config(INT_REGION);
-
- if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, IRQF_DISABLED,
- "arbiter", NULL))
- printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
-
-#ifndef CONFIG_ETRAX_KGDB
- /* Global watch for writes to kernel text segment. */
- crisv32_arbiter_watch(virt_to_phys(&_stext), &_etext - &_stext,
- arbiter_all_clients, arbiter_all_write, NULL);
-#endif
-}
-
-
-
-int crisv32_arbiter_allocate_bandwidth(int client, int region,
- unsigned long bandwidth)
-{
- int i;
- int total_assigned = 0;
- int total_clients = 0;
- int req;
-
- crisv32_arbiter_init();
-
- for (i = 0; i < NBR_OF_CLIENTS; i++)
- {
- total_assigned += requested_slots[region][i];
- total_clients += active_clients[region][i];
- }
- req = NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth);
-
- if (total_assigned + total_clients + req + 1 > NBR_OF_SLOTS)
- return -ENOMEM;
-
- active_clients[region][client] = 1;
- requested_slots[region][client] = req;
- crisv32_arbiter_config(region);
-
- return 0;
-}
-
-int crisv32_arbiter_watch(unsigned long start, unsigned long size,
- unsigned long clients, unsigned long accesses,
- watch_callback* cb)
-{
- int i;
-
- crisv32_arbiter_init();
-
- if (start > 0x80000000) {
- printk("Arbiter: %lX doesn't look like a physical address", start);
- return -EFAULT;
- }
-
- spin_lock(&arbiter_lock);
-
- for (i = 0; i < NUMBER_OF_BP; i++) {
- if (!watches[i].used) {
- reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask);
-
- watches[i].used = 1;
- watches[i].start = start;
- watches[i].end = start + size;
- watches[i].cb = cb;
-
- REG_WR_INT(marb_bp, watches[i].instance, rw_first_addr, watches[i].start);
- REG_WR_INT(marb_bp, watches[i].instance, rw_last_addr, watches[i].end);
- REG_WR_INT(marb_bp, watches[i].instance, rw_op, accesses);
- REG_WR_INT(marb_bp, watches[i].instance, rw_clients, clients);
-
- if (i == 0)
- intr_mask.bp0 = regk_marb_yes;
- else if (i == 1)
- intr_mask.bp1 = regk_marb_yes;
- else if (i == 2)
- intr_mask.bp2 = regk_marb_yes;
- else if (i == 3)
- intr_mask.bp3 = regk_marb_yes;
-
- REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
- spin_unlock(&arbiter_lock);
-
- return i;
- }
- }
- spin_unlock(&arbiter_lock);
- return -ENOMEM;
-}
-
-int crisv32_arbiter_unwatch(int id)
-{
- reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask);
-
- crisv32_arbiter_init();
-
- spin_lock(&arbiter_lock);
-
- if ((id < 0) || (id >= NUMBER_OF_BP) || (!watches[id].used)) {
- spin_unlock(&arbiter_lock);
- return -EINVAL;
- }
-
- memset(&watches[id], 0, sizeof(struct crisv32_watch_entry));
-
- if (id == 0)
- intr_mask.bp0 = regk_marb_no;
- else if (id == 1)
- intr_mask.bp2 = regk_marb_no;
- else if (id == 2)
- intr_mask.bp2 = regk_marb_no;
- else if (id == 3)
- intr_mask.bp3 = regk_marb_no;
-
- REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
-
- spin_unlock(&arbiter_lock);
- return 0;
-}
-
-extern void show_registers(struct pt_regs *regs);
-
-static irqreturn_t
-crisv32_arbiter_irq(int irq, void* dev_id, struct pt_regs* regs)
-{
- reg_marb_r_masked_intr masked_intr = REG_RD(marb, regi_marb, r_masked_intr);
- reg_marb_bp_r_brk_clients r_clients;
- reg_marb_bp_r_brk_addr r_addr;
- reg_marb_bp_r_brk_op r_op;
- reg_marb_bp_r_brk_first_client r_first;
- reg_marb_bp_r_brk_size r_size;
- reg_marb_bp_rw_ack ack = {0};
- reg_marb_rw_ack_intr ack_intr = {.bp0=1,.bp1=1,.bp2=1,.bp3=1};
- struct crisv32_watch_entry* watch;
-
- if (masked_intr.bp0) {
- watch = &watches[0];
- ack_intr.bp0 = regk_marb_yes;
- } else if (masked_intr.bp1) {
- watch = &watches[1];
- ack_intr.bp1 = regk_marb_yes;
- } else if (masked_intr.bp2) {
- watch = &watches[2];
- ack_intr.bp2 = regk_marb_yes;
- } else if (masked_intr.bp3) {
- watch = &watches[3];
- ack_intr.bp3 = regk_marb_yes;
- } else {
- return IRQ_NONE;
- }
-
- /* Retrieve all useful information and print it. */
- r_clients = REG_RD(marb_bp, watch->instance, r_brk_clients);
- r_addr = REG_RD(marb_bp, watch->instance, r_brk_addr);
- r_op = REG_RD(marb_bp, watch->instance, r_brk_op);
- r_first = REG_RD(marb_bp, watch->instance, r_brk_first_client);
- r_size = REG_RD(marb_bp, watch->instance, r_brk_size);
-
- printk("Arbiter IRQ\n");
- printk("Clients %X addr %X op %X first %X size %X\n",
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_clients, r_clients),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_addr, r_addr),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_op, r_op),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_first_client, r_first),
- REG_TYPE_CONV(int, reg_marb_bp_r_brk_size, r_size));
-
- REG_WR(marb_bp, watch->instance, rw_ack, ack);
- REG_WR(marb, regi_marb, rw_ack_intr, ack_intr);
-
- printk("IRQ occured at %lX\n", regs->erp);
-
- if (watch->cb)
- watch->cb();
-
-
- return IRQ_HANDLED;
-}
#include <linux/irq.h>
#include <asm/arch/dma.h>
#include <asm/arch/intmem.h>
-#include <asm/arch/pinmux.h>
+#include <asm/arch/mach/pinmux.h>
+#include <asm/arch/io.h>
/* Functions for allocating DMA channels */
EXPORT_SYMBOL(crisv32_request_dma);
/* Functions for handling pinmux */
EXPORT_SYMBOL(crisv32_pinmux_alloc);
+EXPORT_SYMBOL(crisv32_pinmux_alloc_fixed);
EXPORT_SYMBOL(crisv32_pinmux_dealloc);
+EXPORT_SYMBOL(crisv32_pinmux_dealloc_fixed);
+EXPORT_SYMBOL(crisv32_io_get_name);
+EXPORT_SYMBOL(crisv32_io_get);
/* Functions masking/unmasking interrupts */
EXPORT_SYMBOL(mask_irq);
#include <linux/console.h>
#include <linux/init.h>
-#include <linux/major.h>
-#include <linux/delay.h>
-#include <linux/tty.h>
#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/arch/hwregs/ser_defs.h>
-#include <asm/arch/hwregs/dma_defs.h>
-#include <asm/arch/pinmux.h>
-
-#include <asm/irq.h>
-#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/ser_defs.h>
+#include <hwregs/dma_defs.h>
+#include <asm/arch/mach/pinmux.h>
struct dbg_port
{
115200,
'N',
8
- }
+ },
+#if CONFIG_ETRAX_SERIAL_PORTS == 5
+ {
+ 4,
+ regi_ser4,
+ 0,
+ 115200,
+ 'N',
+ 8
+ },
+#endif
};
static struct dbg_port *port =
#if defined(CONFIG_ETRAX_DEBUG_PORT0)
-&ports[0];
+ &ports[0];
#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
-&ports[1];
+ &ports[1];
#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
-&ports[2];
+ &ports[2];
#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
-&ports[3];
+ &ports[3];
+#elif defined(CONFIG_ETRAX_DEBUG_PORT4)
+ &ports[4];
#else
-NULL;
+ NULL;
#endif
#ifdef CONFIG_ETRAX_KGDB
static struct dbg_port *kgdb_port =
#if defined(CONFIG_ETRAX_KGDB_PORT0)
-&ports[0];
+ &ports[0];
#elif defined(CONFIG_ETRAX_KGDB_PORT1)
-&ports[1];
+ &ports[1];
#elif defined(CONFIG_ETRAX_KGDB_PORT2)
-&ports[2];
+ &ports[2];
#elif defined(CONFIG_ETRAX_KGDB_PORT3)
-&ports[3];
+ &ports[3];
+#elif defined(CONFIG_ETRAX_KGDB_PORT4)
+ &ports[4];
#else
-NULL;
+ NULL;
#endif
#endif
-#ifdef CONFIG_ETRAXFS_SIM
-extern void print_str( const char *str );
-static char buffer[1024];
-static char msg[] = "Debug: ";
-static int buffer_pos = sizeof(msg) - 1;
-#endif
-
-extern struct tty_driver *serial_driver;
-
static void
start_port(struct dbg_port* p)
{
crisv32_pinmux_alloc_fixed(pinmux_ser2);
else if (p->nbr == 3)
crisv32_pinmux_alloc_fixed(pinmux_ser3);
+#if CONFIG_ETRAX_SERIAL_PORTS == 5
+ else if (p->nbr == 4)
+ crisv32_pinmux_alloc_fixed(pinmux_ser4);
+#endif
/* Set up serial port registers */
reg_ser_rw_tr_ctrl tr_ctrl = {0};
REG_WR (ser, p->instance, rw_rec_ctrl, rec_ctrl);
}
-/* No debug */
-#ifdef CONFIG_ETRAX_DEBUG_PORT_NULL
-
-static void
-console_write(struct console *co, const char *buf, unsigned int len)
-{
- return;
-}
-
-/* Target debug */
-#elif !defined(CONFIG_ETRAXFS_SIM)
-
-static void
-console_write_direct(struct console *co, const char *buf, unsigned int len)
-{
- int i;
- reg_ser_r_stat_din stat;
- reg_ser_rw_tr_dma_en tr_dma_en, old;
-
- /* Switch to manual mode */
- tr_dma_en = old = REG_RD (ser, port->instance, rw_tr_dma_en);
- if (tr_dma_en.en == regk_ser_yes) {
- tr_dma_en.en = regk_ser_no;
- REG_WR(ser, port->instance, rw_tr_dma_en, tr_dma_en);
- }
-
- /* Send data */
- for (i = 0; i < len; i++) {
- /* LF -> CRLF */
- if (buf[i] == '\n') {
- do {
- stat = REG_RD (ser, port->instance, r_stat_din);
- } while (!stat.tr_rdy);
- REG_WR_INT (ser, port->instance, rw_dout, '\r');
- }
- /* Wait until transmitter is ready and send.*/
- do {
- stat = REG_RD (ser, port->instance, r_stat_din);
- } while (!stat.tr_rdy);
- REG_WR_INT (ser, port->instance, rw_dout, buf[i]);
- }
-
- /* Restore mode */
- if (tr_dma_en.en != old.en)
- REG_WR(ser, port->instance, rw_tr_dma_en, old);
-}
-
-static void
-console_write(struct console *co, const char *buf, unsigned int len)
-{
- if (!port)
- return;
- console_write_direct(co, buf, len);
-}
-
-
-
-#else
-
-/* VCS debug */
-
-static void
-console_write(struct console *co, const char *buf, unsigned int len)
-{
- char* pos;
- pos = memchr(buf, '\n', len);
- if (pos) {
- int l = ++pos - buf;
- memcpy(buffer + buffer_pos, buf, l);
- memcpy(buffer, msg, sizeof(msg) - 1);
- buffer[buffer_pos + l] = '\0';
- print_str(buffer);
- buffer_pos = sizeof(msg) - 1;
- if (pos - buf != len) {
- memcpy(buffer + buffer_pos, pos, len - l);
- buffer_pos += len - l;
- }
- } else {
- memcpy(buffer + buffer_pos, buf, len);
- buffer_pos += len;
- }
-}
-
-#endif
-
-int raw_printk(const char *fmt, ...)
-{
- static char buf[1024];
- int printed_len;
- va_list args;
- va_start(args, fmt);
- printed_len = vsnprintf(buf, sizeof(buf), fmt, args);
- va_end(args);
- console_write(NULL, buf, strlen(buf));
- return printed_len;
-}
-
-void
-stupid_debug(char* buf)
-{
- console_write(NULL, buf, strlen(buf));
-}
-
#ifdef CONFIG_ETRAX_KGDB
/* Use polling to get a single character from the kernel debug port */
int
getDebugChar(void)
{
- reg_ser_rs_status_data stat;
+ reg_ser_rs_stat_din stat;
reg_ser_rw_ack_intr ack_intr = { 0 };
do {
- stat = REG_RD(ser, kgdb_instance, rs_status_data);
- } while (!stat.data_avail);
+ stat = REG_RD(ser, kgdb_port->instance, rs_stat_din);
+ } while (!stat.dav);
/* Ack the data_avail interrupt. */
- ack_intr.data_avail = 1;
- REG_WR(ser, kgdb_instance, rw_ack_intr, ack_intr);
+ ack_intr.dav = 1;
+ REG_WR(ser, kgdb_port->instance, rw_ack_intr, ack_intr);
return stat.data;
}
void
putDebugChar(int val)
{
- reg_ser_r_status_data stat;
+ reg_ser_r_stat_din stat;
do {
- stat = REG_RD (ser, kgdb_instance, r_status_data);
- } while (!stat.tr_ready);
- REG_WR (ser, kgdb_instance, rw_data_out, REG_TYPE_CONV(reg_ser_rw_data_out, int, val));
+ stat = REG_RD(ser, kgdb_port->instance, r_stat_din);
+ } while (!stat.tr_rdy);
+ REG_WR_INT(ser, kgdb_port->instance, rw_dout, val);
}
#endif /* CONFIG_ETRAX_KGDB */
-static int __init
-console_setup(struct console *co, char *options)
-{
- char* s;
-
- if (options) {
- port = &ports[co->index];
- port->baudrate = 115200;
- port->parity = 'N';
- port->bits = 8;
- port->baudrate = simple_strtoul(options, NULL, 10);
- s = options;
- while(*s >= '0' && *s <= '9')
- s++;
- if (*s) port->parity = *s++;
- if (*s) port->bits = *s++ - '0';
- port->started = 0;
- start_port(port);
- }
- return 0;
-}
-
-/* This is a dummy serial device that throws away anything written to it.
- * This is used when no debug output is wanted.
- */
-static struct tty_driver dummy_driver;
-
-static int dummy_open(struct tty_struct *tty, struct file * filp)
-{
- return 0;
-}
-
-static void dummy_close(struct tty_struct *tty, struct file * filp)
-{
-}
-
-static int dummy_write(struct tty_struct * tty,
- const unsigned char *buf, int count)
-{
- return count;
-}
-
-static int
-dummy_write_room(struct tty_struct *tty)
-{
- return 8192;
-}
-
-void __init
-init_dummy_console(void)
-{
- memset(&dummy_driver, 0, sizeof(struct tty_driver));
- dummy_driver.driver_name = "serial";
- dummy_driver.name = "ttyS";
- dummy_driver.major = TTY_MAJOR;
- dummy_driver.minor_start = 68;
- dummy_driver.num = 1; /* etrax100 has 4 serial ports */
- dummy_driver.type = TTY_DRIVER_TYPE_SERIAL;
- dummy_driver.subtype = SERIAL_TYPE_NORMAL;
- dummy_driver.init_termios = tty_std_termios;
- dummy_driver.init_termios.c_cflag =
- B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
- dummy_driver.flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
-
- dummy_driver.open = dummy_open;
- dummy_driver.close = dummy_close;
- dummy_driver.write = dummy_write;
- dummy_driver.write_room = dummy_write_room;
- if (tty_register_driver(&dummy_driver))
- panic("Couldn't register dummy serial driver\n");
-}
-
-static struct tty_driver*
-crisv32_console_device(struct console* co, int *index)
-{
- if (port)
- *index = port->nbr;
- return port ? serial_driver : &dummy_driver;
-}
-
-static struct console sercons = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : crisv32_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : -1,
- cflag : 0,
- next : NULL
-};
-static struct console sercons0 = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : crisv32_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 0,
- cflag : 0,
- next : NULL
-};
-
-static struct console sercons1 = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : crisv32_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 1,
- cflag : 0,
- next : NULL
-};
-static struct console sercons2 = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : crisv32_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 2,
- cflag : 0,
- next : NULL
-};
-static struct console sercons3 = {
- name : "ttyS",
- write: console_write,
- read : NULL,
- device : crisv32_console_device,
- unblank : NULL,
- setup : console_setup,
- flags : CON_PRINTBUFFER,
- index : 3,
- cflag : 0,
- next : NULL
-};
-
/* Register console for printk's, etc. */
int __init
init_etrax_debug(void)
{
- static int first = 1;
-
- if (!first) {
- unregister_console(&sercons);
- register_console(&sercons0);
- register_console(&sercons1);
- register_console(&sercons2);
- register_console(&sercons3);
- init_dummy_console();
- return 0;
- }
- first = 0;
- register_console(&sercons);
start_port(port);
#ifdef CONFIG_ETRAX_KGDB
#endif /* CONFIG_ETRAX_KGDB */
return 0;
}
-
-__initcall(init_etrax_debug);
* after a timer-interrupt and after each system call.
*
* Stack layout in 'ret_from_system_call':
- * ptrace needs to have all regs on the stack.
+ * ptrace needs to have all regs on the stack.
* if the order here is changed, it needs to be
* updated in fork.c:copy_process, signal.c:do_signal,
* ptrace.c and ptrace.h
;; Deal with pending signals and notify-resume requests.
addoq +TI_flags, $r0, $acr
- move.d [$acr], $r13 ; The thread_info_flags parameter.
- move.d $r9, $r10 ; do_notify_resume syscall/irq param.
- moveq 0, $r11 ; oldset param - 0 in this case.
- move.d $sp, $r12 ; The regs param.
+ move.d [$acr], $r12 ; The thread_info_flags parameter.
+ move.d $sp, $r11 ; The regs param.
jsr do_notify_resume
- nop
+ move.d $r9, $r10 ; do_notify_resume syscall/irq param.
ba _Rexit
nop
btstq REG_BIT(intr_vect, r_nmi, watchdog), $r0
bpl 1f
nop
- jsr handle_watchdog_bite ; In time.c.
+ jsr handle_watchdog_bite ; In time.c.
move.d $sp, $r10 ; Pointer to registers
1: btstq REG_BIT(intr_vect, r_nmi, ext), $r0
bpl 1f
ba do_sigtrap ; SIGTRAP the offending process.
move.d [$sp+], $r0 ; Restore R0 in delay slot.
+ .global kernel_execve
+kernel_execve:
+ move.d __NR_execve, $r9
+ break 13
+ ret
+ nop
+
.data
.section .rodata,"a"
.long sys_epoll_ctl /* 255 */
.long sys_epoll_wait
.long sys_remap_file_pages
- .long sys_set_tid_address
- .long sys_timer_create
- .long sys_timer_settime /* 260 */
- .long sys_timer_gettime
- .long sys_timer_getoverrun
- .long sys_timer_delete
- .long sys_clock_settime
- .long sys_clock_gettime /* 265 */
- .long sys_clock_getres
- .long sys_clock_nanosleep
+ .long sys_set_tid_address
+ .long sys_timer_create
+ .long sys_timer_settime /* 260 */
+ .long sys_timer_gettime
+ .long sys_timer_getoverrun
+ .long sys_timer_delete
+ .long sys_clock_settime
+ .long sys_clock_gettime /* 265 */
+ .long sys_clock_getres
+ .long sys_clock_nanosleep
.long sys_statfs64
.long sys_fstatfs64
.long sys_tgkill /* 270 */
.long sys_utimes
- .long sys_fadvise64_64
+ .long sys_fadvise64_64
.long sys_ni_syscall /* sys_vserver */
.long sys_ni_syscall /* sys_mbind */
.long sys_ni_syscall /* 275 sys_get_mempolicy */
.long sys_mq_getsetattr
.long sys_ni_syscall /* reserved for kexec */
.long sys_waitid
+ .long sys_ni_syscall /* 285 */ /* available */
+ .long sys_add_key
+ .long sys_request_key
+ .long sys_keyctl
+ .long sys_ioprio_set
+ .long sys_ioprio_get /* 290 */
+ .long sys_inotify_init
+ .long sys_inotify_add_watch
+ .long sys_inotify_rm_watch
+ .long sys_migrate_pages
+ .long sys_openat /* 295 */
+ .long sys_mkdirat
+ .long sys_mknodat
+ .long sys_fchownat
+ .long sys_futimesat
+ .long sys_fstatat64 /* 300 */
+ .long sys_unlinkat
+ .long sys_renameat
+ .long sys_linkat
+ .long sys_symlinkat
+ .long sys_readlinkat /* 305 */
+ .long sys_fchmodat
+ .long sys_faccessat
+ .long sys_pselect6
+ .long sys_ppoll
+ .long sys_unshare /* 310 */
+ .long sys_set_robust_list
+ .long sys_get_robust_list
+ .long sys_splice
+ .long sys_sync_file_range
+ .long sys_tee /* 315 */
+ .long sys_vmsplice
+ .long sys_move_pages
+ .long sys_getcpu
+ .long sys_epoll_pwait
+ .long sys_utimensat /* 320 */
+ .long sys_signalfd
+ .long sys_timerfd_create
+ .long sys_eventfd
+ .long sys_fallocate
+ .long sys_timerfd_settime /* 325 */
+ .long sys_timerfd_gettime
/*
* NOTE!! This doesn't have to be exact - we just have
-/* $Id: fasttimer.c,v 1.11 2005/01/04 11:15:46 starvik Exp $
+/*
* linux/arch/cris/kernel/fasttimer.c
*
* Fast timers for ETRAX FS
- * This may be useful in other OS than Linux so use 2 space indentation...
- *
- * $Log: fasttimer.c,v $
- * Revision 1.11 2005/01/04 11:15:46 starvik
- * Don't share timer IRQ.
- *
- * Revision 1.10 2004/12/07 09:19:38 starvik
- * Corrected includes.
- * Use correct interrupt macros.
- *
- * Revision 1.9 2004/05/14 10:18:58 starvik
- * Export fast_timer_list
- *
- * Revision 1.8 2004/05/14 07:58:03 starvik
- * Merge of changes from 2.4
- *
- * Revision 1.7 2003/07/10 12:06:14 starvik
- * Return IRQ_NONE if irq wasn't handled
- *
- * Revision 1.6 2003/07/04 08:27:49 starvik
- * Merge of Linux 2.5.74
- *
- * Revision 1.5 2003/06/05 10:16:22 johana
- * New INTR_VECT macros.
- *
- * Revision 1.4 2003/06/03 08:49:45 johana
- * Fixed typo.
- *
- * Revision 1.3 2003/06/02 12:51:27 johana
- * Now compiles.
- * Commented some include files that probably can be removed.
- *
- * Revision 1.2 2003/06/02 12:09:41 johana
- * Ported to ETRAX FS using the trig interrupt instead of timer1.
- *
- * Revision 1.3 2002/12/12 08:26:32 starvik
- * Don't use C-comments inside CVS comments
- *
- * Revision 1.2 2002/12/11 15:42:02 starvik
- * Extracted v10 (ETRAX 100LX) specific stuff from arch/cris/kernel/
- *
- * Revision 1.1 2002/11/18 07:58:06 starvik
- * Fast timers (from Linux 2.4)
- *
- * Revision 1.5 2002/10/15 06:21:39 starvik
- * Added call to init_waitqueue_head
*
- * Revision 1.4 2002/05/28 17:47:59 johana
- * Added del_fast_timer()
- *
- * Revision 1.3 2002/05/28 16:16:07 johana
- * Handle empty fast_timer_list
- *
- * Revision 1.2 2002/05/27 15:38:42 johana
- * Made it compile without warnings on Linux 2.4.
- * (includes, wait_queue, PROC_FS and snprintf)
- *
- * Revision 1.1 2002/05/27 15:32:25 johana
- * arch/etrax100/kernel/fasttimer.c v1.8 from the elinux tree.
- *
- * Revision 1.8 2001/11/27 13:50:40 pkj
- * Disable interrupts while stopping the timer and while modifying the
- * list of active timers in timer1_handler() as it may be interrupted
- * by other interrupts (e.g., the serial interrupt) which may add fast
- * timers.
- *
- * Revision 1.7 2001/11/22 11:50:32 pkj
- * * Only store information about the last 16 timers.
- * * proc_fasttimer_read() now uses an allocated buffer, since it
- * requires more space than just a page even for only writing the
- * last 16 timers. The buffer is only allocated on request, so
- * unless /proc/fasttimer is read, it is never allocated.
- * * Renamed fast_timer_started to fast_timers_started to match
- * fast_timers_added and fast_timers_expired.
- * * Some clean-up.
- *
- * Revision 1.6 2000/12/13 14:02:08 johana
- * Removed volatile for fast_timer_list
- *
- * Revision 1.5 2000/12/13 13:55:35 johana
- * Added DEBUG_LOG, added som cli() and cleanup
- *
- * Revision 1.4 2000/12/05 13:48:50 johana
- * Added range check when writing proc file, modified timer int handling
- *
- * Revision 1.3 2000/11/23 10:10:20 johana
- * More debug/logging possibilities.
- * Moved GET_JIFFIES_USEC() to timex.h and time.c
- *
- * Revision 1.2 2000/11/01 13:41:04 johana
- * Clean up and bugfixes.
- * Created new do_gettimeofday_fast() that gets a timeval struct
- * with time based on jiffies and *R_TIMER0_DATA, uses a table
- * for fast conversion of timer value to microseconds.
- * (Much faster the standard do_gettimeofday() and we don't really
- * want to use the true time - we want the "uptime" so timers don't screw up
- * when we change the time.
- * TODO: Add efficient support for continuous timers as well.
- *
- * Revision 1.1 2000/10/26 15:49:16 johana
- * Added fasttimer, highresolution timers.
- *
- * Copyright (C) 2000,2001 2002, 2003 Axis Communications AB, Lund, Sweden
+ * Copyright (C) 2000-2006 Axis Communications AB, Lund, Sweden
*/
#include <linux/errno.h>
#include <linux/version.h>
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/timer_defs.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/timer_defs.h>
#include <asm/fasttimer.h>
#include <linux/proc_fs.h>
#define DEBUG_LOG_INCLUDED
#define FAST_TIMER_LOG
-//#define FAST_TIMER_TEST
+/* #define FAST_TIMER_TEST */
#define FAST_TIMER_SANITY_CHECKS
#ifdef FAST_TIMER_SANITY_CHECKS
-#define SANITYCHECK(x) x
-static int sanity_failed = 0;
-#else
-#define SANITYCHECK(x)
+static int sanity_failed;
#endif
#define D1(x)
#define D2(x)
#define DP(x)
-#define __INLINE__ inline
-
-static int fast_timer_running = 0;
-static int fast_timers_added = 0;
-static int fast_timers_started = 0;
-static int fast_timers_expired = 0;
-static int fast_timers_deleted = 0;
-static int fast_timer_is_init = 0;
-static int fast_timer_ints = 0;
+static unsigned int fast_timer_running;
+static unsigned int fast_timers_added;
+static unsigned int fast_timers_started;
+static unsigned int fast_timers_expired;
+static unsigned int fast_timers_deleted;
+static unsigned int fast_timer_is_init;
+static unsigned int fast_timer_ints;
struct fast_timer *fast_timer_list = NULL;
#define DEBUG_LOG_MAX 128
static const char * debug_log_string[DEBUG_LOG_MAX];
static unsigned long debug_log_value[DEBUG_LOG_MAX];
-static int debug_log_cnt = 0;
-static int debug_log_cnt_wrapped = 0;
+static unsigned int debug_log_cnt;
+static unsigned int debug_log_cnt_wrapped;
#define DEBUG_LOG(string, value) \
{ \
int timer_div_settings[NUM_TIMER_STATS];
int timer_delay_settings[NUM_TIMER_STATS];
+struct work_struct fast_work;
static void
-timer_trig_handler(void);
+timer_trig_handler(struct work_struct *work);
/* Not true gettimeofday, only checks the jiffies (uptime) + useconds */
-void __INLINE__ do_gettimeofday_fast(struct timeval *tv)
+inline void do_gettimeofday_fast(struct fasttime_t *tv)
{
- unsigned long sec = jiffies;
- unsigned long usec = GET_JIFFIES_USEC();
-
- usec += (sec % HZ) * (1000000 / HZ);
- sec = sec / HZ;
-
- if (usec > 1000000)
- {
- usec -= 1000000;
- sec++;
- }
- tv->tv_sec = sec;
- tv->tv_usec = usec;
+ tv->tv_jiff = jiffies;
+ tv->tv_usec = GET_JIFFIES_USEC();
}
-int __INLINE__ timeval_cmp(struct timeval *t0, struct timeval *t1)
+inline int fasttime_cmp(struct fasttime_t *t0, struct fasttime_t *t1)
{
- if (t0->tv_sec < t1->tv_sec)
- {
- return -1;
- }
- else if (t0->tv_sec > t1->tv_sec)
- {
- return 1;
- }
- if (t0->tv_usec < t1->tv_usec)
- {
- return -1;
- }
- else if (t0->tv_usec > t1->tv_usec)
- {
- return 1;
- }
- return 0;
+ /* Compare jiffies. Takes care of wrapping */
+ if (time_before(t0->tv_jiff, t1->tv_jiff))
+ return -1;
+ else if (time_after(t0->tv_jiff, t1->tv_jiff))
+ return 1;
+
+ /* Compare us */
+ if (t0->tv_usec < t1->tv_usec)
+ return -1;
+ else if (t0->tv_usec > t1->tv_usec)
+ return 1;
+ return 0;
}
/* Called with ints off */
-void __INLINE__ start_timer_trig(unsigned long delay_us)
+inline void start_timer_trig(unsigned long delay_us)
{
reg_timer_rw_ack_intr ack_intr = { 0 };
reg_timer_rw_intr_mask intr_mask;
reg_timer_rw_trig trig;
reg_timer_rw_trig_cfg trig_cfg = { 0 };
- reg_timer_r_time r_time;
+ reg_timer_r_time r_time0;
+ reg_timer_r_time r_time1;
+ unsigned char trig_wrap;
+ unsigned char time_wrap;
- r_time = REG_RD(timer, regi_timer, r_time);
+ r_time0 = REG_RD(timer, regi_timer0, r_time);
D1(printk("start_timer_trig : %d us freq: %i div: %i\n",
delay_us, freq_index, div));
/* Clear trig irq */
- intr_mask = REG_RD(timer, regi_timer, rw_intr_mask);
+ intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask);
intr_mask.trig = 0;
- REG_WR(timer, regi_timer, rw_intr_mask, intr_mask);
+ REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask);
- /* Set timer values */
- /* r_time is 100MHz (10 ns resolution) */
- trig = r_time + delay_us*(1000/10);
+ /* Set timer values and check if trigger wraps. */
+ /* r_time is 100MHz (10 ns resolution) */
+ trig_wrap = (trig = r_time0 + delay_us*(1000/10)) < r_time0;
timer_div_settings[fast_timers_started % NUM_TIMER_STATS] = trig;
timer_delay_settings[fast_timers_started % NUM_TIMER_STATS] = delay_us;
/* Ack interrupt */
ack_intr.trig = 1;
- REG_WR(timer, regi_timer, rw_ack_intr, ack_intr);
+ REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr);
/* Start timer */
- REG_WR(timer, regi_timer, rw_trig, trig);
+ REG_WR(timer, regi_timer0, rw_trig, trig);
trig_cfg.tmr = regk_timer_time;
- REG_WR(timer, regi_timer, rw_trig_cfg, trig_cfg);
+ REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg);
/* Check if we have already passed the trig time */
- r_time = REG_RD(timer, regi_timer, r_time);
- if (r_time < trig) {
+ r_time1 = REG_RD(timer, regi_timer0, r_time);
+ time_wrap = r_time1 < r_time0;
+
+ if ((trig_wrap && !time_wrap) || (r_time1 < trig)) {
/* No, Enable trig irq */
- intr_mask = REG_RD(timer, regi_timer, rw_intr_mask);
+ intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask);
intr_mask.trig = 1;
- REG_WR(timer, regi_timer, rw_intr_mask, intr_mask);
+ REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask);
fast_timers_started++;
fast_timer_running = 1;
- }
- else
- {
+ } else {
/* We have passed the time, disable trig point, ack intr */
trig_cfg.tmr = regk_timer_off;
- REG_WR(timer, regi_timer, rw_trig_cfg, trig_cfg);
- REG_WR(timer, regi_timer, rw_ack_intr, ack_intr);
- /* call the int routine directly */
- timer_trig_handler();
+ REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg);
+ REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr);
+ /* call the int routine */
+ INIT_WORK(&fast_work, timer_trig_handler);
+ schedule_work(&fast_work);
}
}
do_gettimeofday_fast(&t->tv_set);
tmp = fast_timer_list;
- SANITYCHECK({ /* Check so this is not in the list already... */
- while (tmp != NULL)
- {
- if (tmp == t)
- {
- printk("timer name: %s data: 0x%08lX already in list!\n", name, data);
- sanity_failed++;
- return;
- }
- else
- {
- tmp = tmp->next;
- }
- }
- tmp = fast_timer_list;
- });
+#ifdef FAST_TIMER_SANITY_CHECKS
+ /* Check so this is not in the list already... */
+ while (tmp != NULL) {
+ if (tmp == t) {
+ printk(KERN_DEBUG
+ "timer name: %s data: 0x%08lX already "
+ "in list!\n", name, data);
+ sanity_failed++;
+ goto done;
+ } else
+ tmp = tmp->next;
+ }
+ tmp = fast_timer_list;
+#endif
t->delay_us = delay_us;
t->function = function;
t->name = name;
t->tv_expires.tv_usec = t->tv_set.tv_usec + delay_us % 1000000;
- t->tv_expires.tv_sec = t->tv_set.tv_sec + delay_us / 1000000;
- if (t->tv_expires.tv_usec > 1000000)
- {
+ t->tv_expires.tv_jiff = t->tv_set.tv_jiff + delay_us / 1000000 / HZ;
+ if (t->tv_expires.tv_usec > 1000000) {
t->tv_expires.tv_usec -= 1000000;
- t->tv_expires.tv_sec++;
+ t->tv_expires.tv_jiff += HZ;
}
#ifdef FAST_TIMER_LOG
timer_added_log[fast_timers_added % NUM_TIMER_STATS] = *t;
fast_timers_added++;
/* Check if this should timeout before anything else */
- if (tmp == NULL || timeval_cmp(&t->tv_expires, &tmp->tv_expires) < 0)
- {
+ if (tmp == NULL || fasttime_cmp(&t->tv_expires, &tmp->tv_expires) < 0) {
/* Put first in list and modify the timer value */
t->prev = NULL;
t->next = fast_timer_list;
if (fast_timer_list)
- {
fast_timer_list->prev = t;
- }
fast_timer_list = t;
#ifdef FAST_TIMER_LOG
timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
} else {
/* Put in correct place in list */
while (tmp->next &&
- timeval_cmp(&t->tv_expires, &tmp->next->tv_expires) > 0)
- {
+ fasttime_cmp(&t->tv_expires, &tmp->next->tv_expires) > 0)
tmp = tmp->next;
- }
/* Insert t after tmp */
t->prev = tmp;
t->next = tmp->next;
D2(printk("start_one_shot_timer: %d us done\n", delay_us));
+done:
local_irq_restore(flags);
} /* start_one_shot_timer */
/* Timer interrupt handler for trig interrupts */
static irqreturn_t
-timer_trig_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+timer_trig_interrupt(int irq, void *dev_id)
{
reg_timer_r_masked_intr masked_intr;
-
/* Check if the timer interrupt is for us (a trig int) */
- masked_intr = REG_RD(timer, regi_timer, r_masked_intr);
+ masked_intr = REG_RD(timer, regi_timer0, r_masked_intr);
if (!masked_intr.trig)
return IRQ_NONE;
- timer_trig_handler();
+ timer_trig_handler(NULL);
return IRQ_HANDLED;
}
-static void timer_trig_handler(void)
+static void timer_trig_handler(struct work_struct *work)
{
reg_timer_rw_ack_intr ack_intr = { 0 };
reg_timer_rw_intr_mask intr_mask;
struct fast_timer *t;
unsigned long flags;
+ /* We keep interrupts disabled not only when we modify the
+ * fast timer list, but any time we hold a reference to a
+ * timer in the list, since del_fast_timer may be called
+ * from (another) interrupt context. Thus, the only time
+ * when interrupts are enabled is when calling the timer
+ * callback function.
+ */
local_irq_save(flags);
/* Clear timer trig interrupt */
- intr_mask = REG_RD(timer, regi_timer, rw_intr_mask);
+ intr_mask = REG_RD(timer, regi_timer0, rw_intr_mask);
intr_mask.trig = 0;
- REG_WR(timer, regi_timer, rw_intr_mask, intr_mask);
+ REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask);
/* First stop timer, then ack interrupt */
/* Stop timer */
trig_cfg.tmr = regk_timer_off;
- REG_WR(timer, regi_timer, rw_trig_cfg, trig_cfg);
+ REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg);
/* Ack interrupt */
ack_intr.trig = 1;
- REG_WR(timer, regi_timer, rw_ack_intr, ack_intr);
+ REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr);
fast_timer_running = 0;
fast_timer_ints++;
- local_irq_restore(flags);
+ fast_timer_function_type *f;
+ unsigned long d;
t = fast_timer_list;
- while (t)
- {
- struct timeval tv;
+ while (t) {
+ struct fasttime_t tv;
/* Has it really expired? */
do_gettimeofday_fast(&tv);
- D1(printk("t: %is %06ius\n", tv.tv_sec, tv.tv_usec));
+ D1(printk(KERN_DEBUG
+ "t: %is %06ius\n", tv.tv_jiff, tv.tv_usec));
- if (timeval_cmp(&t->tv_expires, &tv) <= 0)
- {
+ if (fasttime_cmp(&t->tv_expires, &tv) <= 0) {
/* Yes it has expired */
#ifdef FAST_TIMER_LOG
timer_expired_log[fast_timers_expired % NUM_TIMER_STATS] = *t;
fast_timers_expired++;
/* Remove this timer before call, since it may reuse the timer */
- local_irq_save(flags);
if (t->prev)
- {
t->prev->next = t->next;
- }
else
- {
fast_timer_list = t->next;
- }
if (t->next)
- {
t->next->prev = t->prev;
- }
t->prev = NULL;
t->next = NULL;
- local_irq_restore(flags);
- if (t->function != NULL)
- {
- t->function(t->data);
- }
- else
- {
+ /* Save function callback data before enabling
+ * interrupts, since the timer may be removed and we
+ * don't know how it was allocated (e.g. ->function
+ * and ->data may become overwritten after deletion
+ * if the timer was stack-allocated).
+ */
+ f = t->function;
+ d = t->data;
+
+ if (f != NULL) {
+ /* Run the callback function with interrupts
+ * enabled. */
+ local_irq_restore(flags);
+ f(d);
+ local_irq_save(flags);
+ } else
DEBUG_LOG("!trimertrig %i function==NULL!\n", fast_timer_ints);
- }
- }
- else
- {
+ } else {
/* Timer is to early, let's set it again using the normal routines */
D1(printk(".\n"));
}
- local_irq_save(flags);
- if ((t = fast_timer_list) != NULL)
- {
+ t = fast_timer_list;
+ if (t != NULL) {
/* Start next timer.. */
- long us;
- struct timeval tv;
+ long us = 0;
+ struct fasttime_t tv;
do_gettimeofday_fast(&tv);
- us = ((t->tv_expires.tv_sec - tv.tv_sec) * 1000000 +
- t->tv_expires.tv_usec - tv.tv_usec);
- if (us > 0)
- {
- if (!fast_timer_running)
- {
+
+ /* time_after_eq takes care of wrapping */
+ if (time_after_eq(t->tv_expires.tv_jiff, tv.tv_jiff))
+ us = ((t->tv_expires.tv_jiff - tv.tv_jiff) *
+ 1000000 / HZ + t->tv_expires.tv_usec -
+ tv.tv_usec);
+
+ if (us > 0) {
+ if (!fast_timer_running) {
#ifdef FAST_TIMER_LOG
timer_started_log[fast_timers_started % NUM_TIMER_STATS] = *t;
#endif
start_timer_trig(us);
}
- local_irq_restore(flags);
break;
- }
- else
- {
+ } else {
/* Timer already expired, let's handle it better late than never.
* The normal loop handles it
*/
D1(printk("e! %d\n", us));
}
}
- local_irq_restore(flags);
}
- if (!t)
- {
+ local_irq_restore(flags);
+
+ if (!t)
D1(printk("ttrig stop!\n"));
- }
}
static void wake_up_func(unsigned long data)
{
-#ifdef DECLARE_WAITQUEUE
wait_queue_head_t *sleep_wait_p = (wait_queue_head_t*)data;
-#else
- struct wait_queue **sleep_wait_p = (struct wait_queue **)data;
-#endif
wake_up(sleep_wait_p);
}
void schedule_usleep(unsigned long us)
{
struct fast_timer t;
-#ifdef DECLARE_WAITQUEUE
wait_queue_head_t sleep_wait;
init_waitqueue_head(&sleep_wait);
- {
- DECLARE_WAITQUEUE(wait, current);
-#else
- struct wait_queue *sleep_wait = NULL;
- struct wait_queue wait = { current, NULL };
-#endif
D1(printk("schedule_usleep(%d)\n", us));
- add_wait_queue(&sleep_wait, &wait);
- set_current_state(TASK_INTERRUPTIBLE);
start_one_shot_timer(&t, wake_up_func, (unsigned long)&sleep_wait, us,
"usleep");
- schedule();
- set_current_state(TASK_RUNNING);
- remove_wait_queue(&sleep_wait, &wait);
+ /* Uninterruptible sleep on the fast timer. (The condition is
+ * somewhat redundant since the timer is what wakes us up.) */
+ wait_event(sleep_wait, !fast_timer_pending(&t));
+
D1(printk("done schedule_usleep(%d)\n", us));
-#ifdef DECLARE_WAITQUEUE
- }
-#endif
}
#ifdef CONFIG_PROC_FS
unsigned long flags;
int i = 0;
int num_to_show;
- struct timeval tv;
+ struct fasttime_t tv;
struct fast_timer *t, *nextt;
static char *bigbuf = NULL;
static unsigned long used;
- if (!bigbuf && !(bigbuf = vmalloc(BIG_BUF_SIZE)))
- {
- used = 0;
- bigbuf[0] = '\0';
- return 0;
- }
-
- if (!offset || !used)
- {
+ if (!bigbuf) {
+ bigbuf = vmalloc(BIG_BUF_SIZE);
+ if (!bigbuf) {
+ used = 0;
+ if (buf)
+ buf[0] = '\0';
+ return 0;
+ }
+ }
+
+ if (!offset || !used) {
do_gettimeofday_fast(&tv);
used = 0;
used += sprintf(bigbuf + used, "Fast timer running: %s\n",
fast_timer_running ? "yes" : "no");
used += sprintf(bigbuf + used, "Current time: %lu.%06lu\n",
- (unsigned long)tv.tv_sec,
+ (unsigned long)tv.tv_jiff,
(unsigned long)tv.tv_usec);
#ifdef FAST_TIMER_SANITY_CHECKS
used += sprintf(bigbuf + used, "Sanity failed: %i\n",
int end_i = debug_log_cnt;
i = 0;
- if (debug_log_cnt_wrapped)
- {
+ if (debug_log_cnt_wrapped)
i = debug_log_cnt;
- }
while ((i != end_i || (debug_log_cnt_wrapped && !used)) &&
used+100 < BIG_BUF_SIZE)
"d: %6li us data: 0x%08lX"
"\n",
t->name,
- (unsigned long)t->tv_set.tv_sec,
+ (unsigned long)t->tv_set.tv_jiff,
(unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_sec,
+ (unsigned long)t->tv_expires.tv_jiff,
(unsigned long)t->tv_expires.tv_usec,
t->delay_us,
t->data
"d: %6li us data: 0x%08lX"
"\n",
t->name,
- (unsigned long)t->tv_set.tv_sec,
+ (unsigned long)t->tv_set.tv_jiff,
(unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_sec,
+ (unsigned long)t->tv_expires.tv_jiff,
(unsigned long)t->tv_expires.tv_usec,
t->delay_us,
t->data
"d: %6li us data: 0x%08lX"
"\n",
t->name,
- (unsigned long)t->tv_set.tv_sec,
+ (unsigned long)t->tv_set.tv_jiff,
(unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_sec,
+ (unsigned long)t->tv_expires.tv_jiff,
(unsigned long)t->tv_expires.tv_usec,
t->delay_us,
t->data
used += sprintf(bigbuf + used, "Active timers:\n");
local_irq_save(flags);
- local_irq_save(flags);
t = fast_timer_list;
while (t != NULL && (used+100 < BIG_BUF_SIZE))
{
nextt = t->next;
local_irq_restore(flags);
used += sprintf(bigbuf + used, "%-14s s: %6lu.%06lu e: %6lu.%06lu "
- "d: %6li us data: 0x%08lX"
-/* " func: 0x%08lX" */
- "\n",
- t->name,
- (unsigned long)t->tv_set.tv_sec,
- (unsigned long)t->tv_set.tv_usec,
- (unsigned long)t->tv_expires.tv_sec,
- (unsigned long)t->tv_expires.tv_usec,
+ "d: %6li us data: 0x%08lX"
+/* " func: 0x%08lX" */
+ "\n",
+ t->name,
+ (unsigned long)t->tv_set.tv_jiff,
+ (unsigned long)t->tv_set.tv_usec,
+ (unsigned long)t->tv_expires.tv_jiff,
+ (unsigned long)t->tv_expires.tv_usec,
t->delay_us,
t->data
/* , t->function */
);
- local_irq_disable();
+ local_irq_save(flags);
if (t->next != nextt)
{
printk("timer removed!\n");
static struct fast_timer tr[10];
static int exp_num[10];
-static struct timeval tv_exp[100];
+static struct fasttime_t tv_exp[100];
static void test_timeout(unsigned long data)
{
int prev_num;
int j;
- struct timeval tv, tv0, tv1, tv2;
+ struct fasttime_t tv, tv0, tv1, tv2;
printk("fast_timer_test() start\n");
do_gettimeofday_fast(&tv);
{
do_gettimeofday_fast(&tv_exp[j]);
}
- printk("fast_timer_test() %is %06i\n", tv.tv_sec, tv.tv_usec);
+ printk(KERN_DEBUG "fast_timer_test() %is %06i\n", tv.tv_jiff, tv.tv_usec);
for (j = 0; j < 1000; j++)
{
- printk("%i %i %i %i %i\n",j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]);
+ printk(KERN_DEBUG "%i %i %i %i %i\n",
+ j_u[j], j_u[j+1], j_u[j+2], j_u[j+3], j_u[j+4]);
j += 4;
}
for (j = 0; j < 100; j++)
{
- printk("%i.%i %i.%i %i.%i %i.%i %i.%i\n",
- tv_exp[j].tv_sec,tv_exp[j].tv_usec,
- tv_exp[j+1].tv_sec,tv_exp[j+1].tv_usec,
- tv_exp[j+2].tv_sec,tv_exp[j+2].tv_usec,
- tv_exp[j+3].tv_sec,tv_exp[j+3].tv_usec,
- tv_exp[j+4].tv_sec,tv_exp[j+4].tv_usec);
+ printk(KERN_DEBUG "%i.%i %i.%i %i.%i %i.%i %i.%i\n",
+ tv_exp[j].tv_jiff, tv_exp[j].tv_usec,
+ tv_exp[j+1].tv_jiff, tv_exp[j+1].tv_usec,
+ tv_exp[j+2].tv_jiff, tv_exp[j+2].tv_usec,
+ tv_exp[j+3].tv_jiff, tv_exp[j+3].tv_usec,
+ tv_exp[j+4].tv_jiff, tv_exp[j+4].tv_usec);
j += 4;
}
do_gettimeofday_fast(&tv0);
while (num_test_timeout < i)
{
if (num_test_timeout != prev_num)
- {
prev_num = num_test_timeout;
- }
}
do_gettimeofday_fast(&tv2);
- printk("Timers started %is %06i\n", tv0.tv_sec, tv0.tv_usec);
- printk("Timers started at %is %06i\n", tv1.tv_sec, tv1.tv_usec);
- printk("Timers done %is %06i\n", tv2.tv_sec, tv2.tv_usec);
+ printk(KERN_INFO "Timers started %is %06i\n",
+ tv0.tv_jiff, tv0.tv_usec);
+ printk(KERN_INFO "Timers started at %is %06i\n",
+ tv1.tv_jiff, tv1.tv_usec);
+ printk(KERN_INFO "Timers done %is %06i\n",
+ tv2.tv_jiff, tv2.tv_usec);
DP(printk("buf0:\n");
printk(buf0);
printk("buf1:\n");
printk("%-10s set: %6is %06ius exp: %6is %06ius "
"data: 0x%08X func: 0x%08X\n",
t->name,
- t->tv_set.tv_sec,
+ t->tv_set.tv_jiff,
t->tv_set.tv_usec,
- t->tv_expires.tv_sec,
+ t->tv_expires.tv_jiff,
t->tv_expires.tv_usec,
t->data,
t->function
printk(" del: %6ius did exp: %6is %06ius as #%i error: %6li\n",
t->delay_us,
- tv_exp[j].tv_sec,
+ tv_exp[j].tv_jiff,
tv_exp[j].tv_usec,
exp_num[j],
- (tv_exp[j].tv_sec - t->tv_expires.tv_sec)*1000000 + tv_exp[j].tv_usec - t->tv_expires.tv_usec);
+ (tv_exp[j].tv_jiff - t->tv_expires.tv_jiff) *
+ 1000000 + tv_exp[j].tv_usec -
+ t->tv_expires.tv_usec);
}
proc_fasttimer_read(buf5, NULL, 0, 0, 0);
printk("buf5 after all done:\n");
#endif
-void fast_timer_init(void)
+int fast_timer_init(void)
{
/* For some reason, request_irq() hangs when called froom time_init() */
if (!fast_timer_is_init)
printk("fast_timer_init()\n");
#ifdef CONFIG_PROC_FS
- if ((fasttimer_proc_entry = create_proc_entry( "fasttimer", 0, 0 )))
- fasttimer_proc_entry->read_proc = proc_fasttimer_read;
+ fasttimer_proc_entry = create_proc_entry("fasttimer", 0, 0);
+ if (fasttimer_proc_entry)
+ fasttimer_proc_entry->read_proc = proc_fasttimer_read;
#endif /* PROC_FS */
- if(request_irq(TIMER_INTR_VECT, timer_trig_interrupt, IRQF_DISABLED,
- "fast timer int", NULL))
- {
- printk("err: timer1 irq\n");
- }
+ if (request_irq(TIMER0_INTR_VECT, timer_trig_interrupt,
+ IRQF_SHARED | IRQF_DISABLED,
+ "fast timer int", &fast_timer_list))
+ printk(KERN_ERR "err: fasttimer irq\n");
fast_timer_is_init = 1;
#ifdef FAST_TIMER_TEST
printk("do test\n");
fast_timer_test();
#endif
}
+ return 0;
}
+__initcall(fast_timer_init);
* Copyright (C) 2003, Axis Communications AB
*/
-
#define ASSEMBLER_MACROS_ONLY
/*
* The macros found in mmu_defs_asm.h uses the ## concatenation operator, so
* -traditional must not be used when assembling this file.
*/
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/asm/mmu_defs_asm.h>
-#include <asm/arch/hwregs/asm/reg_map_asm.h>
-#include <asm/arch/hwregs/asm/config_defs_asm.h>
-#include <asm/arch/hwregs/asm/bif_core_defs_asm.h>
+#include <hwregs/reg_rdwr.h>
+#include <asm/arch/memmap.h>
+#include <hwregs/intr_vect.h>
+#include <hwregs/asm/mmu_defs_asm.h>
+#include <hwregs/asm/reg_map_asm.h>
+#include <asm/arch/mach/startup.inc>
#define CRAMFS_MAGIC 0x28cd3d45
+#define JHEAD_MAGIC 0x1FF528A6
+#define JHEAD_SIZE 8
#define RAM_INIT_MAGIC 0x56902387
#define COMMAND_LINE_MAGIC 0x87109563
+#define NAND_BOOT_MAGIC 0x9a9db001
;; NOTE: R8 and R9 carry information from the decompressor (if the
;; kernel was compressed). They must not be used in the code below
.global romfs_start
.global romfs_length
.global romfs_in_flash
+ .global nand_boot
.global swapper_pg_dir
- .global crisv32_nand_boot
- .global crisv32_nand_cramfs_offset
;; Dummy section to make it bootable with current VCS simulator
-#ifdef CONFIG_ETRAXFS_SIM
+#ifdef CONFIG_ETRAX_VCS_SIM
.section ".boot", "ax"
ba tstart
nop
;;
di
- ;; Start clocks for used blocks.
- move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
- move.d [$r1], $r0
- or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
- REG_STATE(config, rw_clk_ctrl, bif, yes) | \
- REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
- move.d $r0, [$r1]
-
- ;; Set up waitstates etc
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1
- move.d $r1, [$r0]
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0
- move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1
- move.d $r1, [$r0]
-
-#ifdef CONFIG_ETRAXFS_SIM
- ;; Set up minimal flash waitstates
- move.d 0, $r10
- move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11
- move.d $r10, [$r11]
+ START_CLOCKS
+
+ SETUP_WAIT_STATES
+
+ GIO_INIT
+
+#ifdef CONFIG_SMP
+secondary_cpu_entry: /* Entry point for secondary CPUs */
+ di
#endif
;; Setup and enable the MMU. Use same configuration for both the data
;;
;; Note; 3 cycles is needed for a bank-select to take effect. Further;
;; bank 1 is the instruction MMU, bank 2 is the data MMU.
-#ifndef CONFIG_ETRAXFS_SIM
+#ifndef CONFIG_ETRAX_VCS_SIM
move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
| REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \
| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
;; Map the virtual DRAM to the RW eprom area at address 0.
;; Also map 0xa for the hook calls,
move.d REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8) \
- | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0) \
+ | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4) \
| REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) \
| REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa), $r0
#endif
;; Enable certain page protections and setup linear mapping
;; for f,e,c,b,4,0.
-#ifndef CONFIG_ETRAXFS_SIM
+#ifndef CONFIG_ETRAX_VCS_SIM
move.d REG_STATE(mmu, rw_mm_cfg, we, on) \
| REG_STATE(mmu, rw_mm_cfg, acc, on) \
| REG_STATE(mmu, rw_mm_cfg, ex, on) \
nop
nop
nop
- move $s10, $r0
+ move $s12, $r0
cmpq 0, $r0
beq master_cpu
nop
slave_cpu:
- ; A slave waits for cpu_now_booting to be equal to CPU ID.
- move.d cpu_now_booting, $r1
-slave_wait:
- cmp.d [$r1], $r0
- bne slave_wait
- nop
; Time to boot-up. Get stack location provided by master CPU.
move.d smp_init_current_idle_thread, $r1
move.d [$r1], $sp
jsr smp_callin
nop
master_cpu:
+ /* Set up entry point for secondary CPUs. The boot ROM has set up
+ * EBP at start of internal memory. The CPU will get there
+ * later when we issue an IPI to them... */
+ move.d MEM_INTMEM_START + IPI_INTR_VECT * 4, $r0
+ move.d secondary_cpu_entry, $r1
+ move.d $r1, [$r0]
#endif
-#ifndef CONFIG_ETRAXFS_SIM
- ;; Check if starting from DRAM or flash.
+#ifndef CONFIG_ETRAX_VCS_SIM
+ ; Check if starting from DRAM (network->RAM boot or unpacked
+ ; compressed kernel), or directly from flash.
lapcq ., $r0
and.d 0x7fffffff, $r0 ; Mask off the non-cache bit.
cmp.d 0x10000, $r0 ; Arbitrary, something above this code.
beq _dram_initialized
nop
-#include "../lib/dram_init.S"
+#include "../mach/dram_init.S"
_dram_initialized:
;; Copy the text and data section to DRAM. This depends on that the
;; variables used below are correctly set up by the linker script.
;; The calculated value stored in R4 is used below.
+ ;; Leave the cramfs file system (piggybacked after the kernel) in flash.
moveq 0, $r0 ; Source.
move.d text_start, $r1 ; Destination.
move.d __vmlinux_end, $r2
blo 1b
nop
- ;; Keep CRAMFS in flash.
+ ;; Check for cramfs.
moveq 0, $r0
move.d romfs_length, $r1
move.d $r0, [$r1]
bne 1f
nop
+ ;; Set length and start of cramfs, set romfs_in_flash flag
addoq +4, $r4, $acr
move.d [$acr], $r0
move.d romfs_length, $r1
nop
_inram:
- ;; Check if booting from NAND flash (in that case we just remember the offset
- ;; into the flash where cramfs should be).
- move.d REG_ADDR(config, regi_config, r_bootsel), $r0
- move.d [$r0], $r0
- and.d REG_MASK(config, r_bootsel, boot_mode), $r0
- cmp.d REG_STATE(config, r_bootsel, boot_mode, nand), $r0
- bne move_cramfs
- moveq 1,$r0
- move.d crisv32_nand_boot, $r1
- move.d $r0, [$r1]
- move.d crisv32_nand_cramfs_offset, $r1
- move.d $r9, [$r1]
+ ;; Check if booting from NAND flash; if so, set appropriate flags
+ ;; and move on.
+ cmp.d NAND_BOOT_MAGIC, $r12
+ bne move_cramfs ; not nand, jump
moveq 1, $r0
- move.d romfs_in_flash, $r1
+ move.d nand_boot, $r1 ; tell axisflashmap we're booting from NAND
+ move.d $r0, [$r1]
+ moveq 0, $r0 ; tell axisflashmap romfs is not in
+ move.d romfs_in_flash, $r1 ; (directly accessed) flash
move.d $r0, [$r1]
- jump _start_it
+ jump _start_it ; continue with boot
nop
move_cramfs:
- ;; Move the cramfs after BSS.
+ ;; kernel is in DRAM.
+ ;; Must figure out if there is a piggybacked rootfs image or not.
+ ;; Set romfs_length to 0 => no rootfs image available by default.
moveq 0, $r0
move.d romfs_length, $r1
move.d $r0, [$r1]
-#ifndef CONFIG_ETRAXFS_SIM
+#ifndef CONFIG_ETRAX_VCS_SIM
;; The kernel could have been unpacked to DRAM by the loader, but
- ;; the cramfs image could still be inte the flash immediately
- ;; following the compressed kernel image. The loaded passes the address
- ;; of the bute succeeding the last compressed byte in the flash in
+ ;; the cramfs image could still be in the flash immediately
+ ;; following the compressed kernel image. The loader passes the address
+ ;; of the byte succeeding the last compressed byte in the flash in
;; register R9 when starting the kernel.
cmp.d 0x0ffffff8, $r9
bhs _no_romfs_in_flash ; R9 points outside the flash area.
ba _no_romfs_in_flash
nop
#endif
+ ;; cramfs rootfs might to be in flash. Check for it.
move.d [$r9], $r0 ; cramfs_super.magic
cmp.d CRAMFS_MAGIC, $r0
bne _no_romfs_in_flash
nop
+ ;; found cramfs in flash. set address and size, and romfs_in_flash flag.
addoq +4, $r9, $acr
move.d [$acr], $r0
move.d romfs_length, $r1
nop
_no_romfs_in_flash:
- ;; Look for cramfs.
+ ;; No romfs in flash, so look for cramfs, or jffs2 with jhead,
+ ;; after kernel in RAM, as is the case with network->RAM boot.
+ ;; For cramfs, partition starts with magic and length.
+ ;; For jffs2, a jhead is prepended which contains with magic and length.
+ ;; The jhead is not part of the jffs2 partition however.
#ifndef CONFIG_ETRAXFS_SIM
move.d __vmlinux_end, $r0
#else
move.d __end, $r0
#endif
move.d [$r0], $r1
- cmp.d CRAMFS_MAGIC, $r1
- bne 2f
+ cmp.d CRAMFS_MAGIC, $r1 ; cramfs magic?
+ beq 2f ; yes, jump
+ nop
+ cmp.d JHEAD_MAGIC, $r1 ; jffs2 (jhead) magic?
+ bne 4f ; no, skip copy
nop
+ addq 4, $r0 ; location of jffs2 size
+ move.d [$r0+], $r2 ; fetch jffs2 size -> r2
+ ; r0 now points to start of jffs2
+ ba 3f
+ nop
+2:
+ addoq +4, $r0, $acr ; location of cramfs size
+ move.d [$acr], $r2 ; fetch cramfs size -> r2
+ ; r0 still points to start of cramfs
+3:
+ ;; Now, move the root fs to after kernel's BSS
- addoq +4, $r0, $acr
- move.d [$acr], $r2
- move.d _end, $r1
+ move.d _end, $r1 ; start of cramfs -> r1
move.d romfs_start, $r3
- move.d $r1, [$r3]
+ move.d $r1, [$r3] ; store at romfs_start (for axisflashmap)
move.d romfs_length, $r3
- move.d $r2, [$r3]
+ move.d $r2, [$r3] ; store size at romfs_length
-#ifndef CONFIG_ETRAXFS_SIM
- add.d $r2, $r0
+#ifndef CONFIG_ETRAX_VCS_SIM
+ add.d $r2, $r0 ; copy from end and downwards
add.d $r2, $r1
lsrq 1, $r2 ; Size is in bytes, we copy words.
nop
#endif
-2:
+4:
+ ;; BSS move done.
+ ;; Clear romfs_in_flash flag, as we now know romfs is in DRAM
+ ;; Also clear nand_boot flag; if we got here, we know we've not
+ ;; booted from NAND flash.
moveq 0, $r0
move.d romfs_in_flash, $r1
move.d $r0, [$r1]
+ moveq 0, $r0
+ move.d nand_boot, $r1
+ move.d $r0, [$r1]
jump _start_it ; Jump to cached code.
nop
move.d cris_command_line, $r10
or.d 0x80000000, $r11 ; Make it virtual
1:
- move.b [$r11+], $r12
- move.b $r12, [$r10+]
+ move.b [$r11+], $r1
+ move.b $r1, [$r10+]
subq 1, $r13
bne 1b
nop
move.d etrax_irv, $r1 ; Set the exception base register and pointer.
move.d $r0, [$r1]
-#ifndef CONFIG_ETRAXFS_SIM
+#ifndef CONFIG_ETRAX_VCS_SIM
;; Clear the BSS region from _bss_start to _end.
move.d __bss_start, $r0
move.d _end, $r1
nop
#endif
-#ifdef CONFIG_ETRAXFS_SIM
+#ifdef CONFIG_ETRAX_VCS_SIM
/* Set the watchdog timeout to something big. Will be removed when */
/* watchdog can be disabled with command line option */
move.d 0x7fffffff, $r10
move.d __bss_start, $r0
movem [$r0], $r13
+#ifdef CONFIG_ETRAX_L2CACHE
+ jsr l2cache_init
+ nop
+#endif
+
jump start_kernel ; Jump to start_kernel() in init/main.c.
nop
.data
etrax_irv:
.dword 0
+
+; Variables for communication with the Axis flash map driver (axisflashmap),
+; and for setting up memory in arch/cris/kernel/setup.c .
+
+; romfs_start is set to the start of the root file system, if it exists
+; in directly accessible memory (i.e. NOR Flash when booting from Flash,
+; or RAM when booting directly from a network-downloaded RAM image)
romfs_start:
.dword 0
+
+; romfs_length is set to the size of the root file system image, if it exists
+; in directly accessible memory (see romfs_start). Otherwise it is set to 0.
romfs_length:
.dword 0
+
+; romfs_in_flash is set to 1 if the root file system resides in directly
+; accessible flash memory (i.e. NOR flash). It is set to 0 for RAM boot
+; or NAND flash boot.
romfs_in_flash:
.dword 0
-crisv32_nand_boot:
- .dword 0
-crisv32_nand_cramfs_offset:
+
+; nand_boot is set to 1 when the kernel has been booted from NAND flash
+nand_boot:
.dword 0
swapper_pg_dir = 0xc0002000
.section ".init.data", "aw"
-#include "../lib/hw_settings.S"
+#include "../mach/hw_settings.S"
+++ /dev/null
-/*
- * Helper functions for I/O pins.
- *
- * Copyright (c) 2004 Axis Communications AB.
- */
-
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <linux/ctype.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <asm/io.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/hwregs/gio_defs.h>
-
-struct crisv32_ioport crisv32_ioports[] =
-{
- {
- (unsigned long*)REG_ADDR(gio, regi_gio, rw_pa_oe),
- (unsigned long*)REG_ADDR(gio, regi_gio, rw_pa_dout),
- (unsigned long*)REG_ADDR(gio, regi_gio, r_pa_din),
- 8
- },
- {
- (unsigned long*)REG_ADDR(gio, regi_gio, rw_pb_oe),
- (unsigned long*)REG_ADDR(gio, regi_gio, rw_pb_dout),
- (unsigned long*)REG_ADDR(gio, regi_gio, r_pb_din),
- 18
- },
- {
- (unsigned long*)REG_ADDR(gio, regi_gio, rw_pc_oe),
- (unsigned long*)REG_ADDR(gio, regi_gio, rw_pc_dout),
- (unsigned long*)REG_ADDR(gio, regi_gio, r_pc_din),
- 18
- },
- {
- (unsigned long*)REG_ADDR(gio, regi_gio, rw_pd_oe),
- (unsigned long*)REG_ADDR(gio, regi_gio, rw_pd_dout),
- (unsigned long*)REG_ADDR(gio, regi_gio, r_pd_din),
- 18
- },
- {
- (unsigned long*)REG_ADDR(gio, regi_gio, rw_pe_oe),
- (unsigned long*)REG_ADDR(gio, regi_gio, rw_pe_dout),
- (unsigned long*)REG_ADDR(gio, regi_gio, r_pe_din),
- 18
- }
-};
-
-#define NBR_OF_PORTS ARRAY_SIZE(crisv32_ioports)
-
-struct crisv32_iopin crisv32_led1_green;
-struct crisv32_iopin crisv32_led1_red;
-struct crisv32_iopin crisv32_led2_green;
-struct crisv32_iopin crisv32_led2_red;
-struct crisv32_iopin crisv32_led3_green;
-struct crisv32_iopin crisv32_led3_red;
-
-/* Dummy port used when green LED and red LED is on the same bit */
-static unsigned long io_dummy;
-static struct crisv32_ioport dummy_port =
-{
- &io_dummy,
- &io_dummy,
- &io_dummy,
- 18
-};
-static struct crisv32_iopin dummy_led =
-{
- &dummy_port,
- 0
-};
-
-static int __init crisv32_io_init(void)
-{
- int ret = 0;
- /* Initialize LEDs */
- ret += crisv32_io_get_name(&crisv32_led1_green, CONFIG_ETRAX_LED1G);
- ret += crisv32_io_get_name(&crisv32_led1_red, CONFIG_ETRAX_LED1R);
- ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_LED2G);
- ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_LED2R);
- ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_LED3G);
- ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_LED3R);
- crisv32_io_set_dir(&crisv32_led1_green, crisv32_io_dir_out);
- crisv32_io_set_dir(&crisv32_led1_red, crisv32_io_dir_out);
- crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
- crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
- crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
- crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
-
- if (!strcmp(CONFIG_ETRAX_LED1G, CONFIG_ETRAX_LED1R))
- crisv32_led1_red = dummy_led;
- if (!strcmp(CONFIG_ETRAX_LED2G, CONFIG_ETRAX_LED2R))
- crisv32_led2_red = dummy_led;
-
- return ret;
-}
-
-__initcall(crisv32_io_init);
-
-int crisv32_io_get(struct crisv32_iopin* iopin,
- unsigned int port, unsigned int pin)
-{
- if (port > NBR_OF_PORTS)
- return -EINVAL;
- if (port > crisv32_ioports[port].pin_count)
- return -EINVAL;
-
- iopin->bit = 1 << pin;
- iopin->port = &crisv32_ioports[port];
-
- if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
- return -EIO;
-
- return 0;
-}
-
-int crisv32_io_get_name(struct crisv32_iopin* iopin,
- char* name)
-{
- int port;
- int pin;
-
- if (toupper(*name) == 'P')
- name++;
-
- if (toupper(*name) < 'A' || toupper(*name) > 'E')
- return -EINVAL;
-
- port = toupper(*name) - 'A';
- name++;
- pin = simple_strtoul(name, NULL, 10);
-
- if (pin < 0 || pin > crisv32_ioports[port].pin_count)
- return -EINVAL;
-
- iopin->bit = 1 << pin;
- iopin->port = &crisv32_ioports[port];
-
- if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
- return -EIO;
-
- return 0;
-}
-
-#ifdef CONFIG_PCI
-/* PCI I/O access stuff */
-struct cris_io_operations* cris_iops = NULL;
-EXPORT_SYMBOL(cris_iops);
-#endif
-
#include <linux/threads.h>
#include <linux/spinlock.h>
#include <linux/kernel_stat.h>
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/intr_vect.h>
-#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/intr_vect.h>
+#include <hwregs/intr_vect_defs.h>
#define CPU_FIXED -1
/* IRQ masks (refer to comment for crisv32_do_multiple) */
-#define TIMER_MASK (1 << (TIMER_INTR_VECT - FIRST_IRQ))
+#if TIMER0_INTR_VECT - FIRST_IRQ < 32
+#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ))
+#undef TIMER_VECT1
+#else
+#define TIMER_MASK (1 << (TIMER0_INTR_VECT - FIRST_IRQ - 32))
+#define TIMER_VECT1
+#endif
#ifdef CONFIG_ETRAX_KGDB
#if defined(CONFIG_ETRAX_KGDB_PORT0)
#define IGNOREMASK (1 << (SER0_INTR_VECT - FIRST_IRQ))
cpumask_t mask; /* The CPUs to which the IRQ may be allocated. */
};
-struct cris_irq_allocation irq_allocations[NR_IRQS] =
- {[0 ... NR_IRQS - 1] = {0, CPU_MASK_ALL}};
+struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =
+ { [0 ... NR_REAL_IRQS - 1] = {0, CPU_MASK_ALL} };
static unsigned long irq_regs[NR_CPUS] =
{
#endif
};
+#if NR_REAL_IRQS > 32
+#define NBR_REGS 2
+#else
+#define NBR_REGS 1
+#endif
+
unsigned long cpu_irq_counters[NR_CPUS];
unsigned long irq_counters[NR_REAL_IRQS];
extern void kgdb_init(void);
extern void breakpoint(void);
+/* From traps.c. */
+extern void breakh_BUG(void);
+
/*
- * Build the IRQ handler stubs using macros from irq.h. First argument is the
- * IRQ number, the second argument is the corresponding bit in
- * intr_rw_vect_mask found in asm/arch/hwregs/intr_vect_defs.h.
+ * Build the IRQ handler stubs using macros from irq.h.
*/
-BUILD_IRQ(0x31, (1 << 0)) /* memarb */
-BUILD_IRQ(0x32, (1 << 1)) /* gen_io */
-BUILD_IRQ(0x33, (1 << 2)) /* iop0 */
-BUILD_IRQ(0x34, (1 << 3)) /* iop1 */
-BUILD_IRQ(0x35, (1 << 4)) /* iop2 */
-BUILD_IRQ(0x36, (1 << 5)) /* iop3 */
-BUILD_IRQ(0x37, (1 << 6)) /* dma0 */
-BUILD_IRQ(0x38, (1 << 7)) /* dma1 */
-BUILD_IRQ(0x39, (1 << 8)) /* dma2 */
-BUILD_IRQ(0x3a, (1 << 9)) /* dma3 */
-BUILD_IRQ(0x3b, (1 << 10)) /* dma4 */
-BUILD_IRQ(0x3c, (1 << 11)) /* dma5 */
-BUILD_IRQ(0x3d, (1 << 12)) /* dma6 */
-BUILD_IRQ(0x3e, (1 << 13)) /* dma7 */
-BUILD_IRQ(0x3f, (1 << 14)) /* dma8 */
-BUILD_IRQ(0x40, (1 << 15)) /* dma9 */
-BUILD_IRQ(0x41, (1 << 16)) /* ata */
-BUILD_IRQ(0x42, (1 << 17)) /* sser0 */
-BUILD_IRQ(0x43, (1 << 18)) /* sser1 */
-BUILD_IRQ(0x44, (1 << 19)) /* ser0 */
-BUILD_IRQ(0x45, (1 << 20)) /* ser1 */
-BUILD_IRQ(0x46, (1 << 21)) /* ser2 */
-BUILD_IRQ(0x47, (1 << 22)) /* ser3 */
-BUILD_IRQ(0x48, (1 << 23))
-BUILD_IRQ(0x49, (1 << 24)) /* eth0 */
-BUILD_IRQ(0x4a, (1 << 25)) /* eth1 */
-BUILD_TIMER_IRQ(0x4b, (1 << 26))/* timer */
-BUILD_IRQ(0x4c, (1 << 27)) /* bif_arb */
-BUILD_IRQ(0x4d, (1 << 28)) /* bif_dma */
-BUILD_IRQ(0x4e, (1 << 29)) /* ext */
-BUILD_IRQ(0x4f, (1 << 29)) /* ipi */
+BUILD_IRQ(0x31)
+BUILD_IRQ(0x32)
+BUILD_IRQ(0x33)
+BUILD_IRQ(0x34)
+BUILD_IRQ(0x35)
+BUILD_IRQ(0x36)
+BUILD_IRQ(0x37)
+BUILD_IRQ(0x38)
+BUILD_IRQ(0x39)
+BUILD_IRQ(0x3a)
+BUILD_IRQ(0x3b)
+BUILD_IRQ(0x3c)
+BUILD_IRQ(0x3d)
+BUILD_IRQ(0x3e)
+BUILD_IRQ(0x3f)
+BUILD_IRQ(0x40)
+BUILD_IRQ(0x41)
+BUILD_IRQ(0x42)
+BUILD_IRQ(0x43)
+BUILD_IRQ(0x44)
+BUILD_IRQ(0x45)
+BUILD_IRQ(0x46)
+BUILD_IRQ(0x47)
+BUILD_IRQ(0x48)
+BUILD_IRQ(0x49)
+BUILD_IRQ(0x4a)
+BUILD_IRQ(0x4b)
+BUILD_IRQ(0x4c)
+BUILD_IRQ(0x4d)
+BUILD_IRQ(0x4e)
+BUILD_IRQ(0x4f)
+BUILD_IRQ(0x50)
+#if MACH_IRQS > 32
+BUILD_IRQ(0x51)
+BUILD_IRQ(0x52)
+BUILD_IRQ(0x53)
+BUILD_IRQ(0x54)
+BUILD_IRQ(0x55)
+BUILD_IRQ(0x56)
+BUILD_IRQ(0x57)
+BUILD_IRQ(0x58)
+BUILD_IRQ(0x59)
+BUILD_IRQ(0x5a)
+BUILD_IRQ(0x5b)
+BUILD_IRQ(0x5c)
+BUILD_IRQ(0x5d)
+BUILD_IRQ(0x5e)
+BUILD_IRQ(0x5f)
+BUILD_IRQ(0x60)
+BUILD_IRQ(0x61)
+BUILD_IRQ(0x62)
+BUILD_IRQ(0x63)
+BUILD_IRQ(0x64)
+BUILD_IRQ(0x65)
+BUILD_IRQ(0x66)
+BUILD_IRQ(0x67)
+BUILD_IRQ(0x68)
+BUILD_IRQ(0x69)
+BUILD_IRQ(0x6a)
+BUILD_IRQ(0x6b)
+BUILD_IRQ(0x6c)
+BUILD_IRQ(0x6d)
+BUILD_IRQ(0x6e)
+BUILD_IRQ(0x6f)
+BUILD_IRQ(0x70)
+#endif
/* Pointers to the low-level handlers. */
-static void (*interrupt[NR_IRQS])(void) = {
+static void (*interrupt[MACH_IRQS])(void) = {
IRQ0x31_interrupt, IRQ0x32_interrupt, IRQ0x33_interrupt,
IRQ0x34_interrupt, IRQ0x35_interrupt, IRQ0x36_interrupt,
IRQ0x37_interrupt, IRQ0x38_interrupt, IRQ0x39_interrupt,
IRQ0x46_interrupt, IRQ0x47_interrupt, IRQ0x48_interrupt,
IRQ0x49_interrupt, IRQ0x4a_interrupt, IRQ0x4b_interrupt,
IRQ0x4c_interrupt, IRQ0x4d_interrupt, IRQ0x4e_interrupt,
- IRQ0x4f_interrupt
+ IRQ0x4f_interrupt, IRQ0x50_interrupt,
+#if MACH_IRQS > 32
+ IRQ0x51_interrupt, IRQ0x52_interrupt, IRQ0x53_interrupt,
+ IRQ0x54_interrupt, IRQ0x55_interrupt, IRQ0x56_interrupt,
+ IRQ0x57_interrupt, IRQ0x58_interrupt, IRQ0x59_interrupt,
+ IRQ0x5a_interrupt, IRQ0x5b_interrupt, IRQ0x5c_interrupt,
+ IRQ0x5d_interrupt, IRQ0x5e_interrupt, IRQ0x5f_interrupt,
+ IRQ0x60_interrupt, IRQ0x61_interrupt, IRQ0x62_interrupt,
+ IRQ0x63_interrupt, IRQ0x64_interrupt, IRQ0x65_interrupt,
+ IRQ0x66_interrupt, IRQ0x67_interrupt, IRQ0x68_interrupt,
+ IRQ0x69_interrupt, IRQ0x6a_interrupt, IRQ0x6b_interrupt,
+ IRQ0x6c_interrupt, IRQ0x6d_interrupt, IRQ0x6e_interrupt,
+ IRQ0x6f_interrupt, IRQ0x70_interrupt,
+#endif
};
void
int intr_mask;
unsigned long flags;
- spin_lock_irqsave(&irq_lock, flags);
- intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
-
- /* Remember; 1 let through, 0 block. */
- intr_mask &= ~(1 << (irq - FIRST_IRQ));
-
- REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask);
+ spin_lock_irqsave(&irq_lock, flags);
+ if (irq - FIRST_IRQ < 32)
+ intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
+ rw_mask, 0);
+ else
+ intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
+ rw_mask, 1);
+
+ /* Remember; 1 let thru, 0 block. */
+ if (irq - FIRST_IRQ < 32)
+ intr_mask &= ~(1 << (irq - FIRST_IRQ));
+ else
+ intr_mask &= ~(1 << (irq - FIRST_IRQ - 32));
+
+ if (irq - FIRST_IRQ < 32)
+ REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
+ 0, intr_mask);
+ else
+ REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
+ 1, intr_mask);
spin_unlock_irqrestore(&irq_lock, flags);
}
unsigned long flags;
spin_lock_irqsave(&irq_lock, flags);
- intr_mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
-
- /* Remember; 1 let through, 0 block. */
- intr_mask |= (1 << (irq - FIRST_IRQ));
+ if (irq - FIRST_IRQ < 32)
+ intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
+ rw_mask, 0);
+ else
+ intr_mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
+ rw_mask, 1);
+
+ /* Remember; 1 let thru, 0 block. */
+ if (irq - FIRST_IRQ < 32)
+ intr_mask |= (1 << (irq - FIRST_IRQ));
+ else
+ intr_mask |= (1 << (irq - FIRST_IRQ - 32));
+
+ if (irq - FIRST_IRQ < 32)
+ REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
+ 0, intr_mask);
+ else
+ REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask,
+ 1, intr_mask);
- REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, intr_mask);
spin_unlock_irqrestore(&irq_lock, flags);
}
{
int cpu;
int mask;
- int masked;
+ int masked[NBR_REGS];
int bit;
+ int i;
cpu = smp_processor_id();
*/
irq_enter();
- /* Get which IRQs that happened. */
- masked = REG_RD_INT(intr_vect, irq_regs[cpu], r_masked_vect);
+ for (i = 0; i < NBR_REGS; i++) {
+ /* Get which IRQs that happend. */
+ masked[i] = REG_RD_INT_VECT(intr_vect, irq_regs[cpu],
+ r_masked_vect, i);
- /* Calculate new IRQ mask with these IRQs disabled. */
- mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
- mask &= ~masked;
+ /* Calculate new IRQ mask with these IRQs disabled. */
+ mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
+ mask &= ~masked[i];
/* Timer IRQ is never masked */
- if (masked & TIMER_MASK)
- mask |= TIMER_MASK;
-
- /* Block all the IRQs */
- REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask);
+#ifdef TIMER_VECT1
+ if ((i == 1) && (masked[0] & TIMER_MASK))
+ mask |= TIMER_MASK;
+#else
+ if ((i == 0) && (masked[0] & TIMER_MASK))
+ mask |= TIMER_MASK;
+#endif
+ /* Block all the IRQs */
+ REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
/* Check for timer IRQ and handle it special. */
- if (masked & TIMER_MASK) {
- masked &= ~TIMER_MASK;
- do_IRQ(TIMER_INTR_VECT, regs);
+#ifdef TIMER_VECT1
+ if ((i == 1) && (masked[i] & TIMER_MASK)) {
+ masked[i] &= ~TIMER_MASK;
+ do_IRQ(TIMER0_INTR_VECT, regs);
+ }
+#else
+ if ((i == 0) && (masked[i] & TIMER_MASK)) {
+ masked[i] &= ~TIMER_MASK;
+ do_IRQ(TIMER0_INTR_VECT, regs);
+ }
}
+#endif
#ifdef IGNORE_MASK
/* Remove IRQs that can't be handled as multiple. */
- masked &= ~IGNORE_MASK;
+ masked[0] &= ~IGNORE_MASK;
#endif
/* Handle the rest of the IRQs. */
- for (bit = 0; bit < 32; bit++)
- {
- if (masked & (1 << bit))
- do_IRQ(bit + FIRST_IRQ, regs);
+ for (i = 0; i < NBR_REGS; i++) {
+ for (bit = 0; bit < 32; bit++) {
+ if (masked[i] & (1 << bit))
+ do_IRQ(bit + FIRST_IRQ + i*32, regs);
+ }
}
/* Unblock all the IRQs. */
- mask = REG_RD_INT(intr_vect, irq_regs[cpu], rw_mask);
- mask |= masked;
- REG_WR_INT(intr_vect, irq_regs[cpu], rw_mask, mask);
+ for (i = 0; i < NBR_REGS; i++) {
+ mask = REG_RD_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i);
+ mask |= masked[i];
+ REG_WR_INT_VECT(intr_vect, irq_regs[cpu], rw_mask, i, mask);
+ }
/* This irq_exit() will trigger the soft IRQs. */
irq_exit();
reg_intr_vect_rw_mask vect_mask = {0};
/* Clear all interrupts masks. */
- REG_WR(intr_vect, regi_irq, rw_mask, vect_mask);
+ for (i = 0; i < NBR_REGS; i++)
+ REG_WR_VECT(intr_vect, regi_irq, rw_mask, i, vect_mask);
for (i = 0; i < 256; i++)
etrax_irv->v[i] = weird_irq;
- /* Point all IRQs to bad handlers. */
+ /* Point all IRQ's to bad handlers. */
for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
irq_desc[j].chip = &crisv32_irq_type;
set_exception_vector(i, interrupt[j]);
}
/* Mark Timer and IPI IRQs as CPU local */
- irq_allocations[TIMER_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
- irq_desc[TIMER_INTR_VECT].status |= IRQ_PER_CPU;
+ irq_allocations[TIMER0_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
+ irq_desc[TIMER0_INTR_VECT].status |= IRQ_PER_CPU;
irq_allocations[IPI_INTR_VECT - FIRST_IRQ].cpu = CPU_FIXED;
irq_desc[IPI_INTR_VECT].status |= IRQ_PER_CPU;
set_exception_vector(0x0a, d_mmu_access);
set_exception_vector(0x0b, d_mmu_write);
+#ifdef CONFIG_BUG
+ /* Break 14 handler, used to implement cheap BUG(). */
+ set_exception_vector(0x1e, breakh_BUG);
+#endif
+
/* The system-call trap is reached by "break 13". */
set_exception_vector(0x1d, system_call);
/* Serial port, reads one character. ETRAX 100 specific. from debugport.c */
int getDebugChar(void);
-#ifdef CONFIG_ETRAXFS_SIM
+#ifdef CONFIG_ETRAX_VCS_SIM
int getDebugChar(void)
{
return socketread();
/* Serial port, writes one character. ETRAX 100 specific. from debugport.c */
void putDebugChar(int val);
-#ifdef CONFIG_ETRAXFS_SIM
+#ifdef CONFIG_ETRAX_VCS_SIM
void putDebugChar(int val)
{
socketwrite((char *)&val, 1);
REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
ser_intr_mask = REG_RD(ser, regi_ser0, rw_intr_mask);
- ser_intr_mask.data_avail = regk_ser_yes;
+ ser_intr_mask.dav = regk_ser_yes;
REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask);
#elif defined(CONFIG_ETRAX_KGDB_PORT1)
/* Note: no shortcut registered (not handled by multiple_interrupt).
REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
ser_intr_mask = REG_RD(ser, regi_ser1, rw_intr_mask);
- ser_intr_mask.data_avail = regk_ser_yes;
+ ser_intr_mask.dav = regk_ser_yes;
REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask);
#elif defined(CONFIG_ETRAX_KGDB_PORT2)
/* Note: no shortcut registered (not handled by multiple_interrupt).
REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
ser_intr_mask = REG_RD(ser, regi_ser2, rw_intr_mask);
- ser_intr_mask.data_avail = regk_ser_yes;
+ ser_intr_mask.dav = regk_ser_yes;
REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask);
#elif defined(CONFIG_ETRAX_KGDB_PORT3)
/* Note: no shortcut registered (not handled by multiple_interrupt).
REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
ser_intr_mask = REG_RD(ser, regi_ser3, rw_intr_mask);
- ser_intr_mask.data_avail = regk_ser_yes;
+ ser_intr_mask.dav = regk_ser_yes;
REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask);
#endif
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/slab.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/timer_defs.h>
-#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/timer_defs.h>
+#include <hwregs/intr_vect_defs.h>
extern void stop_watchdog(void);
-#ifdef CONFIG_ETRAX_GPIO
-extern void etrax_gpio_wake_up_check(void); /* Defined in drivers/gpio.c. */
-#endif
-
extern int cris_hlt_counter;
/* We use this if we don't have any better idle routine. */
wd_ctrl.cmd = regk_timer_start;
arch_enable_nmi();
- REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
+ REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
}
#endif
/*
- * Copyright (C) 2000-2003, Axis Communications AB.
+ * Copyright (C) 2000-2007, Axis Communications AB.
*/
#include <linux/kernel.h>
ret = generic_ptrace_pokedata(child, addr, data);
break;
- /* Write the word at location address in the USER area. */
+ /* Write the word at location address in the USER area. */
case PTRACE_POKEUSR:
ret = -EIO;
if ((addr & 3) || addr < 0 || addr > PT_MAX << 2)
break;
- /* Make the child exit by sending it a sigkill. */
+ /* Make the child exit by sending it a sigkill. */
case PTRACE_KILL:
ret = 0;
break;
}
+
/* Get all GP registers from the child. */
case PTRACE_GETREGS: {
- int i;
+ int i;
unsigned long tmp;
for (i = 0; i <= PT_MAX; i++) {
break;
}
+out_tsk:
return ret;
}
unsigned char retcode[8]; /* Trampoline code. */
};
-int do_signal(int restart, sigset_t *oldset, struct pt_regs *regs);
+void do_signal(int restart, struct pt_regs *regs);
void keep_debug_flags(unsigned long oldccs, unsigned long oldspc,
struct pt_regs *regs);
/*
sys_sigsuspend(old_sigset_t mask, long r11, long r12, long r13, long mof,
long srp, struct pt_regs *regs)
{
- sigset_t saveset;
-
mask &= _BLOCKABLE;
-
spin_lock_irq(¤t->sighand->siglock);
-
- saveset = current->blocked;
-
+ current->saved_sigmask = current->blocked;
siginitset(¤t->blocked, mask);
-
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
-
- regs->r10 = -EINTR;
-
- while (1) {
- current->state = TASK_INTERRUPTIBLE;
- schedule();
-
- if (do_signal(0, &saveset, regs)) {
- /*
- * This point is reached twice: once to call
- * the signal handler, then again to return
- * from the sigsuspend system call. When
- * calling the signal handler, R10 hold the
- * signal number as set by do_signal(). The
- * sigsuspend call will always return with
- * the restored value above; -EINTR.
- */
- return regs->r10;
- }
- }
-}
-
-/* Define some dummy arguments to be able to reach the regs argument. */
-int
-sys_rt_sigsuspend(sigset_t *unewset, size_t sigsetsize, long r12, long r13,
- long mof, long srp, struct pt_regs *regs)
-{
- sigset_t saveset;
- sigset_t newset;
-
- if (sigsetsize != sizeof(sigset_t))
- return -EINVAL;
-
- if (copy_from_user(&newset, unewset, sizeof(newset)))
- return -EFAULT;
-
- sigdelsetmask(&newset, ~_BLOCKABLE);
- spin_lock_irq(¤t->sighand->siglock);
-
- saveset = current->blocked;
- current->blocked = newset;
-
recalc_sigpending();
spin_unlock_irq(¤t->sighand->siglock);
-
- regs->r10 = -EINTR;
-
- while (1) {
- current->state = TASK_INTERRUPTIBLE;
- schedule();
-
- if (do_signal(0, &saveset, regs)) {
- /* See comment in function above. */
- return regs->r10;
- }
- }
+ current->state = TASK_INTERRUPTIBLE;
+ schedule();
+ set_thread_flag(TIF_RESTORE_SIGMASK);
+ return -ERESTARTNOHAND;
}
int
goto badframe;
if (do_sigaltstack(&frame->uc.uc_stack, NULL, rdusp()) == -EFAULT)
- goto badframe;
+ goto badframe;
keep_debug_flags(oldccs, oldspc, regs);
/* Grab and setup a signal frame.
*
* Basically a lot of state-info is stacked, and arranged for the
- * user-mode program to return to the kernel using either a trampoline
+ * user-mode program to return to the kernel using either a trampiline
* which performs the syscall sigreturn(), or a provided user-mode
* trampoline.
*/
-static void
+static int
setup_frame(int sig, struct k_sigaction *ka, sigset_t *set,
struct pt_regs * regs)
{
/* Actually move the USP to reflect the stacked frame. */
wrusp((unsigned long)frame);
- return;
+ return 0;
give_sigsegv:
if (sig == SIGSEGV)
ka->sa.sa_handler = SIG_DFL;
force_sig(SIGSEGV, current);
+ return -EFAULT;
}
-static void
+static int
setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
sigset_t *set, struct pt_regs * regs)
{
/* Actually move the usp to reflect the stacked frame. */
wrusp((unsigned long)frame);
- return;
+ return 0;
give_sigsegv:
if (sig == SIGSEGV)
ka->sa.sa_handler = SIG_DFL;
force_sig(SIGSEGV, current);
+ return -EFAULT;
}
/* Invoke a singal handler to, well, handle the signal. */
-static inline void
+static inline int
handle_signal(int canrestart, unsigned long sig,
siginfo_t *info, struct k_sigaction *ka,
sigset_t *oldset, struct pt_regs * regs)
{
+ int ret;
+
/* Check if this got called from a system call. */
if (canrestart) {
/* If so, check system call restarting. */
/* Set up the stack frame. */
if (ka->sa.sa_flags & SA_SIGINFO)
- setup_rt_frame(sig, ka, info, oldset, regs);
+ ret = setup_rt_frame(sig, ka, info, oldset, regs);
else
- setup_frame(sig, ka, oldset, regs);
+ ret = setup_frame(sig, ka, oldset, regs);
if (ka->sa.sa_flags & SA_ONESHOT)
ka->sa.sa_handler = SIG_DFL;
- spin_lock_irq(¤t->sighand->siglock);
- sigorsets(¤t->blocked,¤t->blocked,&ka->sa.sa_mask);
- if (!(ka->sa.sa_flags & SA_NODEFER))
- sigaddset(¤t->blocked,sig);
- recalc_sigpending();
- spin_unlock_irq(¤t->sighand->siglock);
+ if (ret == 0) {
+ spin_lock_irq(¤t->sighand->siglock);
+ sigorsets(¤t->blocked, ¤t->blocked,
+ &ka->sa.sa_mask);
+ if (!(ka->sa.sa_flags & SA_NODEFER))
+ sigaddset(¤t->blocked, sig);
+ recalc_sigpending();
+ spin_unlock_irq(¤t->sighand->siglock);
+ }
+
+ return ret;
}
/*
* we can use user_mode(regs) to see if we came directly from kernel or user
* mode below.
*/
-int
-do_signal(int canrestart, sigset_t *oldset, struct pt_regs *regs)
+void
+do_signal(int canrestart, struct pt_regs *regs)
{
int signr;
siginfo_t info;
struct k_sigaction ka;
+ sigset_t *oldset;
/*
* The common case should go fast, which is why this point is
* without doing anything.
*/
if (!user_mode(regs))
- return 1;
+ return;
- if (!oldset)
+ if (test_thread_flag(TIF_RESTORE_SIGMASK))
+ oldset = ¤t->saved_sigmask;
+ else
oldset = ¤t->blocked;
signr = get_signal_to_deliver(&info, &ka, regs, NULL);
if (signr > 0) {
- /* Deliver the signal. */
- handle_signal(canrestart, signr, &info, &ka, oldset, regs);
- return 1;
+ /* Whee! Actually deliver the signal. */
+ if (handle_signal(canrestart, signr, &info, &ka,
+ oldset, regs)) {
+ /* a signal was successfully delivered; the saved
+ * sigmask will have been stored in the signal frame,
+ * and will be restored by sigreturn, so we can simply
+ * clear the TIF_RESTORE_SIGMASK flag */
+ if (test_thread_flag(TIF_RESTORE_SIGMASK))
+ clear_thread_flag(TIF_RESTORE_SIGMASK);
+ }
+
+ return;
}
/* Got here from a system call? */
}
}
- return 0;
+ /* if there's no signal to deliver, we just put the saved sigmask
+ * back */
+ if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+ clear_thread_flag(TIF_RESTORE_SIGMASK);
+ sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL);
+ }
}
asmlinkage void
user_regs(ti)->spc = 0;
}
/* FIXME: Filter out false h/w breakpoint hits (i.e. EDA
- not within any configured h/w breakpoint range). Synchronize with
+ not withing any configured h/w breakpoint range). Synchronize with
what already exists for kernel debugging. */
if (((user_regs(ti)->exs & 0xff00) >> 8) == BREAK_8_INTR_VECT) {
/* Break 8: subtract 2 from ERP unless in a delay slot. */
+#include <linux/types.h>
#include <asm/delay.h>
-#include <asm/arch/irq.h>
-#include <asm/arch/hwregs/intr_vect.h>
-#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <irq.h>
+#include <hwregs/intr_vect.h>
+#include <hwregs/intr_vect_defs.h>
#include <asm/tlbflush.h>
#include <asm/mmu_context.h>
-#include <asm/arch/hwregs/mmu_defs_asm.h>
-#include <asm/arch/hwregs/supp_reg.h>
+#include <hwregs/asm/mmu_defs_asm.h>
+#include <hwregs/supp_reg.h>
#include <asm/atomic.h>
#include <linux/err.h>
#define IPI_SCHEDULE 1
#define IPI_CALL 2
#define IPI_FLUSH_TLB 4
+#define IPI_BOOT 8
#define FLUSH_ALL (void*)0xffffffff
cpumask_t cpu_online_map = CPU_MASK_NONE;
EXPORT_SYMBOL(cpu_online_map);
cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
+cpumask_t cpu_possible_map;
+EXPORT_SYMBOL(cpu_possible_map);
EXPORT_SYMBOL(phys_cpu_present_map);
/* Variables used during SMP boot */
extern int setup_irq(int, struct irqaction *);
/* Mode registers */
-static unsigned long irq_regs[NR_CPUS] =
-{
+static unsigned long irq_regs[NR_CPUS] = {
regi_irq,
regi_irq2
};
-static irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id, struct pt_regs *regs);
+static irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id);
static int send_ipi(int vector, int wait, cpumask_t cpu_mask);
static struct irqaction irq_ipi = {
.handler = crisv32_ipi_interrupt,
cpu_set(0, cpu_online_map);
cpu_set(0, phys_cpu_present_map);
+ cpu_set(0, cpu_possible_map);
}
void __init smp_cpus_done(unsigned int max_cpus)
{
unsigned timeout;
struct task_struct *idle;
+ cpumask_t cpu_mask = CPU_MASK_NONE;
idle = fork_idle(cpuid);
if (IS_ERR(idle))
smp_init_current_idle_thread = task_thread_info(idle);
cpu_now_booting = cpuid;
+ /* Kick it */
+ cpu_set(cpuid, cpu_online_map);
+ cpu_set(cpuid, cpu_mask);
+ send_ipi(IPI_BOOT, 0, cpu_mask);
+ cpu_clear(cpuid, cpu_online_map);
+
/* Wait for CPU to come online */
for (timeout = 0; timeout < 10000; timeout++) {
if(cpu_online(cpuid)) {
/* Enable IRQ and idle */
REG_WR(intr_vect, irq_regs[cpu], rw_mask, vect_mask);
unmask_irq(IPI_INTR_VECT);
- unmask_irq(TIMER_INTR_VECT);
+ unmask_irq(TIMER0_INTR_VECT);
preempt_disable();
local_irq_enable();
return ret;
}
-irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id)
{
void (*func) (void *info) = call_data->func;
void *info = call_data->info;
-/* $Id: time.c,v 1.19 2005/04/29 05:40:09 starvik Exp $
- *
+/*
* linux/arch/cris/arch-v32/kernel/time.c
*
- * Copyright (C) 2003 Axis Communications AB
+ * Copyright (C) 2003-2007 Axis Communications AB
*
*/
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/threads.h>
+#include <linux/cpufreq.h>
#include <asm/types.h>
#include <asm/signal.h>
#include <asm/io.h>
#include <asm/delay.h>
#include <asm/rtc.h>
#include <asm/irq.h>
-
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/timer_defs.h>
-#include <asm/arch/hwregs/intr_vect_defs.h>
+#include <asm/irq_regs.h>
+
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/timer_defs.h>
+#include <hwregs/intr_vect_defs.h>
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+#include <hwregs/clkgen_defs.h>
+#endif
/* Watchdog defines */
-#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
-#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */
-#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1) /* Number of 763 counts before watchdog bites */
+#define ETRAX_WD_KEY_MASK 0x7F /* key is 7 bit */
+#define ETRAX_WD_HZ 763 /* watchdog counts at 763 Hz */
+/* Number of 763 counts before watchdog bites */
+#define ETRAX_WD_CNT ((2*ETRAX_WD_HZ)/HZ + 1)
unsigned long timer_regs[NR_CPUS] =
{
- regi_timer,
+ regi_timer0,
#ifdef CONFIG_SMP
- regi_timer2
+ regi_timer2
#endif
};
extern int setup_irq(int, struct irqaction *);
extern int have_rtc;
+#ifdef CONFIG_CPU_FREQ
+static int
+cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
+ void *data);
+
+static struct notifier_block cris_time_freq_notifier_block = {
+ .notifier_call = cris_time_freq_notifier,
+};
+#endif
+
unsigned long get_ns_in_jiffie(void)
{
reg_timer_r_tmr0_data data;
unsigned long ns;
- data = REG_RD(timer, regi_timer, r_tmr0_data);
+ data = REG_RD(timer, regi_timer0, r_tmr0_data);
ns = (TIMER0_DIV - data) * 10;
return ns;
}
unsigned long count;
unsigned long usec_count = 0;
- static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
+ /* For the first call after boot */
+ static unsigned long count_p = TIMER0_DIV;
static unsigned long jiffies_p = 0;
- /*
- * cache volatile jiffies temporarily; we have IRQs turned off.
- */
+ /* Cache volatile jiffies temporarily; we have IRQs turned off. */
unsigned long jiffies_t;
/* The timer interrupt comes from Etrax timer 0. In order to get
* better precision, we check the current value. It might have
- * underflowed already though.
- */
+ * underflowed already though. */
+ count = REG_RD(timer, regi_timer0, r_tmr0_data);
+ jiffies_t = jiffies;
- count = REG_RD(timer, regi_timer, r_tmr0_data);
- jiffies_t = jiffies;
-
- /*
- * avoiding timer inconsistencies (they are rare, but they happen)...
- * there are one problem that must be avoided here:
- * 1. the timer counter underflows
+ /* Avoiding timer inconsistencies (they are rare, but they happen)
+ * There is one problem that must be avoided here:
+ * 1. the timer counter underflows
*/
if( jiffies_t == jiffies_p ) {
if( count > count_p ) {
- /* Timer wrapped, use new count and prescale
- * increase the time corresponding to one jiffie
+ /* Timer wrapped, use new count and prescale.
+ * Increase the time corresponding to one jiffy.
*/
usec_count = 1000000/HZ;
}
*/
/* This gives us 1.3 ms to do something useful when the NMI comes */
-/* right now, starting the watchdog is the same as resetting it */
+/* Right now, starting the watchdog is the same as resetting it */
#define start_watchdog reset_watchdog
#if defined(CONFIG_ETRAX_WATCHDOG)
static short int watchdog_key = 42; /* arbitrary 7 bit number */
#endif
-/* number of pages to consider "out of memory". it is normal that the memory
- * is used though, so put this really low.
- */
-
+/* Number of pages to consider "out of memory". It is normal that the memory
+ * is used though, so set this really low. */
#define WATCHDOG_MIN_FREE_PAGES 8
void
#if defined(CONFIG_ETRAX_WATCHDOG)
reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
- /* only keep watchdog happy as long as we have memory left! */
+ /* Only keep watchdog happy as long as we have memory left! */
if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
- /* reset the watchdog with the inverse of the old key */
- watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
+ /* Reset the watchdog with the inverse of the old key */
+ /* Invert key, which is 7 bits */
+ watchdog_key ^= ETRAX_WD_KEY_MASK;
wd_ctrl.cnt = ETRAX_WD_CNT;
wd_ctrl.cmd = regk_timer_start;
wd_ctrl.key = watchdog_key;
- REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
+ REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
}
#endif
}
wd_ctrl.cnt = ETRAX_WD_CNT;
wd_ctrl.cmd = regk_timer_stop;
wd_ctrl.key = watchdog_key;
- REG_WR(timer, regi_timer, rw_wd_ctrl, wd_ctrl);
+ REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
#endif
}
#if defined(CONFIG_ETRAX_WATCHDOG)
extern int cause_of_death;
- raw_printk("Watchdog bite\n");
+ oops_in_progress = 1;
+ printk(KERN_WARNING "Watchdog bite\n");
/* Check if forced restart or unexpected watchdog */
if (cause_of_death == 0xbedead) {
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+ /* There is a bug in Artpec-3 (voodoo TR 78) that requires
+ * us to go to lower frequency for the reset to be reliable
+ */
+ reg_clkgen_rw_clk_ctrl ctrl =
+ REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
+ ctrl.pll = 0;
+ REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
+#endif
while(1);
}
- /* Unexpected watchdog, stop the watchdog and dump registers*/
+ /* Unexpected watchdog, stop the watchdog and dump registers. */
stop_watchdog();
- raw_printk("Oops: bitten by watchdog\n");
- show_registers(regs);
+ printk(KERN_WARNING "Oops: bitten by watchdog\n");
+ show_registers(regs);
+ oops_in_progress = 0;
#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
reset_watchdog();
#endif
#endif
}
-/* last time the cmos clock got updated */
+/* Last time the cmos clock got updated. */
static long last_rtc_update = 0;
/*
* timer_interrupt() needs to keep up the real-time clock,
- * as well as call the "do_timer()" routine every clocktick
+ * as well as call the "do_timer()" routine every clocktick.
*/
-
-//static unsigned short myjiff; /* used by our debug routine print_timestamp */
-
extern void cris_do_profile(struct pt_regs *regs);
static inline irqreturn_t
-timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+timer_interrupt(int irq, void *dev_id)
{
+ struct pt_regs *regs = get_irq_regs();
int cpu = smp_processor_id();
reg_timer_r_masked_intr masked_intr;
reg_timer_rw_ack_intr ack_intr = { 0 };
if (!masked_intr.tmr0)
return IRQ_NONE;
- /* acknowledge the timer irq */
+ /* Acknowledge the timer irq. */
ack_intr.tmr0 = 1;
REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
- /* reset watchdog otherwise it resets us! */
+ /* Reset watchdog otherwise it resets us! */
reset_watchdog();
/* Update statistics. */
if (cpu != 0)
return IRQ_HANDLED;
- /* call the real timer interrupt handler */
+ /* Call the real timer interrupt handler */
do_timer(1);
/*
if (set_rtc_mmss(xtime.tv_sec) == 0)
last_rtc_update = xtime.tv_sec;
else
- last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
+ /* Do it again in 60 s */
+ last_rtc_update = xtime.tv_sec - 600;
}
return IRQ_HANDLED;
}
-/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
- * it needs to be IRQF_DISABLED to make the jiffies update work properly
+/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain.
+ * It needs to be IRQF_DISABLED to make the jiffies update work properly.
*/
-
-static struct irqaction irq_timer = {
- .mask = timer_interrupt,
+static struct irqaction irq_timer = {
+ .handler = timer_interrupt,
.flags = IRQF_SHARED | IRQF_DISABLED,
.mask = CPU_MASK_NONE,
.name = "timer"
cris_timer_init(void)
{
int cpu = smp_processor_id();
- reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
- reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
+ reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
+ reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
reg_timer_rw_intr_mask timer_intr_mask;
- /* Setup the etrax timers
+ /* Setup the etrax timers.
* Base frequency is 100MHz, divider 1000000 -> 100 HZ
* We use timer0, so timer1 is free.
* The trig timer is used by the fasttimer API if enabled.
*/
- tmr0_ctrl.op = regk_timer_ld;
+ tmr0_ctrl.op = regk_timer_ld;
tmr0_ctrl.freq = regk_timer_f100;
- REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
- REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
- tmr0_ctrl.op = regk_timer_run;
- REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
-
- /* enable the timer irq */
- timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
- timer_intr_mask.tmr0 = 1;
- REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
+ REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
+ REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
+ tmr0_ctrl.op = regk_timer_run;
+ REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
+
+ /* Enable the timer irq. */
+ timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
+ timer_intr_mask.tmr0 = 1;
+ REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
}
void __init
{
reg_intr_vect_rw_mask intr_mask;
- /* probe for the RTC and read it if it exists
+ /* Probe for the RTC and read it if it exists.
* Before the RTC can be probed the loops_per_usec variable needs
* to be initialized to make usleep work. A better value for
* loops_per_usec is calculated by the kernel later once the
loops_per_usec = 50;
if(RTC_INIT() < 0) {
- /* no RTC, start at 1980 */
+ /* No RTC, start at 1980 */
xtime.tv_sec = 0;
xtime.tv_nsec = 0;
have_rtc = 0;
} else {
- /* get the current time */
+ /* Get the current time */
have_rtc = 1;
update_xtime_from_cmos();
}
/*
- * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
- * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
+ * Initialize wall_to_monotonic such that adding it to
+ * xtime will yield zero, the tv_nsec field must be normalized
+ * (i.e., 0 <= nsec < NSEC_PER_SEC).
*/
set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
- /* Start CPU local timer */
+ /* Start CPU local timer. */
cris_timer_init();
- /* enable the timer irq in global config */
- intr_mask = REG_RD(intr_vect, regi_irq, rw_mask);
- intr_mask.timer = 1;
- REG_WR(intr_vect, regi_irq, rw_mask, intr_mask);
-
- /* now actually register the timer irq handler that calls timer_interrupt() */
+ /* Enable the timer irq in global config. */
+ intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
+ intr_mask.timer0 = 1;
+ REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);
- setup_irq(TIMER_INTR_VECT, &irq_timer);
+ /* Now actually register the timer irq handler that calls
+ * timer_interrupt(). */
+ setup_irq(TIMER0_INTR_VECT, &irq_timer);
- /* enable watchdog if we should use one */
+ /* Enable watchdog if we should use one. */
#if defined(CONFIG_ETRAX_WATCHDOG)
- printk("Enabling watchdog...\n");
+ printk(KERN_INFO "Enabling watchdog...\n");
start_watchdog();
/* If we use the hardware watchdog, we want to trap it as an NMI
- and dump registers before it resets us. For this to happen, we
- must set the "m" NMI enable flag (which once set, is unset only
- when an NMI is taken).
-
- The same goes for the external NMI, but that doesn't have any
- driver or infrastructure support yet. */
- {
- unsigned long flags;
- local_save_flags(flags);
- flags |= (1<<30); /* NMI M flag is at bit 30 */
- local_irq_restore(flags);
- }
+ * and dump registers before it resets us. For this to happen, we
+ * must set the "m" NMI enable flag (which once set, is unset only
+ * when an NMI is taken). */
+ {
+ unsigned long flags;
+ local_save_flags(flags);
+ flags |= (1<<30); /* NMI M flag is at bit 30 */
+ local_irq_restore(flags);
+ }
+#endif
+
+#ifdef CONFIG_CPU_FREQ
+ cpufreq_register_notifier(&cris_time_freq_notifier_block,
+ CPUFREQ_TRANSITION_NOTIFIER);
#endif
}
+
+#ifdef CONFIG_CPU_FREQ
+static int
+cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
+ void *data)
+{
+ struct cpufreq_freqs *freqs = data;
+ if (val == CPUFREQ_POSTCHANGE) {
+ reg_timer_r_tmr0_data data;
+ reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
+ do {
+ data = REG_RD(timer, timer_regs[freqs->cpu],
+ r_tmr0_data);
+ } while (data > 20);
+ REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
+ }
+ return 0;
+}
+#endif
/*
- * Copyright (C) 2003, Axis Communications AB.
+ * Copyright (C) 2003-2006, Axis Communications AB.
*/
#include <linux/ptrace.h>
+#include <linux/module.h>
#include <asm/uaccess.h>
-
-#include <asm/arch/hwregs/supp_reg.h>
-
-extern void reset_watchdog(void);
-extern void stop_watchdog(void);
-
-extern int raw_printk(const char *fmt, ...);
+#include <hwregs/supp_reg.h>
+#include <hwregs/intr_vect_defs.h>
+#include <asm/irq.h>
void
show_registers(struct pt_regs *regs)
{
/*
* It's possible to use either the USP register or current->thread.usp.
- * USP might not correspond to the current proccess for all cases this
+ * USP might not correspond to the current process for all cases this
* function is called, and current->thread.usp isn't up to date for the
- * current proccess. Experience shows that using USP is the way to go.
+ * current process. Experience shows that using USP is the way to go.
*/
- unsigned long usp;
+ unsigned long usp = rdusp();
unsigned long d_mmu_cause;
unsigned long i_mmu_cause;
- usp = rdusp();
+ printk("CPU: %d\n", smp_processor_id());
- raw_printk("CPU: %d\n", smp_processor_id());
+ printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n",
+ regs->erp, regs->srp, regs->ccs, usp, regs->mof);
- raw_printk("ERP: %08lx SRP: %08lx CCS: %08lx USP: %08lx MOF: %08lx\n",
- regs->erp, regs->srp, regs->ccs, usp, regs->mof);
+ printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
+ regs->r0, regs->r1, regs->r2, regs->r3);
- raw_printk(" r0: %08lx r1: %08lx r2: %08lx r3: %08lx\n",
- regs->r0, regs->r1, regs->r2, regs->r3);
+ printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
+ regs->r4, regs->r5, regs->r6, regs->r7);
- raw_printk(" r4: %08lx r5: %08lx r6: %08lx r7: %08lx\n",
- regs->r4, regs->r5, regs->r6, regs->r7);
+ printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
+ regs->r8, regs->r9, regs->r10, regs->r11);
- raw_printk(" r8: %08lx r9: %08lx r10: %08lx r11: %08lx\n",
- regs->r8, regs->r9, regs->r10, regs->r11);
+ printk("r12: %08lx r13: %08lx oR10: %08lx acr: %08lx\n",
+ regs->r12, regs->r13, regs->orig_r10, regs->acr);
- raw_printk("r12: %08lx r13: %08lx oR10: %08lx acr: %08lx\n",
- regs->r12, regs->r13, regs->orig_r10, regs->acr);
-
- raw_printk("sp: %08lx\n", regs);
+ printk(" sp: %08lx\n", (unsigned long)regs);
SUPP_BANK_SEL(BANK_IM);
SUPP_REG_RD(RW_MM_CAUSE, i_mmu_cause);
SUPP_BANK_SEL(BANK_DM);
SUPP_REG_RD(RW_MM_CAUSE, d_mmu_cause);
- raw_printk(" Data MMU Cause: %08lx\n", d_mmu_cause);
- raw_printk("Instruction MMU Cause: %08lx\n", i_mmu_cause);
+ printk(" Data MMU Cause: %08lx\n", d_mmu_cause);
+ printk("Instruction MMU Cause: %08lx\n", i_mmu_cause);
- raw_printk("Process %s (pid: %d, stackpage: %08lx)\n",
- current->comm, current->pid, (unsigned long) current);
+ printk("Process %s (pid: %d, stackpage=%08lx)\n",
+ current->comm, current->pid, (unsigned long)current);
- /* Show additional info if in kernel-mode. */
+ /*
+ * When in-kernel, we also print out the stack and code at the
+ * time of the fault..
+ */
if (!user_mode(regs)) {
int i;
- unsigned char c;
- show_stack(NULL, (unsigned long *) usp);
+ show_stack(NULL, (unsigned long *)usp);
/*
* If the previous stack-dump wasn't a kernel one, dump the
if (usp != 0)
show_stack(NULL, NULL);
- raw_printk("\nCode: ");
+ printk("\nCode: ");
if (regs->erp < PAGE_OFFSET)
goto bad_value;
* instruction decoding should be in sync at the interesting
* point, but small enough to fit on a row. The regs->erp
* location is pointed out in a ksymoops-friendly way by
- * wrapping the byte for that address in parenthesis.
+ * wrapping the byte for that address in parenthesises.
*/
for (i = -12; i < 12; i++) {
- if (__get_user(c, &((unsigned char *) regs->erp)[i])) {
+ unsigned char c;
+
+ if (__get_user(c, &((unsigned char *)regs->erp)[i])) {
bad_value:
- raw_printk(" Bad IP value.");
+ printk(" Bad IP value.");
break;
}
if (i == 0)
- raw_printk("(%02x) ", c);
+ printk("(%02x) ", c);
else
- raw_printk("%02x ", c);
+ printk("%02x ", c);
}
-
- raw_printk("\n");
+ printk("\n");
}
}
-/*
- * This gets called from entry.S when the watchdog has bitten. Show something
- * similar to an Oops dump, and if the kernel is configured to be a nice doggy;
- * halt instead of reboot.
- */
void
-watchdog_bite_hook(struct pt_regs *regs)
+arch_enable_nmi(void)
{
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- local_irq_disable();
- stop_watchdog();
- show_registers(regs);
+ unsigned long flags;
- while (1)
- ; /* Do nothing. */
-#else
- show_registers(regs);
-#endif
+ local_save_flags(flags);
+ flags |= (1 << 30); /* NMI M flag is at bit 30 */
+ local_irq_restore(flags);
}
-/* This is normally the Oops function. */
-void
-die_if_kernel(const char *str, struct pt_regs *regs, long err)
+extern void (*nmi_handler)(struct pt_regs *);
+void handle_nmi(struct pt_regs *regs)
{
- if (user_mode(regs))
- return;
+#ifdef CONFIG_ETRAXFS
+ reg_intr_vect_r_nmi r;
+#endif
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- /*
- * This printout might take too long and could trigger
- * the watchdog normally. If NICE_DOGGY is set, simply
- * stop the watchdog during the printout.
- */
- stop_watchdog();
+ if (nmi_handler)
+ nmi_handler(regs);
+
+#ifdef CONFIG_ETRAXFS
+ /* Wait until nmi is no longer active. */
+ do {
+ r = REG_RD(intr_vect, regi_irq, r_nmi);
+ } while (r.ext == regk_intr_vect_on);
#endif
+}
- raw_printk("%s: %04lx\n", str, err & 0xffff);
- show_registers(regs);
+#ifdef CONFIG_BUG
+extern void die_if_kernel(const char *str, struct pt_regs *regs, long err);
-#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
- reset_watchdog();
-#endif
+/* Copy of the regs at BUG() time. */
+struct pt_regs BUG_regs;
- do_exit(SIGSEGV);
+void do_BUG(char *file, unsigned int line)
+{
+ printk("kernel BUG at %s:%d!\n", file, line);
+ die_if_kernel("Oops", &BUG_regs, 0);
}
+EXPORT_SYMBOL(do_BUG);
-void arch_enable_nmi(void)
+void fixup_BUG(struct pt_regs *regs)
{
- unsigned long flags;
- local_save_flags(flags);
- flags |= (1<<30); /* NMI M flag is at bit 30 */
- local_irq_restore(flags);
+ BUG_regs = *regs;
+
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+ /*
+ * Fixup the BUG arguments through exception handlers.
+ */
+ {
+ const struct exception_table_entry *fixup;
+
+ /*
+ * ERP points at the "break 14" + 2, compensate for the 2
+ * bytes.
+ */
+ fixup = search_exception_tables(instruction_pointer(regs) - 2);
+ if (fixup) {
+ /* Adjust the instruction pointer in the stackframe. */
+ instruction_pointer(regs) = fixup->fixup;
+ arch_fixup(regs);
+ }
+ }
+#else
+ /* Dont try to lookup the filename + line, just dump regs. */
+ do_BUG("unknown", 0);
+#endif
}
+
+/*
+ * Break 14 handler. Save regs and jump into the fixup_BUG.
+ */
+__asm__ ( ".text\n\t"
+ ".global breakh_BUG\n\t"
+ "breakh_BUG:\n\t"
+ SAVE_ALL
+ KGDB_FIXUP
+ "move.d $sp, $r10\n\t"
+ "jsr fixup_BUG\n\t"
+ "nop\n\t"
+ "jump ret_from_intr\n\t"
+ "nop\n\t");
+
+
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+void
+handle_BUG(struct pt_regs *regs)
+{
+}
+#endif
+#endif
+++ /dev/null
-// $Id: vcs_hook.c,v 1.2 2003/08/12 12:01:06 starvik Exp $
-//
-// Call simulator hook. This is the part running in the
-// simulated program.
-//
-
-#include "vcs_hook.h"
-#include <stdarg.h>
-#include <asm/arch-v32/hwregs/reg_map.h>
-#include <asm/arch-v32/hwregs/intr_vect_defs.h>
-
-#define HOOK_TRIG_ADDR 0xb7000000 /* hook cvlog model reg address */
-#define HOOK_MEM_BASE_ADDR 0xa0000000 /* csp4 (shared mem) base addr */
-
-#define HOOK_DATA(offset) ((unsigned*) HOOK_MEM_BASE_ADDR)[offset]
-#define VHOOK_DATA(offset) ((volatile unsigned*) HOOK_MEM_BASE_ADDR)[offset]
-#define HOOK_TRIG(funcid) do { *((unsigned *) HOOK_TRIG_ADDR) = funcid; } while(0)
-#define HOOK_DATA_BYTE(offset) ((unsigned char*) HOOK_MEM_BASE_ADDR)[offset]
-
-
-// ------------------------------------------------------------------ hook_call
-int hook_call( unsigned id, unsigned pcnt, ...) {
- va_list ap;
- unsigned i;
- unsigned ret;
-#ifdef USING_SOS
- PREEMPT_OFF_SAVE();
-#endif
-
- // pass parameters
- HOOK_DATA(0) = id;
-
- /* Have to make hook_print_str a special case since we call with a
- parameter of byte type. Should perhaps be a separate
- hook_call. */
-
- if (id == hook_print_str) {
- int i;
- char *str;
-
- HOOK_DATA(1) = pcnt;
-
- va_start(ap, pcnt);
- str = (char*)va_arg(ap,unsigned);
-
- for (i=0; i!=pcnt; i++) {
- HOOK_DATA_BYTE(8+i) = str[i];
- }
- HOOK_DATA_BYTE(8+i) = 0; /* null byte */
- }
- else {
- va_start(ap, pcnt);
- for( i = 1; i <= pcnt; i++ ) HOOK_DATA(i) = va_arg(ap,unsigned);
- va_end(ap);
- }
-
- // read from mem to make sure data has propagated to memory before trigging
- *((volatile unsigned*) HOOK_MEM_BASE_ADDR);
-
- // trigger hook
- HOOK_TRIG(id);
-
- // wait for call to finish
- while( VHOOK_DATA(0) > 0 ) {}
-
- // extract return value
-
- ret = VHOOK_DATA(1);
-
-#ifdef USING_SOS
- PREEMPT_RESTORE();
-#endif
- return ret;
-}
-
-unsigned
-hook_buf(unsigned i)
-{
- return (HOOK_DATA(i));
-}
-
-void print_str( const char *str ) {
- int i;
- for (i=1; str[i]; i++); /* find null at end of string */
- hook_call(hook_print_str, i, str);
-}
-
-// --------------------------------------------------------------- CPU_KICK_DOG
-void CPU_KICK_DOG(void) {
- (void) hook_call( hook_kick_dog, 0 );
-}
-
-// ------------------------------------------------------- CPU_WATCHDOG_TIMEOUT
-void CPU_WATCHDOG_TIMEOUT( unsigned t ) {
- (void) hook_call( hook_dog_timeout, 1, t );
-}
# Makefile for Etrax-specific library files..
#
-lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o csumcpfruser.o spinlock.o
+lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \
+ csumcpfruser.o spinlock.o delay.o
/*
* A fast checksum routine using movem
- * Copyright (c) 1998-2001, 2003 Axis Communications AB
+ * Copyright (c) 1998-2007 Axis Communications AB
*
* csum_partial(const unsigned char * buff, int len, unsigned int sum)
*/
;; r11 - length
;; r12 - checksum
- ;; check for breakeven length between movem and normal word looping versions
- ;; we also do _NOT_ want to compute a checksum over more than the
- ;; actual length when length < 40
-
- cmpu.w 80,$r11
- blo _word_loop
- nop
-
- ;; need to save the registers we use below in the movem loop
- ;; this overhead is why we have a check above for breakeven length
- ;; only r0 - r8 have to be saved, the other ones are clobber-able
- ;; according to the ABI
+ ;; Optimized for large packets
+ subq 10*4, $r11
+ blt _word_loop
+ move.d $r11, $acr
subq 9*4,$sp
- subq 10*4,$r11 ; update length for the first loop
+ clearf c
movem $r8,[$sp]
;; do a movem checksum
_mloop: movem [$r10+],$r9 ; read 10 longwords
-
+ ;; Loop count without touching the c flag.
+ addoq -10*4, $acr, $acr
;; perform dword checksumming on the 10 longwords
- add.d $r0,$r12
+ addc $r0,$r12
addc $r1,$r12
addc $r2,$r12
addc $r3,$r12
addc $r8,$r12
addc $r9,$r12
- ;; fold the carry into the checksum, to avoid having to loop the carry
- ;; back into the top
-
- addc 0,$r12
- addc 0,$r12 ; do it again, since we might have generated a carry
-
- subq 10*4,$r11
- bge _mloop
- nop
-
- addq 10*4,$r11 ; compensate for last loop underflowing length
+ ;; test $acr without trashing carry.
+ move.d $acr, $acr
+ bpl _mloop
+ ;; r11 <= acr is not really needed in the mloop, just using the dslot
+ ;; to prepare for what is needed after mloop.
+ move.d $acr, $r11
+ ;; fold the last carry into r13
+ addc 0, $r12
movem [$sp+],$r8 ; restore regs
_word_loop:
- ;; only fold if there is anything to fold.
-
- cmpq 0,$r12
- beq _no_fold
-
- ;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below.
- ;; r9 and r13 can be used as temporaries.
+ addq 10*4,$r11 ; compensate for last loop underflowing length
moveq -1,$r9 ; put 0xffff in r9, faster than move.d 0xffff,r9
lsrq 16,$r9
move.d $r12,$r13
lsrq 16,$r13 ; r13 = checksum >> 16
- and.d $r9,$r12 ; checksum = checksum & 0xffff
- add.d $r13,$r12 ; checksum += r13
- move.d $r12,$r13 ; do the same again, maybe we got a carry last add
- lsrq 16,$r13
- and.d $r9,$r12
- add.d $r13,$r12
+ and.d $r9,$r12 ; checksum = checksum & 0xffff
_no_fold:
- cmpq 2,$r11
+ subq 2,$r11
blt _no_words
- nop
+ add.d $r13,$r12 ; checksum += r13
;; checksum the rest of the words
-
- subq 2,$r11
-
_wloop: subq 2,$r11
bge _wloop
addu.w [$r10+],$r12
- addq 2,$r11
-
_no_words:
+ addq 2,$r11
;; see if we have one odd byte more
- cmpq 1,$r11
- beq _do_byte
+ bne _do_byte
nop
ret
move.d $r12,$r10
/*
* A fast checksum+copy routine using movem
- * Copyright (c) 1998, 2001, 2003 Axis Communications AB
+ * Copyright (c) 1998-2007 Axis Communications AB
*
* Authors: Bjorn Wesen
*
;; r12 - length
;; r13 - checksum
- ;; check for breakeven length between movem and normal word looping versions
- ;; we also do _NOT_ want to compute a checksum over more than the
- ;; actual length when length < 40
-
- cmpu.w 80,$r12
- blo _word_loop
- nop
-
- ;; need to save the registers we use below in the movem loop
- ;; this overhead is why we have a check above for breakeven length
- ;; only r0 - r8 have to be saved, the other ones are clobber-able
- ;; according to the ABI
+ ;; Optimized for large packets
+ subq 10*4, $r12
+ blt _word_loop
+ move.d $r12, $acr
subq 9*4,$sp
- subq 10*4,$r12 ; update length for the first loop
+ clearf c
movem $r8,[$sp]
;; do a movem copy and checksum
-
1: ;; A failing userspace access (the read) will have this as PC.
_mloop: movem [$r10+],$r9 ; read 10 longwords
+ addoq -10*4, $acr, $acr ; loop counter in latency cycle
movem $r9,[$r11+] ; write 10 longwords
;; perform dword checksumming on the 10 longwords
-
- add.d $r0,$r13
+ addc $r0,$r13
addc $r1,$r13
addc $r2,$r13
addc $r3,$r13
addc $r8,$r13
addc $r9,$r13
- ;; fold the carry into the checksum, to avoid having to loop the carry
- ;; back into the top
-
- addc 0,$r13
- addc 0,$r13 ; do it again, since we might have generated a carry
-
- subq 10*4,$r12
- bge _mloop
- nop
-
- addq 10*4,$r12 ; compensate for last loop underflowing length
+ ;; test $acr, without trashing carry.
+ move.d $acr, $acr
+ bpl _mloop
+ ;; r12 <= acr is needed after mloop and in the exception handlers.
+ move.d $acr, $r12
+ ;; fold the last carry into r13
+ addc 0, $r13
movem [$sp+],$r8 ; restore regs
_word_loop:
- ;; only fold if there is anything to fold.
-
- cmpq 0,$r13
- beq _no_fold
+ addq 10*4,$r12 ; compensate for last loop underflowing length
;; fold 32-bit checksum into a 16-bit checksum, to avoid carries below
;; r9 can be used as temporary.
-
move.d $r13,$r9
lsrq 16,$r9 ; r0 = checksum >> 16
and.d 0xffff,$r13 ; checksum = checksum & 0xffff
- add.d $r9,$r13 ; checksum += r0
- move.d $r13,$r9 ; do the same again, maybe we got a carry last add
- lsrq 16,$r9
- and.d 0xffff,$r13
- add.d $r9,$r13
-_no_fold:
- cmpq 2,$r12
+ subq 2, $r12
blt _no_words
- nop
+ add.d $r9,$r13 ; checksum += r0
;; copy and checksum the rest of the words
-
- subq 2,$r12
-
2: ;; A failing userspace access for the read below will have this as PC.
_wloop: move.w [$r10+],$r9
addu.w $r9,$r13
bge _wloop
move.w $r9,[$r11+]
- addq 2,$r12
-
_no_words:
- ;; see if we have one odd byte more
- cmpq 1,$r12
- beq _do_byte
+ addq 2,$r12
+ bne _do_byte
nop
ret
move.d $r13,$r10
--- /dev/null
+/*
+ * Precise Delay Loops for ETRAX FS
+ *
+ * Copyright (C) 2006 Axis Communications AB.
+ *
+ */
+
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/timer_defs.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+
+/*
+ * On ETRAX FS, we can check the free-running read-only 100MHz timer
+ * getting 32-bit 10ns precision, theoretically good for 42.94967295
+ * seconds. Unsigned arithmetic and careful expression handles
+ * wrapping.
+ */
+
+void cris_delay10ns(u32 n10ns)
+{
+ u32 t0 = REG_RD(timer, regi_timer0, r_time);
+ while (REG_RD(timer, regi_timer0, r_time) - t0 < n10ns)
+ ;
+}
+EXPORT_SYMBOL(cris_delay10ns);
cris_spin_lock:
clearf p
-1: test.d [$r10]
+1: test.b [$r10]
beq 1b
clearf p
ax
- clear.d [$r10]
+ clear.b [$r10]
bcs 1b
clearf p
ret
cris_spin_trylock:
clearf p
-1: move.d [$r10], $r11
+1: move.b [$r10], $r11
ax
- clear.d [$r10]
+ clear.b [$r10]
bcs 1b
clearf p
ret
- move.d $r11,$r10
+ movu.b $r11,$r10
--- /dev/null
+if CRIS_MACH_ARTPEC3
+
+menu "Artpec-3 options"
+ depends on CRIS_MACH_ARTPEC3
+
+config ETRAX_DRAM_VIRTUAL_BASE
+ hex
+ default "c0000000"
+
+config ETRAX_L2CACHE
+ bool
+ default y
+
+config ETRAX_SERIAL_PORTS
+ int
+ default 5
+
+config ETRAX_DDR
+ bool
+ default y
+
+config ETRAX_DDR2_MRS
+ hex "DDR2 MRS"
+ default "0"
+
+config ETRAX_DDR2_TIMING
+ hex "DDR2 SDRAM timing"
+ default "0"
+ help
+ SDRAM timing parameters.
+
+config ETRAX_DDR2_CONFIG
+ hex "DDR2 config"
+ default "0"
+
+config ETRAX_PIO_CE0_CFG
+ hex "PIO CE0 configuration"
+ default "0"
+
+config ETRAX_PIO_CE1_CFG
+ hex "PIO CE1 configuration"
+ default "0"
+
+config ETRAX_PIO_CE2_CFG
+ hex "PIO CE2 configuration"
+ default "0"
+
+config ETRAX_DEF_GIO_PA_OE
+ hex "GIO_PA_OE"
+ default "00000000"
+ help
+ Configures the direction of general port A bits. 1 is out, 0 is in.
+ This is often totally different depending on the product used.
+ There are some guidelines though - if you know that only LED's are
+ connected to port PA, then they are usually connected to bits 2-4
+ and you can therefore use 1c. On other boards which don't have the
+ LED's at the general ports, these bits are used for all kinds of
+ stuff. If you don't know what to use, it is always safe to put all
+ as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PA_OUT
+ hex "GIO_PA_OUT"
+ default "00000000"
+ help
+ Configures the initial data for the general port A bits. Most
+ products should use 00 here.
+
+config ETRAX_DEF_GIO_PB_OE
+ hex "GIO_PB_OE"
+ default "000000000"
+ help
+ Configures the direction of general port B bits. 1 is out, 0 is in.
+ This is often totally different depending on the product used.
+ There are some guidelines though - if you know that only LED's are
+ connected to port PA, then they are usually connected to bits 2-4
+ and you can therefore use 1c. On other boards which don't have the
+ LED's at the general ports, these bits are used for all kinds of
+ stuff. If you don't know what to use, it is always safe to put all
+ as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PB_OUT
+ hex "GIO_PB_OUT"
+ default "000000000"
+ help
+ Configures the initial data for the general port B bits. Most
+ products should use 00000 here.
+
+config ETRAX_DEF_GIO_PC_OE
+ hex "GIO_PC_OE"
+ default "00000"
+ help
+ Configures the direction of general port C bits. 1 is out, 0 is in.
+ This is often totally different depending on the product used.
+ There are some guidelines though - if you know that only LED's are
+ connected to port PA, then they are usually connected to bits 2-4
+ and you can therefore use 1c. On other boards which don't have the
+ LED's at the general ports, these bits are used for all kinds of
+ stuff. If you don't know what to use, it is always safe to put all
+ as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PC_OUT
+ hex "GIO_PC_OUT"
+ default "00000"
+ help
+ Configures the initial data for the general port C bits. Most
+ products should use 00000 here.
+
+endmenu
+
+endif
--- /dev/null
+# $Id: Makefile,v 1.3 2007/03/13 11:57:46 starvik Exp $
+#
+# Makefile for the linux kernel.
+#
+
+obj-y := dma.o pinmux.o io.o arbiter.o
+obj-$(CONFIG_ETRAX_VCS_SIM) += vcs_hook.o
+obj-$(CONFIG_CPU_FREQ) += cpufreq.o
+
+clean:
+
--- /dev/null
+/*
+ * Memory arbiter functions. Allocates bandwidth through the
+ * arbiter and sets up arbiter breakpoints.
+ *
+ * The algorithm first assigns slots to the clients that has specified
+ * bandwidth (e.g. ethernet) and then the remaining slots are divided
+ * on all the active clients.
+ *
+ * Copyright (c) 2004-2007 Axis Communications AB.
+ *
+ * The artpec-3 has two arbiters. The memory hierarchy looks like this:
+ *
+ *
+ * CPU DMAs
+ * | |
+ * | |
+ * -------------- ------------------
+ * | foo arbiter|----| Internal memory|
+ * -------------- ------------------
+ * |
+ * --------------
+ * | L2 cache |
+ * --------------
+ * |
+ * h264 etc |
+ * | |
+ * | |
+ * --------------
+ * | bar arbiter|
+ * --------------
+ * |
+ * ---------
+ * | SDRAM |
+ * ---------
+ *
+ */
+
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/marb_foo_defs.h>
+#include <hwregs/marb_bar_defs.h>
+#include <arbiter.h>
+#include <hwregs/intr_vect.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/signal.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+#include <asm/irq_regs.h>
+
+#define D(x)
+
+struct crisv32_watch_entry {
+ unsigned long instance;
+ watch_callback *cb;
+ unsigned long start;
+ unsigned long end;
+ int used;
+};
+
+#define NUMBER_OF_BP 4
+#define SDRAM_BANDWIDTH 400000000
+#define INTMEM_BANDWIDTH 400000000
+#define NBR_OF_SLOTS 64
+#define NBR_OF_REGIONS 2
+#define NBR_OF_CLIENTS 15
+#define ARBITERS 2
+#define UNASSIGNED 100
+
+struct arbiter {
+ unsigned long instance;
+ int nbr_regions;
+ int nbr_clients;
+ int requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS];
+ int active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS];
+};
+
+static struct crisv32_watch_entry watches[ARBITERS][NUMBER_OF_BP] =
+{
+ {
+ {regi_marb_foo_bp0},
+ {regi_marb_foo_bp1},
+ {regi_marb_foo_bp2},
+ {regi_marb_foo_bp3}
+ },
+ {
+ {regi_marb_bar_bp0},
+ {regi_marb_bar_bp1},
+ {regi_marb_bar_bp2},
+ {regi_marb_bar_bp3}
+ }
+};
+
+struct arbiter arbiters[ARBITERS] =
+{
+ { /* L2 cache arbiter */
+ .instance = regi_marb_foo,
+ .nbr_regions = 2,
+ .nbr_clients = 15
+ },
+ { /* DDR2 arbiter */
+ .instance = regi_marb_bar,
+ .nbr_regions = 1,
+ .nbr_clients = 9
+ }
+};
+
+static int max_bandwidth[NBR_OF_REGIONS] = {SDRAM_BANDWIDTH, INTMEM_BANDWIDTH};
+
+DEFINE_SPINLOCK(arbiter_lock);
+
+static irqreturn_t
+crisv32_foo_arbiter_irq(int irq, void *dev_id);
+static irqreturn_t
+crisv32_bar_arbiter_irq(int irq, void *dev_id);
+
+/*
+ * "I'm the arbiter, I know the score.
+ * From square one I'll be watching all 64."
+ * (memory arbiter slots, that is)
+ *
+ * Or in other words:
+ * Program the memory arbiter slots for "region" according to what's
+ * in requested_slots[] and active_clients[], while minimizing
+ * latency. A caller may pass a non-zero positive amount for
+ * "unused_slots", which must then be the unallocated, remaining
+ * number of slots, free to hand out to any client.
+ */
+
+static void crisv32_arbiter_config(int arbiter, int region, int unused_slots)
+{
+ int slot;
+ int client;
+ int interval = 0;
+
+ /*
+ * This vector corresponds to the hardware arbiter slots (see
+ * the hardware documentation for semantics). We initialize
+ * each slot with a suitable sentinel value outside the valid
+ * range {0 .. NBR_OF_CLIENTS - 1} and replace them with
+ * client indexes. Then it's fed to the hardware.
+ */
+ s8 val[NBR_OF_SLOTS];
+
+ for (slot = 0; slot < NBR_OF_SLOTS; slot++)
+ val[slot] = -1;
+
+ for (client = 0; client < arbiters[arbiter].nbr_clients; client++) {
+ int pos;
+ /* Allocate the requested non-zero number of slots, but
+ * also give clients with zero-requests one slot each
+ * while stocks last. We do the latter here, in client
+ * order. This makes sure zero-request clients are the
+ * first to get to any spare slots, else those slots
+ * could, when bandwidth is allocated close to the limit,
+ * all be allocated to low-index non-zero-request clients
+ * in the default-fill loop below. Another positive but
+ * secondary effect is a somewhat better spread of the
+ * zero-bandwidth clients in the vector, avoiding some of
+ * the latency that could otherwise be caused by the
+ * partitioning of non-zero-bandwidth clients at low
+ * indexes and zero-bandwidth clients at high
+ * indexes. (Note that this spreading can only affect the
+ * unallocated bandwidth.) All the above only matters for
+ * memory-intensive situations, of course.
+ */
+ if (!arbiters[arbiter].requested_slots[region][client]) {
+ /*
+ * Skip inactive clients. Also skip zero-slot
+ * allocations in this pass when there are no known
+ * free slots.
+ */
+ if (!arbiters[arbiter].active_clients[region][client] ||
+ unused_slots <= 0)
+ continue;
+
+ unused_slots--;
+
+ /* Only allocate one slot for this client. */
+ interval = NBR_OF_SLOTS;
+ } else
+ interval = NBR_OF_SLOTS /
+ arbiters[arbiter].requested_slots[region][client];
+
+ pos = 0;
+ while (pos < NBR_OF_SLOTS) {
+ if (val[pos] >= 0)
+ pos++;
+ else {
+ val[pos] = client;
+ pos += interval;
+ }
+ }
+ }
+
+ client = 0;
+ for (slot = 0; slot < NBR_OF_SLOTS; slot++) {
+ /*
+ * Allocate remaining slots in round-robin
+ * client-number order for active clients. For this
+ * pass, we ignore requested bandwidth and previous
+ * allocations.
+ */
+ if (val[slot] < 0) {
+ int first = client;
+ while (!arbiters[arbiter].active_clients[region][client]) {
+ client = (client + 1) %
+ arbiters[arbiter].nbr_clients;
+ if (client == first)
+ break;
+ }
+ val[slot] = client;
+ client = (client + 1) % arbiters[arbiter].nbr_clients;
+ }
+ if (arbiter == 0) {
+ if (region == EXT_REGION)
+ REG_WR_INT_VECT(marb_foo, regi_marb_foo,
+ rw_l2_slots, slot, val[slot]);
+ else if (region == INT_REGION)
+ REG_WR_INT_VECT(marb_foo, regi_marb_foo,
+ rw_intm_slots, slot, val[slot]);
+ } else {
+ REG_WR_INT_VECT(marb_bar, regi_marb_bar,
+ rw_ddr2_slots, slot, val[slot]);
+ }
+ }
+}
+
+extern char _stext, _etext;
+
+static void crisv32_arbiter_init(void)
+{
+ static int initialized;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ /*
+ * CPU caches are always set to active, but with zero
+ * bandwidth allocated. It should be ok to allocate zero
+ * bandwidth for the caches, because DMA for other channels
+ * will supposedly finish, once their programmed amount is
+ * done, and then the caches will get access according to the
+ * "fixed scheme" for unclaimed slots. Though, if for some
+ * use-case somewhere, there's a maximum CPU latency for
+ * e.g. some interrupt, we have to start allocating specific
+ * bandwidth for the CPU caches too.
+ */
+ arbiters[0].active_clients[EXT_REGION][11] = 1;
+ arbiters[0].active_clients[EXT_REGION][12] = 1;
+ crisv32_arbiter_config(0, EXT_REGION, 0);
+ crisv32_arbiter_config(0, INT_REGION, 0);
+ crisv32_arbiter_config(1, EXT_REGION, 0);
+
+ if (request_irq(MEMARB_FOO_INTR_VECT, crisv32_foo_arbiter_irq,
+ IRQF_DISABLED, "arbiter", NULL))
+ printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
+
+ if (request_irq(MEMARB_BAR_INTR_VECT, crisv32_bar_arbiter_irq,
+ IRQF_DISABLED, "arbiter", NULL))
+ printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
+
+#ifndef CONFIG_ETRAX_KGDB
+ /* Global watch for writes to kernel text segment. */
+ crisv32_arbiter_watch(virt_to_phys(&_stext), &_etext - &_stext,
+ MARB_CLIENTS(arbiter_all_clients, arbiter_bar_all_clients),
+ arbiter_all_write, NULL);
+#endif
+
+ /* Set up max burst sizes by default */
+ REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_rd_burst, 3);
+ REG_WR_INT(marb_bar, regi_marb_bar, rw_h264_wr_burst, 3);
+ REG_WR_INT(marb_bar, regi_marb_bar, rw_ccd_burst, 3);
+ REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_wr_burst, 3);
+ REG_WR_INT(marb_bar, regi_marb_bar, rw_vin_rd_burst, 3);
+ REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_rd_burst, 3);
+ REG_WR_INT(marb_bar, regi_marb_bar, rw_vout_burst, 3);
+ REG_WR_INT(marb_bar, regi_marb_bar, rw_sclr_fifo_burst, 3);
+ REG_WR_INT(marb_bar, regi_marb_bar, rw_l2cache_burst, 3);
+}
+
+int crisv32_arbiter_allocate_bandwidth(int client, int region,
+ unsigned long bandwidth)
+{
+ int i;
+ int total_assigned = 0;
+ int total_clients = 0;
+ int req;
+ int arbiter = 0;
+
+ crisv32_arbiter_init();
+
+ if (client & 0xffff0000) {
+ arbiter = 1;
+ client >>= 16;
+ }
+
+ for (i = 0; i < arbiters[arbiter].nbr_clients; i++) {
+ total_assigned += arbiters[arbiter].requested_slots[region][i];
+ total_clients += arbiters[arbiter].active_clients[region][i];
+ }
+
+ /* Avoid division by 0 for 0-bandwidth requests. */
+ req = bandwidth == 0
+ ? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth);
+
+ /*
+ * We make sure that there are enough slots only for non-zero
+ * requests. Requesting 0 bandwidth *may* allocate slots,
+ * though if all bandwidth is allocated, such a client won't
+ * get any and will have to rely on getting memory access
+ * according to the fixed scheme that's the default when one
+ * of the slot-allocated clients doesn't claim their slot.
+ */
+ if (total_assigned + req > NBR_OF_SLOTS)
+ return -ENOMEM;
+
+ arbiters[arbiter].active_clients[region][client] = 1;
+ arbiters[arbiter].requested_slots[region][client] = req;
+ crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned);
+
+ /* Propagate allocation from foo to bar */
+ if (arbiter == 0)
+ crisv32_arbiter_allocate_bandwidth(8 << 16,
+ EXT_REGION, bandwidth);
+ return 0;
+}
+
+/*
+ * Main entry for bandwidth deallocation.
+ *
+ * Strictly speaking, for a somewhat constant set of clients where
+ * each client gets a constant bandwidth and is just enabled or
+ * disabled (somewhat dynamically), no action is necessary here to
+ * avoid starvation for non-zero-allocation clients, as the allocated
+ * slots will just be unused. However, handing out those unused slots
+ * to active clients avoids needless latency if the "fixed scheme"
+ * would give unclaimed slots to an eager low-index client.
+ */
+
+void crisv32_arbiter_deallocate_bandwidth(int client, int region)
+{
+ int i;
+ int total_assigned = 0;
+ int arbiter = 0;
+
+ if (client & 0xffff0000)
+ arbiter = 1;
+
+ arbiters[arbiter].requested_slots[region][client] = 0;
+ arbiters[arbiter].active_clients[region][client] = 0;
+
+ for (i = 0; i < arbiters[arbiter].nbr_clients; i++)
+ total_assigned += arbiters[arbiter].requested_slots[region][i];
+
+ crisv32_arbiter_config(arbiter, region, NBR_OF_SLOTS - total_assigned);
+}
+
+int crisv32_arbiter_watch(unsigned long start, unsigned long size,
+ unsigned long clients, unsigned long accesses,
+ watch_callback *cb)
+{
+ int i;
+ int arbiter;
+ int used[2];
+ int ret = 0;
+
+ crisv32_arbiter_init();
+
+ if (start > 0x80000000) {
+ printk(KERN_ERR "Arbiter: %lX doesn't look like a "
+ "physical address", start);
+ return -EFAULT;
+ }
+
+ spin_lock(&arbiter_lock);
+
+ if (clients & 0xffff)
+ used[0] = 1;
+ if (clients & 0xffff0000)
+ used[1] = 1;
+
+ for (arbiter = 0; arbiter < ARBITERS; arbiter++) {
+ if (!used[arbiter])
+ continue;
+
+ for (i = 0; i < NUMBER_OF_BP; i++) {
+ if (!watches[arbiter][i].used) {
+ unsigned intr_mask;
+ if (arbiter)
+ intr_mask = REG_RD_INT(marb_bar,
+ regi_marb_bar, rw_intr_mask);
+ else
+ intr_mask = REG_RD_INT(marb_foo,
+ regi_marb_foo, rw_intr_mask);
+
+ watches[arbiter][i].used = 1;
+ watches[arbiter][i].start = start;
+ watches[arbiter][i].end = start + size;
+ watches[arbiter][i].cb = cb;
+
+ ret |= (i + 1) << (arbiter + 8);
+ if (arbiter) {
+ REG_WR_INT(marb_bar_bp,
+ watches[arbiter][i].instance,
+ rw_first_addr,
+ watches[arbiter][i].start);
+ REG_WR_INT(marb_bar_bp,
+ watches[arbiter][i].instance,
+ rw_last_addr,
+ watches[arbiter][i].end);
+ REG_WR_INT(marb_bar_bp,
+ watches[arbiter][i].instance,
+ rw_op, accesses);
+ REG_WR_INT(marb_bar_bp,
+ watches[arbiter][i].instance,
+ rw_clients,
+ clients & 0xffff);
+ } else {
+ REG_WR_INT(marb_foo_bp,
+ watches[arbiter][i].instance,
+ rw_first_addr,
+ watches[arbiter][i].start);
+ REG_WR_INT(marb_foo_bp,
+ watches[arbiter][i].instance,
+ rw_last_addr,
+ watches[arbiter][i].end);
+ REG_WR_INT(marb_foo_bp,
+ watches[arbiter][i].instance,
+ rw_op, accesses);
+ REG_WR_INT(marb_foo_bp,
+ watches[arbiter][i].instance,
+ rw_clients, clients >> 16);
+ }
+
+ if (i == 0)
+ intr_mask |= 1;
+ else if (i == 1)
+ intr_mask |= 2;
+ else if (i == 2)
+ intr_mask |= 4;
+ else if (i == 3)
+ intr_mask |= 8;
+
+ if (arbiter)
+ REG_WR_INT(marb_bar, regi_marb_bar,
+ rw_intr_mask, intr_mask);
+ else
+ REG_WR_INT(marb_foo, regi_marb_foo,
+ rw_intr_mask, intr_mask);
+
+ spin_unlock(&arbiter_lock);
+
+ break;
+ }
+ }
+ }
+ spin_unlock(&arbiter_lock);
+ if (ret)
+ return ret;
+ else
+ return -ENOMEM;
+}
+
+int crisv32_arbiter_unwatch(int id)
+{
+ int arbiter;
+ int intr_mask;
+
+ crisv32_arbiter_init();
+
+ spin_lock(&arbiter_lock);
+
+ for (arbiter = 0; arbiter < ARBITERS; arbiter++) {
+ int id2;
+
+ if (arbiter)
+ intr_mask = REG_RD_INT(marb_bar, regi_marb_bar,
+ rw_intr_mask);
+ else
+ intr_mask = REG_RD_INT(marb_foo, regi_marb_foo,
+ rw_intr_mask);
+
+ id2 = (id & (0xff << (arbiter + 8))) >> (arbiter + 8);
+ if (id2 == 0)
+ continue;
+ id2--;
+ if ((id2 >= NUMBER_OF_BP) || (!watches[arbiter][id2].used)) {
+ spin_unlock(&arbiter_lock);
+ return -EINVAL;
+ }
+
+ memset(&watches[arbiter][id2], 0,
+ sizeof(struct crisv32_watch_entry));
+
+ if (id2 == 0)
+ intr_mask &= ~1;
+ else if (id2 == 1)
+ intr_mask &= ~2;
+ else if (id2 == 2)
+ intr_mask &= ~4;
+ else if (id2 == 3)
+ intr_mask &= ~8;
+
+ if (arbiter)
+ REG_WR_INT(marb_bar, regi_marb_bar, rw_intr_mask,
+ intr_mask);
+ else
+ REG_WR_INT(marb_foo, regi_marb_foo, rw_intr_mask,
+ intr_mask);
+ }
+
+ spin_unlock(&arbiter_lock);
+ return 0;
+}
+
+extern void show_registers(struct pt_regs *regs);
+
+
+static irqreturn_t
+crisv32_foo_arbiter_irq(int irq, void *dev_id)
+{
+ reg_marb_foo_r_masked_intr masked_intr =
+ REG_RD(marb_foo, regi_marb_foo, r_masked_intr);
+ reg_marb_foo_bp_r_brk_clients r_clients;
+ reg_marb_foo_bp_r_brk_addr r_addr;
+ reg_marb_foo_bp_r_brk_op r_op;
+ reg_marb_foo_bp_r_brk_first_client r_first;
+ reg_marb_foo_bp_r_brk_size r_size;
+ reg_marb_foo_bp_rw_ack ack = {0};
+ reg_marb_foo_rw_ack_intr ack_intr = {
+ .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
+ };
+ struct crisv32_watch_entry *watch;
+ unsigned arbiter = (unsigned)dev_id;
+
+ masked_intr = REG_RD(marb_foo, regi_marb_foo, r_masked_intr);
+
+ if (masked_intr.bp0)
+ watch = &watches[arbiter][0];
+ else if (masked_intr.bp1)
+ watch = &watches[arbiter][1];
+ else if (masked_intr.bp2)
+ watch = &watches[arbiter][2];
+ else if (masked_intr.bp3)
+ watch = &watches[arbiter][3];
+ else
+ return IRQ_NONE;
+
+ /* Retrieve all useful information and print it. */
+ r_clients = REG_RD(marb_foo_bp, watch->instance, r_brk_clients);
+ r_addr = REG_RD(marb_foo_bp, watch->instance, r_brk_addr);
+ r_op = REG_RD(marb_foo_bp, watch->instance, r_brk_op);
+ r_first = REG_RD(marb_foo_bp, watch->instance, r_brk_first_client);
+ r_size = REG_RD(marb_foo_bp, watch->instance, r_brk_size);
+
+ printk(KERN_DEBUG "Arbiter IRQ\n");
+ printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n",
+ REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_clients, r_clients),
+ REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_addr, r_addr),
+ REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_op, r_op),
+ REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_first_client, r_first),
+ REG_TYPE_CONV(int, reg_marb_foo_bp_r_brk_size, r_size));
+
+ REG_WR(marb_foo_bp, watch->instance, rw_ack, ack);
+ REG_WR(marb_foo, regi_marb_foo, rw_ack_intr, ack_intr);
+
+ printk(KERN_DEBUG "IRQ occured at %X\n", (unsigned)get_irq_regs());
+
+ if (watch->cb)
+ watch->cb();
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t
+crisv32_bar_arbiter_irq(int irq, void *dev_id)
+{
+ reg_marb_bar_r_masked_intr masked_intr =
+ REG_RD(marb_bar, regi_marb_bar, r_masked_intr);
+ reg_marb_bar_bp_r_brk_clients r_clients;
+ reg_marb_bar_bp_r_brk_addr r_addr;
+ reg_marb_bar_bp_r_brk_op r_op;
+ reg_marb_bar_bp_r_brk_first_client r_first;
+ reg_marb_bar_bp_r_brk_size r_size;
+ reg_marb_bar_bp_rw_ack ack = {0};
+ reg_marb_bar_rw_ack_intr ack_intr = {
+ .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
+ };
+ struct crisv32_watch_entry *watch;
+ unsigned arbiter = (unsigned)dev_id;
+
+ masked_intr = REG_RD(marb_bar, regi_marb_bar, r_masked_intr);
+
+ if (masked_intr.bp0)
+ watch = &watches[arbiter][0];
+ else if (masked_intr.bp1)
+ watch = &watches[arbiter][1];
+ else if (masked_intr.bp2)
+ watch = &watches[arbiter][2];
+ else if (masked_intr.bp3)
+ watch = &watches[arbiter][3];
+ else
+ return IRQ_NONE;
+
+ /* Retrieve all useful information and print it. */
+ r_clients = REG_RD(marb_bar_bp, watch->instance, r_brk_clients);
+ r_addr = REG_RD(marb_bar_bp, watch->instance, r_brk_addr);
+ r_op = REG_RD(marb_bar_bp, watch->instance, r_brk_op);
+ r_first = REG_RD(marb_bar_bp, watch->instance, r_brk_first_client);
+ r_size = REG_RD(marb_bar_bp, watch->instance, r_brk_size);
+
+ printk(KERN_DEBUG "Arbiter IRQ\n");
+ printk(KERN_DEBUG "Clients %X addr %X op %X first %X size %X\n",
+ REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_clients, r_clients),
+ REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_addr, r_addr),
+ REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_op, r_op),
+ REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_first_client, r_first),
+ REG_TYPE_CONV(int, reg_marb_bar_bp_r_brk_size, r_size));
+
+ REG_WR(marb_bar_bp, watch->instance, rw_ack, ack);
+ REG_WR(marb_bar, regi_marb_bar, rw_ack_intr, ack_intr);
+
+ printk(KERN_DEBUG "IRQ occured at %X\n", (unsigned)get_irq_regs()->erp);
+
+ if (watch->cb)
+ watch->cb();
+
+ return IRQ_HANDLED;
+}
+
--- /dev/null
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cpufreq.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/clkgen_defs.h>
+#include <hwregs/ddr2_defs.h>
+
+static int
+cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
+ void *data);
+
+static struct notifier_block cris_sdram_freq_notifier_block = {
+ .notifier_call = cris_sdram_freq_notifier
+};
+
+static struct cpufreq_frequency_table cris_freq_table[] = {
+ {0x01, 6000},
+ {0x02, 200000},
+ {0, CPUFREQ_TABLE_END},
+};
+
+static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
+{
+ reg_clkgen_rw_clk_ctrl clk_ctrl;
+ clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
+ return clk_ctrl.pll ? 200000 : 6000;
+}
+
+static void cris_freq_set_cpu_state(unsigned int state)
+{
+ int i = 0;
+ struct cpufreq_freqs freqs;
+ reg_clkgen_rw_clk_ctrl clk_ctrl;
+ clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
+
+#ifdef CONFIG_SMP
+ for_each_present_cpu(i)
+#endif
+ {
+ freqs.old = cris_freq_get_cpu_frequency(i);
+ freqs.new = cris_freq_table[state].frequency;
+ freqs.cpu = i;
+ }
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+ local_irq_disable();
+
+ /* Even though we may be SMP they will share the same clock
+ * so all settings are made on CPU0. */
+ if (cris_freq_table[state].frequency == 200000)
+ clk_ctrl.pll = 1;
+ else
+ clk_ctrl.pll = 0;
+ REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
+
+ local_irq_enable();
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+};
+
+static int cris_freq_verify(struct cpufreq_policy *policy)
+{
+ return cpufreq_frequency_table_verify(policy, &cris_freq_table[0]);
+}
+
+static int cris_freq_target(struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation)
+{
+ unsigned int newstate = 0;
+
+ if (cpufreq_frequency_table_target(policy, cris_freq_table,
+ target_freq, relation, &newstate))
+ return -EINVAL;
+
+ cris_freq_set_cpu_state(newstate);
+
+ return 0;
+}
+
+static int cris_freq_cpu_init(struct cpufreq_policy *policy)
+{
+ int result;
+
+ /* cpuinfo and default policy values */
+ policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+ policy->cpuinfo.transition_latency = 1000000; /* 1ms */
+ policy->cur = cris_freq_get_cpu_frequency(0);
+
+ result = cpufreq_frequency_table_cpuinfo(policy, cris_freq_table);
+ if (result)
+ return (result);
+
+ cpufreq_frequency_table_get_attr(cris_freq_table, policy->cpu);
+
+ return 0;
+}
+
+
+static int cris_freq_cpu_exit(struct cpufreq_policy *policy)
+{
+ cpufreq_frequency_table_put_attr(policy->cpu);
+ return 0;
+}
+
+
+static struct freq_attr *cris_freq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
+static struct cpufreq_driver cris_freq_driver = {
+ .get = cris_freq_get_cpu_frequency,
+ .verify = cris_freq_verify,
+ .target = cris_freq_target,
+ .init = cris_freq_cpu_init,
+ .exit = cris_freq_cpu_exit,
+ .name = "cris_freq",
+ .owner = THIS_MODULE,
+ .attr = cris_freq_attr,
+};
+
+static int __init cris_freq_init(void)
+{
+ int ret;
+ ret = cpufreq_register_driver(&cris_freq_driver);
+ cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
+ CPUFREQ_TRANSITION_NOTIFIER);
+ return ret;
+}
+
+static int
+cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
+ void *data)
+{
+ int i;
+ struct cpufreq_freqs *freqs = data;
+ if (val == CPUFREQ_PRECHANGE) {
+ reg_ddr2_rw_cfg cfg =
+ REG_RD(ddr2, regi_ddr2_ctrl, rw_cfg);
+ cfg.ref_interval = (freqs->new == 200000 ? 1560 : 46);
+
+ if (freqs->new == 200000)
+ for (i = 0; i < 50000; i++);
+ REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
+ }
+ return 0;
+}
+
+
+module_init(cris_freq_init);
--- /dev/null
+/* Wrapper for DMA channel allocator that starts clocks etc */
+
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <asm/arch/mach/dma.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/marb_defs.h>
+#include <hwregs/clkgen_defs.h>
+#include <hwregs/strmux_defs.h>
+#include <linux/errno.h>
+#include <asm/system.h>
+#include <arbiter.h>
+
+static char used_dma_channels[MAX_DMA_CHANNELS];
+static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
+
+static DEFINE_SPINLOCK(dma_lock);
+
+int crisv32_request_dma(unsigned int dmanr, const char *device_id,
+ unsigned options, unsigned int bandwidth, enum dma_owner owner)
+{
+ unsigned long flags;
+ reg_clkgen_rw_clk_ctrl clk_ctrl;
+ reg_strmux_rw_cfg strmux_cfg;
+
+ if (crisv32_arbiter_allocate_bandwidth(dmanr,
+ options & DMA_INT_MEM ? INT_REGION : EXT_REGION,
+ bandwidth))
+ return -ENOMEM;
+
+ spin_lock_irqsave(&dma_lock, flags);
+
+ if (used_dma_channels[dmanr]) {
+ spin_unlock_irqrestore(&dma_lock, flags);
+ if (options & DMA_VERBOSE_ON_ERROR)
+ printk(KERN_ERR "Failed to request DMA %i for %s, "
+ "already allocated by %s\n",
+ dmanr,
+ device_id,
+ used_dma_channels_users[dmanr]);
+
+ if (options & DMA_PANIC_ON_ERROR)
+ panic("request_dma error!");
+ spin_unlock_irqrestore(&dma_lock, flags);
+ return -EBUSY;
+ }
+ clk_ctrl = REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
+ strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
+
+ switch (dmanr) {
+ case 0:
+ case 1:
+ clk_ctrl.dma0_1_eth = 1;
+ break;
+ case 2:
+ case 3:
+ clk_ctrl.dma2_3_strcop = 1;
+ break;
+ case 4:
+ case 5:
+ clk_ctrl.dma4_5_iop = 1;
+ break;
+ case 6:
+ case 7:
+ clk_ctrl.sser_ser_dma6_7 = 1;
+ break;
+ case 9:
+ case 11:
+ clk_ctrl.dma9_11 = 1;
+ break;
+#if MAX_DMA_CHANNELS-1 != 11
+#error Check dma.c
+#endif
+ default:
+ spin_unlock_irqrestore(&dma_lock, flags);
+ if (options & DMA_VERBOSE_ON_ERROR)
+ printk(KERN_ERR "Failed to request DMA %i for %s, "
+ "only 0-%i valid)\n",
+ dmanr, device_id, MAX_DMA_CHANNELS-1);
+
+ if (options & DMA_PANIC_ON_ERROR)
+ panic("request_dma error!");
+ return -EINVAL;
+ }
+
+ switch (owner) {
+ case dma_eth:
+ if (dmanr == 0)
+ strmux_cfg.dma0 = regk_strmux_eth;
+ else if (dmanr == 1)
+ strmux_cfg.dma1 = regk_strmux_eth;
+ else
+ panic("Invalid DMA channel for eth\n");
+ break;
+ case dma_ser0:
+ if (dmanr == 0)
+ strmux_cfg.dma0 = regk_strmux_ser0;
+ else if (dmanr == 1)
+ strmux_cfg.dma1 = regk_strmux_ser0;
+ else
+ panic("Invalid DMA channel for ser0\n");
+ break;
+ case dma_ser3:
+ if (dmanr == 2)
+ strmux_cfg.dma2 = regk_strmux_ser3;
+ else if (dmanr == 3)
+ strmux_cfg.dma3 = regk_strmux_ser3;
+ else
+ panic("Invalid DMA channel for ser3\n");
+ break;
+ case dma_strp:
+ if (dmanr == 2)
+ strmux_cfg.dma2 = regk_strmux_strcop;
+ else if (dmanr == 3)
+ strmux_cfg.dma3 = regk_strmux_strcop;
+ else
+ panic("Invalid DMA channel for strp\n");
+ break;
+ case dma_ser1:
+ if (dmanr == 4)
+ strmux_cfg.dma4 = regk_strmux_ser1;
+ else if (dmanr == 5)
+ strmux_cfg.dma5 = regk_strmux_ser1;
+ else
+ panic("Invalid DMA channel for ser1\n");
+ break;
+ case dma_iop:
+ if (dmanr == 4)
+ strmux_cfg.dma4 = regk_strmux_iop;
+ else if (dmanr == 5)
+ strmux_cfg.dma5 = regk_strmux_iop;
+ else
+ panic("Invalid DMA channel for iop\n");
+ break;
+ case dma_ser2:
+ if (dmanr == 6)
+ strmux_cfg.dma6 = regk_strmux_ser2;
+ else if (dmanr == 7)
+ strmux_cfg.dma7 = regk_strmux_ser2;
+ else
+ panic("Invalid DMA channel for ser2\n");
+ break;
+ case dma_sser:
+ if (dmanr == 6)
+ strmux_cfg.dma6 = regk_strmux_sser;
+ else if (dmanr == 7)
+ strmux_cfg.dma7 = regk_strmux_sser;
+ else
+ panic("Invalid DMA channel for sser\n");
+ break;
+ case dma_ser4:
+ if (dmanr == 9)
+ strmux_cfg.dma9 = regk_strmux_ser4;
+ else
+ panic("Invalid DMA channel for ser4\n");
+ break;
+ case dma_jpeg:
+ if (dmanr == 9)
+ strmux_cfg.dma9 = regk_strmux_jpeg;
+ else
+ panic("Invalid DMA channel for JPEG\n");
+ break;
+ case dma_h264:
+ if (dmanr == 11)
+ strmux_cfg.dma11 = regk_strmux_h264;
+ else
+ panic("Invalid DMA channel for H264\n");
+ break;
+ }
+
+ used_dma_channels[dmanr] = 1;
+ used_dma_channels_users[dmanr] = device_id;
+ REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
+ REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
+ spin_unlock_irqrestore(&dma_lock, flags);
+ return 0;
+}
+
+void crisv32_free_dma(unsigned int dmanr)
+{
+ spin_lock(&dma_lock);
+ used_dma_channels[dmanr] = 0;
+ spin_unlock(&dma_lock);
+}
--- /dev/null
+/*
+ * DDR SDRAM initialization - alter with care
+ * This file is intended to be included from other assembler files
+ *
+ * Note: This file may not modify r8 or r9 because they are used to
+ * carry information from the decompresser to the kernel
+ *
+ * Copyright (C) 2005-2007 Axis Communications AB
+ *
+ * Authors: Mikael Starvik <starvik@axis.com>
+ */
+
+/* Just to be certain the config file is included, we include it here
+ * explicitely instead of depending on it being included in the file that
+ * uses this code.
+ */
+
+#include <hwregs/asm/reg_map_asm.h>
+#include <hwregs/asm/ddr2_defs_asm.h>
+
+ ;; WARNING! The registers r8 and r9 are used as parameters carrying
+ ;; information from the decompressor (if the kernel was compressed).
+ ;; They should not be used in the code below.
+
+ ;; Refer to ddr2 MDS for initialization sequence
+
+ ; Start clock
+ move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_cfg), $r0
+ move.d REG_STATE(ddr2, rw_phy_cfg, en, yes), $r1
+ move.d $r1, [$r0]
+
+ ; Reset phy and start calibration
+ move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_phy_ctrl), $r0
+ move.d REG_STATE(ddr2, rw_phy_ctrl, rst, yes) | \
+ REG_STATE(ddr2, rw_phy_ctrl, cal_rst, yes), $r1
+ move.d $r1, [$r0]
+ move.d REG_STATE(ddr2, rw_phy_ctrl, cal_start, yes), $r1
+ move.d $r1, [$r0]
+
+ ; 2. Wait 200us
+ move.d 10000, $r2
+1: bne 1b
+ subq 1, $r2
+
+ ; Issue commands
+ move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_ctrl), $r0
+ move.d sdram_commands_start, $r2
+command_loop:
+ movu.b [$r2+], $r1
+ movu.w [$r2+], $r3
+do_cmd:
+ lslq 16, $r1
+ or.d $r3, $r1
+ move.d $r1, [$r0]
+ cmp.d sdram_commands_end, $r2
+ blo command_loop
+ nop
+
+ ; Set timing
+ move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing), $r0
+ move.d CONFIG_ETRAX_DDR2_TIMING, $r1
+ move.d $r1, [$r0]
+
+ ; Set latency
+ move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_latency), $r0
+ move.d 0x13, $r1
+ move.d $r1, [$r0]
+
+ ; Set configuration
+ move.d REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg), $r0
+ move.d CONFIG_ETRAX_DDR2_CONFIG, $r1
+ move.d $r1, [$r0]
+
+ ba after_sdram_commands
+ nop
+
+sdram_commands_start:
+ .byte regk_ddr2_deselect
+ .word 0
+ .byte regk_ddr2_pre
+ .word regk_ddr2_pre_all
+ .byte regk_ddr2_emrs2
+ .word 0
+ .byte regk_ddr2_emrs3
+ .word 0
+ .byte regk_ddr2_emrs
+ .word regk_ddr2_dll_en
+ .byte regk_ddr2_mrs
+ .word regk_ddr2_dll_rst
+ .byte regk_ddr2_pre
+ .word regk_ddr2_pre_all
+ .byte regk_ddr2_ref
+ .word 0
+ .byte regk_ddr2_ref
+ .word 0
+ .byte regk_ddr2_mrs
+ .word CONFIG_ETRAX_DDR2_MRS & 0xffff
+ .byte regk_ddr2_emrs
+ .word regk_ddr2_ocd_default | regk_ddr2_dll_en
+ .byte regk_ddr2_emrs
+ .word regk_ddr2_ocd_exit | regk_ddr2_dll_en | (CONFIG_ETRAX_DDR2_MRS >> 16)
+sdram_commands_end:
+ .align 1
+after_sdram_commands:
--- /dev/null
+/*
+ * This table is used by some tools to extract hardware parameters.
+ * The table should be included in the kernel and the decompressor.
+ * Don't forget to update the tools if you change this table.
+ *
+ * Copyright (C) 2001-2007 Axis Communications AB
+ *
+ * Authors: Mikael Starvik <starvik@axis.com>
+ */
+
+#include <hwregs/asm/reg_map_asm.h>
+#include <hwregs/asm/ddr2_defs_asm.h>
+#include <hwregs/asm/gio_defs_asm.h>
+
+ .ascii "HW_PARAM_MAGIC" ; Magic number
+ .dword 0xc0004000 ; Kernel start address
+
+ ; Debug port
+#ifdef CONFIG_ETRAX_DEBUG_PORT0
+ .dword 0
+#elif defined(CONFIG_ETRAX_DEBUG_PORT1)
+ .dword 1
+#elif defined(CONFIG_ETRAX_DEBUG_PORT2)
+ .dword 2
+#elif defined(CONFIG_ETRAX_DEBUG_PORT3)
+ .dword 3
+#else
+ .dword 4 ; No debug
+#endif
+
+ ; Register values
+ .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_cfg)
+ .dword CONFIG_ETRAX_DDR2_CONFIG
+ .dword REG_ADDR(ddr2, regi_ddr2_ctrl, rw_timing)
+ .dword CONFIG_ETRAX_DDR2_TIMING
+ .dword CONFIG_ETRAX_DDR2_MRS
+
+ .dword REG_ADDR(gio, regi_gio, rw_pa_dout)
+ .dword CONFIG_ETRAX_DEF_GIO_PA_OUT
+ .dword REG_ADDR(gio, regi_gio, rw_pa_oe)
+ .dword CONFIG_ETRAX_DEF_GIO_PA_OE
+ .dword REG_ADDR(gio, regi_gio, rw_pb_dout)
+ .dword CONFIG_ETRAX_DEF_GIO_PB_OUT
+ .dword REG_ADDR(gio, regi_gio, rw_pb_oe)
+ .dword CONFIG_ETRAX_DEF_GIO_PB_OE
+ .dword REG_ADDR(gio, regi_gio, rw_pc_dout)
+ .dword CONFIG_ETRAX_DEF_GIO_PC_OUT
+ .dword REG_ADDR(gio, regi_gio, rw_pc_oe)
+ .dword CONFIG_ETRAX_DEF_GIO_PC_OE
+
+ .dword 0 ; No more register values
--- /dev/null
+/*
+ * Helper functions for I/O pins.
+ *
+ * Copyright (c) 2005-2007 Axis Communications AB.
+ */
+
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/io.h>
+#include <asm/arch/mach/pinmux.h>
+#include <hwregs/gio_defs.h>
+
+struct crisv32_ioport crisv32_ioports[] = {
+ {
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
+ (unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
+ 32
+ },
+ {
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
+ (unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
+ 32
+ },
+ {
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
+ (unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
+ 16
+ },
+};
+
+#define NBR_OF_PORTS sizeof(crisv32_ioports)/sizeof(struct crisv32_ioport)
+
+struct crisv32_iopin crisv32_led_net0_green;
+struct crisv32_iopin crisv32_led_net0_red;
+struct crisv32_iopin crisv32_led2_green;
+struct crisv32_iopin crisv32_led2_red;
+struct crisv32_iopin crisv32_led3_green;
+struct crisv32_iopin crisv32_led3_red;
+
+/* Dummy port used when green LED and red LED is on the same bit */
+static unsigned long io_dummy;
+static struct crisv32_ioport dummy_port = {
+ &io_dummy,
+ &io_dummy,
+ &io_dummy,
+ 32
+};
+static struct crisv32_iopin dummy_led = {
+ &dummy_port,
+ 0
+};
+
+static int __init crisv32_io_init(void)
+{
+ int ret = 0;
+
+ u32 i;
+
+ /* Locks *should* be dynamically initialized. */
+ for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
+ spin_lock_init(&crisv32_ioports[i].lock);
+ spin_lock_init(&dummy_port.lock);
+
+ /* Initialize LEDs */
+#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
+ ret += crisv32_io_get_name(&crisv32_led_net0_green,
+ CONFIG_ETRAX_LED_G_NET0);
+ crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
+ if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
+ ret += crisv32_io_get_name(&crisv32_led_net0_red,
+ CONFIG_ETRAX_LED_R_NET0);
+ crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
+ } else
+ crisv32_led_net0_red = dummy_led;
+#endif
+
+ ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
+ ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
+ ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
+ ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
+
+ crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
+ crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
+ crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
+ crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
+
+ return ret;
+}
+
+__initcall(crisv32_io_init);
+
+int crisv32_io_get(struct crisv32_iopin *iopin,
+ unsigned int port, unsigned int pin)
+{
+ if (port > NBR_OF_PORTS)
+ return -EINVAL;
+ if (port > crisv32_ioports[port].pin_count)
+ return -EINVAL;
+
+ iopin->bit = 1 << pin;
+ iopin->port = &crisv32_ioports[port];
+
+ if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
+ return -EIO;
+
+ return 0;
+}
+
+int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
+{
+ int port;
+ int pin;
+
+ if (toupper(*name) == 'P')
+ name++;
+
+ if (toupper(*name) < 'A' || toupper(*name) > 'E')
+ return -EINVAL;
+
+ port = toupper(*name) - 'A';
+ name++;
+ pin = simple_strtoul(name, NULL, 10);
+
+ if (pin < 0 || pin > crisv32_ioports[port].pin_count)
+ return -EINVAL;
+
+ iopin->bit = 1 << pin;
+ iopin->port = &crisv32_ioports[port];
+
+ if (crisv32_pinmux_alloc(port, pin, pin, pinmux_gpio))
+ return -EIO;
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+/* PCI I/O access stuff */
+struct cris_io_operations *cris_iops = NULL;
+EXPORT_SYMBOL(cris_iops);
+#endif
+
--- /dev/null
+/*
+ * Allocator for I/O pins. All pins are allocated to GPIO at bootup.
+ * Unassigned pins and GPIO pins can be allocated to a fixed interface
+ * or the I/O processor instead.
+ *
+ * Copyright (c) 2005-2007 Axis Communications AB.
+ */
+
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/spinlock.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <pinmux.h>
+#include <hwregs/pinmux_defs.h>
+#include <hwregs/clkgen_defs.h>
+
+#undef DEBUG
+
+#define PINS 80
+#define PORT_PINS 32
+#define PORTS 3
+
+static char pins[PINS];
+static DEFINE_SPINLOCK(pinmux_lock);
+
+static void crisv32_pinmux_set(int port);
+
+int
+crisv32_pinmux_init(void)
+{
+ static int initialized;
+
+ if (!initialized) {
+ initialized = 1;
+ REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0);
+ crisv32_pinmux_alloc(PORT_A, 0, 31, pinmux_gpio);
+ crisv32_pinmux_alloc(PORT_B, 0, 31, pinmux_gpio);
+ crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_gpio);
+ }
+
+ return 0;
+}
+
+int
+crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode)
+{
+ int i;
+ unsigned long flags;
+
+ crisv32_pinmux_init();
+
+ if (port >= PORTS)
+ return -EINVAL;
+
+ spin_lock_irqsave(&pinmux_lock, flags);
+
+ for (i = first_pin; i <= last_pin; i++) {
+ if ((pins[port * PORT_PINS + i] != pinmux_none) &&
+ (pins[port * PORT_PINS + i] != pinmux_gpio) &&
+ (pins[port * PORT_PINS + i] != mode)) {
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+#ifdef DEBUG
+ panic("Pinmux alloc failed!\n");
+#endif
+ return -EPERM;
+ }
+ }
+
+ for (i = first_pin; i <= last_pin; i++)
+ pins[port * PORT_PINS + i] = mode;
+
+ crisv32_pinmux_set(port);
+
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+
+ return 0;
+}
+
+int
+crisv32_pinmux_alloc_fixed(enum fixed_function function)
+{
+ int ret = -EINVAL;
+ char saved[sizeof pins];
+ unsigned long flags;
+
+ spin_lock_irqsave(&pinmux_lock, flags);
+
+ /* Save internal data for recovery */
+ memcpy(saved, pins, sizeof pins);
+
+ crisv32_pinmux_init(); /* must be done before we read rw_hwprot */
+
+ reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
+ reg_clkgen_rw_clk_ctrl clk_ctrl = REG_RD(clkgen, regi_clkgen,
+ rw_clk_ctrl);
+
+ switch (function) {
+ case pinmux_eth:
+ clk_ctrl.eth = regk_clkgen_yes;
+ clk_ctrl.dma0_1_eth = regk_clkgen_yes;
+ ret = crisv32_pinmux_alloc(PORT_B, 8, 23, pinmux_fixed);
+ ret |= crisv32_pinmux_alloc(PORT_B, 24, 25, pinmux_fixed);
+ hwprot.eth = hwprot.eth_mdio = regk_pinmux_yes;
+ break;
+ case pinmux_geth:
+ ret = crisv32_pinmux_alloc(PORT_B, 0, 7, pinmux_fixed);
+ hwprot.geth = regk_pinmux_yes;
+ break;
+ case pinmux_tg_cmos:
+ clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes;
+ ret = crisv32_pinmux_alloc(PORT_B, 27, 29, pinmux_fixed);
+ hwprot.tg_clk = regk_pinmux_yes;
+ break;
+ case pinmux_tg_ccd:
+ clk_ctrl.ccd_tg_100 = clk_ctrl.ccd_tg_200 = regk_clkgen_yes;
+ ret = crisv32_pinmux_alloc(PORT_B, 27, 31, pinmux_fixed);
+ ret |= crisv32_pinmux_alloc(PORT_C, 0, 15, pinmux_fixed);
+ hwprot.tg = hwprot.tg_clk = regk_pinmux_yes;
+ break;
+ case pinmux_vout:
+ clk_ctrl.strdma0_2_video = regk_clkgen_yes;
+ ret = crisv32_pinmux_alloc(PORT_A, 8, 18, pinmux_fixed);
+ hwprot.vout = hwprot.vout_sync = regk_pinmux_yes;
+ break;
+ case pinmux_ser1:
+ clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
+ ret = crisv32_pinmux_alloc(PORT_A, 24, 25, pinmux_fixed);
+ hwprot.ser1 = regk_pinmux_yes;
+ break;
+ case pinmux_ser2:
+ clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
+ ret = crisv32_pinmux_alloc(PORT_A, 26, 27, pinmux_fixed);
+ hwprot.ser2 = regk_pinmux_yes;
+ break;
+ case pinmux_ser3:
+ clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
+ ret = crisv32_pinmux_alloc(PORT_A, 28, 29, pinmux_fixed);
+ hwprot.ser3 = regk_pinmux_yes;
+ break;
+ case pinmux_ser4:
+ clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
+ ret = crisv32_pinmux_alloc(PORT_A, 30, 31, pinmux_fixed);
+ hwprot.ser4 = regk_pinmux_yes;
+ break;
+ case pinmux_sser:
+ clk_ctrl.sser_ser_dma6_7 = regk_clkgen_yes;
+ ret = crisv32_pinmux_alloc(PORT_A, 19, 23, pinmux_fixed);
+ hwprot.sser = regk_pinmux_yes;
+ break;
+ case pinmux_pio:
+ hwprot.pio = regk_pinmux_yes;
+ ret = 0;
+ break;
+ case pinmux_pwm0:
+ ret = crisv32_pinmux_alloc(PORT_A, 30, 30, pinmux_fixed);
+ hwprot.pwm0 = regk_pinmux_yes;
+ break;
+ case pinmux_pwm1:
+ ret = crisv32_pinmux_alloc(PORT_A, 31, 31, pinmux_fixed);
+ hwprot.pwm1 = regk_pinmux_yes;
+ break;
+ case pinmux_pwm2:
+ ret = crisv32_pinmux_alloc(PORT_B, 26, 26, pinmux_fixed);
+ hwprot.pwm2 = regk_pinmux_yes;
+ break;
+ case pinmux_i2c0:
+ ret = crisv32_pinmux_alloc(PORT_A, 0, 1, pinmux_fixed);
+ hwprot.i2c0 = regk_pinmux_yes;
+ break;
+ case pinmux_i2c1:
+ ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
+ hwprot.i2c1 = regk_pinmux_yes;
+ break;
+ case pinmux_i2c1_3wire:
+ ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
+ ret |= crisv32_pinmux_alloc(PORT_A, 7, 7, pinmux_fixed);
+ hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_yes;
+ break;
+ case pinmux_i2c1_sda1:
+ ret = crisv32_pinmux_alloc(PORT_A, 2, 4, pinmux_fixed);
+ hwprot.i2c1 = hwprot.i2c1_sda1 = regk_pinmux_yes;
+ break;
+ case pinmux_i2c1_sda2:
+ ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
+ ret |= crisv32_pinmux_alloc(PORT_A, 5, 5, pinmux_fixed);
+ hwprot.i2c1 = hwprot.i2c1_sda2 = regk_pinmux_yes;
+ break;
+ case pinmux_i2c1_sda3:
+ ret = crisv32_pinmux_alloc(PORT_A, 2, 3, pinmux_fixed);
+ ret |= crisv32_pinmux_alloc(PORT_A, 6, 6, pinmux_fixed);
+ hwprot.i2c1 = hwprot.i2c1_sda3 = regk_pinmux_yes;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (!ret) {
+ REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
+ REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl);
+ } else
+ memcpy(pins, saved, sizeof pins);
+
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+
+ return ret;
+}
+
+void
+crisv32_pinmux_set(int port)
+{
+ int i;
+ int gpio_val = 0;
+ int iop_val = 0;
+ int pin = port * PORT_PINS;
+
+ for (i = 0; (i < PORT_PINS) && (pin < PINS); i++, pin++) {
+ if (pins[pin] == pinmux_gpio)
+ gpio_val |= (1 << i);
+ else if (pins[pin] == pinmux_iop)
+ iop_val |= (1 << i);
+ }
+
+ REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_gio_pa + 4 * port,
+ gpio_val);
+ REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_iop_pa + 4 * port,
+ iop_val);
+
+#ifdef DEBUG
+ crisv32_pinmux_dump();
+#endif
+}
+
+int
+crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
+{
+ int i;
+ unsigned long flags;
+
+ crisv32_pinmux_init();
+
+ if (port > PORTS)
+ return -EINVAL;
+
+ spin_lock_irqsave(&pinmux_lock, flags);
+
+ for (i = first_pin; i <= last_pin; i++)
+ pins[port * PORT_PINS + i] = pinmux_none;
+
+ crisv32_pinmux_set(port);
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+
+ return 0;
+}
+
+int
+crisv32_pinmux_dealloc_fixed(enum fixed_function function)
+{
+ int ret = -EINVAL;
+ char saved[sizeof pins];
+ unsigned long flags;
+
+ spin_lock_irqsave(&pinmux_lock, flags);
+
+ /* Save internal data for recovery */
+ memcpy(saved, pins, sizeof pins);
+
+ crisv32_pinmux_init(); /* must be done before we read rw_hwprot */
+
+ reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
+
+ switch (function) {
+ case pinmux_eth:
+ ret = crisv32_pinmux_dealloc(PORT_B, 8, 23);
+ ret |= crisv32_pinmux_dealloc(PORT_B, 24, 25);
+ ret |= crisv32_pinmux_dealloc(PORT_B, 0, 7);
+ hwprot.eth = hwprot.eth_mdio = hwprot.geth = regk_pinmux_no;
+ break;
+ case pinmux_tg_cmos:
+ ret = crisv32_pinmux_dealloc(PORT_B, 27, 29);
+ hwprot.tg_clk = regk_pinmux_no;
+ break;
+ case pinmux_tg_ccd:
+ ret = crisv32_pinmux_dealloc(PORT_B, 27, 31);
+ ret |= crisv32_pinmux_dealloc(PORT_C, 0, 15);
+ hwprot.tg = hwprot.tg_clk = regk_pinmux_no;
+ break;
+ case pinmux_vout:
+ ret = crisv32_pinmux_dealloc(PORT_A, 8, 18);
+ hwprot.vout = hwprot.vout_sync = regk_pinmux_no;
+ break;
+ case pinmux_ser1:
+ ret = crisv32_pinmux_dealloc(PORT_A, 24, 25);
+ hwprot.ser1 = regk_pinmux_no;
+ break;
+ case pinmux_ser2:
+ ret = crisv32_pinmux_dealloc(PORT_A, 26, 27);
+ hwprot.ser2 = regk_pinmux_no;
+ break;
+ case pinmux_ser3:
+ ret = crisv32_pinmux_dealloc(PORT_A, 28, 29);
+ hwprot.ser3 = regk_pinmux_no;
+ break;
+ case pinmux_ser4:
+ ret = crisv32_pinmux_dealloc(PORT_A, 30, 31);
+ hwprot.ser4 = regk_pinmux_no;
+ break;
+ case pinmux_sser:
+ ret = crisv32_pinmux_dealloc(PORT_A, 19, 23);
+ hwprot.sser = regk_pinmux_no;
+ break;
+ case pinmux_pwm0:
+ ret = crisv32_pinmux_dealloc(PORT_A, 30, 30);
+ hwprot.pwm0 = regk_pinmux_no;
+ break;
+ case pinmux_pwm1:
+ ret = crisv32_pinmux_dealloc(PORT_A, 31, 31);
+ hwprot.pwm1 = regk_pinmux_no;
+ break;
+ case pinmux_pwm2:
+ ret = crisv32_pinmux_dealloc(PORT_B, 26, 26);
+ hwprot.pwm2 = regk_pinmux_no;
+ break;
+ case pinmux_i2c0:
+ ret = crisv32_pinmux_dealloc(PORT_A, 0, 1);
+ hwprot.i2c0 = regk_pinmux_no;
+ break;
+ case pinmux_i2c1:
+ ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
+ hwprot.i2c1 = regk_pinmux_no;
+ break;
+ case pinmux_i2c1_3wire:
+ ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
+ ret |= crisv32_pinmux_dealloc(PORT_A, 7, 7);
+ hwprot.i2c1 = hwprot.i2c1_sen = regk_pinmux_no;
+ break;
+ case pinmux_i2c1_sda1:
+ ret = crisv32_pinmux_dealloc(PORT_A, 2, 4);
+ hwprot.i2c1_sda1 = regk_pinmux_no;
+ break;
+ case pinmux_i2c1_sda2:
+ ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
+ ret |= crisv32_pinmux_dealloc(PORT_A, 5, 5);
+ hwprot.i2c1_sda2 = regk_pinmux_no;
+ break;
+ case pinmux_i2c1_sda3:
+ ret = crisv32_pinmux_dealloc(PORT_A, 2, 3);
+ ret |= crisv32_pinmux_dealloc(PORT_A, 6, 6);
+ hwprot.i2c1_sda3 = regk_pinmux_no;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ if (!ret)
+ REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
+ else
+ memcpy(pins, saved, sizeof pins);
+
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+
+ return ret;
+}
+
+void
+crisv32_pinmux_dump(void)
+{
+ int i, j;
+ int pin = 0;
+
+ crisv32_pinmux_init();
+
+ for (i = 0; i < PORTS; i++) {
+ pin++;
+ printk(KERN_DEBUG "Port %c\n", 'A'+i);
+ for (j = 0; (j < PORT_PINS) && (pin < PINS); j++, pin++)
+ printk(KERN_DEBUG
+ " Pin %d = %d\n", j, pins[i * PORT_PINS + j]);
+ }
+}
+
+__initcall(crisv32_pinmux_init);
--- /dev/null
+/*
+ * Simulator hook mechanism
+ */
+
+#include "vcs_hook.h"
+#include <asm/io.h>
+#include <stdarg.h>
+
+#define HOOK_TRIG_ADDR 0xb7000000
+#define HOOK_MEM_BASE_ADDR 0xce000000
+
+static volatile unsigned *hook_base;
+
+#define HOOK_DATA(offset) hook_base[offset]
+#define VHOOK_DATA(offset) hook_base[offset]
+#define HOOK_TRIG(funcid) \
+ do { \
+ *((unsigned *) HOOK_TRIG_ADDR) = funcid; \
+ } while (0)
+#define HOOK_DATA_BYTE(offset) ((unsigned char *)hook_base)[offset]
+
+static void hook_init(void)
+{
+ static int first = 1;
+ if (first) {
+ first = 0;
+ hook_base = ioremap(HOOK_MEM_BASE_ADDR, 8192);
+ }
+}
+
+static unsigned hook_trig(unsigned id)
+{
+ unsigned ret;
+
+ /* preempt_disable(); */
+
+ /* Dummy read from mem to make sure data has propagated to memory
+ * before trigging */
+ ret = *hook_base;
+
+ /* trigger hook */
+ HOOK_TRIG(id);
+
+ /* wait for call to finish */
+ while (VHOOK_DATA(0) > 0) ;
+
+ /* extract return value */
+
+ ret = VHOOK_DATA(1);
+
+ return ret;
+}
+
+int hook_call(unsigned id, unsigned pcnt, ...)
+{
+ va_list ap;
+ int i;
+ unsigned ret;
+
+ hook_init();
+
+ HOOK_DATA(0) = id;
+
+ va_start(ap, pcnt);
+ for (i = 1; i <= pcnt; i++)
+ HOOK_DATA(i) = va_arg(ap, unsigned);
+ va_end(ap);
+
+ ret = hook_trig(id);
+
+ return ret;
+}
+
+int hook_call_str(unsigned id, unsigned size, const char *str)
+{
+ int i;
+ unsigned ret;
+
+ hook_init();
+
+ HOOK_DATA(0) = id;
+ HOOK_DATA(1) = size;
+
+ for (i = 0; i < size; i++)
+ HOOK_DATA_BYTE(8 + i) = str[i];
+ HOOK_DATA_BYTE(8 + i) = 0;
+
+ ret = hook_trig(id);
+
+ return ret;
+}
+
+void print_str(const char *str)
+{
+ int i;
+ /* find null at end of string */
+ for (i = 1; str[i]; i++) ;
+ hook_call(hook_print_str, i, str);
+}
+
+void CPU_WATCHDOG_TIMEOUT(unsigned t)
+{
+}
--- /dev/null
+/*
+ * Simulator hook call mechanism
+ */
+
+#ifndef __hook_h__
+#define __hook_h__
+
+int hook_call(unsigned id, unsigned pcnt, ...);
+int hook_call_str(unsigned id, unsigned size, const char *str);
+
+enum hook_ids {
+ hook_debug_on = 1,
+ hook_debug_off,
+ hook_stop_sim_ok,
+ hook_stop_sim_fail,
+ hook_alloc_shared,
+ hook_ptr_shared,
+ hook_free_shared,
+ hook_file2shared,
+ hook_cmp_shared,
+ hook_print_params,
+ hook_sim_time,
+ hook_stop_sim,
+ hook_kick_dog,
+ hook_dog_timeout,
+ hook_rand,
+ hook_srand,
+ hook_rand_range,
+ hook_print_str,
+ hook_print_hex,
+ hook_cmp_offset_shared,
+ hook_fill_random_shared,
+ hook_alloc_random_data,
+ hook_calloc_random_data,
+ hook_print_int,
+ hook_print_uint,
+ hook_fputc,
+ hook_init_fd,
+ hook_sbrk,
+ hook_print_context_descr,
+ hook_print_data_descr,
+ hook_print_group_descr,
+ hook_fill_shared,
+ hook_sl_srand,
+ hook_sl_rand_irange,
+ hook_sl_rand_urange,
+ hook_sl_sh_malloc_aligned,
+ hook_sl_sh_calloc_aligned,
+ hook_sl_sh_alloc_random_data,
+ hook_sl_sh_file2mem,
+ hook_sl_vera_mbox_handle,
+ hook_sl_vera_mbox_put,
+ hook_sl_vera_mbox_get,
+ hook_sl_system,
+ hook_sl_sh_hexdump
+};
+
+#endif
--- /dev/null
+if ETRAXFS
+
+menu "ETRAX FS options"
+ depends on ETRAXFS
+
+config ETRAX_DRAM_VIRTUAL_BASE
+ hex
+ depends on ETRAX_ARCH_V32
+ default "c0000000"
+
+config ETRAX_SERIAL_PORTS
+ int
+ default 4
+
+config ETRAX_MEM_GRP1_CONFIG
+ hex "MEM_GRP1_CONFIG"
+ depends on ETRAX_ARCH_V32
+ default "4044a"
+ help
+ Waitstates for flash. The default value is suitable for the
+ standard flashes used in axis products (120 ns).
+
+config ETRAX_MEM_GRP2_CONFIG
+ hex "MEM_GRP2_CONFIG"
+ depends on ETRAX_ARCH_V32
+ default "0"
+ help
+ Waitstates for SRAM. 0 is a good choice for most Axis products.
+
+config ETRAX_MEM_GRP3_CONFIG
+ hex "MEM_GRP3_CONFIG"
+ depends on ETRAX_ARCH_V32
+ default "0"
+ help
+ Waitstates for CSP0-3. 0 is a good choice for most Axis products.
+ It may need to be changed if external devices such as extra
+ register-mapped LEDs are used.
+
+config ETRAX_MEM_GRP4_CONFIG
+ hex "MEM_GRP4_CONFIG"
+ depends on ETRAX_ARCH_V32
+ default "0"
+ help
+ Waitstates for CSP4-6. 0 is a good choice for most Axis products.
+
+config ETRAX_SDRAM_GRP0_CONFIG
+ hex "SDRAM_GRP0_CONFIG"
+ depends on ETRAX_ARCH_V32
+ default "336"
+ help
+ SDRAM configuration for group 0. The value depends on the
+ hardware configuration. The default value is suitable
+ for 32 MB organized as two 16 bits chips (e.g. Axis
+ part number 18550) connected as one 32 bit device (i.e. in
+ the same group).
+
+config ETRAX_SDRAM_GRP1_CONFIG
+ hex "SDRAM_GRP1_CONFIG"
+ depends on ETRAX_ARCH_V32
+ default "0"
+ help
+ SDRAM configuration for group 1. The defult value is 0
+ because group 1 is not used in the default configuration,
+ described in the help for SDRAM_GRP0_CONFIG.
+
+config ETRAX_SDRAM_TIMING
+ hex "SDRAM_TIMING"
+ depends on ETRAX_ARCH_V32
+ default "104a"
+ help
+ SDRAM timing parameters. The default value is ok for
+ most hardwares but large SDRAMs may require a faster
+ refresh (a.k.a 8K refresh). The default value implies
+ 100MHz clock and SDR mode.
+
+config ETRAX_SDRAM_COMMAND
+ hex "SDRAM_COMMAND"
+ depends on ETRAX_ARCH_V32
+ default "0"
+ help
+ SDRAM command. Should be 0 unless you really know what
+ you are doing (may be != 0 for unusual address line
+ mappings such as in a MCM)..
+
+config ETRAX_DEF_GIO_PA_OE
+ hex "GIO_PA_OE"
+ depends on ETRAX_ARCH_V32
+ default "1c"
+ help
+ Configures the direction of general port A bits. 1 is out, 0 is in.
+ This is often totally different depending on the product used.
+ There are some guidelines though - if you know that only LED's are
+ connected to port PA, then they are usually connected to bits 2-4
+ and you can therefore use 1c. On other boards which don't have the
+ LED's at the general ports, these bits are used for all kinds of
+ stuff. If you don't know what to use, it is always safe to put all
+ as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PA_OUT
+ hex "GIO_PA_OUT"
+ depends on ETRAX_ARCH_V32
+ default "00"
+ help
+ Configures the initial data for the general port A bits. Most
+ products should use 00 here.
+
+config ETRAX_DEF_GIO_PB_OE
+ hex "GIO_PB_OE"
+ depends on ETRAX_ARCH_V32
+ default "00000"
+ help
+ Configures the direction of general port B bits. 1 is out, 0 is in.
+ This is often totally different depending on the product used.
+ There are some guidelines though - if you know that only LED's are
+ connected to port PA, then they are usually connected to bits 2-4
+ and you can therefore use 1c. On other boards which don't have the
+ LED's at the general ports, these bits are used for all kinds of
+ stuff. If you don't know what to use, it is always safe to put all
+ as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PB_OUT
+ hex "GIO_PB_OUT"
+ depends on ETRAX_ARCH_V32
+ default "00000"
+ help
+ Configures the initial data for the general port B bits. Most
+ products should use 00000 here.
+
+config ETRAX_DEF_GIO_PC_OE
+ hex "GIO_PC_OE"
+ depends on ETRAX_ARCH_V32
+ default "00000"
+ help
+ Configures the direction of general port C bits. 1 is out, 0 is in.
+ This is often totally different depending on the product used.
+ There are some guidelines though - if you know that only LED's are
+ connected to port PA, then they are usually connected to bits 2-4
+ and you can therefore use 1c. On other boards which don't have the
+ LED's at the general ports, these bits are used for all kinds of
+ stuff. If you don't know what to use, it is always safe to put all
+ as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PC_OUT
+ hex "GIO_PC_OUT"
+ depends on ETRAX_ARCH_V32
+ default "00000"
+ help
+ Configures the initial data for the general port C bits. Most
+ products should use 00000 here.
+
+config ETRAX_DEF_GIO_PD_OE
+ hex "GIO_PD_OE"
+ depends on ETRAX_ARCH_V32
+ default "00000"
+ help
+ Configures the direction of general port D bits. 1 is out, 0 is in.
+ This is often totally different depending on the product used.
+ There are some guidelines though - if you know that only LED's are
+ connected to port PA, then they are usually connected to bits 2-4
+ and you can therefore use 1c. On other boards which don't have the
+ LED's at the general ports, these bits are used for all kinds of
+ stuff. If you don't know what to use, it is always safe to put all
+ as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PD_OUT
+ hex "GIO_PD_OUT"
+ depends on ETRAX_ARCH_V32
+ default "00000"
+ help
+ Configures the initial data for the general port D bits. Most
+ products should use 00000 here.
+
+config ETRAX_DEF_GIO_PE_OE
+ hex "GIO_PE_OE"
+ depends on ETRAX_ARCH_V32
+ default "00000"
+ help
+ Configures the direction of general port E bits. 1 is out, 0 is in.
+ This is often totally different depending on the product used.
+ There are some guidelines though - if you know that only LED's are
+ connected to port PA, then they are usually connected to bits 2-4
+ and you can therefore use 1c. On other boards which don't have the
+ LED's at the general ports, these bits are used for all kinds of
+ stuff. If you don't know what to use, it is always safe to put all
+ as inputs, although floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PE_OUT
+ hex "GIO_PE_OUT"
+ depends on ETRAX_ARCH_V32
+ default "00000"
+ help
+ Configures the initial data for the general port E bits. Most
+ products should use 00000 here.
+
+config ETRAX_DEF_GIO_PV_OE
+ hex "GIO_PV_OE"
+ depends on ETRAX_VIRTUAL_GPIO
+ default "0000"
+ help
+ Configures the direction of virtual general port V bits. 1 is out,
+ 0 is in. This is often totally different depending on the product
+ used. These bits are used for all kinds of stuff. If you don't know
+ what to use, it is always safe to put all as inputs, although
+ floating inputs isn't good.
+
+config ETRAX_DEF_GIO_PV_OUT
+ hex "GIO_PV_OUT"
+ depends on ETRAX_VIRTUAL_GPIO
+ default "0000"
+ help
+ Configures the initial data for the virtual general port V bits.
+ Most products should use 0000 here.
+
+endmenu
+
+endif
--- /dev/null
+# $Id: Makefile,v 1.3 2007/03/13 11:57:46 starvik Exp $
+#
+# Makefile for the linux kernel.
+#
+
+obj-y := dma.o pinmux.o io.o arbiter.o
+bj-$(CONFIG_ETRAX_VCS_SIM) += vcs_hook.o
+obj-$(CONFIG_CPU_FREQ) += cpufreq.o
+
+clean:
+
--- /dev/null
+/*
+ * Memory arbiter functions. Allocates bandwidth through the
+ * arbiter and sets up arbiter breakpoints.
+ *
+ * The algorithm first assigns slots to the clients that has specified
+ * bandwidth (e.g. ethernet) and then the remaining slots are divided
+ * on all the active clients.
+ *
+ * Copyright (c) 2004-2007 Axis Communications AB.
+ */
+
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/marb_defs.h>
+#include <arbiter.h>
+#include <hwregs/intr_vect.h>
+#include <linux/interrupt.h>
+#include <linux/signal.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+#include <asm/irq_regs.h>
+
+struct crisv32_watch_entry {
+ unsigned long instance;
+ watch_callback *cb;
+ unsigned long start;
+ unsigned long end;
+ int used;
+};
+
+#define NUMBER_OF_BP 4
+#define NBR_OF_CLIENTS 14
+#define NBR_OF_SLOTS 64
+#define SDRAM_BANDWIDTH 100000000 /* Some kind of expected value */
+#define INTMEM_BANDWIDTH 400000000
+#define NBR_OF_REGIONS 2
+
+static struct crisv32_watch_entry watches[NUMBER_OF_BP] = {
+ {regi_marb_bp0},
+ {regi_marb_bp1},
+ {regi_marb_bp2},
+ {regi_marb_bp3}
+};
+
+static u8 requested_slots[NBR_OF_REGIONS][NBR_OF_CLIENTS];
+static u8 active_clients[NBR_OF_REGIONS][NBR_OF_CLIENTS];
+static int max_bandwidth[NBR_OF_REGIONS] =
+ { SDRAM_BANDWIDTH, INTMEM_BANDWIDTH };
+
+DEFINE_SPINLOCK(arbiter_lock);
+
+static irqreturn_t crisv32_arbiter_irq(int irq, void *dev_id);
+
+/*
+ * "I'm the arbiter, I know the score.
+ * From square one I'll be watching all 64."
+ * (memory arbiter slots, that is)
+ *
+ * Or in other words:
+ * Program the memory arbiter slots for "region" according to what's
+ * in requested_slots[] and active_clients[], while minimizing
+ * latency. A caller may pass a non-zero positive amount for
+ * "unused_slots", which must then be the unallocated, remaining
+ * number of slots, free to hand out to any client.
+ */
+
+static void crisv32_arbiter_config(int region, int unused_slots)
+{
+ int slot;
+ int client;
+ int interval = 0;
+
+ /*
+ * This vector corresponds to the hardware arbiter slots (see
+ * the hardware documentation for semantics). We initialize
+ * each slot with a suitable sentinel value outside the valid
+ * range {0 .. NBR_OF_CLIENTS - 1} and replace them with
+ * client indexes. Then it's fed to the hardware.
+ */
+ s8 val[NBR_OF_SLOTS];
+
+ for (slot = 0; slot < NBR_OF_SLOTS; slot++)
+ val[slot] = -1;
+
+ for (client = 0; client < NBR_OF_CLIENTS; client++) {
+ int pos;
+ /* Allocate the requested non-zero number of slots, but
+ * also give clients with zero-requests one slot each
+ * while stocks last. We do the latter here, in client
+ * order. This makes sure zero-request clients are the
+ * first to get to any spare slots, else those slots
+ * could, when bandwidth is allocated close to the limit,
+ * all be allocated to low-index non-zero-request clients
+ * in the default-fill loop below. Another positive but
+ * secondary effect is a somewhat better spread of the
+ * zero-bandwidth clients in the vector, avoiding some of
+ * the latency that could otherwise be caused by the
+ * partitioning of non-zero-bandwidth clients at low
+ * indexes and zero-bandwidth clients at high
+ * indexes. (Note that this spreading can only affect the
+ * unallocated bandwidth.) All the above only matters for
+ * memory-intensive situations, of course.
+ */
+ if (!requested_slots[region][client]) {
+ /*
+ * Skip inactive clients. Also skip zero-slot
+ * allocations in this pass when there are no known
+ * free slots.
+ */
+ if (!active_clients[region][client]
+ || unused_slots <= 0)
+ continue;
+
+ unused_slots--;
+
+ /* Only allocate one slot for this client. */
+ interval = NBR_OF_SLOTS;
+ } else
+ interval =
+ NBR_OF_SLOTS / requested_slots[region][client];
+
+ pos = 0;
+ while (pos < NBR_OF_SLOTS) {
+ if (val[pos] >= 0)
+ pos++;
+ else {
+ val[pos] = client;
+ pos += interval;
+ }
+ }
+ }
+
+ client = 0;
+ for (slot = 0; slot < NBR_OF_SLOTS; slot++) {
+ /*
+ * Allocate remaining slots in round-robin
+ * client-number order for active clients. For this
+ * pass, we ignore requested bandwidth and previous
+ * allocations.
+ */
+ if (val[slot] < 0) {
+ int first = client;
+ while (!active_clients[region][client]) {
+ client = (client + 1) % NBR_OF_CLIENTS;
+ if (client == first)
+ break;
+ }
+ val[slot] = client;
+ client = (client + 1) % NBR_OF_CLIENTS;
+ }
+ if (region == EXT_REGION)
+ REG_WR_INT_VECT(marb, regi_marb, rw_ext_slots, slot,
+ val[slot]);
+ else if (region == INT_REGION)
+ REG_WR_INT_VECT(marb, regi_marb, rw_int_slots, slot,
+ val[slot]);
+ }
+}
+
+extern char _stext, _etext;
+
+static void crisv32_arbiter_init(void)
+{
+ static int initialized;
+
+ if (initialized)
+ return;
+
+ initialized = 1;
+
+ /*
+ * CPU caches are always set to active, but with zero
+ * bandwidth allocated. It should be ok to allocate zero
+ * bandwidth for the caches, because DMA for other channels
+ * will supposedly finish, once their programmed amount is
+ * done, and then the caches will get access according to the
+ * "fixed scheme" for unclaimed slots. Though, if for some
+ * use-case somewhere, there's a maximum CPU latency for
+ * e.g. some interrupt, we have to start allocating specific
+ * bandwidth for the CPU caches too.
+ */
+ active_clients[EXT_REGION][10] = active_clients[EXT_REGION][11] = 1;
+ crisv32_arbiter_config(EXT_REGION, 0);
+ crisv32_arbiter_config(INT_REGION, 0);
+
+ if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, IRQF_DISABLED,
+ "arbiter", NULL))
+ printk(KERN_ERR "Couldn't allocate arbiter IRQ\n");
+
+#ifndef CONFIG_ETRAX_KGDB
+ /* Global watch for writes to kernel text segment. */
+ crisv32_arbiter_watch(virt_to_phys(&_stext), &_etext - &_stext,
+ arbiter_all_clients, arbiter_all_write, NULL);
+#endif
+}
+
+/* Main entry for bandwidth allocation. */
+
+int crisv32_arbiter_allocate_bandwidth(int client, int region,
+ unsigned long bandwidth)
+{
+ int i;
+ int total_assigned = 0;
+ int total_clients = 0;
+ int req;
+
+ crisv32_arbiter_init();
+
+ for (i = 0; i < NBR_OF_CLIENTS; i++) {
+ total_assigned += requested_slots[region][i];
+ total_clients += active_clients[region][i];
+ }
+
+ /* Avoid division by 0 for 0-bandwidth requests. */
+ req = bandwidth == 0
+ ? 0 : NBR_OF_SLOTS / (max_bandwidth[region] / bandwidth);
+
+ /*
+ * We make sure that there are enough slots only for non-zero
+ * requests. Requesting 0 bandwidth *may* allocate slots,
+ * though if all bandwidth is allocated, such a client won't
+ * get any and will have to rely on getting memory access
+ * according to the fixed scheme that's the default when one
+ * of the slot-allocated clients doesn't claim their slot.
+ */
+ if (total_assigned + req > NBR_OF_SLOTS)
+ return -ENOMEM;
+
+ active_clients[region][client] = 1;
+ requested_slots[region][client] = req;
+ crisv32_arbiter_config(region, NBR_OF_SLOTS - total_assigned);
+
+ return 0;
+}
+
+/*
+ * Main entry for bandwidth deallocation.
+ *
+ * Strictly speaking, for a somewhat constant set of clients where
+ * each client gets a constant bandwidth and is just enabled or
+ * disabled (somewhat dynamically), no action is necessary here to
+ * avoid starvation for non-zero-allocation clients, as the allocated
+ * slots will just be unused. However, handing out those unused slots
+ * to active clients avoids needless latency if the "fixed scheme"
+ * would give unclaimed slots to an eager low-index client.
+ */
+
+void crisv32_arbiter_deallocate_bandwidth(int client, int region)
+{
+ int i;
+ int total_assigned = 0;
+
+ requested_slots[region][client] = 0;
+ active_clients[region][client] = 0;
+
+ for (i = 0; i < NBR_OF_CLIENTS; i++)
+ total_assigned += requested_slots[region][i];
+
+ crisv32_arbiter_config(region, NBR_OF_SLOTS - total_assigned);
+}
+
+int crisv32_arbiter_watch(unsigned long start, unsigned long size,
+ unsigned long clients, unsigned long accesses,
+ watch_callback *cb)
+{
+ int i;
+
+ crisv32_arbiter_init();
+
+ if (start > 0x80000000) {
+ printk(KERN_ERR "Arbiter: %lX doesn't look like a "
+ "physical address", start);
+ return -EFAULT;
+ }
+
+ spin_lock(&arbiter_lock);
+
+ for (i = 0; i < NUMBER_OF_BP; i++) {
+ if (!watches[i].used) {
+ reg_marb_rw_intr_mask intr_mask =
+ REG_RD(marb, regi_marb, rw_intr_mask);
+
+ watches[i].used = 1;
+ watches[i].start = start;
+ watches[i].end = start + size;
+ watches[i].cb = cb;
+
+ REG_WR_INT(marb_bp, watches[i].instance, rw_first_addr,
+ watches[i].start);
+ REG_WR_INT(marb_bp, watches[i].instance, rw_last_addr,
+ watches[i].end);
+ REG_WR_INT(marb_bp, watches[i].instance, rw_op,
+ accesses);
+ REG_WR_INT(marb_bp, watches[i].instance, rw_clients,
+ clients);
+
+ if (i == 0)
+ intr_mask.bp0 = regk_marb_yes;
+ else if (i == 1)
+ intr_mask.bp1 = regk_marb_yes;
+ else if (i == 2)
+ intr_mask.bp2 = regk_marb_yes;
+ else if (i == 3)
+ intr_mask.bp3 = regk_marb_yes;
+
+ REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
+ spin_unlock(&arbiter_lock);
+
+ return i;
+ }
+ }
+ spin_unlock(&arbiter_lock);
+ return -ENOMEM;
+}
+
+int crisv32_arbiter_unwatch(int id)
+{
+ reg_marb_rw_intr_mask intr_mask = REG_RD(marb, regi_marb, rw_intr_mask);
+
+ crisv32_arbiter_init();
+
+ spin_lock(&arbiter_lock);
+
+ if ((id < 0) || (id >= NUMBER_OF_BP) || (!watches[id].used)) {
+ spin_unlock(&arbiter_lock);
+ return -EINVAL;
+ }
+
+ memset(&watches[id], 0, sizeof(struct crisv32_watch_entry));
+
+ if (id == 0)
+ intr_mask.bp0 = regk_marb_no;
+ else if (id == 1)
+ intr_mask.bp2 = regk_marb_no;
+ else if (id == 2)
+ intr_mask.bp2 = regk_marb_no;
+ else if (id == 3)
+ intr_mask.bp3 = regk_marb_no;
+
+ REG_WR(marb, regi_marb, rw_intr_mask, intr_mask);
+
+ spin_unlock(&arbiter_lock);
+ return 0;
+}
+
+extern void show_registers(struct pt_regs *regs);
+
+static irqreturn_t crisv32_arbiter_irq(int irq, void *dev_id)
+{
+ reg_marb_r_masked_intr masked_intr =
+ REG_RD(marb, regi_marb, r_masked_intr);
+ reg_marb_bp_r_brk_clients r_clients;
+ reg_marb_bp_r_brk_addr r_addr;
+ reg_marb_bp_r_brk_op r_op;
+ reg_marb_bp_r_brk_first_client r_first;
+ reg_marb_bp_r_brk_size r_size;
+ reg_marb_bp_rw_ack ack = { 0 };
+ reg_marb_rw_ack_intr ack_intr = {
+ .bp0 = 1, .bp1 = 1, .bp2 = 1, .bp3 = 1
+ };
+ struct crisv32_watch_entry *watch;
+
+ if (masked_intr.bp0) {
+ watch = &watches[0];
+ ack_intr.bp0 = regk_marb_yes;
+ } else if (masked_intr.bp1) {
+ watch = &watches[1];
+ ack_intr.bp1 = regk_marb_yes;
+ } else if (masked_intr.bp2) {
+ watch = &watches[2];
+ ack_intr.bp2 = regk_marb_yes;
+ } else if (masked_intr.bp3) {
+ watch = &watches[3];
+ ack_intr.bp3 = regk_marb_yes;
+ } else {
+ return IRQ_NONE;
+ }
+
+ /* Retrieve all useful information and print it. */
+ r_clients = REG_RD(marb_bp, watch->instance, r_brk_clients);
+ r_addr = REG_RD(marb_bp, watch->instance, r_brk_addr);
+ r_op = REG_RD(marb_bp, watch->instance, r_brk_op);
+ r_first = REG_RD(marb_bp, watch->instance, r_brk_first_client);
+ r_size = REG_RD(marb_bp, watch->instance, r_brk_size);
+
+ printk(KERN_INFO "Arbiter IRQ\n");
+ printk(KERN_INFO "Clients %X addr %X op %X first %X size %X\n",
+ REG_TYPE_CONV(int, reg_marb_bp_r_brk_clients, r_clients),
+ REG_TYPE_CONV(int, reg_marb_bp_r_brk_addr, r_addr),
+ REG_TYPE_CONV(int, reg_marb_bp_r_brk_op, r_op),
+ REG_TYPE_CONV(int, reg_marb_bp_r_brk_first_client, r_first),
+ REG_TYPE_CONV(int, reg_marb_bp_r_brk_size, r_size));
+
+ REG_WR(marb_bp, watch->instance, rw_ack, ack);
+ REG_WR(marb, regi_marb, rw_ack_intr, ack_intr);
+
+ printk(KERN_INFO "IRQ occured at %lX\n", get_irq_regs()->erp);
+
+ if (watch->cb)
+ watch->cb();
+
+ return IRQ_HANDLED;
+}
--- /dev/null
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/cpufreq.h>
+#include <hwregs/reg_map.h>
+#include <asm/arch/hwregs/reg_rdwr.h>
+#include <asm/arch/hwregs/config_defs.h>
+#include <asm/arch/hwregs/bif_core_defs.h>
+
+static int
+cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
+ void *data);
+
+static struct notifier_block cris_sdram_freq_notifier_block = {
+ .notifier_call = cris_sdram_freq_notifier
+};
+
+static struct cpufreq_frequency_table cris_freq_table[] = {
+ {0x01, 6000},
+ {0x02, 200000},
+ {0, CPUFREQ_TABLE_END},
+};
+
+static unsigned int cris_freq_get_cpu_frequency(unsigned int cpu)
+{
+ reg_config_rw_clk_ctrl clk_ctrl;
+ clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
+ return clk_ctrl.pll ? 200000 : 6000;
+}
+
+static void cris_freq_set_cpu_state(unsigned int state)
+{
+ int i;
+ struct cpufreq_freqs freqs;
+ reg_config_rw_clk_ctrl clk_ctrl;
+ clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
+
+ for_each_possible_cpu(i) {
+ freqs.old = cris_freq_get_cpu_frequency(i);
+ freqs.new = cris_freq_table[state].frequency;
+ freqs.cpu = i;
+ }
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+ local_irq_disable();
+
+ /* Even though we may be SMP they will share the same clock
+ * so all settings are made on CPU0. */
+ if (cris_freq_table[state].frequency == 200000)
+ clk_ctrl.pll = 1;
+ else
+ clk_ctrl.pll = 0;
+ REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
+
+ local_irq_enable();
+
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+};
+
+static int cris_freq_verify(struct cpufreq_policy *policy)
+{
+ return cpufreq_frequency_table_verify(policy, &cris_freq_table[0]);
+}
+
+static int cris_freq_target(struct cpufreq_policy *policy,
+ unsigned int target_freq, unsigned int relation)
+{
+ unsigned int newstate = 0;
+
+ if (cpufreq_frequency_table_target
+ (policy, cris_freq_table, target_freq, relation, &newstate))
+ return -EINVAL;
+
+ cris_freq_set_cpu_state(newstate);
+
+ return 0;
+}
+
+static int cris_freq_cpu_init(struct cpufreq_policy *policy)
+{
+ int result;
+
+ /* cpuinfo and default policy values */
+ policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+ policy->cpuinfo.transition_latency = 1000000; /* 1ms */
+ policy->cur = cris_freq_get_cpu_frequency(0);
+
+ result = cpufreq_frequency_table_cpuinfo(policy, cris_freq_table);
+ if (result)
+ return (result);
+
+ cpufreq_frequency_table_get_attr(cris_freq_table, policy->cpu);
+
+ return 0;
+}
+
+static int cris_freq_cpu_exit(struct cpufreq_policy *policy)
+{
+ cpufreq_frequency_table_put_attr(policy->cpu);
+ return 0;
+}
+
+static struct freq_attr *cris_freq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
+static struct cpufreq_driver cris_freq_driver = {
+ .get = cris_freq_get_cpu_frequency,
+ .verify = cris_freq_verify,
+ .target = cris_freq_target,
+ .init = cris_freq_cpu_init,
+ .exit = cris_freq_cpu_exit,
+ .name = "cris_freq",
+ .owner = THIS_MODULE,
+ .attr = cris_freq_attr,
+};
+
+static int __init cris_freq_init(void)
+{
+ int ret;
+ ret = cpufreq_register_driver(&cris_freq_driver);
+ cpufreq_register_notifier(&cris_sdram_freq_notifier_block,
+ CPUFREQ_TRANSITION_NOTIFIER);
+ return ret;
+}
+
+static int
+cris_sdram_freq_notifier(struct notifier_block *nb, unsigned long val,
+ void *data)
+{
+ int i;
+ struct cpufreq_freqs *freqs = data;
+ if (val == CPUFREQ_PRECHANGE) {
+ reg_bif_core_rw_sdram_timing timing =
+ REG_RD(bif_core, regi_bif_core, rw_sdram_timing);
+ timing.cpd = (freqs->new == 200000 ? 0 : 1);
+
+ if (freqs->new == 200000)
+ for (i = 0; i < 50000; i++) ;
+ REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing);
+ }
+ return 0;
+}
+
+module_init(cris_freq_init);
#include <linux/kernel.h>
#include <linux/spinlock.h>
#include <asm/dma.h>
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/marb_defs.h>
-#include <asm/arch/hwregs/config_defs.h>
-#include <asm/arch/hwregs/strmux_defs.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/marb_defs.h>
+#include <hwregs/config_defs.h>
+#include <hwregs/strmux_defs.h>
#include <linux/errno.h>
#include <asm/system.h>
-#include <asm/arch/arbiter.h>
+#include <asm/arch/mach/arbiter.h>
static char used_dma_channels[MAX_DMA_CHANNELS];
-static const char * used_dma_channels_users[MAX_DMA_CHANNELS];
+static const char *used_dma_channels_users[MAX_DMA_CHANNELS];
static DEFINE_SPINLOCK(dma_lock);
-int crisv32_request_dma(unsigned int dmanr, const char * device_id,
- unsigned options, unsigned int bandwidth,
+int crisv32_request_dma(unsigned int dmanr, const char *device_id,
+ unsigned options, unsigned int bandwidth,
enum dma_owner owner)
{
unsigned long flags;
reg_config_rw_clk_ctrl clk_ctrl;
reg_strmux_rw_cfg strmux_cfg;
- if (crisv32_arbiter_allocate_bandwidth(dmanr,
- options & DMA_INT_MEM ? INT_REGION : EXT_REGION,
- bandwidth))
- return -ENOMEM;
+ if (crisv32_arbiter_allocate_bandwidth(dmanr,
+ options & DMA_INT_MEM ?
+ INT_REGION : EXT_REGION,
+ bandwidth))
+ return -ENOMEM;
spin_lock_irqsave(&dma_lock, flags);
if (used_dma_channels[dmanr]) {
spin_unlock_irqrestore(&dma_lock, flags);
if (options & DMA_VERBOSE_ON_ERROR) {
- printk("Failed to request DMA %i for %s, already allocated by %s\n", dmanr, device_id, used_dma_channels_users[dmanr]);
+ printk(KERN_ERR "Failed to request DMA %i for %s, "
+ "already allocated by %s\n",
+ dmanr,
+ device_id,
+ used_dma_channels_users[dmanr]);
}
if (options & DMA_PANIC_ON_ERROR)
panic("request_dma error!");
+ spin_unlock_irqrestore(&dma_lock, flags);
return -EBUSY;
}
clk_ctrl = REG_RD(config, regi_config, rw_clk_ctrl);
strmux_cfg = REG_RD(strmux, regi_strmux, rw_cfg);
- switch(dmanr)
- {
+ switch (dmanr) {
case 0:
case 1:
clk_ctrl.dma01_eth0 = 1;
default:
spin_unlock_irqrestore(&dma_lock, flags);
if (options & DMA_VERBOSE_ON_ERROR) {
- printk("Failed to request DMA %i for %s, only 0-%i valid)\n", dmanr, device_id, MAX_DMA_CHANNELS-1);
+ printk(KERN_ERR "Failed to request DMA %i for %s, "
+ "only 0-%i valid)\n",
+ dmanr, device_id, MAX_DMA_CHANNELS - 1);
}
if (options & DMA_PANIC_ON_ERROR)
return -EINVAL;
}
- switch(owner)
- {
+ switch (owner) {
case dma_eth0:
if (dmanr == 0)
strmux_cfg.dma0 = regk_strmux_eth0;
used_dma_channels_users[dmanr] = device_id;
REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl);
REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg);
- spin_unlock_irqrestore(&dma_lock,flags);
+ spin_unlock_irqrestore(&dma_lock, flags);
return 0;
}
-/* $Id: dram_init.S,v 1.4 2005/04/24 18:48:32 starvik Exp $
- *
+/*
* DRAM/SDRAM initialization - alter with care
* This file is intended to be included from other assembler files
*
* Note: This file may not modify r8 or r9 because they are used to
* carry information from the decompresser to the kernel
*
- * Copyright (C) 2000-2003 Axis Communications AB
+ * Copyright (C) 2000-2007 Axis Communications AB
*
- * Authors: Mikael Starvik (starvik@axis.com)
+ * Authors: Mikael Starvik <starvik@axis.com>
*/
/* Just to be certain the config file is included, we include it here
- * explicitly instead of depending on it being included in the file that
+ * explicitely instead of depending on it being included in the file that
* uses this code.
*/
-#include <asm/arch/hwregs/asm/reg_map_asm.h>
-#include <asm/arch/hwregs/asm/bif_core_defs_asm.h>
+#include <hwregs/asm/reg_map_asm.h>
+#include <hwregs/asm/bif_core_defs_asm.h>
;; WARNING! The registers r8 and r9 are used as parameters carrying
;; information from the decompressor (if the kernel was compressed).
move.d 0x40, $r4 ; Assume 32 bits and CAS latency = 2
move.d CONFIG_ETRAX_SDRAM_TIMING, $r1
- and.d 0x07, $r1 ; Get CAS latency
+ and.d 0x07, $r1 ; Get CAS latency
cmpq 2, $r1 ; CL = 2 ?
beq _bw_check
nop
subq 1, $r2
; Issue initialization command sequence
- move.d _sdram_commands_start, $r2
- and.d 0x000fffff, $r2 ; Make sure commands are read from flash
- move.d _sdram_commands_end, $r3
- and.d 0x000fffff, $r3
+ lapc _sdram_commands_start, $r2
+ lapc _sdram_commands_end, $r3
1: clear.d $r6
- move.b [$r2+], $r6 ; Load command
+ move.b [$r2+], $r6 ; Load command
or.d $r4, $r6 ; Add calculated mrs
move.d $r6, [$r5] ; Write rw_sdram_cmd
; Wait 80 ns between each command
/*
- * $Id: hw_settings.S,v 1.3 2005/04/24 18:36:57 starvik Exp $
- *
* This table is used by some tools to extract hardware parameters.
* The table should be included in the kernel and the decompressor.
* Don't forget to update the tools if you change this table.
*
- * Copyright (C) 2001 Axis Communications AB
+ * Copyright (C) 2001-2007 Axis Communications AB
*
- * Authors: Mikael Starvik (starvik@axis.com)
+ * Authors: Mikael Starvik <starvik@axis.com>
*/
-#include <asm/arch/hwregs/asm/reg_map_asm.h>
-#include <asm/arch/hwregs/asm/bif_core_defs_asm.h>
-#include <asm/arch/hwregs/asm/gio_defs_asm.h>
+#include <hwregs/asm/reg_map_asm.h>
+#include <hwregs/asm/bif_core_defs_asm.h>
+#include <hwregs/asm/gio_defs_asm.h>
.ascii "HW_PARAM_MAGIC" ; Magic number
.dword 0xc0004000 ; Kernel start address
--- /dev/null
+/*
+ * Helper functions for I/O pins.
+ *
+ * Copyright (c) 2004-2007 Axis Communications AB.
+ */
+
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <asm/io.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/hwregs/gio_defs.h>
+
+#ifndef DEBUG
+#define DEBUG(x)
+#endif
+
+struct crisv32_ioport crisv32_ioports[] = {
+ {
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_oe),
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pa_dout),
+ (unsigned long *)REG_ADDR(gio, regi_gio, r_pa_din),
+ 8
+ },
+ {
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_oe),
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pb_dout),
+ (unsigned long *)REG_ADDR(gio, regi_gio, r_pb_din),
+ 18
+ },
+ {
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_oe),
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pc_dout),
+ (unsigned long *)REG_ADDR(gio, regi_gio, r_pc_din),
+ 18
+ },
+ {
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_oe),
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pd_dout),
+ (unsigned long *)REG_ADDR(gio, regi_gio, r_pd_din),
+ 18
+ },
+ {
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_oe),
+ (unsigned long *)REG_ADDR(gio, regi_gio, rw_pe_dout),
+ (unsigned long *)REG_ADDR(gio, regi_gio, r_pe_din),
+ 18
+ }
+};
+
+#define NBR_OF_PORTS sizeof(crisv32_ioports)/sizeof(struct crisv32_ioport)
+
+struct crisv32_iopin crisv32_led_net0_green;
+struct crisv32_iopin crisv32_led_net0_red;
+struct crisv32_iopin crisv32_led_net1_green;
+struct crisv32_iopin crisv32_led_net1_red;
+struct crisv32_iopin crisv32_led2_green;
+struct crisv32_iopin crisv32_led2_red;
+struct crisv32_iopin crisv32_led3_green;
+struct crisv32_iopin crisv32_led3_red;
+
+/* Dummy port used when green LED and red LED is on the same bit */
+static unsigned long io_dummy;
+static struct crisv32_ioport dummy_port = {
+ &io_dummy,
+ &io_dummy,
+ &io_dummy,
+ 18
+};
+static struct crisv32_iopin dummy_led = {
+ &dummy_port,
+ 0
+};
+
+static int __init crisv32_io_init(void)
+{
+ int ret = 0;
+
+ u32 i;
+
+ /* Locks *should* be dynamically initialized. */
+ for (i = 0; i < ARRAY_SIZE(crisv32_ioports); i++)
+ spin_lock_init(&crisv32_ioports[i].lock);
+ spin_lock_init(&dummy_port.lock);
+
+ /* Initialize LEDs */
+#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
+ ret +=
+ crisv32_io_get_name(&crisv32_led_net0_green,
+ CONFIG_ETRAX_LED_G_NET0);
+ crisv32_io_set_dir(&crisv32_led_net0_green, crisv32_io_dir_out);
+ if (strcmp(CONFIG_ETRAX_LED_G_NET0, CONFIG_ETRAX_LED_R_NET0)) {
+ ret +=
+ crisv32_io_get_name(&crisv32_led_net0_red,
+ CONFIG_ETRAX_LED_R_NET0);
+ crisv32_io_set_dir(&crisv32_led_net0_red, crisv32_io_dir_out);
+ } else
+ crisv32_led_net0_red = dummy_led;
+#endif
+
+#ifdef CONFIG_ETRAX_NBR_LED_GRP_TWO
+ ret +=
+ crisv32_io_get_name(&crisv32_led_net1_green,
+ CONFIG_ETRAX_LED_G_NET1);
+ crisv32_io_set_dir(&crisv32_led_net1_green, crisv32_io_dir_out);
+ if (strcmp(CONFIG_ETRAX_LED_G_NET1, CONFIG_ETRAX_LED_R_NET1)) {
+ crisv32_io_get_name(&crisv32_led_net1_red,
+ CONFIG_ETRAX_LED_R_NET1);
+ crisv32_io_set_dir(&crisv32_led_net1_red, crisv32_io_dir_out);
+ } else
+ crisv32_led_net1_red = dummy_led;
+#endif
+
+ ret += crisv32_io_get_name(&crisv32_led2_green, CONFIG_ETRAX_V32_LED2G);
+ ret += crisv32_io_get_name(&crisv32_led2_red, CONFIG_ETRAX_V32_LED2R);
+ ret += crisv32_io_get_name(&crisv32_led3_green, CONFIG_ETRAX_V32_LED3G);
+ ret += crisv32_io_get_name(&crisv32_led3_red, CONFIG_ETRAX_V32_LED3R);
+
+ crisv32_io_set_dir(&crisv32_led2_green, crisv32_io_dir_out);
+ crisv32_io_set_dir(&crisv32_led2_red, crisv32_io_dir_out);
+ crisv32_io_set_dir(&crisv32_led3_green, crisv32_io_dir_out);
+ crisv32_io_set_dir(&crisv32_led3_red, crisv32_io_dir_out);
+
+ return ret;
+}
+
+__initcall(crisv32_io_init);
+
+int crisv32_io_get(struct crisv32_iopin *iopin,
+ unsigned int port, unsigned int pin)
+{
+ if (port > NBR_OF_PORTS)
+ return -EINVAL;
+ if (port > crisv32_ioports[port].pin_count)
+ return -EINVAL;
+
+ iopin->bit = 1 << pin;
+ iopin->port = &crisv32_ioports[port];
+
+ /* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
+ /* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
+ if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
+ return -EIO;
+ DEBUG(printk(KERN_DEBUG "crisv32_io_get: Allocated pin %d on port %d\n",
+ pin, port));
+
+ return 0;
+}
+
+int crisv32_io_get_name(struct crisv32_iopin *iopin, const char *name)
+{
+ int port;
+ int pin;
+
+ if (toupper(*name) == 'P')
+ name++;
+
+ if (toupper(*name) < 'A' || toupper(*name) > 'E')
+ return -EINVAL;
+
+ port = toupper(*name) - 'A';
+ name++;
+ pin = simple_strtoul(name, NULL, 10);
+
+ if (pin < 0 || pin > crisv32_ioports[port].pin_count)
+ return -EINVAL;
+
+ iopin->bit = 1 << pin;
+ iopin->port = &crisv32_ioports[port];
+
+ /* Only allocate pinmux gpiopins if port != PORT_A (port 0) */
+ /* NOTE! crisv32_pinmux_alloc thinks PORT_B is port 0 */
+ if (port != 0 && crisv32_pinmux_alloc(port - 1, pin, pin, pinmux_gpio))
+ return -EIO;
+
+ DEBUG(printk(KERN_DEBUG
+ "crisv32_io_get_name: Allocated pin %d on port %d\n",
+ pin, port));
+
+ return 0;
+}
+
+#ifdef CONFIG_PCI
+/* PCI I/O access stuff */
+struct cris_io_operations *cris_iops = NULL;
+EXPORT_SYMBOL(cris_iops);
+#endif
--- /dev/null
+/*
+ * Allocator for I/O pins. All pins are allocated to GPIO at bootup.
+ * Unassigned pins and GPIO pins can be allocated to a fixed interface
+ * or the I/O processor instead.
+ *
+ * Copyright (c) 2004-2007 Axis Communications AB.
+ */
+
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/spinlock.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <pinmux.h>
+#include <hwregs/pinmux_defs.h>
+
+#undef DEBUG
+
+#define PORT_PINS 18
+#define PORTS 4
+
+static char pins[PORTS][PORT_PINS];
+static DEFINE_SPINLOCK(pinmux_lock);
+
+static void crisv32_pinmux_set(int port);
+
+int crisv32_pinmux_init(void)
+{
+ static int initialized;
+
+ if (!initialized) {
+ reg_pinmux_rw_pa pa = REG_RD(pinmux, regi_pinmux, rw_pa);
+ initialized = 1;
+ REG_WR_INT(pinmux, regi_pinmux, rw_hwprot, 0);
+ pa.pa0 = pa.pa1 = pa.pa2 = pa.pa3 =
+ pa.pa4 = pa.pa5 = pa.pa6 = pa.pa7 = regk_pinmux_yes;
+ REG_WR(pinmux, regi_pinmux, rw_pa, pa);
+ crisv32_pinmux_alloc(PORT_B, 0, PORT_PINS - 1, pinmux_gpio);
+ crisv32_pinmux_alloc(PORT_C, 0, PORT_PINS - 1, pinmux_gpio);
+ crisv32_pinmux_alloc(PORT_D, 0, PORT_PINS - 1, pinmux_gpio);
+ crisv32_pinmux_alloc(PORT_E, 0, PORT_PINS - 1, pinmux_gpio);
+ }
+
+ return 0;
+}
+
+int
+crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode)
+{
+ int i;
+ unsigned long flags;
+
+ crisv32_pinmux_init();
+
+ if (port > PORTS)
+ return -EINVAL;
+
+ spin_lock_irqsave(&pinmux_lock, flags);
+
+ for (i = first_pin; i <= last_pin; i++) {
+ if ((pins[port][i] != pinmux_none)
+ && (pins[port][i] != pinmux_gpio)
+ && (pins[port][i] != mode)) {
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+#ifdef DEBUG
+ panic("Pinmux alloc failed!\n");
+#endif
+ return -EPERM;
+ }
+ }
+
+ for (i = first_pin; i <= last_pin; i++)
+ pins[port][i] = mode;
+
+ crisv32_pinmux_set(port);
+
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+
+ return 0;
+}
+
+int crisv32_pinmux_alloc_fixed(enum fixed_function function)
+{
+ int ret = -EINVAL;
+ char saved[sizeof pins];
+ unsigned long flags;
+
+ spin_lock_irqsave(&pinmux_lock, flags);
+
+ /* Save internal data for recovery */
+ memcpy(saved, pins, sizeof pins);
+
+ crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */
+
+ reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
+
+ switch (function) {
+ case pinmux_ser1:
+ ret = crisv32_pinmux_alloc(PORT_C, 4, 7, pinmux_fixed);
+ hwprot.ser1 = regk_pinmux_yes;
+ break;
+ case pinmux_ser2:
+ ret = crisv32_pinmux_alloc(PORT_C, 8, 11, pinmux_fixed);
+ hwprot.ser2 = regk_pinmux_yes;
+ break;
+ case pinmux_ser3:
+ ret = crisv32_pinmux_alloc(PORT_C, 12, 15, pinmux_fixed);
+ hwprot.ser3 = regk_pinmux_yes;
+ break;
+ case pinmux_sser0:
+ ret = crisv32_pinmux_alloc(PORT_C, 0, 3, pinmux_fixed);
+ ret |= crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);
+ hwprot.sser0 = regk_pinmux_yes;
+ break;
+ case pinmux_sser1:
+ ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
+ hwprot.sser1 = regk_pinmux_yes;
+ break;
+ case pinmux_ata0:
+ ret = crisv32_pinmux_alloc(PORT_D, 5, 7, pinmux_fixed);
+ ret |= crisv32_pinmux_alloc(PORT_D, 15, 17, pinmux_fixed);
+ hwprot.ata0 = regk_pinmux_yes;
+ break;
+ case pinmux_ata1:
+ ret = crisv32_pinmux_alloc(PORT_D, 0, 4, pinmux_fixed);
+ ret |= crisv32_pinmux_alloc(PORT_E, 17, 17, pinmux_fixed);
+ hwprot.ata1 = regk_pinmux_yes;
+ break;
+ case pinmux_ata2:
+ ret = crisv32_pinmux_alloc(PORT_C, 11, 15, pinmux_fixed);
+ ret |= crisv32_pinmux_alloc(PORT_E, 3, 3, pinmux_fixed);
+ hwprot.ata2 = regk_pinmux_yes;
+ break;
+ case pinmux_ata3:
+ ret = crisv32_pinmux_alloc(PORT_C, 8, 10, pinmux_fixed);
+ ret |= crisv32_pinmux_alloc(PORT_C, 0, 2, pinmux_fixed);
+ hwprot.ata2 = regk_pinmux_yes;
+ break;
+ case pinmux_ata:
+ ret = crisv32_pinmux_alloc(PORT_B, 0, 15, pinmux_fixed);
+ ret |= crisv32_pinmux_alloc(PORT_D, 8, 15, pinmux_fixed);
+ hwprot.ata = regk_pinmux_yes;
+ break;
+ case pinmux_eth1:
+ ret = crisv32_pinmux_alloc(PORT_E, 0, 17, pinmux_fixed);
+ hwprot.eth1 = regk_pinmux_yes;
+ hwprot.eth1_mgm = regk_pinmux_yes;
+ break;
+ case pinmux_timer:
+ ret = crisv32_pinmux_alloc(PORT_C, 16, 16, pinmux_fixed);
+ hwprot.timer = regk_pinmux_yes;
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+ return ret;
+ }
+
+ if (!ret)
+ REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
+ else
+ memcpy(pins, saved, sizeof pins);
+
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+
+ return ret;
+}
+
+void crisv32_pinmux_set(int port)
+{
+ int i;
+ int gpio_val = 0;
+ int iop_val = 0;
+
+ for (i = 0; i < PORT_PINS; i++) {
+ if (pins[port][i] == pinmux_gpio)
+ gpio_val |= (1 << i);
+ else if (pins[port][i] == pinmux_iop)
+ iop_val |= (1 << i);
+ }
+
+ REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_gio + 8 * port,
+ gpio_val);
+ REG_WRITE(int, regi_pinmux + REG_RD_ADDR_pinmux_rw_pb_iop + 8 * port,
+ iop_val);
+
+#ifdef DEBUG
+ crisv32_pinmux_dump();
+#endif
+}
+
+int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
+{
+ int i;
+ unsigned long flags;
+
+ crisv32_pinmux_init();
+
+ if (port > PORTS)
+ return -EINVAL;
+
+ spin_lock_irqsave(&pinmux_lock, flags);
+
+ for (i = first_pin; i <= last_pin; i++)
+ pins[port][i] = pinmux_none;
+
+ crisv32_pinmux_set(port);
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+
+ return 0;
+}
+
+int crisv32_pinmux_dealloc_fixed(enum fixed_function function)
+{
+ int ret = -EINVAL;
+ char saved[sizeof pins];
+ unsigned long flags;
+
+ spin_lock_irqsave(&pinmux_lock, flags);
+
+ /* Save internal data for recovery */
+ memcpy(saved, pins, sizeof pins);
+
+ crisv32_pinmux_init(); /* Must be done before we read rw_hwprot */
+
+ reg_pinmux_rw_hwprot hwprot = REG_RD(pinmux, regi_pinmux, rw_hwprot);
+
+ switch (function) {
+ case pinmux_ser1:
+ ret = crisv32_pinmux_dealloc(PORT_C, 4, 7);
+ hwprot.ser1 = regk_pinmux_no;
+ break;
+ case pinmux_ser2:
+ ret = crisv32_pinmux_dealloc(PORT_C, 8, 11);
+ hwprot.ser2 = regk_pinmux_no;
+ break;
+ case pinmux_ser3:
+ ret = crisv32_pinmux_dealloc(PORT_C, 12, 15);
+ hwprot.ser3 = regk_pinmux_no;
+ break;
+ case pinmux_sser0:
+ ret = crisv32_pinmux_dealloc(PORT_C, 0, 3);
+ ret |= crisv32_pinmux_dealloc(PORT_C, 16, 16);
+ hwprot.sser0 = regk_pinmux_no;
+ break;
+ case pinmux_sser1:
+ ret = crisv32_pinmux_dealloc(PORT_D, 0, 4);
+ hwprot.sser1 = regk_pinmux_no;
+ break;
+ case pinmux_ata0:
+ ret = crisv32_pinmux_dealloc(PORT_D, 5, 7);
+ ret |= crisv32_pinmux_dealloc(PORT_D, 15, 17);
+ hwprot.ata0 = regk_pinmux_no;
+ break;
+ case pinmux_ata1:
+ ret = crisv32_pinmux_dealloc(PORT_D, 0, 4);
+ ret |= crisv32_pinmux_dealloc(PORT_E, 17, 17);
+ hwprot.ata1 = regk_pinmux_no;
+ break;
+ case pinmux_ata2:
+ ret = crisv32_pinmux_dealloc(PORT_C, 11, 15);
+ ret |= crisv32_pinmux_dealloc(PORT_E, 3, 3);
+ hwprot.ata2 = regk_pinmux_no;
+ break;
+ case pinmux_ata3:
+ ret = crisv32_pinmux_dealloc(PORT_C, 8, 10);
+ ret |= crisv32_pinmux_dealloc(PORT_C, 0, 2);
+ hwprot.ata2 = regk_pinmux_no;
+ break;
+ case pinmux_ata:
+ ret = crisv32_pinmux_dealloc(PORT_B, 0, 15);
+ ret |= crisv32_pinmux_dealloc(PORT_D, 8, 15);
+ hwprot.ata = regk_pinmux_no;
+ break;
+ case pinmux_eth1:
+ ret = crisv32_pinmux_dealloc(PORT_E, 0, 17);
+ hwprot.eth1 = regk_pinmux_no;
+ hwprot.eth1_mgm = regk_pinmux_no;
+ break;
+ case pinmux_timer:
+ ret = crisv32_pinmux_dealloc(PORT_C, 16, 16);
+ hwprot.timer = regk_pinmux_no;
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+ return ret;
+ }
+
+ if (!ret)
+ REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot);
+ else
+ memcpy(pins, saved, sizeof pins);
+
+ spin_unlock_irqrestore(&pinmux_lock, flags);
+
+ return ret;
+}
+
+void crisv32_pinmux_dump(void)
+{
+ int i, j;
+
+ crisv32_pinmux_init();
+
+ for (i = 0; i < PORTS; i++) {
+ printk(KERN_DEBUG "Port %c\n", 'B' + i);
+ for (j = 0; j < PORT_PINS; j++)
+ printk(KERN_DEBUG " Pin %d = %d\n", j, pins[i][j]);
+ }
+}
+
+__initcall(crisv32_pinmux_init);
--- /dev/null
+/*
+ * Call simulator hook. This is the part running in the
+ * simulated program.
+ */
+
+#include "vcs_hook.h"
+#include <stdarg.h>
+#include <asm/arch-v32/hwregs/reg_map.h>
+#include <asm/arch-v32/hwregs/intr_vect_defs.h>
+
+#define HOOK_TRIG_ADDR 0xb7000000 /* hook cvlog model reg address */
+#define HOOK_MEM_BASE_ADDR 0xa0000000 /* csp4 (shared mem) base addr */
+
+#define HOOK_DATA(offset) ((unsigned *)HOOK_MEM_BASE_ADDR)[offset]
+#define VHOOK_DATA(offset) ((volatile unsigned *)HOOK_MEM_BASE_ADDR)[offset]
+#define HOOK_TRIG(funcid) \
+ do { \
+ *((unsigned *) HOOK_TRIG_ADDR) = funcid; \
+ } while (0)
+#define HOOK_DATA_BYTE(offset) ((unsigned char *)HOOK_MEM_BASE_ADDR)[offset]
+
+int hook_call(unsigned id, unsigned pcnt, ...)
+{
+ va_list ap;
+ unsigned i;
+ unsigned ret;
+#ifdef USING_SOS
+ PREEMPT_OFF_SAVE();
+#endif
+
+ /* pass parameters */
+ HOOK_DATA(0) = id;
+
+ /* Have to make hook_print_str a special case since we call with a
+ * parameter of byte type. Should perhaps be a separate
+ * hook_call. */
+
+ if (id == hook_print_str) {
+ int i;
+ char *str;
+
+ HOOK_DATA(1) = pcnt;
+
+ va_start(ap, pcnt);
+ str = (char *)va_arg(ap, unsigned);
+
+ for (i = 0; i != pcnt; i++)
+ HOOK_DATA_BYTE(8 + i) = str[i];
+
+ HOOK_DATA_BYTE(8 + i) = 0; /* null byte */
+ } else {
+ va_start(ap, pcnt);
+ for (i = 1; i <= pcnt; i++)
+ HOOK_DATA(i) = va_arg(ap, unsigned);
+ va_end(ap);
+ }
+
+ /* read from mem to make sure data has propagated to memory before
+ * trigging */
+ ret = *((volatile unsigned *)HOOK_MEM_BASE_ADDR);
+
+ /* trigger hook */
+ HOOK_TRIG(id);
+
+ /* wait for call to finish */
+ while (VHOOK_DATA(0) > 0) ;
+
+ /* extract return value */
+
+ ret = VHOOK_DATA(1);
+
+#ifdef USING_SOS
+ PREEMPT_RESTORE();
+#endif
+ return ret;
+}
+
+unsigned hook_buf(unsigned i)
+{
+ return (HOOK_DATA(i));
+}
+
+void print_str(const char *str)
+{
+ int i;
+ /* find null at end of string */
+ for (i = 1; str[i]; i++) ;
+ hook_call(hook_print_str, i, str);
+}
+
+void CPU_KICK_DOG(void)
+{
+ (void)hook_call(hook_kick_dog, 0);
+}
+
+void CPU_WATCHDOG_TIMEOUT(unsigned t)
+{
+ (void)hook_call(hook_dog_timeout, 1, t);
+}
+
-// $Id: vcs_hook.h,v 1.1 2003/08/12 12:01:06 starvik Exp $
-//
-// Call simulator hook functions
+/*
+ * Call simulator hook functions
+ */
#ifndef HOOK_H
#define HOOK_H
-int hook_call( unsigned id, unsigned pcnt, ...);
+int hook_call(unsigned id, unsigned pcnt, ...);
enum hook_ids {
hook_debug_on = 1,
# Makefile for the Linux/cris parts of the memory manager.
-obj-y := mmu.o init.o tlb.o intmem.o
+obj-y += mmu.o init.o tlb.o intmem.o
+obj-$(CONFIG_ETRAX_L2CACHE) += l2cache.o
REG_STATE(mmu, rw_mm_cfg, seg_d, page) |
REG_STATE(mmu, rw_mm_cfg, seg_c, linear) |
REG_STATE(mmu, rw_mm_cfg, seg_b, linear) |
-#ifndef CONFIG_ETRAXFS_SIM
+#ifndef CONFIG_ETRAX_VCS_SIM
REG_STATE(mmu, rw_mm_cfg, seg_a, page) |
#else
REG_STATE(mmu, rw_mm_cfg, seg_a, linear) |
mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) |
REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) |
REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) |
-#ifndef CONFIG_ETRAXFS_SIM
REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) |
-#else
- REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x0) |
-#endif
REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) |
-#ifndef CONFIG_ETRAXFS_SIM
+#ifndef CONFIG_ETRAX_VCS_SIM
REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) |
#else
REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa) |
#include <linux/list.h>
#include <linux/slab.h>
#include <asm/io.h>
-#include <asm/arch/memmap.h>
+#include <memmap.h>
#define STATUS_FREE 0
#define STATUS_ALLOCATED 1
+#ifdef CONFIG_ETRAX_L2CACHE
+#define RESERVED_SIZE 66*1024
+#else
+#define RESERVED_SIZE 0
+#endif
+
struct intmem_allocation {
struct list_head entry;
unsigned int size;
struct intmem_allocation* alloc =
(struct intmem_allocation*)kmalloc(sizeof *alloc, GFP_KERNEL);
INIT_LIST_HEAD(&intmem_allocations);
- intmem_virtual = ioremap(MEM_INTMEM_START, MEM_INTMEM_SIZE);
+ intmem_virtual = ioremap(MEM_INTMEM_START + RESERVED_SIZE,
+ MEM_INTMEM_SIZE - RESERVED_SIZE);
initiated = 1;
- alloc->size = MEM_INTMEM_SIZE;
+ alloc->size = MEM_INTMEM_SIZE - RESERVED_SIZE;
alloc->offset = 0;
alloc->status = STATUS_FREE;
list_add_tail(&alloc->entry, &intmem_allocations);
(struct intmem_allocation*)
kmalloc(sizeof *alloc, GFP_ATOMIC);
alloc->status = STATUS_FREE;
- alloc->size = allocation->size - size - alignment;
- alloc->offset = allocation->offset + size;
+ alloc->size = allocation->size - size -
+ alignment;
+ alloc->offset = allocation->offset + size +
+ alignment;
list_add(&alloc->entry, &allocation->entry);
if (alignment) {
- struct intmem_allocation* tmp;
- tmp = (struct intmem_allocation*)
- kmalloc(sizeof *tmp, GFP_ATOMIC);
+ struct intmem_allocation *tmp;
+ tmp = (struct intmem_allocation *)
+ kmalloc(sizeof *tmp,
+ GFP_ATOMIC);
tmp->offset = allocation->offset;
tmp->size = alignment;
tmp->status = STATUS_FREE;
allocation->offset += alignment;
- list_add_tail(&tmp->entry, &allocation->entry);
+ list_add_tail(&tmp->entry,
+ &allocation->entry);
}
}
allocation->status = STATUS_ALLOCATED;
list_for_each_entry_safe(allocation, tmp, &intmem_allocations, entry) {
if (allocation->offset == (int)(addr - intmem_virtual)) {
- struct intmem_allocation* prev =
+ struct intmem_allocation *prev =
list_entry(allocation->entry.prev,
struct intmem_allocation, entry);
- struct intmem_allocation* next =
+ struct intmem_allocation *next =
list_entry(allocation->entry.next,
struct intmem_allocation, entry);
allocation->status = STATUS_FREE;
/* Join with prev and/or next if also free */
- if (prev->status == STATUS_FREE) {
+ if ((prev != &intmem_allocations) &&
+ (prev->status == STATUS_FREE)) {
prev->size += allocation->size;
list_del(&allocation->entry);
kfree(allocation);
allocation = prev;
}
- if (next->status == STATUS_FREE) {
+ if ((next != &intmem_allocations) &&
+ (next->status == STATUS_FREE)) {
allocation->size += next->size;
list_del(&next->entry);
kfree(next);
void* crisv32_intmem_phys_to_virt(unsigned long addr)
{
- return (void*)(addr - MEM_INTMEM_START+
- (unsigned long)intmem_virtual);
+ return (void *)(addr - (MEM_INTMEM_START + RESERVED_SIZE) +
+ (unsigned long)intmem_virtual);
}
unsigned long crisv32_intmem_virt_to_phys(void* addr)
{
return (unsigned long)((unsigned long )addr -
- (unsigned long)intmem_virtual + MEM_INTMEM_START);
+ (unsigned long)intmem_virtual + MEM_INTMEM_START +
+ RESERVED_SIZE);
}
-
+module_init(crisv32_intmem_init);
--- /dev/null
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <memmap.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/l2cache_defs.h>
+#include <asm/io.h>
+
+#define L2CACHE_SIZE 64
+
+int __init l2cache_init(void)
+{
+ reg_l2cache_rw_ctrl ctrl = {0};
+ reg_l2cache_rw_cfg cfg = {.en = regk_l2cache_yes};
+
+ ctrl.csize = L2CACHE_SIZE;
+ ctrl.cbase = L2CACHE_SIZE / 4 + (L2CACHE_SIZE % 4 ? 1 : 0);
+ REG_WR(l2cache, regi_l2cache, rw_ctrl, ctrl);
+
+ /* Flush the tag memory */
+ memset((void *)(MEM_INTMEM_START | MEM_NON_CACHEABLE), 0, 2*1024);
+
+ /* Enable the cache */
+ REG_WR(l2cache, regi_l2cache, rw_cfg, cfg);
+
+ return 0;
+}
+
+; WARNING : The refill handler has been modified, see below !!!
+
/*
* Copyright (C) 2003 Axis Communications AB
*
; Note that the code is optimized to minimize stalls (makes the code harder
; to read).
;
+; WARNING !!!
+; Modified by Mikael Asker 060725: added a workaround for strange TLB
+; behavior. If the same PTE is present in more than one set, the TLB
+; doesn't recognize it and we get stuck in a loop of refill exceptions.
+; The workaround detects such loops and exits them by flushing
+; the TLB contents. The problem and workaround were verified
+; in VCS by Mikael Starvik.
+;
; Each page is 8 KB. Each PMD holds 8192/4 PTEs (each PTE is 4 bytes) so each
; PMD holds 16 MB of virtual memory.
; Bits 0-12 : Offset within a page
; Bits 24-31 : PMD offset within the PGD
.macro MMU_REFILL_HANDLER handler, mmu
+ .data
+1: .dword 0 ; refill_count
+ ; == 0 <=> last_refill_cause is invalid
+2: .dword 0 ; last_refill_cause
+ .text
.globl \handler
\handler:
subq 4, $sp
subq 4, $sp
move \mmu, $srs ; Select MMU support register bank
move.d $acr, [$sp]
- subq 4, $sp
- move.d $r0, [$sp]
+ subq 12, $sp
+ move.d 1b, $acr ; Point to refill_count
+ movem $r2, [$sp]
+
+ test.d [$acr] ; refill_count == 0 ?
+ beq 5f ; yes, last_refill_cause is invalid
+ move.d $acr, $r1
+
+ ; last_refill_cause is valid, investigate cause
+ addq 4, $r1 ; Point to last_refill_cause
+ move $s3, $r0 ; Get rw_mm_cause
+ move.d [$r1], $r2 ; Get last_refill_cause
+ cmp.d $r0, $r2 ; rw_mm_cause == last_refill_cause ?
+ beq 6f ; yes, increment count
+ moveq 1, $r2
+
+ ; rw_mm_cause != last_refill_cause
+ move.d $r2, [$acr] ; refill_count = 1
+ move.d $r0, [$r1] ; last_refill_cause = rw_mm_cause
+
+3: ; Probably not in a loop, continue normal processing
#ifdef CONFIG_SMP
move $s7, $acr ; PGD
#else
move.d per_cpu__current_pgd, $acr ; PGD
#endif
; Look up PMD in PGD
- move $s3, $r0 ; rw_mm_cause
lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31)
move.d [$acr], $acr ; PGD for the current process
addi $r0.d, $acr, $acr
move $s3, $r0 ; rw_mm_cause
move.d [$acr], $acr ; Get PMD
- beq 1f
+ beq 8f
; Look up PTE in PMD
lsrq PAGE_SHIFT, $r0
and.w PAGE_MASK, $acr ; Remove PMD flags
and.d 0x7ff, $r0 ; Get PTE index into PMD (bit 13-23)
addi $r0.d, $acr, $acr
move.d [$acr], $acr ; Get PTE
- beq 2f
- move.d [$sp+], $r0 ; Pop r0 in delayslot
+ beq 9f
+ movem [$sp], $r2 ; Restore r0-r2 in delay slot
+ addq 12, $sp
; Store in TLB
move $acr, $s5
- ; Return
+4: ; Return
move.d [$sp+], $acr
- move [$sp], $srs
+ move [$sp], $srs
addq 4, $sp
rete
rfe
-1: ; PMD missing, let the mm subsystem fix it up.
- move.d [$sp+], $r0 ; Pop r0
-2: ; PTE missing, let the mm subsystem fix it up.
+
+5: ; last_refill_cause is invalid
+ moveq 1, $r2
+ addq 4, $r1 ; Point to last_refill_cause
+ move.d $r2, [$acr] ; refill_count = 1
+ move $s3, $r0 ; Get rw_mm_cause
+ ba 3b ; Continue normal processing
+ move.d $r0,[$r1] ; last_refill_cause = rw_mm_cause
+
+6: ; rw_mm_cause == last_refill_cause
+ move.d [$acr], $r2 ; Get refill_count
+ cmpq 4, $r2 ; refill_count > 4 ?
+ bhi 7f ; yes
+ addq 1, $r2 ; refill_count++
+ ba 3b ; Continue normal processing
+ move.d $r2, [$acr]
+
+7: ; refill_count > 4, error
+ move.d $acr, $r0 ; Save pointer to refill_count
+ clear.d [$r0] ; refill_count = 0
+
+ ;; rewind the short stack
+ movem [$sp], $r2 ; Restore r0-r2
+ addq 12, $sp
+ move.d [$sp+], $acr
+ move [$sp], $srs
+ addq 4, $sp
+ ;; Keep it simple (slow), save all the regs.
+ SAVE_ALL
+ jsr __flush_tlb_all
+ nop
+ ba ret_from_intr ; Return
+ nop
+
+8: ; PMD missing, let the mm subsystem fix it up.
+ movem [$sp], $r2 ; Restore r0-r2
+9: ; PTE missing, let the mm subsystem fix it up.
+ addq 12, $sp
move.d [$sp+], $acr
- move [$sp], $srs
+ move [$sp], $srs
addq 4, $sp
SAVE_ALL
move \mmu, $srs
#include <asm/arch/hwregs/supp_reg.h>
#define UPDATE_TLB_SEL_IDX(val) \
-do { \
- unsigned long tlb_sel; \
+do { \
+ unsigned long tlb_sel; \
\
tlb_sel = REG_FIELD(mmu, rw_mm_tlb_sel, idx, val); \
SUPP_REG_WR(RW_MM_TLB_SEL, tlb_sel); \
* The TLB can host up to 256 different mm contexts at the same time. The running
* context is found in the PID register. Each TLB entry contains a page_id that
* has to match the PID register to give a hit. page_id_map keeps track of which
- * mm is assigned to which page_id, making sure it's known when to invalidate TLB
- * entries.
+ * mm's is assigned to which page_id's, making sure it's known when to
+ * invalidate TLB entries.
*
* The last page_id is never running, it is used as an invalid page_id so that
* it's possible to make TLB entries that will nerver match.
switch_mm(struct mm_struct *prev, struct mm_struct *next,
struct task_struct *tsk)
{
- int cpu = smp_processor_id();
-
- /* Make sure there is a MMU context. */
- spin_lock(&mmu_context_lock);
- get_mmu_context(next);
- cpu_set(cpu, next->cpu_vm_mask);
- spin_unlock(&mmu_context_lock);
-
- /*
- * Remember the pgd for the fault handlers. Keep a separate copy of it
- * because current and active_mm might be invalid at points where
- * there's still a need to derefer the pgd.
- */
- per_cpu(current_pgd, cpu) = next->pgd;
-
- /* Switch context in the MMU. */
- if (tsk && task_thread_info(tsk))
- {
- SPEC_REG_WR(SPEC_REG_PID, next->context.page_id | task_thread_info(tsk)->tls);
- }
- else
- {
- SPEC_REG_WR(SPEC_REG_PID, next->context.page_id);
- }
+ if (prev != next) {
+ int cpu = smp_processor_id();
+
+ /* Make sure there is a MMU context. */
+ spin_lock(&mmu_context_lock);
+ get_mmu_context(next);
+ cpu_set(cpu, next->cpu_vm_mask);
+ spin_unlock(&mmu_context_lock);
+
+ /*
+ * Remember the pgd for the fault handlers. Keep a seperate
+ * copy of it because current and active_mm might be invalid
+ * at points where * there's still a need to derefer the pgd.
+ */
+ per_cpu(current_pgd, cpu) = next->pgd;
+
+ /* Switch context in the MMU. */
+ if (tsk && task_thread_info(tsk)) {
+ SPEC_REG_WR(SPEC_REG_PID, next->context.page_id |
+ task_thread_info(tsk)->tls);
+ } else {
+ SPEC_REG_WR(SPEC_REG_PID, next->context.page_id);
+ }
+ }
}
*/
#include <asm-generic/vmlinux.lds.h>
+#include <asm/page.h>
+
+#ifdef CONFIG_ETRAX_VMEM_SIZE
+#define __CONFIG_ETRAX_VMEM_SIZE CONFIG_ETRAX_VMEM_SIZE
+#else
+#define __CONFIG_ETRAX_VMEM_SIZE 0
+#endif
jiffies = jiffies_64;
SECTIONS
dram_start = .;
ebp_start = .;
- /* The boot section is only necessary until the VCS top level testbench */
- /* includes both flash and DRAM. */
+ /* The boot section is only necessary until the VCS top */
+ /* level testbench includes both flash and DRAM. */
.boot : { *(.boot) }
- . = DRAM_VIRTUAL_BASE + 0x4000; /* See head.S and pages reserved at the start. */
+ /* See head.S and pages reserved at the start. */
+ . = DRAM_VIRTUAL_BASE + 0x4000;
_text = .; /* Text and read-only data. */
text_start = .; /* Lots of aliases. */
_stext = .;
__stext = .;
.text : {
- *(.text)
+ TEXT_TEXT
SCHED_TEXT
LOCK_TEXT
*(.fixup)
__etext = .;
. = ALIGN(4); /* Exception table. */
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
RODATA
__edata = . ; /* End of data section. */
_edata = . ;
- . = ALIGN(8192); /* init_task and stack, must be aligned. */
- .data.init_task : { *(.data.init_task) }
+ . = ALIGN(PAGE_SIZE); /* init_task and stack, must be aligned. */
+ .data.init_task : { *(.data.init_task) }
- . = ALIGN(8192); /* Init code and data. */
- __init_begin = .;
+ . = ALIGN(PAGE_SIZE); /* Init code and data. */
+ __init_begin = .;
.init.text : {
_sinittext = .;
INIT_TEXT
_einittext = .;
}
.init.data : { INIT_DATA }
- . = ALIGN(16);
- __setup_start = .;
- .init.setup : { *(.init.setup) }
- __setup_end = .;
+ . = ALIGN(16);
+ __setup_start = .;
+ .init.setup : { *(.init.setup) }
+ __setup_end = .;
__start___param = .;
__param : { *(__param) }
__stop___param = .;
- .initcall.init : {
+ .initcall.init : {
__initcall_start = .;
- *(.initcall1.init);
- *(.initcall2.init);
- *(.initcall3.init);
- *(.initcall4.init);
- *(.initcall5.init);
- *(.initcall6.init);
- *(.initcall7.init);
+ INITCALLS
__initcall_end = .;
}
}
SECURITY_INIT
- PERCPU(8192)
+ __vmlinux_end = .; /* Last address of the physical file. */
+ PERCPU(PAGE_SIZE)
-#ifdef CONFIG_BLK_DEV_INITRD
.init.ramfs : {
__initramfs_start = .;
*(.init.ramfs)
__initramfs_end = .;
- /*
- * We fill to the next page, so we can discard all init
- * pages without needing to consider what payload might be
- * appended to the kernel image.
- */
- FILL (0);
- . = ALIGN (8192);
}
-#endif
- __vmlinux_end = .; /* Last address of the physical file. */
- __init_end = .;
+ /*
+ * We fill to the next page, so we can discard all init
+ * pages without needing to consider what payload might be
+ * appended to the kernel image.
+ */
+ . = ALIGN (PAGE_SIZE);
+
+ __init_end = .;
__data_end = . ; /* Move to _edata? */
__bss_start = .; /* BSS. */
__end = .;
/* Sections to be discarded */
- /DISCARD/ : {
+ /DISCARD/ : {
EXIT_TEXT
EXIT_DATA
*(.exitcall.exit)
}
- dram_end = dram_start + CONFIG_ETRAX_DRAM_SIZE*1024*1024;
+ dram_end = dram_start + (CONFIG_ETRAX_DRAM_SIZE - __CONFIG_ETRAX_VMEM_SIZE)*1024*1024;
}
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc3
+# Mon Dec 3 11:18:54 2007
+#
+CONFIG_MMU=y
+CONFIG_ZONE_DMA=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_IOMAP=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NO_IOPORT=y
+CONFIG_FORCE_MAX_ZONEORDER=6
+CONFIG_CRIS=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# General setup
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
+# CONFIG_ETRAX_WATCHDOG is not set
+CONFIG_ETRAX_FAST_TIMER=y
+# CONFIG_ETRAX_KMALLOCED_MODULES is not set
+# CONFIG_OOM_REBOOT is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+
+#
+# Hardware setup
+#
+# CONFIG_ETRAX100LX is not set
+# CONFIG_ETRAX100LX_V2 is not set
+# CONFIG_SVINTO_SIM is not set
+# CONFIG_ETRAXFS is not set
+CONFIG_CRIS_MACH_ARTPEC3=y
+# CONFIG_ETRAX_VCS_SIM is not set
+# CONFIG_ETRAX_ARCH_V10 is not set
+CONFIG_ETRAX_ARCH_V32=y
+CONFIG_ETRAX_DRAM_SIZE=32
+CONFIG_ETRAX_VMEM_SIZE=8
+CONFIG_ETRAX_FLASH_BUSWIDTH=2
+CONFIG_ETRAX_NANDFLASH_BUSWIDTH=1
+CONFIG_ETRAX_FLASH1_SIZE=4
+CONFIG_ETRAX_DEBUG_PORT0=y
+# CONFIG_ETRAX_DEBUG_PORT1 is not set
+# CONFIG_ETRAX_DEBUG_PORT2 is not set
+# CONFIG_ETRAX_DEBUG_PORT3 is not set
+# CONFIG_ETRAX_DEBUG_PORT_NULL is not set
+CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000
+CONFIG_ETRAX_SERIAL_PORTS=5
+CONFIG_ETRAX_DEF_GIO_PA_OE=1c
+CONFIG_ETRAX_DEF_GIO_PA_OUT=00
+CONFIG_ETRAX_DEF_GIO_PB_OE=00000
+CONFIG_ETRAX_DEF_GIO_PB_OUT=00000
+CONFIG_ETRAX_DEF_GIO_PC_OE=00000
+CONFIG_ETRAX_DEF_GIO_PC_OUT=00000
+
+#
+# Artpec-3 options
+#
+CONFIG_ETRAX_L2CACHE=y
+CONFIG_ETRAX_DDR=y
+CONFIG_ETRAX_DDR2_MRS=0
+CONFIG_ETRAX_DDR2_TIMING=0
+CONFIG_ETRAX_DDR2_CONFIG=0
+CONFIG_ETRAX_PIO_CE0_CFG=0
+CONFIG_ETRAX_PIO_CE1_CFG=0
+CONFIG_ETRAX_PIO_CE2_CFG=0
+# CONFIG_CPU_FREQ is not set
+# CONFIG_ETRAX_NBR_LED_GRP_ZERO is not set
+CONFIG_ETRAX_NBR_LED_GRP_ONE=y
+# CONFIG_ETRAX_NBR_LED_GRP_TWO is not set
+CONFIG_ETRAX_LED_G_NET0="PA3"
+CONFIG_ETRAX_LED_R_NET0="PA4"
+CONFIG_ETRAX_V32_LED2G="PA5"
+CONFIG_ETRAX_V32_LED2R="PA6"
+CONFIG_ETRAX_V32_LED3G="PA7"
+CONFIG_ETRAX_V32_LED3R="PA7"
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Drivers for built-in interfaces
+#
+CONFIG_ETRAX_ETHERNET=y
+# CONFIG_ETRAX_IDE is not set
+CONFIG_ETRAX_AXISFLASHMAP=y
+CONFIG_ETRAX_PTABLE_SECTOR=65536
+# CONFIG_ETRAX_I2C is not set
+# CONFIG_ETRAX_GPIO is not set
+# CONFIG_ETRAX_NO_PHY is not set
+# CONFIG_ETRAX_ETHERNET_IFACE0 is not set
+# CONFIG_ETRAX_ETHERNET_GBIT is not set
+# CONFIG_ETRAXFS_SERIAL is not set
+# CONFIG_ETRAX_SYNCHRONOUS_SERIAL is not set
+# CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE is not set
+# CONFIG_ETRAX_NANDFLASH is not set
+# CONFIG_ETRAX_CARDBUS is not set
+# CONFIG_ETRAX_IOP_FW_LOAD is not set
+# CONFIG_ETRAX_STREAMCOPROC is not set
+# CONFIG_ETRAX_SPI_MMC is not set
+# CONFIG_ETRAX_SPI_MMC_BOARD is not set
+# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
+CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+CONFIG_MTD_MTDRAM=y
+CONFIG_MTDRAM_TOTAL_SIZE=0
+CONFIG_MTDRAM_ERASE_SIZE=64
+CONFIG_MTDRAM_ABS_POS=0x0
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_HW_RANDOM=y
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PROFILING is not set
+# CONFIG_SYSTEM_PROFILER is not set
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SAMPLES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_DMA=y
#
# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.11
-# Mon Jun 20 13:42:02 2005
+# Linux kernel version: 2.6.24-rc3
+# Mon Dec 3 11:34:27 2007
#
CONFIG_MMU=y
-CONFIG_UID16=y
+CONFIG_ZONE_DMA=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_IOMAP=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NO_IOPORT=y
+CONFIG_FORCE_MAX_ZONEORDER=6
CONFIG_CRIS=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
-# Code maturity level options
+# General setup
#
CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y
-
-#
-# General setup
-#
+CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
# CONFIG_AUDIT is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_HOTPLUG is not set
-CONFIG_KOBJECT_UEVENT=y
# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
#
-# Loadable module support
+# IO Schedulers
#
-# CONFIG_MODULES is not set
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
#
# General setup
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_MISC is not set
CONFIG_GENERIC_HARDIRQS=y
-# CONFIG_SMP is not set
CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
# CONFIG_ETRAX_WATCHDOG is not set
CONFIG_ETRAX_FAST_TIMER=y
-# CONFIG_PREEMPT is not set
+# CONFIG_ETRAX_KMALLOCED_MODULES is not set
# CONFIG_OOM_REBOOT is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
#
# Hardware setup
CONFIG_ETRAX100LX_V2=y
# CONFIG_SVINTO_SIM is not set
# CONFIG_ETRAXFS is not set
-# CONFIG_ETRAXFS_SIM is not set
+# CONFIG_CRIS_MACH_ARTPEC3 is not set
+# CONFIG_ETRAX_VCS_SIM is not set
CONFIG_ETRAX_ARCH_V10=y
# CONFIG_ETRAX_ARCH_V32 is not set
CONFIG_ETRAX_DRAM_SIZE=32
CONFIG_ETRAX_FLASH_BUSWIDTH=2
+CONFIG_ETRAX_NANDFLASH_BUSWIDTH=1
CONFIG_ETRAX_FLASH1_SIZE=4
+# CONFIG_ETRAX_DEBUG_PORT0 is not set
+# CONFIG_ETRAX_DEBUG_PORT1 is not set
+# CONFIG_ETRAX_DEBUG_PORT2 is not set
+# CONFIG_ETRAX_DEBUG_PORT3 is not set
+CONFIG_ETRAX_DEBUG_PORT_NULL=y
+
+#
+# CRIS v10 options
+#
CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000
CONFIG_ETRAX_PA_LEDS=y
# CONFIG_ETRAX_PB_LEDS is not set
# CONFIG_ETRAX_CSP0_LEDS is not set
# CONFIG_ETRAX_NO_LEDS is not set
CONFIG_ETRAX_LED1G=2
-CONFIG_ETRAX_LED1R=2
-CONFIG_ETRAX_LED2G=3
-CONFIG_ETRAX_LED2R=3
+CONFIG_ETRAX_LED1R=3
+CONFIG_ETRAX_LED2G=4
+CONFIG_ETRAX_LED2R=5
CONFIG_ETRAX_LED3G=2
CONFIG_ETRAX_LED3R=2
-CONFIG_ETRAX_DEBUG_PORT0=y
-# CONFIG_ETRAX_DEBUG_PORT1 is not set
-# CONFIG_ETRAX_DEBUG_PORT2 is not set
-# CONFIG_ETRAX_DEBUG_PORT3 is not set
-# CONFIG_ETRAX_DEBUG_PORT_NULL is not set
CONFIG_ETRAX_RESCUE_SER0=y
# CONFIG_ETRAX_RESCUE_SER1 is not set
# CONFIG_ETRAX_RESCUE_SER2 is not set
# CONFIG_ETRAX_RESCUE_SER3 is not set
-CONFIG_ETRAX_DEF_R_WAITSTATES=0x95a6
-CONFIG_ETRAX_DEF_R_BUS_CONFIG=0x4
-CONFIG_ETRAX_SDRAM=y
-CONFIG_ETRAX_DEF_R_SDRAM_CONFIG=0x09e05757
-CONFIG_ETRAX_DEF_R_SDRAM_TIMING=0x80008002
-CONFIG_ETRAX_DEF_R_PORT_PA_DIR=0x1d
-CONFIG_ETRAX_DEF_R_PORT_PA_DATA=0x00
-CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG=0x00
-CONFIG_ETRAX_DEF_R_PORT_PB_DIR=0x1e
-CONFIG_ETRAX_DEF_R_PORT_PB_DATA=0xf3
+CONFIG_ETRAX_DEF_R_WAITSTATES=95a6
+CONFIG_ETRAX_DEF_R_BUS_CONFIG=104
+# CONFIG_ETRAX_SDRAM is not set
+CONFIG_ETRAX_DEF_R_DRAM_CONFIG=1a200040
+CONFIG_ETRAX_DEF_R_DRAM_TIMING=5611
+CONFIG_ETRAX_DEF_R_PORT_PA_DIR=1c
+CONFIG_ETRAX_DEF_R_PORT_PA_DATA=00
+CONFIG_ETRAX_DEF_R_PORT_PB_CONFIG=00
+CONFIG_ETRAX_DEF_R_PORT_PB_DIR=00
+CONFIG_ETRAX_DEF_R_PORT_PB_DATA=ff
# CONFIG_ETRAX_SOFT_SHUTDOWN is not set
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
#
# Drivers for built-in interfaces
#
CONFIG_ETRAX_ETHERNET=y
-# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
-CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
CONFIG_ETRAX_SERIAL=y
# CONFIG_ETRAX_SERIAL_FAST_TIMER is not set
# CONFIG_ETRAX_SERIAL_FLUSH_DMA_FAST is not set
CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS=5
-CONFIG_ETRAX_SERIAL_PORT0=y
-# CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_OUT is not set
-CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT=y
-# CONFIG_ETRAX_SERIAL_PORT0_NO_DMA_IN is not set
-CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN=y
-CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_NONE=y
-# CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PA is not set
-# CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_ON_PB is not set
-# CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED is not set
-CONFIG_ETRAX_SER0_DTR_ON_PA_BIT=-1
-CONFIG_ETRAX_SER0_RI_ON_PA_BIT=-1
-CONFIG_ETRAX_SER0_DSR_ON_PA_BIT=-1
-CONFIG_ETRAX_SER0_CD_ON_PA_BIT=-1
-CONFIG_ETRAX_SER0_DTR_ON_PB_BIT=-1
-CONFIG_ETRAX_SER0_RI_ON_PB_BIT=-1
-CONFIG_ETRAX_SER0_DSR_ON_PB_BIT=-1
-CONFIG_ETRAX_SER0_CD_ON_PB_BIT=-1
+# CONFIG_ETRAX_SERIAL_PORT0 is not set
# CONFIG_ETRAX_SERIAL_PORT1 is not set
-CONFIG_ETRAX_SERIAL_PORT2=y
-# CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_OUT is not set
-CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT=y
-# CONFIG_ETRAX_SERIAL_PORT2_NO_DMA_IN is not set
-CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN=y
-CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_NONE=y
-# CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PA is not set
-# CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_ON_PB is not set
-# CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED is not set
-CONFIG_ETRAX_SER2_DTR_ON_PA_BIT=-1
-CONFIG_ETRAX_SER2_RI_ON_PA_BIT=-1
-CONFIG_ETRAX_SER2_DSR_ON_PA_BIT=-1
-CONFIG_ETRAX_SER2_CD_ON_PA_BIT=-1
-CONFIG_ETRAX_SER2_DTR_ON_PB_BIT=-1
-CONFIG_ETRAX_SER2_RI_ON_PB_BIT=-1
-CONFIG_ETRAX_SER2_DSR_ON_PB_BIT=-1
-CONFIG_ETRAX_SER2_CD_ON_PB_BIT=-1
+# CONFIG_ETRAX_SERIAL_PORT2 is not set
# CONFIG_ETRAX_SERIAL_PORT3 is not set
-CONFIG_ETRAX_RS485=y
-# CONFIG_ETRAX_RS485_ON_PA is not set
-# CONFIG_ETRAX_RS485_DISABLE_RECEIVER is not set
-CONFIG_ETRAX_IDE=y
-CONFIG_ETRAX_IDE_DELAY=15
-CONFIG_ETRAX_IDE_PB7_RESET=y
-# CONFIG_ETRAX_IDE_G27_RESET is not set
-CONFIG_ETRAX_USB_HOST=y
-CONFIG_ETRAX_USB_HOST_PORT1=y
-CONFIG_ETRAX_USB_HOST_PORT2=y
+# CONFIG_ETRAX_RS485 is not set
+# CONFIG_ETRAX_IDE is not set
+# CONFIG_ETRAX_USB_HOST is not set
CONFIG_ETRAX_AXISFLASHMAP=y
CONFIG_ETRAX_PTABLE_SECTOR=65536
# CONFIG_ETRAX_I2C is not set
# CONFIG_ETRAX_GPIO is not set
-CONFIG_ETRAX_RTC=y
-CONFIG_ETRAX_DS1302=y
-# CONFIG_ETRAX_PCF8563 is not set
-CONFIG_ETRAX_DS1302_RST_ON_GENERIC_PORT=y
-CONFIG_ETRAX_DS1302_RSTBIT=0
-CONFIG_ETRAX_DS1302_SCLBIT=1
-CONFIG_ETRAX_DS1302_SDABIT=0
-CONFIG_ETRAX_DS1302_TRICKLE_CHARGE=0
+# CONFIG_ETRAX_RTC is not set
+# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
+CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
+# CONFIG_SYS_HYPERVISOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
-CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_GEN_PROBE=y
# CONFIG_MTD_CFI_ADV_OPTIONS is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_AMDSTD_RETRY=0
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
CONFIG_MTD_RAM=y
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_SHARP is not set
-# CONFIG_MTD_JEDEC is not set
#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
CONFIG_MTDRAM_TOTAL_SIZE=0
CONFIG_MTDRAM_ERASE_SIZE=64
CONFIG_MTDRAM_ABS_POS=0x0
-# CONFIG_MTD_BLKMTD is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
+# UBI - Unsorted block images
#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
+# CONFIG_MTD_UBI is not set
+CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=16
CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_INITRAMFS_SOURCE=""
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
# CONFIG_CDROM_PKTCDVD is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_IOSCHED_CFQ=y
# CONFIG_ATA_OVER_ETH is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-# CONFIG_PARIDE is not set
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-# CONFIG_IDEDISK_MULTI_MODE is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_IDE_ARM is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_SCSI is not set
-# CONFIG_ISCSI_TCP is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-# CONFIG_NETLINK_DEV is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# IP: Netfilter Configuration
-#
-# CONFIG_IP_NF_CONNTRACK is not set
-# CONFIG_IP_NF_CONNTRACK_MARK is not set
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_AF_RXRPC_DEBUG is not set
-# CONFIG_BT is not set
-# CONFIG_I2C is not set
-
CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
-# CONFIG_MII is not set
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
+# Wireless LAN
#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_SHAPER is not set
# CONFIG_NETCONSOLE is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
-# CONFIG_PHONE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_RTC_CLASS is not set
#
# Input device support
# CONFIG_INPUT is not set
#
-# Input I/O drivers
+# Hardware I/O ports
#
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
# CONFIG_SERIO_RAW is not set
# CONFIG_GAMEPORT is not set
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
#
# Character devices
#
# CONFIG_VT is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
+CONFIG_HW_RANDOM=y
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
-# CONFIG_RTC_LIB is not set
-# CONFIG_RTC_CLASS is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
# CONFIG_RAW_DRIVER is not set
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
+# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
-
-#
-# XFS support
-#
+# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
CONFIG_DNOTIFY=y
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
CONFIG_TMPFS=y
-# CONFIG_TMPFS_XATTR is not set
+# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
-CONFIG_JFFS_FS=y
-CONFIG_JFFS_FS_VERBOSE=0
-# CONFIG_JFFS_PROC_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
-# CONFIG_JFFS2_FS_NAND is not set
-# CONFIG_JFFS2_FS_NOR_ECC is not set
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
CONFIG_CRAMFS=y
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
# CONFIG_NFS_V4 is not set
# CONFIG_NFS_DIRECTIO is not set
# CONFIG_NFSD is not set
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
# CONFIG_NLS is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# Generic devices
-#
-# CONFIG_SND_MPU401_UART is not set
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_VIRMIDI is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-# CONFIG_PARPORT_PC_PCMCIA is not set
-# CONFIG_NET_PCMCIA is not set
-
-#
-# PC-card bridges
-#
-
-#
-# USB support
-#
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_BANDWIDTH is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_SL811_HCD is not set
-
-#
-# USB Device Class drivers
-#
-
-#
-# USB Bluetooth TTY can only be used with disabled Bluetooth subsystem
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information
-#
-# CONFIG_USB_STORAGE is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-# HID_SUPPORT is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_MTOUCH is not set
-# CONFIG_USB_EGALAX is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-
-#
-# USB Multimedia devices
-#
-# CONFIG_USB_DABUSB is not set
-
-#
-# Video4Linux support is needed for USB Multimedia device support
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-CONFIG_USB_RTL8150=y
-# CONFIG_USB_USBNET is not set
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGETKIT is not set
-# CONFIG_USB_PHIDGETSERVO is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB ATM/DSL drivers
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
+# CONFIG_DLM is not set
#
# Kernel hacking
#
# CONFIG_PROFILING is not set
# CONFIG_SYSTEM_PROFILER is not set
-# CONFIG_ETRAX_KGDB is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_FRAME_POINTER is not set
-# CONFIG_DEBUG_NMI_OOPS is not set
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SAMPLES is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
-#
-# Hardware crypto devices
-# CONFIG_CRYPTO_HW is not set
-
#
# Library routines
#
+CONFIG_BITREVERSE=y
# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_DMA=y
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc3
+# Fri Nov 30 14:24:26 2007
+#
+CONFIG_MMU=y
+CONFIG_ZONE_DMA=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_IOMAP=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NO_IOPORT=y
+CONFIG_FORCE_MAX_ZONEORDER=6
+CONFIG_CRIS=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAIR_USER_SCHED=y
+# CONFIG_FAIR_CGROUP_SCHED is not set
+CONFIG_SYSFS_DEPRECATED=y
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# General setup
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_ETRAX_CMDLINE="root=/dev/mtdblock3 init=/linuxrc"
+# CONFIG_ETRAX_WATCHDOG is not set
+CONFIG_ETRAX_FAST_TIMER=y
+# CONFIG_ETRAX_KMALLOCED_MODULES is not set
+# CONFIG_OOM_REBOOT is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+
+#
+# Hardware setup
+#
+# CONFIG_ETRAX100LX is not set
+# CONFIG_ETRAX100LX_V2 is not set
+# CONFIG_SVINTO_SIM is not set
+CONFIG_ETRAXFS=y
+# CONFIG_CRIS_MACH_ARTPEC3 is not set
+# CONFIG_ETRAX_VCS_SIM is not set
+# CONFIG_ETRAX_ARCH_V10 is not set
+CONFIG_ETRAX_ARCH_V32=y
+CONFIG_ETRAX_DRAM_SIZE=32
+CONFIG_ETRAX_FLASH_BUSWIDTH=2
+CONFIG_ETRAX_NANDFLASH_BUSWIDTH=1
+CONFIG_ETRAX_FLASH1_SIZE=4
+CONFIG_ETRAX_DEBUG_PORT0=y
+# CONFIG_ETRAX_DEBUG_PORT1 is not set
+# CONFIG_ETRAX_DEBUG_PORT2 is not set
+# CONFIG_ETRAX_DEBUG_PORT3 is not set
+# CONFIG_ETRAX_DEBUG_PORT_NULL is not set
+CONFIG_ETRAX_DRAM_VIRTUAL_BASE=c0000000
+
+#
+# ETRAX FS options
+#
+CONFIG_ETRAX_SERIAL_PORTS=4
+CONFIG_ETRAX_MEM_GRP1_CONFIG=4044a
+CONFIG_ETRAX_MEM_GRP2_CONFIG=0
+CONFIG_ETRAX_MEM_GRP3_CONFIG=0
+CONFIG_ETRAX_MEM_GRP4_CONFIG=0
+CONFIG_ETRAX_SDRAM_GRP0_CONFIG=336
+CONFIG_ETRAX_SDRAM_GRP1_CONFIG=0
+CONFIG_ETRAX_SDRAM_TIMING=104a
+CONFIG_ETRAX_SDRAM_COMMAND=0
+CONFIG_ETRAX_DEF_GIO_PA_OE=1c
+CONFIG_ETRAX_DEF_GIO_PA_OUT=00
+CONFIG_ETRAX_DEF_GIO_PB_OE=00000
+CONFIG_ETRAX_DEF_GIO_PB_OUT=00000
+CONFIG_ETRAX_DEF_GIO_PC_OE=00000
+CONFIG_ETRAX_DEF_GIO_PC_OUT=00000
+CONFIG_ETRAX_DEF_GIO_PD_OE=00000
+CONFIG_ETRAX_DEF_GIO_PD_OUT=00000
+CONFIG_ETRAX_DEF_GIO_PE_OE=00000
+CONFIG_ETRAX_DEF_GIO_PE_OUT=00000
+# CONFIG_CPU_FREQ is not set
+# CONFIG_ETRAX_NBR_LED_GRP_ZERO is not set
+CONFIG_ETRAX_NBR_LED_GRP_ONE=y
+# CONFIG_ETRAX_NBR_LED_GRP_TWO is not set
+CONFIG_ETRAX_LED_G_NET0="PA3"
+CONFIG_ETRAX_LED_R_NET0="PA4"
+CONFIG_ETRAX_V32_LED2G="PA5"
+CONFIG_ETRAX_V32_LED2R="PA6"
+CONFIG_ETRAX_V32_LED3G="PA7"
+CONFIG_ETRAX_V32_LED3R="PA7"
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+# CONFIG_NETFILTER_NETLINK is not set
+# CONFIG_NF_CONNTRACK_ENABLED is not set
+# CONFIG_NF_CONNTRACK is not set
+# CONFIG_NETFILTER_XTABLES is not set
+
+#
+# IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Drivers for built-in interfaces
+#
+CONFIG_ETRAX_ETHERNET=y
+# CONFIG_ETRAX_IDE is not set
+CONFIG_ETRAX_AXISFLASHMAP=y
+CONFIG_ETRAX_PTABLE_SECTOR=65536
+# CONFIG_ETRAX_I2C is not set
+# CONFIG_ETRAX_GPIO is not set
+# CONFIG_ETRAX_NO_PHY is not set
+# CONFIG_ETRAX_ETHERNET_IFACE0 is not set
+# CONFIG_ETRAX_ETHERNET_IFACE1 is not set
+# CONFIG_ETRAXFS_SERIAL is not set
+# CONFIG_ETRAX_SYNCHRONOUS_SERIAL is not set
+# CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE is not set
+# CONFIG_ETRAX_NANDFLASH is not set
+# CONFIG_ETRAX_CARDBUS is not set
+# CONFIG_ETRAX_IOP_FW_LOAD is not set
+# CONFIG_ETRAX_STREAMCOPROC is not set
+# CONFIG_ETRAX_SPI_MMC is not set
+# CONFIG_ETRAX_SPI_MMC_BOARD is not set
+# CONFIG_ETRAX_NETWORK_LED_ON_WHEN_LINK is not set
+CONFIG_ETRAX_NETWORK_LED_ON_WHEN_ACTIVITY=y
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+CONFIG_MTD_MTDRAM=y
+CONFIG_MTDRAM_TOTAL_SIZE=0
+CONFIG_MTDRAM_ERASE_SIZE=64
+CONFIG_MTDRAM_ABS_POS=0x0
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+# CONFIG_SERIO_LIBPS2 is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_HW_RANDOM=y
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4DEV_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PROFILING is not set
+# CONFIG_SYSTEM_PROFILER is not set
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SAMPLES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_DMA=y
#define DEBUGP(fmt , ...)
#endif
+#ifdef CONFIG_ETRAX_KMALLOCED_MODULES
+#define MALLOC_MODULE(size) kmalloc(size, GFP_KERNEL)
+#define FREE_MODULE(region) kfree(region)
+#else
+#define MALLOC_MODULE(size) vmalloc_exec(size)
+#define FREE_MODULE(region) vfree(region)
+#endif
+
void *module_alloc(unsigned long size)
{
if (size == 0)
return NULL;
- return vmalloc_exec(size);
+ return MALLOC_MODULE(size);
}
/* Free memory returned from module_alloc */
void module_free(struct module *mod, void *module_region)
{
- vfree(module_region);
+ FREE_MODULE(module_region);
/* FIXME: If module_region == mod->init_region, trim exception
- table entries. */
+ table entries. */
}
/* We don't need anything special. */
-/* $Id: process.c,v 1.21 2005/03/04 08:16:17 starvik Exp $
- *
+/*
* linux/arch/cris/kernel/process.c
*
* Copyright (C) 1995 Linus Torvalds
*
* Authors: Bjorn Wesen (bjornw@axis.com)
*
- * $Log: process.c,v $
- * Revision 1.21 2005/03/04 08:16:17 starvik
- * Merge of Linux 2.6.11.
- *
- * Revision 1.20 2005/01/18 05:57:22 starvik
- * Renamed hlt_counter to cris_hlt_counter and made it global.
- *
- * Revision 1.19 2004/10/19 13:07:43 starvik
- * Merge of Linux 2.6.9
- *
- * Revision 1.18 2004/08/16 12:37:23 starvik
- * Merge of Linux 2.6.8
- *
- * Revision 1.17 2004/04/05 13:53:48 starvik
- * Merge of Linux 2.6.5
- *
- * Revision 1.16 2003/10/27 08:04:33 starvik
- * Merge of Linux 2.6.0-test9
- *
- * Revision 1.15 2003/09/11 07:29:52 starvik
- * Merge of Linux 2.6.0-test5
- *
- * Revision 1.14 2003/06/10 10:21:12 johana
- * Moved thread_saved_pc() from arch/cris/kernel/process.c to
- * subarch specific process.c. arch-v32 has an erp, no irp.
- *
- * Revision 1.13 2003/04/09 05:20:47 starvik
- * Merge of Linux 2.5.67
- *
- * Revision 1.12 2002/12/11 15:41:11 starvik
- * Extracted v10 (ETRAX 100LX) specific stuff to arch/cris/arch-v10/kernel
- *
- * Revision 1.11 2002/12/10 09:00:10 starvik
- * Merge of Linux 2.5.51
- *
- * Revision 1.10 2002/11/27 08:42:34 starvik
- * Argument to user_regs() is thread_info*
- *
- * Revision 1.9 2002/11/26 09:44:21 starvik
- * New threads exits through ret_from_fork (necessary for preemptive scheduling)
- *
- * Revision 1.8 2002/11/19 14:35:24 starvik
- * Changes from linux 2.4
- * Changed struct initializer syntax to the currently prefered notation
- *
- * Revision 1.7 2002/11/18 07:39:42 starvik
- * thread_saved_pc moved here from processor.h
- *
- * Revision 1.6 2002/11/14 06:51:27 starvik
- * Made cpu_idle more similar with other archs
- * init_task_union -> init_thread_union
- * Updated for new interrupt macros
- * sys_clone and do_fork have a new argument, user_tid
- *
- * Revision 1.5 2002/11/05 06:45:11 starvik
- * Merge of Linux 2.5.45
- *
- * Revision 1.4 2002/02/05 15:37:44 bjornw
- * Need init_task.h
- *
- * Revision 1.3 2002/01/21 15:22:49 bjornw
- * current->counter is gone
- *
- * Revision 1.22 2001/11/13 09:40:43 orjanf
- * Added dump_fpu (needed for core dumps).
- *
- * Revision 1.21 2001/11/12 18:26:21 pkj
- * Fixed compiler warnings.
- *
- * Revision 1.20 2001/10/03 08:21:39 jonashg
- * cause_of_death does not exist if CONFIG_SVINTO_SIM is defined.
- *
- * Revision 1.19 2001/09/26 11:52:54 bjornw
- * INIT_MMAP is gone in 2.4.10
- *
- * Revision 1.18 2001/08/21 21:43:51 hp
- * Move last watchdog fix inside #ifdef CONFIG_ETRAX_WATCHDOG
- *
- * Revision 1.17 2001/08/21 13:48:01 jonashg
- * Added fix by HP to avoid oops when doing a hard_reset_now.
- *
- * Revision 1.16 2001/06/21 02:00:40 hp
- * * entry.S: Include asm/unistd.h.
- * (_sys_call_table): Use section .rodata, not .data.
- * (_kernel_thread): Move from...
- * * process.c: ... here.
- * * entryoffsets.c (VAL): Break out from...
- * (OF): Use VAL.
- * (LCLONE_VM): New asmified value from CLONE_VM.
- *
- * Revision 1.15 2001/06/20 16:31:57 hp
- * Add comments to describe empty functions according to review.
- *
- * Revision 1.14 2001/05/29 11:27:59 markusl
- * Fixed so that hard_reset_now will do reset even if watchdog wasn't enabled
- *
- * Revision 1.13 2001/03/20 19:44:06 bjornw
- * Use the 7th syscall argument for regs instead of current_regs
- *
*/
/*
* low exit latency (ie sit in a loop waiting for
* somebody to say that they'd like to reschedule)
*/
+
void cpu_idle (void)
{
/* endless idle loop with no priority at all */
* linux/arch/cris/kernel/ptrace.c
*
* Parts taken from the m68k port.
- *
+ *
* Copyright (c) 2000, 2001, 2002 Axis Communications AB
*
* Authors: Bjorn Wesen
*
- * $Log: ptrace.c,v $
- * Revision 1.10 2004/09/22 11:50:01 orjanf
- * * Moved get_reg/put_reg to arch-specific files.
- * * Added functions to access debug registers (CRISv32).
- * * Added support for PTRACE_SINGLESTEP (CRISv32).
- * * Added S flag to CCS_MASK (CRISv32).
- *
- * Revision 1.9 2003/07/04 12:56:11 tobiasa
- * Moved arch-specific code to arch-specific files.
- *
- * Revision 1.8 2003/04/09 05:20:47 starvik
- * Merge of Linux 2.5.67
- *
- * Revision 1.7 2002/11/27 08:42:34 starvik
- * Argument to user_regs() is thread_info*
- *
- * Revision 1.6 2002/11/20 11:56:11 starvik
- * Merge of Linux 2.5.48
- *
- * Revision 1.5 2002/11/18 07:41:19 starvik
- * Removed warning
- *
- * Revision 1.4 2002/11/11 12:47:28 starvik
- * SYSCALL_TRACE has been moved to thread flags
- *
- * Revision 1.3 2002/02/05 15:37:18 bjornw
- * * Add do_notify_resume (replaces do_signal in the callchain)
- * * syscall_trace is now do_syscall_trace
- * * current->ptrace flag PT_TRACESYS -> PT_SYSCALLTRACE
- * * Keep track of the current->work.syscall_trace counter
- *
- * Revision 1.2 2001/12/18 13:35:20 bjornw
- * Applied the 2.4.13->2.4.16 CRIS patch to 2.5.1 (is a copy of 2.4.15).
- *
- * Revision 1.8 2001/11/12 18:26:21 pkj
- * Fixed compiler warnings.
- *
- * Revision 1.7 2001/09/26 11:53:49 bjornw
- * PTRACE_DETACH works more simple in 2.4.10
- *
- * Revision 1.6 2001/07/25 16:08:47 bjornw
- * PTRACE_ATTACH bulk moved into arch-independent code in 2.4.7
- *
- * Revision 1.5 2001/03/26 14:24:28 orjanf
- * * Changed loop condition.
- * * Added comment documenting non-standard ptrace behaviour.
- *
- * Revision 1.4 2001/03/20 19:44:41 bjornw
- * Use the user_regs macro instead of thread.esp0
- *
- * Revision 1.3 2000/12/18 23:45:25 bjornw
- * Linux/CRIS first version
- *
- *
*/
#include <linux/kernel.h>
void do_notify_resume(int canrestart, struct pt_regs *regs,
- __u32 thread_info_flags )
+ __u32 thread_info_flags)
{
/* deal with pending signal delivery */
if (thread_info_flags & _TIF_SIGPENDING)
*/
#include <linux/sched.h>
-#include <linux/init.h>
#include <asm/semaphore-helper.h>
/*
#include <linux/screen_info.h>
#include <linux/utsname.h>
#include <linux/pfn.h>
-
+#include <linux/cpu.h>
#include <asm/setup.h>
/*
extern unsigned long romfs_start, romfs_length, romfs_in_flash; /* from head.S */
+static struct cpu cpu_devices[NR_CPUS];
+
extern void show_etrax_copyright(void); /* arch-vX/kernel/setup.c */
/* This mainly sets up the memory area, and can be really confusing.
* given by the macro __pa().
*
* In this DRAM, the kernel code and data is loaded, in the beginning.
- * It really starts at c0004000 to make room for some special pages -
+ * It really starts at c0004000 to make room for some special pages -
* the start address is text_start. The kernel data ends at _end. After
* this the ROM filesystem is appended (if there is any).
- *
+ *
* Between this address and dram_end, we have RAM pages usable to the
* boot code and the system.
*
*/
-void __init
-setup_arch(char **cmdline_p)
+void __init setup_arch(char **cmdline_p)
{
extern void init_etrax_debug(void);
unsigned long bootmap_size;
unsigned long start_pfn, max_pfn;
unsigned long memory_start;
- /* register an initial console printing routine for printk's */
+ /* register an initial console printing routine for printk's */
init_etrax_debug();
min_low_pfn = PAGE_OFFSET >> PAGE_SHIFT;
bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
- min_low_pfn,
+ min_low_pfn,
max_low_pfn);
/* And free all memory not belonging to the kernel (addr, size) */
extern int show_cpuinfo(struct seq_file *m, void *v);
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
.show = show_cpuinfo,
};
+static int __init topology_init(void)
+{
+ int i;
+
+ for_each_possible_cpu(i) {
+ return register_cpu(&cpu_devices[i], i);
+ }
+
+ return 0;
+}
+
+subsys_initcall(topology_init);
-/* $Id: time.c,v 1.18 2005/03/04 08:16:17 starvik Exp $
- *
+/*
* linux/arch/cris/kernel/time.c
*
* Copyright (C) 1991, 1992, 1995 Linus Torvalds
* Linux/CRIS specific code:
*
* Authors: Bjorn Wesen
- * Johan Adolfsson
+ * Johan Adolfsson
*
*/
#endif
#ifdef CONFIG_PROFILING
- profile_tick(CPU_PROFILING);
+ profile_tick(CPU_PROFILING);
#endif
}
+unsigned long long sched_clock(void)
+{
+ return (unsigned long long)jiffies * (1000000000 / HZ) +
+ get_ns_in_jiffie();
+}
+
static int
__init init_udelay(void)
{
-/* $Id: traps.c,v 1.11 2005/01/24 16:03:19 orjanf Exp $
- *
+/*
* linux/arch/cris/traps.c
*
- * Here we handle the break vectors not used by the system call
- * mechanism, as well as some general stack/register dumping
+ * Here we handle the break vectors not used by the system call
+ * mechanism, as well as some general stack/register dumping
* things.
- *
- * Copyright (C) 2000-2002 Axis Communications AB
+ *
+ * Copyright (C) 2000-2007 Axis Communications AB
*
* Authors: Bjorn Wesen
- * Hans-Peter Nilsson
+ * Hans-Peter Nilsson
*
*/
#include <linux/init.h>
#include <linux/module.h>
+
#include <asm/pgtable.h>
#include <asm/uaccess.h>
+extern void arch_enable_nmi(void);
+extern void stop_watchdog(void);
+extern void reset_watchdog(void);
+extern void show_registers(struct pt_regs *regs);
+
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+extern void handle_BUG(struct pt_regs *regs);
+#else
+#define handle_BUG(regs)
+#endif
+
static int kstack_depth_to_print = 24;
-extern int raw_printk(const char *fmt, ...);
+void (*nmi_handler)(struct pt_regs *);
-void show_trace(unsigned long * stack)
+void
+show_trace(unsigned long *stack)
{
unsigned long addr, module_start, module_end;
extern char _stext, _etext;
int i;
- raw_printk("\nCall Trace: ");
+ printk("\nCall Trace: ");
- i = 1;
- module_start = VMALLOC_START;
- module_end = VMALLOC_END;
+ i = 1;
+ module_start = VMALLOC_START;
+ module_end = VMALLOC_END;
- while (((long) stack & (THREAD_SIZE-1)) != 0) {
- if (__get_user (addr, stack)) {
+ while (((long)stack & (THREAD_SIZE-1)) != 0) {
+ if (__get_user(addr, stack)) {
/* This message matches "failing address" marked
s390 in ksymoops, so lines containing it will
not be filtered out by ksymoops. */
- raw_printk ("Failing address 0x%lx\n", (unsigned long)stack);
+ printk("Failing address 0x%lx\n", (unsigned long)stack);
break;
}
stack++;
- /*
- * If the address is either in the text segment of the
- * kernel, or in the region which contains vmalloc'ed
- * memory, it *may* be the address of a calling
- * routine; if so, print it so that someone tracing
- * down the cause of the crash will be able to figure
- * out the call path that was taken.
- */
- if (((addr >= (unsigned long) &_stext) &&
- (addr <= (unsigned long) &_etext)) ||
- ((addr >= module_start) && (addr <= module_end))) {
- if (i && ((i % 8) == 0))
- raw_printk("\n ");
- raw_printk("[<%08lx>] ", addr);
- i++;
- }
- }
+ /*
+ * If the address is either in the text segment of the
+ * kernel, or in the region which contains vmalloc'ed
+ * memory, it *may* be the address of a calling
+ * routine; if so, print it so that someone tracing
+ * down the cause of the crash will be able to figure
+ * out the call path that was taken.
+ */
+ if (((addr >= (unsigned long)&_stext) &&
+ (addr <= (unsigned long)&_etext)) ||
+ ((addr >= module_start) && (addr <= module_end))) {
+ if (i && ((i % 8) == 0))
+ printk("\n ");
+ printk("[<%08lx>] ", addr);
+ i++;
+ }
+ }
}
/*
* with the ksymoops maintainer.
*/
-void
+void
show_stack(struct task_struct *task, unsigned long *sp)
{
- unsigned long *stack, addr;
- int i;
+ unsigned long *stack, addr;
+ int i;
/*
* debugging aid: "show_stack(NULL);" prints a
* back trace.
*/
- if(sp == NULL) {
+ if (sp == NULL) {
if (task)
sp = (unsigned long*)task->thread.ksp;
else
sp = (unsigned long*)rdsp();
}
- stack = sp;
+ stack = sp;
- raw_printk("\nStack from %08lx:\n ", (unsigned long)stack);
- for(i = 0; i < kstack_depth_to_print; i++) {
- if (((long) stack & (THREAD_SIZE-1)) == 0)
- break;
- if (i && ((i % 8) == 0))
- raw_printk("\n ");
- if (__get_user (addr, stack)) {
+ printk("\nStack from %08lx:\n ", (unsigned long)stack);
+ for (i = 0; i < kstack_depth_to_print; i++) {
+ if (((long)stack & (THREAD_SIZE-1)) == 0)
+ break;
+ if (i && ((i % 8) == 0))
+ printk("\n ");
+ if (__get_user(addr, stack)) {
/* This message matches "failing address" marked
s390 in ksymoops, so lines containing it will
not be filtered out by ksymoops. */
- raw_printk ("Failing address 0x%lx\n", (unsigned long)stack);
+ printk("Failing address 0x%lx\n", (unsigned long)stack);
break;
}
stack++;
- raw_printk("%08lx ", addr);
- }
+ printk("%08lx ", addr);
+ }
show_trace(sp);
}
-static void (*nmi_handler)(struct pt_regs*);
-extern void arch_enable_nmi(void);
+#if 0
+/* displays a short stack trace */
-void set_nmi_handler(void (*handler)(struct pt_regs*))
+int
+show_stack(void)
{
- nmi_handler = handler;
- arch_enable_nmi();
+ unsigned long *sp = (unsigned long *)rdusp();
+ int i;
+
+ printk("Stack dump [0x%08lx]:\n", (unsigned long)sp);
+ for (i = 0; i < 16; i++)
+ printk("sp + %d: 0x%08lx\n", i*4, sp[i]);
+ return 0;
}
+#endif
-void handle_nmi(struct pt_regs* regs)
+void
+dump_stack(void)
{
- if (nmi_handler)
- nmi_handler(regs);
+ show_stack(NULL, NULL);
+}
+EXPORT_SYMBOL(dump_stack);
+
+void
+set_nmi_handler(void (*handler)(struct pt_regs *))
+{
+ nmi_handler = handler;
+ arch_enable_nmi();
}
#ifdef CONFIG_DEBUG_NMI_OOPS
-void oops_nmi_handler(struct pt_regs* regs)
+void
+oops_nmi_handler(struct pt_regs *regs)
{
- stop_watchdog();
- raw_printk("NMI!\n");
- show_registers(regs);
+ stop_watchdog();
+ oops_in_progress = 1;
+ printk("NMI!\n");
+ show_registers(regs);
+ oops_in_progress = 0;
}
-static int
-__init oops_nmi_register(void)
+static int __init
+oops_nmi_register(void)
{
- set_nmi_handler(oops_nmi_handler);
- return 0;
+ set_nmi_handler(oops_nmi_handler);
+ return 0;
}
__initcall(oops_nmi_register);
#endif
-#if 0
-/* displays a short stack trace */
-
-int
-show_stack()
+/*
+ * This gets called from entry.S when the watchdog has bitten. Show something
+ * similiar to an Oops dump, and if the kernel is configured to be a nice
+ * doggy, then halt instead of reboot.
+ */
+void
+watchdog_bite_hook(struct pt_regs *regs)
{
- unsigned long *sp = (unsigned long *)rdusp();
- int i;
- raw_printk("Stack dump [0x%08lx]:\n", (unsigned long)sp);
- for(i = 0; i < 16; i++)
- raw_printk("sp + %d: 0x%08lx\n", i*4, sp[i]);
- return 0;
-}
+#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
+ local_irq_disable();
+ stop_watchdog();
+ show_registers(regs);
+
+ while (1)
+ ; /* Do nothing. */
+#else
+ show_registers(regs);
#endif
+}
-void dump_stack(void)
+/* This is normally the Oops function. */
+void
+die_if_kernel(const char *str, struct pt_regs *regs, long err)
{
- show_stack(NULL, NULL);
-}
+ if (user_mode(regs))
+ return;
-EXPORT_SYMBOL(dump_stack);
+#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
+ /*
+ * This printout might take too long and could trigger
+ * the watchdog normally. If NICE_DOGGY is set, simply
+ * stop the watchdog during the printout.
+ */
+ stop_watchdog();
+#endif
-void __init
-trap_init(void)
-{
- /* Nothing needs to be done */
+ handle_BUG(regs);
+
+ printk("%s: %04lx\n", str, err & 0xffff);
+
+ show_registers(regs);
+
+ oops_in_progress = 0;
+
+#ifdef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
+ reset_watchdog();
+#endif
+ do_exit(SIGSEGV);
}
-void spinning_cpu(void* addr)
+void __init
+trap_init(void)
{
- raw_printk("CPU %d spinning on %X\n", smp_processor_id(), addr);
- dump_stack();
+ /* Nothing needs to be done */
}
/*
* linux/arch/cris/mm/fault.c
*
- * Copyright (C) 2000, 2001 Axis Communications AB
- *
- * Authors: Bjorn Wesen
- *
- * $Log: fault.c,v $
- * Revision 1.20 2005/03/04 08:16:18 starvik
- * Merge of Linux 2.6.11.
- *
- * Revision 1.19 2005/01/14 10:07:59 starvik
- * Fixed warning.
- *
- * Revision 1.18 2005/01/12 08:10:14 starvik
- * Re-added the change of frametype when handling kernel page fault fixup
- * for v10. This is necessary to avoid that the CPU remakes the faulting
- * access.
- *
- * Revision 1.17 2005/01/11 13:53:05 starvik
- * Use raw_printk.
- *
- * Revision 1.16 2004/12/17 11:39:41 starvik
- * SMP support.
- *
- * Revision 1.15 2004/11/23 18:36:18 starvik
- * Stack is now non-executable.
- * Signal handler trampolines are placed in a reserved page mapped into all
- * processes.
- *
- * Revision 1.14 2004/11/23 07:10:21 starvik
- * Moved find_fixup_code to generic code.
- *
- * Revision 1.13 2004/11/23 07:00:54 starvik
- * Actually use the execute permission bit in the MMU. This makes it possible
- * to prevent e.g. attacks where executable code is put on the stack.
- *
- * Revision 1.12 2004/09/29 06:16:04 starvik
- * Use instruction_pointer
- *
- * Revision 1.11 2004/05/14 07:58:05 starvik
- * Merge of changes from 2.4
- *
- * Revision 1.10 2003/10/27 14:51:24 starvik
- * Removed debugcode
- *
- * Revision 1.9 2003/10/27 14:50:42 starvik
- * Changed do_page_fault signature
- *
- * Revision 1.8 2003/07/04 13:02:48 tobiasa
- * Moved code snippet from arch/cris/mm/fault.c that searches for fixup code
- * to separate function in arch-specific files.
- *
- * Revision 1.7 2003/01/22 06:48:38 starvik
- * Fixed warnings issued by GCC 3.2.1
- *
- * Revision 1.6 2003/01/09 14:42:52 starvik
- * Merge of Linux 2.5.55
- *
- * Revision 1.5 2002/12/11 14:44:48 starvik
- * Extracted v10 (ETRAX 100LX) specific stuff to arch/cris/arch-v10/mm
- *
- * Revision 1.4 2002/11/13 15:10:28 starvik
- * pte_offset has been renamed to pte_offset_kernel
- *
- * Revision 1.3 2002/11/05 06:45:13 starvik
- * Merge of Linux 2.5.45
- *
- * Revision 1.2 2001/12/18 13:35:22 bjornw
- * Applied the 2.4.13->2.4.16 CRIS patch to 2.5.1 (is a copy of 2.4.15).
- *
- * Revision 1.20 2001/11/22 13:34:06 bjornw
- * * Bug workaround (LX TR89): force a rerun of the whole of an interrupted
- * unaligned write, because the second half of the write will be corrupted
- * otherwise. Affected unaligned writes spanning not-yet mapped pages.
- * * Optimization: use the wr_rd bit in R_MMU_CAUSE to know whether a miss
- * was due to a read or a write (before we didn't know this until the next
- * restart of the interrupted instruction, thus wasting one fault-irq)
- *
- * Revision 1.19 2001/11/12 19:02:10 pkj
- * Fixed compiler warnings.
- *
- * Revision 1.18 2001/07/18 22:14:32 bjornw
- * Enable interrupts in the bulk of do_page_fault
- *
- * Revision 1.17 2001/07/18 13:07:23 bjornw
- * * Detect non-existant PTE's in vmalloc pmd synchronization
- * * Remove comment about fast-paths for VMALLOC_START etc, because all that
- * was totally bogus anyway it turned out :)
- * * Fix detection of vmalloc-area synchronization
- * * Add some comments
- *
- * Revision 1.16 2001/06/13 00:06:08 bjornw
- * current_pgd should be volatile
- *
- * Revision 1.15 2001/06/13 00:02:23 bjornw
- * Use a separate variable to store the current pgd to avoid races in schedule
- *
- * Revision 1.14 2001/05/16 17:41:07 hp
- * Last comment tweak further tweaked.
- *
- * Revision 1.13 2001/05/15 00:58:44 hp
- * Expand a bit on the comment why we compare address >= TASK_SIZE rather
- * than >= VMALLOC_START.
- *
- * Revision 1.12 2001/04/04 10:51:14 bjornw
- * mmap_sem is grabbed for reading
- *
- * Revision 1.11 2001/03/23 07:36:07 starvik
- * Corrected according to review remarks
- *
- * Revision 1.10 2001/03/21 16:10:11 bjornw
- * CRIS_FRAME_FIXUP not needed anymore, use FRAME_NORMAL
- *
- * Revision 1.9 2001/03/05 13:22:20 bjornw
- * Spell-fix and fix in vmalloc_fault handling
- *
- * Revision 1.8 2000/11/22 14:45:31 bjornw
- * * 2.4.0-test10 removed the set_pgdir instantaneous kernel global mapping
- * into all processes. Instead we fill in the missing PTE entries on demand.
- *
- * Revision 1.7 2000/11/21 16:39:09 bjornw
- * fixup switches frametype
- *
- * Revision 1.6 2000/11/17 16:54:08 bjornw
- * More detailed siginfo reporting
+ * Copyright (C) 2000-2006 Axis Communications AB
*
+ * Authors: Bjorn Wesen
*
*/
extern int find_fixup_code(struct pt_regs *);
extern void die_if_kernel(const char *, struct pt_regs *, long);
-extern int raw_printk(const char *fmt, ...);
/* debug of low-level TLB reload */
#undef DEBUG
* address.
*
* error_code:
- * bit 0 == 0 means no page found, 1 means protection fault
- * bit 1 == 0 means read, 1 means write
+ * bit 0 == 0 means no page found, 1 means protection fault
+ * bit 1 == 0 means read, 1 means write
*
* If this routine detects a bad access, it returns 1, otherwise it
* returns 0.
siginfo_t info;
int fault;
- D(printk("Page fault for %lX on %X at %lX, prot %d write %d\n",
- address, smp_processor_id(), instruction_pointer(regs),
- protection, writeaccess));
+ D(printk(KERN_DEBUG
+ "Page fault for %lX on %X at %lX, prot %d write %d\n",
+ address, smp_processor_id(), instruction_pointer(regs),
+ protection, writeaccess));
tsk = current;
* context, we must not take the fault..
*/
- if (in_atomic() || !mm)
+ if (in_interrupt() || !mm)
goto no_context;
down_read(&mm->mmap_sem);
/* info.si_code has been set above */
info.si_addr = (void *)address;
force_sig_info(SIGSEGV, &info, tsk);
+ printk(KERN_NOTICE "%s (pid %d) segfaults for page "
+ "address %08lx at pc %08lx\n",
+ tsk->comm, tsk->pid, address, instruction_pointer(regs));
return;
}
/* Are we prepared to handle this kernel fault?
*
- * (The kernel has valid exception-points in the source
+ * (The kernel has valid exception-points in the source
* when it acesses user-memory. When it fails in one
* of those points, we find it in a table and do a jump
* to some fixup code that loads an appropriate error
* terminate things with extreme prejudice.
*/
- if ((unsigned long) (address) < PAGE_SIZE)
- raw_printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
- else
- raw_printk(KERN_ALERT "Unable to handle kernel access");
- raw_printk(" at virtual address %08lx\n",address);
-
- die_if_kernel("Oops", regs, (writeaccess << 1) | protection);
+ if (!oops_in_progress) {
+ oops_in_progress = 1;
+ if ((unsigned long) (address) < PAGE_SIZE)
+ printk(KERN_ALERT "Unable to handle kernel NULL "
+ "pointer dereference");
+ else
+ printk(KERN_ALERT "Unable to handle kernel access"
+ " at virtual address %08lx\n", address);
+
+ die_if_kernel("Oops", regs, (writeaccess << 1) | protection);
+ oops_in_progress = 0;
+ }
do_exit(SIGKILL);
up_read(&mm->mmap_sem);
printk("VM: killing process %s\n", tsk->comm);
if (user_mode(regs))
- do_group_exit(SIGKILL);
+ do_exit(SIGKILL);
goto no_context;
do_sigbus:
/* Since we're two-level, we don't need to do both
* set_pgd and set_pmd (they do the same thing). If
* we go three-level at some point, do the right thing
- * with pgd_present and set_pgd here.
- *
+ * with pgd_present and set_pgd here.
+ *
* Also, since the vmalloc area is global, we don't
* need to copy individual PTE's, it is enough to
* copy the pgd pointer into the pte page of the
*
* Authors: Bjorn Wesen (bjornw@axis.com)
*
- * $Log: init.c,v $
- * Revision 1.11 2004/05/28 09:28:56 starvik
- * Calculation of loops_per_usec moved because initialization order has changed
- * in Linux 2.6.
- *
- * Revision 1.10 2004/05/14 07:58:05 starvik
- * Merge of changes from 2.4
- *
- * Revision 1.9 2003/07/04 08:27:54 starvik
- * Merge of Linux 2.5.74
- *
- * Revision 1.8 2003/04/09 05:20:48 starvik
- * Merge of Linux 2.5.67
- *
- * Revision 1.7 2003/01/22 06:48:38 starvik
- * Fixed warnings issued by GCC 3.2.1
- *
- * Revision 1.6 2002/12/11 14:44:48 starvik
- * Extracted v10 (ETRAX 100LX) specific stuff to arch/cris/arch-v10/mm
- *
- * Revision 1.5 2002/11/18 07:37:37 starvik
- * Added cache bug workaround (from Linux 2.4)
- *
- * Revision 1.4 2002/11/13 15:40:24 starvik
- * Removed the page table cache stuff (as done in other archs)
- *
- * Revision 1.3 2002/11/05 06:45:13 starvik
- * Merge of Linux 2.5.45
- *
- * Revision 1.2 2001/12/18 13:35:22 bjornw
- * Applied the 2.4.13->2.4.16 CRIS patch to 2.5.1 (is a copy of 2.4.15).
- *
- * Revision 1.31 2001/11/13 16:22:00 bjornw
- * Skip calculating totalram and sharedram in si_meminfo
- *
- * Revision 1.30 2001/11/12 19:02:10 pkj
- * Fixed compiler warnings.
- *
- * Revision 1.29 2001/07/25 16:09:50 bjornw
- * val->sharedram will stay 0
- *
- * Revision 1.28 2001/06/28 16:30:17 bjornw
- * Oops. This needs to wait until 2.4.6 is merged
- *
- * Revision 1.27 2001/06/28 14:04:07 bjornw
- * Fill in sharedram
- *
- * Revision 1.26 2001/06/18 06:36:02 hp
- * Enable free_initmem of __init-type pages
- *
- * Revision 1.25 2001/06/13 00:02:23 bjornw
- * Use a separate variable to store the current pgd to avoid races in schedule
- *
- * Revision 1.24 2001/05/15 00:52:20 hp
- * Only map segment 0xa as seg if CONFIG_JULIETTE
- *
- * Revision 1.23 2001/04/04 14:35:40 bjornw
- * * Removed get_pte_slow and friends (2.4.3 change)
- * * Removed bad_pmd handling (2.4.3 change)
- *
- * Revision 1.22 2001/04/04 13:38:04 matsfg
- * Moved ioremap to a separate function instead
- *
- * Revision 1.21 2001/03/27 09:28:33 bjornw
- * ioremap used too early - lets try it in mem_init instead
- *
- * Revision 1.20 2001/03/23 07:39:21 starvik
- * Corrected according to review remarks
- *
- * Revision 1.19 2001/03/15 14:25:17 bjornw
- * More general shadow registers and ioremaped addresses for external I/O
- *
- * Revision 1.18 2001/02/23 12:46:44 bjornw
- * * 0xc was not CSE1; 0x8 is, same as uncached flash, so we move the uncached
- * flash during CRIS_LOW_MAP from 0xe to 0x8 so both the flash and the I/O
- * is mapped straight over (for !CRIS_LOW_MAP the uncached flash is still 0xe)
- *
- * Revision 1.17 2001/02/22 15:05:21 bjornw
- * Map 0x9 straight over during LOW_MAP to allow for memory mapped LEDs
- *
- * Revision 1.16 2001/02/22 15:02:35 bjornw
- * Map 0xc straight over during LOW_MAP to allow for memory mapped I/O
- *
- * Revision 1.15 2001/01/10 21:12:10 bjornw
- * loops_per_sec -> loops_per_jiffy
- *
- * Revision 1.14 2000/11/22 16:23:20 bjornw
- * Initialize totalhigh counters to 0 to make /proc/meminfo look nice.
- *
- * Revision 1.13 2000/11/21 16:37:51 bjornw
- * Temporarily disable initmem freeing
- *
- * Revision 1.12 2000/11/21 13:55:07 bjornw
- * Use CONFIG_CRIS_LOW_MAP for the low VM map instead of explicit CPU type
- *
- * Revision 1.11 2000/10/06 12:38:22 bjornw
- * Cast empty_bad_page correctly (should really be of * type from the start..
- *
- * Revision 1.10 2000/10/04 16:53:57 bjornw
- * Fix memory-map due to LX features
- *
- * Revision 1.9 2000/09/13 15:47:49 bjornw
- * Wrong count in reserved-pages loop
- *
- * Revision 1.8 2000/09/13 14:35:10 bjornw
- * 2.4.0-test8 added a new arg to free_area_init_node
- *
- * Revision 1.7 2000/08/17 15:35:55 bjornw
- * 2.4.0-test6 removed MAP_NR and inserted virt_to_page
- *
- *
*/
#include <linux/init.h>
bool
default y
+config HZ
+ int
+ default 1000
+
mainmenu "Fujitsu FR-V Kernel Configuration"
source "init/Kconfig"
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
return pte;
}
-struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
struct page *page;
#else
page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0);
#endif
- if (page)
+ if (page) {
clear_highpage(page);
- flush_dcache_page(page);
+ pgtable_page_ctor(page);
+ flush_dcache_page(page);
+ }
return page;
}
bool
default y
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
config NO_IOPORT
def_bool y
bool
default n
+config HZ
+ int
+ default 100
+
source "init/Kconfig"
source "arch/h8300/Kconfig.cpu"
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
data8 sys_fchmodat
data8 sys_faccessat
data8 sys_pselect6
- data8 sys_ppoll
+ data8 sys_ppoll // 1295
data8 sys_unshare
data8 sys_splice
data8 sys_set_robust_list
data8 sys_signalfd
data8 sys_ni_syscall
data8 sys_eventfd
+ data8 sys_timerfd_create // 1310
+ data8 sys_timerfd_settime
+ data8 sys_timerfd_gettime
.org sys_call_table + 8*NR_syscalls // guard against failures to increase NR_syscalls
* Copyright (C) 2000 Intel
* Copyright (C) Chuck Fleckenstein <cfleck@co.intel.com>
*
- * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
+ * Copyright (C) 1999, 2004-2008 Silicon Graphics, Inc.
* Copyright (C) Vijay Chander <vijay@engr.sgi.com>
*
* Copyright (C) 2006 FUJITSU LIMITED
/* Caller prevents this from being called after init */
static void * __init_refok mca_bootmem(void)
{
- void *p;
-
- p = alloc_bootmem(sizeof(struct ia64_mca_cpu) * NR_CPUS +
- KERNEL_STACK_SIZE);
- return (void *)ALIGN((unsigned long)p, KERNEL_STACK_SIZE);
+ return __alloc_bootmem(sizeof(struct ia64_mca_cpu),
+ KERNEL_STACK_SIZE, 0);
}
/* Do per-CPU MCA-related initialization. */
ia64_mca_cpu_init(void *cpu_data)
{
void *pal_vaddr;
+ void *data;
+ long sz = sizeof(struct ia64_mca_cpu);
+ int cpu = smp_processor_id();
static int first_time = 1;
- if (first_time) {
- void *mca_data;
- int cpu;
-
- first_time = 0;
- mca_data = mca_bootmem();
- for (cpu = 0; cpu < NR_CPUS; cpu++) {
- format_mca_init_stack(mca_data,
- offsetof(struct ia64_mca_cpu, mca_stack),
- "MCA", cpu);
- format_mca_init_stack(mca_data,
- offsetof(struct ia64_mca_cpu, init_stack),
- "INIT", cpu);
- __per_cpu_mca[cpu] = __pa(mca_data);
- mca_data += sizeof(struct ia64_mca_cpu);
- }
- }
-
/*
- * The MCA info structure was allocated earlier and its
- * physical address saved in __per_cpu_mca[cpu]. Copy that
- * address * to ia64_mca_data so we can access it as a per-CPU
- * variable.
+ * Structure will already be allocated if cpu has been online,
+ * then offlined.
*/
- __get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()];
+ if (__per_cpu_mca[cpu]) {
+ data = __va(__per_cpu_mca[cpu]);
+ } else {
+ if (first_time) {
+ data = mca_bootmem();
+ first_time = 0;
+ } else
+ data = page_address(alloc_pages_node(numa_node_id(),
+ GFP_KERNEL, get_order(sz)));
+ if (!data)
+ panic("Could not allocate MCA memory for cpu %d\n",
+ cpu);
+ }
+ format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, mca_stack),
+ "MCA", cpu);
+ format_mca_init_stack(data, offsetof(struct ia64_mca_cpu, init_stack),
+ "INIT", cpu);
+ __get_cpu_var(ia64_mca_data) = __per_cpu_mca[cpu] = __pa(data);
/*
* Stash away a copy of the PTE needed to map the per-CPU page.
if (task != current) put_task_struct(task);
}
-static inline void
-pfm_set_task_notify(struct task_struct *task)
-{
- struct thread_info *info;
-
- info = (struct thread_info *) ((char *) task + IA64_TASK_SIZE);
- set_bit(TIF_PERFMON_WORK, &info->flags);
-}
-
-static inline void
-pfm_clear_task_notify(void)
-{
- clear_thread_flag(TIF_PERFMON_WORK);
-}
-
static inline void
pfm_reserve_page(unsigned long a)
{
PFM_SET_WORK_PENDING(task, 1);
- pfm_set_task_notify(task);
+ tsk_set_notify_resume(task);
/*
* XXX: send reschedule if task runs on another CPU
PFM_SET_WORK_PENDING(current, 0);
- pfm_clear_task_notify();
+ tsk_clear_notify_resume(current);
regs = task_pt_regs(current);
* when coming from ctxsw, current still points to the
* previous task, therefore we must work with task and not current.
*/
- pfm_set_task_notify(task);
+ tsk_set_notify_resume(task);
}
/*
* defer until state is changed (shorten spin window). the context is locked
#include "sigframe.h"
void (*ia64_mark_idle)(int);
-static DEFINE_PER_CPU(unsigned int, cpu_idle_state);
unsigned long boot_option_idle_override = 0;
EXPORT_SYMBOL(boot_option_idle_override);
show_stack(NULL, NULL);
}
+void tsk_clear_notify_resume(struct task_struct *tsk)
+{
+#ifdef CONFIG_PERFMON
+ if (tsk->thread.pfm_needs_checking)
+ return;
+#endif
+ if (test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_RSE))
+ return;
+ clear_ti_thread_flag(task_thread_info(tsk), TIF_NOTIFY_RESUME);
+}
+
void
do_notify_resume_user (sigset_t *unused, struct sigscratch *scr, long in_syscall)
{
/* deal with pending signal delivery */
if (test_thread_flag(TIF_SIGPENDING)||test_thread_flag(TIF_RESTORE_SIGMASK))
ia64_do_signal(scr, in_syscall);
+
+ /* copy user rbs to kernel rbs */
+ if (unlikely(test_thread_flag(TIF_RESTORE_RSE)))
+ ia64_sync_krbs();
}
static int pal_halt = 1;
}
#endif /* CONFIG_HOTPLUG_CPU */
-void cpu_idle_wait(void)
+static void do_nothing(void *unused)
{
- unsigned int cpu, this_cpu = get_cpu();
- cpumask_t map;
- cpumask_t tmp = current->cpus_allowed;
-
- set_cpus_allowed(current, cpumask_of_cpu(this_cpu));
- put_cpu();
-
- cpus_clear(map);
- for_each_online_cpu(cpu) {
- per_cpu(cpu_idle_state, cpu) = 1;
- cpu_set(cpu, map);
- }
-
- __get_cpu_var(cpu_idle_state) = 0;
+}
- wmb();
- do {
- ssleep(1);
- for_each_online_cpu(cpu) {
- if (cpu_isset(cpu, map) && !per_cpu(cpu_idle_state, cpu))
- cpu_clear(cpu, map);
- }
- cpus_and(map, map, cpu_online_map);
- } while (!cpus_empty(map));
- set_cpus_allowed(current, tmp);
+/*
+ * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
+ * pm_idle and update to new pm_idle value. Required while changing pm_idle
+ * handler on SMP systems.
+ *
+ * Caller must have changed pm_idle to the new value before the call. Old
+ * pm_idle value will not be used by any CPU after the return of this function.
+ */
+void cpu_idle_wait(void)
+{
+ smp_mb();
+ /* kick all the CPUs so that they exit out of pm_idle */
+ smp_call_function(do_nothing, NULL, 0, 1);
}
EXPORT_SYMBOL_GPL(cpu_idle_wait);
#ifdef CONFIG_SMP
min_xtp();
#endif
- if (__get_cpu_var(cpu_idle_state))
- __get_cpu_var(cpu_idle_state) = 0;
-
rmb();
if (mark_idle)
(*mark_idle)(1);
return 0;
}
+static long
+ia64_sync_kernel_rbs (struct task_struct *child, struct switch_stack *sw,
+ unsigned long user_rbs_start, unsigned long user_rbs_end)
+{
+ unsigned long addr, val;
+ long ret;
+
+ /* now copy word for word from user rbs to kernel rbs: */
+ for (addr = user_rbs_start; addr < user_rbs_end; addr += 8) {
+ if (access_process_vm(child, addr, &val, sizeof(val), 0)
+ != sizeof(val))
+ return -EIO;
+
+ ret = ia64_poke(child, sw, user_rbs_end, addr, val);
+ if (ret < 0)
+ return ret;
+ }
+ return 0;
+}
+
+typedef long (*syncfunc_t)(struct task_struct *, struct switch_stack *,
+ unsigned long, unsigned long);
+
+static void do_sync_rbs(struct unw_frame_info *info, void *arg)
+{
+ struct pt_regs *pt;
+ unsigned long urbs_end;
+ syncfunc_t fn = arg;
+
+ if (unw_unwind_to_user(info) < 0)
+ return;
+ pt = task_pt_regs(info->task);
+ urbs_end = ia64_get_user_rbs_end(info->task, pt, NULL);
+
+ fn(info->task, info->sw, pt->ar_bspstore, urbs_end);
+}
+
+/*
+ * when a thread is stopped (ptraced), debugger might change thread's user
+ * stack (change memory directly), and we must avoid the RSE stored in kernel
+ * to override user stack (user space's RSE is newer than kernel's in the
+ * case). To workaround the issue, we copy kernel RSE to user RSE before the
+ * task is stopped, so user RSE has updated data. we then copy user RSE to
+ * kernel after the task is resummed from traced stop and kernel will use the
+ * newer RSE to return to user. TIF_RESTORE_RSE is the flag to indicate we need
+ * synchronize user RSE to kernel.
+ */
+void ia64_ptrace_stop(void)
+{
+ if (test_and_set_tsk_thread_flag(current, TIF_RESTORE_RSE))
+ return;
+ tsk_set_notify_resume(current);
+ unw_init_running(do_sync_rbs, ia64_sync_user_rbs);
+}
+
+/*
+ * This is called to read back the register backing store.
+ */
+void ia64_sync_krbs(void)
+{
+ clear_tsk_thread_flag(current, TIF_RESTORE_RSE);
+ tsk_clear_notify_resume(current);
+
+ unw_init_running(do_sync_rbs, ia64_sync_kernel_rbs);
+}
+
+/*
+ * After PTRACE_ATTACH, a thread's register backing store area in user
+ * space is assumed to contain correct data whenever the thread is
+ * stopped. arch_ptrace_stop takes care of this on tracing stops.
+ * But if the child was already stopped for job control when we attach
+ * to it, then it might not ever get into ptrace_stop by the time we
+ * want to examine the user memory containing the RBS.
+ */
+void
+ptrace_attach_sync_user_rbs (struct task_struct *child)
+{
+ int stopped = 0;
+ struct unw_frame_info info;
+
+ /*
+ * If the child is in TASK_STOPPED, we need to change that to
+ * TASK_TRACED momentarily while we operate on it. This ensures
+ * that the child won't be woken up and return to user mode while
+ * we are doing the sync. (It can only be woken up for SIGKILL.)
+ */
+
+ read_lock(&tasklist_lock);
+ if (child->signal) {
+ spin_lock_irq(&child->sighand->siglock);
+ if (child->state == TASK_STOPPED &&
+ !test_and_set_tsk_thread_flag(child, TIF_RESTORE_RSE)) {
+ tsk_set_notify_resume(child);
+
+ child->state = TASK_TRACED;
+ stopped = 1;
+ }
+ spin_unlock_irq(&child->sighand->siglock);
+ }
+ read_unlock(&tasklist_lock);
+
+ if (!stopped)
+ return;
+
+ unw_init_from_blocked_task(&info, child);
+ do_sync_rbs(&info, ia64_sync_user_rbs);
+
+ /*
+ * Now move the child back into TASK_STOPPED if it should be in a
+ * job control stop, so that SIGCONT can be used to wake it up.
+ */
+ read_lock(&tasklist_lock);
+ if (child->signal) {
+ spin_lock_irq(&child->sighand->siglock);
+ if (child->state == TASK_TRACED &&
+ (child->signal->flags & SIGNAL_STOP_STOPPED)) {
+ child->state = TASK_STOPPED;
+ }
+ spin_unlock_irq(&child->sighand->siglock);
+ }
+ read_unlock(&tasklist_lock);
+}
+
static inline int
thread_matches (struct task_struct *thread, unsigned long addr)
{
struct task_struct *child;
struct switch_stack *sw;
long ret;
+ struct unw_frame_info info;
lock_kernel();
ret = -EPERM;
if (request == PTRACE_ATTACH) {
ret = ptrace_attach(child);
+ if (!ret)
+ arch_ptrace_attach(child);
goto out_tsk;
}
/* write the word at location addr */
urbs_end = ia64_get_user_rbs_end(child, pt, NULL);
ret = ia64_poke(child, sw, urbs_end, addr, data);
+
+ /* Make sure user RBS has the latest data */
+ unw_init_from_blocked_task(&info, child);
+ do_sync_rbs(&info, ia64_sync_user_rbs);
+
goto out_tsk;
case PTRACE_PEEKUSR:
&& (current->ptrace & PT_PTRACED))
syscall_trace();
+ /* copy user rbs to kernel rbs */
+ if (test_thread_flag(TIF_RESTORE_RSE))
+ ia64_sync_krbs();
+
if (unlikely(current->audit_context)) {
long syscall;
int arch;
|| test_thread_flag(TIF_SINGLESTEP))
&& (current->ptrace & PT_PTRACED))
syscall_trace();
+
+ /* copy user rbs to kernel rbs */
+ if (test_thread_flag(TIF_RESTORE_RSE))
+ ia64_sync_krbs();
}
#endif
static struct clocksource clocksource_itc = {
- .name = "itc",
- .rating = 350,
- .read = itc_get_cycles,
- .mask = CLOCKSOURCE_MASK(64),
- .mult = 0, /*to be caluclated*/
- .shift = 16,
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+ .name = "itc",
+ .rating = 350,
+ .read = itc_get_cycles,
+ .mask = CLOCKSOURCE_MASK(64),
+ .mult = 0, /*to be calculated*/
+ .shift = 16,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static struct clocksource *itc_clocksource;
config NO_DMA
def_bool y
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
+config HZ
+ int
+ default 100
+
source "init/Kconfig"
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
config NO_DMA
def_bool SUN3
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
+config HZ
+ int
+ default 100
+
mainmenu "Linux/68k Kernel Configuration"
source "init/Kconfig"
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/reboot.h>
#include <linux/init_task.h>
#include <linux/mqueue.h>
}
EXPORT_SYMBOL(dump_fpu);
-/*
- * fill in the user structure for a core dump..
- */
-void dump_thread(struct pt_regs * regs, struct user * dump)
-{
- struct switch_stack *sw;
-
-/* changed the size calculations - should hopefully work better. lbt */
- dump->magic = CMAGIC;
- dump->start_code = 0;
- dump->start_stack = rdusp() & ~(PAGE_SIZE - 1);
- dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
- dump->u_dsize = ((unsigned long) (current->mm->brk +
- (PAGE_SIZE-1))) >> PAGE_SHIFT;
- dump->u_dsize -= dump->u_tsize;
- dump->u_ssize = 0;
-
- if (dump->start_stack < TASK_SIZE)
- dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;
-
- dump->u_ar0 = offsetof(struct user, regs);
- sw = ((struct switch_stack *)regs) - 1;
- dump->regs.d1 = regs->d1;
- dump->regs.d2 = regs->d2;
- dump->regs.d3 = regs->d3;
- dump->regs.d4 = regs->d4;
- dump->regs.d5 = regs->d5;
- dump->regs.d6 = sw->d6;
- dump->regs.d7 = sw->d7;
- dump->regs.a0 = regs->a0;
- dump->regs.a1 = regs->a1;
- dump->regs.a2 = regs->a2;
- dump->regs.a3 = sw->a3;
- dump->regs.a4 = sw->a4;
- dump->regs.a5 = sw->a5;
- dump->regs.a6 = sw->a6;
- dump->regs.d0 = regs->d0;
- dump->regs.orig_d0 = regs->orig_d0;
- dump->regs.stkadj = regs->stkadj;
- dump->regs.sr = regs->sr;
- dump->regs.pc = regs->pc;
- dump->regs.fmtvec = (regs->format << 12) | regs->vector;
- /* dump floating point stuff */
- dump->u_fpvalid = dump_fpu (regs, &dump->m68kfp);
-}
-EXPORT_SYMBOL(dump_thread);
-
/*
* sys_execve() executes a new program.
*/
static void c_stop(struct seq_file *m, void *v)
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/module.h>
-#include <linux/a.out.h>
#include <linux/user.h>
#include <linux/string.h>
#include <linux/linkage.h>
config NO_IOPORT
def_bool y
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
source "init/Kconfig"
menu "Processor type and features"
running more threads on a system and also reduces the pressure
on the VM subsystem for higher order allocations.
+config HZ
+ int
+ default 1000 if CLEOPATRA
+ default 100
+
comment "RAM configuration"
config RAMBASE
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
init_8259A(0);
- for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++)
+ for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
+ set_irq_probe(i);
+ }
setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
}
return;
pp = (struct prda *) v;
- pp->prda_sys.t_pid = current->pid;
+ pp->prda_sys.t_pid = task_pid_vnr(current);
pp->prda_sys.t_prid = read_c0_prid();
- pp->prda_sys.t_rpid = current->pid;
+ pp->prda_sys.t_rpid = task_pid_vnr(current);
/* We leave the rest set to zero */
}
prstatus.pr_info.si_signo = prstatus.pr_cursig = signr;
prstatus.pr_sigpend = current->pending.signal.sig[0];
prstatus.pr_sighold = current->blocked.sig[0];
- psinfo.pr_pid = prstatus.pr_pid = current->pid;
- psinfo.pr_ppid = prstatus.pr_ppid = current->parent->pid;
- psinfo.pr_pgrp = prstatus.pr_pgrp = task_pgrp_nr(current);
- psinfo.pr_sid = prstatus.pr_sid = task_session_nr(current);
- if (current->pid == current->tgid) {
+ psinfo.pr_pid = prstatus.pr_pid = task_pid_vnr(current);
+ psinfo.pr_ppid = prstatus.pr_ppid = task_pid_vnr(current->parent);
+ psinfo.pr_pgrp = prstatus.pr_pgrp = task_pgrp_vnr(current);
+ psinfo.pr_sid = prstatus.pr_sid = task_session_vnr(current);
+ if (thread_group_leader(current)) {
/*
* This is the record for the group leader. Add in the
* cumulative times of previous dead threads. This total
#define W_MASK (W_EXITED | W_TRAPPED | W_STOPPED | W_CONT | W_NOHANG)
-asmlinkage int irix_waitsys(int type, int pid,
+asmlinkage int irix_waitsys(int type, int upid,
struct irix5_siginfo __user *info, int options,
struct rusage __user *ru)
{
+ struct pid *pid = NULL;
int flag, retval;
DECLARE_WAITQUEUE(wait, current);
struct task_struct *tsk;
if (type != IRIX_P_PID && type != IRIX_P_PGID && type != IRIX_P_ALL)
return -EINVAL;
+ if (type != IRIX_P_ALL)
+ pid = find_get_pid(upid);
add_wait_queue(¤t->signal->wait_chldexit, &wait);
repeat:
flag = 0;
tsk = current;
list_for_each(_p, &tsk->children) {
p = list_entry(_p, struct task_struct, sibling);
- if ((type == IRIX_P_PID) && p->pid != pid)
+ if ((type == IRIX_P_PID) && task_pid(p) != pid)
continue;
- if ((type == IRIX_P_PGID) && task_pgrp_nr(p) != pid)
+ if ((type == IRIX_P_PGID) && task_pgrp(p) != pid)
continue;
if ((p->exit_signal != SIGCHLD))
continue;
retval = __put_user(SIGCHLD, &info->sig);
retval |= __put_user(0, &info->code);
- retval |= __put_user(p->pid, &info->stuff.procinfo.pid);
+ retval |= __put_user(task_pid_vnr(p), &info->stuff.procinfo.pid);
retval |= __put_user((p->exit_code >> 8) & 0xff,
&info->stuff.procinfo.procdata.child.status);
retval |= __put_user(p->utime, &info->stuff.procinfo.procdata.child.utime);
getrusage(p, RUSAGE_BOTH, ru);
retval = __put_user(SIGCHLD, &info->sig);
retval |= __put_user(1, &info->code); /* CLD_EXITED */
- retval |= __put_user(p->pid, &info->stuff.procinfo.pid);
+ retval |= __put_user(task_pid_vnr(p), &info->stuff.procinfo.pid);
retval |= __put_user((p->exit_code >> 8) & 0xff,
&info->stuff.procinfo.procdata.child.status);
retval |= __put_user(p->utime,
retval |= __put_user(p->stime,
&info->stuff.procinfo.procdata.child.stime);
if (retval)
- return retval;
+ goto end_waitsys;
if (p->real_parent != p->parent) {
write_lock_irq(&tasklist_lock);
end_waitsys:
current->state = TASK_RUNNING;
remove_wait_queue(¤t->signal->wait_chldexit, &wait);
+ put_pid(pid);
return retval;
}
void __init init_IRQ(void)
{
+ int i;
+
+ for (i = 0; i < NR_IRQS; i++)
+ set_irq_noprobe(i);
+
arch_init_irq();
#ifdef CONFIG_KGDB
asmlinkage int irix_getpid(struct pt_regs *regs)
{
- regs->regs[3] = current->real_parent->pid;
- return current->pid;
+ regs->regs[3] = task_pid_vnr(current->real_parent);
+ return task_pid_vnr(current);
}
asmlinkage int irix_getuid(struct pt_regs *regs)
printk("[%s:%d] setpgrp(%d) ", current->comm, current->pid, flags);
#endif
if(!flags)
- error = task_pgrp_nr(current);
+ error = task_pgrp_vnr(current);
else
error = sys_setsid();
#ifdef DEBUG_PROCGRPS
- printk("returning %d\n", task_pgrp_nr(current));
+ printk("returning %d\n", error);
#endif
return error;
pid, pgrp);
#endif
if(!pid)
- pid = current->pid;
+ pid = task_pid_vnr(current);
/* Wheee, weird sysv thing... */
- if ((pgrp == 0) && (pid == current->pid))
+ if ((pgrp == 0) && (pid == task_pid_vnr(current)))
error = sys_setsid();
else
error = sys_setpgid(pid, pgrp);
--- /dev/null
+#
+# For a description of the syntax of this configuration file,
+# see Documentation/kbuild/kconfig-language.txt.
+#
+
+mainmenu "Linux Kernel Configuration"
+
+config MN10300
+ def_bool y
+
+config AM33
+ def_bool y
+
+config MMU
+ def_bool y
+
+config HIGHMEM
+ def_bool n
+
+config NUMA
+ def_bool n
+
+config UID16
+ def_bool y
+
+config RWSEM_GENERIC_SPINLOCK
+ def_bool y
+
+config RWSEM_XCHGADD_ALGORITHM
+ bool
+
+config GENERIC_HARDIRQS_NO__DO_IRQ
+ def_bool y
+
+config GENERIC_CALIBRATE_DELAY
+ def_bool y
+
+config GENERIC_FIND_NEXT_BIT
+ def_bool y
+
+config GENERIC_HWEIGHT
+ def_bool y
+
+config GENERIC_TIME
+ def_bool y
+
+config GENERIC_BUG
+ def_bool y
+
+config QUICKLIST
+ def_bool y
+
+config ARCH_HAS_ILOG2_U32
+ def_bool y
+
+config ARCH_SUPPORTS_AOUT
+ def_bool n
+
+# Use the generic interrupt handling code in kernel/irq/
+config GENERIC_HARDIRQS
+ def_bool y
+
+config HOTPLUG_CPU
+ def_bool n
+
+mainmenu "Matsushita MN10300/AM33 Kernel Configuration"
+
+source "init/Kconfig"
+
+
+menu "Matsushita MN10300 system setup"
+
+choice
+ prompt "Unit type"
+ default MN10300_UNIT_ASB2303
+ help
+ This option specifies board for which the kernel will be
+ compiled. It affects the external peripherals catered for.
+
+config MN10300_UNIT_ASB2303
+ bool "ASB2303"
+
+config MN10300_UNIT_ASB2305
+ bool "ASB2305"
+
+endchoice
+
+choice
+ prompt "Processor support"
+ default MN10300_PROC_MN103E010
+ help
+ This option specifies the processor for which the kernel will be
+ compiled. It affects the on-chip peripherals catered for.
+
+config MN10300_PROC_MN103E010
+ bool "MN103E010"
+ depends on MN10300_UNIT_ASB2303 || MN10300_UNIT_ASB2305
+ select MN10300_PROC_HAS_TTYSM0
+ select MN10300_PROC_HAS_TTYSM1
+ select MN10300_PROC_HAS_TTYSM2
+
+endchoice
+
+choice
+ prompt "Processor core support"
+ default MN10300_CPU_AM33V2
+ help
+ This option specifies the processor core for which the kernel will be
+ compiled. It affects the instruction set used.
+
+config MN10300_CPU_AM33V2
+ bool "AM33v2"
+
+endchoice
+
+config FPU
+ bool "FPU present"
+ default y
+ depends on MN10300_PROC_MN103E010
+
+choice
+ prompt "CPU Caching mode"
+ default MN10300_CACHE_WBACK
+ help
+ This option determines the caching mode for the kernel.
+
+ Write-Back caching mode involves the all reads and writes causing
+ the affected cacheline to be read into the cache first before being
+ operated upon. Memory is not then updated by a write until the cache
+ is filled and a cacheline needs to be displaced from the cache to
+ make room. Only at that point is it written back.
+
+ Write-Through caching only fetches cachelines from memory on a
+ read. Writes always get written directly to memory. If the affected
+ cacheline is also in cache, it will be updated too.
+
+ The final option is to turn of caching entirely.
+
+config MN10300_CACHE_WBACK
+ bool "Write-Back"
+
+config MN10300_CACHE_WTHRU
+ bool "Write-Through"
+
+config MN10300_CACHE_DISABLED
+ bool "Disabled"
+
+endchoice
+
+menu "Memory layout options"
+
+config KERNEL_RAM_BASE_ADDRESS
+ hex "Base address of kernel RAM"
+ default "0x90000000"
+
+config INTERRUPT_VECTOR_BASE
+ hex "Base address of vector table"
+ default "0x90000000"
+ help
+ The base address of the vector table will be programmed into
+ the TBR register. It must be on 16MiB address boundary.
+
+config KERNEL_TEXT_ADDRESS
+ hex "Base address of kernel"
+ default "0x90001000"
+
+config KERNEL_ZIMAGE_BASE_ADDRESS
+ hex "Base address of compressed vmlinux image"
+ default "0x90700000"
+
+endmenu
+
+config PREEMPT
+ bool "Preemptible Kernel"
+ help
+ This option reduces the latency of the kernel when reacting to
+ real-time or interactive events by allowing a low priority process to
+ be preempted even if it is in kernel mode executing a system call.
+ This allows applications to run more reliably even when the system is
+ under load.
+
+ Say Y here if you are building a kernel for a desktop, embedded
+ or real-time system. Say N if you are unsure.
+
+config PREEMPT_BKL
+ bool "Preempt The Big Kernel Lock"
+ depends on PREEMPT
+ default y
+ help
+ This option reduces the latency of the kernel by making the
+ big kernel lock preemptible.
+
+ Say Y here if you are building a kernel for a desktop system.
+ Say N if you are unsure.
+
+config MN10300_CURRENT_IN_E2
+ bool "Hold current task address in E2 register"
+ default y
+ help
+ This option removes the E2/R2 register from the set available to gcc
+ for normal use and instead uses it to store the address of the
+ current process's task_struct whilst in the kernel.
+
+ This means the kernel doesn't need to calculate the address each time
+ "current" is used (take SP, AND with mask and dereference pointer
+ just to get the address), and instead can just use E2+offset
+ addressing each time.
+
+ This has no effect on userspace.
+
+config MN10300_USING_JTAG
+ bool "Using JTAG to debug kernel"
+ default y
+ help
+ This options indicates that JTAG will be used to debug the kernel. It
+ suppresses the use of certain hardware debugging features, such as
+ single-stepping, which are taken over completely by the JTAG unit.
+
+config MN10300_RTC
+ bool "Using MN10300 RTC"
+ depends on MN10300_PROC_MN103E010
+ default n
+ help
+
+ This option enables support for the RTC, thus enabling time to be
+ tracked, even when system is powered down. This is available on-chip
+ on the MN103E010.
+
+config MN10300_WD_TIMER
+ bool "Using MN10300 watchdog timer"
+ default y
+ help
+ This options indicates that the watchdog timer will be used.
+
+config PCI
+ bool "Use PCI"
+ depends on MN10300_UNIT_ASB2305
+ default y
+ help
+ Some systems (such as the ASB2305) have PCI onboard. If you have one
+ of these boards and you wish to use the PCI facilities, say Y here.
+
+ The PCI-HOWTO, available from
+ <http://www.tldp.org/docs.html#howto>, contains valuable
+ information about which PCI hardware does work under Linux and which
+ doesn't.
+
+source "drivers/pci/Kconfig"
+
+source "drivers/pcmcia/Kconfig"
+
+menu "MN10300 internal serial options"
+
+config MN10300_PROC_HAS_TTYSM0
+ bool
+ default n
+
+config MN10300_PROC_HAS_TTYSM1
+ bool
+ default n
+
+config MN10300_PROC_HAS_TTYSM2
+ bool
+ default n
+
+config MN10300_TTYSM
+ bool "Support for ttySM serial ports"
+ depends on MN10300
+ default y
+ select SERIAL_CORE
+ help
+ This option enables support for the on-chip serial ports that the
+ MN10300 has available.
+
+config MN10300_TTYSM_CONSOLE
+ bool "Support for console on ttySM serial ports"
+ depends on MN10300_TTYSM
+ select SERIAL_CORE_CONSOLE
+ help
+ This option enables support for a console on the on-chip serial ports
+ that the MN10300 has available.
+
+#
+# /dev/ttySM0
+#
+config MN10300_TTYSM0
+ bool "Enable SIF0 (/dev/ttySM0)"
+ depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM0
+ help
+ Enable access to SIF0 through /dev/ttySM0 or gdb-stub
+
+choice
+ prompt "Select the timer to supply the clock for SIF0"
+ default MN10300_TTYSM0_TIMER8
+ depends on MN10300_TTYSM0
+
+config MN10300_TTYSM0_TIMER8
+ bool "Use timer 8 (16-bit)"
+
+config MN10300_TTYSM0_TIMER2
+ bool "Use timer 2 (8-bit)"
+
+endchoice
+
+#
+# /dev/ttySM1
+#
+config MN10300_TTYSM1
+ bool "Enable SIF1 (/dev/ttySM1)"
+ depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM1
+ help
+ Enable access to SIF1 through /dev/ttySM1 or gdb-stub
+
+choice
+ prompt "Select the timer to supply the clock for SIF1"
+ default MN10300_TTYSM0_TIMER9
+ depends on MN10300_TTYSM1
+
+config MN10300_TTYSM1_TIMER9
+ bool "Use timer 9 (16-bit)"
+
+config MN10300_TTYSM1_TIMER3
+ bool "Use timer 3 (8-bit)"
+
+endchoice
+
+#
+# /dev/ttySM2
+#
+config MN10300_TTYSM2
+ bool "Enable SIF2 (/dev/ttySM2)"
+ depends on MN10300_TTYSM && MN10300_PROC_HAS_TTYSM2
+ help
+ Enable access to SIF2 through /dev/ttySM2 or gdb-stub
+
+choice
+ prompt "Select the timer to supply the clock for SIF2"
+ default MN10300_TTYSM0_TIMER10
+ depends on MN10300_TTYSM2
+
+config MN10300_TTYSM2_TIMER10
+ bool "Use timer 10 (16-bit)"
+
+endchoice
+
+config MN10300_TTYSM2_CTS
+ bool "Enable the use of the CTS line /dev/ttySM2"
+ depends on MN10300_TTYSM2
+
+endmenu
+
+source "mm/Kconfig"
+
+menu "Power management options"
+source kernel/power/Kconfig
+endmenu
+
+endmenu
+
+
+menu "Executable formats"
+
+source "fs/Kconfig.binfmt"
+
+endmenu
+
+source "net/Kconfig"
+
+source "drivers/Kconfig"
+
+source "fs/Kconfig"
+
+source "arch/mn10300/Kconfig.debug"
+
+source "security/Kconfig"
+
+source "crypto/Kconfig"
+
+source "lib/Kconfig"
+
+source "arch/mn10300/oprofile/Kconfig"
--- /dev/null
+menu "Kernel hacking"
+
+source "lib/Kconfig.debug"
+
+config DEBUG_STACKOVERFLOW
+ bool "Check for stack overflows"
+ depends on DEBUG_KERNEL
+
+config DEBUG_DECOMPRESS_KERNEL
+ bool "Using serial port during decompressing kernel"
+ depends on DEBUG_KERNEL
+ default n
+ help
+ If you say Y here you will confirm the start and the end of
+ decompressing Linux seeing "Uncompressing Linux... " and
+ "Ok, booting the kernel.\n" on console.
+
+config KPROBES
+ bool "Kprobes"
+ depends on DEBUG_KERNEL
+ help
+ Kprobes allows you to trap at almost any kernel address and
+ execute a callback function. register_kprobe() establishes
+ a probepoint and specifies the callback. Kprobes is useful
+ for kernel debugging, non-intrusive instrumentation and testing.
+ If in doubt, say "N".
+
+config GDBSTUB
+ bool "Remote GDB kernel debugging"
+ depends on DEBUG_KERNEL
+ select DEBUG_INFO
+ select FRAME_POINTER
+ help
+ If you say Y here, it will be possible to remotely debug the kernel
+ using gdb. This enlarges your kernel ELF image disk size by several
+ megabytes and requires a machine with more than 16 MB, better 32 MB
+ RAM to avoid excessive linking time. This is only useful for kernel
+ hackers. If unsure, say N.
+
+config GDBSTUB_IMMEDIATE
+ bool "Break into GDB stub immediately"
+ depends on GDBSTUB
+ help
+ If you say Y here, GDB stub will break into the program as soon as
+ possible, leaving the program counter at the beginning of
+ start_kernel() in init/main.c.
+
+config GDB_CONSOLE
+ bool "Console output to GDB"
+ depends on GDBSTUB
+ help
+ If you are using GDB for remote debugging over a serial port and
+ would like kernel messages to be formatted into GDB $O packets so
+ that GDB prints them as program output, say 'Y'.
+
+config GDBSTUB_DEBUGGING
+ bool "Debug GDB stub by messages to serial port"
+ depends on GDBSTUB
+ help
+ This causes debugging messages to be displayed at various points
+ during execution of the GDB stub routines. Such messages will be
+ displayed on ttyS0 if that isn't the GDB stub's port, or ttySM0
+ otherwise.
+
+config GDBSTUB_DEBUG_ENTRY
+ bool "Debug GDB stub entry"
+ depends on GDBSTUB_DEBUGGING
+ help
+ This option causes information to be displayed about entry to or exit
+ from the main GDB stub routine.
+
+config GDBSTUB_DEBUG_PROTOCOL
+ bool "Debug GDB stub protocol"
+ depends on GDBSTUB_DEBUGGING
+ help
+ This option causes information to be displayed about the GDB remote
+ protocol messages generated exchanged with GDB.
+
+config GDBSTUB_DEBUG_IO
+ bool "Debug GDB stub I/O"
+ depends on GDBSTUB_DEBUGGING
+ help
+ This option causes information to be displayed about GDB stub's
+ low-level I/O.
+
+config GDBSTUB_DEBUG_BREAKPOINT
+ bool "Debug GDB stub breakpoint management"
+ depends on GDBSTUB_DEBUGGING
+ help
+ This option causes information to be displayed about GDB stub's
+ breakpoint management.
+
+choice
+ prompt "GDB stub port"
+ default GDBSTUB_TTYSM0
+ depends on GDBSTUB
+ help
+ Select the serial port used for GDB-stub.
+
+config GDBSTUB_ON_TTYSM0
+ bool "/dev/ttySM0 [SIF0]"
+ depends on MN10300_TTYSM0
+ select GDBSTUB_ON_TTYSMx
+
+config GDBSTUB_ON_TTYSM1
+ bool "/dev/ttySM1 [SIF1]"
+ depends on MN10300_TTYSM1
+ select GDBSTUB_ON_TTYSMx
+
+config GDBSTUB_ON_TTYSM2
+ bool "/dev/ttySM2 [SIF2]"
+ depends on MN10300_TTYSM2
+ select GDBSTUB_ON_TTYSMx
+
+config GDBSTUB_ON_TTYS0
+ bool "/dev/ttyS0"
+ select GDBSTUB_ON_TTYSx
+
+config GDBSTUB_ON_TTYS1
+ bool "/dev/ttyS1"
+ select GDBSTUB_ON_TTYSx
+
+endchoice
+
+config GDBSTUB_ON_TTYSMx
+ bool
+ depends on GDBSTUB_ON_TTYSM0 || GDBSTUB_ON_TTYSM1 || GDBSTUB_ON_TTYSM2
+ default y
+
+config GDBSTUB_ON_TTYSx
+ bool
+ depends on GDBSTUB_ON_TTYS0 || GDBSTUB_ON_TTYS1
+ default y
+
+endmenu
--- /dev/null
+###############################################################################
+#
+# MN10300 Kernel makefile system specifications
+#
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Modified by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+###############################################################################
+
+KBUILD_DEFCONFIG := asb2303_defconfig
+
+CCSPECS := $(shell $(CC) -v 2>&1 | grep "^Reading specs from " | head -1 | cut -c20-)
+CCDIR := $(strip $(patsubst %/specs,%,$(CCSPECS)))
+KBUILD_CPPFLAGS += -nostdinc -I$(CCDIR)/include
+
+LDFLAGS :=
+OBJCOPYFLAGS := -O binary -R .note -R .comment -S
+#LDFLAGS_vmlinux := -Map linkmap.txt
+CHECKFLAGS +=
+
+PROCESSOR := unset
+UNIT := unset
+
+KBUILD_CFLAGS += -mam33 -mmem-funcs -DCPU=AM33
+KBUILD_AFLAGS += -mam33 -DCPU=AM33
+
+ifeq ($(CONFIG_MN10300_CURRENT_IN_E2),y)
+KBUILD_CFLAGS += -ffixed-e2 -fcall-saved-e5
+endif
+
+ifeq ($(CONFIG_MN10300_PROC_MN103E010),y)
+PROCESSOR := mn103e010
+endif
+
+ifeq ($(CONFIG_MN10300_UNIT_ASB2303),y)
+UNIT := asb2303
+endif
+ifeq ($(CONFIG_MN10300_UNIT_ASB2305),y)
+UNIT := asb2305
+endif
+
+
+head-y := arch/mn10300/kernel/head.o arch/mn10300/kernel/init_task.o
+
+core-y += arch/mn10300/kernel/ arch/mn10300/mm/
+
+ifneq ($(PROCESSOR),unset)
+core-y += arch/mn10300/proc-$(PROCESSOR)/
+endif
+ifneq ($(UNIT),unset)
+core-y += arch/mn10300/unit-$(UNIT)/
+endif
+libs-y += arch/mn10300/lib/
+
+drivers-$(CONFIG_OPROFILE) += arch/mn10300/oprofile/
+
+boot := arch/mn10300/boot
+
+.PHONY: zImage
+
+KBUILD_IMAGE := $(boot)/zImage
+CLEAN_FILES += $(boot)/zImage
+CLEAN_FILES += $(boot)/compressed/vmlinux
+CLEAN_FILES += $(boot)/compressed/vmlinux.bin
+CLEAN_FILES += $(boot)/compressed/vmlinux.bin.gz
+
+zImage: vmlinux
+ $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
+
+all: zImage
+
+bootstrap:
+ $(Q)$(MAKEBOOT) bootstrap
+
+archclean:
+ $(Q)$(MAKE) $(clean)=arch/mn10300/proc-mn103e010
+ $(Q)$(MAKE) $(clean)=arch/mn10300/unit-asb2303
+ $(Q)$(MAKE) $(clean)=arch/mn10300/unit-asb2305
+
+define archhelp
+ echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)'
+endef
+
+# If you make sure the .S files get compiled with debug info,
+# uncomment the following to disable optimisations
+# that are unhelpful whilst debugging.
+ifdef CONFIG_DEBUG_INFO
+#KBUILD_CFLAGS += -O1
+KBUILD_AFLAGS += -Wa,--gdwarf2
+endif
+
+###################################################################################################
+#
+# juggle some symlinks in the MN10300 asm include dir
+#
+# Update machine proc and unit symlinks if something which affects
+# them changed. We use .proc / .unit to indicate when they were
+# updated last, otherwise make uses the target directory mtime.
+#
+###################################################################################################
+
+# processor specific definitions
+include/asm-mn10300/.proc: $(wildcard include/config/proc/*.h) include/config/auto.conf
+ @echo ' SYMLINK include/asm-mn10300/proc -> include/asm-mn10300/proc-$(PROCESSOR)'
+ifneq ($(KBUILD_SRC),)
+ $(Q)mkdir -p include/asm-mn10300
+ $(Q)ln -fsn $(srctree)/include/asm-mn10300/proc-$(PROCESSOR) include/asm-mn10300/proc
+else
+ $(Q)ln -fsn proc-$(PROCESSOR) include/asm-mn10300/proc
+endif
+ @touch $@
+
+CLEAN_FILES += include/asm-mn10300/proc include/asm-mn10300/.proc
+
+prepare: include/asm-mn10300/.proc
+
+# unit specific definitions
+include/asm-mn10300/.unit: $(wildcard include/config/unit/*.h) include/config/auto.conf
+ @echo ' SYMLINK include/asm-mn10300/unit -> include/asm-mn10300/unit-$(UNIT)'
+ifneq ($(KBUILD_SRC),)
+ $(Q)mkdir -p include/asm-mn10300
+ $(Q)ln -fsn $(srctree)/include/asm-mn10300/unit-$(UNIT) include/asm-mn10300/unit
+else
+ $(Q)ln -fsn unit-$(UNIT) include/asm-mn10300/unit
+endif
+ @touch $@
+
+CLEAN_FILES += include/asm-mn10300/unit include/asm-mn10300/.unit
+
+prepare: include/asm-mn10300/.unit
--- /dev/null
+# MN10300 kernel compressor and wrapper
+#
+# Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Written by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+
+targets := vmlinux.bin zImage
+
+subdir- := compressed
+
+# ---------------------------------------------------------------------------
+
+
+$(obj)/zImage: $(obj)/compressed/vmlinux FORCE
+ $(call if_changed,objcopy)
+ @echo 'Kernel: $@ is ready'
+
+$(obj)/vmlinux.bin: $(obj)/compressed/vmlinux FORCE
+ $(call if_changed,objcopy)
+
+$(obj)/compressed/vmlinux: FORCE
+ $(Q)$(MAKE) $(build)=$(obj)/compressed IMAGE_OFFSET=$(IMAGE_OFFSET) $@
--- /dev/null
+#
+# Create a compressed vmlinux image from the original vmlinux
+#
+
+targets := vmlinux vmlinux.bin vmlinux.bin.gz head.o misc.o piggy.o
+
+LDFLAGS_vmlinux := -Ttext $(CONFIG_KERNEL_ZIMAGE_BASE_ADDRESS) -e startup_32
+
+$(obj)/vmlinux: $(obj)/head.o $(obj)/misc.o $(obj)/piggy.o FORCE
+ $(call if_changed,ld)
+ @:
+
+$(obj)/vmlinux.bin: vmlinux FORCE
+ $(call if_changed,objcopy)
+
+$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
+ $(call if_changed,gzip)
+
+LDFLAGS_piggy.o := -r --format binary --oformat elf32-am33lin -T
+
+$(obj)/piggy.o: $(obj)/vmlinux.lds $(obj)/vmlinux.bin.gz FORCE
+ $(call if_changed,ld)
--- /dev/null
+/* Boot entry point for a compressed MN10300 kernel
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+ .section .text
+
+#define DEBUG
+
+#include <linux/linkage.h>
+#include <asm/cpu-regs.h>
+
+ .globl startup_32
+startup_32:
+ # first save off parameters from bootloader
+ mov param_save_area,a0
+ mov d0,(a0)
+ mov d1,(4,a0)
+ mov d2,(8,a0)
+
+ mov sp,a3
+ mov decomp_stack+0x2000-4,a0
+ mov a0,sp
+
+ # invalidate and enable both of the caches
+ mov CHCTR,a0
+ clr d0
+ movhu d0,(a0) # turn off first
+ mov CHCTR_ICINV|CHCTR_DCINV,d0
+ movhu d0,(a0)
+ setlb
+ mov (a0),d0
+ btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
+ lne
+ mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD,d0 # writethru dcache
+ movhu d0,(a0) # enable
+
+ # clear the BSS area
+ mov __bss_start,a0
+ mov _end,a1
+ clr d0
+bssclear:
+ cmp a1,a0
+ bge bssclear_end
+ movbu d0,(a0)
+ inc a0
+ bra bssclear
+bssclear_end:
+
+ # decompress the kernel
+ call decompress_kernel[],0
+
+ # disable caches again
+ mov CHCTR,a0
+ clr d0
+ movhu d0,(a0)
+ setlb
+ mov (a0),d0
+ btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
+ lne
+
+ mov param_save_area,a0
+ mov (a0),d0
+ mov (4,a0),d1
+ mov (8,a0),d2
+
+ mov a3,sp
+ mov CONFIG_KERNEL_TEXT_ADDRESS,a0
+ jmp (a0)
+
+ .data
+ .align 4
+param_save_area:
+ .rept 3
+ .word 0
+ .endr
+
+ .section .bss
+ .align 4
+decomp_stack:
+ .space 0x2000
--- /dev/null
+/* MN10300 Miscellaneous helper routines for kernel decompressor
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Modified by David Howells (dhowells@redhat.com)
+ * - Derived from arch/x86/boot/compressed/misc_32.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/compiler.h>
+#include <asm/serial-regs.h>
+#include "misc.h"
+
+#ifndef CONFIG_GDBSTUB_ON_TTYSx
+/* display 'Uncompressing Linux... ' messages on ttyS0 or ttyS1 */
+#if 1 /* ttyS0 */
+#define CYG_DEV_BASE 0xA6FB0000
+#else /* ttyS1 */
+#define CYG_DEV_BASE 0xA6FC0000
+#endif
+
+#define CYG_DEV_THR (*((volatile __u8*)(CYG_DEV_BASE + 0x00)))
+#define CYG_DEV_MCR (*((volatile __u8*)(CYG_DEV_BASE + 0x10)))
+#define SIO_MCR_DTR 0x01
+#define SIO_MCR_RTS 0x02
+#define CYG_DEV_LSR (*((volatile __u8*)(CYG_DEV_BASE + 0x14)))
+#define SIO_LSR_THRE 0x20 /* transmitter holding register empty */
+#define SIO_LSR_TEMT 0x40 /* transmitter register empty */
+#define CYG_DEV_MSR (*((volatile __u8*)(CYG_DEV_BASE + 0x18)))
+#define SIO_MSR_CTS 0x10 /* clear to send */
+#define SIO_MSR_DSR 0x20 /* data set ready */
+
+#define LSR_WAIT_FOR(STATE) \
+ do { while (!(CYG_DEV_LSR & SIO_LSR_##STATE)) {} } while (0)
+#define FLOWCTL_QUERY(LINE) \
+ ({ CYG_DEV_MSR & SIO_MSR_##LINE; })
+#define FLOWCTL_WAIT_FOR(LINE) \
+ do { while (!(CYG_DEV_MSR & SIO_MSR_##LINE)) {} } while (0)
+#define FLOWCTL_CLEAR(LINE) \
+ do { CYG_DEV_MCR &= ~SIO_MCR_##LINE; } while (0)
+#define FLOWCTL_SET(LINE) \
+ do { CYG_DEV_MCR |= SIO_MCR_##LINE; } while (0)
+#endif
+
+/*
+ * gzip declarations
+ */
+
+#define OF(args) args
+#define STATIC static
+
+#undef memset
+#undef memcpy
+
+static inline void *memset(const void *s, int c, size_t n)
+{
+ int i;
+ char *ss = (char *) s;
+
+ for (i = 0; i < n; i++)
+ ss[i] = c;
+ return (void *)s;
+}
+
+#define memzero(s, n) memset((s), 0, (n))
+
+static inline void *memcpy(void *__dest, const void *__src, size_t __n)
+{
+ int i;
+ const char *s = __src;
+ char *d = __dest;
+
+ for (i = 0; i < __n; i++)
+ d[i] = s[i];
+ return __dest;
+}
+
+typedef unsigned char uch;
+typedef unsigned short ush;
+typedef unsigned long ulg;
+
+#define WSIZE 0x8000 /* Window size must be at least 32k, and a power of
+ * two */
+
+static uch *inbuf; /* input buffer */
+static uch window[WSIZE]; /* sliding window buffer */
+
+static unsigned insize; /* valid bytes in inbuf */
+static unsigned inptr; /* index of next byte to be processed in inbuf */
+static unsigned outcnt; /* bytes in output buffer */
+
+/* gzip flag byte */
+#define ASCII_FLAG 0x01 /* bit 0 set: file probably ASCII text */
+#define CONTINUATION 0x02 /* bit 1 set: continuation of multi-part gzip file */
+#define EXTRA_FIELD 0x04 /* bit 2 set: extra field present */
+#define ORIG_NAME 0x08 /* bit 3 set: original file name present */
+#define COMMENT 0x10 /* bit 4 set: file comment present */
+#define ENCRYPTED 0x20 /* bit 5 set: file is encrypted */
+#define RESERVED 0xC0 /* bit 6,7: reserved */
+
+/* Diagnostic functions */
+#ifdef DEBUG
+# define Assert(cond, msg) { if (!(cond)) error(msg); }
+# define Trace(x) fprintf x
+# define Tracev(x) { if (verbose) fprintf x ; }
+# define Tracevv(x) { if (verbose > 1) fprintf x ; }
+# define Tracec(c, x) { if (verbose && (c)) fprintf x ; }
+# define Tracecv(c, x) { if (verbose > 1 && (c)) fprintf x ; }
+#else
+# define Assert(cond, msg)
+# define Trace(x)
+# define Tracev(x)
+# define Tracevv(x)
+# define Tracec(c, x)
+# define Tracecv(c, x)
+#endif
+
+static int fill_inbuf(void);
+static void flush_window(void);
+static void error(const char *) __attribute__((noreturn));
+static void kputs(const char *);
+
+static inline unsigned char get_byte(void)
+{
+ unsigned char ch = inptr < insize ? inbuf[inptr++] : fill_inbuf();
+
+#if 0
+ char hex[3];
+ hex[0] = ((ch & 0x0f) > 9) ?
+ ((ch & 0x0f) + 'A' - 0xa) : ((ch & 0x0f) + '0');
+ hex[1] = ((ch >> 4) > 9) ?
+ ((ch >> 4) + 'A' - 0xa) : ((ch >> 4) + '0');
+ hex[2] = 0;
+ kputs(hex);
+#endif
+ return ch;
+}
+
+/*
+ * This is set up by the setup-routine at boot-time
+ */
+#define EXT_MEM_K (*(unsigned short *)0x90002)
+#ifndef STANDARD_MEMORY_BIOS_CALL
+#define ALT_MEM_K (*(unsigned long *) 0x901e0)
+#endif
+#define SCREEN_INFO (*(struct screen_info *)0x90000)
+
+static long bytes_out;
+static uch *output_data;
+static unsigned long output_ptr;
+
+
+static void *malloc(int size);
+
+static inline void free(void *where)
+{ /* Don't care */
+}
+
+static unsigned long free_mem_ptr = (unsigned long) &end;
+static unsigned long free_mem_end_ptr = (unsigned long) &end + 0x90000;
+
+static inline void gzip_mark(void **ptr)
+{
+ kputs(".");
+ *ptr = (void *) free_mem_ptr;
+}
+
+static inline void gzip_release(void **ptr)
+{
+ free_mem_ptr = (unsigned long) *ptr;
+}
+
+#define INPLACE_MOVE_ROUTINE 0x1000
+#define LOW_BUFFER_START 0x2000
+#define LOW_BUFFER_END 0x90000
+#define LOW_BUFFER_SIZE (LOW_BUFFER_END - LOW_BUFFER_START)
+#define HEAP_SIZE 0x3000
+static int high_loaded;
+static uch *high_buffer_start /* = (uch *)(((ulg)&end) + HEAP_SIZE)*/;
+
+static char *vidmem = (char *)0xb8000;
+static int lines, cols;
+
+#include "../../../../lib/inflate.c"
+
+static void *malloc(int size)
+{
+ void *p;
+
+ if (size < 0)
+ error("Malloc error\n");
+ if (!free_mem_ptr)
+ error("Memory error\n");
+
+ free_mem_ptr = (free_mem_ptr + 3) & ~3; /* Align */
+
+ p = (void *) free_mem_ptr;
+ free_mem_ptr += size;
+
+ if (free_mem_ptr >= free_mem_end_ptr)
+ error("\nOut of memory\n");
+
+ return p;
+}
+
+static inline void scroll(void)
+{
+ int i;
+
+ memcpy(vidmem, vidmem + cols * 2, (lines - 1) * cols * 2);
+ for (i = (lines - 1) * cols * 2; i < lines * cols * 2; i += 2)
+ vidmem[i] = ' ';
+}
+
+static inline void kputchar(unsigned char ch)
+{
+#ifdef CONFIG_MN10300_UNIT_ASB2305
+ while (SC0STR & SC01STR_TBF)
+ continue;
+
+ if (ch == 0x0a) {
+ SC0TXB = 0x0d;
+ while (SC0STR & SC01STR_TBF)
+ continue;
+ }
+
+ SC0TXB = ch;
+
+#else
+ while (SC1STR & SC01STR_TBF)
+ continue;
+
+ if (ch == 0x0a) {
+ SC1TXB = 0x0d;
+ while (SC1STR & SC01STR_TBF)
+ continue;
+ }
+
+ SC1TXB = ch;
+
+#endif
+}
+
+static void kputs(const char *s)
+{
+#ifdef CONFIG_DEBUG_DECOMPRESS_KERNEL
+#ifndef CONFIG_GDBSTUB_ON_TTYSx
+ char ch;
+
+ FLOWCTL_SET(DTR);
+
+ while (*s) {
+ LSR_WAIT_FOR(THRE);
+
+ ch = *s++;
+ if (ch == 0x0a) {
+ CYG_DEV_THR = 0x0d;
+ LSR_WAIT_FOR(THRE);
+ }
+ CYG_DEV_THR = ch;
+ }
+
+ FLOWCTL_CLEAR(DTR);
+#else
+
+ for (; *s; s++)
+ kputchar(*s);
+
+#endif
+#endif /* CONFIG_DEBUG_DECOMPRESS_KERNEL */
+}
+
+/* ===========================================================================
+ * Fill the input buffer. This is called only when the buffer is empty
+ * and at least one byte is really needed.
+ */
+static int fill_inbuf()
+{
+ if (insize != 0)
+ error("ran out of input data\n");
+
+ inbuf = input_data;
+ insize = input_len;
+ inptr = 1;
+ return inbuf[0];
+}
+
+/* ===========================================================================
+ * Write the output window window[0..outcnt-1] and update crc and bytes_out.
+ * (Used for the decompressed data only.)
+ */
+static void flush_window_low(void)
+{
+ ulg c = crc; /* temporary variable */
+ unsigned n;
+ uch *in, *out, ch;
+
+ in = window;
+ out = &output_data[output_ptr];
+ for (n = 0; n < outcnt; n++) {
+ ch = *out++ = *in++;
+ c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
+ }
+ crc = c;
+ bytes_out += (ulg)outcnt;
+ output_ptr += (ulg)outcnt;
+ outcnt = 0;
+}
+
+static void flush_window_high(void)
+{
+ ulg c = crc; /* temporary variable */
+ unsigned n;
+ uch *in, ch;
+ in = window;
+ for (n = 0; n < outcnt; n++) {
+ ch = *output_data++ = *in++;
+ if ((ulg) output_data == LOW_BUFFER_END)
+ output_data = high_buffer_start;
+ c = crc_32_tab[((int)c ^ ch) & 0xff] ^ (c >> 8);
+ }
+ crc = c;
+ bytes_out += (ulg)outcnt;
+ outcnt = 0;
+}
+
+static void flush_window(void)
+{
+ if (high_loaded)
+ flush_window_high();
+ else
+ flush_window_low();
+}
+
+static void error(const char *x)
+{
+ kputs("\n\n");
+ kputs(x);
+ kputs("\n\n -- System halted");
+
+ while (1)
+ /* Halt */;
+}
+
+#define STACK_SIZE (4096)
+
+long user_stack[STACK_SIZE];
+
+struct {
+ long *a;
+ short b;
+} stack_start = { &user_stack[STACK_SIZE], 0 };
+
+void setup_normal_output_buffer(void)
+{
+#ifdef STANDARD_MEMORY_BIOS_CALL
+ if (EXT_MEM_K < 1024)
+ error("Less than 2MB of memory.\n");
+#else
+ if ((ALT_MEM_K > EXT_MEM_K ? ALT_MEM_K : EXT_MEM_K) < 1024)
+ error("Less than 2MB of memory.\n");
+#endif
+ output_data = (char *) 0x100000; /* Points to 1M */
+}
+
+struct moveparams {
+ uch *low_buffer_start;
+ int lcount;
+ uch *high_buffer_start;
+ int hcount;
+};
+
+void setup_output_buffer_if_we_run_high(struct moveparams *mv)
+{
+ high_buffer_start = (uch *)(((ulg) &end) + HEAP_SIZE);
+#ifdef STANDARD_MEMORY_BIOS_CALL
+ if (EXT_MEM_K < (3 * 1024))
+ error("Less than 4MB of memory.\n");
+#else
+ if ((ALT_MEM_K > EXT_MEM_K ? ALT_MEM_K : EXT_MEM_K) < (3 * 1024))
+ error("Less than 4MB of memory.\n");
+#endif
+ mv->low_buffer_start = output_data = (char *) LOW_BUFFER_START;
+ high_loaded = 1;
+ free_mem_end_ptr = (long) high_buffer_start;
+ if (0x100000 + LOW_BUFFER_SIZE > (ulg) high_buffer_start) {
+ high_buffer_start = (uch *)(0x100000 + LOW_BUFFER_SIZE);
+ mv->hcount = 0; /* say: we need not to move high_buffer */
+ } else {
+ mv->hcount = -1;
+ }
+ mv->high_buffer_start = high_buffer_start;
+}
+
+void close_output_buffer_if_we_run_high(struct moveparams *mv)
+{
+ mv->lcount = bytes_out;
+ if (bytes_out > LOW_BUFFER_SIZE) {
+ mv->lcount = LOW_BUFFER_SIZE;
+ if (mv->hcount)
+ mv->hcount = bytes_out - LOW_BUFFER_SIZE;
+ } else {
+ mv->hcount = 0;
+ }
+}
+
+#undef DEBUGFLAG
+#ifdef DEBUGFLAG
+int debugflag;
+#endif
+
+int decompress_kernel(struct moveparams *mv)
+{
+#ifdef DEBUGFLAG
+ while (!debugflag)
+ barrier();
+#endif
+
+ output_data = (char *) CONFIG_KERNEL_TEXT_ADDRESS;
+
+ makecrc();
+ kputs("Uncompressing Linux... ");
+ gunzip();
+ kputs("Ok, booting the kernel.\n");
+ return 0;
+}
--- /dev/null
+/* Internal definitions for the MN10300 kernel decompressor
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+extern int end;
+
+/*
+ * vmlinux.lds
+ */
+extern char input_data[];
+extern int input_len;
--- /dev/null
+SECTIONS
+{
+ .data : {
+ input_len = .;
+ LONG(input_data_end - input_data) input_data = .;
+ *(.data)
+ input_data_end = .;
+ }
+}
--- /dev/null
+#!/bin/sh
+#
+# arch/mn10300/boot/install -c.sh
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# Licence. See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (C) 1995 by Linus Torvalds
+#
+# Adapted from code in arch/i386/boot/Makefile by H. Peter Anvin
+#
+# "make install -c" script for i386 architecture
+#
+# Arguments:
+# $1 - kernel version
+# $2 - kernel image file
+# $3 - kernel map file
+# $4 - default install -c path (blank if root directory)
+# $5 - boot rom file
+#
+
+# User may have a custom install -c script
+
+rm -fr $4/../usr/include/linux $4/../usr/include/asm
+install -c -m 0755 $2 $4/vmlinuz
+install -c -m 0755 $5 $4/boot.rom
+install -c -m 0755 -d $4/../usr/include/linux
+cd $TOPDIR/include/linux
+for i in `find . -maxdepth 1 -name '*.h' -print`; do
+ install -c -m 0644 $i $4/../usr/include/linux
+done
+install -c -m 0755 -d $4/../usr/include/linux/byteorder
+cd $TOPDIR/include/linux/byteorder
+for i in `find . -name '*.h' -print`; do
+ install -c -m 0644 $i $4/../usr/include/linux/byteorder
+done
+install -c -m 0755 -d $4/../usr/include/linux/lockd
+cd $TOPDIR/include/linux/lockd
+for i in `find . -name '*.h' -print`; do
+ install -c -m 0644 $i $4/../usr/include/linux/lockd
+done
+install -c -m 0755 -d $4/../usr/include/linux/netfilter_ipv4
+cd $TOPDIR/include/linux/netfilter_ipv4
+for i in `find . -name '*.h' -print`; do
+ install -c -m 0644 $i $4/../usr/include/linux/netfilter_ipv4
+done
+install -c -m 0755 -d $4/../usr/include/linux/nfsd
+cd $TOPDIR/include/linux/nfsd
+for i in `find . -name '*.h' -print`; do
+ install -c -m 0644 $i $4/../usr/include/linux/nfsd/$i
+done
+install -c -m 0755 -d $4/../usr/include/linux/raid
+cd $TOPDIR/include/linux/raid
+for i in `find . -name '*.h' -print`; do
+ install -c -m 0644 $i $4/../usr/include/linux/raid
+done
+install -c -m 0755 -d $4/../usr/include/linux/sunrpc
+cd $TOPDIR/include/linux/sunrpc
+for i in `find . -name '*.h' -print`; do
+ install -c -m 0644 $i $4/../usr/include/linux/sunrpc
+done
+install -c -m 0755 -d $4/../usr/include/asm
+cd $TOPDIR/include/asm
+for i in `find . -name '*.h' -print`; do
+ install -c -m 0644 $i $4/../usr/include/asm
+done
--- /dev/null
+/*
+ * Copyright (C) 1991, 1992 Linus Torvalds
+ * Copyright (C) 1997 Martin Mares
+ */
+
+/*
+ * This file builds a disk-image from three different files:
+ *
+ * - bootsect: exactly 512 bytes of 8086 machine code, loads the rest
+ * - setup: 8086 machine code, sets up system parm
+ * - system: 80386 code for actual system
+ *
+ * It does some checking that all files are of the correct type, and
+ * just writes the result to stdout, removing headers and padding to
+ * the right amount. It also writes some system data to stderr.
+ */
+
+/*
+ * Changes by tytso to allow root device specification
+ * High loaded stuff by Hans Lermen & Werner Almesberger, Feb. 1996
+ * Cross compiling fixes by Gertjan van Wingerde, July 1996
+ * Rewritten by Martin Mares, April 1997
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <sys/sysmacros.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <asm/boot.h>
+
+#define DEFAULT_MAJOR_ROOT 0
+#define DEFAULT_MINOR_ROOT 0
+
+/* Minimal number of setup sectors (see also bootsect.S) */
+#define SETUP_SECTS 4
+
+uint8_t buf[1024];
+int fd;
+int is_big_kernel;
+
+__attribute__((noreturn))
+void die(const char *str, ...)
+{
+ va_list args;
+ va_start(args, str);
+ vfprintf(stderr, str, args);
+ fputc('\n', stderr);
+ exit(1);
+}
+
+void file_open(const char *name)
+{
+ fd = open(name, O_RDONLY, 0);
+ if (fd < 0)
+ die("Unable to open `%s': %m", name);
+}
+
+__attribute__((noreturn))
+void usage(void)
+{
+ die("Usage: build [-b] bootsect setup system [rootdev] [> image]");
+}
+
+int main(int argc, char **argv)
+{
+ unsigned int i, c, sz, setup_sectors;
+ uint32_t sys_size;
+ uint8_t major_root, minor_root;
+ struct stat sb;
+
+ if (argc > 2 && !strcmp(argv[1], "-b")) {
+ is_big_kernel = 1;
+ argc--, argv++;
+ }
+ if ((argc < 4) || (argc > 5))
+ usage();
+ if (argc > 4) {
+ if (!strcmp(argv[4], "CURRENT")) {
+ if (stat("/", &sb)) {
+ perror("/");
+ die("Couldn't stat /");
+ }
+ major_root = major(sb.st_dev);
+ minor_root = minor(sb.st_dev);
+ } else if (strcmp(argv[4], "FLOPPY")) {
+ if (stat(argv[4], &sb)) {
+ perror(argv[4]);
+ die("Couldn't stat root device.");
+ }
+ major_root = major(sb.st_rdev);
+ minor_root = minor(sb.st_rdev);
+ } else {
+ major_root = 0;
+ minor_root = 0;
+ }
+ } else {
+ major_root = DEFAULT_MAJOR_ROOT;
+ minor_root = DEFAULT_MINOR_ROOT;
+ }
+ fprintf(stderr, "Root device is (%d, %d)\n", major_root, minor_root);
+
+ file_open(argv[1]);
+ i = read(fd, buf, sizeof(buf));
+ fprintf(stderr, "Boot sector %d bytes.\n", i);
+ if (i != 512)
+ die("Boot block must be exactly 512 bytes");
+ if (buf[510] != 0x55 || buf[511] != 0xaa)
+ die("Boot block hasn't got boot flag (0xAA55)");
+ buf[508] = minor_root;
+ buf[509] = major_root;
+ if (write(1, buf, 512) != 512)
+ die("Write call failed");
+ close(fd);
+
+ /* Copy the setup code */
+ file_open(argv[2]);
+ for (i = 0; (c = read(fd, buf, sizeof(buf))) > 0; i += c)
+ if (write(1, buf, c) != c)
+ die("Write call failed");
+ if (c != 0)
+ die("read-error on `setup'");
+ close(fd);
+
+ /* Pad unused space with zeros */
+ setup_sectors = (i + 511) / 512;
+ /* for compatibility with ancient versions of LILO. */
+ if (setup_sectors < SETUP_SECTS)
+ setup_sectors = SETUP_SECTS;
+ fprintf(stderr, "Setup is %d bytes.\n", i);
+ memset(buf, 0, sizeof(buf));
+ while (i < setup_sectors * 512) {
+ c = setup_sectors * 512 - i;
+ if (c > sizeof(buf))
+ c = sizeof(buf);
+ if (write(1, buf, c) != c)
+ die("Write call failed");
+ i += c;
+ }
+
+ file_open(argv[3]);
+ if (fstat(fd, &sb))
+ die("Unable to stat `%s': %m", argv[3]);
+ sz = sb.st_size;
+ fprintf(stderr, "System is %d kB\n", sz / 1024);
+ sys_size = (sz + 15) / 16;
+ /* 0x28000*16 = 2.5 MB, conservative estimate for the current maximum */
+ if (sys_size > (is_big_kernel ? 0x28000 : DEF_SYSSIZE))
+ die("System is too big. Try using %smodules.",
+ is_big_kernel ? "" : "bzImage or ");
+ if (sys_size > 0xffff)
+ fprintf(stderr,
+ "warning: kernel is too big for standalone boot "
+ "from floppy\n");
+ while (sz > 0) {
+ int l, n;
+
+ l = (sz > sizeof(buf)) ? sizeof(buf) : sz;
+ n = read(fd, buf, l);
+ if (n != l) {
+ if (n < 0)
+ die("Error reading %s: %m", argv[3]);
+ else
+ die("%s: Unexpected EOF", argv[3]);
+ }
+ if (write(1, buf, l) != l)
+ die("Write failed");
+ sz -= l;
+ }
+ close(fd);
+
+ /* Write sizes to the bootsector */
+ if (lseek(1, 497, SEEK_SET) != 497)
+ die("Output: seek failed");
+ buf[0] = setup_sectors;
+ if (write(1, buf, 1) != 1)
+ die("Write of setup sector count failed");
+ if (lseek(1, 500, SEEK_SET) != 500)
+ die("Output: seek failed");
+ buf[0] = (sys_size & 0xff);
+ buf[1] = ((sys_size >> 8) & 0xff);
+ if (write(1, buf, 2) != 2)
+ die("Write of image length failed");
+
+ return 0;
+}
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.24-rc2
+# Fri Nov 16 13:36:38 2007
+#
+CONFIG_MN10300=y
+CONFIG_AM33=y
+CONFIG_MMU=y
+# CONFIG_HIGHMEM is not set
+# CONFIG_NUMA is not set
+CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_BUG=y
+CONFIG_QUICKLIST=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+# CONFIG_ARCH_SUPPORTS_AOUT is not set
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HOTPLUG_CPU is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_AUDIT is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CGROUPS is not set
+# CONFIG_FAIR_GROUP_SCHED is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+# CONFIG_MODULES is not set
+# CONFIG_BLOCK is not set
+
+#
+# Matsushita MN10300 system setup
+#
+CONFIG_MN10300_UNIT_ASB2303=y
+# CONFIG_MN10300_UNIT_ASB2305 is not set
+CONFIG_MN10300_PROC_MN103E010=y
+CONFIG_MN10300_CPU_AM33V2=y
+CONFIG_FPU=y
+CONFIG_MN10300_CACHE_WBACK=y
+# CONFIG_MN10300_CACHE_WTHRU is not set
+# CONFIG_MN10300_CACHE_DISABLED is not set
+
+#
+# Memory layout options
+#
+CONFIG_KERNEL_RAM_BASE_ADDRESS=0x90000000
+CONFIG_INTERRUPT_VECTOR_BASE=0x90000000
+CONFIG_KERNEL_TEXT_ADDRESS=0x90001000
+CONFIG_KERNEL_ZIMAGE_BASE_ADDRESS=0x90700000
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_BKL=y
+CONFIG_MN10300_CURRENT_IN_E2=y
+CONFIG_MN10300_USING_JTAG=y
+CONFIG_MN10300_RTC=y
+CONFIG_MN10300_WD_TIMER=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+
+#
+# MN10300 internal serial options
+#
+CONFIG_MN10300_PROC_HAS_TTYSM0=y
+CONFIG_MN10300_PROC_HAS_TTYSM1=y
+CONFIG_MN10300_PROC_HAS_TTYSM2=y
+CONFIG_MN10300_TTYSM=y
+CONFIG_MN10300_TTYSM_CONSOLE=y
+CONFIG_MN10300_TTYSM0=y
+CONFIG_MN10300_TTYSM0_TIMER8=y
+# CONFIG_MN10300_TTYSM0_TIMER2 is not set
+CONFIG_MN10300_TTYSM1=y
+CONFIG_MN10300_TTYSM1_TIMER9=y
+# CONFIG_MN10300_TTYSM1_TIMER3 is not set
+# CONFIG_MN10300_TTYSM2 is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+# CONFIG_SPARSEMEM_STATIC is not set
+# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=1
+CONFIG_VIRT_TO_BUS=y
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+
+#
+# Executable formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_MAC80211 is not set
+# CONFIG_IEEE80211 is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=0
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+CONFIG_MTD_CFI_I4=y
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0x0
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_EEPROM_93CX6 is not set
+
+#
+# SCSI device support
+#
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NETDEVICES_MULTIQUEUE is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_SMC91X=y
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_SHAPER is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+# CONFIG_INPUT is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_RSA is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_RTC=y
+# CONFIG_R3964 is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_WATCHDOG is not set
+
+#
+# Sonics Silicon Backplane
+#
+CONFIG_SSB_POSSIBLE=y
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_RTC_CLASS is not set
+
+#
+# Userspace I/O
+#
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_DNOTIFY=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFS_DIRECTIO is not set
+# CONFIG_NFSD is not set
+CONFIG_ROOT_NFS=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_BIND34 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_SAMPLES is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+
+#
+# Profiling support
+#
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
--- /dev/null
+#
+# Makefile for the MN10300-specific core kernel code
+#
+extra-y := head.o init_task.o vmlinux.lds
+
+obj-y := process.o semaphore.o signal.o entry.o fpu.o traps.o irq.o \
+ ptrace.o setup.o time.o sys_mn10300.o io.o kthread.o \
+ switch_to.o mn10300_ksyms.o kernel_execve.o
+
+obj-$(CONFIG_MN10300_WD_TIMER) += mn10300-watchdog.o mn10300-watchdog-low.o
+
+obj-$(CONFIG_FPU) += fpu-low.o
+
+obj-$(CONFIG_MN10300_TTYSM) += mn10300-serial.o mn10300-serial-low.o \
+ mn10300-debug.o
+obj-$(CONFIG_GDBSTUB) += gdb-stub.o gdb-low.o
+obj-$(CONFIG_GDBSTUB_ON_TTYSx) += gdb-io-serial.o gdb-io-serial-low.o
+obj-$(CONFIG_GDBSTUB_ON_TTYSMx) += gdb-io-ttysm.o gdb-io-ttysm-low.o
+
+ifneq ($(CONFIG_MN10300_CACHE_DISABLED),y)
+obj-$(CONFIG_GDBSTUB) += gdb-cache.o
+endif
+
+obj-$(CONFIG_MN10300_RTC) += rtc.o
+obj-$(CONFIG_PROFILE) += profile.o profile-low.o
+obj-$(CONFIG_MODULES) += module.o
+obj-$(CONFIG_KPROBES) += kprobes.o
--- /dev/null
+/*
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed
+ * to extract and format the required data.
+ */
+
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/personality.h>
+#include <asm/ucontext.h>
+#include <asm/processor.h>
+#include <asm/thread_info.h>
+#include <asm/ptrace.h>
+#include "sigframe.h"
+#include "mn10300-serial.h"
+
+#define DEFINE(sym, val) \
+ asm volatile("\n->" #sym " %0 " #val : : "i" (val))
+
+#define BLANK() asm volatile("\n->")
+
+#define OFFSET(sym, str, mem) \
+ DEFINE(sym, offsetof(struct str, mem));
+
+void foo(void)
+{
+ OFFSET(SIGCONTEXT_d0, sigcontext, d0);
+ OFFSET(SIGCONTEXT_d1, sigcontext, d1);
+ BLANK();
+
+ OFFSET(TI_task, thread_info, task);
+ OFFSET(TI_exec_domain, thread_info, exec_domain);
+ OFFSET(TI_flags, thread_info, flags);
+ OFFSET(TI_cpu, thread_info, cpu);
+ OFFSET(TI_preempt_count, thread_info, preempt_count);
+ OFFSET(TI_addr_limit, thread_info, addr_limit);
+ OFFSET(TI_restart_block, thread_info, restart_block);
+ BLANK();
+
+ OFFSET(REG_D0, pt_regs, d0);
+ OFFSET(REG_D1, pt_regs, d1);
+ OFFSET(REG_D2, pt_regs, d2);
+ OFFSET(REG_D3, pt_regs, d3);
+ OFFSET(REG_A0, pt_regs, a0);
+ OFFSET(REG_A1, pt_regs, a1);
+ OFFSET(REG_A2, pt_regs, a2);
+ OFFSET(REG_A3, pt_regs, a3);
+ OFFSET(REG_E0, pt_regs, e0);
+ OFFSET(REG_E1, pt_regs, e1);
+ OFFSET(REG_E2, pt_regs, e2);
+ OFFSET(REG_E3, pt_regs, e3);
+ OFFSET(REG_E4, pt_regs, e4);
+ OFFSET(REG_E5, pt_regs, e5);
+ OFFSET(REG_E6, pt_regs, e6);
+ OFFSET(REG_E7, pt_regs, e7);
+ OFFSET(REG_SP, pt_regs, sp);
+ OFFSET(REG_EPSW, pt_regs, epsw);
+ OFFSET(REG_PC, pt_regs, pc);
+ OFFSET(REG_LAR, pt_regs, lar);
+ OFFSET(REG_LIR, pt_regs, lir);
+ OFFSET(REG_MDR, pt_regs, mdr);
+ OFFSET(REG_MCVF, pt_regs, mcvf);
+ OFFSET(REG_MCRL, pt_regs, mcrl);
+ OFFSET(REG_MCRH, pt_regs, mcrh);
+ OFFSET(REG_MDRQ, pt_regs, mdrq);
+ OFFSET(REG_ORIG_D0, pt_regs, orig_d0);
+ OFFSET(REG_NEXT, pt_regs, next);
+ DEFINE(REG__END, sizeof(struct pt_regs));
+ BLANK();
+
+ OFFSET(THREAD_UREGS, thread_struct, uregs);
+ OFFSET(THREAD_PC, thread_struct, pc);
+ OFFSET(THREAD_SP, thread_struct, sp);
+ OFFSET(THREAD_A3, thread_struct, a3);
+ OFFSET(THREAD_USP, thread_struct, usp);
+ OFFSET(THREAD_FRAME, thread_struct, __frame);
+ BLANK();
+
+ DEFINE(CLONE_VM_asm, CLONE_VM);
+ DEFINE(CLONE_FS_asm, CLONE_FS);
+ DEFINE(CLONE_FILES_asm, CLONE_FILES);
+ DEFINE(CLONE_SIGHAND_asm, CLONE_SIGHAND);
+ DEFINE(CLONE_UNTRACED_asm, CLONE_UNTRACED);
+ DEFINE(SIGCHLD_asm, SIGCHLD);
+ BLANK();
+
+ OFFSET(EXEC_DOMAIN_handler, exec_domain, handler);
+ OFFSET(RT_SIGFRAME_sigcontext, rt_sigframe, uc.uc_mcontext);
+
+ DEFINE(PAGE_SIZE_asm, PAGE_SIZE);
+
+ OFFSET(__rx_buffer, mn10300_serial_port, rx_buffer);
+ OFFSET(__rx_inp, mn10300_serial_port, rx_inp);
+ OFFSET(__rx_outp, mn10300_serial_port, rx_outp);
+ OFFSET(__tx_info_buffer, mn10300_serial_port, uart.info);
+ OFFSET(__tx_xchar, mn10300_serial_port, tx_xchar);
+ OFFSET(__tx_break, mn10300_serial_port, tx_break);
+ OFFSET(__intr_flags, mn10300_serial_port, intr_flags);
+ OFFSET(__rx_icr, mn10300_serial_port, rx_icr);
+ OFFSET(__tx_icr, mn10300_serial_port, tx_icr);
+ OFFSET(__tm_icr, mn10300_serial_port, _tmicr);
+ OFFSET(__iobase, mn10300_serial_port, _iobase);
+
+ DEFINE(__UART_XMIT_SIZE, UART_XMIT_SIZE);
+ OFFSET(__xmit_buffer, uart_info, xmit.buf);
+ OFFSET(__xmit_head, uart_info, xmit.head);
+ OFFSET(__xmit_tail, uart_info, xmit.tail);
+}
--- /dev/null
+###############################################################################
+#
+# MN10300 Exception and interrupt entry points
+#
+# Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Modified by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+###############################################################################
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/smp.h>
+#include <asm/system.h>
+#include <asm/thread_info.h>
+#include <asm/intctl-regs.h>
+#include <asm/busctl-regs.h>
+#include <asm/timer-regs.h>
+#include <asm/unit/leds.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/errno.h>
+#include <asm/asm-offsets.h>
+#include <asm/frame.inc>
+
+#ifdef CONFIG_PREEMPT
+#define preempt_stop __cli
+#else
+#define preempt_stop
+#define resume_kernel restore_all
+#endif
+
+ .macro __cli
+ and ~EPSW_IM,epsw
+ or EPSW_IE|MN10300_CLI_LEVEL,epsw
+ nop
+ nop
+ nop
+ .endm
+ .macro __sti
+ or EPSW_IE|EPSW_IM_7,epsw
+ .endm
+
+
+ .am33_2
+
+###############################################################################
+#
+# the return path for a forked child
+# - on entry, D0 holds the address of the previous task to run
+#
+###############################################################################
+ENTRY(ret_from_fork)
+ call schedule_tail[],0
+ GET_THREAD_INFO a2
+
+ # return 0 to indicate child process
+ clr d0
+ mov d0,(REG_D0,fp)
+ jmp syscall_exit
+
+###############################################################################
+#
+# system call handler
+#
+###############################################################################
+ENTRY(system_call)
+ add -4,sp
+ SAVE_ALL
+ mov d0,(REG_ORIG_D0,fp)
+ GET_THREAD_INFO a2
+ cmp nr_syscalls,d0
+ bcc syscall_badsys
+ btst _TIF_SYSCALL_TRACE,(TI_flags,a2)
+ bne syscall_trace_entry
+syscall_call:
+ add d0,d0,a1
+ add a1,a1
+ mov (REG_A0,fp),d0
+ mov (sys_call_table,a1),a0
+ calls (a0)
+ mov d0,(REG_D0,fp)
+syscall_exit:
+ # make sure we don't miss an interrupt setting need_resched or
+ # sigpending between sampling and the rti
+ __cli
+ mov (TI_flags,a2),d2
+ btst _TIF_ALLWORK_MASK,d2
+ bne syscall_exit_work
+restore_all:
+ RESTORE_ALL
+
+###############################################################################
+#
+# perform work that needs to be done immediately before resumption and syscall
+# tracing
+#
+###############################################################################
+ ALIGN
+syscall_exit_work:
+ btst _TIF_SYSCALL_TRACE,d2
+ beq work_pending
+ __sti # could let do_syscall_trace() call
+ # schedule() instead
+ mov fp,d0
+ mov 1,d1
+ call do_syscall_trace[],0 # do_syscall_trace(regs,entryexit)
+ jmp resume_userspace
+
+ ALIGN
+work_pending:
+ btst _TIF_NEED_RESCHED,d2
+ beq work_notifysig
+
+work_resched:
+ call schedule[],0
+
+ # make sure we don't miss an interrupt setting need_resched or
+ # sigpending between sampling and the rti
+ __cli
+
+ # is there any work to be done other than syscall tracing?
+ mov (TI_flags,a2),d2
+ btst _TIF_WORK_MASK,d2
+ beq restore_all
+ btst _TIF_NEED_RESCHED,d2
+ bne work_resched
+
+ # deal with pending signals and notify-resume requests
+work_notifysig:
+ mov fp,d0
+ mov d2,d1
+ call do_notify_resume[],0
+ jmp resume_userspace
+
+ # perform syscall entry tracing
+syscall_trace_entry:
+ mov -ENOSYS,d0
+ mov d0,(REG_D0,fp)
+ mov fp,d0
+ clr d1
+ call do_syscall_trace[],0
+ mov (REG_ORIG_D0,fp),d0
+ mov (REG_D1,fp),d1
+ cmp nr_syscalls,d0
+ bcs syscall_call
+ jmp syscall_exit
+
+syscall_badsys:
+ mov -ENOSYS,d0
+ mov d0,(REG_D0,fp)
+ jmp resume_userspace
+
+ # userspace resumption stub bypassing syscall exit tracing
+ .globl ret_from_exception, ret_from_intr
+ ALIGN
+ret_from_exception:
+ preempt_stop
+ret_from_intr:
+ GET_THREAD_INFO a2
+ mov (REG_EPSW,fp),d0 # need to deliver signals before
+ # returning to userspace
+ and EPSW_nSL,d0
+ beq resume_kernel # returning to supervisor mode
+
+ENTRY(resume_userspace)
+ # make sure we don't miss an interrupt setting need_resched or
+ # sigpending between sampling and the rti
+ __cli
+
+ # is there any work to be done on int/exception return?
+ mov (TI_flags,a2),d2
+ btst _TIF_WORK_MASK,d2
+ bne work_pending
+ jmp restore_all
+
+#ifdef CONFIG_PREEMPT
+ENTRY(resume_kernel)
+ mov (TI_preempt_count,a2),d0 # non-zero preempt_count ?
+ cmp 0,d0
+ bne restore_all
+
+need_resched:
+ btst _TIF_NEED_RESCHED,(TI_flags,a2)
+ beq restore_all
+ mov (REG_EPSW,fp),d0
+ and EPSW_IM,d0
+ cmp EPSW_IM_7,d0 # interrupts off (exception path) ?
+ beq restore_all
+ call preempt_schedule_irq[],0
+ jmp need_resched
+#endif
+
+
+###############################################################################
+#
+# IRQ handler entry point
+# - intended to be entered at multiple priorities
+#
+###############################################################################
+ENTRY(irq_handler)
+ add -4,sp
+ SAVE_ALL
+
+ # it's not a syscall
+ mov 0xffffffff,d0
+ mov d0,(REG_ORIG_D0,fp)
+
+ mov fp,d0
+ call do_IRQ[],0 # do_IRQ(regs)
+
+ jmp ret_from_intr
+
+###############################################################################
+#
+# Monitor Signal handler entry point
+#
+###############################################################################
+ENTRY(monitor_signal)
+ movbu (0xae000001),d1
+ cmp 1,d1
+ beq monsignal
+ ret [],0
+
+monsignal:
+ or EPSW_NMID,epsw
+ mov d0,a0
+ mov a0,sp
+ mov (REG_EPSW,fp),d1
+ and ~EPSW_nSL,d1
+ mov d1,(REG_EPSW,fp)
+ movm (sp),[d2,d3,a2,a3,exreg0,exreg1,exother]
+ mov (sp),a1
+ mov a1,usp
+ movm (sp),[other]
+ add 4,sp
+here: jmp 0x8e000008-here+0x8e000008
+
+###############################################################################
+#
+# Double Fault handler entry point
+# - note that there will not be a stack, D0/A0 will hold EPSW/PC as were
+#
+###############################################################################
+ .section .bss
+ .balign THREAD_SIZE
+ .space THREAD_SIZE
+__df_stack:
+ .previous
+
+ENTRY(double_fault)
+ mov a0,(__df_stack-4) # PC as was
+ mov d0,(__df_stack-8) # EPSW as was
+ mn10300_set_dbfleds # display 'db-f' on the LEDs
+ mov 0xaa55aa55,d0
+ mov d0,(__df_stack-12) # no ORIG_D0
+ mov sp,a0 # save corrupted SP
+ mov __df_stack-12,sp # emergency supervisor stack
+ SAVE_ALL
+ mov a0,(REG_A0,fp) # save corrupted SP as A0 (which got
+ # clobbered by the CPU)
+ mov fp,d0
+ calls do_double_fault
+double_fault_loop:
+ bra double_fault_loop
+
+###############################################################################
+#
+# Bus Error handler entry point
+# - handle external (async) bus errors separately
+#
+###############################################################################
+ENTRY(raw_bus_error)
+ add -4,sp
+ mov d0,(sp)
+ mov (BCBERR),d0 # what
+ btst BCBERR_BEMR_DMA,d0 # see if it was an external bus error
+ beq __common_exception_aux # it wasn't
+
+ SAVE_ALL
+ mov (BCBEAR),d1 # destination of erroneous access
+
+ mov (REG_ORIG_D0,fp),d2
+ mov d2,(REG_D0,fp)
+ mov -1,d2
+ mov d2,(REG_ORIG_D0,fp)
+
+ add -4,sp
+ mov fp,(12,sp) # frame pointer
+ call io_bus_error[],0
+ jmp restore_all
+
+###############################################################################
+#
+# Miscellaneous exception entry points
+#
+###############################################################################
+ENTRY(nmi_handler)
+ add -4,sp
+ mov d0,(sp)
+ mov (TBR),d0
+ bra __common_exception_nonmi
+
+ENTRY(__common_exception)
+ add -4,sp
+ mov d0,(sp)
+
+__common_exception_aux:
+ mov (TBR),d0
+ and ~EPSW_NMID,epsw # turn NMIs back on if not NMI
+ or EPSW_IE,epsw
+
+__common_exception_nonmi:
+ and 0x0000FFFF,d0 # turn the exception code into a vector
+ # table index
+
+ btst 0x00000007,d0
+ bne 1f
+ cmp 0x00000400,d0
+ bge 1f
+
+ SAVE_ALL # build the stack frame
+
+ mov (REG_D0,fp),a2 # get the exception number
+ mov (REG_ORIG_D0,fp),d0
+ mov d0,(REG_D0,fp)
+ mov -1,d0
+ mov d0,(REG_ORIG_D0,fp)
+
+#ifdef CONFIG_GDBSTUB
+ btst 0x01,(gdbstub_busy)
+ beq 2f
+ and ~EPSW_IE,epsw
+ mov fp,d0
+ mov a2,d1
+ call gdbstub_exception[],0 # gdbstub itself caused an exception
+ bra restore_all
+2:
+#endif
+
+ mov fp,d0 # arg 0: stacked register file
+ mov a2,d1 # arg 1: exception number
+ lsr 1,a2
+
+ mov (exception_table,a2),a2
+ calls (a2)
+ jmp ret_from_exception
+
+1: pi # BUG() equivalent
+
+###############################################################################
+#
+# Exception handler functions table
+#
+###############################################################################
+ .data
+ENTRY(exception_table)
+ .rept 0x400>>1
+ .long uninitialised_exception
+ .endr
+ .previous
+
+###############################################################################
+#
+# Change an entry in the exception table
+# - D0 exception code, D1 handler
+#
+###############################################################################
+ENTRY(set_excp_vector)
+ lsr 1,d0
+ add exception_table,d0
+ mov d1,(d0)
+ mov 4,d1
+#if defined(CONFIG_MN10300_CACHE_WBACK)
+ jmp mn10300_dcache_flush_inv_range2
+#else
+ ret [],0
+#endif
+
+###############################################################################
+#
+# System call table
+#
+###############################################################################
+ .data
+ENTRY(sys_call_table)
+ .long sys_restart_syscall /* 0 */
+ .long sys_exit
+ .long sys_fork
+ .long sys_read
+ .long sys_write
+ .long sys_open /* 5 */
+ .long sys_close
+ .long sys_waitpid
+ .long sys_creat
+ .long sys_link
+ .long sys_unlink /* 10 */
+ .long sys_execve
+ .long sys_chdir
+ .long sys_time
+ .long sys_mknod
+ .long sys_chmod /* 15 */
+ .long sys_lchown16
+ .long sys_ni_syscall /* old break syscall holder */
+ .long sys_stat
+ .long sys_lseek
+ .long sys_getpid /* 20 */
+ .long sys_mount
+ .long sys_oldumount
+ .long sys_setuid16
+ .long sys_getuid16
+ .long sys_stime /* 25 */
+ .long sys_ptrace
+ .long sys_alarm
+ .long sys_fstat
+ .long sys_pause
+ .long sys_utime /* 30 */
+ .long sys_ni_syscall /* old stty syscall holder */
+ .long sys_ni_syscall /* old gtty syscall holder */
+ .long sys_access
+ .long sys_nice
+ .long sys_ni_syscall /* 35 - old ftime syscall holder */
+ .long sys_sync
+ .long sys_kill
+ .long sys_rename
+ .long sys_mkdir
+ .long sys_rmdir /* 40 */
+ .long sys_dup
+ .long sys_pipe
+ .long sys_times
+ .long sys_ni_syscall /* old prof syscall holder */
+ .long sys_brk /* 45 */
+ .long sys_setgid16
+ .long sys_getgid16
+ .long sys_signal
+ .long sys_geteuid16
+ .long sys_getegid16 /* 50 */
+ .long sys_acct
+ .long sys_umount /* recycled never used phys() */
+ .long sys_ni_syscall /* old lock syscall holder */
+ .long sys_ioctl
+ .long sys_fcntl /* 55 */
+ .long sys_ni_syscall /* old mpx syscall holder */
+ .long sys_setpgid
+ .long sys_ni_syscall /* old ulimit syscall holder */
+ .long sys_ni_syscall /* old sys_olduname */
+ .long sys_umask /* 60 */
+ .long sys_chroot
+ .long sys_ustat
+ .long sys_dup2
+ .long sys_getppid
+ .long sys_getpgrp /* 65 */
+ .long sys_setsid
+ .long sys_sigaction
+ .long sys_sgetmask
+ .long sys_ssetmask
+ .long sys_setreuid16 /* 70 */
+ .long sys_setregid16
+ .long sys_sigsuspend
+ .long sys_sigpending
+ .long sys_sethostname
+ .long sys_setrlimit /* 75 */
+ .long sys_old_getrlimit
+ .long sys_getrusage
+ .long sys_gettimeofday
+ .long sys_settimeofday
+ .long sys_getgroups16 /* 80 */
+ .long sys_setgroups16
+ .long old_select
+ .long sys_symlink
+ .long sys_lstat
+ .long sys_readlink /* 85 */
+ .long sys_uselib
+ .long sys_swapon
+ .long sys_reboot
+ .long old_readdir
+ .long old_mmap /* 90 */
+ .long sys_munmap
+ .long sys_truncate
+ .long sys_ftruncate
+ .long sys_fchmod
+ .long sys_fchown16 /* 95 */
+ .long sys_getpriority
+ .long sys_setpriority
+ .long sys_ni_syscall /* old profil syscall holder */
+ .long sys_statfs
+ .long sys_fstatfs /* 100 */
+ .long sys_ni_syscall /* ioperm */
+ .long sys_socketcall
+ .long sys_syslog
+ .long sys_setitimer
+ .long sys_getitimer /* 105 */
+ .long sys_newstat
+ .long sys_newlstat
+ .long sys_newfstat
+ .long sys_ni_syscall /* old sys_uname */
+ .long sys_ni_syscall /* 110 - iopl */
+ .long sys_vhangup
+ .long sys_ni_syscall /* old "idle" system call */
+ .long sys_ni_syscall /* vm86old */
+ .long sys_wait4
+ .long sys_swapoff /* 115 */
+ .long sys_sysinfo
+ .long sys_ipc
+ .long sys_fsync
+ .long sys_sigreturn
+ .long sys_clone /* 120 */
+ .long sys_setdomainname
+ .long sys_newuname
+ .long sys_ni_syscall /* modify_ldt */
+ .long sys_adjtimex
+ .long sys_mprotect /* 125 */
+ .long sys_sigprocmask
+ .long sys_ni_syscall /* old "create_module" */
+ .long sys_init_module
+ .long sys_delete_module
+ .long sys_ni_syscall /* 130: old "get_kernel_syms" */
+ .long sys_quotactl
+ .long sys_getpgid
+ .long sys_fchdir
+ .long sys_bdflush
+ .long sys_sysfs /* 135 */
+ .long sys_personality
+ .long sys_ni_syscall /* reserved for afs_syscall */
+ .long sys_setfsuid16
+ .long sys_setfsgid16
+ .long sys_llseek /* 140 */
+ .long sys_getdents
+ .long sys_select
+ .long sys_flock
+ .long sys_msync
+ .long sys_readv /* 145 */
+ .long sys_writev
+ .long sys_getsid
+ .long sys_fdatasync
+ .long sys_sysctl
+ .long sys_mlock /* 150 */
+ .long sys_munlock
+ .long sys_mlockall
+ .long sys_munlockall
+ .long sys_sched_setparam
+ .long sys_sched_getparam /* 155 */
+ .long sys_sched_setscheduler
+ .long sys_sched_getscheduler
+ .long sys_sched_yield
+ .long sys_sched_get_priority_max
+ .long sys_sched_get_priority_min /* 160 */
+ .long sys_sched_rr_get_interval
+ .long sys_nanosleep
+ .long sys_mremap
+ .long sys_setresuid16
+ .long sys_getresuid16 /* 165 */
+ .long sys_ni_syscall /* vm86 */
+ .long sys_ni_syscall /* Old sys_query_module */
+ .long sys_poll
+ .long sys_nfsservctl
+ .long sys_setresgid16 /* 170 */
+ .long sys_getresgid16
+ .long sys_prctl
+ .long sys_rt_sigreturn
+ .long sys_rt_sigaction
+ .long sys_rt_sigprocmask /* 175 */
+ .long sys_rt_sigpending
+ .long sys_rt_sigtimedwait
+ .long sys_rt_sigqueueinfo
+ .long sys_rt_sigsuspend
+ .long sys_pread64 /* 180 */
+ .long sys_pwrite64
+ .long sys_chown16
+ .long sys_getcwd
+ .long sys_capget
+ .long sys_capset /* 185 */
+ .long sys_sigaltstack
+ .long sys_sendfile
+ .long sys_ni_syscall /* reserved for streams1 */
+ .long sys_ni_syscall /* reserved for streams2 */
+ .long sys_vfork /* 190 */
+ .long sys_getrlimit
+ .long sys_mmap2
+ .long sys_truncate64
+ .long sys_ftruncate64
+ .long sys_stat64 /* 195 */
+ .long sys_lstat64
+ .long sys_fstat64
+ .long sys_lchown
+ .long sys_getuid
+ .long sys_getgid /* 200 */
+ .long sys_geteuid
+ .long sys_getegid
+ .long sys_setreuid
+ .long sys_setregid
+ .long sys_getgroups /* 205 */
+ .long sys_setgroups
+ .long sys_fchown
+ .long sys_setresuid
+ .long sys_getresuid
+ .long sys_setresgid /* 210 */
+ .long sys_getresgid
+ .long sys_chown
+ .long sys_setuid
+ .long sys_setgid
+ .long sys_setfsuid /* 215 */
+ .long sys_setfsgid
+ .long sys_pivot_root
+ .long sys_mincore
+ .long sys_madvise
+ .long sys_getdents64 /* 220 */
+ .long sys_fcntl64
+ .long sys_ni_syscall /* reserved for TUX */
+ .long sys_ni_syscall
+ .long sys_gettid
+ .long sys_readahead /* 225 */
+ .long sys_setxattr
+ .long sys_lsetxattr
+ .long sys_fsetxattr
+ .long sys_getxattr
+ .long sys_lgetxattr /* 230 */
+ .long sys_fgetxattr
+ .long sys_listxattr
+ .long sys_llistxattr
+ .long sys_flistxattr
+ .long sys_removexattr /* 235 */
+ .long sys_lremovexattr
+ .long sys_fremovexattr
+ .long sys_tkill
+ .long sys_sendfile64
+ .long sys_futex /* 240 */
+ .long sys_sched_setaffinity
+ .long sys_sched_getaffinity
+ .long sys_ni_syscall /* sys_set_thread_area */
+ .long sys_ni_syscall /* sys_get_thread_area */
+ .long sys_io_setup /* 245 */
+ .long sys_io_destroy
+ .long sys_io_getevents
+ .long sys_io_submit
+ .long sys_io_cancel
+ .long sys_fadvise64 /* 250 */
+ .long sys_ni_syscall
+ .long sys_exit_group
+ .long sys_lookup_dcookie
+ .long sys_epoll_create
+ .long sys_epoll_ctl /* 255 */
+ .long sys_epoll_wait
+ .long sys_remap_file_pages
+ .long sys_set_tid_address
+ .long sys_timer_create
+ .long sys_timer_settime /* 260 */
+ .long sys_timer_gettime
+ .long sys_timer_getoverrun
+ .long sys_timer_delete
+ .long sys_clock_settime
+ .long sys_clock_gettime /* 265 */
+ .long sys_clock_getres
+ .long sys_clock_nanosleep
+ .long sys_statfs64
+ .long sys_fstatfs64
+ .long sys_tgkill /* 270 */
+ .long sys_utimes
+ .long sys_fadvise64_64
+ .long sys_ni_syscall /* sys_vserver */
+ .long sys_mbind
+ .long sys_get_mempolicy /* 275 */
+ .long sys_set_mempolicy
+ .long sys_mq_open
+ .long sys_mq_unlink
+ .long sys_mq_timedsend
+ .long sys_mq_timedreceive /* 280 */
+ .long sys_mq_notify
+ .long sys_mq_getsetattr
+ .long sys_kexec_load
+ .long sys_waitid
+ .long sys_ni_syscall /* 285 */ /* available */
+ .long sys_add_key
+ .long sys_request_key
+ .long sys_keyctl
+ .long sys_cacheflush
+ .long sys_ioprio_set /* 290 */
+ .long sys_ioprio_get
+ .long sys_inotify_init
+ .long sys_inotify_add_watch
+ .long sys_inotify_rm_watch
+ .long sys_migrate_pages /* 295 */
+ .long sys_openat
+ .long sys_mkdirat
+ .long sys_mknodat
+ .long sys_fchownat
+ .long sys_futimesat /* 300 */
+ .long sys_fstatat64
+ .long sys_unlinkat
+ .long sys_renameat
+ .long sys_linkat
+ .long sys_symlinkat /* 305 */
+ .long sys_readlinkat
+ .long sys_fchmodat
+ .long sys_faccessat
+ .long sys_pselect6
+ .long sys_ppoll /* 310 */
+ .long sys_unshare
+ .long sys_set_robust_list
+ .long sys_get_robust_list
+ .long sys_splice
+ .long sys_sync_file_range /* 315 */
+ .long sys_tee
+ .long sys_vmsplice
+ .long sys_move_pages
+ .long sys_getcpu
+ .long sys_epoll_pwait /* 320 */
+ .long sys_utimensat
+ .long sys_signalfd
+ .long sys_timerfd_create
+ .long sys_eventfd
+ .long sys_fallocate /* 325 */
+ .long sys_timerfd_settime
+ .long sys_timerfd_gettime
+
+
+nr_syscalls=(.-sys_call_table)/4
--- /dev/null
+/* MN10300 Low level FPU management operations
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <asm/cpu-regs.h>
+
+###############################################################################
+#
+# void fpu_init_state(void)
+# - initialise the FPU
+#
+###############################################################################
+ .globl fpu_init_state
+ .type fpu_init_state,@function
+fpu_init_state:
+ mov epsw,d0
+ or EPSW_FE,epsw
+
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ nop
+ nop
+ nop
+#endif
+ fmov 0,fs0
+ fmov fs0,fs1
+ fmov fs0,fs2
+ fmov fs0,fs3
+ fmov fs0,fs4
+ fmov fs0,fs5
+ fmov fs0,fs6
+ fmov fs0,fs7
+ fmov fs0,fs8
+ fmov fs0,fs9
+ fmov fs0,fs10
+ fmov fs0,fs11
+ fmov fs0,fs12
+ fmov fs0,fs13
+ fmov fs0,fs14
+ fmov fs0,fs15
+ fmov fs0,fs16
+ fmov fs0,fs17
+ fmov fs0,fs18
+ fmov fs0,fs19
+ fmov fs0,fs20
+ fmov fs0,fs21
+ fmov fs0,fs22
+ fmov fs0,fs23
+ fmov fs0,fs24
+ fmov fs0,fs25
+ fmov fs0,fs26
+ fmov fs0,fs27
+ fmov fs0,fs28
+ fmov fs0,fs29
+ fmov fs0,fs30
+ fmov fs0,fs31
+ fmov FPCR_INIT,fpcr
+
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ nop
+ nop
+ nop
+#endif
+ mov d0,epsw
+ ret [],0
+
+ .size fpu_init_state,.-fpu_init_state
+
+###############################################################################
+#
+# void fpu_save(struct fpu_state_struct *)
+# - save the fpu state
+# - note that an FPU Operational exception might occur during this process
+#
+###############################################################################
+ .globl fpu_save
+ .type fpu_save,@function
+fpu_save:
+ mov epsw,d1
+ or EPSW_FE,epsw /* enable the FPU so we can access it */
+
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ nop
+ nop
+#endif
+ mov d0,a0
+ fmov fs0,(a0+)
+ fmov fs1,(a0+)
+ fmov fs2,(a0+)
+ fmov fs3,(a0+)
+ fmov fs4,(a0+)
+ fmov fs5,(a0+)
+ fmov fs6,(a0+)
+ fmov fs7,(a0+)
+ fmov fs8,(a0+)
+ fmov fs9,(a0+)
+ fmov fs10,(a0+)
+ fmov fs11,(a0+)
+ fmov fs12,(a0+)
+ fmov fs13,(a0+)
+ fmov fs14,(a0+)
+ fmov fs15,(a0+)
+ fmov fs16,(a0+)
+ fmov fs17,(a0+)
+ fmov fs18,(a0+)
+ fmov fs19,(a0+)
+ fmov fs20,(a0+)
+ fmov fs21,(a0+)
+ fmov fs22,(a0+)
+ fmov fs23,(a0+)
+ fmov fs24,(a0+)
+ fmov fs25,(a0+)
+ fmov fs26,(a0+)
+ fmov fs27,(a0+)
+ fmov fs28,(a0+)
+ fmov fs29,(a0+)
+ fmov fs30,(a0+)
+ fmov fs31,(a0+)
+ fmov fpcr,d0
+ mov d0,(a0)
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ nop
+ nop
+#endif
+
+ mov d1,epsw
+ ret [],0
+
+ .size fpu_save,.-fpu_save
+
+###############################################################################
+#
+# void fpu_restore(struct fpu_state_struct *)
+# - restore the fpu state
+# - note that an FPU Operational exception might occur during this process
+#
+###############################################################################
+ .globl fpu_restore
+ .type fpu_restore,@function
+fpu_restore:
+ mov epsw,d1
+ or EPSW_FE,epsw /* enable the FPU so we can access it */
+
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ nop
+ nop
+#endif
+ mov d0,a0
+ fmov (a0+),fs0
+ fmov (a0+),fs1
+ fmov (a0+),fs2
+ fmov (a0+),fs3
+ fmov (a0+),fs4
+ fmov (a0+),fs5
+ fmov (a0+),fs6
+ fmov (a0+),fs7
+ fmov (a0+),fs8
+ fmov (a0+),fs9
+ fmov (a0+),fs10
+ fmov (a0+),fs11
+ fmov (a0+),fs12
+ fmov (a0+),fs13
+ fmov (a0+),fs14
+ fmov (a0+),fs15
+ fmov (a0+),fs16
+ fmov (a0+),fs17
+ fmov (a0+),fs18
+ fmov (a0+),fs19
+ fmov (a0+),fs20
+ fmov (a0+),fs21
+ fmov (a0+),fs22
+ fmov (a0+),fs23
+ fmov (a0+),fs24
+ fmov (a0+),fs25
+ fmov (a0+),fs26
+ fmov (a0+),fs27
+ fmov (a0+),fs28
+ fmov (a0+),fs29
+ fmov (a0+),fs30
+ fmov (a0+),fs31
+ mov (a0),d0
+ fmov d0,fpcr
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ nop
+ nop
+ nop
+#endif
+
+ mov d1,epsw
+ ret [],0
+
+ .size fpu_restore,.-fpu_restore
--- /dev/null
+/* MN10300 FPU management
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <asm/uaccess.h>
+#include <asm/fpu.h>
+#include <asm/elf.h>
+#include <asm/exceptions.h>
+
+struct task_struct *fpu_state_owner;
+
+/*
+ * handle an exception due to the FPU being disabled
+ */
+asmlinkage void fpu_disabled(struct pt_regs *regs, enum exception_code code)
+{
+ struct task_struct *tsk = current;
+
+ if (!user_mode(regs))
+ die_if_no_fixup("An FPU Disabled exception happened in"
+ " kernel space\n",
+ regs, code);
+
+#ifdef CONFIG_FPU
+ preempt_disable();
+
+ /* transfer the last process's FPU state to memory */
+ if (fpu_state_owner) {
+ fpu_save(&fpu_state_owner->thread.fpu_state);
+ fpu_state_owner->thread.uregs->epsw &= ~EPSW_FE;
+ }
+
+ /* the current process now owns the FPU state */
+ fpu_state_owner = tsk;
+ regs->epsw |= EPSW_FE;
+
+ /* load the FPU with the current process's FPU state or invent a new
+ * clean one if the process doesn't have one */
+ if (is_using_fpu(tsk)) {
+ fpu_restore(&tsk->thread.fpu_state);
+ } else {
+ fpu_init_state();
+ set_using_fpu(tsk);
+ }
+
+ preempt_enable();
+#else
+ {
+ siginfo_t info;
+
+ info.si_signo = SIGFPE;
+ info.si_errno = 0;
+ info.si_addr = (void *) tsk->thread.uregs->pc;
+ info.si_code = FPE_FLTINV;
+
+ force_sig_info(SIGFPE, &info, tsk);
+ }
+#endif /* CONFIG_FPU */
+}
+
+/*
+ * handle an FPU operational exception
+ * - there's a possibility that if the FPU is asynchronous, the signal might
+ * be meant for a process other than the current one
+ */
+asmlinkage void fpu_exception(struct pt_regs *regs, enum exception_code code)
+{
+ struct task_struct *tsk = fpu_state_owner;
+ siginfo_t info;
+
+ if (!user_mode(regs))
+ die_if_no_fixup("An FPU Operation exception happened in"
+ " kernel space\n",
+ regs, code);
+
+ if (!tsk)
+ die_if_no_fixup("An FPU Operation exception happened,"
+ " but the FPU is not in use",
+ regs, code);
+
+ info.si_signo = SIGFPE;
+ info.si_errno = 0;
+ info.si_addr = (void *) tsk->thread.uregs->pc;
+ info.si_code = FPE_FLTINV;
+
+#ifdef CONFIG_FPU
+ {
+ u32 fpcr;
+
+ /* get FPCR (we need to enable the FPU whilst we do this) */
+ asm volatile(" or %1,epsw \n"
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ " nop \n"
+ " nop \n"
+ " nop \n"
+#endif
+ " fmov fpcr,%0 \n"
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ " nop \n"
+ " nop \n"
+ " nop \n"
+#endif
+ " and %2,epsw \n"
+ : "=&d"(fpcr)
+ : "i"(EPSW_FE), "i"(~EPSW_FE)
+ );
+
+ if (fpcr & FPCR_EC_Z)
+ info.si_code = FPE_FLTDIV;
+ else if (fpcr & FPCR_EC_O)
+ info.si_code = FPE_FLTOVF;
+ else if (fpcr & FPCR_EC_U)
+ info.si_code = FPE_FLTUND;
+ else if (fpcr & FPCR_EC_I)
+ info.si_code = FPE_FLTRES;
+ }
+#endif
+
+ force_sig_info(SIGFPE, &info, tsk);
+}
+
+/*
+ * save the FPU state to a signal context
+ */
+int fpu_setup_sigcontext(struct fpucontext *fpucontext)
+{
+#ifdef CONFIG_FPU
+ struct task_struct *tsk = current;
+
+ if (!is_using_fpu(tsk))
+ return 0;
+
+ /* transfer the current FPU state to memory and cause fpu_init() to be
+ * triggered by the next attempted FPU operation by the current
+ * process.
+ */
+ preempt_disable();
+
+ if (fpu_state_owner == tsk) {
+ fpu_save(&tsk->thread.fpu_state);
+ fpu_state_owner->thread.uregs->epsw &= ~EPSW_FE;
+ fpu_state_owner = NULL;
+ }
+
+ preempt_enable();
+
+ /* we no longer have a valid current FPU state */
+ clear_using_fpu(tsk);
+
+ /* transfer the saved FPU state onto the userspace stack */
+ if (copy_to_user(fpucontext,
+ &tsk->thread.fpu_state,
+ min(sizeof(struct fpu_state_struct),
+ sizeof(struct fpucontext))))
+ return -1;
+
+ return 1;
+#else
+ return 0;
+#endif
+}
+
+/*
+ * kill a process's FPU state during restoration after signal handling
+ */
+void fpu_kill_state(struct task_struct *tsk)
+{
+#ifdef CONFIG_FPU
+ /* disown anything left in the FPU */
+ preempt_disable();
+
+ if (fpu_state_owner == tsk) {
+ fpu_state_owner->thread.uregs->epsw &= ~EPSW_FE;
+ fpu_state_owner = NULL;
+ }
+
+ preempt_enable();
+#endif
+ /* we no longer have a valid current FPU state */
+ clear_using_fpu(tsk);
+}
+
+/*
+ * restore the FPU state from a signal context
+ */
+int fpu_restore_sigcontext(struct fpucontext *fpucontext)
+{
+ struct task_struct *tsk = current;
+ int ret;
+
+ /* load up the old FPU state */
+ ret = copy_from_user(&tsk->thread.fpu_state,
+ fpucontext,
+ min(sizeof(struct fpu_state_struct),
+ sizeof(struct fpucontext)));
+ if (!ret)
+ set_using_fpu(tsk);
+
+ return ret;
+}
+
+/*
+ * fill in the FPU structure for a core dump
+ */
+int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpreg)
+{
+ struct task_struct *tsk = current;
+ int fpvalid;
+
+ fpvalid = is_using_fpu(tsk);
+ if (fpvalid) {
+ unlazy_fpu(tsk);
+ memcpy(fpreg, &tsk->thread.fpu_state, sizeof(*fpreg));
+ }
+
+ return fpvalid;
+}
--- /dev/null
+###############################################################################
+#
+# MN10300 Low-level cache purging routines for gdbstub
+#
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Written by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+###############################################################################
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/smp.h>
+#include <asm/cache.h>
+#include <asm/cpu-regs.h>
+#include <asm/exceptions.h>
+#include <asm/frame.inc>
+#include <asm/serial-regs.h>
+
+ .text
+
+###############################################################################
+#
+# GDB stub cache purge
+#
+###############################################################################
+ .type gdbstub_purge_cache,@function
+ENTRY(gdbstub_purge_cache)
+ #######################################################################
+ # read the addresses tagged in the cache's tag RAM and attempt to flush
+ # those addresses specifically
+ # - we rely on the hardware to filter out invalid tag entry addresses
+ mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address
+ mov DCACHE_PURGE(0,0),a1 # dcache purge request address
+ mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of entries
+
+mn10300_dcache_flush_loop:
+ mov (a0),d0
+ and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0
+ or L1_CACHE_TAG_VALID,d0 # retain valid entries in the
+ # cache
+ mov d0,(a1) # conditional purge
+
+mn10300_dcache_flush_skip:
+ add L1_CACHE_BYTES,a0
+ add L1_CACHE_BYTES,a1
+ add -1,d1
+ bne mn10300_dcache_flush_loop
+
+;; # unconditionally flush and invalidate the dcache
+;; mov DCACHE_PURGE(0,0),a1 # dcache purge request address
+;; mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of
+;; # entries
+;;
+;; gdbstub_purge_cache__dcache_loop:
+;; mov (a1),d0 # unconditional purge
+;;
+;; add L1_CACHE_BYTES,a1
+;; add -1,d1
+;; bne gdbstub_purge_cache__dcache_loop
+
+ #######################################################################
+ # now invalidate the icache
+ mov CHCTR,a0
+ movhu (a0),a1
+
+ mov epsw,d1
+ and ~EPSW_IE,epsw
+ nop
+ nop
+
+ # disable the icache
+ and ~CHCTR_ICEN,d0
+ movhu d0,(a0)
+
+ # and wait for it to calm down
+ setlb
+ movhu (a0),d0
+ btst CHCTR_ICBUSY,d0
+ lne
+
+ # invalidate
+ or CHCTR_ICINV,d0
+ movhu d0,(a0)
+
+ # wait for the cache to finish
+ mov CHCTR,a0
+ setlb
+ movhu (a0),d0
+ btst CHCTR_ICBUSY,d0
+ lne
+
+ # and reenable it
+ movhu a1,(a0)
+ movhu (a0),d0 # read back to flush
+ # (SIGILLs all over without this)
+
+ mov d1,epsw
+
+ ret [],0
+
+ .size gdbstub_purge_cache,.-gdbstub_purge_cache
--- /dev/null
+###############################################################################
+#
+# 16550 serial Rx interrupt handler for gdbstub I/O
+#
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Written by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+###############################################################################
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/smp.h>
+#include <asm/cpu-regs.h>
+#include <asm/thread_info.h>
+#include <asm/frame.inc>
+#include <asm/intctl-regs.h>
+#include <asm/unit/serial.h>
+
+ .text
+
+###############################################################################
+#
+# GDB stub serial receive interrupt entry point
+# - intended to run at interrupt priority 0
+#
+###############################################################################
+ .globl gdbstub_io_rx_handler
+ .type gdbstub_io_rx_handler,@function
+gdbstub_io_rx_handler:
+ movm [d2,d3,a2,a3],(sp)
+
+#if 1
+ movbu (GDBPORT_SERIAL_IIR),d2
+#endif
+
+ mov (gdbstub_rx_inp),a3
+gdbstub_io_rx_more:
+ mov a3,a2
+ add 2,a3
+ and 0x00000fff,a3
+ mov (gdbstub_rx_outp),d3
+ cmp a3,d3
+ beq gdbstub_io_rx_overflow
+
+ movbu (GDBPORT_SERIAL_LSR),d3
+ btst UART_LSR_DR,d3
+ beq gdbstub_io_rx_done
+ movbu (GDBPORT_SERIAL_RX),d2
+ movbu d3,(gdbstub_rx_buffer+1,a2)
+ movbu d2,(gdbstub_rx_buffer,a2)
+ mov a3,(gdbstub_rx_inp)
+ bra gdbstub_io_rx_more
+
+gdbstub_io_rx_done:
+ mov GxICR_DETECT,d2
+ movbu d2,(XIRQxICR(GDBPORT_SERIAL_IRQ)) # ACK the interrupt
+ movhu (XIRQxICR(GDBPORT_SERIAL_IRQ)),d2 # flush
+ movm (sp),[d2,d3,a2,a3]
+ bset 0x01,(gdbstub_busy)
+ beq gdbstub_io_rx_enter
+ rti
+
+gdbstub_io_rx_overflow:
+ bset 0x01,(gdbstub_rx_overflow)
+ bra gdbstub_io_rx_done
+
+gdbstub_io_rx_enter:
+ or EPSW_IE|EPSW_IM_1,epsw
+ add -4,sp
+ SAVE_ALL
+
+ mov 0xffffffff,d0
+ mov d0,(REG_ORIG_D0,fp)
+ mov 0x280,d1
+
+ mov fp,d0
+ call gdbstub_rx_irq[],0 # gdbstub_rx_irq(regs,excep)
+
+ and ~EPSW_IE,epsw
+ bclr 0x01,(gdbstub_busy)
+
+ .globl gdbstub_return
+gdbstub_return:
+ RESTORE_ALL
+
+ .size gdbstub_io_rx_handler,.-gdbstub_io_rx_handler
--- /dev/null
+/* 16550 serial driver for gdbstub I/O
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/nmi.h>
+
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/gdb-stub.h>
+#include <asm/exceptions.h>
+#include <asm/serial-regs.h>
+#include <asm/unit/serial.h>
+
+/*
+ * initialise the GDB stub
+ */
+void gdbstub_io_init(void)
+{
+ u16 tmp;
+
+ /* set up the serial port */
+ GDBPORT_SERIAL_LCR = UART_LCR_WLEN8; /* 1N8 */
+ GDBPORT_SERIAL_FCR = (UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
+ UART_FCR_CLEAR_XMIT);
+
+ FLOWCTL_CLEAR(DTR);
+ FLOWCTL_SET(RTS);
+
+ gdbstub_io_set_baud(115200);
+
+ /* we want to get serial receive interrupts */
+ XIRQxICR(GDBPORT_SERIAL_IRQ) = 0;
+ tmp = XIRQxICR(GDBPORT_SERIAL_IRQ);
+
+ IVAR0 = EXCEP_IRQ_LEVEL0;
+ set_intr_stub(EXCEP_IRQ_LEVEL0, gdbstub_io_rx_handler);
+
+ XIRQxICR(GDBPORT_SERIAL_IRQ) &= ~GxICR_REQUEST;
+ XIRQxICR(GDBPORT_SERIAL_IRQ) = GxICR_ENABLE | GxICR_LEVEL_0;
+ tmp = XIRQxICR(GDBPORT_SERIAL_IRQ);
+
+ GDBPORT_SERIAL_IER = UART_IER_RDI | UART_IER_RLSI;
+
+ /* permit level 0 IRQs to take place */
+ asm volatile(
+ " and %0,epsw \n"
+ " or %1,epsw \n"
+ :
+ : "i"(~EPSW_IM), "i"(EPSW_IE | EPSW_IM_1)
+ );
+}
+
+/*
+ * set up the GDB stub serial port baud rate timers
+ */
+void gdbstub_io_set_baud(unsigned baud)
+{
+ unsigned value;
+ u8 lcr;
+
+ value = 18432000 / 16 / baud;
+
+ lcr = GDBPORT_SERIAL_LCR;
+ GDBPORT_SERIAL_LCR |= UART_LCR_DLAB;
+ GDBPORT_SERIAL_DLL = value & 0xff;
+ GDBPORT_SERIAL_DLM = (value >> 8) & 0xff;
+ GDBPORT_SERIAL_LCR = lcr;
+}
+
+/*
+ * wait for a character to come from the debugger
+ */
+int gdbstub_io_rx_char(unsigned char *_ch, int nonblock)
+{
+ unsigned ix;
+ u8 ch, st;
+
+ *_ch = 0xff;
+
+ if (gdbstub_rx_unget) {
+ *_ch = gdbstub_rx_unget;
+ gdbstub_rx_unget = 0;
+ return 0;
+ }
+
+ try_again:
+ /* pull chars out of the buffer */
+ ix = gdbstub_rx_outp;
+ if (ix == gdbstub_rx_inp) {
+ if (nonblock)
+ return -EAGAIN;
+#ifdef CONFIG_MN10300_WD_TIMER
+ watchdog_alert_counter = 0;
+#endif /* CONFIG_MN10300_WD_TIMER */
+ goto try_again;
+ }
+
+ ch = gdbstub_rx_buffer[ix++];
+ st = gdbstub_rx_buffer[ix++];
+ gdbstub_rx_outp = ix & 0x00000fff;
+
+ if (st & UART_LSR_BI) {
+ gdbstub_proto("### GDB Rx Break Detected ###\n");
+ return -EINTR;
+ } else if (st & (UART_LSR_FE | UART_LSR_OE | UART_LSR_PE)) {
+ gdbstub_proto("### GDB Rx Error (st=%02x) ###\n", st);
+ return -EIO;
+ } else {
+ gdbstub_proto("### GDB Rx %02x (st=%02x) ###\n", ch, st);
+ *_ch = ch & 0x7f;
+ return 0;
+ }
+}
+
+/*
+ * send a character to the debugger
+ */
+void gdbstub_io_tx_char(unsigned char ch)
+{
+ FLOWCTL_SET(DTR);
+ LSR_WAIT_FOR(THRE);
+ /* FLOWCTL_WAIT_FOR(CTS); */
+
+ if (ch == 0x0a) {
+ GDBPORT_SERIAL_TX = 0x0d;
+ LSR_WAIT_FOR(THRE);
+ /* FLOWCTL_WAIT_FOR(CTS); */
+ }
+ GDBPORT_SERIAL_TX = ch;
+
+ FLOWCTL_CLEAR(DTR);
+}
+
+/*
+ * send a character to the debugger
+ */
+void gdbstub_io_tx_flush(void)
+{
+ LSR_WAIT_FOR(TEMT);
+ LSR_WAIT_FOR(THRE);
+ FLOWCTL_CLEAR(DTR);
+}
--- /dev/null
+###############################################################################
+#
+# MN10300 On-chip serial Rx interrupt handler for GDB stub I/O
+#
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Written by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+###############################################################################
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/smp.h>
+#include <asm/thread_info.h>
+#include <asm/cpu-regs.h>
+#include <asm/frame.inc>
+#include <asm/intctl-regs.h>
+#include <asm/unit/serial.h>
+#include "mn10300-serial.h"
+
+ .text
+
+###############################################################################
+#
+# GDB stub serial receive interrupt entry point
+# - intended to run at interrupt priority 0
+#
+###############################################################################
+ .globl gdbstub_io_rx_handler
+ .type gdbstub_io_rx_handler,@function
+gdbstub_io_rx_handler:
+ movm [d2,d3,a2,a3],(sp)
+
+ mov (gdbstub_rx_inp),a3
+gdbstub_io_rx_more:
+ mov a3,a2
+ add 2,a3
+ and PAGE_SIZE_asm-1,a3
+ mov (gdbstub_rx_outp),d3
+ cmp a3,d3
+ beq gdbstub_io_rx_overflow
+
+ movbu (SCgSTR),d3
+ btst SC01STR_RBF,d3
+ beq gdbstub_io_rx_done
+ movbu (SCgRXB),d2
+ movbu d3,(gdbstub_rx_buffer+1,a2)
+ movbu d2,(gdbstub_rx_buffer,a2)
+ mov a3,(gdbstub_rx_inp)
+ bra gdbstub_io_rx_more
+
+gdbstub_io_rx_done:
+ mov GxICR_DETECT,d2
+ movbu d2,(GxICR(SCgRXIRQ)) # ACK the interrupt
+ movhu (GxICR(SCgRXIRQ)),d2 # flush
+
+ movm (sp),[d2,d3,a2,a3]
+ bset 0x01,(gdbstub_busy)
+ beq gdbstub_io_rx_enter
+ rti
+
+gdbstub_io_rx_overflow:
+ bset 0x01,(gdbstub_rx_overflow)
+ bra gdbstub_io_rx_done
+
+###############################################################################
+#
+# debugging interrupt - enter the GDB stub proper
+#
+###############################################################################
+gdbstub_io_rx_enter:
+ or EPSW_IE|EPSW_IM_1,epsw
+ add -4,sp
+ SAVE_ALL
+
+ mov 0xffffffff,d0
+ mov d0,(REG_ORIG_D0,fp)
+ mov 0x280,d1
+
+ mov fp,d0
+ call gdbstub_rx_irq[],0 # gdbstub_io_rx_irq(regs,excep)
+
+ and ~EPSW_IE,epsw
+ bclr 0x01,(gdbstub_busy)
+
+ .globl gdbstub_return
+gdbstub_return:
+ RESTORE_ALL
+
+ .size gdbstub_io_rx_handler,.-gdbstub_io_rx_handler
--- /dev/null
+/* MN10300 On-chip serial driver for gdbstub I/O
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/tty.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/gdb-stub.h>
+#include <asm/exceptions.h>
+#include <asm/unit/clock.h>
+#include "mn10300-serial.h"
+
+#if defined(CONFIG_GDBSTUB_ON_TTYSM0)
+struct mn10300_serial_port *const gdbstub_port = &mn10300_serial_port_sif0;
+#elif defined(CONFIG_GDBSTUB_ON_TTYSM1)
+struct mn10300_serial_port *const gdbstub_port = &mn10300_serial_port_sif1;
+#else
+struct mn10300_serial_port *const gdbstub_port = &mn10300_serial_port_sif2;
+#endif
+
+
+/*
+ * initialise the GDB stub I/O routines
+ */
+void __init gdbstub_io_init(void)
+{
+ uint16_t scxctr;
+ int tmp;
+
+ switch (gdbstub_port->clock_src) {
+ case MNSCx_CLOCK_SRC_IOCLK:
+ gdbstub_port->ioclk = MN10300_IOCLK;
+ break;
+
+#ifdef MN10300_IOBCLK
+ case MNSCx_CLOCK_SRC_IOBCLK:
+ gdbstub_port->ioclk = MN10300_IOBCLK;
+ break;
+#endif
+ default:
+ BUG();
+ }
+
+ /* set up the serial port */
+ gdbstub_io_set_baud(115200);
+
+ /* we want to get serial receive interrupts */
+ set_intr_level(gdbstub_port->rx_irq, GxICR_LEVEL_0);
+ set_intr_level(gdbstub_port->tx_irq, GxICR_LEVEL_0);
+ set_intr_stub(EXCEP_IRQ_LEVEL0, gdbstub_io_rx_handler);
+
+ *gdbstub_port->rx_icr |= GxICR_ENABLE;
+ tmp = *gdbstub_port->rx_icr;
+
+ /* enable the device */
+ scxctr = SC01CTR_CLN_8BIT; /* 1N8 */
+ switch (gdbstub_port->div_timer) {
+ case MNSCx_DIV_TIMER_16BIT:
+ scxctr |= SC0CTR_CK_TM8UFLOW_8; /* == SC1CTR_CK_TM9UFLOW_8
+ == SC2CTR_CK_TM10UFLOW_8 */
+ break;
+
+ case MNSCx_DIV_TIMER_8BIT:
+ scxctr |= SC0CTR_CK_TM2UFLOW_8;
+ break;
+ }
+
+ scxctr |= SC01CTR_TXE | SC01CTR_RXE;
+
+ *gdbstub_port->_control = scxctr;
+ tmp = *gdbstub_port->_control;
+
+ /* permit level 0 IRQs only */
+ asm volatile(
+ " and %0,epsw \n"
+ " or %1,epsw \n"
+ :
+ : "i"(~EPSW_IM), "i"(EPSW_IE|EPSW_IM_1)
+ );
+}
+
+/*
+ * set up the GDB stub serial port baud rate timers
+ */
+void gdbstub_io_set_baud(unsigned baud)
+{
+ const unsigned bits = 10; /* 1 [start] + 8 [data] + 0 [parity] +
+ * 1 [stop] */
+ unsigned long ioclk = gdbstub_port->ioclk;
+ unsigned xdiv, tmp;
+ uint16_t tmxbr;
+ uint8_t tmxmd;
+
+ if (!baud) {
+ baud = 9600;
+ } else if (baud == 134) {
+ baud = 269; /* 134 is really 134.5 */
+ xdiv = 2;
+ }
+
+try_alternative:
+ xdiv = 1;
+
+ switch (gdbstub_port->div_timer) {
+ case MNSCx_DIV_TIMER_16BIT:
+ tmxmd = TM8MD_SRC_IOCLK;
+ tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 65535)
+ goto timer_okay;
+
+ tmxmd = TM8MD_SRC_IOCLK_8;
+ tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 65535)
+ goto timer_okay;
+
+ tmxmd = TM8MD_SRC_IOCLK_32;
+ tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 65535)
+ goto timer_okay;
+
+ break;
+
+ case MNSCx_DIV_TIMER_8BIT:
+ tmxmd = TM2MD_SRC_IOCLK;
+ tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 255)
+ goto timer_okay;
+
+ tmxmd = TM2MD_SRC_IOCLK_8;
+ tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 255)
+ goto timer_okay;
+
+ tmxmd = TM2MD_SRC_IOCLK_32;
+ tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 255)
+ goto timer_okay;
+ break;
+ }
+
+ /* as a last resort, if the quotient is zero, default to 9600 bps */
+ baud = 9600;
+ goto try_alternative;
+
+timer_okay:
+ gdbstub_port->uart.timeout = (2 * bits * HZ) / baud;
+ gdbstub_port->uart.timeout += HZ / 50;
+
+ /* set the timer to produce the required baud rate */
+ switch (gdbstub_port->div_timer) {
+ case MNSCx_DIV_TIMER_16BIT:
+ *gdbstub_port->_tmxmd = 0;
+ *gdbstub_port->_tmxbr = tmxbr;
+ *gdbstub_port->_tmxmd = TM8MD_INIT_COUNTER;
+ *gdbstub_port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
+ break;
+
+ case MNSCx_DIV_TIMER_8BIT:
+ *gdbstub_port->_tmxmd = 0;
+ *(volatile u8 *) gdbstub_port->_tmxbr = (u8)tmxbr;
+ *gdbstub_port->_tmxmd = TM2MD_INIT_COUNTER;
+ *gdbstub_port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
+ break;
+ }
+}
+
+/*
+ * wait for a character to come from the debugger
+ */
+int gdbstub_io_rx_char(unsigned char *_ch, int nonblock)
+{
+ unsigned ix;
+ u8 ch, st;
+
+ *_ch = 0xff;
+
+ if (gdbstub_rx_unget) {
+ *_ch = gdbstub_rx_unget;
+ gdbstub_rx_unget = 0;
+ return 0;
+ }
+
+try_again:
+ /* pull chars out of the buffer */
+ ix = gdbstub_rx_outp;
+ if (ix == gdbstub_rx_inp) {
+ if (nonblock)
+ return -EAGAIN;
+#ifdef CONFIG_MN10300_WD_TIMER
+ watchdog_alert_counter = 0;
+#endif /* CONFIG_MN10300_WD_TIMER */
+ goto try_again;
+ }
+
+ ch = gdbstub_rx_buffer[ix++];
+ st = gdbstub_rx_buffer[ix++];
+ gdbstub_rx_outp = ix & (PAGE_SIZE - 1);
+
+ st &= SC01STR_RXF | SC01STR_RBF | SC01STR_FEF | SC01STR_PEF |
+ SC01STR_OEF;
+
+ /* deal with what we've got
+ * - note that the UART doesn't do BREAK-detection for us
+ */
+ if (st & SC01STR_FEF && ch == 0) {
+ switch (gdbstub_port->rx_brk) {
+ case 0: gdbstub_port->rx_brk = 1; goto try_again;
+ case 1: gdbstub_port->rx_brk = 2; goto try_again;
+ case 2:
+ gdbstub_port->rx_brk = 3;
+ gdbstub_proto("### GDB MNSERIAL Rx Break Detected"
+ " ###\n");
+ return -EINTR;
+ default:
+ goto try_again;
+ }
+ } else if (st & SC01STR_FEF) {
+ if (gdbstub_port->rx_brk)
+ goto try_again;
+
+ gdbstub_proto("### GDB MNSERIAL Framing Error ###\n");
+ return -EIO;
+ } else if (st & SC01STR_OEF) {
+ if (gdbstub_port->rx_brk)
+ goto try_again;
+
+ gdbstub_proto("### GDB MNSERIAL Overrun Error ###\n");
+ return -EIO;
+ } else if (st & SC01STR_PEF) {
+ if (gdbstub_port->rx_brk)
+ goto try_again;
+
+ gdbstub_proto("### GDB MNSERIAL Parity Error ###\n");
+ return -EIO;
+ } else {
+ /* look for the tail-end char on a break run */
+ if (gdbstub_port->rx_brk == 3) {
+ switch (ch) {
+ case 0xFF:
+ case 0xFE:
+ case 0xFC:
+ case 0xF8:
+ case 0xF0:
+ case 0xE0:
+ case 0xC0:
+ case 0x80:
+ case 0x00:
+ gdbstub_port->rx_brk = 0;
+ goto try_again;
+ default:
+ break;
+ }
+ }
+
+ gdbstub_port->rx_brk = 0;
+ gdbstub_io("### GDB Rx %02x (st=%02x) ###\n", ch, st);
+ *_ch = ch & 0x7f;
+ return 0;
+ }
+}
+
+/*
+ * send a character to the debugger
+ */
+void gdbstub_io_tx_char(unsigned char ch)
+{
+ while (*gdbstub_port->_status & SC01STR_TBF)
+ continue;
+
+ if (ch == 0x0a) {
+ *(u8 *) gdbstub_port->_txb = 0x0d;
+ while (*gdbstub_port->_status & SC01STR_TBF)
+ continue;
+ }
+
+ *(u8 *) gdbstub_port->_txb = ch;
+}
+
+/*
+ * flush the transmission buffers
+ */
+void gdbstub_io_tx_flush(void)
+{
+ while (*gdbstub_port->_status & (SC01STR_TBF | SC01STR_TXF))
+ continue;
+}
--- /dev/null
+###############################################################################
+#
+# MN10300 Low-level gdbstub routines
+#
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Written by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+###############################################################################
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/smp.h>
+#include <asm/cache.h>
+#include <asm/cpu-regs.h>
+#include <asm/exceptions.h>
+#include <asm/frame.inc>
+#include <asm/serial-regs.h>
+
+ .text
+
+###############################################################################
+#
+# GDB stub read memory with guard
+# - D0 holds the memory address to read
+# - D1 holds the address to store the byte into
+#
+###############################################################################
+ .globl gdbstub_read_byte_guard
+ .globl gdbstub_read_byte_cont
+ENTRY(gdbstub_read_byte)
+ mov d0,a0
+ mov d1,a1
+ clr d0
+gdbstub_read_byte_guard:
+ movbu (a0),d1
+gdbstub_read_byte_cont:
+ movbu d1,(a1)
+ ret [],0
+
+ .globl gdbstub_read_word_guard
+ .globl gdbstub_read_word_cont
+ENTRY(gdbstub_read_word)
+ mov d0,a0
+ mov d1,a1
+ clr d0
+gdbstub_read_word_guard:
+ movhu (a0),d1
+gdbstub_read_word_cont:
+ movhu d1,(a1)
+ ret [],0
+
+ .globl gdbstub_read_dword_guard
+ .globl gdbstub_read_dword_cont
+ENTRY(gdbstub_read_dword)
+ mov d0,a0
+ mov d1,a1
+ clr d0
+gdbstub_read_dword_guard:
+ mov (a0),d1
+gdbstub_read_dword_cont:
+ mov d1,(a1)
+ ret [],0
+
+###############################################################################
+#
+# GDB stub write memory with guard
+# - D0 holds the byte to store
+# - D1 holds the memory address to write
+#
+###############################################################################
+ .globl gdbstub_write_byte_guard
+ .globl gdbstub_write_byte_cont
+ENTRY(gdbstub_write_byte)
+ mov d0,a0
+ mov d1,a1
+ clr d0
+gdbstub_write_byte_guard:
+ movbu a0,(a1)
+gdbstub_write_byte_cont:
+ ret [],0
+
+ .globl gdbstub_write_word_guard
+ .globl gdbstub_write_word_cont
+ENTRY(gdbstub_write_word)
+ mov d0,a0
+ mov d1,a1
+ clr d0
+gdbstub_write_word_guard:
+ movhu a0,(a1)
+gdbstub_write_word_cont:
+ ret [],0
+
+ .globl gdbstub_write_dword_guard
+ .globl gdbstub_write_dword_cont
+ENTRY(gdbstub_write_dword)
+ mov d0,a0
+ mov d1,a1
+ clr d0
+gdbstub_write_dword_guard:
+ mov a0,(a1)
+gdbstub_write_dword_cont:
+ ret [],0
+
+###############################################################################
+#
+# GDB stub BUG() trap
+#
+###############################################################################
+ENTRY(__gdbstub_bug_trap)
+ .byte 0xF7,0xF7 # don't use 0xFF as the JTAG unit preempts that
+ ret [],0
--- /dev/null
+/* MN10300 GDB stub
+ *
+ * Originally written by Glenn Engel, Lake Stevens Instrument Division
+ *
+ * Contributed by HP Systems
+ *
+ * Modified for SPARC by Stu Grossman, Cygnus Support.
+ *
+ * Modified for Linux/MIPS (and MIPS in general) by Andreas Busse
+ * Send complaints, suggestions etc. to <andy@waldorf-gmbh.de>
+ *
+ * Copyright (C) 1995 Andreas Busse
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Modified for Linux/mn10300 by David Howells <dhowells@redhat.com>
+ */
+
+/*
+ * To enable debugger support, two things need to happen. One, a
+ * call to set_debug_traps() is necessary in order to allow any breakpoints
+ * or error conditions to be properly intercepted and reported to gdb.
+ * Two, a breakpoint needs to be generated to begin communication. This
+ * is most easily accomplished by a call to breakpoint(). Breakpoint()
+ * simulates a breakpoint by executing a BREAK instruction.
+ *
+ *
+ * The following gdb commands are supported:
+ *
+ * command function Return value
+ *
+ * g return the value of the CPU registers hex data or ENN
+ * G set the value of the CPU registers OK or ENN
+ *
+ * mAA..AA,LLLL Read LLLL bytes at address AA..AA hex data or ENN
+ * MAA..AA,LLLL: Write LLLL bytes at address AA.AA OK or ENN
+ *
+ * c Resume at current address SNN ( signal NN)
+ * cAA..AA Continue at address AA..AA SNN
+ *
+ * s Step one instruction SNN
+ * sAA..AA Step one instruction from AA..AA SNN
+ *
+ * k kill
+ *
+ * ? What was the last sigval ? SNN (signal NN)
+ *
+ * bBB..BB Set baud rate to BB..BB OK or BNN, then sets
+ * baud rate
+ *
+ * All commands and responses are sent with a packet which includes a
+ * checksum. A packet consists of
+ *
+ * $<packet info>#<checksum>.
+ *
+ * where
+ * <packet info> :: <characters representing the command or response>
+ * <checksum> :: < two hex digits computed as modulo 256 sum of <packetinfo>>
+ *
+ * When a packet is received, it is first acknowledged with either '+' or '-'.
+ * '+' indicates a successful transfer. '-' indicates a failed transfer.
+ *
+ * Example:
+ *
+ * Host: Reply:
+ * $m0,10#2a +$00010203040506070809101112131415#42
+ *
+ *
+ * ==============
+ * MORE EXAMPLES:
+ * ==============
+ *
+ * For reference -- the following are the steps that one
+ * company took (RidgeRun Inc) to get remote gdb debugging
+ * going. In this scenario the host machine was a PC and the
+ * target platform was a Galileo EVB64120A MIPS evaluation
+ * board.
+ *
+ * Step 1:
+ * First download gdb-5.0.tar.gz from the internet.
+ * and then build/install the package.
+ *
+ * Example:
+ * $ tar zxf gdb-5.0.tar.gz
+ * $ cd gdb-5.0
+ * $ ./configure --target=am33_2.0-linux-gnu
+ * $ make
+ * $ install
+ * am33_2.0-linux-gnu-gdb
+ *
+ * Step 2:
+ * Configure linux for remote debugging and build it.
+ *
+ * Example:
+ * $ cd ~/linux
+ * $ make menuconfig <go to "Kernel Hacking" and turn on remote debugging>
+ * $ make dep; make vmlinux
+ *
+ * Step 3:
+ * Download the kernel to the remote target and start
+ * the kernel running. It will promptly halt and wait
+ * for the host gdb session to connect. It does this
+ * since the "Kernel Hacking" option has defined
+ * CONFIG_REMOTE_DEBUG which in turn enables your calls
+ * to:
+ * set_debug_traps();
+ * breakpoint();
+ *
+ * Step 4:
+ * Start the gdb session on the host.
+ *
+ * Example:
+ * $ am33_2.0-linux-gnu-gdb vmlinux
+ * (gdb) set remotebaud 115200
+ * (gdb) target remote /dev/ttyS1
+ * ...at this point you are connected to
+ * the remote target and can use gdb
+ * in the normal fasion. Setting
+ * breakpoints, single stepping,
+ * printing variables, etc.
+ *
+ */
+
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/bug.h>
+
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/gdb-stub.h>
+#include <asm/exceptions.h>
+#include <asm/cacheflush.h>
+#include <asm/serial-regs.h>
+#include <asm/busctl-regs.h>
+#include <asm/unit/leds.h>
+#include <asm/unit/serial.h>
+
+/* define to use F7F7 rather than FF which is subverted by JTAG debugger */
+#undef GDBSTUB_USE_F7F7_AS_BREAKPOINT
+
+/*
+ * BUFMAX defines the maximum number of characters in inbound/outbound buffers
+ * at least NUMREGBYTES*2 are needed for register packets
+ */
+#define BUFMAX 2048
+
+static const char gdbstub_banner[] =
+ "Linux/MN10300 GDB Stub (c) RedHat 2007\n";
+
+u8 gdbstub_rx_buffer[PAGE_SIZE] __attribute__((aligned(PAGE_SIZE)));
+u32 gdbstub_rx_inp;
+u32 gdbstub_rx_outp;
+u8 gdbstub_busy;
+u8 gdbstub_rx_overflow;
+u8 gdbstub_rx_unget;
+
+static u8 gdbstub_flush_caches;
+static char input_buffer[BUFMAX];
+static char output_buffer[BUFMAX];
+static char trans_buffer[BUFMAX];
+
+static const char hexchars[] = "0123456789abcdef";
+
+struct gdbstub_bkpt {
+ u8 *addr; /* address of breakpoint */
+ u8 len; /* size of breakpoint */
+ u8 origbytes[7]; /* original bytes */
+};
+
+static struct gdbstub_bkpt gdbstub_bkpts[256];
+
+/*
+ * local prototypes
+ */
+static void getpacket(char *buffer);
+static int putpacket(char *buffer);
+static int computeSignal(enum exception_code excep);
+static int hex(unsigned char ch);
+static int hexToInt(char **ptr, int *intValue);
+static unsigned char *mem2hex(const void *mem, char *buf, int count,
+ int may_fault);
+static const char *hex2mem(const char *buf, void *_mem, int count,
+ int may_fault);
+
+/*
+ * Convert ch from a hex digit to an int
+ */
+static int hex(unsigned char ch)
+{
+ if (ch >= 'a' && ch <= 'f')
+ return ch - 'a' + 10;
+ if (ch >= '0' && ch <= '9')
+ return ch - '0';
+ if (ch >= 'A' && ch <= 'F')
+ return ch - 'A' + 10;
+ return -1;
+}
+
+#ifdef CONFIG_GDBSTUB_DEBUGGING
+
+void debug_to_serial(const char *p, int n)
+{
+ __debug_to_serial(p, n);
+ /* gdbstub_console_write(NULL, p, n); */
+}
+
+void gdbstub_printk(const char *fmt, ...)
+{
+ va_list args;
+ int len;
+
+ /* Emit the output into the temporary buffer */
+ va_start(args, fmt);
+ len = vsnprintf(trans_buffer, sizeof(trans_buffer), fmt, args);
+ va_end(args);
+ debug_to_serial(trans_buffer, len);
+}
+
+#endif
+
+static inline char *gdbstub_strcpy(char *dst, const char *src)
+{
+ int loop = 0;
+ while ((dst[loop] = src[loop]))
+ loop++;
+ return dst;
+}
+
+/*
+ * scan for the sequence $<data>#<checksum>
+ */
+static void getpacket(char *buffer)
+{
+ unsigned char checksum;
+ unsigned char xmitcsum;
+ unsigned char ch;
+ int count, i, ret, error;
+
+ for (;;) {
+ /*
+ * wait around for the start character,
+ * ignore all other characters
+ */
+ do {
+ gdbstub_io_rx_char(&ch, 0);
+ } while (ch != '$');
+
+ checksum = 0;
+ xmitcsum = -1;
+ count = 0;
+ error = 0;
+
+ /*
+ * now, read until a # or end of buffer is found
+ */
+ while (count < BUFMAX) {
+ ret = gdbstub_io_rx_char(&ch, 0);
+ if (ret < 0)
+ error = ret;
+
+ if (ch == '#')
+ break;
+ checksum += ch;
+ buffer[count] = ch;
+ count++;
+ }
+
+ if (error == -EIO) {
+ gdbstub_proto("### GDB Rx Error - Skipping packet"
+ " ###\n");
+ gdbstub_proto("### GDB Tx NAK\n");
+ gdbstub_io_tx_char('-');
+ continue;
+ }
+
+ if (count >= BUFMAX || error)
+ continue;
+
+ buffer[count] = 0;
+
+ /* read the checksum */
+ ret = gdbstub_io_rx_char(&ch, 0);
+ if (ret < 0)
+ error = ret;
+ xmitcsum = hex(ch) << 4;
+
+ ret = gdbstub_io_rx_char(&ch, 0);
+ if (ret < 0)
+ error = ret;
+ xmitcsum |= hex(ch);
+
+ if (error) {
+ if (error == -EIO)
+ gdbstub_io("### GDB Rx Error -"
+ " Skipping packet\n");
+ gdbstub_io("### GDB Tx NAK\n");
+ gdbstub_io_tx_char('-');
+ continue;
+ }
+
+ /* check the checksum */
+ if (checksum != xmitcsum) {
+ gdbstub_io("### GDB Tx NAK\n");
+ gdbstub_io_tx_char('-'); /* failed checksum */
+ continue;
+ }
+
+ gdbstub_proto("### GDB Rx '$%s#%02x' ###\n", buffer, checksum);
+ gdbstub_io("### GDB Tx ACK\n");
+ gdbstub_io_tx_char('+'); /* successful transfer */
+
+ /*
+ * if a sequence char is present,
+ * reply the sequence ID
+ */
+ if (buffer[2] == ':') {
+ gdbstub_io_tx_char(buffer[0]);
+ gdbstub_io_tx_char(buffer[1]);
+
+ /*
+ * remove sequence chars from buffer
+ */
+ count = 0;
+ while (buffer[count])
+ count++;
+ for (i = 3; i <= count; i++)
+ buffer[i - 3] = buffer[i];
+ }
+
+ break;
+ }
+}
+
+/*
+ * send the packet in buffer.
+ * - return 0 if successfully ACK'd
+ * - return 1 if abandoned due to new incoming packet
+ */
+static int putpacket(char *buffer)
+{
+ unsigned char checksum;
+ unsigned char ch;
+ int count;
+
+ /*
+ * $<packet info>#<checksum>.
+ */
+ gdbstub_proto("### GDB Tx $'%s'#?? ###\n", buffer);
+
+ do {
+ gdbstub_io_tx_char('$');
+ checksum = 0;
+ count = 0;
+
+ while ((ch = buffer[count]) != 0) {
+ gdbstub_io_tx_char(ch);
+ checksum += ch;
+ count += 1;
+ }
+
+ gdbstub_io_tx_char('#');
+ gdbstub_io_tx_char(hexchars[checksum >> 4]);
+ gdbstub_io_tx_char(hexchars[checksum & 0xf]);
+
+ } while (gdbstub_io_rx_char(&ch, 0),
+ ch == '-' && (gdbstub_io("### GDB Rx NAK\n"), 0),
+ ch != '-' && ch != '+' &&
+ (gdbstub_io("### GDB Rx ??? %02x\n", ch), 0),
+ ch != '+' && ch != '$');
+
+ if (ch == '+') {
+ gdbstub_io("### GDB Rx ACK\n");
+ return 0;
+ }
+
+ gdbstub_io("### GDB Tx Abandoned\n");
+ gdbstub_rx_unget = ch;
+ return 1;
+}
+
+/*
+ * While we find nice hex chars, build an int.
+ * Return number of chars processed.
+ */
+static int hexToInt(char **ptr, int *intValue)
+{
+ int numChars = 0;
+ int hexValue;
+
+ *intValue = 0;
+
+ while (**ptr) {
+ hexValue = hex(**ptr);
+ if (hexValue < 0)
+ break;
+
+ *intValue = (*intValue << 4) | hexValue;
+ numChars++;
+
+ (*ptr)++;
+ }
+
+ return (numChars);
+}
+
+/*
+ * We single-step by setting breakpoints. When an exception
+ * is handled, we need to restore the instructions hoisted
+ * when the breakpoints were set.
+ *
+ * This is where we save the original instructions.
+ */
+static struct gdb_bp_save {
+ u8 *addr;
+ u8 opcode[2];
+} step_bp[2];
+
+static const unsigned char gdbstub_insn_sizes[256] =
+{
+ /* 1 2 3 4 5 6 7 8 9 a b c d e f */
+ 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, /* 0 */
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 1 */
+ 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, /* 2 */
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, /* 3 */
+ 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, /* 4 */
+ 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, /* 5 */
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 6 */
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 7 */
+ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 8 */
+ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 9 */
+ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* a */
+ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* b */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 2, /* c */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* d */
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* e */
+ 0, 2, 2, 2, 2, 2, 2, 4, 0, 3, 0, 4, 0, 6, 7, 1 /* f */
+};
+
+static int __gdbstub_mark_bp(u8 *addr, int ix)
+{
+ if (addr < (u8 *) 0x70000000UL)
+ return 0;
+ /* 70000000-7fffffff: vmalloc area */
+ if (addr < (u8 *) 0x80000000UL)
+ goto okay;
+ if (addr < (u8 *) 0x8c000000UL)
+ return 0;
+ /* 8c000000-93ffffff: SRAM, SDRAM */
+ if (addr < (u8 *) 0x94000000UL)
+ goto okay;
+ return 0;
+
+okay:
+ if (gdbstub_read_byte(addr + 0, &step_bp[ix].opcode[0]) < 0 ||
+ gdbstub_read_byte(addr + 1, &step_bp[ix].opcode[1]) < 0)
+ return 0;
+
+ step_bp[ix].addr = addr;
+ return 1;
+}
+
+static inline void __gdbstub_restore_bp(void)
+{
+#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
+ if (step_bp[0].addr) {
+ gdbstub_write_byte(step_bp[0].opcode[0], step_bp[0].addr + 0);
+ gdbstub_write_byte(step_bp[0].opcode[1], step_bp[0].addr + 1);
+ }
+ if (step_bp[1].addr) {
+ gdbstub_write_byte(step_bp[1].opcode[0], step_bp[1].addr + 0);
+ gdbstub_write_byte(step_bp[1].opcode[1], step_bp[1].addr + 1);
+ }
+#else
+ if (step_bp[0].addr)
+ gdbstub_write_byte(step_bp[0].opcode[0], step_bp[0].addr + 0);
+ if (step_bp[1].addr)
+ gdbstub_write_byte(step_bp[1].opcode[0], step_bp[1].addr + 0);
+#endif
+
+ gdbstub_flush_caches = 1;
+
+ step_bp[0].addr = NULL;
+ step_bp[0].opcode[0] = 0;
+ step_bp[0].opcode[1] = 0;
+ step_bp[1].addr = NULL;
+ step_bp[1].opcode[0] = 0;
+ step_bp[1].opcode[1] = 0;
+}
+
+/*
+ * emulate single stepping by means of breakpoint instructions
+ */
+static int gdbstub_single_step(struct pt_regs *regs)
+{
+ unsigned size;
+ uint32_t x;
+ uint8_t cur, *pc, *sp;
+
+ step_bp[0].addr = NULL;
+ step_bp[0].opcode[0] = 0;
+ step_bp[0].opcode[1] = 0;
+ step_bp[1].addr = NULL;
+ step_bp[1].opcode[0] = 0;
+ step_bp[1].opcode[1] = 0;
+ x = 0;
+
+ pc = (u8 *) regs->pc;
+ sp = (u8 *) (regs + 1);
+ if (gdbstub_read_byte(pc, &cur) < 0)
+ return -EFAULT;
+
+ gdbstub_bkpt("Single Step from %p { %02x }\n", pc, cur);
+
+ gdbstub_flush_caches = 1;
+
+ size = gdbstub_insn_sizes[cur];
+ if (size > 0) {
+ if (!__gdbstub_mark_bp(pc + size, 0))
+ goto fault;
+ } else {
+ switch (cur) {
+ /* Bxx (d8,PC) */
+ case 0xc0:
+ case 0xc1:
+ case 0xc2:
+ case 0xc3:
+ case 0xc4:
+ case 0xc5:
+ case 0xc6:
+ case 0xc7:
+ case 0xc8:
+ case 0xc9:
+ case 0xca:
+ if (gdbstub_read_byte(pc + 1, (u8 *) &x) < 0)
+ goto fault;
+ if (!__gdbstub_mark_bp(pc + 2, 0))
+ goto fault;
+ if ((x < 0 || x > 2) &&
+ !__gdbstub_mark_bp(pc + (s8) x, 1))
+ goto fault;
+ break;
+
+ /* LXX (d8,PC) */
+ case 0xd0:
+ case 0xd1:
+ case 0xd2:
+ case 0xd3:
+ case 0xd4:
+ case 0xd5:
+ case 0xd6:
+ case 0xd7:
+ case 0xd8:
+ case 0xd9:
+ case 0xda:
+ if (!__gdbstub_mark_bp(pc + 1, 0))
+ goto fault;
+ if (regs->pc != regs->lar &&
+ !__gdbstub_mark_bp((u8 *) regs->lar, 1))
+ goto fault;
+ break;
+
+ /* SETLB - loads the next for bytes into the LIR
+ * register */
+ case 0xdb:
+ if (!__gdbstub_mark_bp(pc + 1, 0))
+ goto fault;
+ break;
+
+ /* JMP (d16,PC) or CALL (d16,PC) */
+ case 0xcc:
+ case 0xcd:
+ if (gdbstub_read_byte(pc + 1, ((u8 *) &x) + 0) < 0 ||
+ gdbstub_read_byte(pc + 2, ((u8 *) &x) + 1) < 0)
+ goto fault;
+ if (!__gdbstub_mark_bp(pc + (s16) x, 0))
+ goto fault;
+ break;
+
+ /* JMP (d32,PC) or CALL (d32,PC) */
+ case 0xdc:
+ case 0xdd:
+ if (gdbstub_read_byte(pc + 1, ((u8 *) &x) + 0) < 0 ||
+ gdbstub_read_byte(pc + 2, ((u8 *) &x) + 1) < 0 ||
+ gdbstub_read_byte(pc + 3, ((u8 *) &x) + 2) < 0 ||
+ gdbstub_read_byte(pc + 4, ((u8 *) &x) + 3) < 0)
+ goto fault;
+ if (!__gdbstub_mark_bp(pc + (s32) x, 0))
+ goto fault;
+ break;
+
+ /* RETF */
+ case 0xde:
+ if (!__gdbstub_mark_bp((u8 *) regs->mdr, 0))
+ goto fault;
+ break;
+
+ /* RET */
+ case 0xdf:
+ if (gdbstub_read_byte(pc + 2, (u8 *) &x) < 0)
+ goto fault;
+ sp += (s8)x;
+ if (gdbstub_read_byte(sp + 0, ((u8 *) &x) + 0) < 0 ||
+ gdbstub_read_byte(sp + 1, ((u8 *) &x) + 1) < 0 ||
+ gdbstub_read_byte(sp + 2, ((u8 *) &x) + 2) < 0 ||
+ gdbstub_read_byte(sp + 3, ((u8 *) &x) + 3) < 0)
+ goto fault;
+ if (!__gdbstub_mark_bp((u8 *) x, 0))
+ goto fault;
+ break;
+
+ case 0xf0:
+ if (gdbstub_read_byte(pc + 1, &cur) < 0)
+ goto fault;
+
+ if (cur >= 0xf0 && cur <= 0xf7) {
+ /* JMP (An) / CALLS (An) */
+ switch (cur & 3) {
+ case 0: x = regs->a0; break;
+ case 1: x = regs->a1; break;
+ case 2: x = regs->a2; break;
+ case 3: x = regs->a3; break;
+ }
+ if (!__gdbstub_mark_bp((u8 *) x, 0))
+ goto fault;
+ } else if (cur == 0xfc) {
+ /* RETS */
+ if (gdbstub_read_byte(
+ sp + 0, ((u8 *) &x) + 0) < 0 ||
+ gdbstub_read_byte(
+ sp + 1, ((u8 *) &x) + 1) < 0 ||
+ gdbstub_read_byte(
+ sp + 2, ((u8 *) &x) + 2) < 0 ||
+ gdbstub_read_byte(
+ sp + 3, ((u8 *) &x) + 3) < 0)
+ goto fault;
+ if (!__gdbstub_mark_bp((u8 *) x, 0))
+ goto fault;
+ } else if (cur == 0xfd) {
+ /* RTI */
+ if (gdbstub_read_byte(
+ sp + 4, ((u8 *) &x) + 0) < 0 ||
+ gdbstub_read_byte(
+ sp + 5, ((u8 *) &x) + 1) < 0 ||
+ gdbstub_read_byte(
+ sp + 6, ((u8 *) &x) + 2) < 0 ||
+ gdbstub_read_byte(
+ sp + 7, ((u8 *) &x) + 3) < 0)
+ goto fault;
+ if (!__gdbstub_mark_bp((u8 *) x, 0))
+ goto fault;
+ } else {
+ if (!__gdbstub_mark_bp(pc + 2, 0))
+ goto fault;
+ }
+
+ break;
+
+ /* potential 3-byte conditional branches */
+ case 0xf8:
+ if (gdbstub_read_byte(pc + 1, &cur) < 0)
+ goto fault;
+ if (!__gdbstub_mark_bp(pc + 3, 0))
+ goto fault;
+
+ if (cur >= 0xe8 && cur <= 0xeb) {
+ if (gdbstub_read_byte(
+ pc + 2, ((u8 *) &x) + 0) < 0)
+ goto fault;
+ if ((x < 0 || x > 3) &&
+ !__gdbstub_mark_bp(pc + (s8) x, 1))
+ goto fault;
+ }
+ break;
+
+ case 0xfa:
+ if (gdbstub_read_byte(pc + 1, &cur) < 0)
+ goto fault;
+
+ if (cur == 0xff) {
+ /* CALLS (d16,PC) */
+ if (gdbstub_read_byte(
+ pc + 2, ((u8 *) &x) + 0) < 0 ||
+ gdbstub_read_byte(
+ pc + 3, ((u8 *) &x) + 1) < 0)
+ goto fault;
+ if (!__gdbstub_mark_bp(pc + (s16) x, 0))
+ goto fault;
+ } else {
+ if (!__gdbstub_mark_bp(pc + 4, 0))
+ goto fault;
+ }
+ break;
+
+ case 0xfc:
+ if (gdbstub_read_byte(pc + 1, &cur) < 0)
+ goto fault;
+ if (cur == 0xff) {
+ /* CALLS (d32,PC) */
+ if (gdbstub_read_byte(
+ pc + 2, ((u8 *) &x) + 0) < 0 ||
+ gdbstub_read_byte(
+ pc + 3, ((u8 *) &x) + 1) < 0 ||
+ gdbstub_read_byte(
+ pc + 4, ((u8 *) &x) + 2) < 0 ||
+ gdbstub_read_byte(
+ pc + 5, ((u8 *) &x) + 3) < 0)
+ goto fault;
+ if (!__gdbstub_mark_bp(
+ pc + (s32) x, 0))
+ goto fault;
+ } else {
+ if (!__gdbstub_mark_bp(
+ pc + 6, 0))
+ goto fault;
+ }
+ break;
+
+ }
+ }
+
+ gdbstub_bkpt("Step: %02x at %p; %02x at %p\n",
+ step_bp[0].opcode[0], step_bp[0].addr,
+ step_bp[1].opcode[0], step_bp[1].addr);
+
+ if (step_bp[0].addr) {
+#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
+ if (gdbstub_write_byte(0xF7, step_bp[0].addr + 0) < 0 ||
+ gdbstub_write_byte(0xF7, step_bp[0].addr + 1) < 0)
+ goto fault;
+#else
+ if (gdbstub_write_byte(0xFF, step_bp[0].addr + 0) < 0)
+ goto fault;
+#endif
+ }
+
+ if (step_bp[1].addr) {
+#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
+ if (gdbstub_write_byte(0xF7, step_bp[1].addr + 0) < 0 ||
+ gdbstub_write_byte(0xF7, step_bp[1].addr + 1) < 0)
+ goto fault;
+#else
+ if (gdbstub_write_byte(0xFF, step_bp[1].addr + 0) < 0)
+ goto fault;
+#endif
+ }
+
+ return 0;
+
+ fault:
+ /* uh-oh - silly address alert, try and restore things */
+ __gdbstub_restore_bp();
+ return -EFAULT;
+}
+
+#ifdef CONFIG_GDBSTUB_CONSOLE
+
+void gdbstub_console_write(struct console *con, const char *p, unsigned n)
+{
+ static const char gdbstub_cr[] = { 0x0d };
+ char outbuf[26];
+ int qty;
+ u8 busy;
+
+ busy = gdbstub_busy;
+ gdbstub_busy = 1;
+
+ outbuf[0] = 'O';
+
+ while (n > 0) {
+ qty = 1;
+
+ while (n > 0 && qty < 20) {
+ mem2hex(p, outbuf + qty, 2, 0);
+ qty += 2;
+ if (*p == 0x0a) {
+ mem2hex(gdbstub_cr, outbuf + qty, 2, 0);
+ qty += 2;
+ }
+ p++;
+ n--;
+ }
+
+ outbuf[qty] = 0;
+ putpacket(outbuf);
+ }
+
+ gdbstub_busy = busy;
+}
+
+static kdev_t gdbstub_console_dev(struct console *con)
+{
+ return MKDEV(1, 3); /* /dev/null */
+}
+
+static struct console gdbstub_console = {
+ .name = "gdb",
+ .write = gdbstub_console_write,
+ .device = gdbstub_console_dev,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+};
+
+#endif
+
+/*
+ * Convert the memory pointed to by mem into hex, placing result in buf.
+ * - if successful, return a pointer to the last char put in buf (NUL)
+ * - in case of mem fault, return NULL
+ * may_fault is non-zero if we are reading from arbitrary memory, but is
+ * currently not used.
+ */
+static
+unsigned char *mem2hex(const void *_mem, char *buf, int count, int may_fault)
+{
+ const u8 *mem = _mem;
+ u8 ch[4];
+
+ if ((u32) mem & 1 && count >= 1) {
+ if (gdbstub_read_byte(mem, ch) != 0)
+ return 0;
+ *buf++ = hexchars[ch[0] >> 4];
+ *buf++ = hexchars[ch[0] & 0xf];
+ mem++;
+ count--;
+ }
+
+ if ((u32) mem & 3 && count >= 2) {
+ if (gdbstub_read_word(mem, ch) != 0)
+ return 0;
+ *buf++ = hexchars[ch[0] >> 4];
+ *buf++ = hexchars[ch[0] & 0xf];
+ *buf++ = hexchars[ch[1] >> 4];
+ *buf++ = hexchars[ch[1] & 0xf];
+ mem += 2;
+ count -= 2;
+ }
+
+ while (count >= 4) {
+ if (gdbstub_read_dword(mem, ch) != 0)
+ return 0;
+ *buf++ = hexchars[ch[0] >> 4];
+ *buf++ = hexchars[ch[0] & 0xf];
+ *buf++ = hexchars[ch[1] >> 4];
+ *buf++ = hexchars[ch[1] & 0xf];
+ *buf++ = hexchars[ch[2] >> 4];
+ *buf++ = hexchars[ch[2] & 0xf];
+ *buf++ = hexchars[ch[3] >> 4];
+ *buf++ = hexchars[ch[3] & 0xf];
+ mem += 4;
+ count -= 4;
+ }
+
+ if (count >= 2) {
+ if (gdbstub_read_word(mem, ch) != 0)
+ return 0;
+ *buf++ = hexchars[ch[0] >> 4];
+ *buf++ = hexchars[ch[0] & 0xf];
+ *buf++ = hexchars[ch[1] >> 4];
+ *buf++ = hexchars[ch[1] & 0xf];
+ mem += 2;
+ count -= 2;
+ }
+
+ if (count >= 1) {
+ if (gdbstub_read_byte(mem, ch) != 0)
+ return 0;
+ *buf++ = hexchars[ch[0] >> 4];
+ *buf++ = hexchars[ch[0] & 0xf];
+ }
+
+ *buf = 0;
+ return buf;
+}
+
+/*
+ * convert the hex array pointed to by buf into binary to be placed in mem
+ * return a pointer to the character AFTER the last byte written
+ * may_fault is non-zero if we are reading from arbitrary memory, but is
+ * currently not used.
+ */
+static
+const char *hex2mem(const char *buf, void *_mem, int count, int may_fault)
+{
+ u8 *mem = _mem;
+ union {
+ u32 val;
+ u8 b[4];
+ } ch;
+
+ if ((u32) mem & 1 && count >= 1) {
+ ch.b[0] = hex(*buf++) << 4;
+ ch.b[0] |= hex(*buf++);
+ if (gdbstub_write_byte(ch.val, mem) != 0)
+ return 0;
+ mem++;
+ count--;
+ }
+
+ if ((u32) mem & 3 && count >= 2) {
+ ch.b[0] = hex(*buf++) << 4;
+ ch.b[0] |= hex(*buf++);
+ ch.b[1] = hex(*buf++) << 4;
+ ch.b[1] |= hex(*buf++);
+ if (gdbstub_write_word(ch.val, mem) != 0)
+ return 0;
+ mem += 2;
+ count -= 2;
+ }
+
+ while (count >= 4) {
+ ch.b[0] = hex(*buf++) << 4;
+ ch.b[0] |= hex(*buf++);
+ ch.b[1] = hex(*buf++) << 4;
+ ch.b[1] |= hex(*buf++);
+ ch.b[2] = hex(*buf++) << 4;
+ ch.b[2] |= hex(*buf++);
+ ch.b[3] = hex(*buf++) << 4;
+ ch.b[3] |= hex(*buf++);
+ if (gdbstub_write_dword(ch.val, mem) != 0)
+ return 0;
+ mem += 4;
+ count -= 4;
+ }
+
+ if (count >= 2) {
+ ch.b[0] = hex(*buf++) << 4;
+ ch.b[0] |= hex(*buf++);
+ ch.b[1] = hex(*buf++) << 4;
+ ch.b[1] |= hex(*buf++);
+ if (gdbstub_write_word(ch.val, mem) != 0)
+ return 0;
+ mem += 2;
+ count -= 2;
+ }
+
+ if (count >= 1) {
+ ch.b[0] = hex(*buf++) << 4;
+ ch.b[0] |= hex(*buf++);
+ if (gdbstub_write_byte(ch.val, mem) != 0)
+ return 0;
+ }
+
+ return buf;
+}
+
+/*
+ * This table contains the mapping between MN10300 exception codes, and
+ * signals, which are primarily what GDB understands. It also indicates
+ * which hardware traps we need to commandeer when initializing the stub.
+ */
+static const struct excep_to_sig_map {
+ enum exception_code excep; /* MN10300 exception code */
+ unsigned char signo; /* Signal that we map this into */
+} excep_to_sig_map[] = {
+ { EXCEP_ITLBMISS, SIGSEGV },
+ { EXCEP_DTLBMISS, SIGSEGV },
+ { EXCEP_TRAP, SIGTRAP },
+ { EXCEP_ISTEP, SIGTRAP },
+ { EXCEP_IBREAK, SIGTRAP },
+ { EXCEP_OBREAK, SIGTRAP },
+ { EXCEP_UNIMPINS, SIGILL },
+ { EXCEP_UNIMPEXINS, SIGILL },
+ { EXCEP_MEMERR, SIGSEGV },
+ { EXCEP_MISALIGN, SIGSEGV },
+ { EXCEP_BUSERROR, SIGBUS },
+ { EXCEP_ILLINSACC, SIGSEGV },
+ { EXCEP_ILLDATACC, SIGSEGV },
+ { EXCEP_IOINSACC, SIGSEGV },
+ { EXCEP_PRIVINSACC, SIGSEGV },
+ { EXCEP_PRIVDATACC, SIGSEGV },
+ { EXCEP_FPU_DISABLED, SIGFPE },
+ { EXCEP_FPU_UNIMPINS, SIGFPE },
+ { EXCEP_FPU_OPERATION, SIGFPE },
+ { EXCEP_WDT, SIGALRM },
+ { EXCEP_NMI, SIGQUIT },
+ { EXCEP_IRQ_LEVEL0, SIGINT },
+ { EXCEP_IRQ_LEVEL1, SIGINT },
+ { EXCEP_IRQ_LEVEL2, SIGINT },
+ { EXCEP_IRQ_LEVEL3, SIGINT },
+ { EXCEP_IRQ_LEVEL4, SIGINT },
+ { EXCEP_IRQ_LEVEL5, SIGINT },
+ { EXCEP_IRQ_LEVEL6, SIGINT },
+ { 0, 0}
+};
+
+/*
+ * convert the MN10300 exception code into a UNIX signal number
+ */
+static int computeSignal(enum exception_code excep)
+{
+ const struct excep_to_sig_map *map;
+
+ for (map = excep_to_sig_map; map->signo; map++)
+ if (map->excep == excep)
+ return map->signo;
+
+ return SIGHUP; /* default for things we don't know about */
+}
+
+static u32 gdbstub_fpcr, gdbstub_fpufs_array[32];
+
+/*
+ *
+ */
+static void gdbstub_store_fpu(void)
+{
+#ifdef CONFIG_FPU
+
+ asm volatile(
+ "or %2,epsw\n"
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ "nop\n"
+ "nop\n"
+#endif
+ "mov %1, a1\n"
+ "fmov fs0, (a1+)\n"
+ "fmov fs1, (a1+)\n"
+ "fmov fs2, (a1+)\n"
+ "fmov fs3, (a1+)\n"
+ "fmov fs4, (a1+)\n"
+ "fmov fs5, (a1+)\n"
+ "fmov fs6, (a1+)\n"
+ "fmov fs7, (a1+)\n"
+ "fmov fs8, (a1+)\n"
+ "fmov fs9, (a1+)\n"
+ "fmov fs10, (a1+)\n"
+ "fmov fs11, (a1+)\n"
+ "fmov fs12, (a1+)\n"
+ "fmov fs13, (a1+)\n"
+ "fmov fs14, (a1+)\n"
+ "fmov fs15, (a1+)\n"
+ "fmov fs16, (a1+)\n"
+ "fmov fs17, (a1+)\n"
+ "fmov fs18, (a1+)\n"
+ "fmov fs19, (a1+)\n"
+ "fmov fs20, (a1+)\n"
+ "fmov fs21, (a1+)\n"
+ "fmov fs22, (a1+)\n"
+ "fmov fs23, (a1+)\n"
+ "fmov fs24, (a1+)\n"
+ "fmov fs25, (a1+)\n"
+ "fmov fs26, (a1+)\n"
+ "fmov fs27, (a1+)\n"
+ "fmov fs28, (a1+)\n"
+ "fmov fs29, (a1+)\n"
+ "fmov fs30, (a1+)\n"
+ "fmov fs31, (a1+)\n"
+ "fmov fpcr, %0\n"
+ : "=d"(gdbstub_fpcr)
+ : "g" (&gdbstub_fpufs_array), "i"(EPSW_FE)
+ : "a1"
+ );
+#endif
+}
+
+/*
+ *
+ */
+static void gdbstub_load_fpu(void)
+{
+#ifdef CONFIG_FPU
+
+ asm volatile(
+ "or %1,epsw\n"
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ "nop\n"
+ "nop\n"
+#endif
+ "mov %0, a1\n"
+ "fmov (a1+), fs0\n"
+ "fmov (a1+), fs1\n"
+ "fmov (a1+), fs2\n"
+ "fmov (a1+), fs3\n"
+ "fmov (a1+), fs4\n"
+ "fmov (a1+), fs5\n"
+ "fmov (a1+), fs6\n"
+ "fmov (a1+), fs7\n"
+ "fmov (a1+), fs8\n"
+ "fmov (a1+), fs9\n"
+ "fmov (a1+), fs10\n"
+ "fmov (a1+), fs11\n"
+ "fmov (a1+), fs12\n"
+ "fmov (a1+), fs13\n"
+ "fmov (a1+), fs14\n"
+ "fmov (a1+), fs15\n"
+ "fmov (a1+), fs16\n"
+ "fmov (a1+), fs17\n"
+ "fmov (a1+), fs18\n"
+ "fmov (a1+), fs19\n"
+ "fmov (a1+), fs20\n"
+ "fmov (a1+), fs21\n"
+ "fmov (a1+), fs22\n"
+ "fmov (a1+), fs23\n"
+ "fmov (a1+), fs24\n"
+ "fmov (a1+), fs25\n"
+ "fmov (a1+), fs26\n"
+ "fmov (a1+), fs27\n"
+ "fmov (a1+), fs28\n"
+ "fmov (a1+), fs29\n"
+ "fmov (a1+), fs30\n"
+ "fmov (a1+), fs31\n"
+ "fmov %2, fpcr\n"
+ :
+ : "g" (&gdbstub_fpufs_array), "i"(EPSW_FE), "d"(gdbstub_fpcr)
+ : "a1"
+ );
+#endif
+}
+
+/*
+ * set a software breakpoint
+ */
+int gdbstub_set_breakpoint(u8 *addr, int len)
+{
+ int bkpt, loop, xloop;
+
+#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
+ len = (len + 1) & ~1;
+#endif
+
+ gdbstub_bkpt("setbkpt(%p,%d)\n", addr, len);
+
+ for (bkpt = 255; bkpt >= 0; bkpt--)
+ if (!gdbstub_bkpts[bkpt].addr)
+ break;
+ if (bkpt < 0)
+ return -ENOSPC;
+
+ for (loop = 0; loop < len; loop++)
+ if (gdbstub_read_byte(&addr[loop],
+ &gdbstub_bkpts[bkpt].origbytes[loop]
+ ) < 0)
+ return -EFAULT;
+
+ gdbstub_flush_caches = 1;
+
+#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
+ for (loop = 0; loop < len; loop++)
+ if (gdbstub_write_byte(0xF7, &addr[loop]) < 0)
+ goto restore;
+#else
+ for (loop = 0; loop < len; loop++)
+ if (gdbstub_write_byte(0xFF, &addr[loop]) < 0)
+ goto restore;
+#endif
+
+ gdbstub_bkpts[bkpt].addr = addr;
+ gdbstub_bkpts[bkpt].len = len;
+
+ gdbstub_bkpt("Set BKPT[%02x]: %p-%p {%02x%02x%02x%02x%02x%02x%02x}\n",
+ bkpt,
+ gdbstub_bkpts[bkpt].addr,
+ gdbstub_bkpts[bkpt].addr + gdbstub_bkpts[bkpt].len - 1,
+ gdbstub_bkpts[bkpt].origbytes[0],
+ gdbstub_bkpts[bkpt].origbytes[1],
+ gdbstub_bkpts[bkpt].origbytes[2],
+ gdbstub_bkpts[bkpt].origbytes[3],
+ gdbstub_bkpts[bkpt].origbytes[4],
+ gdbstub_bkpts[bkpt].origbytes[5],
+ gdbstub_bkpts[bkpt].origbytes[6]
+ );
+
+ return 0;
+
+restore:
+ for (xloop = 0; xloop < loop; xloop++)
+ gdbstub_write_byte(gdbstub_bkpts[bkpt].origbytes[xloop],
+ addr + xloop);
+ return -EFAULT;
+}
+
+/*
+ * clear a software breakpoint
+ */
+int gdbstub_clear_breakpoint(u8 *addr, int len)
+{
+ int bkpt, loop;
+
+#ifdef GDBSTUB_USE_F7F7_AS_BREAKPOINT
+ len = (len + 1) & ~1;
+#endif
+
+ gdbstub_bkpt("clearbkpt(%p,%d)\n", addr, len);
+
+ for (bkpt = 255; bkpt >= 0; bkpt--)
+ if (gdbstub_bkpts[bkpt].addr == addr &&
+ gdbstub_bkpts[bkpt].len == len)
+ break;
+ if (bkpt < 0)
+ return -ENOENT;
+
+ gdbstub_bkpts[bkpt].addr = NULL;
+
+ gdbstub_flush_caches = 1;
+
+ for (loop = 0; loop < len; loop++)
+ if (gdbstub_write_byte(gdbstub_bkpts[bkpt].origbytes[loop],
+ addr + loop) < 0)
+ return -EFAULT;
+
+ return 0;
+}
+
+/*
+ * This function does all command processing for interfacing to gdb
+ * - returns 1 if the exception should be skipped, 0 otherwise.
+ */
+static int gdbstub(struct pt_regs *regs, enum exception_code excep)
+{
+ unsigned long *stack;
+ unsigned long epsw, mdr;
+ uint32_t zero, ssp;
+ uint8_t broke;
+ char *ptr;
+ int sigval;
+ int addr;
+ int length;
+ int loop;
+
+ if (excep == EXCEP_FPU_DISABLED)
+ return 0;
+
+ gdbstub_flush_caches = 0;
+
+ mn10300_set_gdbleds(1);
+
+ asm volatile("mov mdr,%0" : "=d"(mdr));
+ asm volatile("mov epsw,%0" : "=d"(epsw));
+ asm volatile("mov %0,epsw"
+ :: "d"((epsw & ~EPSW_IM) | EPSW_IE | EPSW_IM_1));
+
+ gdbstub_store_fpu();
+
+#ifdef CONFIG_GDBSTUB_IMMEDIATE
+ /* skip the initial pause loop */
+ if (regs->pc == (unsigned long) __gdbstub_pause)
+ regs->pc = (unsigned long) start_kernel;
+#endif
+
+ /* if we were single stepping, restore the opcodes hoisted for the
+ * breakpoint[s] */
+ broke = 0;
+ if ((step_bp[0].addr && step_bp[0].addr == (u8 *) regs->pc) ||
+ (step_bp[1].addr && step_bp[1].addr == (u8 *) regs->pc))
+ broke = 1;
+
+ __gdbstub_restore_bp();
+
+ if (gdbstub_rx_unget) {
+ sigval = SIGINT;
+ if (gdbstub_rx_unget != 3)
+ goto packet_waiting;
+ gdbstub_rx_unget = 0;
+ }
+
+ stack = (unsigned long *) regs->sp;
+ sigval = broke ? SIGTRAP : computeSignal(excep);
+
+ /* send information about a BUG() */
+ if (!user_mode(regs) && excep == EXCEP_SYSCALL15) {
+ const struct bug_entry *bug;
+
+ bug = find_bug(regs->pc);
+ if (bug)
+ goto found_bug;
+ length = snprintf(trans_buffer, sizeof(trans_buffer),
+ "BUG() at address %lx\n", regs->pc);
+ goto send_bug_pkt;
+
+ found_bug:
+ length = snprintf(trans_buffer, sizeof(trans_buffer),
+ "BUG() at address %lx (%s:%d)\n",
+ regs->pc, bug->file, bug->line);
+
+ send_bug_pkt:
+ ptr = output_buffer;
+ *ptr++ = 'O';
+ ptr = mem2hex(trans_buffer, ptr, length, 0);
+ *ptr = 0;
+ putpacket(output_buffer);
+
+ regs->pc -= 2;
+ sigval = SIGABRT;
+ } else if (regs->pc == (unsigned long) __gdbstub_bug_trap) {
+ regs->pc = regs->mdr;
+ sigval = SIGABRT;
+ }
+
+ /*
+ * send a message to the debugger's user saying what happened if it may
+ * not be clear cut (we can't map exceptions onto signals properly)
+ */
+ if (sigval != SIGINT && sigval != SIGTRAP && sigval != SIGILL) {
+ static const char title[] = "Excep ", tbcberr[] = "BCBERR ";
+ static const char crlf[] = "\r\n";
+ char hx;
+ u32 bcberr = BCBERR;
+
+ ptr = output_buffer;
+ *ptr++ = 'O';
+ ptr = mem2hex(title, ptr, sizeof(title) - 1, 0);
+
+ hx = hexchars[(excep & 0xf000) >> 12];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+ hx = hexchars[(excep & 0x0f00) >> 8];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+ hx = hexchars[(excep & 0x00f0) >> 4];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+ hx = hexchars[(excep & 0x000f)];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+
+ ptr = mem2hex(crlf, ptr, sizeof(crlf) - 1, 0);
+ *ptr = 0;
+ putpacket(output_buffer); /* send it off... */
+
+ /* BCBERR */
+ ptr = output_buffer;
+ *ptr++ = 'O';
+ ptr = mem2hex(tbcberr, ptr, sizeof(tbcberr) - 1, 0);
+
+ hx = hexchars[(bcberr & 0xf0000000) >> 28];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+ hx = hexchars[(bcberr & 0x0f000000) >> 24];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+ hx = hexchars[(bcberr & 0x00f00000) >> 20];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+ hx = hexchars[(bcberr & 0x000f0000) >> 16];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+ hx = hexchars[(bcberr & 0x0000f000) >> 12];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+ hx = hexchars[(bcberr & 0x00000f00) >> 8];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+ hx = hexchars[(bcberr & 0x000000f0) >> 4];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+ hx = hexchars[(bcberr & 0x0000000f)];
+ *ptr++ = hexchars[hx >> 4]; *ptr++ = hexchars[hx & 0xf];
+
+ ptr = mem2hex(crlf, ptr, sizeof(crlf) - 1, 0);
+ *ptr = 0;
+ putpacket(output_buffer); /* send it off... */
+ }
+
+ /*
+ * tell the debugger that an exception has occurred
+ */
+ ptr = output_buffer;
+
+ /*
+ * Send trap type (converted to signal)
+ */
+ *ptr++ = 'T';
+ *ptr++ = hexchars[sigval >> 4];
+ *ptr++ = hexchars[sigval & 0xf];
+
+ /*
+ * Send Error PC
+ */
+ *ptr++ = hexchars[GDB_REGID_PC >> 4];
+ *ptr++ = hexchars[GDB_REGID_PC & 0xf];
+ *ptr++ = ':';
+ ptr = mem2hex(®s->pc, ptr, 4, 0);
+ *ptr++ = ';';
+
+ /*
+ * Send frame pointer
+ */
+ *ptr++ = hexchars[GDB_REGID_FP >> 4];
+ *ptr++ = hexchars[GDB_REGID_FP & 0xf];
+ *ptr++ = ':';
+ ptr = mem2hex(®s->a3, ptr, 4, 0);
+ *ptr++ = ';';
+
+ /*
+ * Send stack pointer
+ */
+ ssp = (unsigned long) (regs + 1);
+ *ptr++ = hexchars[GDB_REGID_SP >> 4];
+ *ptr++ = hexchars[GDB_REGID_SP & 0xf];
+ *ptr++ = ':';
+ ptr = mem2hex(&ssp, ptr, 4, 0);
+ *ptr++ = ';';
+
+ *ptr++ = 0;
+ putpacket(output_buffer); /* send it off... */
+
+packet_waiting:
+ /*
+ * Wait for input from remote GDB
+ */
+ while (1) {
+ output_buffer[0] = 0;
+ getpacket(input_buffer);
+
+ switch (input_buffer[0]) {
+ /* request repeat of last signal number */
+ case '?':
+ output_buffer[0] = 'S';
+ output_buffer[1] = hexchars[sigval >> 4];
+ output_buffer[2] = hexchars[sigval & 0xf];
+ output_buffer[3] = 0;
+ break;
+
+ case 'd':
+ /* toggle debug flag */
+ break;
+
+ /*
+ * Return the value of the CPU registers
+ */
+ case 'g':
+ zero = 0;
+ ssp = (u32) (regs + 1);
+ ptr = output_buffer;
+ ptr = mem2hex(®s->d0, ptr, 4, 0);
+ ptr = mem2hex(®s->d1, ptr, 4, 0);
+ ptr = mem2hex(®s->d2, ptr, 4, 0);
+ ptr = mem2hex(®s->d3, ptr, 4, 0);
+ ptr = mem2hex(®s->a0, ptr, 4, 0);
+ ptr = mem2hex(®s->a1, ptr, 4, 0);
+ ptr = mem2hex(®s->a2, ptr, 4, 0);
+ ptr = mem2hex(®s->a3, ptr, 4, 0);
+
+ ptr = mem2hex(&ssp, ptr, 4, 0); /* 8 */
+ ptr = mem2hex(®s->pc, ptr, 4, 0);
+ ptr = mem2hex(®s->mdr, ptr, 4, 0);
+ ptr = mem2hex(®s->epsw, ptr, 4, 0);
+ ptr = mem2hex(®s->lir, ptr, 4, 0);
+ ptr = mem2hex(®s->lar, ptr, 4, 0);
+ ptr = mem2hex(®s->mdrq, ptr, 4, 0);
+
+ ptr = mem2hex(®s->e0, ptr, 4, 0); /* 15 */
+ ptr = mem2hex(®s->e1, ptr, 4, 0);
+ ptr = mem2hex(®s->e2, ptr, 4, 0);
+ ptr = mem2hex(®s->e3, ptr, 4, 0);
+ ptr = mem2hex(®s->e4, ptr, 4, 0);
+ ptr = mem2hex(®s->e5, ptr, 4, 0);
+ ptr = mem2hex(®s->e6, ptr, 4, 0);
+ ptr = mem2hex(®s->e7, ptr, 4, 0);
+
+ ptr = mem2hex(&ssp, ptr, 4, 0);
+ ptr = mem2hex(®s, ptr, 4, 0);
+ ptr = mem2hex(®s->sp, ptr, 4, 0);
+ ptr = mem2hex(®s->mcrh, ptr, 4, 0); /* 26 */
+ ptr = mem2hex(®s->mcrl, ptr, 4, 0);
+ ptr = mem2hex(®s->mcvf, ptr, 4, 0);
+
+ ptr = mem2hex(&gdbstub_fpcr, ptr, 4, 0); /* 29 - FPCR */
+ ptr = mem2hex(&zero, ptr, 4, 0);
+ ptr = mem2hex(&zero, ptr, 4, 0);
+ for (loop = 0; loop < 32; loop++)
+ ptr = mem2hex(&gdbstub_fpufs_array[loop],
+ ptr, 4, 0); /* 32 - FS0-31 */
+
+ break;
+
+ /*
+ * set the value of the CPU registers - return OK
+ */
+ case 'G':
+ {
+ const char *ptr;
+
+ ptr = &input_buffer[1];
+ ptr = hex2mem(ptr, ®s->d0, 4, 0);
+ ptr = hex2mem(ptr, ®s->d1, 4, 0);
+ ptr = hex2mem(ptr, ®s->d2, 4, 0);
+ ptr = hex2mem(ptr, ®s->d3, 4, 0);
+ ptr = hex2mem(ptr, ®s->a0, 4, 0);
+ ptr = hex2mem(ptr, ®s->a1, 4, 0);
+ ptr = hex2mem(ptr, ®s->a2, 4, 0);
+ ptr = hex2mem(ptr, ®s->a3, 4, 0);
+
+ ptr = hex2mem(ptr, &ssp, 4, 0); /* 8 */
+ ptr = hex2mem(ptr, ®s->pc, 4, 0);
+ ptr = hex2mem(ptr, ®s->mdr, 4, 0);
+ ptr = hex2mem(ptr, ®s->epsw, 4, 0);
+ ptr = hex2mem(ptr, ®s->lir, 4, 0);
+ ptr = hex2mem(ptr, ®s->lar, 4, 0);
+ ptr = hex2mem(ptr, ®s->mdrq, 4, 0);
+
+ ptr = hex2mem(ptr, ®s->e0, 4, 0); /* 15 */
+ ptr = hex2mem(ptr, ®s->e1, 4, 0);
+ ptr = hex2mem(ptr, ®s->e2, 4, 0);
+ ptr = hex2mem(ptr, ®s->e3, 4, 0);
+ ptr = hex2mem(ptr, ®s->e4, 4, 0);
+ ptr = hex2mem(ptr, ®s->e5, 4, 0);
+ ptr = hex2mem(ptr, ®s->e6, 4, 0);
+ ptr = hex2mem(ptr, ®s->e7, 4, 0);
+
+ ptr = hex2mem(ptr, &ssp, 4, 0);
+ ptr = hex2mem(ptr, &zero, 4, 0);
+ ptr = hex2mem(ptr, ®s->sp, 4, 0);
+ ptr = hex2mem(ptr, ®s->mcrh, 4, 0); /* 26 */
+ ptr = hex2mem(ptr, ®s->mcrl, 4, 0);
+ ptr = hex2mem(ptr, ®s->mcvf, 4, 0);
+
+ ptr = hex2mem(ptr, &zero, 4, 0); /* 29 - FPCR */
+ ptr = hex2mem(ptr, &zero, 4, 0);
+ ptr = hex2mem(ptr, &zero, 4, 0);
+ for (loop = 0; loop < 32; loop++) /* 32 - FS0-31 */
+ ptr = hex2mem(ptr, &zero, 4, 0);
+
+#if 0
+ /*
+ * See if the stack pointer has moved. If so, then copy
+ * the saved locals and ins to the new location.
+ */
+ unsigned long *newsp = (unsigned long *) registers[SP];
+ if (sp != newsp)
+ sp = memcpy(newsp, sp, 16 * 4);
+#endif
+
+ gdbstub_strcpy(output_buffer, "OK");
+ }
+ break;
+
+ /*
+ * mAA..AA,LLLL Read LLLL bytes at address AA..AA
+ */
+ case 'm':
+ ptr = &input_buffer[1];
+
+ if (hexToInt(&ptr, &addr) &&
+ *ptr++ == ',' &&
+ hexToInt(&ptr, &length)
+ ) {
+ if (mem2hex((char *) addr, output_buffer,
+ length, 1))
+ break;
+ gdbstub_strcpy(output_buffer, "E03");
+ } else {
+ gdbstub_strcpy(output_buffer, "E01");
+ }
+ break;
+
+ /*
+ * MAA..AA,LLLL: Write LLLL bytes at address AA.AA
+ * return OK
+ */
+ case 'M':
+ ptr = &input_buffer[1];
+
+ if (hexToInt(&ptr, &addr) &&
+ *ptr++ == ',' &&
+ hexToInt(&ptr, &length) &&
+ *ptr++ == ':'
+ ) {
+ if (hex2mem(ptr, (char *) addr, length, 1))
+ gdbstub_strcpy(output_buffer, "OK");
+ else
+ gdbstub_strcpy(output_buffer, "E03");
+
+ gdbstub_flush_caches = 1;
+ } else {
+ gdbstub_strcpy(output_buffer, "E02");
+ }
+ break;
+
+ /*
+ * cAA..AA Continue at address AA..AA(optional)
+ */
+ case 'c':
+ /* try to read optional parameter, pc unchanged if no
+ * parm */
+
+ ptr = &input_buffer[1];
+ if (hexToInt(&ptr, &addr))
+ regs->pc = addr;
+ goto done;
+
+ /*
+ * kill the program
+ */
+ case 'k' :
+ goto done; /* just continue */
+
+ /*
+ * Reset the whole machine (FIXME: system dependent)
+ */
+ case 'r':
+ break;
+
+ /*
+ * Step to next instruction
+ */
+ case 's':
+ /*
+ * using the T flag doesn't seem to perform single
+ * stepping (it seems to wind up being caught by the
+ * JTAG unit), so we have to use breakpoints and
+ * continue instead.
+ */
+ if (gdbstub_single_step(regs) < 0)
+ /* ignore any fault error for now */
+ gdbstub_printk("unable to set single-step"
+ " bp\n");
+ goto done;
+
+ /*
+ * Set baud rate (bBB)
+ */
+ case 'b':
+ do {
+ int baudrate;
+
+ ptr = &input_buffer[1];
+ if (!hexToInt(&ptr, &baudrate)) {
+ gdbstub_strcpy(output_buffer, "B01");
+ break;
+ }
+
+ if (baudrate) {
+ /* ACK before changing speed */
+ putpacket("OK");
+ gdbstub_io_set_baud(baudrate);
+ }
+ } while (0);
+ break;
+
+ /*
+ * Set breakpoint
+ */
+ case 'Z':
+ ptr = &input_buffer[1];
+
+ if (!hexToInt(&ptr, &loop) || *ptr++ != ',' ||
+ !hexToInt(&ptr, &addr) || *ptr++ != ',' ||
+ !hexToInt(&ptr, &length)
+ ) {
+ gdbstub_strcpy(output_buffer, "E01");
+ break;
+ }
+
+ /* only support software breakpoints */
+ gdbstub_strcpy(output_buffer, "E03");
+ if (loop != 0 ||
+ length < 1 ||
+ length > 7 ||
+ (unsigned long) addr < 4096)
+ break;
+
+ if (gdbstub_set_breakpoint((u8 *) addr, length) < 0)
+ break;
+
+ gdbstub_strcpy(output_buffer, "OK");
+ break;
+
+ /*
+ * Clear breakpoint
+ */
+ case 'z':
+ ptr = &input_buffer[1];
+
+ if (!hexToInt(&ptr, &loop) || *ptr++ != ',' ||
+ !hexToInt(&ptr, &addr) || *ptr++ != ',' ||
+ !hexToInt(&ptr, &length)
+ ) {
+ gdbstub_strcpy(output_buffer, "E01");
+ break;
+ }
+
+ /* only support software breakpoints */
+ gdbstub_strcpy(output_buffer, "E03");
+ if (loop != 0 ||
+ length < 1 ||
+ length > 7 ||
+ (unsigned long) addr < 4096)
+ break;
+
+ if (gdbstub_clear_breakpoint((u8 *) addr, length) < 0)
+ break;
+
+ gdbstub_strcpy(output_buffer, "OK");
+ break;
+
+ default:
+ gdbstub_proto("### GDB Unsupported Cmd '%s'\n",
+ input_buffer);
+ break;
+ }
+
+ /* reply to the request */
+ putpacket(output_buffer);
+ }
+
+done:
+ /*
+ * Need to flush the instruction cache here, as we may
+ * have deposited a breakpoint, and the icache probably
+ * has no way of knowing that a data ref to some location
+ * may have changed something that is in the instruction
+ * cache.
+ * NB: We flush both caches, just to be sure...
+ */
+ if (gdbstub_flush_caches)
+ gdbstub_purge_cache();
+
+ gdbstub_load_fpu();
+ mn10300_set_gdbleds(0);
+ if (excep == EXCEP_NMI)
+ NMICR = NMICR_NMIF;
+
+ touch_softlockup_watchdog();
+
+ local_irq_restore(epsw);
+ return 1;
+}
+
+/*
+ * handle event interception
+ */
+asmlinkage int gdbstub_intercept(struct pt_regs *regs,
+ enum exception_code excep)
+{
+ static u8 notfirst = 1;
+ int ret;
+
+ if (gdbstub_busy)
+ gdbstub_printk("--> gdbstub reentered itself\n");
+ gdbstub_busy = 1;
+
+ if (notfirst) {
+ unsigned long mdr;
+ asm("mov mdr,%0" : "=d"(mdr));
+
+ gdbstub_entry(
+ "--> gdbstub_intercept(%p,%04x) [MDR=%lx PC=%lx]\n",
+ regs, excep, mdr, regs->pc);
+
+ gdbstub_entry(
+ "PC: %08lx EPSW: %08lx SSP: %08lx mode: %s\n",
+ regs->pc, regs->epsw, (unsigned long) &ret,
+ user_mode(regs) ? "User" : "Super");
+ gdbstub_entry(
+ "d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n",
+ regs->d0, regs->d1, regs->d2, regs->d3);
+ gdbstub_entry(
+ "a0: %08lx a1: %08lx a2: %08lx a3: %08lx\n",
+ regs->a0, regs->a1, regs->a2, regs->a3);
+ gdbstub_entry(
+ "e0: %08lx e1: %08lx e2: %08lx e3: %08lx\n",
+ regs->e0, regs->e1, regs->e2, regs->e3);
+ gdbstub_entry(
+ "e4: %08lx e5: %08lx e6: %08lx e7: %08lx\n",
+ regs->e4, regs->e5, regs->e6, regs->e7);
+ gdbstub_entry(
+ "lar: %08lx lir: %08lx mdr: %08lx usp: %08lx\n",
+ regs->lar, regs->lir, regs->mdr, regs->sp);
+ gdbstub_entry(
+ "cvf: %08lx crl: %08lx crh: %08lx drq: %08lx\n",
+ regs->mcvf, regs->mcrl, regs->mcrh, regs->mdrq);
+ gdbstub_entry(
+ "threadinfo=%p task=%p)\n",
+ current_thread_info(), current);
+ } else {
+ notfirst = 1;
+ }
+
+ ret = gdbstub(regs, excep);
+
+ gdbstub_entry("<-- gdbstub_intercept()\n");
+ gdbstub_busy = 0;
+ return ret;
+}
+
+/*
+ * handle the GDB stub itself causing an exception
+ */
+asmlinkage void gdbstub_exception(struct pt_regs *regs,
+ enum exception_code excep)
+{
+ unsigned long mdr;
+
+ asm("mov mdr,%0" : "=d"(mdr));
+ gdbstub_entry("--> gdbstub exception({%p},%04x) [MDR=%lx]\n",
+ regs, excep, mdr);
+
+ while ((unsigned long) regs == 0xffffffff) {}
+
+ /* handle guarded memory accesses where we know it might fault */
+ if (regs->pc == (unsigned) gdbstub_read_byte_guard) {
+ regs->pc = (unsigned) gdbstub_read_byte_cont;
+ goto fault;
+ }
+
+ if (regs->pc == (unsigned) gdbstub_read_word_guard) {
+ regs->pc = (unsigned) gdbstub_read_word_cont;
+ goto fault;
+ }
+
+ if (regs->pc == (unsigned) gdbstub_read_dword_guard) {
+ regs->pc = (unsigned) gdbstub_read_dword_cont;
+ goto fault;
+ }
+
+ if (regs->pc == (unsigned) gdbstub_write_byte_guard) {
+ regs->pc = (unsigned) gdbstub_write_byte_cont;
+ goto fault;
+ }
+
+ if (regs->pc == (unsigned) gdbstub_write_word_guard) {
+ regs->pc = (unsigned) gdbstub_write_word_cont;
+ goto fault;
+ }
+
+ if (regs->pc == (unsigned) gdbstub_write_dword_guard) {
+ regs->pc = (unsigned) gdbstub_write_dword_cont;
+ goto fault;
+ }
+
+ gdbstub_printk("\n### GDB stub caused an exception ###\n");
+
+ /* something went horribly wrong */
+ console_verbose();
+ show_registers(regs);
+
+ panic("GDB Stub caused an unexpected exception - can't continue\n");
+
+ /* we caught an attempt by the stub to access silly memory */
+fault:
+ gdbstub_entry("<-- gdbstub exception() = EFAULT\n");
+ regs->d0 = -EFAULT;
+ return;
+}
+
+/*
+ * send an exit message to GDB
+ */
+void gdbstub_exit(int status)
+{
+ unsigned char checksum;
+ unsigned char ch;
+ int count;
+
+ gdbstub_busy = 1;
+ output_buffer[0] = 'W';
+ output_buffer[1] = hexchars[(status >> 4) & 0x0F];
+ output_buffer[2] = hexchars[status & 0x0F];
+ output_buffer[3] = 0;
+
+ gdbstub_io_tx_char('$');
+ checksum = 0;
+ count = 0;
+
+ while ((ch = output_buffer[count]) != 0) {
+ gdbstub_io_tx_char(ch);
+ checksum += ch;
+ count += 1;
+ }
+
+ gdbstub_io_tx_char('#');
+ gdbstub_io_tx_char(hexchars[checksum >> 4]);
+ gdbstub_io_tx_char(hexchars[checksum & 0xf]);
+
+ /* make sure the output is flushed, or else RedBoot might clobber it */
+ gdbstub_io_tx_flush();
+
+ gdbstub_busy = 0;
+}
+
+/*
+ * initialise the GDB stub
+ */
+asmlinkage void __init gdbstub_init(void)
+{
+#ifdef CONFIG_GDBSTUB_IMMEDIATE
+ unsigned char ch;
+ int ret;
+#endif
+
+ gdbstub_busy = 1;
+
+ printk(KERN_INFO "%s", gdbstub_banner);
+
+ gdbstub_io_init();
+
+ gdbstub_entry("--> gdbstub_init\n");
+
+ /* try to talk to GDB (or anyone insane enough to want to type GDB
+ * protocol by hand) */
+ gdbstub_io("### GDB Tx ACK\n");
+ gdbstub_io_tx_char('+'); /* 'hello world' */
+
+#ifdef CONFIG_GDBSTUB_IMMEDIATE
+ gdbstub_printk("GDB Stub waiting for packet\n");
+
+ /* in case GDB is started before us, ACK any packets that are already
+ * sitting there (presumably "$?#xx")
+ */
+ do { gdbstub_io_rx_char(&ch, 0); } while (ch != '$');
+ do { gdbstub_io_rx_char(&ch, 0); } while (ch != '#');
+ /* eat first csum byte */
+ do { ret = gdbstub_io_rx_char(&ch, 0); } while (ret != 0);
+ /* eat second csum byte */
+ do { ret = gdbstub_io_rx_char(&ch, 0); } while (ret != 0);
+
+ gdbstub_io("### GDB Tx NAK\n");
+ gdbstub_io_tx_char('-'); /* NAK it */
+
+#else
+ printk("GDB Stub ready\n");
+#endif
+
+ gdbstub_busy = 0;
+ gdbstub_entry("<-- gdbstub_init\n");
+}
+
+/*
+ * register the console at a more appropriate time
+ */
+#ifdef CONFIG_GDBSTUB_CONSOLE
+static int __init gdbstub_postinit(void)
+{
+ printk(KERN_NOTICE "registering console\n");
+ register_console(&gdbstub_console);
+ return 0;
+}
+
+__initcall(gdbstub_postinit);
+#endif
+
+/*
+ * handle character reception on GDB serial port
+ * - jump into the GDB stub if BREAK is detected on the serial line
+ */
+asmlinkage void gdbstub_rx_irq(struct pt_regs *regs, enum exception_code excep)
+{
+ char ch;
+ int ret;
+
+ gdbstub_entry("--> gdbstub_rx_irq\n");
+
+ do {
+ ret = gdbstub_io_rx_char(&ch, 1);
+ if (ret != -EIO && ret != -EAGAIN) {
+ if (ret != -EINTR)
+ gdbstub_rx_unget = ch;
+ gdbstub(regs, excep);
+ }
+ } while (ret != -EAGAIN);
+
+ gdbstub_entry("<-- gdbstub_rx_irq\n");
+}
--- /dev/null
+/* Boot entry point for MN10300 kernel
+ *
+ * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#include <linux/threads.h>
+#include <linux/linkage.h>
+#include <linux/serial_reg.h>
+#include <asm/thread_info.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/frame.inc>
+#include <asm/param.h>
+#include <asm/unit/serial.h>
+
+ .section .text.head,"ax"
+
+###############################################################################
+#
+# bootloader entry point
+#
+###############################################################################
+ .globl _start
+ .type _start,@function
+_start:
+ # save commandline pointer
+ mov d0,a3
+
+ # preload the PGD pointer register
+ mov swapper_pg_dir,d0
+ mov d0,(PTBR)
+
+ # turn on the TLBs
+ mov MMUCTR_IIV|MMUCTR_DIV,d0
+ mov d0,(MMUCTR)
+ mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0
+ mov d0,(MMUCTR)
+
+ # turn on AM33v2 exception handling mode and set the trap table base
+ movhu (CPUP),d0
+ or CPUP_EXM_AM33V2,d0
+ movhu d0,(CPUP)
+ mov CONFIG_INTERRUPT_VECTOR_BASE,d0
+ mov d0,(TBR)
+
+ # invalidate and enable both of the caches
+ mov CHCTR,a0
+ clr d0
+ movhu d0,(a0) # turn off first
+ mov CHCTR_ICINV|CHCTR_DCINV,d0
+ movhu d0,(a0)
+ setlb
+ mov (a0),d0
+ btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
+ lne
+
+#ifndef CONFIG_MN10300_CACHE_DISABLED
+#ifdef CONFIG_MN10300_CACHE_WBACK
+#ifndef CONFIG_MN10300_CACHE_WBACK_NOWRALLOC
+ mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
+#else
+ mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0
+#endif /* CACHE_DISABLED */
+#else
+ mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
+#endif /* WBACK */
+ movhu d0,(a0) # enable
+#endif /* NOWRALLOC */
+
+ # turn on RTS on the debug serial port if applicable
+#ifdef CONFIG_MN10300_UNIT_ASB2305
+ bset UART_MCR_RTS,(ASB2305_DEBUG_MCR)
+#endif
+
+ # clear the BSS area
+ mov __bss_start,a0
+ mov __bss_stop,a1
+ clr d0
+bssclear:
+ cmp a1,a0
+ bge bssclear_end
+ mov d0,(a0)
+ inc4 a0
+ bra bssclear
+bssclear_end:
+
+ # retrieve the parameters (including command line) before we overwrite
+ # them
+ cmp 0xabadcafe,d1
+ bne __no_parameters
+
+__copy_parameters:
+ mov redboot_command_line,a0
+ mov a0,a1
+ add COMMAND_LINE_SIZE,a1
+1:
+ movbu (a3),d0
+ inc a3
+ movbu d0,(a0)
+ inc a0
+ cmp a1,a0
+ blt 1b
+
+ mov redboot_platform_name,a0
+ mov a0,a1
+ add COMMAND_LINE_SIZE,a1
+ mov d2,a3
+1:
+ movbu (a3),d0
+ inc a3
+ movbu d0,(a0)
+ inc a0
+ cmp a1,a0
+ blt 1b
+
+__no_parameters:
+
+ # set up the registers with recognisable rubbish in them
+ mov init_thread_union+THREAD_SIZE-12,sp
+
+ mov 0xea01eaea,d0
+ mov d0,(4,sp) # EPSW save area
+ mov 0xea02eaea,d0
+ mov d0,(8,sp) # PC save area
+
+ mov 0xeb0060ed,d0
+ mov d0,mdr
+ mov 0xeb0061ed,d0
+ mov d0,mdrq
+ mov 0xeb0062ed,d0
+ mov d0,mcrh
+ mov 0xeb0063ed,d0
+ mov d0,mcrl
+ mov 0xeb0064ed,d0
+ mov d0,mcvf
+ mov 0xed0065ed,a3
+ mov a3,usp
+
+ mov 0xed00e0ed,e0
+ mov 0xed00e1ed,e1
+ mov 0xed00e2ed,e2
+ mov 0xed00e3ed,e3
+ mov 0xed00e4ed,e4
+ mov 0xed00e5ed,e5
+ mov 0xed00e6ed,e6
+ mov 0xed00e7ed,e7
+
+ mov 0xed00d0ed,d0
+ mov 0xed00d1ed,d1
+ mov 0xed00d2ed,d2
+ mov 0xed00d3ed,d3
+ mov 0xed00a0ed,a0
+ mov 0xed00a1ed,a1
+ mov 0xed00a2ed,a2
+ mov 0,a3
+
+ # set up the initial kernel stack
+ SAVE_ALL
+ mov 0xffffffff,d0
+ mov d0,(REG_ORIG_D0,fp)
+
+ # put different recognisable rubbish in the regs
+ mov 0xfb0060ed,d0
+ mov d0,mdr
+ mov 0xfb0061ed,d0
+ mov d0,mdrq
+ mov 0xfb0062ed,d0
+ mov d0,mcrh
+ mov 0xfb0063ed,d0
+ mov d0,mcrl
+ mov 0xfb0064ed,d0
+ mov d0,mcvf
+ mov 0xfd0065ed,a0
+ mov a0,usp
+
+ mov 0xfd00e0ed,e0
+ mov 0xfd00e1ed,e1
+ mov 0xfd00e2ed,e2
+ mov 0xfd00e3ed,e3
+ mov 0xfd00e4ed,e4
+ mov 0xfd00e5ed,e5
+ mov 0xfd00e6ed,e6
+ mov 0xfd00e7ed,e7
+
+ mov 0xfd00d0ed,d0
+ mov 0xfd00d1ed,d1
+ mov 0xfd00d2ed,d2
+ mov 0xfd00d3ed,d3
+ mov 0xfd00a0ed,a0
+ mov 0xfd00a1ed,a1
+ mov 0xfd00a2ed,a2
+
+ # we may be holding current in E2
+#ifdef CONFIG_MN10300_CURRENT_IN_E2
+ mov init_task,e2
+#endif
+
+ # initialise the processor and the unit
+ call processor_init[],0
+ call unit_init[],0
+
+#ifdef CONFIG_GDBSTUB
+ call gdbstub_init[],0
+
+#ifdef CONFIG_GDBSTUB_IMMEDIATE
+ .globl __gdbstub_pause
+__gdbstub_pause:
+ bra __gdbstub_pause
+#endif
+#endif
+
+ jmp start_kernel
+ .size _start, _start-.
+ENTRY(__head_end)
+
+/*
+ * This is initialized to disallow all access to the low 2G region
+ * - the high 2G region is managed directly by the MMU
+ * - range 0x70000000-0x7C000000 are initialised for use by VMALLOC
+ */
+ .section .bss
+ .balign PAGE_SIZE
+ENTRY(swapper_pg_dir)
+ .space PTRS_PER_PGD*4
+
+/*
+ * The page tables are initialized to only 8MB here - the final page
+ * tables are set up later depending on memory size.
+ */
+
+ .balign PAGE_SIZE
+ENTRY(empty_zero_page)
+ .space PAGE_SIZE
+
+ .balign PAGE_SIZE
+ENTRY(empty_bad_page)
+ .space PAGE_SIZE
+
+ .balign PAGE_SIZE
+ENTRY(empty_bad_pte_table)
+ .space PAGE_SIZE
+
+ .balign PAGE_SIZE
+ENTRY(large_page_table)
+ .space PAGE_SIZE
+
+ .balign PAGE_SIZE
+ENTRY(kernel_vmalloc_ptes)
+ .space ((VMALLOC_END-VMALLOC_START)/PAGE_SIZE)*4
--- /dev/null
+/* MN10300 Initial task definitions
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/init_task.h>
+#include <linux/fs.h>
+#include <linux/mqueue.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+
+static struct fs_struct init_fs = INIT_FS;
+static struct files_struct init_files = INIT_FILES;
+static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
+static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
+struct mm_struct init_mm = INIT_MM(init_mm);
+EXPORT_SYMBOL(init_mm);
+
+/*
+ * Initial thread structure.
+ *
+ * We need to make sure that this is THREAD_SIZE aligned due to the
+ * way process stacks are handled. This is done by having a special
+ * "init_task" linker map entry..
+ */
+union thread_union init_thread_union
+ __attribute__((__section__(".data.init_task"))) =
+ { INIT_THREAD_INFO(init_task) };
+
+/*
+ * Initial task structure.
+ *
+ * All other task structs will be allocated on slabs in fork.c
+ */
+struct task_struct init_task = INIT_TASK(init_task);
+EXPORT_SYMBOL(init_task);
--- /dev/null
+/* Internal definitions for the arch part of the core kernel
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+/*
+ * kthread.S
+ */
+extern int kernel_thread_helper(int);
+
+/*
+ * entry.S
+ */
+extern void ret_from_fork(struct task_struct *) __attribute__((noreturn));
--- /dev/null
+/* MN10300 Misaligned multibyte-word I/O
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <asm/io.h>
+
+/*
+ * output data from a potentially misaligned buffer
+ */
+void __outsl(unsigned long addr, const void *buffer, int count)
+{
+ const unsigned char *buf = buffer;
+ unsigned long val;
+
+ while (count--) {
+ memcpy(&val, buf, 4);
+ outl(val, addr);
+ buf += 4;
+ }
+}
+EXPORT_SYMBOL(__outsl);
--- /dev/null
+/* MN10300 Arch-specific interrupt handling
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/seq_file.h>
+#include <asm/setup.h>
+
+unsigned long __mn10300_irq_enabled_epsw = EPSW_IE | EPSW_IM_7;
+EXPORT_SYMBOL(__mn10300_irq_enabled_epsw);
+
+atomic_t irq_err_count;
+
+/*
+ * MN10300 INTC controller operations
+ */
+static void mn10300_cpupic_disable(unsigned int irq)
+{
+ u16 tmp = GxICR(irq);
+ GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT;
+ tmp = GxICR(irq);
+}
+
+static void mn10300_cpupic_enable(unsigned int irq)
+{
+ u16 tmp = GxICR(irq);
+ GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE;
+ tmp = GxICR(irq);
+}
+
+static void mn10300_cpupic_ack(unsigned int irq)
+{
+ u16 tmp;
+ *(volatile u8 *) &GxICR(irq) = GxICR_DETECT;
+ tmp = GxICR(irq);
+}
+
+static void mn10300_cpupic_mask(unsigned int irq)
+{
+ u16 tmp = GxICR(irq);
+ GxICR(irq) = (tmp & GxICR_LEVEL);
+ tmp = GxICR(irq);
+}
+
+static void mn10300_cpupic_mask_ack(unsigned int irq)
+{
+ u16 tmp = GxICR(irq);
+ GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_DETECT;
+ tmp = GxICR(irq);
+}
+
+static void mn10300_cpupic_unmask(unsigned int irq)
+{
+ u16 tmp = GxICR(irq);
+ GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
+ tmp = GxICR(irq);
+}
+
+static void mn10300_cpupic_end(unsigned int irq)
+{
+ u16 tmp = GxICR(irq);
+ GxICR(irq) = (tmp & GxICR_LEVEL) | GxICR_ENABLE;
+ tmp = GxICR(irq);
+}
+
+static struct irq_chip mn10300_cpu_pic = {
+ .name = "cpu",
+ .disable = mn10300_cpupic_disable,
+ .enable = mn10300_cpupic_enable,
+ .ack = mn10300_cpupic_ack,
+ .mask = mn10300_cpupic_mask,
+ .mask_ack = mn10300_cpupic_mask_ack,
+ .unmask = mn10300_cpupic_unmask,
+ .end = mn10300_cpupic_end,
+};
+
+/*
+ * 'what should we do if we get a hw irq event on an illegal vector'.
+ * each architecture has to answer this themselves.
+ */
+void ack_bad_irq(int irq)
+{
+ printk(KERN_WARNING "unexpected IRQ trap at vector %02x\n", irq);
+}
+
+/*
+ * change the level at which an IRQ executes
+ * - must not be called whilst interrupts are being processed!
+ */
+void set_intr_level(int irq, u16 level)
+{
+ u16 tmp;
+
+ if (in_interrupt())
+ BUG();
+
+ tmp = GxICR(irq);
+ GxICR(irq) = (tmp & GxICR_ENABLE) | level;
+ tmp = GxICR(irq);
+}
+
+/*
+ * mark an interrupt to be ACK'd after interrupt handlers have been run rather
+ * than before
+ * - see Documentation/mn10300/features.txt
+ */
+void set_intr_postackable(int irq)
+{
+ set_irq_handler(irq, handle_level_irq);
+}
+
+/*
+ * initialise the interrupt system
+ */
+void __init init_IRQ(void)
+{
+ int irq;
+
+ for (irq = 0; irq < NR_IRQS; irq++)
+ if (irq_desc[irq].chip == &no_irq_type)
+ set_irq_chip_and_handler(irq, &mn10300_cpu_pic,
+ handle_edge_irq);
+ unit_init_IRQ();
+}
+
+/*
+ * handle normal device IRQs
+ */
+asmlinkage void do_IRQ(void)
+{
+ unsigned long sp, epsw, irq_disabled_epsw, old_irq_enabled_epsw;
+ int irq;
+
+ sp = current_stack_pointer();
+ if (sp - (sp & ~(THREAD_SIZE - 1)) < STACK_WARN)
+ BUG();
+
+ /* make sure local_irq_enable() doesn't muck up the interrupt priority
+ * setting in EPSW */
+ old_irq_enabled_epsw = __mn10300_irq_enabled_epsw;
+ local_save_flags(epsw);
+ __mn10300_irq_enabled_epsw = EPSW_IE | (EPSW_IM & epsw);
+ irq_disabled_epsw = EPSW_IE | MN10300_CLI_LEVEL;
+
+ __IRQ_STAT(smp_processor_id(), __irq_count)++;
+
+ irq_enter();
+
+ for (;;) {
+ /* ask the interrupt controller for the next IRQ to process
+ * - the result we get depends on EPSW.IM
+ */
+ irq = IAGR & IAGR_GN;
+ if (!irq)
+ break;
+
+ local_irq_restore(irq_disabled_epsw);
+
+ generic_handle_irq(irq >> 2);
+
+ /* restore IRQ controls for IAGR access */
+ local_irq_restore(epsw);
+ }
+
+ __mn10300_irq_enabled_epsw = old_irq_enabled_epsw;
+
+ irq_exit();
+}
+
+/*
+ * Display interrupt management information through /proc/interrupts
+ */
+int show_interrupts(struct seq_file *p, void *v)
+{
+ int i = *(loff_t *) v, j, cpu;
+ struct irqaction *action;
+ unsigned long flags;
+
+ switch (i) {
+ /* display column title bar naming CPUs */
+ case 0:
+ seq_printf(p, " ");
+ for (j = 0; j < NR_CPUS; j++)
+ if (cpu_online(j))
+ seq_printf(p, "CPU%d ", j);
+ seq_putc(p, '\n');
+ break;
+
+ /* display information rows, one per active CPU */
+ case 1 ... NR_IRQS - 1:
+ spin_lock_irqsave(&irq_desc[i].lock, flags);
+
+ action = irq_desc[i].action;
+ if (action) {
+ seq_printf(p, "%3d: ", i);
+ for_each_present_cpu(cpu)
+ seq_printf(p, "%10u ", kstat_cpu(cpu).irqs[i]);
+ seq_printf(p, " %14s.%u", irq_desc[i].chip->name,
+ (GxICR(i) & GxICR_LEVEL) >>
+ GxICR_LEVEL_SHIFT);
+ seq_printf(p, " %s", action->name);
+
+ for (action = action->next;
+ action;
+ action = action->next)
+ seq_printf(p, ", %s", action->name);
+
+ seq_putc(p, '\n');
+ }
+
+ spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+ break;
+
+ /* polish off with NMI and error counters */
+ case NR_IRQS:
+ seq_printf(p, "NMI: ");
+ for (j = 0; j < NR_CPUS; j++)
+ if (cpu_online(j))
+ seq_printf(p, "%10u ", nmi_count(j));
+ seq_putc(p, '\n');
+
+ seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
+ break;
+ }
+
+ return 0;
+}
--- /dev/null
+/* MN10300 In-kernel program execution
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/linkage.h>
+#include <asm/unistd.h>
+
+###############################################################################
+#
+# Do a system call from kernel instead of calling sys_execve so we end up with
+# proper pt_regs.
+#
+# int kernel_execve(const char *filename, char *const argv[],
+# char *const envp[])
+#
+# On entry: D0/D1/8(SP): arguments to function
+# On return: D0: syscall return.
+#
+###############################################################################
+ .globl kernel_execve
+ .type kernel_execve,@function
+kernel_execve:
+ mov a3,a1
+ mov d0,a0
+ mov (12,sp),a3
+ mov +__NR_execve,d0
+ syscall 0
+ mov a1,a3
+ rets
+
+ .size kernel_execve,.-kernel_execve
--- /dev/null
+/* MN10300 Kernel probes implementation
+ *
+ * Copyright (C) 2005 Red Hat, Inc. All Rights Reserved.
+ * Written by Mark Salter (msalter@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public Licence as published by
+ * the Free Software Foundation; either version 2 of the Licence, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public Licence for more details.
+ *
+ * You should have received a copy of the GNU General Public Licence
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+#include <linux/kprobes.h>
+#include <linux/ptrace.h>
+#include <linux/spinlock.h>
+#include <linux/preempt.h>
+#include <linux/kdebug.h>
+#include <asm/cacheflush.h>
+
+struct kretprobe_blackpoint kretprobe_blacklist[] = { { NULL, NULL } };
+const int kretprobe_blacklist_size = ARRAY_SIZE(kretprobe_blacklist);
+
+/* kprobe_status settings */
+#define KPROBE_HIT_ACTIVE 0x00000001
+#define KPROBE_HIT_SS 0x00000002
+
+static struct kprobe *current_kprobe;
+static unsigned long current_kprobe_orig_pc;
+static unsigned long current_kprobe_next_pc;
+static int current_kprobe_ss_flags;
+static unsigned long kprobe_status;
+static kprobe_opcode_t current_kprobe_ss_buf[MAX_INSN_SIZE + 2];
+static unsigned long current_kprobe_bp_addr;
+
+DEFINE_PER_CPU(struct kprobe *, current_kprobe) = NULL;
+
+
+/* singlestep flag bits */
+#define SINGLESTEP_BRANCH 1
+#define SINGLESTEP_PCREL 2
+
+#define READ_BYTE(p, valp) \
+ do { *(u8 *)(valp) = *(u8 *)(p); } while (0)
+
+#define READ_WORD16(p, valp) \
+ do { \
+ READ_BYTE((p), (valp)); \
+ READ_BYTE((u8 *)(p) + 1, (u8 *)(valp) + 1); \
+ } while (0)
+
+#define READ_WORD32(p, valp) \
+ do { \
+ READ_BYTE((p), (valp)); \
+ READ_BYTE((u8 *)(p) + 1, (u8 *)(valp) + 1); \
+ READ_BYTE((u8 *)(p) + 2, (u8 *)(valp) + 2); \
+ READ_BYTE((u8 *)(p) + 3, (u8 *)(valp) + 3); \
+ } while (0)
+
+
+static const u8 mn10300_insn_sizes[256] =
+{
+ /* 1 2 3 4 5 6 7 8 9 a b c d e f */
+ 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, /* 0 */
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 1 */
+ 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, /* 2 */
+ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, /* 3 */
+ 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, /* 4 */
+ 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, /* 5 */
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 6 */
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* 7 */
+ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 8 */
+ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* 9 */
+ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* a */
+ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, /* b */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 2, /* c */
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* d */
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* e */
+ 0, 2, 2, 2, 2, 2, 2, 4, 0, 3, 0, 4, 0, 6, 7, 1 /* f */
+};
+
+#define LT (1 << 0)
+#define GT (1 << 1)
+#define GE (1 << 2)
+#define LE (1 << 3)
+#define CS (1 << 4)
+#define HI (1 << 5)
+#define CC (1 << 6)
+#define LS (1 << 7)
+#define EQ (1 << 8)
+#define NE (1 << 9)
+#define RA (1 << 10)
+#define VC (1 << 11)
+#define VS (1 << 12)
+#define NC (1 << 13)
+#define NS (1 << 14)
+
+static const u16 cond_table[] = {
+ /* V C N Z */
+ /* 0 0 0 0 */ (NE | NC | CC | VC | GE | GT | HI),
+ /* 0 0 0 1 */ (EQ | NC | CC | VC | GE | LE | LS),
+ /* 0 0 1 0 */ (NE | NS | CC | VC | LT | LE | HI),
+ /* 0 0 1 1 */ (EQ | NS | CC | VC | LT | LE | LS),
+ /* 0 1 0 0 */ (NE | NC | CS | VC | GE | GT | LS),
+ /* 0 1 0 1 */ (EQ | NC | CS | VC | GE | LE | LS),
+ /* 0 1 1 0 */ (NE | NS | CS | VC | LT | LE | LS),
+ /* 0 1 1 1 */ (EQ | NS | CS | VC | LT | LE | LS),
+ /* 1 0 0 0 */ (NE | NC | CC | VS | LT | LE | HI),
+ /* 1 0 0 1 */ (EQ | NC | CC | VS | LT | LE | LS),
+ /* 1 0 1 0 */ (NE | NS | CC | VS | GE | GT | HI),
+ /* 1 0 1 1 */ (EQ | NS | CC | VS | GE | LE | LS),
+ /* 1 1 0 0 */ (NE | NC | CS | VS | LT | LE | LS),
+ /* 1 1 0 1 */ (EQ | NC | CS | VS | LT | LE | LS),
+ /* 1 1 1 0 */ (NE | NS | CS | VS | GE | GT | LS),
+ /* 1 1 1 1 */ (EQ | NS | CS | VS | GE | LE | LS),
+};
+
+/*
+ * Calculate what the PC will be after executing next instruction
+ */
+static unsigned find_nextpc(struct pt_regs *regs, int *flags)
+{
+ unsigned size;
+ s8 x8;
+ s16 x16;
+ s32 x32;
+ u8 opc, *pc, *sp, *next;
+
+ next = 0;
+ *flags = SINGLESTEP_PCREL;
+
+ pc = (u8 *) regs->pc;
+ sp = (u8 *) (regs + 1);
+ opc = *pc;
+
+ size = mn10300_insn_sizes[opc];
+ if (size > 0) {
+ next = pc + size;
+ } else {
+ switch (opc) {
+ /* Bxx (d8,PC) */
+ case 0xc0 ... 0xca:
+ x8 = 2;
+ if (cond_table[regs->epsw & 0xf] & (1 << (opc & 0xf)))
+ x8 = (s8)pc[1];
+ next = pc + x8;
+ *flags |= SINGLESTEP_BRANCH;
+ break;
+
+ /* JMP (d16,PC) or CALL (d16,PC) */
+ case 0xcc:
+ case 0xcd:
+ READ_WORD16(pc + 1, &x16);
+ next = pc + x16;
+ *flags |= SINGLESTEP_BRANCH;
+ break;
+
+ /* JMP (d32,PC) or CALL (d32,PC) */
+ case 0xdc:
+ case 0xdd:
+ READ_WORD32(pc + 1, &x32);
+ next = pc + x32;
+ *flags |= SINGLESTEP_BRANCH;
+ break;
+
+ /* RETF */
+ case 0xde:
+ next = (u8 *)regs->mdr;
+ *flags &= ~SINGLESTEP_PCREL;
+ *flags |= SINGLESTEP_BRANCH;
+ break;
+
+ /* RET */
+ case 0xdf:
+ sp += pc[2];
+ READ_WORD32(sp, &x32);
+ next = (u8 *)x32;
+ *flags &= ~SINGLESTEP_PCREL;
+ *flags |= SINGLESTEP_BRANCH;
+ break;
+
+ case 0xf0:
+ next = pc + 2;
+ opc = pc[1];
+ if (opc >= 0xf0 && opc <= 0xf7) {
+ /* JMP (An) / CALLS (An) */
+ switch (opc & 3) {
+ case 0:
+ next = (u8 *)regs->a0;
+ break;
+ case 1:
+ next = (u8 *)regs->a1;
+ break;
+ case 2:
+ next = (u8 *)regs->a2;
+ break;
+ case 3:
+ next = (u8 *)regs->a3;
+ break;
+ }
+ *flags &= ~SINGLESTEP_PCREL;
+ *flags |= SINGLESTEP_BRANCH;
+ } else if (opc == 0xfc) {
+ /* RETS */
+ READ_WORD32(sp, &x32);
+ next = (u8 *)x32;
+ *flags &= ~SINGLESTEP_PCREL;
+ *flags |= SINGLESTEP_BRANCH;
+ } else if (opc == 0xfd) {
+ /* RTI */
+ READ_WORD32(sp + 4, &x32);
+ next = (u8 *)x32;
+ *flags &= ~SINGLESTEP_PCREL;
+ *flags |= SINGLESTEP_BRANCH;
+ }
+ break;
+
+ /* potential 3-byte conditional branches */
+ case 0xf8:
+ next = pc + 3;
+ opc = pc[1];
+ if (opc >= 0xe8 && opc <= 0xeb &&
+ (cond_table[regs->epsw & 0xf] &
+ (1 << ((opc & 0xf) + 3)))
+ ) {
+ READ_BYTE(pc+2, &x8);
+ next = pc + x8;
+ *flags |= SINGLESTEP_BRANCH;
+ }
+ break;
+
+ case 0xfa:
+ if (pc[1] == 0xff) {
+ /* CALLS (d16,PC) */
+ READ_WORD16(pc + 2, &x16);
+ next = pc + x16;
+ } else
+ next = pc + 4;
+ *flags |= SINGLESTEP_BRANCH;
+ break;
+
+ case 0xfc:
+ x32 = 6;
+ if (pc[1] == 0xff) {
+ /* CALLS (d32,PC) */
+ READ_WORD32(pc + 2, &x32);
+ }
+ next = pc + x32;
+ *flags |= SINGLESTEP_BRANCH;
+ break;
+ /* LXX (d8,PC) */
+ /* SETLB - loads the next four bytes into the LIR reg */
+ case 0xd0 ... 0xda:
+ case 0xdb:
+ panic("Can't singlestep Lxx/SETLB\n");
+ break;
+ }
+ }
+ return (unsigned)next;
+
+}
+
+/*
+ * set up out of place singlestep of some branching instructions
+ */
+static unsigned __kprobes singlestep_branch_setup(struct pt_regs *regs)
+{
+ u8 opc, *pc, *sp, *next;
+
+ next = NULL;
+ pc = (u8 *) regs->pc;
+ sp = (u8 *) (regs + 1);
+
+ switch (pc[0]) {
+ case 0xc0 ... 0xca: /* Bxx (d8,PC) */
+ case 0xcc: /* JMP (d16,PC) */
+ case 0xdc: /* JMP (d32,PC) */
+ case 0xf8: /* Bxx (d8,PC) 3-byte version */
+ /* don't really need to do anything except cause trap */
+ next = pc;
+ break;
+
+ case 0xcd: /* CALL (d16,PC) */
+ pc[1] = 5;
+ pc[2] = 0;
+ next = pc + 5;
+ break;
+
+ case 0xdd: /* CALL (d32,PC) */
+ pc[1] = 7;
+ pc[2] = 0;
+ pc[3] = 0;
+ pc[4] = 0;
+ next = pc + 7;
+ break;
+
+ case 0xde: /* RETF */
+ next = pc + 3;
+ regs->mdr = (unsigned) next;
+ break;
+
+ case 0xdf: /* RET */
+ sp += pc[2];
+ next = pc + 3;
+ *(unsigned *)sp = (unsigned) next;
+ break;
+
+ case 0xf0:
+ next = pc + 2;
+ opc = pc[1];
+ if (opc >= 0xf0 && opc <= 0xf3) {
+ /* CALLS (An) */
+ /* use CALLS (d16,PC) to avoid mucking with An */
+ pc[0] = 0xfa;
+ pc[1] = 0xff;
+ pc[2] = 4;
+ pc[3] = 0;
+ next = pc + 4;
+ } else if (opc >= 0xf4 && opc <= 0xf7) {
+ /* JMP (An) */
+ next = pc;
+ } else if (opc == 0xfc) {
+ /* RETS */
+ next = pc + 2;
+ *(unsigned *) sp = (unsigned) next;
+ } else if (opc == 0xfd) {
+ /* RTI */
+ next = pc + 2;
+ *(unsigned *)(sp + 4) = (unsigned) next;
+ }
+ break;
+
+ case 0xfa: /* CALLS (d16,PC) */
+ pc[2] = 4;
+ pc[3] = 0;
+ next = pc + 4;
+ break;
+
+ case 0xfc: /* CALLS (d32,PC) */
+ pc[2] = 6;
+ pc[3] = 0;
+ pc[4] = 0;
+ pc[5] = 0;
+ next = pc + 6;
+ break;
+
+ case 0xd0 ... 0xda: /* LXX (d8,PC) */
+ case 0xdb: /* SETLB */
+ panic("Can't singlestep Lxx/SETLB\n");
+ }
+
+ return (unsigned) next;
+}
+
+int __kprobes arch_prepare_kprobe(struct kprobe *p)
+{
+ return 0;
+}
+
+void __kprobes arch_copy_kprobe(struct kprobe *p)
+{
+ memcpy(p->ainsn.insn, p->addr, MAX_INSN_SIZE);
+}
+
+void __kprobes arch_arm_kprobe(struct kprobe *p)
+{
+ *p->addr = BREAKPOINT_INSTRUCTION;
+ flush_icache_range((unsigned long) p->addr,
+ (unsigned long) p->addr + sizeof(kprobe_opcode_t));
+}
+
+void __kprobes arch_disarm_kprobe(struct kprobe *p)
+{
+ mn10300_dcache_flush();
+ mn10300_icache_inv();
+}
+
+void arch_remove_kprobe(struct kprobe *p)
+{
+}
+
+static inline
+void __kprobes disarm_kprobe(struct kprobe *p, struct pt_regs *regs)
+{
+ *p->addr = p->opcode;
+ regs->pc = (unsigned long) p->addr;
+ mn10300_dcache_flush();
+ mn10300_icache_inv();
+}
+
+static inline
+void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
+{
+ unsigned long nextpc;
+
+ current_kprobe_orig_pc = regs->pc;
+ memcpy(current_kprobe_ss_buf, &p->ainsn.insn[0], MAX_INSN_SIZE);
+ regs->pc = (unsigned long) current_kprobe_ss_buf;
+
+ nextpc = find_nextpc(regs, ¤t_kprobe_ss_flags);
+ if (current_kprobe_ss_flags & SINGLESTEP_PCREL)
+ current_kprobe_next_pc =
+ current_kprobe_orig_pc + (nextpc - regs->pc);
+ else
+ current_kprobe_next_pc = nextpc;
+
+ /* branching instructions need special handling */
+ if (current_kprobe_ss_flags & SINGLESTEP_BRANCH)
+ nextpc = singlestep_branch_setup(regs);
+
+ current_kprobe_bp_addr = nextpc;
+
+ *(u8 *) nextpc = BREAKPOINT_INSTRUCTION;
+ mn10300_dcache_flush_range2((unsigned) current_kprobe_ss_buf,
+ sizeof(current_kprobe_ss_buf));
+ mn10300_icache_inv();
+}
+
+static inline int __kprobes kprobe_handler(struct pt_regs *regs)
+{
+ struct kprobe *p;
+ int ret = 0;
+ unsigned int *addr = (unsigned int *) regs->pc;
+
+ /* We're in an interrupt, but this is clear and BUG()-safe. */
+ preempt_disable();
+
+ /* Check we're not actually recursing */
+ if (kprobe_running()) {
+ /* We *are* holding lock here, so this is safe.
+ Disarm the probe we just hit, and ignore it. */
+ p = get_kprobe(addr);
+ if (p) {
+ disarm_kprobe(p, regs);
+ ret = 1;
+ } else {
+ p = current_kprobe;
+ if (p->break_handler && p->break_handler(p, regs))
+ goto ss_probe;
+ }
+ /* If it's not ours, can't be delete race, (we hold lock). */
+ goto no_kprobe;
+ }
+
+ p = get_kprobe(addr);
+ if (!p) {
+ if (*addr != BREAKPOINT_INSTRUCTION) {
+ /* The breakpoint instruction was removed right after
+ * we hit it. Another cpu has removed either a
+ * probepoint or a debugger breakpoint at this address.
+ * In either case, no further handling of this
+ * interrupt is appropriate.
+ */
+ ret = 1;
+ }
+ /* Not one of ours: let kernel handle it */
+ goto no_kprobe;
+ }
+
+ kprobe_status = KPROBE_HIT_ACTIVE;
+ current_kprobe = p;
+ if (p->pre_handler(p, regs)) {
+ /* handler has already set things up, so skip ss setup */
+ return 1;
+ }
+
+ss_probe:
+ prepare_singlestep(p, regs);
+ kprobe_status = KPROBE_HIT_SS;
+ return 1;
+
+no_kprobe:
+ preempt_enable_no_resched();
+ return ret;
+}
+
+/*
+ * Called after single-stepping. p->addr is the address of the
+ * instruction whose first byte has been replaced by the "breakpoint"
+ * instruction. To avoid the SMP problems that can occur when we
+ * temporarily put back the original opcode to single-step, we
+ * single-stepped a copy of the instruction. The address of this
+ * copy is p->ainsn.insn.
+ */
+static void __kprobes resume_execution(struct kprobe *p, struct pt_regs *regs)
+{
+ /* we may need to fixup regs/stack after singlestepping a call insn */
+ if (current_kprobe_ss_flags & SINGLESTEP_BRANCH) {
+ regs->pc = current_kprobe_orig_pc;
+ switch (p->ainsn.insn[0]) {
+ case 0xcd: /* CALL (d16,PC) */
+ *(unsigned *) regs->sp = regs->mdr = regs->pc + 5;
+ break;
+ case 0xdd: /* CALL (d32,PC) */
+ /* fixup mdr and return address on stack */
+ *(unsigned *) regs->sp = regs->mdr = regs->pc + 7;
+ break;
+ case 0xf0:
+ if (p->ainsn.insn[1] >= 0xf0 &&
+ p->ainsn.insn[1] <= 0xf3) {
+ /* CALLS (An) */
+ /* fixup MDR and return address on stack */
+ regs->mdr = regs->pc + 2;
+ *(unsigned *) regs->sp = regs->mdr;
+ }
+ break;
+
+ case 0xfa: /* CALLS (d16,PC) */
+ /* fixup MDR and return address on stack */
+ *(unsigned *) regs->sp = regs->mdr = regs->pc + 4;
+ break;
+
+ case 0xfc: /* CALLS (d32,PC) */
+ /* fixup MDR and return address on stack */
+ *(unsigned *) regs->sp = regs->mdr = regs->pc + 6;
+ break;
+ }
+ }
+
+ regs->pc = current_kprobe_next_pc;
+ current_kprobe_bp_addr = 0;
+}
+
+static inline int __kprobes post_kprobe_handler(struct pt_regs *regs)
+{
+ if (!kprobe_running())
+ return 0;
+
+ if (current_kprobe->post_handler)
+ current_kprobe->post_handler(current_kprobe, regs, 0);
+
+ resume_execution(current_kprobe, regs);
+ reset_current_kprobe();
+ preempt_enable_no_resched();
+ return 1;
+}
+
+/* Interrupts disabled, kprobe_lock held. */
+static inline
+int __kprobes kprobe_fault_handler(struct pt_regs *regs, int trapnr)
+{
+ if (current_kprobe->fault_handler &&
+ current_kprobe->fault_handler(current_kprobe, regs, trapnr))
+ return 1;
+
+ if (kprobe_status & KPROBE_HIT_SS) {
+ resume_execution(current_kprobe, regs);
+ reset_current_kprobe();
+ preempt_enable_no_resched();
+ }
+ return 0;
+}
+
+/*
+ * Wrapper routine to for handling exceptions.
+ */
+int __kprobes kprobe_exceptions_notify(struct notifier_block *self,
+ unsigned long val, void *data)
+{
+ struct die_args *args = data;
+
+ switch (val) {
+ case DIE_BREAKPOINT:
+ if (current_kprobe_bp_addr != args->regs->pc) {
+ if (kprobe_handler(args->regs))
+ return NOTIFY_STOP;
+ } else {
+ if (post_kprobe_handler(args->regs))
+ return NOTIFY_STOP;
+ }
+ break;
+ case DIE_GPF:
+ if (kprobe_running() &&
+ kprobe_fault_handler(args->regs, args->trapnr))
+ return NOTIFY_STOP;
+ break;
+ default:
+ break;
+ }
+ return NOTIFY_DONE;
+}
+
+/* Jprobes support. */
+static struct pt_regs jprobe_saved_regs;
+static struct pt_regs *jprobe_saved_regs_location;
+static kprobe_opcode_t jprobe_saved_stack[MAX_STACK_SIZE];
+
+int __kprobes setjmp_pre_handler(struct kprobe *p, struct pt_regs *regs)
+{
+ struct jprobe *jp = container_of(p, struct jprobe, kp);
+
+ jprobe_saved_regs_location = regs;
+ memcpy(&jprobe_saved_regs, regs, sizeof(struct pt_regs));
+
+ /* Save a whole stack frame, this gets arguments
+ * pushed onto the stack after using up all the
+ * arg registers.
+ */
+ memcpy(&jprobe_saved_stack, regs + 1, sizeof(jprobe_saved_stack));
+
+ /* setup return addr to the jprobe handler routine */
+ regs->pc = (unsigned long) jp->entry;
+ return 1;
+}
+
+void __kprobes jprobe_return(void)
+{
+ void *orig_sp = jprobe_saved_regs_location + 1;
+
+ preempt_enable_no_resched();
+ asm volatile(" mov %0,sp\n"
+ ".globl jprobe_return_bp_addr\n"
+ "jprobe_return_bp_addr:\n\t"
+ " .byte 0xff\n"
+ : : "d" (orig_sp));
+}
+
+extern void jprobe_return_bp_addr(void);
+
+int __kprobes longjmp_break_handler(struct kprobe *p, struct pt_regs *regs)
+{
+ u8 *addr = (u8 *) regs->pc;
+
+ if (addr == (u8 *) jprobe_return_bp_addr) {
+ if (jprobe_saved_regs_location != regs) {
+ printk(KERN_ERR"JPROBE:"
+ " Current regs (%p) does not match saved regs"
+ " (%p).\n",
+ regs, jprobe_saved_regs_location);
+ BUG();
+ }
+
+ /* Restore old register state.
+ */
+ memcpy(regs, &jprobe_saved_regs, sizeof(struct pt_regs));
+
+ memcpy(regs + 1, &jprobe_saved_stack,
+ sizeof(jprobe_saved_stack));
+ return 1;
+ }
+ return 0;
+}
+
+int __init arch_init_kprobes(void)
+{
+ return 0;
+}
--- /dev/null
+/* MN10300 Kernel thread trampoline function
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by Mark Salter (msalter@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+ .text
+
+###############################################################################
+#
+# kernel_thread_helper - trampoline for kernel_thread()
+#
+# On entry:
+# A2 = address of function to call
+# D2 = function argument
+#
+###############################################################################
+ .globl kernel_thread_helper
+ .type kernel_thread_helper,@function
+kernel_thread_helper:
+ mov do_exit,d1
+ mov d1,(sp)
+ mov d1,mdr
+ mov d2,d0
+ jmp (a2)
+
+ .size kernel_thread_helper,.-kernel_thread_helper
--- /dev/null
+/* Debugging stuff for the MN10300-based processors
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/sched.h>
+#include <asm/serial-regs.h>
+
+#undef MN10300_CONSOLE_ON_SERIO
+
+/*
+ * write a string directly through one of the serial ports on-board the MN10300
+ */
+#ifdef MN10300_CONSOLE_ON_SERIO
+void debug_to_serial_mnser(const char *p, int n)
+{
+ char ch;
+
+ for (; n > 0; n--) {
+ ch = *p++;
+
+#if MN10300_CONSOLE_ON_SERIO == 0
+ while (SC0STR & (SC01STR_TBF)) continue;
+ SC0TXB = ch;
+ while (SC0STR & (SC01STR_TBF)) continue;
+ if (ch == 0x0a) {
+ SC0TXB = 0x0d;
+ while (SC0STR & (SC01STR_TBF)) continue;
+ }
+
+#elif MN10300_CONSOLE_ON_SERIO == 1
+ while (SC1STR & (SC01STR_TBF)) continue;
+ SC1TXB = ch;
+ while (SC1STR & (SC01STR_TBF)) continue;
+ if (ch == 0x0a) {
+ SC1TXB = 0x0d;
+ while (SC1STR & (SC01STR_TBF)) continue;
+ }
+
+#elif MN10300_CONSOLE_ON_SERIO == 2
+ while (SC2STR & (SC2STR_TBF)) continue;
+ SC2TXB = ch;
+ while (SC2STR & (SC2STR_TBF)) continue;
+ if (ch == 0x0a) {
+ SC2TXB = 0x0d;
+ while (SC2STR & (SC2STR_TBF)) continue;
+ }
+
+#endif
+ }
+}
+#endif
+
--- /dev/null
+###############################################################################
+#
+# Virtual DMA driver for MN10300 serial ports
+#
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Written by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+###############################################################################
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/page.h>
+#include <asm/smp.h>
+#include <asm/cpu-regs.h>
+#include <asm/frame.inc>
+#include <asm/timer-regs.h>
+#include <asm/proc/cache.h>
+#include <asm/unit/timex.h>
+#include "mn10300-serial.h"
+
+#define SCxCTR 0x00
+#define SCxICR 0x04
+#define SCxTXB 0x08
+#define SCxRXB 0x09
+#define SCxSTR 0x0c
+#define SCxTIM 0x0d
+
+ .text
+
+###############################################################################
+#
+# serial port interrupt virtual DMA entry point
+# - intended to run at interrupt priority 1 (not affected by local_irq_disable)
+#
+###############################################################################
+ .balign L1_CACHE_BYTES
+ENTRY(mn10300_serial_vdma_interrupt)
+ or EPSW_IE,psw # permit overriding by
+ # debugging interrupts
+ movm [d2,d3,a2,a3,exreg0],(sp)
+
+ movhu (IAGR),a2 # see if which interrupt is
+ # pending
+ and IAGR_GN,a2
+ add a2,a2
+ add mn10300_serial_int_tbl,a2
+
+ mov (a2+),a3
+ mov (__iobase,a3),e2
+ mov (a2),a2
+ jmp (a2)
+
+###############################################################################
+#
+# serial port receive interrupt virtual DMA entry point
+# - intended to run at interrupt priority 1 (not affected by local_irq_disable)
+# - stores data/status byte pairs in the ring buffer
+# - induces a scheduler tick timer interrupt when done, which we then subvert
+# on entry:
+# A3 struct mn10300_serial_port *
+# E2 I/O port base
+#
+###############################################################################
+ENTRY(mn10300_serial_vdma_rx_handler)
+ mov (__rx_icr,a3),e3
+ mov GxICR_DETECT,d2
+ movbu d2,(e3) # ACK the interrupt
+ movhu (e3),d2 # flush
+
+ mov (__rx_inp,a3),d3
+ mov d3,a2
+ add 2,d3
+ and MNSC_BUFFER_SIZE-1,d3
+ mov (__rx_outp,a3),d2
+ cmp d3,d2
+ beq mnsc_vdma_rx_overflow
+
+ mov (__rx_buffer,a3),d2
+ add d2,a2
+ movhu (SCxSTR,e2),d2
+ movbu d2,(1,a2)
+ movbu (SCxRXB,e2),d2
+ movbu d2,(a2)
+ mov d3,(__rx_inp,a3)
+ bset MNSCx_RX_AVAIL,(__intr_flags,a3)
+
+mnsc_vdma_rx_done:
+ mov (__tm_icr,a3),a2
+ mov GxICR_LEVEL_6|GxICR_ENABLE|GxICR_REQUEST|GxICR_DETECT,d2
+ movhu d2,(a2) # request a slow interrupt
+ movhu (a2),d2 # flush
+
+ movm (sp),[d2,d3,a2,a3,exreg0]
+ rti
+
+mnsc_vdma_rx_overflow:
+ bset MNSCx_RX_OVERF,(__intr_flags,a3)
+ bra mnsc_vdma_rx_done
+
+###############################################################################
+#
+# serial port transmit interrupt virtual DMA entry point
+# - intended to run at interrupt priority 1 (not affected by local_irq_disable)
+# - retrieves data bytes from the ring buffer and passes them to the serial port
+# - induces a scheduler tick timer interrupt when done, which we then subvert
+# A3 struct mn10300_serial_port *
+# E2 I/O port base
+#
+###############################################################################
+ .balign L1_CACHE_BYTES
+ENTRY(mn10300_serial_vdma_tx_handler)
+ mov (__tx_icr,a3),e3
+ mov GxICR_DETECT,d2
+ movbu d2,(e3) # ACK the interrupt
+ movhu (e3),d2 # flush
+
+ btst 0x01,(__tx_break,a3) # handle transmit break request
+ bne mnsc_vdma_tx_break
+
+ movbu (SCxSTR,e2),d2 # don't try and transmit a char if the
+ # buffer is not empty
+ btst SC01STR_TBF,d2 # (may have tried to jumpstart)
+ bne mnsc_vdma_tx_noint
+
+ movbu (__tx_xchar,a3),d2 # handle hi-pri XON/XOFF
+ or d2,d2
+ bne mnsc_vdma_tx_xchar
+
+ mov (__tx_info_buffer,a3),a2 # get the uart_info struct for Tx
+ mov (__xmit_tail,a2),d3
+ mov (__xmit_head,a2),d2
+ cmp d3,d2
+ beq mnsc_vdma_tx_empty
+
+ mov (__xmit_buffer,a2),d2 # get a char from the buffer and
+ # transmit it
+ movbu (d3,d2),d2
+ movbu d2,(SCxTXB,e2) # Tx
+
+ inc d3 # advance the buffer pointer
+ and __UART_XMIT_SIZE-1,d3
+ mov (__xmit_head,a2),d2
+ mov d3,(__xmit_tail,a2)
+
+ sub d3,d2 # see if we've written everything
+ beq mnsc_vdma_tx_empty
+
+ and __UART_XMIT_SIZE-1,d2 # see if we just made a hole
+ cmp __UART_XMIT_SIZE-2,d2
+ beq mnsc_vdma_tx_made_hole
+
+mnsc_vdma_tx_done:
+ mov (__tm_icr,a3),a2
+ mov GxICR_LEVEL_6|GxICR_ENABLE|GxICR_REQUEST|GxICR_DETECT,d2
+ movhu d2,(a2) # request a slow interrupt
+ movhu (a2),d2 # flush
+
+mnsc_vdma_tx_noint:
+ movm (sp),[d2,d3,a2,a3,exreg0]
+ rti
+
+mnsc_vdma_tx_empty:
+ mov +(GxICR_LEVEL_1|GxICR_DETECT),d2
+ movhu d2,(e3) # disable the interrupt
+ movhu (e3),d2 # flush
+
+ bset MNSCx_TX_EMPTY,(__intr_flags,a3)
+ bra mnsc_vdma_tx_done
+
+mnsc_vdma_tx_break:
+ movhu (SCxCTR,e2),d2 # turn on break mode
+ or SC01CTR_BKE,d2
+ movhu d2,(SCxCTR,e2)
+ mov +(GxICR_LEVEL_1|GxICR_DETECT),d2
+ movhu d2,(e3) # disable transmit interrupts on this
+ # channel
+ movhu (e3),d2 # flush
+ bra mnsc_vdma_tx_noint
+
+mnsc_vdma_tx_xchar:
+ bclr 0xff,(__tx_xchar,a3)
+ movbu d2,(SCxTXB,e2)
+ bra mnsc_vdma_tx_done
+
+mnsc_vdma_tx_made_hole:
+ bset MNSCx_TX_SPACE,(__intr_flags,a3)
+ bra mnsc_vdma_tx_done
--- /dev/null
+/* MN10300 On-chip serial port UART driver
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+static const char serial_name[] = "MN10300 Serial driver";
+static const char serial_version[] = "mn10300_serial-1.0";
+static const char serial_revdate[] = "2007-11-06";
+
+#if defined(CONFIG_MN10300_TTYSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/serial.h>
+#include <linux/circ_buf.h>
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/major.h>
+#include <linux/string.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/bitops.h>
+#include <asm/serial-regs.h>
+#include <asm/unit/timex.h>
+#include "mn10300-serial.h"
+
+static inline __attribute__((format(printf, 1, 2)))
+void no_printk(const char *fmt, ...)
+{
+}
+
+#define kenter(FMT, ...) \
+ printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__)
+#define _enter(FMT, ...) \
+ no_printk(KERN_DEBUG "-->%s(" FMT ")\n", __func__, ##__VA_ARGS__)
+#define kdebug(FMT, ...) \
+ printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__)
+#define _debug(FMT, ...) \
+ no_printk(KERN_DEBUG "--- " FMT "\n", ##__VA_ARGS__)
+#define kproto(FMT, ...) \
+ printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__)
+#define _proto(FMT, ...) \
+ no_printk(KERN_DEBUG "### MNSERIAL " FMT " ###\n", ##__VA_ARGS__)
+
+#define NR_UARTS 3
+
+#ifdef CONFIG_MN10300_TTYSM_CONSOLE
+static void mn10300_serial_console_write(struct console *co,
+ const char *s, unsigned count);
+static int __init mn10300_serial_console_setup(struct console *co,
+ char *options);
+
+static struct uart_driver mn10300_serial_driver;
+static struct console mn10300_serial_console = {
+ .name = "ttySM",
+ .write = mn10300_serial_console_write,
+ .device = uart_console_device,
+ .setup = mn10300_serial_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &mn10300_serial_driver,
+};
+#endif
+
+static struct uart_driver mn10300_serial_driver = {
+ .owner = NULL,
+ .driver_name = "mn10300-serial",
+ .dev_name = "ttySM",
+ .major = TTY_MAJOR,
+ .minor = 128,
+ .nr = NR_UARTS,
+#ifdef CONFIG_MN10300_TTYSM_CONSOLE
+ .cons = &mn10300_serial_console,
+#endif
+};
+
+static unsigned int mn10300_serial_tx_empty(struct uart_port *);
+static void mn10300_serial_set_mctrl(struct uart_port *, unsigned int mctrl);
+static unsigned int mn10300_serial_get_mctrl(struct uart_port *);
+static void mn10300_serial_stop_tx(struct uart_port *);
+static void mn10300_serial_start_tx(struct uart_port *);
+static void mn10300_serial_send_xchar(struct uart_port *, char ch);
+static void mn10300_serial_stop_rx(struct uart_port *);
+static void mn10300_serial_enable_ms(struct uart_port *);
+static void mn10300_serial_break_ctl(struct uart_port *, int ctl);
+static int mn10300_serial_startup(struct uart_port *);
+static void mn10300_serial_shutdown(struct uart_port *);
+static void mn10300_serial_set_termios(struct uart_port *,
+ struct ktermios *new,
+ struct ktermios *old);
+static const char *mn10300_serial_type(struct uart_port *);
+static void mn10300_serial_release_port(struct uart_port *);
+static int mn10300_serial_request_port(struct uart_port *);
+static void mn10300_serial_config_port(struct uart_port *, int);
+static int mn10300_serial_verify_port(struct uart_port *,
+ struct serial_struct *);
+
+static const struct uart_ops mn10300_serial_ops = {
+ .tx_empty = mn10300_serial_tx_empty,
+ .set_mctrl = mn10300_serial_set_mctrl,
+ .get_mctrl = mn10300_serial_get_mctrl,
+ .stop_tx = mn10300_serial_stop_tx,
+ .start_tx = mn10300_serial_start_tx,
+ .send_xchar = mn10300_serial_send_xchar,
+ .stop_rx = mn10300_serial_stop_rx,
+ .enable_ms = mn10300_serial_enable_ms,
+ .break_ctl = mn10300_serial_break_ctl,
+ .startup = mn10300_serial_startup,
+ .shutdown = mn10300_serial_shutdown,
+ .set_termios = mn10300_serial_set_termios,
+ .type = mn10300_serial_type,
+ .release_port = mn10300_serial_release_port,
+ .request_port = mn10300_serial_request_port,
+ .config_port = mn10300_serial_config_port,
+ .verify_port = mn10300_serial_verify_port,
+};
+
+static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id);
+
+/*
+ * the first on-chip serial port: ttySM0 (aka SIF0)
+ */
+#ifdef CONFIG_MN10300_TTYSM0
+struct mn10300_serial_port mn10300_serial_port_sif0 = {
+ .uart.ops = &mn10300_serial_ops,
+ .uart.membase = (void __iomem *) &SC0CTR,
+ .uart.mapbase = (unsigned long) &SC0CTR,
+ .uart.iotype = UPIO_MEM,
+ .uart.irq = 0,
+ .uart.uartclk = 0, /* MN10300_IOCLK, */
+ .uart.fifosize = 1,
+ .uart.flags = UPF_BOOT_AUTOCONF,
+ .uart.line = 0,
+ .uart.type = PORT_MN10300,
+ .uart.lock =
+ __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif0.uart.lock),
+ .name = "ttySM0",
+ ._iobase = &SC0CTR,
+ ._control = &SC0CTR,
+ ._status = (volatile u8 *) &SC0STR,
+ ._intr = &SC0ICR,
+ ._rxb = &SC0RXB,
+ ._txb = &SC0TXB,
+ .rx_name = "ttySM0/Rx",
+ .tx_name = "ttySM0/Tx",
+#ifdef CONFIG_MN10300_TTYSM0_TIMER8
+ .tm_name = "ttySM0/Timer8",
+ ._tmxmd = &TM8MD,
+ ._tmxbr = &TM8BR,
+ ._tmicr = &TM8ICR,
+ .tm_irq = TM8IRQ,
+ .div_timer = MNSCx_DIV_TIMER_16BIT,
+#else /* CONFIG_MN10300_TTYSM0_TIMER2 */
+ .tm_name = "ttySM0/Timer2",
+ ._tmxmd = &TM2MD,
+ ._tmxbr = (volatile u16 *) &TM2BR,
+ ._tmicr = &TM2ICR,
+ .tm_irq = TM2IRQ,
+ .div_timer = MNSCx_DIV_TIMER_8BIT,
+#endif
+ .rx_irq = SC0RXIRQ,
+ .tx_irq = SC0TXIRQ,
+ .rx_icr = &GxICR(SC0RXIRQ),
+ .tx_icr = &GxICR(SC0TXIRQ),
+ .clock_src = MNSCx_CLOCK_SRC_IOCLK,
+ .options = 0,
+#ifdef CONFIG_GDBSTUB_ON_TTYSM0
+ .gdbstub = 1,
+#endif
+};
+#endif /* CONFIG_MN10300_TTYSM0 */
+
+/*
+ * the second on-chip serial port: ttySM1 (aka SIF1)
+ */
+#ifdef CONFIG_MN10300_TTYSM1
+struct mn10300_serial_port mn10300_serial_port_sif1 = {
+ .uart.ops = &mn10300_serial_ops,
+ .uart.membase = (void __iomem *) &SC1CTR,
+ .uart.mapbase = (unsigned long) &SC1CTR,
+ .uart.iotype = UPIO_MEM,
+ .uart.irq = 0,
+ .uart.uartclk = 0, /* MN10300_IOCLK, */
+ .uart.fifosize = 1,
+ .uart.flags = UPF_BOOT_AUTOCONF,
+ .uart.line = 1,
+ .uart.type = PORT_MN10300,
+ .uart.lock =
+ __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif1.uart.lock),
+ .name = "ttySM1",
+ ._iobase = &SC1CTR,
+ ._control = &SC1CTR,
+ ._status = (volatile u8 *) &SC1STR,
+ ._intr = &SC1ICR,
+ ._rxb = &SC1RXB,
+ ._txb = &SC1TXB,
+ .rx_name = "ttySM1/Rx",
+ .tx_name = "ttySM1/Tx",
+#ifdef CONFIG_MN10300_TTYSM1_TIMER9
+ .tm_name = "ttySM1/Timer9",
+ ._tmxmd = &TM9MD,
+ ._tmxbr = &TM9BR,
+ ._tmicr = &TM9ICR,
+ .tm_irq = TM9IRQ,
+ .div_timer = MNSCx_DIV_TIMER_16BIT,
+#else /* CONFIG_MN10300_TTYSM1_TIMER3 */
+ .tm_name = "ttySM1/Timer3",
+ ._tmxmd = &TM3MD,
+ ._tmxbr = (volatile u16 *) &TM3BR,
+ ._tmicr = &TM3ICR,
+ .tm_irq = TM3IRQ,
+ .div_timer = MNSCx_DIV_TIMER_8BIT,
+#endif
+ .rx_irq = SC1RXIRQ,
+ .tx_irq = SC1TXIRQ,
+ .rx_icr = &GxICR(SC1RXIRQ),
+ .tx_icr = &GxICR(SC1TXIRQ),
+ .clock_src = MNSCx_CLOCK_SRC_IOCLK,
+ .options = 0,
+#ifdef CONFIG_GDBSTUB_ON_TTYSM1
+ .gdbstub = 1,
+#endif
+};
+#endif /* CONFIG_MN10300_TTYSM1 */
+
+/*
+ * the third on-chip serial port: ttySM2 (aka SIF2)
+ */
+#ifdef CONFIG_MN10300_TTYSM2
+struct mn10300_serial_port mn10300_serial_port_sif2 = {
+ .uart.ops = &mn10300_serial_ops,
+ .uart.membase = (void __iomem *) &SC2CTR,
+ .uart.mapbase = (unsigned long) &SC2CTR,
+ .uart.iotype = UPIO_MEM,
+ .uart.irq = 0,
+ .uart.uartclk = 0, /* MN10300_IOCLK, */
+ .uart.fifosize = 1,
+ .uart.flags = UPF_BOOT_AUTOCONF,
+ .uart.line = 2,
+#ifdef CONFIG_MN10300_TTYSM2_CTS
+ .uart.type = PORT_MN10300_CTS,
+#else
+ .uart.type = PORT_MN10300,
+#endif
+ .uart.lock =
+ __SPIN_LOCK_UNLOCKED(mn10300_serial_port_sif2.uart.lock),
+ .name = "ttySM2",
+ .rx_name = "ttySM2/Rx",
+ .tx_name = "ttySM2/Tx",
+ .tm_name = "ttySM2/Timer10",
+ ._iobase = &SC2CTR,
+ ._control = &SC2CTR,
+ ._status = &SC2STR,
+ ._intr = &SC2ICR,
+ ._rxb = &SC2RXB,
+ ._txb = &SC2TXB,
+ ._tmxmd = &TM10MD,
+ ._tmxbr = &TM10BR,
+ ._tmicr = &TM10ICR,
+ .tm_irq = TM10IRQ,
+ .div_timer = MNSCx_DIV_TIMER_16BIT,
+ .rx_irq = SC2RXIRQ,
+ .tx_irq = SC2TXIRQ,
+ .rx_icr = &GxICR(SC2RXIRQ),
+ .tx_icr = &GxICR(SC2TXIRQ),
+ .clock_src = MNSCx_CLOCK_SRC_IOCLK,
+#ifdef CONFIG_MN10300_TTYSM2_CTS
+ .options = MNSCx_OPT_CTS,
+#else
+ .options = 0,
+#endif
+#ifdef CONFIG_GDBSTUB_ON_TTYSM2
+ .gdbstub = 1,
+#endif
+};
+#endif /* CONFIG_MN10300_TTYSM2 */
+
+
+/*
+ * list of available serial ports
+ */
+struct mn10300_serial_port *mn10300_serial_ports[NR_UARTS + 1] = {
+#ifdef CONFIG_MN10300_TTYSM0
+ [0] = &mn10300_serial_port_sif0,
+#endif
+#ifdef CONFIG_MN10300_TTYSM1
+ [1] = &mn10300_serial_port_sif1,
+#endif
+#ifdef CONFIG_MN10300_TTYSM2
+ [2] = &mn10300_serial_port_sif2,
+#endif
+ [NR_UARTS] = NULL,
+};
+
+
+/*
+ * we abuse the serial ports' baud timers' interrupt lines to get the ability
+ * to deliver interrupts to userspace as we use the ports' interrupt lines to
+ * do virtual DMA on account of the ports having no hardware FIFOs
+ *
+ * we can generate an interrupt manually in the assembly stubs by writing to
+ * the enable and detect bits in the interrupt control register, so all we need
+ * to do here is disable the interrupt line
+ *
+ * note that we can't just leave the line enabled as the baud rate timer *also*
+ * generates interrupts
+ */
+static void mn10300_serial_mask_ack(unsigned int irq)
+{
+ u16 tmp;
+ GxICR(irq) = GxICR_LEVEL_6;
+ tmp = GxICR(irq); /* flush write buffer */
+}
+
+static void mn10300_serial_nop(unsigned int irq)
+{
+}
+
+static struct irq_chip mn10300_serial_pic = {
+ .name = "mnserial",
+ .ack = mn10300_serial_mask_ack,
+ .mask = mn10300_serial_mask_ack,
+ .mask_ack = mn10300_serial_mask_ack,
+ .unmask = mn10300_serial_nop,
+ .end = mn10300_serial_nop,
+};
+
+
+/*
+ * serial virtual DMA interrupt jump table
+ */
+struct mn10300_serial_int mn10300_serial_int_tbl[NR_IRQS];
+
+static void mn10300_serial_dis_tx_intr(struct mn10300_serial_port *port)
+{
+ u16 x;
+ *port->tx_icr = GxICR_LEVEL_1 | GxICR_DETECT;
+ x = *port->tx_icr;
+}
+
+static void mn10300_serial_en_tx_intr(struct mn10300_serial_port *port)
+{
+ u16 x;
+ *port->tx_icr = GxICR_LEVEL_1 | GxICR_ENABLE;
+ x = *port->tx_icr;
+}
+
+static void mn10300_serial_dis_rx_intr(struct mn10300_serial_port *port)
+{
+ u16 x;
+ *port->rx_icr = GxICR_LEVEL_1 | GxICR_DETECT;
+ x = *port->rx_icr;
+}
+
+/*
+ * multi-bit equivalent of test_and_clear_bit()
+ */
+static int mask_test_and_clear(volatile u8 *ptr, u8 mask)
+{
+ u32 epsw;
+ asm volatile(" bclr %1,(%2) \n"
+ " mov epsw,%0 \n"
+ : "=d"(epsw) : "d"(mask), "a"(ptr));
+ return !(epsw & EPSW_FLAG_Z);
+}
+
+/*
+ * receive chars from the ring buffer for this serial port
+ * - must do break detection here (not done in the UART)
+ */
+static void mn10300_serial_receive_interrupt(struct mn10300_serial_port *port)
+{
+ struct uart_icount *icount = &port->uart.icount;
+ struct tty_struct *tty = port->uart.info->tty;
+ unsigned ix;
+ int count;
+ u8 st, ch, push, status, overrun;
+
+ _enter("%s", port->name);
+
+ push = 0;
+
+ count = CIRC_CNT(port->rx_inp, port->rx_outp, MNSC_BUFFER_SIZE);
+ count = tty_buffer_request_room(tty, count);
+ if (count == 0) {
+ if (!tty->low_latency)
+ tty_flip_buffer_push(tty);
+ return;
+ }
+
+try_again:
+ /* pull chars out of the hat */
+ ix = port->rx_outp;
+ if (ix == port->rx_inp) {
+ if (push && !tty->low_latency)
+ tty_flip_buffer_push(tty);
+ return;
+ }
+
+ ch = port->rx_buffer[ix++];
+ st = port->rx_buffer[ix++];
+ smp_rmb();
+ port->rx_outp = ix & (MNSC_BUFFER_SIZE - 1);
+ port->uart.icount.rx++;
+
+ st &= SC01STR_FEF | SC01STR_PEF | SC01STR_OEF;
+ status = 0;
+ overrun = 0;
+
+ /* the UART doesn't detect BREAK, so we have to do that ourselves
+ * - it starts as a framing error on a NUL character
+ * - then we count another two NUL characters before issuing TTY_BREAK
+ * - then we end on a normal char or one that has all the bottom bits
+ * zero and the top bits set
+ */
+ switch (port->rx_brk) {
+ case 0:
+ /* not breaking at the moment */
+ break;
+
+ case 1:
+ if (st & SC01STR_FEF && ch == 0) {
+ port->rx_brk = 2;
+ goto try_again;
+ }
+ goto not_break;
+
+ case 2:
+ if (st & SC01STR_FEF && ch == 0) {
+ port->rx_brk = 3;
+ _proto("Rx Break Detected");
+ icount->brk++;
+ if (uart_handle_break(&port->uart))
+ goto ignore_char;
+ status |= 1 << TTY_BREAK;
+ goto insert;
+ }
+ goto not_break;
+
+ default:
+ if (st & (SC01STR_FEF | SC01STR_PEF | SC01STR_OEF))
+ goto try_again; /* still breaking */
+
+ port->rx_brk = 0; /* end of the break */
+
+ switch (ch) {
+ case 0xFF:
+ case 0xFE:
+ case 0xFC:
+ case 0xF8:
+ case 0xF0:
+ case 0xE0:
+ case 0xC0:
+ case 0x80:
+ case 0x00:
+ /* discard char at probable break end */
+ goto try_again;
+ }
+ break;
+ }
+
+process_errors:
+ /* handle framing error */
+ if (st & SC01STR_FEF) {
+ if (ch == 0) {
+ /* framing error with NUL char is probably a BREAK */
+ port->rx_brk = 1;
+ goto try_again;
+ }
+
+ _proto("Rx Framing Error");
+ icount->frame++;
+ status |= 1 << TTY_FRAME;
+ }
+
+ /* handle parity error */
+ if (st & SC01STR_PEF) {
+ _proto("Rx Parity Error");
+ icount->parity++;
+ status = TTY_PARITY;
+ }
+
+ /* handle normal char */
+ if (status == 0) {
+ if (uart_handle_sysrq_char(&port->uart, ch))
+ goto ignore_char;
+ status = (1 << TTY_NORMAL);
+ }
+
+ /* handle overrun error */
+ if (st & SC01STR_OEF) {
+ if (port->rx_brk)
+ goto try_again;
+
+ _proto("Rx Overrun Error");
+ icount->overrun++;
+ overrun = 1;
+ }
+
+insert:
+ status &= port->uart.read_status_mask;
+
+ if (!overrun && !(status & port->uart.ignore_status_mask)) {
+ int flag;
+
+ if (status & (1 << TTY_BREAK))
+ flag = TTY_BREAK;
+ else if (status & (1 << TTY_PARITY))
+ flag = TTY_PARITY;
+ else if (status & (1 << TTY_FRAME))
+ flag = TTY_FRAME;
+ else
+ flag = TTY_NORMAL;
+
+ tty_insert_flip_char(tty, ch, flag);
+ }
+
+ /* overrun is special, since it's reported immediately, and doesn't
+ * affect the current character
+ */
+ if (overrun)
+ tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+
+ count--;
+ if (count <= 0) {
+ if (!tty->low_latency)
+ tty_flip_buffer_push(tty);
+ return;
+ }
+
+ignore_char:
+ push = 1;
+ goto try_again;
+
+not_break:
+ port->rx_brk = 0;
+ goto process_errors;
+}
+
+/*
+ * handle an interrupt from the serial transmission "virtual DMA" driver
+ * - note: the interrupt routine will disable its own interrupts when the Tx
+ * buffer is empty
+ */
+static void mn10300_serial_transmit_interrupt(struct mn10300_serial_port *port)
+{
+ _enter("%s", port->name);
+
+ if (uart_tx_stopped(&port->uart) ||
+ uart_circ_empty(&port->uart.info->xmit))
+ mn10300_serial_dis_tx_intr(port);
+
+ if (uart_circ_chars_pending(&port->uart.info->xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(&port->uart);
+}
+
+/*
+ * deal with a change in the status of the CTS line
+ */
+static void mn10300_serial_cts_changed(struct mn10300_serial_port *port, u8 st)
+{
+ u16 ctr;
+
+ port->tx_cts = st;
+ port->uart.icount.cts++;
+
+ /* flip the CTS state selector flag to interrupt when it changes
+ * back */
+ ctr = *port->_control;
+ ctr ^= SC2CTR_TWS;
+ *port->_control = ctr;
+
+ uart_handle_cts_change(&port->uart, st & SC2STR_CTS);
+ wake_up_interruptible(&port->uart.info->delta_msr_wait);
+}
+
+/*
+ * handle a virtual interrupt generated by the lower level "virtual DMA"
+ * routines (irq is the baud timer interrupt)
+ */
+static irqreturn_t mn10300_serial_interrupt(int irq, void *dev_id)
+{
+ struct mn10300_serial_port *port = dev_id;
+ u8 st;
+
+ spin_lock(&port->uart.lock);
+
+ if (port->intr_flags) {
+ _debug("INT %s: %x", port->name, port->intr_flags);
+
+ if (mask_test_and_clear(&port->intr_flags, MNSCx_RX_AVAIL))
+ mn10300_serial_receive_interrupt(port);
+
+ if (mask_test_and_clear(&port->intr_flags,
+ MNSCx_TX_SPACE | MNSCx_TX_EMPTY))
+ mn10300_serial_transmit_interrupt(port);
+ }
+
+ /* the only modem control line amongst the whole lot is CTS on
+ * serial port 2 */
+ if (port->type == PORT_MN10300_CTS) {
+ st = *port->_status;
+ if ((port->tx_cts ^ st) & SC2STR_CTS)
+ mn10300_serial_cts_changed(port, st);
+ }
+
+ spin_unlock(&port->uart.lock);
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * return indication of whether the hardware transmit buffer is empty
+ */
+static unsigned int mn10300_serial_tx_empty(struct uart_port *_port)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ _enter("%s", port->name);
+
+ return (*port->_status & (SC01STR_TXF | SC01STR_TBF)) ?
+ 0 : TIOCSER_TEMT;
+}
+
+/*
+ * set the modem control lines (we don't have any)
+ */
+static void mn10300_serial_set_mctrl(struct uart_port *_port,
+ unsigned int mctrl)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ _enter("%s,%x", port->name, mctrl);
+}
+
+/*
+ * get the modem control line statuses
+ */
+static unsigned int mn10300_serial_get_mctrl(struct uart_port *_port)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ _enter("%s", port->name);
+
+ if (port->type == PORT_MN10300_CTS && !(*port->_status & SC2STR_CTS))
+ return TIOCM_CAR | TIOCM_DSR;
+
+ return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR;
+}
+
+/*
+ * stop transmitting characters
+ */
+static void mn10300_serial_stop_tx(struct uart_port *_port)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ _enter("%s", port->name);
+
+ /* disable the virtual DMA */
+ mn10300_serial_dis_tx_intr(port);
+}
+
+/*
+ * start transmitting characters
+ * - jump-start transmission if it has stalled
+ * - enable the serial Tx interrupt (used by the virtual DMA controller)
+ * - force an interrupt to happen if necessary
+ */
+static void mn10300_serial_start_tx(struct uart_port *_port)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ u16 x;
+
+ _enter("%s{%lu}",
+ port->name,
+ CIRC_CNT(&port->uart.info->xmit.head,
+ &port->uart.info->xmit.tail,
+ UART_XMIT_SIZE));
+
+ /* kick the virtual DMA controller */
+ x = *port->tx_icr;
+ x |= GxICR_ENABLE;
+
+ if (*port->_status & SC01STR_TBF)
+ x &= ~(GxICR_REQUEST | GxICR_DETECT);
+ else
+ x |= GxICR_REQUEST | GxICR_DETECT;
+
+ _debug("CTR=%04hx ICR=%02hx STR=%04x TMD=%02hx TBR=%04hx ICR=%04hx",
+ *port->_control, *port->_intr, *port->_status,
+ *port->_tmxmd, *port->_tmxbr, *port->tx_icr);
+
+ *port->tx_icr = x;
+ x = *port->tx_icr;
+}
+
+/*
+ * transmit a high-priority XON/XOFF character
+ */
+static void mn10300_serial_send_xchar(struct uart_port *_port, char ch)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ _enter("%s,%02x", port->name, ch);
+
+ if (likely(port->gdbstub)) {
+ port->tx_xchar = ch;
+ if (ch)
+ mn10300_serial_en_tx_intr(port);
+ }
+}
+
+/*
+ * stop receiving characters
+ * - called whilst the port is being closed
+ */
+static void mn10300_serial_stop_rx(struct uart_port *_port)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ u16 ctr;
+
+ _enter("%s", port->name);
+
+ ctr = *port->_control;
+ ctr &= ~SC01CTR_RXE;
+ *port->_control = ctr;
+
+ mn10300_serial_dis_rx_intr(port);
+}
+
+/*
+ * enable modem status interrupts
+ */
+static void mn10300_serial_enable_ms(struct uart_port *_port)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ u16 ctr, cts;
+
+ _enter("%s", port->name);
+
+ if (port->type == PORT_MN10300_CTS) {
+ /* want to interrupt when CTS goes low if CTS is now high and
+ * vice versa
+ */
+ port->tx_cts = *port->_status;
+
+ cts = (port->tx_cts & SC2STR_CTS) ?
+ SC2CTR_TWE : SC2CTR_TWE | SC2CTR_TWS;
+
+ ctr = *port->_control;
+ ctr &= ~SC2CTR_TWS;
+ ctr |= cts;
+ *port->_control = ctr;
+
+ mn10300_serial_en_tx_intr(port);
+ }
+}
+
+/*
+ * transmit or cease transmitting a break signal
+ */
+static void mn10300_serial_break_ctl(struct uart_port *_port, int ctl)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ _enter("%s,%d", port->name, ctl);
+
+ if (ctl) {
+ /* tell the virtual DMA handler to assert BREAK */
+ port->tx_break = 1;
+ mn10300_serial_en_tx_intr(port);
+ } else {
+ port->tx_break = 0;
+ *port->_control &= ~SC01CTR_BKE;
+ mn10300_serial_en_tx_intr(port);
+ }
+}
+
+/*
+ * grab the interrupts and enable the port for reception
+ */
+static int mn10300_serial_startup(struct uart_port *_port)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+ struct mn10300_serial_int *pint;
+
+ _enter("%s{%d}", port->name, port->gdbstub);
+
+ if (unlikely(port->gdbstub))
+ return -EBUSY;
+
+ /* allocate an Rx buffer for the virtual DMA handler */
+ port->rx_buffer = kmalloc(MNSC_BUFFER_SIZE, GFP_KERNEL);
+ if (!port->rx_buffer)
+ return -ENOMEM;
+
+ port->rx_inp = port->rx_outp = 0;
+
+ /* finally, enable the device */
+ *port->_intr = SC01ICR_TI;
+ *port->_control |= SC01CTR_TXE | SC01CTR_RXE;
+
+ pint = &mn10300_serial_int_tbl[port->rx_irq];
+ pint->port = port;
+ pint->vdma = mn10300_serial_vdma_rx_handler;
+ pint = &mn10300_serial_int_tbl[port->tx_irq];
+ pint->port = port;
+ pint->vdma = mn10300_serial_vdma_tx_handler;
+
+ set_intr_level(port->rx_irq, GxICR_LEVEL_1);
+ set_intr_level(port->tx_irq, GxICR_LEVEL_1);
+ set_irq_chip(port->tm_irq, &mn10300_serial_pic);
+
+ if (request_irq(port->rx_irq, mn10300_serial_interrupt,
+ IRQF_DISABLED, port->rx_name, port) < 0)
+ goto error;
+
+ if (request_irq(port->tx_irq, mn10300_serial_interrupt,
+ IRQF_DISABLED, port->tx_name, port) < 0)
+ goto error2;
+
+ if (request_irq(port->tm_irq, mn10300_serial_interrupt,
+ IRQF_DISABLED, port->tm_name, port) < 0)
+ goto error3;
+ mn10300_serial_mask_ack(port->tm_irq);
+
+ return 0;
+
+error3:
+ free_irq(port->tx_irq, port);
+error2:
+ free_irq(port->rx_irq, port);
+error:
+ kfree(port->rx_buffer);
+ port->rx_buffer = NULL;
+ return -EBUSY;
+}
+
+/*
+ * shutdown the port and release interrupts
+ */
+static void mn10300_serial_shutdown(struct uart_port *_port)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ _enter("%s", port->name);
+
+ /* disable the serial port and its baud rate timer */
+ port->tx_break = 0;
+ *port->_control &= ~(SC01CTR_TXE | SC01CTR_RXE | SC01CTR_BKE);
+ *port->_tmxmd = 0;
+
+ if (port->rx_buffer) {
+ void *buf = port->rx_buffer;
+ port->rx_buffer = NULL;
+ kfree(buf);
+ }
+
+ /* disable all intrs */
+ free_irq(port->tm_irq, port);
+ free_irq(port->rx_irq, port);
+ free_irq(port->tx_irq, port);
+
+ *port->rx_icr = GxICR_LEVEL_1;
+ *port->tx_icr = GxICR_LEVEL_1;
+}
+
+/*
+ * this routine is called to set the UART divisor registers to match the
+ * specified baud rate for a serial port.
+ */
+static void mn10300_serial_change_speed(struct mn10300_serial_port *port,
+ struct ktermios *new,
+ struct ktermios *old)
+{
+ unsigned long flags;
+ unsigned long ioclk = port->ioclk;
+ unsigned cflag;
+ int baud, bits, xdiv, tmp;
+ u16 tmxbr, scxctr;
+ u8 tmxmd, battempt;
+ u8 div_timer = port->div_timer;
+
+ _enter("%s{%lu}", port->name, ioclk);
+
+ /* byte size and parity */
+ cflag = new->c_cflag;
+ switch (cflag & CSIZE) {
+ case CS7: scxctr = SC01CTR_CLN_7BIT; bits = 9; break;
+ case CS8: scxctr = SC01CTR_CLN_8BIT; bits = 10; break;
+ default: scxctr = SC01CTR_CLN_8BIT; bits = 10; break;
+ }
+
+ if (cflag & CSTOPB) {
+ scxctr |= SC01CTR_STB_2BIT;
+ bits++;
+ }
+
+ if (cflag & PARENB) {
+ bits++;
+ if (cflag & PARODD)
+ scxctr |= SC01CTR_PB_ODD;
+#ifdef CMSPAR
+ else if (cflag & CMSPAR)
+ scxctr |= SC01CTR_PB_FIXED0;
+#endif
+ else
+ scxctr |= SC01CTR_PB_EVEN;
+ }
+
+ /* Determine divisor based on baud rate */
+ battempt = 0;
+
+ if (div_timer == MNSCx_DIV_TIMER_16BIT)
+ scxctr |= SC0CTR_CK_TM8UFLOW_8; /* ( == SC1CTR_CK_TM9UFLOW_8
+ * == SC2CTR_CK_TM10UFLOW) */
+ else if (div_timer == MNSCx_DIV_TIMER_8BIT)
+ scxctr |= SC0CTR_CK_TM2UFLOW_8;
+
+try_alternative:
+ baud = uart_get_baud_rate(&port->uart, new, old, 0,
+ port->ioclk / 8);
+
+ _debug("ALT %d [baud %d]", battempt, baud);
+
+ if (!baud)
+ baud = 9600; /* B0 transition handled in rs_set_termios */
+ xdiv = 1;
+ if (baud == 134) {
+ baud = 269; /* 134 is really 134.5 */
+ xdiv = 2;
+ }
+
+ if (baud == 38400 &&
+ (port->uart.flags & UPF_SPD_MASK) == UPF_SPD_CUST
+ ) {
+ _debug("CUSTOM %u", port->uart.custom_divisor);
+
+ if (div_timer == MNSCx_DIV_TIMER_16BIT) {
+ if (port->uart.custom_divisor <= 65535) {
+ tmxmd = TM8MD_SRC_IOCLK;
+ tmxbr = port->uart.custom_divisor;
+ port->uart.uartclk = ioclk;
+ goto timer_okay;
+ }
+ if (port->uart.custom_divisor / 8 <= 65535) {
+ tmxmd = TM8MD_SRC_IOCLK_8;
+ tmxbr = port->uart.custom_divisor / 8;
+ port->uart.custom_divisor = tmxbr * 8;
+ port->uart.uartclk = ioclk / 8;
+ goto timer_okay;
+ }
+ if (port->uart.custom_divisor / 32 <= 65535) {
+ tmxmd = TM8MD_SRC_IOCLK_32;
+ tmxbr = port->uart.custom_divisor / 32;
+ port->uart.custom_divisor = tmxbr * 32;
+ port->uart.uartclk = ioclk / 32;
+ goto timer_okay;
+ }
+
+ } else if (div_timer == MNSCx_DIV_TIMER_8BIT) {
+ if (port->uart.custom_divisor <= 255) {
+ tmxmd = TM2MD_SRC_IOCLK;
+ tmxbr = port->uart.custom_divisor;
+ port->uart.uartclk = ioclk;
+ goto timer_okay;
+ }
+ if (port->uart.custom_divisor / 8 <= 255) {
+ tmxmd = TM2MD_SRC_IOCLK_8;
+ tmxbr = port->uart.custom_divisor / 8;
+ port->uart.custom_divisor = tmxbr * 8;
+ port->uart.uartclk = ioclk / 8;
+ goto timer_okay;
+ }
+ if (port->uart.custom_divisor / 32 <= 255) {
+ tmxmd = TM2MD_SRC_IOCLK_32;
+ tmxbr = port->uart.custom_divisor / 32;
+ port->uart.custom_divisor = tmxbr * 32;
+ port->uart.uartclk = ioclk / 32;
+ goto timer_okay;
+ }
+ }
+ }
+
+ switch (div_timer) {
+ case MNSCx_DIV_TIMER_16BIT:
+ port->uart.uartclk = ioclk;
+ tmxmd = TM8MD_SRC_IOCLK;
+ tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 65535)
+ goto timer_okay;
+
+ port->uart.uartclk = ioclk / 8;
+ tmxmd = TM8MD_SRC_IOCLK_8;
+ tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 65535)
+ goto timer_okay;
+
+ port->uart.uartclk = ioclk / 32;
+ tmxmd = TM8MD_SRC_IOCLK_32;
+ tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 65535)
+ goto timer_okay;
+ break;
+
+ case MNSCx_DIV_TIMER_8BIT:
+ port->uart.uartclk = ioclk;
+ tmxmd = TM2MD_SRC_IOCLK;
+ tmxbr = tmp = (ioclk / (baud * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 255)
+ goto timer_okay;
+
+ port->uart.uartclk = ioclk / 8;
+ tmxmd = TM2MD_SRC_IOCLK_8;
+ tmxbr = tmp = (ioclk / (baud * 8 * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 255)
+ goto timer_okay;
+
+ port->uart.uartclk = ioclk / 32;
+ tmxmd = TM2MD_SRC_IOCLK_32;
+ tmxbr = tmp = (ioclk / (baud * 32 * xdiv) + 4) / 8 - 1;
+ if (tmp > 0 && tmp <= 255)
+ goto timer_okay;
+ break;
+
+ default:
+ BUG();
+ return;
+ }
+
+ /* refuse to change to a baud rate we can't support */
+ _debug("CAN'T SUPPORT");
+
+ switch (battempt) {
+ case 0:
+ if (old) {
+ new->c_cflag &= ~CBAUD;
+ new->c_cflag |= (old->c_cflag & CBAUD);
+ battempt = 1;
+ goto try_alternative;
+ }
+
+ case 1:
+ /* as a last resort, if the quotient is zero, default to 9600
+ * bps */
+ new->c_cflag &= ~CBAUD;
+ new->c_cflag |= B9600;
+ battempt = 2;
+ goto try_alternative;
+
+ default:
+ /* hmmm... can't seem to support 9600 either
+ * - we could try iterating through the speeds we know about to
+ * find the lowest
+ */
+ new->c_cflag &= ~CBAUD;
+ new->c_cflag |= B0;
+
+ if (div_timer == MNSCx_DIV_TIMER_16BIT)
+ tmxmd = TM8MD_SRC_IOCLK_32;
+ else if (div_timer == MNSCx_DIV_TIMER_8BIT)
+ tmxmd = TM2MD_SRC_IOCLK_32;
+ tmxbr = 1;
+
+ port->uart.uartclk = ioclk / 32;
+ break;
+ }
+timer_okay:
+
+ _debug("UARTCLK: %u / %hu", port->uart.uartclk, tmxbr);
+
+ /* make the changes */
+ spin_lock_irqsave(&port->uart.lock, flags);
+
+ uart_update_timeout(&port->uart, new->c_cflag, baud);
+
+ /* set the timer to produce the required baud rate */
+ switch (div_timer) {
+ case MNSCx_DIV_TIMER_16BIT:
+ *port->_tmxmd = 0;
+ *port->_tmxbr = tmxbr;
+ *port->_tmxmd = TM8MD_INIT_COUNTER;
+ *port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
+ break;
+
+ case MNSCx_DIV_TIMER_8BIT:
+ *port->_tmxmd = 0;
+ *(volatile u8 *) port->_tmxbr = (u8) tmxbr;
+ *port->_tmxmd = TM2MD_INIT_COUNTER;
+ *port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
+ break;
+ }
+
+ /* CTS flow control flag and modem status interrupts */
+ scxctr &= ~(SC2CTR_TWE | SC2CTR_TWS);
+
+ if (port->type == PORT_MN10300_CTS && cflag & CRTSCTS) {
+ /* want to interrupt when CTS goes low if CTS is now
+ * high and vice versa
+ */
+ port->tx_cts = *port->_status;
+
+ if (port->tx_cts & SC2STR_CTS)
+ scxctr |= SC2CTR_TWE;
+ else
+ scxctr |= SC2CTR_TWE | SC2CTR_TWS;
+ }
+
+ /* set up parity check flag */
+ port->uart.read_status_mask = (1 << TTY_NORMAL) | (1 << TTY_OVERRUN);
+ if (new->c_iflag & INPCK)
+ port->uart.read_status_mask |=
+ (1 << TTY_PARITY) | (1 << TTY_FRAME);
+ if (new->c_iflag & (BRKINT | PARMRK))
+ port->uart.read_status_mask |= (1 << TTY_BREAK);
+
+ /* characters to ignore */
+ port->uart.ignore_status_mask = 0;
+ if (new->c_iflag & IGNPAR)
+ port->uart.ignore_status_mask |=
+ (1 << TTY_PARITY) | (1 << TTY_FRAME);
+ if (new->c_iflag & IGNBRK) {
+ port->uart.ignore_status_mask |= (1 << TTY_BREAK);
+ /*
+ * If we're ignoring parity and break indicators,
+ * ignore overruns to (for real raw support).
+ */
+ if (new->c_iflag & IGNPAR)
+ port->uart.ignore_status_mask |= (1 << TTY_OVERRUN);
+ }
+
+ /* Ignore all characters if CREAD is not set */
+ if ((new->c_cflag & CREAD) == 0)
+ port->uart.ignore_status_mask |= (1 << TTY_NORMAL);
+
+ scxctr |= *port->_control & (SC01CTR_TXE | SC01CTR_RXE | SC01CTR_BKE);
+ *port->_control = scxctr;
+
+ spin_unlock_irqrestore(&port->uart.lock, flags);
+}
+
+/*
+ * set the terminal I/O parameters
+ */
+static void mn10300_serial_set_termios(struct uart_port *_port,
+ struct ktermios *new,
+ struct ktermios *old)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ _enter("%s,%p,%p", port->name, new, old);
+
+ mn10300_serial_change_speed(port, new, old);
+
+ /* handle turning off CRTSCTS */
+ if (!(new->c_cflag & CRTSCTS)) {
+ u16 ctr = *port->_control;
+ ctr &= ~SC2CTR_TWE;
+ *port->_control = ctr;
+ }
+}
+
+/*
+ * return description of port type
+ */
+static const char *mn10300_serial_type(struct uart_port *_port)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ if (port->uart.type == PORT_MN10300_CTS)
+ return "MN10300 SIF_CTS";
+
+ return "MN10300 SIF";
+}
+
+/*
+ * release I/O and memory regions in use by port
+ */
+static void mn10300_serial_release_port(struct uart_port *_port)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ _enter("%s", port->name);
+
+ release_mem_region((unsigned long) port->_iobase, 16);
+}
+
+/*
+ * request I/O and memory regions for port
+ */
+static int mn10300_serial_request_port(struct uart_port *_port)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ _enter("%s", port->name);
+
+ request_mem_region((unsigned long) port->_iobase, 16, port->name);
+ return 0;
+}
+
+/*
+ * configure the type and reserve the ports
+ */
+static void mn10300_serial_config_port(struct uart_port *_port, int type)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+
+ _enter("%s", port->name);
+
+ port->uart.type = PORT_MN10300;
+
+ if (port->options & MNSCx_OPT_CTS)
+ port->uart.type = PORT_MN10300_CTS;
+
+ mn10300_serial_request_port(_port);
+}
+
+/*
+ * verify serial parameters are suitable for this port type
+ */
+static int mn10300_serial_verify_port(struct uart_port *_port,
+ struct serial_struct *ss)
+{
+ struct mn10300_serial_port *port =
+ container_of(_port, struct mn10300_serial_port, uart);
+ void *mapbase = (void *) (unsigned long) port->uart.mapbase;
+
+ _enter("%s", port->name);
+
+ /* these things may not be changed */
+ if (ss->irq != port->uart.irq ||
+ ss->port != port->uart.iobase ||
+ ss->io_type != port->uart.iotype ||
+ ss->iomem_base != mapbase ||
+ ss->iomem_reg_shift != port->uart.regshift ||
+ ss->hub6 != port->uart.hub6 ||
+ ss->xmit_fifo_size != port->uart.fifosize)
+ return -EINVAL;
+
+ /* type may be changed on a port that supports CTS */
+ if (ss->type != port->uart.type) {
+ if (!(port->options & MNSCx_OPT_CTS))
+ return -EINVAL;
+
+ if (ss->type != PORT_MN10300 &&
+ ss->type != PORT_MN10300_CTS)
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
+ * initialise the MN10300 on-chip UARTs
+ */
+static int __init mn10300_serial_init(void)
+{
+ struct mn10300_serial_port *port;
+ int ret, i;
+
+ printk(KERN_INFO "%s version %s (%s)\n",
+ serial_name, serial_version, serial_revdate);
+
+#ifdef CONFIG_MN10300_TTYSM2
+ SC2TIM = 8; /* make the baud base of timer 2 IOCLK/8 */
+#endif
+
+ set_intr_stub(EXCEP_IRQ_LEVEL1, mn10300_serial_vdma_interrupt);
+
+ ret = uart_register_driver(&mn10300_serial_driver);
+ if (!ret) {
+ for (i = 0 ; i < NR_PORTS ; i++) {
+ port = mn10300_serial_ports[i];
+ if (!port || port->gdbstub)
+ continue;
+
+ switch (port->clock_src) {
+ case MNSCx_CLOCK_SRC_IOCLK:
+ port->ioclk = MN10300_IOCLK;
+ break;
+
+#ifdef MN10300_IOBCLK
+ case MNSCx_CLOCK_SRC_IOBCLK:
+ port->ioclk = MN10300_IOBCLK;
+ break;
+#endif
+ default:
+ BUG();
+ }
+
+ ret = uart_add_one_port(&mn10300_serial_driver,
+ &port->uart);
+
+ if (ret < 0) {
+ _debug("ERROR %d", -ret);
+ break;
+ }
+ }
+
+ if (ret)
+ uart_unregister_driver(&mn10300_serial_driver);
+ }
+
+ return ret;
+}
+
+__initcall(mn10300_serial_init);
+
+
+#ifdef CONFIG_MN10300_TTYSM_CONSOLE
+
+/*
+ * print a string to the serial port without disturbing the real user of the
+ * port too much
+ * - the console must be locked by the caller
+ */
+static void mn10300_serial_console_write(struct console *co,
+ const char *s, unsigned count)
+{
+ struct mn10300_serial_port *port;
+ unsigned i;
+ u16 scxctr, txicr, tmp;
+ u8 tmxmd;
+
+ port = mn10300_serial_ports[co->index];
+
+ /* firstly hijack the serial port from the "virtual DMA" controller */
+ txicr = *port->tx_icr;
+ *port->tx_icr = GxICR_LEVEL_1;
+ tmp = *port->tx_icr;
+
+ /* the transmitter may be disabled */
+ scxctr = *port->_control;
+ if (!(scxctr & SC01CTR_TXE)) {
+ /* restart the UART clock */
+ tmxmd = *port->_tmxmd;
+
+ switch (port->div_timer) {
+ case MNSCx_DIV_TIMER_16BIT:
+ *port->_tmxmd = 0;
+ *port->_tmxmd = TM8MD_INIT_COUNTER;
+ *port->_tmxmd = tmxmd | TM8MD_COUNT_ENABLE;
+ break;
+
+ case MNSCx_DIV_TIMER_8BIT:
+ *port->_tmxmd = 0;
+ *port->_tmxmd = TM2MD_INIT_COUNTER;
+ *port->_tmxmd = tmxmd | TM2MD_COUNT_ENABLE;
+ break;
+ }
+
+ /* enable the transmitter */
+ *port->_control = (scxctr & ~SC01CTR_BKE) | SC01CTR_TXE;
+
+ } else if (scxctr & SC01CTR_BKE) {
+ /* stop transmitting BREAK */
+ *port->_control = (scxctr & ~SC01CTR_BKE);
+ }
+
+ /* send the chars into the serial port (with LF -> LFCR conversion) */
+ for (i = 0; i < count; i++) {
+ char ch = *s++;
+
+ while (*port->_status & SC01STR_TBF)
+ continue;
+ *(u8 *) port->_txb = ch;
+
+ if (ch == 0x0a) {
+ while (*port->_status & SC01STR_TBF)
+ continue;
+ *(u8 *) port->_txb = 0xd;
+ }
+ }
+
+ /* can't let the transmitter be turned off if it's actually
+ * transmitting */
+ while (*port->_status & (SC01STR_TXF | SC01STR_TBF))
+ continue;
+
+ /* disable the transmitter if we re-enabled it */
+ if (!(scxctr & SC01CTR_TXE))
+ *port->_control = scxctr;
+
+ *port->tx_icr = txicr;
+ tmp = *port->tx_icr;
+}
+
+/*
+ * set up a serial port as a console
+ * - construct a cflag setting for the first rs_open()
+ * - initialize the serial port
+ * - return non-zero if we didn't find a serial port.
+ */
+static int __init mn10300_serial_console_setup(struct console *co,
+ char *options)
+{
+ struct mn10300_serial_port *port;
+ int i, parity = 'n', baud = 9600, bits = 8, flow = 0;
+
+ for (i = 0 ; i < NR_PORTS ; i++) {
+ port = mn10300_serial_ports[i];
+ if (port && !port->gdbstub && port->uart.line == co->index)
+ goto found_device;
+ }
+
+ return -ENODEV;
+
+found_device:
+ switch (port->clock_src) {
+ case MNSCx_CLOCK_SRC_IOCLK:
+ port->ioclk = MN10300_IOCLK;
+ break;
+
+#ifdef MN10300_IOBCLK
+ case MNSCx_CLOCK_SRC_IOBCLK:
+ port->ioclk = MN10300_IOBCLK;
+ break;
+#endif
+ default:
+ BUG();
+ }
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+ return uart_set_options(&port->uart, co, baud, parity, bits, flow);
+}
+
+/*
+ * register console
+ */
+static int __init mn10300_serial_console_init(void)
+{
+ register_console(&mn10300_serial_console);
+ return 0;
+}
+
+console_initcall(mn10300_serial_console_init);
+#endif
--- /dev/null
+/* MN10300 On-chip serial port driver definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _MN10300_SERIAL_H
+#define _MN10300_SERIAL_H
+
+#ifndef __ASSEMBLY__
+#include <linux/serial_core.h>
+#include <linux/termios.h>
+#endif
+
+#include <asm/page.h>
+#include <asm/serial-regs.h>
+
+#define NR_PORTS 3 /* should be set 3 or 9 or 16 */
+
+#define MNSC_BUFFER_SIZE +(PAGE_SIZE / 2)
+
+/* intr_flags bits */
+#define MNSCx_RX_AVAIL 0x01
+#define MNSCx_RX_OVERF 0x02
+#define MNSCx_TX_SPACE 0x04
+#define MNSCx_TX_EMPTY 0x08
+
+#ifndef __ASSEMBLY__
+
+struct mn10300_serial_port {
+ char *rx_buffer; /* reception buffer base */
+ unsigned rx_inp; /* pointer to rx input offset */
+ unsigned rx_outp; /* pointer to rx output offset */
+ u8 tx_xchar; /* high-priority XON/XOFF buffer */
+ u8 tx_break; /* transmit break request */
+ u8 intr_flags; /* interrupt flags */
+ volatile u16 *rx_icr; /* Rx interrupt control register */
+ volatile u16 *tx_icr; /* Tx interrupt control register */
+ int rx_irq; /* reception IRQ */
+ int tx_irq; /* transmission IRQ */
+ int tm_irq; /* timer IRQ */
+
+ const char *name; /* name of serial port */
+ const char *rx_name; /* Rx interrupt handler name of serial port */
+ const char *tx_name; /* Tx interrupt handler name of serial port */
+ const char *tm_name; /* Timer interrupt handler name */
+ unsigned short type; /* type of serial port */
+ unsigned char isconsole; /* T if it's a console */
+ volatile void *_iobase; /* pointer to base of I/O control regs */
+ volatile u16 *_control; /* control register pointer */
+ volatile u8 *_status; /* status register pointer */
+ volatile u8 *_intr; /* interrupt register pointer */
+ volatile void *_rxb; /* receive buffer register pointer */
+ volatile void *_txb; /* transmit buffer register pointer */
+ volatile u16 *_tmicr; /* timer interrupt control register */
+ volatile u8 *_tmxmd; /* baud rate timer mode register */
+ volatile u16 *_tmxbr; /* baud rate timer base register */
+
+ /* this must come down here so that assembly can use BSET to access the
+ * above fields */
+ struct uart_port uart;
+
+ unsigned short rx_brk; /* current break reception status */
+ u16 tx_cts; /* current CTS status */
+ int gdbstub; /* preemptively stolen by GDB stub */
+
+ u8 clock_src; /* clock source */
+#define MNSCx_CLOCK_SRC_IOCLK 0
+#define MNSCx_CLOCK_SRC_IOBCLK 1
+
+ u8 div_timer; /* timer used as divisor */
+#define MNSCx_DIV_TIMER_16BIT 0
+#define MNSCx_DIV_TIMER_8BIT 1
+
+ u16 options; /* options */
+#define MNSCx_OPT_CTS 0x0001
+
+ unsigned long ioclk; /* base clock rate */
+};
+
+#ifdef CONFIG_MN10300_TTYSM0
+extern struct mn10300_serial_port mn10300_serial_port_sif0;
+#endif
+
+#ifdef CONFIG_MN10300_TTYSM1
+extern struct mn10300_serial_port mn10300_serial_port_sif1;
+#endif
+
+#ifdef CONFIG_MN10300_TTYSM2
+extern struct mn10300_serial_port mn10300_serial_port_sif2;
+#endif
+
+extern struct mn10300_serial_port *mn10300_serial_ports[];
+
+struct mn10300_serial_int {
+ struct mn10300_serial_port *port;
+ asmlinkage void (*vdma)(void);
+};
+
+extern struct mn10300_serial_int mn10300_serial_int_tbl[];
+
+extern asmlinkage void mn10300_serial_vdma_interrupt(void);
+extern asmlinkage void mn10300_serial_vdma_rx_handler(void);
+extern asmlinkage void mn10300_serial_vdma_tx_handler(void);
+
+#endif /* __ASSEMBLY__ */
+
+#if defined(CONFIG_GDBSTUB_ON_TTYSM0)
+#define SCgSTR SC0STR
+#define SCgRXB SC0RXB
+#define SCgRXIRQ SC0RXIRQ
+#elif defined(CONFIG_GDBSTUB_ON_TTYSM1)
+#define SCgSTR SC1STR
+#define SCgRXB SC1RXB
+#define SCgRXIRQ SC1RXIRQ
+#elif defined(CONFIG_GDBSTUB_ON_TTYSM2)
+#define SCgSTR SC2STR
+#define SCgRXB SC2RXB
+#define SCgRXIRQ SC2RXIRQ
+#endif
+
+#endif /* _MN10300_SERIAL_H */
--- /dev/null
+###############################################################################
+#
+# MN10300 Watchdog interrupt handler
+#
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Written by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+###############################################################################
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/intctl-regs.h>
+#include <asm/timer-regs.h>
+#include <asm/frame.inc>
+
+ .text
+
+###############################################################################
+#
+# Watchdog handler entry point
+# - special non-maskable interrupt
+#
+###############################################################################
+ .globl watchdog_handler
+ .type watchdog_handler,@function
+watchdog_handler:
+ add -4,sp
+ SAVE_ALL
+
+ mov 0xffffffff,d0
+ mov d0,(REG_ORIG_D0,fp)
+
+ mov fp,d0
+ lsr 2,d1
+ call watchdog_interrupt[],0 # watchdog_interrupt(regs,irq)
+
+ jmp ret_from_intr
+
+ .size watchdog_handler,.-watchdog_handler
+
+###############################################################################
+#
+# Watchdog touch entry point
+# - kept to absolute minimum (unfortunately, it's prototyped in linux/nmi.h so
+# we can't inline it)
+#
+###############################################################################
+ .globl touch_nmi_watchdog
+ .type touch_nmi_watchdog,@function
+touch_nmi_watchdog:
+ clr d0
+ mov d0,(watchdog_alert_counter)
+ ret [],0
+
+ .size touch_nmi_watchdog,.-touch_nmi_watchdog
--- /dev/null
+/* MN10300 Watchdog timer
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ * - Derived from arch/i386/kernel/nmi.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <linux/nmi.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/intctl-regs.h>
+#include <asm/rtc-regs.h>
+#include <asm/div64.h>
+#include <asm/smp.h>
+#include <asm/gdb-stub.h>
+#include <asm/proc/clock.h>
+
+static DEFINE_SPINLOCK(watchdog_print_lock);
+static unsigned int watchdog;
+static unsigned int watchdog_hz = 1;
+unsigned int watchdog_alert_counter;
+
+EXPORT_SYMBOL(touch_nmi_watchdog);
+
+/*
+ * the best way to detect whether a CPU has a 'hard lockup' problem
+ * is to check its timer makes IRQ counts. If they are not
+ * changing then that CPU has some problem.
+ *
+ * as these watchdog NMI IRQs are generated on every CPU, we only
+ * have to check the current processor.
+ *
+ * since NMIs dont listen to _any_ locks, we have to be extremely
+ * careful not to rely on unsafe variables. The printk might lock
+ * up though, so we have to break up any console locks first ...
+ * [when there will be more tty-related locks, break them up
+ * here too!]
+ */
+static unsigned int last_irq_sums[NR_CPUS];
+
+int __init check_watchdog(void)
+{
+ irq_cpustat_t tmp[1];
+
+ printk(KERN_INFO "Testing Watchdog... ");
+
+ memcpy(tmp, irq_stat, sizeof(tmp));
+ local_irq_enable();
+ mdelay((10 * 1000) / watchdog_hz); /* wait 10 ticks */
+ local_irq_disable();
+
+ if (nmi_count(0) - tmp[0].__nmi_count <= 5) {
+ printk(KERN_WARNING "CPU#%d: Watchdog appears to be stuck!\n",
+ 0);
+ return -1;
+ }
+
+ printk(KERN_INFO "OK.\n");
+
+ /* now that we know it works we can reduce NMI frequency to
+ * something more reasonable; makes a difference in some configs
+ */
+ watchdog_hz = 1;
+
+ return 0;
+}
+
+static int __init setup_watchdog(char *str)
+{
+ unsigned tmp;
+ int opt;
+ u8 ctr;
+
+ get_option(&str, &opt);
+ if (opt != 1)
+ return 0;
+
+ watchdog = opt;
+ if (watchdog) {
+ set_intr_stub(EXCEP_WDT, watchdog_handler);
+ ctr = WDCTR_WDCK_65536th;
+ WDCTR = WDCTR_WDRST | ctr;
+ WDCTR = ctr;
+ tmp = WDCTR;
+
+ tmp = __muldiv64u(1 << (16 + ctr * 2), 1000000, MN10300_WDCLK);
+ tmp = 1000000000 / tmp;
+ watchdog_hz = (tmp + 500) / 1000;
+ }
+
+ return 1;
+}
+
+__setup("watchdog=", setup_watchdog);
+
+void __init watchdog_go(void)
+{
+ u8 wdt;
+
+ if (watchdog) {
+ printk(KERN_INFO "Watchdog: running at %uHz\n", watchdog_hz);
+ wdt = WDCTR & ~WDCTR_WDCNE;
+ WDCTR = wdt | WDCTR_WDRST;
+ wdt = WDCTR;
+ WDCTR = wdt | WDCTR_WDCNE;
+ wdt = WDCTR;
+
+ check_watchdog();
+ }
+}
+
+asmlinkage
+void watchdog_interrupt(struct pt_regs *regs, enum exception_code excep)
+{
+
+ /*
+ * Since current-> is always on the stack, and we always switch
+ * the stack NMI-atomically, it's safe to use smp_processor_id().
+ */
+ int sum, cpu = smp_processor_id();
+ u8 wdt, tmp;
+
+ wdt = WDCTR & ~WDCTR_WDCNE;
+ WDCTR = wdt;
+ tmp = WDCTR;
+ NMICR = NMICR_WDIF;
+
+ nmi_count(cpu)++;
+ kstat_this_cpu.irqs[NMIIRQ]++;
+ sum = irq_stat[cpu].__irq_count;
+
+ if (last_irq_sums[cpu] == sum) {
+ /*
+ * Ayiee, looks like this CPU is stuck ...
+ * wait a few IRQs (5 seconds) before doing the oops ...
+ */
+ watchdog_alert_counter++;
+ if (watchdog_alert_counter == 5 * watchdog_hz) {
+ spin_lock(&watchdog_print_lock);
+ /*
+ * We are in trouble anyway, lets at least try
+ * to get a message out.
+ */
+ bust_spinlocks(1);
+ printk(KERN_ERR
+ "NMI Watchdog detected LOCKUP on CPU%d,"
+ " pc %08lx, registers:\n",
+ cpu, regs->pc);
+ show_registers(regs);
+ printk("console shuts up ...\n");
+ console_silent();
+ spin_unlock(&watchdog_print_lock);
+ bust_spinlocks(0);
+#ifdef CONFIG_GDBSTUB
+ if (gdbstub_busy)
+ gdbstub_exception(regs, excep);
+ else
+ gdbstub_intercept(regs, excep);
+#endif
+ do_exit(SIGSEGV);
+ }
+ } else {
+ last_irq_sums[cpu] = sum;
+ watchdog_alert_counter = 0;
+ }
+
+ WDCTR = wdt | WDCTR_WDRST;
+ tmp = WDCTR;
+ WDCTR = wdt | WDCTR_WDCNE;
+ tmp = WDCTR;
+}
--- /dev/null
+/* MN10300 Miscellaneous and library kernel exports
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <asm/uaccess.h>
+
+
+EXPORT_SYMBOL(change_bit);
+EXPORT_SYMBOL(test_and_change_bit);
+
+EXPORT_SYMBOL(memcpy);
+EXPORT_SYMBOL(memmove);
+EXPORT_SYMBOL(memset);
+
+EXPORT_SYMBOL(strncpy_from_user);
+EXPORT_SYMBOL(__strncpy_from_user);
+EXPORT_SYMBOL(clear_user);
+EXPORT_SYMBOL(__clear_user);
+EXPORT_SYMBOL(__generic_copy_from_user);
+EXPORT_SYMBOL(__generic_copy_to_user);
+EXPORT_SYMBOL(strnlen_user);
+
+extern u64 __ashrdi3(u64, unsigned);
+extern u64 __ashldi3(u64, unsigned);
+extern u64 __lshrdi3(u64, unsigned);
+extern s64 __negdi2(s64);
+EXPORT_SYMBOL(__ashrdi3);
+EXPORT_SYMBOL(__ashldi3);
+EXPORT_SYMBOL(__lshrdi3);
+EXPORT_SYMBOL(__negdi2);
--- /dev/null
+/* MN10300 Kernel module helper routines
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by Mark Salter (msalter@redhat.com)
+ * - Derived from arch/i386/kernel/module.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public Licence as published by
+ * the Free Software Foundation; either version 2 of the Licence, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public Licence for more details.
+ *
+ * You should have received a copy of the GNU General Public Licence
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/moduleloader.h>
+#include <linux/elf.h>
+#include <linux/vmalloc.h>
+#include <linux/fs.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+
+#if 0
+#define DEBUGP printk
+#else
+#define DEBUGP(fmt, ...)
+#endif
+
+/*
+ * allocate storage for a module
+ */
+void *module_alloc(unsigned long size)
+{
+ if (size == 0)
+ return NULL;
+ return vmalloc_exec(size);
+}
+
+/*
+ * free memory returned from module_alloc()
+ */
+void module_free(struct module *mod, void *module_region)
+{
+ vfree(module_region);
+ /* FIXME: If module_region == mod->init_region, trim exception
+ * table entries. */
+}
+
+/*
+ * allow the arch to fix up the section table
+ * - we don't need anything special
+ */
+int module_frob_arch_sections(Elf_Ehdr *hdr,
+ Elf_Shdr *sechdrs,
+ char *secstrings,
+ struct module *mod)
+{
+ return 0;
+}
+
+static uint32_t reloc_get16(uint8_t *p)
+{
+ return p[0] | (p[1] << 8);
+}
+
+static uint32_t reloc_get24(uint8_t *p)
+{
+ return reloc_get16(p) | (p[2] << 16);
+}
+
+static uint32_t reloc_get32(uint8_t *p)
+{
+ return reloc_get16(p) | (reloc_get16(p+2) << 16);
+}
+
+static void reloc_put16(uint8_t *p, uint32_t val)
+{
+ p[0] = val & 0xff;
+ p[1] = (val >> 8) & 0xff;
+}
+
+static void reloc_put24(uint8_t *p, uint32_t val)
+{
+ reloc_put16(p, val);
+ p[2] = (val >> 16) & 0xff;
+}
+
+static void reloc_put32(uint8_t *p, uint32_t val)
+{
+ reloc_put16(p, val);
+ reloc_put16(p+2, val >> 16);
+}
+
+/*
+ * apply a REL relocation
+ */
+int apply_relocate(Elf32_Shdr *sechdrs,
+ const char *strtab,
+ unsigned int symindex,
+ unsigned int relsec,
+ struct module *me)
+{
+ printk(KERN_ERR "module %s: RELOCATION unsupported\n",
+ me->name);
+ return -ENOEXEC;
+}
+
+/*
+ * apply a RELA relocation
+ */
+int apply_relocate_add(Elf32_Shdr *sechdrs,
+ const char *strtab,
+ unsigned int symindex,
+ unsigned int relsec,
+ struct module *me)
+{
+ unsigned int i;
+ Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr;
+ Elf32_Sym *sym;
+ Elf32_Addr relocation;
+ uint8_t *location;
+ uint32_t value;
+
+ DEBUGP("Applying relocate section %u to %u\n",
+ relsec, sechdrs[relsec].sh_info);
+
+ for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {
+ /* this is where to make the change */
+ location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
+ + rel[i].r_offset;
+
+ /* this is the symbol the relocation is referring to (note that
+ * all undefined symbols have been resolved by the caller) */
+ sym = (Elf32_Sym *)sechdrs[symindex].sh_addr
+ + ELF32_R_SYM(rel[i].r_info);
+
+ /* this is the adjustment to be made */
+ relocation = sym->st_value + rel[i].r_addend;
+
+ switch (ELF32_R_TYPE(rel[i].r_info)) {
+ /* for the first four relocation types, we add the
+ * adjustment into the value at the location given */
+ case R_MN10300_32:
+ value = reloc_get32(location);
+ value += relocation;
+ reloc_put32(location, value);
+ break;
+ case R_MN10300_24:
+ value = reloc_get24(location);
+ value += relocation;
+ reloc_put24(location, value);
+ break;
+ case R_MN10300_16:
+ value = reloc_get16(location);
+ value += relocation;
+ reloc_put16(location, value);
+ break;
+ case R_MN10300_8:
+ *location += relocation;
+ break;
+
+ /* for the next three relocation types, we write the
+ * adjustment with the address subtracted over the
+ * value at the location given */
+ case R_MN10300_PCREL32:
+ value = relocation - (uint32_t) location;
+ reloc_put32(location, value);
+ break;
+ case R_MN10300_PCREL16:
+ value = relocation - (uint32_t) location;
+ reloc_put16(location, value);
+ break;
+ case R_MN10300_PCREL8:
+ *location = relocation - (uint32_t) location;
+ break;
+
+ default:
+ printk(KERN_ERR "module %s: Unknown relocation: %u\n",
+ me->name, ELF32_R_TYPE(rel[i].r_info));
+ return -ENOEXEC;
+ }
+ }
+ return 0;
+}
+
+/*
+ * finish loading the module
+ */
+int module_finalize(const Elf_Ehdr *hdr,
+ const Elf_Shdr *sechdrs,
+ struct module *me)
+{
+ return 0;
+}
+
+/*
+ * finish clearing the module
+ */
+void module_arch_cleanup(struct module *mod)
+{
+}
--- /dev/null
+/* MN10300 Process handling code
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/stddef.h>
+#include <linux/unistd.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/user.h>
+#include <linux/a.out.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/reboot.h>
+#include <linux/percpu.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/mmu_context.h>
+#include <asm/fpu.h>
+#include <asm/reset-regs.h>
+#include <asm/gdb-stub.h>
+#include "internal.h"
+
+/*
+ * power management idle function, if any..
+ */
+void (*pm_idle)(void);
+EXPORT_SYMBOL(pm_idle);
+
+/*
+ * return saved PC of a blocked thread.
+ */
+unsigned long thread_saved_pc(struct task_struct *tsk)
+{
+ return ((unsigned long *) tsk->thread.sp)[3];
+}
+
+/*
+ * power off function, if any
+ */
+void (*pm_power_off)(void);
+EXPORT_SYMBOL(pm_power_off);
+
+/*
+ * we use this if we don't have any better idle routine
+ */
+static void default_idle(void)
+{
+ local_irq_disable();
+ if (!need_resched())
+ safe_halt();
+ else
+ local_irq_enable();
+}
+
+/*
+ * the idle thread
+ * - there's no useful work to be done, so just try to conserve power and have
+ * a low exit latency (ie sit in a loop waiting for somebody to say that
+ * they'd like to reschedule)
+ */
+void cpu_idle(void)
+{
+ int cpu = smp_processor_id();
+
+ /* endless idle loop with no priority at all */
+ for (;;) {
+ while (!need_resched()) {
+ void (*idle)(void);
+
+ smp_rmb();
+ idle = pm_idle;
+ if (!idle)
+ idle = default_idle;
+
+ irq_stat[cpu].idle_timestamp = jiffies;
+ idle();
+ }
+
+ preempt_enable_no_resched();
+ schedule();
+ preempt_disable();
+ }
+}
+
+void release_segments(struct mm_struct *mm)
+{
+}
+
+void machine_restart(char *cmd)
+{
+#ifdef CONFIG_GDBSTUB
+ gdbstub_exit(0);
+#endif
+
+#ifdef mn10300_unit_hard_reset
+ mn10300_unit_hard_reset();
+#else
+ mn10300_proc_hard_reset();
+#endif
+}
+
+void machine_halt(void)
+{
+#ifdef CONFIG_GDBSTUB
+ gdbstub_exit(0);
+#endif
+}
+
+void machine_power_off(void)
+{
+#ifdef CONFIG_GDBSTUB
+ gdbstub_exit(0);
+#endif
+}
+
+void show_regs(struct pt_regs *regs)
+{
+}
+
+/*
+ * create a kernel thread
+ */
+int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
+{
+ struct pt_regs regs;
+
+ memset(®s, 0, sizeof(regs));
+
+ regs.a2 = (unsigned long) fn;
+ regs.d2 = (unsigned long) arg;
+ regs.pc = (unsigned long) kernel_thread_helper;
+ local_save_flags(regs.epsw);
+ regs.epsw |= EPSW_IE | EPSW_IM_7;
+
+ /* Ok, create the new process.. */
+ return do_fork(flags | CLONE_VM | CLONE_UNTRACED, 0, ®s, 0,
+ NULL, NULL);
+}
+
+/*
+ * free current thread data structures etc..
+ */
+void exit_thread(void)
+{
+ exit_fpu();
+}
+
+void flush_thread(void)
+{
+ flush_fpu();
+}
+
+void release_thread(struct task_struct *dead_task)
+{
+}
+
+/*
+ * we do not have to muck with descriptors here, that is
+ * done in switch_mm() as needed.
+ */
+void copy_segments(struct task_struct *p, struct mm_struct *new_mm)
+{
+}
+
+/*
+ * this gets called before we allocate a new thread and copy the current task
+ * into it so that we can store lazy state into memory
+ */
+void prepare_to_copy(struct task_struct *tsk)
+{
+ unlazy_fpu(tsk);
+}
+
+/*
+ * set up the kernel stack for a new thread and copy arch-specific thread
+ * control information
+ */
+int copy_thread(int nr, unsigned long clone_flags,
+ unsigned long c_usp, unsigned long ustk_size,
+ struct task_struct *p, struct pt_regs *kregs)
+{
+ struct pt_regs *c_uregs, *c_kregs, *uregs;
+ unsigned long c_ksp;
+
+ uregs = current->thread.uregs;
+
+ c_ksp = (unsigned long) task_stack_page(p) + THREAD_SIZE;
+
+ /* allocate the userspace exception frame and set it up */
+ c_ksp -= sizeof(struct pt_regs);
+ c_uregs = (struct pt_regs *) c_ksp;
+
+ p->thread.uregs = c_uregs;
+ *c_uregs = *uregs;
+ c_uregs->sp = c_usp;
+ c_uregs->epsw &= ~EPSW_FE; /* my FPU */
+
+ c_ksp -= 12; /* allocate function call ABI slack */
+
+ /* the new TLS pointer is passed in as arg #5 to sys_clone() */
+ if (clone_flags & CLONE_SETTLS)
+ c_uregs->e2 = __frame->d3;
+
+ /* set up the return kernel frame if called from kernel_thread() */
+ c_kregs = c_uregs;
+ if (kregs != uregs) {
+ c_ksp -= sizeof(struct pt_regs);
+ c_kregs = (struct pt_regs *) c_ksp;
+ *c_kregs = *kregs;
+ c_kregs->sp = c_usp;
+ c_kregs->next = c_uregs;
+#ifdef CONFIG_MN10300_CURRENT_IN_E2
+ c_kregs->e2 = (unsigned long) p; /* current */
+#endif
+
+ c_ksp -= 12; /* allocate function call ABI slack */
+ }
+
+ /* set up things up so the scheduler can start the new task */
+ p->thread.__frame = c_kregs;
+ p->thread.a3 = (unsigned long) c_kregs;
+ p->thread.sp = c_ksp;
+ p->thread.pc = (unsigned long) ret_from_fork;
+ p->thread.wchan = (unsigned long) ret_from_fork;
+ p->thread.usp = c_usp;
+
+ return 0;
+}
+
+/*
+ * clone a process
+ * - tlsptr is retrieved by copy_thread() from __frame->d3
+ */
+asmlinkage long sys_clone(unsigned long clone_flags, unsigned long newsp,
+ int __user *parent_tidptr, int __user *child_tidptr,
+ int __user *tlsptr)
+{
+ return do_fork(clone_flags, newsp ?: __frame->sp, __frame, 0,
+ parent_tidptr, child_tidptr);
+}
+
+asmlinkage long sys_fork(void)
+{
+ return do_fork(SIGCHLD, __frame->sp, __frame, 0, NULL, NULL);
+}
+
+asmlinkage long sys_vfork(void)
+{
+ return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, __frame->sp, __frame,
+ 0, NULL, NULL);
+}
+
+asmlinkage long sys_execve(char __user *name,
+ char __user * __user *argv,
+ char __user * __user *envp)
+{
+ char *filename;
+ int error;
+
+ lock_kernel();
+
+ filename = getname(name);
+ error = PTR_ERR(filename);
+ if (!IS_ERR(filename)) {
+ error = do_execve(filename, argv, envp, __frame);
+ if (error == 0)
+ current->ptrace &= ~PT_DTRACE;
+
+ putname(filename);
+ }
+
+ unlock_kernel();
+ return error;
+}
+
+unsigned long get_wchan(struct task_struct *p)
+{
+ return p->thread.wchan;
+}
--- /dev/null
+###############################################################################
+#
+# Fast profiling interrupt handler
+#
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Written by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+###############################################################################
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/segment.h>
+#include <asm/smp.h>
+#include <asm/intctl-regs.h>
+#include <asm/timer-regs.h>
+
+#define pi break
+
+ .balign 4
+counter:
+ .long -1
+
+###############################################################################
+#
+# Profiling interrupt entry point
+# - intended to run at interrupt priority 1
+#
+###############################################################################
+ENTRY(profile_handler)
+ movm [d2,d3,a2],(sp)
+
+ # ignore userspace
+ mov (12,sp),d2
+ and EPSW_nSL,d2
+ bne out
+
+ # do nothing if there's no buffer
+ mov (prof_buffer),a2
+ and a2,a2
+ beq out
+ or 0x20000000,a2
+
+ # calculate relative position in text segment
+ mov (16,sp),d2
+ sub _stext,d2
+ mov (prof_shift),d3
+ lsr d3,d2
+ mov (prof_len),d3
+ cmp d3,d2
+ bcc outside_text
+
+ # increment the appropriate profile bucket
+do_inc:
+ asl2 d2
+ mov (a2,d2),d3
+ inc d3
+ mov d3,(a2,d2)
+out:
+ mov GxICR_DETECT,d2
+ movbu d2,(TM11ICR) # ACK the interrupt
+ movbu (TM11ICR),d2
+ movm (sp),[d2,d3,a2]
+ rti
+
+outside_text:
+ sub 1,d3
+ mov d3,d2
+ bra do_inc
--- /dev/null
+/* MN10300 Profiling setup
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+/*
+ * initialise the profiling if enabled
+ * - using with gdbstub will give anomalous results
+ * - can't be used with gdbstub if running at IRQ priority 0
+ */
+static __init int profile_init(void)
+{
+ u16 tmp;
+
+ if (!prof_buffer)
+ return 0;
+
+ /* use timer 11 to drive the profiling interrupts */
+ set_intr_stub(EXCEP_IRQ_LEVEL0, profile_handler);
+
+ /* set IRQ priority at which to run */
+ set_intr_level(TM11IRQ, GxICR_LEVEL_0);
+
+ /* set up timer 11
+ * - source: (IOCLK 33MHz)*2 = 66MHz
+ * - frequency: (33330000*2) / 8 / 20625 = 202Hz
+ */
+ TM11BR = 20625 - 1;
+ TM11MD = TM8MD_SRC_IOCLK_8;
+ TM11MD |= TM8MD_INIT_COUNTER;
+ TM11MD &= ~TM8MD_INIT_COUNTER;
+ TM11MD |= TM8MD_COUNT_ENABLE;
+
+ TM11ICR |= GxICR_ENABLE;
+ tmp = TM11ICR;
+
+ printk(KERN_INFO "Profiling initiated on timer 11, priority 0, %uHz\n",
+ mn10300_ioclk / 8 / (TM11BR + 1));
+ printk(KERN_INFO "Profile histogram stored %p-%p\n",
+ prof_buffer, (u8 *)(prof_buffer + prof_len) - 1);
+
+ return 0;
+}
+
+__initcall(profile_init);
--- /dev/null
+/* MN10300 Process tracing
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Modified by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/errno.h>
+#include <linux/ptrace.h>
+#include <linux/user.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+#include <asm/system.h>
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+#include <asm/fpu.h>
+#include <asm/asm-offsets.h>
+
+/*
+ * translate ptrace register IDs into struct pt_regs offsets
+ */
+static const u8 ptrace_regid_to_frame[] = {
+ [PT_A3 << 2] = REG_A3,
+ [PT_A2 << 2] = REG_A2,
+ [PT_D3 << 2] = REG_D3,
+ [PT_D2 << 2] = REG_D2,
+ [PT_MCVF << 2] = REG_MCVF,
+ [PT_MCRL << 2] = REG_MCRL,
+ [PT_MCRH << 2] = REG_MCRH,
+ [PT_MDRQ << 2] = REG_MDRQ,
+ [PT_E1 << 2] = REG_E1,
+ [PT_E0 << 2] = REG_E0,
+ [PT_E7 << 2] = REG_E7,
+ [PT_E6 << 2] = REG_E6,
+ [PT_E5 << 2] = REG_E5,
+ [PT_E4 << 2] = REG_E4,
+ [PT_E3 << 2] = REG_E3,
+ [PT_E2 << 2] = REG_E2,
+ [PT_SP << 2] = REG_SP,
+ [PT_LAR << 2] = REG_LAR,
+ [PT_LIR << 2] = REG_LIR,
+ [PT_MDR << 2] = REG_MDR,
+ [PT_A1 << 2] = REG_A1,
+ [PT_A0 << 2] = REG_A0,
+ [PT_D1 << 2] = REG_D1,
+ [PT_D0 << 2] = REG_D0,
+ [PT_ORIG_D0 << 2] = REG_ORIG_D0,
+ [PT_EPSW << 2] = REG_EPSW,
+ [PT_PC << 2] = REG_PC,
+};
+
+static inline int get_stack_long(struct task_struct *task, int offset)
+{
+ return *(unsigned long *)
+ ((unsigned long) task->thread.uregs + offset);
+}
+
+/*
+ * this routine will put a word on the processes privileged stack.
+ * the offset is how far from the base addr as stored in the TSS.
+ * this routine assumes that all the privileged stacks are in our
+ * data space.
+ */
+static inline
+int put_stack_long(struct task_struct *task, int offset, unsigned long data)
+{
+ unsigned long stack;
+
+ stack = (unsigned long) task->thread.uregs + offset;
+ *(unsigned long *) stack = data;
+ return 0;
+}
+
+static inline unsigned long get_fpregs(struct fpu_state_struct *buf,
+ struct task_struct *tsk)
+{
+ return __copy_to_user(buf, &tsk->thread.fpu_state,
+ sizeof(struct fpu_state_struct));
+}
+
+static inline unsigned long set_fpregs(struct task_struct *tsk,
+ struct fpu_state_struct *buf)
+{
+ return __copy_from_user(&tsk->thread.fpu_state, buf,
+ sizeof(struct fpu_state_struct));
+}
+
+static inline void fpsave_init(struct task_struct *task)
+{
+ memset(&task->thread.fpu_state, 0, sizeof(struct fpu_state_struct));
+}
+
+/*
+ * make sure the single step bit is not set
+ */
+void ptrace_disable(struct task_struct *child)
+{
+#ifndef CONFIG_MN10300_USING_JTAG
+ struct user *dummy = NULL;
+ long tmp;
+
+ tmp = get_stack_long(child, (unsigned long) &dummy->regs.epsw);
+ tmp &= ~EPSW_T;
+ put_stack_long(child, (unsigned long) &dummy->regs.epsw, tmp);
+#endif
+}
+
+/*
+ * set the single step bit
+ */
+void ptrace_enable(struct task_struct *child)
+{
+#ifndef CONFIG_MN10300_USING_JTAG
+ struct user *dummy = NULL;
+ long tmp;
+
+ tmp = get_stack_long(child, (unsigned long) &dummy->regs.epsw);
+ tmp |= EPSW_T;
+ put_stack_long(child, (unsigned long) &dummy->regs.epsw, tmp);
+#endif
+}
+
+/*
+ * handle the arch-specific side of process tracing
+ */
+long arch_ptrace(struct task_struct *child, long request, long addr, long data)
+{
+ struct fpu_state_struct fpu_state;
+ int i, ret;
+
+ switch (request) {
+ /* read the word at location addr. */
+ case PTRACE_PEEKTEXT: {
+ unsigned long tmp;
+ int copied;
+
+ copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
+ ret = -EIO;
+ if (copied != sizeof(tmp))
+ break;
+ ret = put_user(tmp, (unsigned long *) data);
+ break;
+ }
+
+ /* read the word at location addr. */
+ case PTRACE_PEEKDATA: {
+ unsigned long tmp;
+ int copied;
+
+ copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
+ ret = -EIO;
+ if (copied != sizeof(tmp))
+ break;
+ ret = put_user(tmp, (unsigned long *) data);
+ break;
+ }
+
+ /* read the word at location addr in the USER area. */
+ case PTRACE_PEEKUSR: {
+ unsigned long tmp;
+
+ ret = -EIO;
+ if ((addr & 3) || addr < 0 ||
+ addr > sizeof(struct user) - 3)
+ break;
+
+ tmp = 0; /* Default return condition */
+ if (addr < NR_PTREGS << 2)
+ tmp = get_stack_long(child,
+ ptrace_regid_to_frame[addr]);
+ ret = put_user(tmp, (unsigned long *) data);
+ break;
+ }
+
+ /* write the word at location addr. */
+ case PTRACE_POKETEXT:
+ case PTRACE_POKEDATA:
+ if (access_process_vm(child, addr, &data, sizeof(data), 1) ==
+ sizeof(data))
+ ret = 0;
+ else
+ ret = -EIO;
+ break;
+
+ /* write the word at location addr in the USER area */
+ case PTRACE_POKEUSR:
+ ret = -EIO;
+ if ((addr & 3) || addr < 0 ||
+ addr > sizeof(struct user) - 3)
+ break;
+
+ ret = 0;
+ if (addr < NR_PTREGS << 2)
+ ret = put_stack_long(child, ptrace_regid_to_frame[addr],
+ data);
+ break;
+
+ /* continue and stop at next (return from) syscall */
+ case PTRACE_SYSCALL:
+ /* restart after signal. */
+ case PTRACE_CONT:
+ ret = -EIO;
+ if ((unsigned long) data > _NSIG)
+ break;
+ if (request == PTRACE_SYSCALL)
+ set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
+ else
+ clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
+ child->exit_code = data;
+ ptrace_disable(child);
+ wake_up_process(child);
+ ret = 0;
+ break;
+
+ /*
+ * make the child exit
+ * - the best I can do is send it a sigkill
+ * - perhaps it should be put in the status that it wants to
+ * exit
+ */
+ case PTRACE_KILL:
+ ret = 0;
+ if (child->exit_state == EXIT_ZOMBIE) /* already dead */
+ break;
+ child->exit_code = SIGKILL;
+ clear_tsk_thread_flag(child, TIF_SINGLESTEP);
+ ptrace_disable(child);
+ wake_up_process(child);
+ break;
+
+ case PTRACE_SINGLESTEP: /* set the trap flag. */
+#ifndef CONFIG_MN10300_USING_JTAG
+ ret = -EIO;
+ if ((unsigned long) data > _NSIG)
+ break;
+ clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
+ ptrace_enable(child);
+ child->exit_code = data;
+ wake_up_process(child);
+ ret = 0;
+#else
+ ret = -EINVAL;
+#endif
+ break;
+
+ case PTRACE_DETACH: /* detach a process that was attached. */
+ ret = ptrace_detach(child, data);
+ break;
+
+ /* Get all gp regs from the child. */
+ case PTRACE_GETREGS: {
+ unsigned long tmp;
+
+ if (!access_ok(VERIFY_WRITE, (unsigned *) data, NR_PTREGS << 2)) {
+ ret = -EIO;
+ break;
+ }
+
+ for (i = 0; i < NR_PTREGS << 2; i += 4) {
+ tmp = get_stack_long(child, ptrace_regid_to_frame[i]);
+ __put_user(tmp, (unsigned long *) data);
+ data += sizeof(tmp);
+ }
+ ret = 0;
+ break;
+ }
+
+ case PTRACE_SETREGS: { /* Set all gp regs in the child. */
+ unsigned long tmp;
+
+ if (!access_ok(VERIFY_READ, (unsigned long *)data,
+ sizeof(struct pt_regs))) {
+ ret = -EIO;
+ break;
+ }
+
+ for (i = 0; i < NR_PTREGS << 2; i += 4) {
+ __get_user(tmp, (unsigned long *) data);
+ put_stack_long(child, ptrace_regid_to_frame[i], tmp);
+ data += sizeof(tmp);
+ }
+ ret = 0;
+ break;
+ }
+
+ case PTRACE_GETFPREGS: { /* Get the child FPU state. */
+ if (is_using_fpu(child)) {
+ unlazy_fpu(child);
+ fpu_state = child->thread.fpu_state;
+ } else {
+ memset(&fpu_state, 0, sizeof(fpu_state));
+ }
+
+ ret = -EIO;
+ if (copy_to_user((void *) data, &fpu_state,
+ sizeof(fpu_state)) == 0)
+ ret = 0;
+ break;
+ }
+
+ case PTRACE_SETFPREGS: { /* Set the child FPU state. */
+ ret = -EFAULT;
+ if (copy_from_user(&fpu_state, (const void *) data,
+ sizeof(fpu_state)) == 0) {
+ fpu_kill_state(child);
+ child->thread.fpu_state = fpu_state;
+ set_using_fpu(child);
+ ret = 0;
+ }
+ break;
+ }
+
+ case PTRACE_SETOPTIONS: {
+ if (data & PTRACE_O_TRACESYSGOOD)
+ child->ptrace |= PT_TRACESYSGOOD;
+ else
+ child->ptrace &= ~PT_TRACESYSGOOD;
+ ret = 0;
+ break;
+ }
+
+ default:
+ ret = -EIO;
+ break;
+ }
+
+ return ret;
+}
+
+/*
+ * notification of system call entry/exit
+ * - triggered by current->work.syscall_trace
+ */
+asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit)
+{
+#if 0
+ /* just in case... */
+ printk(KERN_DEBUG "[%d] syscall_%lu(%lx,%lx,%lx,%lx) = %lx\n",
+ current->pid,
+ regs->orig_d0,
+ regs->a0,
+ regs->d1,
+ regs->a3,
+ regs->a2,
+ regs->d0);
+ return;
+#endif
+
+ if (!test_thread_flag(TIF_SYSCALL_TRACE) &&
+ !test_thread_flag(TIF_SINGLESTEP))
+ return;
+ if (!(current->ptrace & PT_PTRACED))
+ return;
+
+ /* the 0x80 provides a way for the tracing parent to distinguish
+ between a syscall stop and SIGTRAP delivery */
+ ptrace_notify(SIGTRAP |
+ ((current->ptrace & PT_TRACESYSGOOD) &&
+ !test_thread_flag(TIF_SINGLESTEP) ? 0x80 : 0));
+
+ /*
+ * this isn't the same as continuing with a signal, but it will do
+ * for normal use. strace only continues with a signal if the
+ * stopping signal is not SIGTRAP. -brl
+ */
+ if (current->exit_code) {
+ send_sig(current->exit_code, current, 1);
+ current->exit_code = 0;
+ }
+}
--- /dev/null
+/* MN10300 RTC management
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/mc146818rtc.h>
+#include <linux/bcd.h>
+#include <linux/timex.h>
+#include <asm/rtc-regs.h>
+#include <asm/rtc.h>
+
+DEFINE_SPINLOCK(rtc_lock);
+EXPORT_SYMBOL(rtc_lock);
+
+/* last time the RTC got updated */
+static long last_rtc_update;
+
+/* time for RTC to update itself in ioclks */
+static unsigned long mn10300_rtc_update_period;
+
+/*
+ * read the current RTC time
+ */
+unsigned long __init get_initial_rtc_time(void)
+{
+ struct rtc_time tm;
+
+ get_rtc_time(&tm);
+
+ return mktime(tm.tm_year, tm.tm_mon, tm.tm_mday,
+ tm.tm_hour, tm.tm_min, tm.tm_sec);
+}
+
+/*
+ * In order to set the CMOS clock precisely, set_rtc_mmss has to be called 500
+ * ms after the second nowtime has started, because when nowtime is written
+ * into the registers of the CMOS clock, it will jump to the next second
+ * precisely 500 ms later. Check the Motorola MC146818A or Dallas DS12887 data
+ * sheet for details.
+ *
+ * BUG: This routine does not handle hour overflow properly; it just
+ * sets the minutes. Usually you'll only notice that after reboot!
+ */
+static int set_rtc_mmss(unsigned long nowtime)
+{
+ unsigned char save_control, save_freq_select;
+ int retval = 0;
+ int real_seconds, real_minutes, cmos_minutes;
+
+ /* gets recalled with irq locally disabled */
+ spin_lock(&rtc_lock);
+ save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being
+ * set */
+ CMOS_WRITE(save_control | RTC_SET, RTC_CONTROL);
+
+ save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset
+ * prescaler */
+ CMOS_WRITE(save_freq_select | RTC_DIV_RESET2, RTC_FREQ_SELECT);
+
+ cmos_minutes = CMOS_READ(RTC_MINUTES);
+ if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
+ BCD_TO_BIN(cmos_minutes);
+
+ /*
+ * since we're only adjusting minutes and seconds,
+ * don't interfere with hour overflow. This avoids
+ * messing with unknown time zones but requires your
+ * RTC not to be off by more than 15 minutes
+ */
+ real_seconds = nowtime % 60;
+ real_minutes = nowtime / 60;
+ if (((abs(real_minutes - cmos_minutes) + 15) / 30) & 1)
+ /* correct for half hour time zone */
+ real_minutes += 30;
+ real_minutes %= 60;
+
+ if (abs(real_minutes - cmos_minutes) < 30) {
+ if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+ BIN_TO_BCD(real_seconds);
+ BIN_TO_BCD(real_minutes);
+ }
+ CMOS_WRITE(real_seconds, RTC_SECONDS);
+ CMOS_WRITE(real_minutes, RTC_MINUTES);
+ } else {
+ printk(KERN_WARNING
+ "set_rtc_mmss: can't update from %d to %d\n",
+ cmos_minutes, real_minutes);
+ retval = -1;
+ }
+
+ /* The following flags have to be released exactly in this order,
+ * otherwise the DS12887 (popular MC146818A clone with integrated
+ * battery and quartz) will not reset the oscillator and will not
+ * update precisely 500 ms later. You won't find this mentioned in
+ * the Dallas Semiconductor data sheets, but who believes data
+ * sheets anyway ... -- Markus Kuhn
+ */
+ CMOS_WRITE(save_control, RTC_CONTROL);
+ CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
+ spin_unlock(&rtc_lock);
+
+ return retval;
+}
+
+void check_rtc_time(void)
+{
+ /* the RTC clock just finished ticking over again this second
+ * - if we have an externally synchronized Linux clock, then update
+ * RTC clock accordingly every ~11 minutes. set_rtc_mmss() has to be
+ * called as close as possible to 500 ms before the new second starts.
+ */
+ if ((time_status & STA_UNSYNC) == 0 &&
+ xtime.tv_sec > last_rtc_update + 660 &&
+ xtime.tv_nsec / 1000 >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
+ xtime.tv_nsec / 1000 <= 500000 + ((unsigned) TICK_SIZE) / 2
+ ) {
+ if (set_rtc_mmss(xtime.tv_sec) == 0)
+ last_rtc_update = xtime.tv_sec;
+ else
+ /* do it again in 60s */
+ last_rtc_update = xtime.tv_sec - 600;
+ }
+}
+
+/*
+ * calibrate the TSC clock against the RTC
+ */
+void __init calibrate_clock(void)
+{
+ unsigned long count0, counth, count1;
+ unsigned char status;
+
+ /* make sure the RTC is running and is set to operate in 24hr mode */
+ status = RTSRC;
+ RTCRB |= RTCRB_SET;
+ RTCRB |= RTCRB_TM_24HR;
+ RTCRA |= RTCRA_DVR;
+ RTCRA &= ~RTCRA_DVR;
+ RTCRB &= ~RTCRB_SET;
+
+ /* work out the clock speed by counting clock cycles between ends of
+ * the RTC update cycle - track the RTC through one complete update
+ * cycle (1 second)
+ */
+ startup_timestamp_counter();
+
+ while (!(RTCRA & RTCRA_UIP)) {}
+ while ((RTCRA & RTCRA_UIP)) {}
+
+ count0 = TMTSCBC;
+
+ while (!(RTCRA & RTCRA_UIP)) {}
+
+ counth = TMTSCBC;
+
+ while ((RTCRA & RTCRA_UIP)) {}
+
+ count1 = TMTSCBC;
+
+ shutdown_timestamp_counter();
+
+ MN10300_TSCCLK = count0 - count1; /* the timers count down */
+ mn10300_rtc_update_period = counth - count1;
+ MN10300_TSC_PER_HZ = MN10300_TSCCLK / HZ;
+}
--- /dev/null
+/* MN10300 Semaphore implementation
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/sched.h>
+#include <linux/module.h>
+#include <asm/semaphore.h>
+
+struct sem_waiter {
+ struct list_head list;
+ struct task_struct *task;
+};
+
+#if SEMAPHORE_DEBUG
+void semtrace(struct semaphore *sem, const char *str)
+{
+ if (sem->debug)
+ printk(KERN_DEBUG "[%d] %s({%d,%d})\n",
+ current->pid,
+ str,
+ atomic_read(&sem->count),
+ list_empty(&sem->wait_list) ? 0 : 1);
+}
+#else
+#define semtrace(SEM, STR) do { } while (0)
+#endif
+
+/*
+ * wait for a token to be granted from a semaphore
+ * - entered with lock held and interrupts disabled
+ */
+void __down(struct semaphore *sem, unsigned long flags)
+{
+ struct task_struct *tsk = current;
+ struct sem_waiter waiter;
+
+ semtrace(sem, "Entering __down");
+
+ /* set up my own style of waitqueue */
+ waiter.task = tsk;
+ get_task_struct(tsk);
+
+ list_add_tail(&waiter.list, &sem->wait_list);
+
+ /* we don't need to touch the semaphore struct anymore */
+ spin_unlock_irqrestore(&sem->wait_lock, flags);
+
+ /* wait to be given the semaphore */
+ set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+
+ for (;;) {
+ if (!waiter.task)
+ break;
+ schedule();
+ set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+ }
+
+ tsk->state = TASK_RUNNING;
+ semtrace(sem, "Leaving __down");
+}
+EXPORT_SYMBOL(__down);
+
+/*
+ * interruptibly wait for a token to be granted from a semaphore
+ * - entered with lock held and interrupts disabled
+ */
+int __down_interruptible(struct semaphore *sem, unsigned long flags)
+{
+ struct task_struct *tsk = current;
+ struct sem_waiter waiter;
+ int ret;
+
+ semtrace(sem, "Entering __down_interruptible");
+
+ /* set up my own style of waitqueue */
+ waiter.task = tsk;
+ get_task_struct(tsk);
+
+ list_add_tail(&waiter.list, &sem->wait_list);
+
+ /* we don't need to touch the semaphore struct anymore */
+ set_task_state(tsk, TASK_INTERRUPTIBLE);
+
+ spin_unlock_irqrestore(&sem->wait_lock, flags);
+
+ /* wait to be given the semaphore */
+ ret = 0;
+ for (;;) {
+ if (!waiter.task)
+ break;
+ if (unlikely(signal_pending(current)))
+ goto interrupted;
+ schedule();
+ set_task_state(tsk, TASK_INTERRUPTIBLE);
+ }
+
+ out:
+ tsk->state = TASK_RUNNING;
+ semtrace(sem, "Leaving __down_interruptible");
+ return ret;
+
+ interrupted:
+ spin_lock_irqsave(&sem->wait_lock, flags);
+ list_del(&waiter.list);
+ spin_unlock_irqrestore(&sem->wait_lock, flags);
+
+ ret = 0;
+ if (!waiter.task) {
+ put_task_struct(current);
+ ret = -EINTR;
+ }
+ goto out;
+}
+EXPORT_SYMBOL(__down_interruptible);
+
+/*
+ * release a single token back to a semaphore
+ * - entered with lock held and interrupts disabled
+ */
+void __up(struct semaphore *sem)
+{
+ struct task_struct *tsk;
+ struct sem_waiter *waiter;
+
+ semtrace(sem, "Entering __up");
+
+ /* grant the token to the process at the front of the queue */
+ waiter = list_entry(sem->wait_list.next, struct sem_waiter, list);
+
+ /* We must be careful not to touch 'waiter' after we set ->task = NULL.
+ * It is an allocated on the waiter's stack and may become invalid at
+ * any time after that point (due to a wakeup from another source).
+ */
+ list_del_init(&waiter->list);
+ tsk = waiter->task;
+ smp_mb();
+ waiter->task = NULL;
+ wake_up_process(tsk);
+ put_task_struct(tsk);
+
+ semtrace(sem, "Leaving __up");
+}
+EXPORT_SYMBOL(__up);
--- /dev/null
+/* MN10300 Arch-specific initialisation
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/stddef.h>
+#include <linux/unistd.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/user.h>
+#include <linux/a.out.h>
+#include <linux/tty.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/bootmem.h>
+#include <linux/seq_file.h>
+#include <asm/processor.h>
+#include <linux/console.h>
+#include <asm/uaccess.h>
+#include <asm/system.h>
+#include <asm/setup.h>
+#include <asm/io.h>
+#include <asm/smp.h>
+#include <asm/proc/proc.h>
+#include <asm/busctl-regs.h>
+#include <asm/fpu.h>
+#include <asm/sections.h>
+
+struct mn10300_cpuinfo boot_cpu_data;
+
+/* For PCI or other memory-mapped resources */
+unsigned long pci_mem_start = 0x18000000;
+
+char redboot_command_line[COMMAND_LINE_SIZE] =
+ "console=ttyS0,115200 root=/dev/mtdblock3 rw";
+
+char __initdata redboot_platform_name[COMMAND_LINE_SIZE];
+
+static struct resource code_resource = {
+ .start = 0x100000,
+ .end = 0,
+ .name = "Kernel code",
+};
+
+static struct resource data_resource = {
+ .start = 0,
+ .end = 0,
+ .name = "Kernel data",
+};
+
+static unsigned long __initdata phys_memory_base;
+static unsigned long __initdata phys_memory_end;
+static unsigned long __initdata memory_end;
+unsigned long memory_size;
+
+struct thread_info *__current_ti = &init_thread_union.thread_info;
+struct task_struct *__current = &init_task;
+
+#define mn10300_known_cpus 3
+static const char *const mn10300_cputypes[] = {
+ "am33v1",
+ "am33v2",
+ "am34v1",
+ "unknown"
+};
+
+/*
+ *
+ */
+static void __init parse_mem_cmdline(char **cmdline_p)
+{
+ char *from, *to, c;
+
+ /* save unparsed command line copy for /proc/cmdline */
+ strcpy(boot_command_line, redboot_command_line);
+
+ /* see if there's an explicit memory size option */
+ from = redboot_command_line;
+ to = redboot_command_line;
+ c = ' ';
+
+ for (;;) {
+ if (c == ' ' && !memcmp(from, "mem=", 4)) {
+ if (to != redboot_command_line)
+ to--;
+ memory_size = memparse(from + 4, &from);
+ }
+
+ c = *(from++);
+ if (!c)
+ break;
+
+ *(to++) = c;
+ }
+
+ *to = '\0';
+ *cmdline_p = redboot_command_line;
+
+ if (memory_size == 0)
+ panic("Memory size not known\n");
+
+ memory_end = (unsigned long) CONFIG_KERNEL_RAM_BASE_ADDRESS +
+ memory_size;
+ if (memory_end > phys_memory_end)
+ memory_end = phys_memory_end;
+}
+
+/*
+ * architecture specific setup
+ */
+void __init setup_arch(char **cmdline_p)
+{
+ unsigned long bootmap_size;
+ unsigned long kstart_pfn, start_pfn, free_pfn, end_pfn;
+
+ cpu_init();
+ unit_setup();
+ parse_mem_cmdline(cmdline_p);
+
+ init_mm.start_code = (unsigned long)&_text;
+ init_mm.end_code = (unsigned long) &_etext;
+ init_mm.end_data = (unsigned long) &_edata;
+ init_mm.brk = (unsigned long) &_end;
+
+ code_resource.start = virt_to_bus(&_text);
+ code_resource.end = virt_to_bus(&_etext)-1;
+ data_resource.start = virt_to_bus(&_etext);
+ data_resource.end = virt_to_bus(&_edata)-1;
+
+#define PFN_UP(x) (((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
+#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
+#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
+
+ start_pfn = (CONFIG_KERNEL_RAM_BASE_ADDRESS >> PAGE_SHIFT);
+ kstart_pfn = PFN_UP(__pa(&_text));
+ free_pfn = PFN_UP(__pa(&_end));
+ end_pfn = PFN_DOWN(__pa(memory_end));
+
+ bootmap_size = init_bootmem_node(&contig_page_data,
+ free_pfn,
+ start_pfn,
+ end_pfn);
+
+ if (kstart_pfn > start_pfn)
+ free_bootmem(PFN_PHYS(start_pfn),
+ PFN_PHYS(kstart_pfn - start_pfn));
+
+ free_bootmem(PFN_PHYS(free_pfn),
+ PFN_PHYS(end_pfn - free_pfn));
+
+ /* If interrupt vector table is in main ram, then we need to
+ reserve the page it is occupying. */
+ if (CONFIG_INTERRUPT_VECTOR_BASE >= CONFIG_KERNEL_RAM_BASE_ADDRESS &&
+ CONFIG_INTERRUPT_VECTOR_BASE < memory_end)
+ reserve_bootmem(CONFIG_INTERRUPT_VECTOR_BASE, 1,
+ BOOTMEM_DEFAULT);
+
+ reserve_bootmem(PAGE_ALIGN(PFN_PHYS(free_pfn)), bootmap_size,
+ BOOTMEM_DEFAULT);
+
+#ifdef CONFIG_VT
+#if defined(CONFIG_VGA_CONSOLE)
+ conswitchp = &vga_con;
+#elif defined(CONFIG_DUMMY_CONSOLE)
+ conswitchp = &dummy_con;
+#endif
+#endif
+
+ paging_init();
+}
+
+/*
+ * perform CPU initialisation
+ */
+void __init cpu_init(void)
+{
+ unsigned long cpurev = CPUREV, type;
+ unsigned long base, size;
+
+ type = (CPUREV & CPUREV_TYPE) >> CPUREV_TYPE_S;
+ if (type > mn10300_known_cpus)
+ type = mn10300_known_cpus;
+
+ printk(KERN_INFO "Matsushita %s, rev %ld\n",
+ mn10300_cputypes[type],
+ (cpurev & CPUREV_REVISION) >> CPUREV_REVISION_S);
+
+ /* determine the memory size and base from the memory controller regs */
+ memory_size = 0;
+
+ base = SDBASE(0);
+ if (base & SDBASE_CE) {
+ size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;
+ size = ~size + 1;
+ base &= SDBASE_CBA;
+
+ printk(KERN_INFO "SDRAM[0]: %luMb @%08lx\n", size >> 20, base);
+ memory_size += size;
+ phys_memory_base = base;
+ }
+
+ base = SDBASE(1);
+ if (base & SDBASE_CE) {
+ size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT;
+ size = ~size + 1;
+ base &= SDBASE_CBA;
+
+ printk(KERN_INFO "SDRAM[1]: %luMb @%08lx\n", size >> 20, base);
+ memory_size += size;
+ if (phys_memory_base == 0)
+ phys_memory_base = base;
+ }
+
+ phys_memory_end = phys_memory_base + memory_size;
+
+#ifdef CONFIG_FPU
+ fpu_init_state();
+#endif
+}
+
+/*
+ * Get CPU information for use by the procfs.
+ */
+static int show_cpuinfo(struct seq_file *m, void *v)
+{
+ unsigned long cpurev = CPUREV, type, icachesz, dcachesz;
+
+ type = (CPUREV & CPUREV_TYPE) >> CPUREV_TYPE_S;
+ if (type > mn10300_known_cpus)
+ type = mn10300_known_cpus;
+
+ icachesz =
+ ((cpurev & CPUREV_ICWAY ) >> CPUREV_ICWAY_S) *
+ ((cpurev & CPUREV_ICSIZE) >> CPUREV_ICSIZE_S) *
+ 1024;
+
+ dcachesz =
+ ((cpurev & CPUREV_DCWAY ) >> CPUREV_DCWAY_S) *
+ ((cpurev & CPUREV_DCSIZE) >> CPUREV_DCSIZE_S) *
+ 1024;
+
+ seq_printf(m,
+ "processor : 0\n"
+ "vendor_id : Matsushita\n"
+ "cpu core : %s\n"
+ "cpu rev : %lu\n"
+ "model name : " PROCESSOR_MODEL_NAME "\n"
+ "icache size: %lu\n"
+ "dcache size: %lu\n",
+ mn10300_cputypes[type],
+ (cpurev & CPUREV_REVISION) >> CPUREV_REVISION_S,
+ icachesz,
+ dcachesz
+ );
+
+ seq_printf(m,
+ "ioclk speed: %lu.%02luMHz\n"
+ "bogomips : %lu.%02lu\n\n",
+ MN10300_IOCLK / 1000000,
+ (MN10300_IOCLK / 10000) % 100,
+ loops_per_jiffy / (500000 / HZ),
+ (loops_per_jiffy / (5000 / HZ)) % 100
+ );
+
+ return 0;
+}
+
+static void *c_start(struct seq_file *m, loff_t *pos)
+{
+ return *pos < NR_CPUS ? cpu_data + *pos : NULL;
+}
+
+static void *c_next(struct seq_file *m, void *v, loff_t *pos)
+{
+ ++*pos;
+ return c_start(m, pos);
+}
+
+static void c_stop(struct seq_file *m, void *v)
+{
+}
+
+struct seq_operations cpuinfo_op = {
+ .start = c_start,
+ .next = c_next,
+ .stop = c_stop,
+ .show = show_cpuinfo,
+};
--- /dev/null
+/* MN10300 Signal frame definitions
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+struct sigframe
+{
+ void (*pretcode)(void);
+ int sig;
+ struct sigcontext *psc;
+ struct sigcontext sc;
+ struct fpucontext fpuctx;
+ unsigned long extramask[_NSIG_WORDS-1];
+ char retcode[8];
+};
+
+struct rt_sigframe
+{
+ void (*pretcode)(void);
+ int sig;
+ struct siginfo *pinfo;
+ void *puc;
+ struct siginfo info;
+ struct ucontext uc;
+ struct fpucontext fpuctx;
+ char retcode[8];
+};
--- /dev/null
+/* MN10300 Signal handling
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/errno.h>
+#include <linux/wait.h>
+#include <linux/ptrace.h>
+#include <linux/unistd.h>
+#include <linux/stddef.h>
+#include <linux/tty.h>
+#include <linux/personality.h>
+#include <linux/suspend.h>
+#include <asm/cacheflush.h>
+#include <asm/ucontext.h>
+#include <asm/uaccess.h>
+#include <asm/fpu.h>
+#include "sigframe.h"
+
+#define DEBUG_SIG 0
+
+#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
+
+/*
+ * atomically swap in the new signal mask, and wait for a signal.
+ */
+asmlinkage long sys_sigsuspend(int history0, int history1, old_sigset_t mask)
+{
+ mask &= _BLOCKABLE;
+ spin_lock_irq(¤t->sighand->siglock);
+ current->saved_sigmask = current->blocked;
+ siginitset(¤t->blocked, mask);
+ recalc_sigpending();
+ spin_unlock_irq(¤t->sighand->siglock);
+
+ current->state = TASK_INTERRUPTIBLE;
+ schedule();
+ set_thread_flag(TIF_RESTORE_SIGMASK);
+ return -ERESTARTNOHAND;
+}
+
+/*
+ * set signal action syscall
+ */
+asmlinkage long sys_sigaction(int sig,
+ const struct old_sigaction __user *act,
+ struct old_sigaction __user *oact)
+{
+ struct k_sigaction new_ka, old_ka;
+ int ret;
+
+ if (act) {
+ old_sigset_t mask;
+ if (verify_area(VERIFY_READ, act, sizeof(*act)) ||
+ __get_user(new_ka.sa.sa_handler, &act->sa_handler) ||
+ __get_user(new_ka.sa.sa_restorer, &act->sa_restorer))
+ return -EFAULT;
+ __get_user(new_ka.sa.sa_flags, &act->sa_flags);
+ __get_user(mask, &act->sa_mask);
+ siginitset(&new_ka.sa.sa_mask, mask);
+ }
+
+ ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
+
+ if (!ret && oact) {
+ if (verify_area(VERIFY_WRITE, oact, sizeof(*oact)) ||
+ __put_user(old_ka.sa.sa_handler, &oact->sa_handler) ||
+ __put_user(old_ka.sa.sa_restorer, &oact->sa_restorer))
+ return -EFAULT;
+ __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
+ __put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
+ }
+
+ return ret;
+}
+
+/*
+ * set alternate signal stack syscall
+ */
+asmlinkage long sys_sigaltstack(const stack_t __user *uss, stack_t *uoss)
+{
+ return do_sigaltstack(uss, uoss, __frame->sp);
+}
+
+/*
+ * do a signal return; undo the signal stack.
+ */
+static int restore_sigcontext(struct pt_regs *regs,
+ struct sigcontext __user *sc, long *_d0)
+{
+ unsigned int err = 0;
+
+ if (is_using_fpu(current))
+ fpu_kill_state(current);
+
+#define COPY(x) err |= __get_user(regs->x, &sc->x)
+ COPY(d1); COPY(d2); COPY(d3);
+ COPY(a0); COPY(a1); COPY(a2); COPY(a3);
+ COPY(e0); COPY(e1); COPY(e2); COPY(e3);
+ COPY(e4); COPY(e5); COPY(e6); COPY(e7);
+ COPY(lar); COPY(lir);
+ COPY(mdr); COPY(mdrq);
+ COPY(mcvf); COPY(mcrl); COPY(mcrh);
+ COPY(sp); COPY(pc);
+#undef COPY
+
+ {
+ unsigned int tmpflags;
+#ifndef CONFIG_MN10300_USING_JTAG
+#define USER_EPSW (EPSW_FLAG_Z | EPSW_FLAG_N | EPSW_FLAG_C | EPSW_FLAG_V | \
+ EPSW_T | EPSW_nAR)
+#else
+#define USER_EPSW (EPSW_FLAG_Z | EPSW_FLAG_N | EPSW_FLAG_C | EPSW_FLAG_V | \
+ EPSW_nAR)
+#endif
+ err |= __get_user(tmpflags, &sc->epsw);
+ regs->epsw = (regs->epsw & ~USER_EPSW) |
+ (tmpflags & USER_EPSW);
+ regs->orig_d0 = -1; /* disable syscall checks */
+ }
+
+ {
+ struct fpucontext *buf;
+ err |= __get_user(buf, &sc->fpucontext);
+ if (buf) {
+ if (verify_area(VERIFY_READ, buf, sizeof(*buf)))
+ goto badframe;
+ err |= fpu_restore_sigcontext(buf);
+ }
+ }
+
+ err |= __get_user(*_d0, &sc->d0);
+ return err;
+
+badframe:
+ return 1;
+}
+
+/*
+ * standard signal return syscall
+ */
+asmlinkage long sys_sigreturn(void)
+{
+ struct sigframe __user *frame = (struct sigframe __user *) __frame->sp;
+ sigset_t set;
+ long d0;
+
+ if (verify_area(VERIFY_READ, frame, sizeof(*frame)))
+ goto badframe;
+ if (__get_user(set.sig[0], &frame->sc.oldmask))
+ goto badframe;
+
+ if (_NSIG_WORDS > 1 &&
+ __copy_from_user(&set.sig[1], &frame->extramask,
+ sizeof(frame->extramask)))
+ goto badframe;
+
+ sigdelsetmask(&set, ~_BLOCKABLE);
+ spin_lock_irq(¤t->sighand->siglock);
+ current->blocked = set;
+ recalc_sigpending();
+ spin_unlock_irq(¤t->sighand->siglock);
+
+ if (restore_sigcontext(__frame, &frame->sc, &d0))
+ goto badframe;
+
+ return d0;
+
+badframe:
+ force_sig(SIGSEGV, current);
+ return 0;
+}
+
+/*
+ * realtime signal return syscall
+ */
+asmlinkage long sys_rt_sigreturn(void)
+{
+ struct rt_sigframe __user *frame =
+ (struct rt_sigframe __user *) __frame->sp;
+ sigset_t set;
+ unsigned long d0;
+
+ if (verify_area(VERIFY_READ, frame, sizeof(*frame)))
+ goto badframe;
+ if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
+ goto badframe;
+
+ sigdelsetmask(&set, ~_BLOCKABLE);
+ spin_lock_irq(¤t->sighand->siglock);
+ current->blocked = set;
+ recalc_sigpending();
+ spin_unlock_irq(¤t->sighand->siglock);
+
+ if (restore_sigcontext(__frame, &frame->uc.uc_mcontext, &d0))
+ goto badframe;
+
+ if (do_sigaltstack(&frame->uc.uc_stack, NULL, __frame->sp) == -EFAULT)
+ goto badframe;
+
+ return d0;
+
+badframe:
+ force_sig(SIGSEGV, current);
+ return 0;
+}
+
+/*
+ * store the userspace context into a signal frame
+ */
+static int setup_sigcontext(struct sigcontext __user *sc,
+ struct fpucontext *fpuctx,
+ struct pt_regs *regs,
+ unsigned long mask)
+{
+ int tmp, err = 0;
+
+#define COPY(x) err |= __put_user(regs->x, &sc->x)
+ COPY(d0); COPY(d1); COPY(d2); COPY(d3);
+ COPY(a0); COPY(a1); COPY(a2); COPY(a3);
+ COPY(e0); COPY(e1); COPY(e2); COPY(e3);
+ COPY(e4); COPY(e5); COPY(e6); COPY(e7);
+ COPY(lar); COPY(lir);
+ COPY(mdr); COPY(mdrq);
+ COPY(mcvf); COPY(mcrl); COPY(mcrh);
+ COPY(sp); COPY(epsw); COPY(pc);
+#undef COPY
+
+ tmp = fpu_setup_sigcontext(fpuctx);
+ if (tmp < 0)
+ err = 1;
+ else
+ err |= __put_user(tmp ? fpuctx : NULL, &sc->fpucontext);
+
+ /* non-iBCS2 extensions.. */
+ err |= __put_user(mask, &sc->oldmask);
+
+ return err;
+}
+
+/*
+ * determine which stack to use..
+ */
+static inline void __user *get_sigframe(struct k_sigaction *ka,
+ struct pt_regs *regs,
+ size_t frame_size)
+{
+ unsigned long sp;
+
+ /* default to using normal stack */
+ sp = regs->sp;
+
+ /* this is the X/Open sanctioned signal stack switching. */
+ if (ka->sa.sa_flags & SA_ONSTACK) {
+ if (!on_sig_stack(sp))
+ sp = current->sas_ss_sp + current->sas_ss_size;
+ }
+
+ return (void __user *) ((sp - frame_size) & ~7UL);
+}
+
+/*
+ * set up a normal signal frame
+ */
+static int setup_frame(int sig, struct k_sigaction *ka, sigset_t *set,
+ struct pt_regs *regs)
+{
+ struct sigframe __user *frame;
+ int rsig;
+
+ frame = get_sigframe(ka, regs, sizeof(*frame));
+
+ if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
+ goto give_sigsegv;
+
+ rsig = sig;
+ if (sig < 32 &&
+ current_thread_info()->exec_domain &&
+ current_thread_info()->exec_domain->signal_invmap)
+ rsig = current_thread_info()->exec_domain->signal_invmap[sig];
+
+ if (__put_user(rsig, &frame->sig) < 0 ||
+ __put_user(&frame->sc, &frame->psc) < 0)
+ goto give_sigsegv;
+
+ if (setup_sigcontext(&frame->sc, &frame->fpuctx, regs, set->sig[0]))
+ goto give_sigsegv;
+
+ if (_NSIG_WORDS > 1) {
+ if (__copy_to_user(frame->extramask, &set->sig[1],
+ sizeof(frame->extramask)))
+ goto give_sigsegv;
+ }
+
+ /* set up to return from userspace. If provided, use a stub already in
+ * userspace */
+ if (ka->sa.sa_flags & SA_RESTORER) {
+ if (__put_user(ka->sa.sa_restorer, &frame->pretcode))
+ goto give_sigsegv;
+ } else {
+ if (__put_user((void (*)(void))frame->retcode,
+ &frame->pretcode))
+ goto give_sigsegv;
+ /* this is mov $,d0; syscall 0 */
+ if (__put_user(0x2c, (char *)(frame->retcode + 0)) ||
+ __put_user(__NR_sigreturn, (char *)(frame->retcode + 1)) ||
+ __put_user(0x00, (char *)(frame->retcode + 2)) ||
+ __put_user(0xf0, (char *)(frame->retcode + 3)) ||
+ __put_user(0xe0, (char *)(frame->retcode + 4)))
+ goto give_sigsegv;
+ flush_icache_range((unsigned long) frame->retcode,
+ (unsigned long) frame->retcode + 5);
+ }
+
+ /* set up registers for signal handler */
+ regs->sp = (unsigned long) frame;
+ regs->pc = (unsigned long) ka->sa.sa_handler;
+ regs->d0 = sig;
+ regs->d1 = (unsigned long) &frame->sc;
+
+ set_fs(USER_DS);
+
+ /* the tracer may want to single-step inside the handler */
+ if (test_thread_flag(TIF_SINGLESTEP))
+ ptrace_notify(SIGTRAP);
+
+#if DEBUG_SIG
+ printk(KERN_DEBUG "SIG deliver %d (%s:%d): sp=%p pc=%lx ra=%p\n",
+ sig, current->comm, current->pid, frame, regs->pc,
+ frame->pretcode);
+#endif
+
+ return 0;
+
+give_sigsegv:
+ force_sig(SIGSEGV, current);
+ return -EFAULT;
+}
+
+/*
+ * set up a realtime signal frame
+ */
+static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
+ sigset_t *set, struct pt_regs *regs)
+{
+ struct rt_sigframe __user *frame;
+ int rsig;
+
+ frame = get_sigframe(ka, regs, sizeof(*frame));
+
+ if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
+ goto give_sigsegv;
+
+ rsig = sig;
+ if (sig < 32 &&
+ current_thread_info()->exec_domain &&
+ current_thread_info()->exec_domain->signal_invmap)
+ rsig = current_thread_info()->exec_domain->signal_invmap[sig];
+
+ if (__put_user(rsig, &frame->sig) ||
+ __put_user(&frame->info, &frame->pinfo) ||
+ __put_user(&frame->uc, &frame->puc) ||
+ copy_siginfo_to_user(&frame->info, info))
+ goto give_sigsegv;
+
+ /* create the ucontext. */
+ if (__put_user(0, &frame->uc.uc_flags) ||
+ __put_user(0, &frame->uc.uc_link) ||
+ __put_user((void *)current->sas_ss_sp, &frame->uc.uc_stack.ss_sp) ||
+ __put_user(sas_ss_flags(regs->sp), &frame->uc.uc_stack.ss_flags) ||
+ __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size) ||
+ setup_sigcontext(&frame->uc.uc_mcontext,
+ &frame->fpuctx, regs, set->sig[0]) ||
+ __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set)))
+ goto give_sigsegv;
+
+ /* set up to return from userspace. If provided, use a stub already in
+ * userspace */
+ if (ka->sa.sa_flags & SA_RESTORER) {
+ if (__put_user(ka->sa.sa_restorer, &frame->pretcode))
+ goto give_sigsegv;
+ } else {
+ if (__put_user((void(*)(void))frame->retcode,
+ &frame->pretcode) ||
+ /* This is mov $,d0; syscall 0 */
+ __put_user(0x2c, (char *)(frame->retcode + 0)) ||
+ __put_user(__NR_rt_sigreturn,
+ (char *)(frame->retcode + 1)) ||
+ __put_user(0x00, (char *)(frame->retcode + 2)) ||
+ __put_user(0xf0, (char *)(frame->retcode + 3)) ||
+ __put_user(0xe0, (char *)(frame->retcode + 4)))
+ goto give_sigsegv;
+
+ flush_icache_range((u_long) frame->retcode,
+ (u_long) frame->retcode + 5);
+ }
+
+ /* Set up registers for signal handler */
+ regs->sp = (unsigned long) frame;
+ regs->pc = (unsigned long) ka->sa.sa_handler;
+ regs->d0 = sig;
+ regs->d1 = (long) &frame->info;
+
+ set_fs(USER_DS);
+
+ /* the tracer may want to single-step inside the handler */
+ if (test_thread_flag(TIF_SINGLESTEP))
+ ptrace_notify(SIGTRAP);
+
+#if DEBUG_SIG
+ printk(KERN_DEBUG "SIG deliver %d (%s:%d): sp=%p pc=%lx ra=%p\n",
+ sig, current->comm, current->pid, frame, regs->pc,
+ frame->pretcode);
+#endif
+
+ return 0;
+
+give_sigsegv:
+ force_sig(SIGSEGV, current);
+ return -EFAULT;
+}
+
+/*
+ * handle the actual delivery of a signal to userspace
+ */
+static int handle_signal(int sig,
+ siginfo_t *info, struct k_sigaction *ka,
+ sigset_t *oldset, struct pt_regs *regs)
+{
+ int ret;
+
+ /* Are we from a system call? */
+ if (regs->orig_d0 >= 0) {
+ /* If so, check system call restarting.. */
+ switch (regs->d0) {
+ case -ERESTART_RESTARTBLOCK:
+ case -ERESTARTNOHAND:
+ regs->d0 = -EINTR;
+ break;
+
+ case -ERESTARTSYS:
+ if (!(ka->sa.sa_flags & SA_RESTART)) {
+ regs->d0 = -EINTR;
+ break;
+ }
+
+ /* fallthrough */
+ case -ERESTARTNOINTR:
+ regs->d0 = regs->orig_d0;
+ regs->pc -= 2;
+ }
+ }
+
+ /* Set up the stack frame */
+ if (ka->sa.sa_flags & SA_SIGINFO)
+ ret = setup_rt_frame(sig, ka, info, oldset, regs);
+ else
+ ret = setup_frame(sig, ka, oldset, regs);
+
+ if (ret == 0) {
+ spin_lock_irq(¤t->sighand->siglock);
+ sigorsets(¤t->blocked, ¤t->blocked,
+ &ka->sa.sa_mask);
+ if (!(ka->sa.sa_flags & SA_NODEFER))
+ sigaddset(¤t->blocked, sig);
+ recalc_sigpending();
+ spin_unlock_irq(¤t->sighand->siglock);
+ }
+
+ return ret;
+}
+
+/*
+ * handle a potential signal
+ */
+static void do_signal(struct pt_regs *regs)
+{
+ struct k_sigaction ka;
+ siginfo_t info;
+ sigset_t *oldset;
+ int signr;
+
+ /* we want the common case to go fast, which is why we may in certain
+ * cases get here from kernel mode */
+ if (!user_mode(regs))
+ return;
+
+ if (test_thread_flag(TIF_RESTORE_SIGMASK))
+ oldset = ¤t->saved_sigmask;
+ else
+ oldset = ¤t->blocked;
+
+ signr = get_signal_to_deliver(&info, &ka, regs, NULL);
+ if (signr > 0) {
+ if (handle_signal(signr, &info, &ka, oldset, regs) == 0) {
+ /* a signal was successfully delivered; the saved
+ * sigmask will have been stored in the signal frame,
+ * and will be restored by sigreturn, so we can simply
+ * clear the TIF_RESTORE_SIGMASK flag */
+ if (test_thread_flag(TIF_RESTORE_SIGMASK))
+ clear_thread_flag(TIF_RESTORE_SIGMASK);
+ }
+
+ return;
+ }
+
+ /* did we come from a system call? */
+ if (regs->orig_d0 >= 0) {
+ /* restart the system call - no handlers present */
+ switch (regs->d0) {
+ case -ERESTARTNOHAND:
+ case -ERESTARTSYS:
+ case -ERESTARTNOINTR:
+ regs->d0 = regs->orig_d0;
+ regs->pc -= 2;
+ break;
+
+ case -ERESTART_RESTARTBLOCK:
+ regs->d0 = __NR_restart_syscall;
+ regs->pc -= 2;
+ break;
+ }
+ }
+
+ /* if there's no signal to deliver, we just put the saved sigmask
+ * back */
+ if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+ clear_thread_flag(TIF_RESTORE_SIGMASK);
+ sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL);
+ }
+}
+
+/*
+ * notification of userspace execution resumption
+ * - triggered by current->work.notify_resume
+ */
+asmlinkage void do_notify_resume(struct pt_regs *regs, u32 thread_info_flags)
+{
+ /* Pending single-step? */
+ if (thread_info_flags & _TIF_SINGLESTEP) {
+#ifndef CONFIG_MN10300_USING_JTAG
+ regs->epsw |= EPSW_T;
+ clear_thread_flag(TIF_SINGLESTEP);
+#else
+ BUG(); /* no h/w single-step if using JTAG unit */
+#endif
+ }
+
+ /* deal with pending signal delivery */
+ if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
+ do_signal(regs);
+}
--- /dev/null
+###############################################################################
+#
+# MN10300 Context switch operation
+#
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Written by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+###############################################################################
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/thread_info.h>
+#include <asm/cpu-regs.h>
+
+ .text
+
+###############################################################################
+#
+# struct task_struct *__switch_to(struct thread_struct *prev,
+# struct thread_struct *next,
+# struct task_struct *prev_task)
+#
+###############################################################################
+ENTRY(__switch_to)
+ movm [d2,d3,a2,a3,exreg1],(sp)
+ or EPSW_NMID,epsw
+
+ mov (44,sp),d2
+
+ mov d0,a0
+ mov d1,a1
+
+ # save prev context
+ mov (__frame),d0
+ mov d0,(THREAD_FRAME,a0)
+ mov __switch_back,d0
+ mov d0,(THREAD_PC,a0)
+ mov sp,a2
+ mov a2,(THREAD_SP,a0)
+ mov a3,(THREAD_A3,a0)
+
+ mov (THREAD_A3,a1),a3
+ mov (THREAD_SP,a1),a2
+
+ # switch
+ mov a2,sp
+
+ # load next context
+ GET_THREAD_INFO a2
+ mov a2,(__current_ti)
+ mov (TI_task,a2),a2
+ mov a2,(__current)
+#ifdef CONFIG_MN10300_CURRENT_IN_E2
+ mov a2,e2
+#endif
+
+ mov (THREAD_FRAME,a1),a2
+ mov a2,(__frame)
+ mov (THREAD_PC,a1),a2
+ mov d2,d0 # for ret_from_fork
+ mov d0,a0 # for __switch_to
+
+ jmp (a2)
+
+__switch_back:
+ and ~EPSW_NMID,epsw
+ ret [d2,d3,a2,a3,exreg1],32
--- /dev/null
+/* MN10300 Weird system calls
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/syscalls.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/sem.h>
+#include <linux/msg.h>
+#include <linux/shm.h>
+#include <linux/stat.h>
+#include <linux/mman.h>
+#include <linux/file.h>
+#include <linux/utsname.h>
+#include <linux/syscalls.h>
+#include <linux/tty.h>
+
+#include <asm/uaccess.h>
+
+#define MIN_MAP_ADDR PAGE_SIZE /* minimum fixed mmap address */
+
+/*
+ * sys_pipe() is the normal C calling standard for creating
+ * a pipe. It's not the way Unix traditionally does this, though.
+ */
+asmlinkage long sys_pipe(unsigned long __user *fildes)
+{
+ int fd[2];
+ int error;
+
+ error = do_pipe(fd);
+ if (!error) {
+ if (copy_to_user(fildes, fd, 2 * sizeof(int)))
+ error = -EFAULT;
+ }
+ return error;
+}
+
+/*
+ * memory mapping syscall
+ */
+asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
+ unsigned long prot, unsigned long flags,
+ unsigned long fd, unsigned long pgoff)
+{
+ struct file *file = NULL;
+ long error = -EINVAL;
+
+ flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
+
+ if (flags & MAP_FIXED && addr < MIN_MAP_ADDR)
+ goto out;
+
+ error = -EBADF;
+ if (!(flags & MAP_ANONYMOUS)) {
+ file = fget(fd);
+ if (!file)
+ goto out;
+ }
+
+ down_write(¤t->mm->mmap_sem);
+ error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
+ up_write(¤t->mm->mmap_sem);
+
+ if (file)
+ fput(file);
+out:
+ return error;
+}
+
+asmlinkage long old_mmap(unsigned long addr, unsigned long len,
+ unsigned long prot, unsigned long flags,
+ unsigned long fd, unsigned long offset)
+{
+ if (offset & ~PAGE_MASK)
+ return -EINVAL;
+ return sys_mmap2(addr, len, prot, flags, fd, offset >> PAGE_SHIFT);
+}
+
+struct sel_arg_struct {
+ unsigned long n;
+ fd_set *inp;
+ fd_set *outp;
+ fd_set *exp;
+ struct timeval *tvp;
+};
+
+asmlinkage int old_select(struct sel_arg_struct __user *arg)
+{
+ struct sel_arg_struct a;
+
+ if (copy_from_user(&a, arg, sizeof(a)))
+ return -EFAULT;
+ /* sys_select() does the appropriate kernel locking */
+ return sys_select(a.n, a.inp, a.outp, a.exp, a.tvp);
+}
+
+/*
+ * sys_ipc() is the de-multiplexer for the SysV IPC calls..
+ *
+ * This is really horribly ugly.
+ */
+asmlinkage long sys_ipc(uint call, int first, int second,
+ int third, void __user *ptr, long fifth)
+{
+ int version, ret;
+
+ version = call >> 16; /* hack for backward compatibility */
+ call &= 0xffff;
+
+ switch (call) {
+ case SEMOP:
+ return sys_semtimedop(first, (struct sembuf __user *)ptr,
+ second, NULL);
+ case SEMTIMEDOP:
+ return sys_semtimedop(first, (struct sembuf __user *)ptr,
+ second,
+ (const struct timespec __user *)fifth);
+ case SEMGET:
+ return sys_semget(first, second, third);
+ case SEMCTL: {
+ union semun fourth;
+ if (!ptr)
+ return -EINVAL;
+ if (get_user(fourth.__pad, (void __user * __user *) ptr))
+ return -EFAULT;
+ return sys_semctl(first, second, third, fourth);
+ }
+
+ case MSGSND:
+ return sys_msgsnd(first, (struct msgbuf __user *) ptr,
+ second, third);
+ case MSGRCV:
+ switch (version) {
+ case 0: {
+ struct ipc_kludge tmp;
+ if (!ptr)
+ return -EINVAL;
+
+ if (copy_from_user(&tmp,
+ (struct ipc_kludge __user *) ptr,
+ sizeof(tmp)))
+ return -EFAULT;
+ return sys_msgrcv(first, tmp.msgp, second,
+ tmp.msgtyp, third);
+ }
+ default:
+ return sys_msgrcv(first,
+ (struct msgbuf __user *) ptr,
+ second, fifth, third);
+ }
+ case MSGGET:
+ return sys_msgget((key_t) first, second);
+ case MSGCTL:
+ return sys_msgctl(first, second,
+ (struct msqid_ds __user *) ptr);
+
+ case SHMAT:
+ switch (version) {
+ default: {
+ ulong raddr;
+ ret = do_shmat(first, (char __user *) ptr, second,
+ &raddr);
+ if (ret)
+ return ret;
+ return put_user(raddr, (ulong *) third);
+ }
+ case 1: /* iBCS2 emulator entry point */
+ if (!segment_eq(get_fs(), get_ds()))
+ return -EINVAL;
+ return do_shmat(first, (char __user *) ptr, second,
+ (ulong *) third);
+ }
+ case SHMDT:
+ return sys_shmdt((char __user *)ptr);
+ case SHMGET:
+ return sys_shmget(first, second, third);
+ case SHMCTL:
+ return sys_shmctl(first, second,
+ (struct shmid_ds __user *) ptr);
+ default:
+ return -EINVAL;
+ }
+}
--- /dev/null
+/* MN10300 Low level time management
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ * - Derived from arch/i386/kernel/time.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/profile.h>
+#include <asm/irq.h>
+#include <asm/div64.h>
+#include <asm/processor.h>
+#include <asm/intctl-regs.h>
+#include <asm/rtc.h>
+
+#ifdef CONFIG_MN10300_RTC
+unsigned long mn10300_ioclk; /* system I/O clock frequency */
+unsigned long mn10300_iobclk; /* system I/O clock frequency */
+unsigned long mn10300_tsc_per_HZ; /* number of ioclks per jiffy */
+#endif /* CONFIG_MN10300_RTC */
+
+static unsigned long mn10300_last_tsc; /* time-stamp counter at last time
+ * interrupt occurred */
+
+static irqreturn_t timer_interrupt(int irq, void *dev_id);
+
+static struct irqaction timer_irq = {
+ .handler = timer_interrupt,
+ .flags = IRQF_DISABLED | IRQF_SHARED | IRQF_TIMER,
+ .mask = CPU_MASK_NONE,
+ .name = "timer",
+};
+
+/*
+ * scheduler clock - returns current time in nanosec units.
+ */
+unsigned long long sched_clock(void)
+{
+ union {
+ unsigned long long l;
+ u32 w[2];
+ } quot;
+
+ quot.w[0] = mn10300_last_tsc - get_cycles();
+ quot.w[1] = 1000000000;
+
+ asm("mulu %2,%3,%0,%1"
+ : "=r"(quot.w[1]), "=r"(quot.w[0])
+ : "0"(quot.w[1]), "1"(quot.w[0])
+ : "cc");
+
+ do_div(quot.l, MN10300_TSCCLK);
+
+ return quot.l;
+}
+
+/*
+ * advance the kernel's time keeping clocks (xtime and jiffies)
+ * - we use Timer 0 & 1 cascaded as a clock to nudge us the next time
+ * there's a need to update
+ */
+static irqreturn_t timer_interrupt(int irq, void *dev_id)
+{
+ unsigned tsc, elapse;
+
+ write_seqlock(&xtime_lock);
+
+ while (tsc = get_cycles(),
+ elapse = mn10300_last_tsc - tsc, /* time elapsed since last
+ * tick */
+ elapse > MN10300_TSC_PER_HZ
+ ) {
+ mn10300_last_tsc -= MN10300_TSC_PER_HZ;
+
+ /* advance the kernel's time tracking system */
+ profile_tick(CPU_PROFILING);
+ do_timer(1);
+ update_process_times(user_mode(get_irq_regs()));
+ check_rtc_time();
+ }
+
+ write_sequnlock(&xtime_lock);
+ return IRQ_HANDLED;
+}
+
+/*
+ * initialise the various timers used by the main part of the kernel
+ */
+void __init time_init(void)
+{
+ /* we need the prescalar running to be able to use IOCLK/8
+ * - IOCLK runs at 1/4 (ST5 open) or 1/8 (ST5 closed) internal CPU clock
+ * - IOCLK runs at Fosc rate (crystal speed)
+ */
+ TMPSCNT |= TMPSCNT_ENABLE;
+
+ startup_timestamp_counter();
+
+ printk(KERN_INFO
+ "timestamp counter I/O clock running at %lu.%02lu"
+ " (calibrated against RTC)\n",
+ MN10300_TSCCLK / 1000000, (MN10300_TSCCLK / 10000) % 100);
+
+ xtime.tv_sec = get_initial_rtc_time();
+ xtime.tv_nsec = 0;
+
+ mn10300_last_tsc = TMTSCBC;
+
+ /* use timer 0 & 1 cascaded to tick at as close to HZ as possible */
+ setup_irq(TMJCIRQ, &timer_irq);
+
+ set_intr_level(TMJCIRQ, TMJCICR_LEVEL);
+
+ startup_jiffies_counter();
+
+#ifdef CONFIG_MN10300_WD_TIMER
+ /* start the watchdog timer */
+ watchdog_go();
+#endif
+}
--- /dev/null
+/* MN10300 Exception handling
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Modified by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/ptrace.h>
+#include <linux/timer.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/kallsyms.h>
+#include <linux/pci.h>
+#include <linux/kdebug.h>
+#include <linux/bug.h>
+#include <linux/irq.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/atomic.h>
+#include <asm/smp.h>
+#include <asm/pgalloc.h>
+#include <asm/cacheflush.h>
+#include <asm/cpu-regs.h>
+#include <asm/busctl-regs.h>
+#include <asm/unit/leds.h>
+#include <asm/fpu.h>
+#include <asm/gdb-stub.h>
+#include <asm/sections.h>
+
+#if (CONFIG_INTERRUPT_VECTOR_BASE & 0xffffff)
+#error "INTERRUPT_VECTOR_BASE not aligned to 16MiB boundary!"
+#endif
+
+struct pt_regs *__frame; /* current frame pointer */
+EXPORT_SYMBOL(__frame);
+
+int kstack_depth_to_print = 24;
+
+spinlock_t die_lock = __SPIN_LOCK_UNLOCKED(die_lock);
+
+ATOMIC_NOTIFIER_HEAD(mn10300_die_chain);
+
+/*
+ * These constants are for searching for possible module text
+ * segments. MODULE_RANGE is a guess of how much space is likely
+ * to be vmalloced.
+ */
+#define MODULE_RANGE (8 * 1024 * 1024)
+
+#define DO_ERROR(signr, prologue, str, name) \
+asmlinkage void name(struct pt_regs *regs, u32 intcode) \
+{ \
+ prologue; \
+ if (die_if_no_fixup(str, regs, intcode)) \
+ return; \
+ force_sig(signr, current); \
+}
+
+#define DO_EINFO(signr, prologue, str, name, sicode) \
+asmlinkage void name(struct pt_regs *regs, u32 intcode) \
+{ \
+ siginfo_t info; \
+ prologue; \
+ if (die_if_no_fixup(str, regs, intcode)) \
+ return; \
+ info.si_signo = signr; \
+ if (signr == SIGILL && sicode == ILL_ILLOPC) { \
+ uint8_t opcode; \
+ if (get_user(opcode, (uint8_t __user *)regs->pc) == 0) \
+ if (opcode == 0xff) \
+ info.si_signo = SIGTRAP; \
+ } \
+ info.si_errno = 0; \
+ info.si_code = sicode; \
+ info.si_addr = (void *) regs->pc; \
+ force_sig_info(info.si_signo, &info, current); \
+}
+
+DO_ERROR(SIGTRAP, {}, "trap", trap);
+DO_ERROR(SIGSEGV, {}, "ibreak", ibreak);
+DO_ERROR(SIGSEGV, {}, "obreak", obreak);
+DO_EINFO(SIGSEGV, {}, "access error", access_error, SEGV_ACCERR);
+DO_EINFO(SIGSEGV, {}, "insn access error", insn_acc_error, SEGV_ACCERR);
+DO_EINFO(SIGSEGV, {}, "data access error", data_acc_error, SEGV_ACCERR);
+DO_EINFO(SIGILL, {}, "privileged opcode", priv_op, ILL_PRVOPC);
+DO_EINFO(SIGILL, {}, "invalid opcode", invalid_op, ILL_ILLOPC);
+DO_EINFO(SIGILL, {}, "invalid ex opcode", invalid_exop, ILL_ILLOPC);
+DO_EINFO(SIGBUS, {}, "invalid address", mem_error, BUS_ADRERR);
+DO_EINFO(SIGBUS, {}, "bus error", bus_error, BUS_ADRERR);
+DO_EINFO(SIGILL, {}, "FPU invalid opcode", fpu_invalid_op, ILL_COPROC);
+
+DO_ERROR(SIGTRAP,
+#ifndef CONFIG_MN10300_USING_JTAG
+ DCR &= ~0x0001,
+#else
+ {},
+#endif
+ "single step", istep);
+
+/*
+ * handle NMI
+ */
+asmlinkage void nmi(struct pt_regs *regs, enum exception_code code)
+{
+ /* see if gdbstub wants to deal with it */
+#ifdef CONFIG_GDBSTUB
+ if (gdbstub_intercept(regs, code))
+ return;
+#endif
+
+ printk(KERN_WARNING "--- Register Dump ---\n");
+ show_registers(regs);
+ printk(KERN_WARNING "---------------------\n");
+}
+
+/*
+ * show a stack trace from the specified stack pointer
+ */
+void show_trace(unsigned long *sp)
+{
+ unsigned long *stack, addr, module_start, module_end;
+ int i;
+
+ printk(KERN_EMERG "\n"
+ KERN_EMERG "Call Trace:");
+
+ stack = sp;
+ i = 0;
+ module_start = VMALLOC_START;
+ module_end = VMALLOC_END;
+
+ while (((long) stack & (THREAD_SIZE - 1)) != 0) {
+ addr = *stack++;
+ if (__kernel_text_address(addr)) {
+#if 1
+ printk(" [<%08lx>]", addr);
+ print_symbol(" %s", addr);
+ printk("\n");
+#else
+ if ((i % 6) == 0)
+ printk("\n" KERN_EMERG " ");
+ printk("[<%08lx>] ", addr);
+ i++;
+#endif
+ }
+ }
+
+ printk("\n");
+}
+
+/*
+ * show the raw stack from the specified stack pointer
+ */
+void show_stack(struct task_struct *task, unsigned long *sp)
+{
+ unsigned long *stack;
+ int i;
+
+ if (!sp)
+ sp = (unsigned long *) &sp;
+
+ stack = sp;
+ printk(KERN_EMERG "Stack:");
+ for (i = 0; i < kstack_depth_to_print; i++) {
+ if (((long) stack & (THREAD_SIZE - 1)) == 0)
+ break;
+ if ((i % 8) == 0)
+ printk("\n" KERN_EMERG " ");
+ printk("%08lx ", *stack++);
+ }
+
+ show_trace(sp);
+}
+
+/*
+ * the architecture-independent dump_stack generator
+ */
+void dump_stack(void)
+{
+ unsigned long stack;
+
+ show_stack(current, &stack);
+}
+EXPORT_SYMBOL(dump_stack);
+
+/*
+ * dump the register file in the specified exception frame
+ */
+void show_registers_only(struct pt_regs *regs)
+{
+ unsigned long ssp;
+
+ ssp = (unsigned long) regs + sizeof(*regs);
+
+ printk(KERN_EMERG "PC: %08lx EPSW: %08lx SSP: %08lx mode: %s\n",
+ regs->pc, regs->epsw, ssp, user_mode(regs) ? "User" : "Super");
+ printk(KERN_EMERG "d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n",
+ regs->d0, regs->d1, regs->d2, regs->d3);
+ printk(KERN_EMERG "a0: %08lx a1: %08lx a2: %08lx a3: %08lx\n",
+ regs->a0, regs->a1, regs->a2, regs->a3);
+ printk(KERN_EMERG "e0: %08lx e1: %08lx e2: %08lx e3: %08lx\n",
+ regs->e0, regs->e1, regs->e2, regs->e3);
+ printk(KERN_EMERG "e4: %08lx e5: %08lx e6: %08lx e7: %08lx\n",
+ regs->e4, regs->e5, regs->e6, regs->e7);
+ printk(KERN_EMERG "lar: %08lx lir: %08lx mdr: %08lx usp: %08lx\n",
+ regs->lar, regs->lir, regs->mdr, regs->sp);
+ printk(KERN_EMERG "cvf: %08lx crl: %08lx crh: %08lx drq: %08lx\n",
+ regs->mcvf, regs->mcrl, regs->mcrh, regs->mdrq);
+ printk(KERN_EMERG "threadinfo=%p task=%p)\n",
+ current_thread_info(), current);
+
+ if ((unsigned long) current >= 0x90000000UL &&
+ (unsigned long) current < 0x94000000UL)
+ printk(KERN_EMERG "Process %s (pid: %d)\n",
+ current->comm, current->pid);
+
+ printk(KERN_EMERG "CPUP: %04hx\n", CPUP);
+ printk(KERN_EMERG "TBR: %08x\n", TBR);
+ printk(KERN_EMERG "DEAR: %08x\n", DEAR);
+ printk(KERN_EMERG "sISR: %08x\n", sISR);
+ printk(KERN_EMERG "NMICR: %04hx\n", NMICR);
+ printk(KERN_EMERG "BCBERR: %08x\n", BCBERR);
+ printk(KERN_EMERG "BCBEAR: %08x\n", BCBEAR);
+ printk(KERN_EMERG "MMUFCR: %08x\n", MMUFCR);
+ printk(KERN_EMERG "IPTEU : %08x IPTEL2: %08x\n", IPTEU, IPTEL2);
+ printk(KERN_EMERG "DPTEU: %08x DPTEL2: %08x\n", DPTEU, DPTEL2);
+}
+
+/*
+ * dump the registers and the stack
+ */
+void show_registers(struct pt_regs *regs)
+{
+ unsigned long sp;
+ int i;
+
+ show_registers_only(regs);
+
+ if (!user_mode(regs))
+ sp = (unsigned long) regs + sizeof(*regs);
+ else
+ sp = regs->sp;
+
+ /* when in-kernel, we also print out the stack and code at the
+ * time of the fault..
+ */
+ if (!user_mode(regs)) {
+ printk(KERN_EMERG "\n");
+ show_stack(current, (unsigned long *) sp);
+
+#if 0
+ printk(KERN_EMERG "\n"
+ KERN_EMERG "Code: ");
+ if (regs->pc < PAGE_OFFSET)
+ goto bad;
+
+ for (i = 0; i < 20; i++) {
+ unsigned char c;
+ if (__get_user(c, &((unsigned char *) regs->pc)[i]))
+ goto bad;
+ printk("%02x ", c);
+ }
+#else
+ i = 0;
+#endif
+ }
+
+ printk("\n");
+ return;
+
+#if 0
+bad:
+ printk(KERN_EMERG " Bad PC value.");
+ break;
+#endif
+}
+
+/*
+ *
+ */
+void show_trace_task(struct task_struct *tsk)
+{
+ unsigned long sp = tsk->thread.sp;
+
+ /* User space on another CPU? */
+ if ((sp ^ (unsigned long) tsk) & (PAGE_MASK << 1))
+ return;
+
+ show_trace((unsigned long *) sp);
+}
+
+/*
+ * note the untimely death of part of the kernel
+ */
+void die(const char *str, struct pt_regs *regs, enum exception_code code)
+{
+ console_verbose();
+ spin_lock_irq(&die_lock);
+ printk(KERN_EMERG "\n"
+ KERN_EMERG "%s: %04x\n",
+ str, code & 0xffff);
+ show_registers(regs);
+
+ if (regs->pc >= 0x02000000 && regs->pc < 0x04000000 &&
+ (regs->epsw & (EPSW_IM | EPSW_IE)) != (EPSW_IM | EPSW_IE)) {
+ printk(KERN_EMERG "Exception in usermode interrupt handler\n");
+ printk(KERN_EMERG "\n"
+ KERN_EMERG " Please connect to kernel debugger !!\n");
+ asm volatile ("0: bra 0b");
+ }
+
+ spin_unlock_irq(&die_lock);
+ do_exit(SIGSEGV);
+}
+
+/*
+ * see if there's a fixup handler we can force a jump to when an exception
+ * happens due to something kernel code did
+ */
+int die_if_no_fixup(const char *str, struct pt_regs *regs,
+ enum exception_code code)
+{
+ if (user_mode(regs))
+ return 0;
+
+ peripheral_leds_display_exception(code);
+
+ switch (code) {
+ /* see if we can fixup the kernel accessing memory */
+ case EXCEP_ITLBMISS:
+ case EXCEP_DTLBMISS:
+ case EXCEP_IAERROR:
+ case EXCEP_DAERROR:
+ case EXCEP_MEMERR:
+ case EXCEP_MISALIGN:
+ case EXCEP_BUSERROR:
+ case EXCEP_ILLDATACC:
+ case EXCEP_IOINSACC:
+ case EXCEP_PRIVINSACC:
+ case EXCEP_PRIVDATACC:
+ case EXCEP_DATINSACC:
+ if (fixup_exception(regs))
+ return 1;
+ case EXCEP_UNIMPINS:
+ if (regs->pc && *(uint8_t *)regs->pc == 0xff)
+ if (notify_die(DIE_BREAKPOINT, str, regs, code, 0, 0))
+ return 1;
+ break;
+ default:
+ break;
+ }
+
+ /* see if gdbstub wants to deal with it */
+#ifdef CONFIG_GDBSTUB
+ if (gdbstub_intercept(regs, code))
+ return 1;
+#endif
+
+ if (notify_die(DIE_GPF, str, regs, code, 0, 0))
+ return 1;
+
+ /* make the process die as the last resort */
+ die(str, regs, code);
+}
+
+/*
+ * handle unsupported syscall instructions (syscall 1-15)
+ */
+static asmlinkage void unsupported_syscall(struct pt_regs *regs,
+ enum exception_code code)
+{
+ struct task_struct *tsk = current;
+ siginfo_t info;
+
+ /* catch a kernel BUG() */
+ if (code == EXCEP_SYSCALL15 && !user_mode(regs)) {
+ if (report_bug(regs->pc, regs) == BUG_TRAP_TYPE_BUG) {
+#ifdef CONFIG_GDBSTUB
+ __gdbstub_bug_trap();
+#endif
+ }
+ }
+
+ regs->pc -= 2; /* syscall return addr is _after_ the instruction */
+
+ die_if_no_fixup("An unsupported syscall insn was used by the kernel\n",
+ regs, code);
+
+ info.si_signo = SIGILL;
+ info.si_errno = ENOSYS;
+ info.si_code = ILL_ILLTRP;
+ info.si_addr = (void *) regs->pc;
+ force_sig_info(SIGILL, &info, tsk);
+}
+
+/*
+ * display the register file when the stack pointer gets clobbered
+ */
+asmlinkage void do_double_fault(struct pt_regs *regs)
+{
+ struct task_struct *tsk = current;
+
+ strcpy(tsk->comm, "emergency tsk");
+ tsk->pid = 0;
+ console_verbose();
+ printk(KERN_EMERG "--- double fault ---\n");
+ show_registers(regs);
+}
+
+/*
+ * asynchronous bus error (external, usually I/O DMA)
+ */
+asmlinkage void io_bus_error(u32 bcberr, u32 bcbear, struct pt_regs *regs)
+{
+ console_verbose();
+
+ printk(KERN_EMERG "\n"
+ KERN_EMERG "Asynchronous I/O Bus Error\n"
+ KERN_EMERG "==========================\n");
+
+ if (bcberr & BCBERR_BEME)
+ printk(KERN_EMERG "- Multiple recorded errors\n");
+
+ printk(KERN_EMERG "- Faulting Buses:%s%s%s\n",
+ bcberr & BCBERR_BEMR_CI ? " CPU-Ins-Fetch" : "",
+ bcberr & BCBERR_BEMR_CD ? " CPU-Data" : "",
+ bcberr & BCBERR_BEMR_DMA ? " DMA" : "");
+
+ printk(KERN_EMERG "- %s %s access made to %s at address %08x\n",
+ bcberr & BCBERR_BEBST ? "Burst" : "Single",
+ bcberr & BCBERR_BERW ? "Read" : "Write",
+ bcberr & BCBERR_BESB_MON ? "Monitor Space" :
+ bcberr & BCBERR_BESB_IO ? "Internal CPU I/O Space" :
+ bcberr & BCBERR_BESB_EX ? "External I/O Bus" :
+ bcberr & BCBERR_BESB_OPEX ? "External Memory Bus" :
+ "On Chip Memory",
+ bcbear
+ );
+
+ printk(KERN_EMERG "- Detected by the %s\n",
+ bcberr&BCBERR_BESD ? "Bus Control Unit" : "Slave Bus");
+
+#ifdef CONFIG_PCI
+#define BRIDGEREGB(X) (*(volatile __u8 *)(0xBE040000 + (X)))
+#define BRIDGEREGW(X) (*(volatile __u16 *)(0xBE040000 + (X)))
+#define BRIDGEREGL(X) (*(volatile __u32 *)(0xBE040000 + (X)))
+
+ printk(KERN_EMERG "- PCI Memory Paging Reg: %08x\n",
+ *(volatile __u32 *) (0xBFFFFFF4));
+ printk(KERN_EMERG "- PCI Bridge Base Address 0: %08x\n",
+ BRIDGEREGL(PCI_BASE_ADDRESS_0));
+ printk(KERN_EMERG "- PCI Bridge AMPCI Base Address: %08x\n",
+ BRIDGEREGL(0x48));
+ printk(KERN_EMERG "- PCI Bridge Command: %04hx\n",
+ BRIDGEREGW(PCI_COMMAND));
+ printk(KERN_EMERG "- PCI Bridge Status: %04hx\n",
+ BRIDGEREGW(PCI_STATUS));
+ printk(KERN_EMERG "- PCI Bridge Int Status: %08hx\n",
+ BRIDGEREGL(0x4c));
+#endif
+
+ printk(KERN_EMERG "\n");
+ show_registers(regs);
+
+ panic("Halted due to asynchronous I/O Bus Error\n");
+}
+
+/*
+ * handle an exception for which a handler has not yet been installed
+ */
+asmlinkage void uninitialised_exception(struct pt_regs *regs,
+ enum exception_code code)
+{
+
+ /* see if gdbstub wants to deal with it */
+#ifdef CONFIG_GDBSTUB
+ if (gdbstub_intercept(regs, code))
+ return;
+#endif
+
+ peripheral_leds_display_exception(code);
+ printk(KERN_EMERG "Uninitialised Exception 0x%04x\n", code & 0xFFFF);
+ show_registers(regs);
+
+ for (;;)
+ continue;
+}
+
+/*
+ * set an interrupt stub to jump to a handler
+ * ! NOTE: this does *not* flush the caches
+ */
+void __init __set_intr_stub(enum exception_code code, void *handler)
+{
+ unsigned long addr;
+ u8 *vector = (u8 *)(CONFIG_INTERRUPT_VECTOR_BASE + code);
+
+ addr = (unsigned long) handler - (unsigned long) vector;
+ vector[0] = 0xdc; /* JMP handler */
+ vector[1] = addr;
+ vector[2] = addr >> 8;
+ vector[3] = addr >> 16;
+ vector[4] = addr >> 24;
+ vector[5] = 0xcb;
+ vector[6] = 0xcb;
+ vector[7] = 0xcb;
+}
+
+/*
+ * set an interrupt stub to jump to a handler
+ */
+void __init set_intr_stub(enum exception_code code, void *handler)
+{
+ unsigned long addr;
+ u8 *vector = (u8 *)(CONFIG_INTERRUPT_VECTOR_BASE + code);
+
+ addr = (unsigned long) handler - (unsigned long) vector;
+ vector[0] = 0xdc; /* JMP handler */
+ vector[1] = addr;
+ vector[2] = addr >> 8;
+ vector[3] = addr >> 16;
+ vector[4] = addr >> 24;
+ vector[5] = 0xcb;
+ vector[6] = 0xcb;
+ vector[7] = 0xcb;
+
+ mn10300_dcache_flush_inv();
+ mn10300_icache_inv();
+}
+
+/*
+ * set an interrupt stub to invoke the JTAG unit and then jump to a handler
+ */
+void __init set_jtag_stub(enum exception_code code, void *handler)
+{
+ unsigned long addr;
+ u8 *vector = (u8 *)(CONFIG_INTERRUPT_VECTOR_BASE + code);
+
+ addr = (unsigned long) handler - ((unsigned long) vector + 1);
+ vector[0] = 0xff; /* PI to jump into JTAG debugger */
+ vector[1] = 0xdc; /* jmp handler */
+ vector[2] = addr;
+ vector[3] = addr >> 8;
+ vector[4] = addr >> 16;
+ vector[5] = addr >> 24;
+ vector[6] = 0xcb;
+ vector[7] = 0xcb;
+
+ mn10300_dcache_flush_inv();
+ flush_icache_range((unsigned long) vector, (unsigned long) vector + 8);
+}
+
+/*
+ * initialise the exception table
+ */
+void __init trap_init(void)
+{
+ set_excp_vector(EXCEP_TRAP, trap);
+ set_excp_vector(EXCEP_ISTEP, istep);
+ set_excp_vector(EXCEP_IBREAK, ibreak);
+ set_excp_vector(EXCEP_OBREAK, obreak);
+
+ set_excp_vector(EXCEP_PRIVINS, priv_op);
+ set_excp_vector(EXCEP_UNIMPINS, invalid_op);
+ set_excp_vector(EXCEP_UNIMPEXINS, invalid_exop);
+ set_excp_vector(EXCEP_MEMERR, mem_error);
+ set_excp_vector(EXCEP_MISALIGN, misalignment);
+ set_excp_vector(EXCEP_BUSERROR, bus_error);
+ set_excp_vector(EXCEP_ILLINSACC, insn_acc_error);
+ set_excp_vector(EXCEP_ILLDATACC, data_acc_error);
+ set_excp_vector(EXCEP_IOINSACC, insn_acc_error);
+ set_excp_vector(EXCEP_PRIVINSACC, insn_acc_error);
+ set_excp_vector(EXCEP_PRIVDATACC, data_acc_error);
+ set_excp_vector(EXCEP_DATINSACC, insn_acc_error);
+ set_excp_vector(EXCEP_FPU_DISABLED, fpu_disabled);
+ set_excp_vector(EXCEP_FPU_UNIMPINS, fpu_invalid_op);
+ set_excp_vector(EXCEP_FPU_OPERATION, fpu_exception);
+
+ set_excp_vector(EXCEP_NMI, nmi);
+
+ set_excp_vector(EXCEP_SYSCALL1, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL2, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL3, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL4, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL5, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL6, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL7, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL8, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL9, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL10, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL11, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL12, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL13, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL14, unsupported_syscall);
+ set_excp_vector(EXCEP_SYSCALL15, unsupported_syscall);
+}
+
+/*
+ * determine if a program counter value is a valid bug address
+ */
+int is_valid_bugaddr(unsigned long pc)
+{
+ return pc >= PAGE_OFFSET;
+}
--- /dev/null
+/* MN10300 Main kernel linker script
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#define __VMLINUX_LDS__
+#include <asm-generic/vmlinux.lds.h>
+#include <asm/thread_info.h>
+
+OUTPUT_FORMAT("elf32-am33lin", "elf32-am33lin", "elf32-am33lin")
+OUTPUT_ARCH(mn10300)
+ENTRY(_start)
+jiffies = jiffies_64;
+#ifndef CONFIG_MN10300_CURRENT_IN_E2
+current = __current;
+#endif
+SECTIONS
+{
+ . = CONFIG_KERNEL_TEXT_ADDRESS;
+ /* read-only */
+ _stext = .;
+ _text = .; /* Text and read-only data */
+ .text : {
+ *(
+ .text.head
+ .text
+ )
+ TEXT_TEXT
+ SCHED_TEXT
+ LOCK_TEXT
+ KPROBES_TEXT
+ *(.fixup)
+ *(.gnu.warning)
+ } = 0xcb
+
+ _etext = .; /* End of text section */
+
+ . = ALIGN(16); /* Exception table */
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ BUG_TABLE
+
+ RODATA
+
+ /* writeable */
+ .data : { /* Data */
+ DATA_DATA
+ CONSTRUCTORS
+ }
+
+ . = ALIGN(4096);
+ __nosave_begin = .;
+ .data_nosave : { *(.data.nosave) }
+ . = ALIGN(4096);
+ __nosave_end = .;
+
+ . = ALIGN(4096);
+ .data.page_aligned : { *(.data.idt) }
+
+ . = ALIGN(32);
+ .data.cacheline_aligned : { *(.data.cacheline_aligned) }
+
+ /* rarely changed data like cpu maps */
+ . = ALIGN(32);
+ .data.read_mostly : AT(ADDR(.data.read_mostly)) {
+ *(.data.read_mostly)
+ _edata = .; /* End of data section */
+ }
+
+ . = ALIGN(THREAD_SIZE); /* init_task */
+ .data.init_task : { *(.data.init_task) }
+
+ /* might get freed after init */
+ . = ALIGN(4096);
+ .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) {
+ __smp_locks = .;
+ *(.smp_locks)
+ __smp_locks_end = .;
+ }
+
+ /* will be freed after init */
+ . = ALIGN(4096); /* Init code and data */
+ __init_begin = .;
+ .init.text : {
+ _sinittext = .;
+ *(.init.text)
+ _einittext = .;
+ }
+ .init.data : { *(.init.data) }
+ . = ALIGN(16);
+ __setup_start = .;
+ .setup.init : { KEEP(*(.init.setup)) }
+ __setup_end = .;
+
+ __initcall_start = .;
+ .initcall.init : {
+ INITCALLS
+ }
+ __initcall_end = .;
+ __con_initcall_start = .;
+ .con_initcall.init : { *(.con_initcall.init) }
+ __con_initcall_end = .;
+
+ SECURITY_INIT
+ . = ALIGN(4);
+ __alt_instructions = .;
+ .altinstructions : { *(.altinstructions) }
+ __alt_instructions_end = .;
+ .altinstr_replacement : { *(.altinstr_replacement) }
+ /* .exit.text is discard at runtime, not link time, to deal with references
+ from .altinstructions and .eh_frame */
+ .exit.text : { *(.exit.text) }
+ .exit.data : { *(.exit.data) }
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ . = ALIGN(4096);
+ __initramfs_start = .;
+ .init.ramfs : { *(.init.ramfs) }
+ __initramfs_end = .;
+#endif
+
+ . = ALIGN(32);
+ __per_cpu_start = .;
+ .data.percpu : { *(.data.percpu) }
+ __per_cpu_end = .;
+ . = ALIGN(4096);
+ __init_end = .;
+ /* freed after init ends here */
+
+ __bss_start = .; /* BSS */
+ .bss : {
+ *(.bss.page_aligned)
+ *(.bss)
+ }
+ . = ALIGN(4);
+ __bss_stop = .;
+
+ _end = . ;
+
+ /* This is where the kernel creates the early boot page tables */
+ . = ALIGN(4096);
+ pg0 = .;
+
+ /* Sections to be discarded */
+ /DISCARD/ : {
+ *(.exitcall.exit)
+ }
+
+ STABS_DEBUG
+
+ DWARF_DEBUG
+}
--- /dev/null
+#
+# Makefile for the MN10300-specific library files..
+#
+
+lib-y = delay.o usercopy.o checksum.o bitops.o memcpy.o memmove.o memset.o
+lib-y += do_csum.o
+lib-y += __ashldi3.o __ashrdi3.o __lshrdi3.o negdi2.o
--- /dev/null
+/* MN10300 64-bit arithmetic left shift
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <asm/cache.h>
+
+ .text
+ .balign L1_CACHE_BYTES
+
+###############################################################################
+#
+# unsigned long long __ashldi3(unsigned long long value [D1:D0],
+# unsigned by [(12,SP)])
+#
+###############################################################################
+ .globl __ashldi3
+ .type __ashldi3,@function
+__ashldi3:
+ mov (12,sp),a0
+ and +63,a0
+ beq __ashldi3_zero
+
+ cmp +31,a0
+ bhi __ashldi3_32plus
+
+ # the count is in the range 1-31
+ asl a0,d1
+
+ mov +32,a1
+ sub a0,a1,a1 # a1 = 32 - count
+ lsr a1,d0,a1 # get overflow from LSW -> MSW
+
+ or_asl a1,d1,a0,d0 # insert overflow into MSW and
+ # shift the LSW
+ rets
+
+ .balign L1_CACHE_BYTES
+ # the count is in the range 32-63
+__ashldi3_32plus:
+ asl a0,d0,d1
+ clr d0
+__ashldi3_zero:
+ rets
+
+ .size __ashldi3, .-__ashldi3
--- /dev/null
+/* MN10300 64-bit arithmetic right shift
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <asm/cache.h>
+
+ .text
+ .balign L1_CACHE_BYTES
+
+###############################################################################
+#
+# unsigned long long __ashrdi3(unsigned long long value [D1:D0],
+# unsigned by [(12,SP)])
+#
+###############################################################################
+ .globl __ashrdi3
+ .type __ashrdi3,@function
+__ashrdi3:
+ mov (12,sp),a0
+ and +63,a0
+ beq __ashrdi3_zero
+
+ cmp +31,a0
+ bhi __ashrdi3_32plus
+
+ # the count is in the range 1-31
+ lsr a0,d0
+
+ mov +32,a1
+ sub a0,a1,a1 # a1 = 32 - count
+ asl a1,d1,a1 # get underflow from MSW -> LSW
+
+ or_asr a1,d0,a0,d1 # insert underflow into LSW and
+ # shift the MSW
+ rets
+
+ .balign L1_CACHE_BYTES
+ # the count is in the range 32-63
+__ashrdi3_32plus:
+ asr a0,d1,d0
+ ext d0 # sign-extend result through MDR
+ mov mdr,d1
+__ashrdi3_zero:
+ rets
+
+ .size __ashrdi3, .-__ashrdi3
--- /dev/null
+/* MN10300 64-bit logical right shift
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#include <asm/cache.h>
+
+ .text
+ .balign L1_CACHE_BYTES
+
+###############################################################################
+#
+# unsigned long long __lshrdi3(unsigned long long value [D1:D0],
+# unsigned by [(12,SP)])
+#
+###############################################################################
+ .globl __lshrdi3
+ .type __lshrdi3,@function
+__lshrdi3:
+ mov (12,sp),a0
+ and +63,a0
+ beq __lshrdi3_zero
+
+ cmp +31,a0
+ bhi __lshrdi3_32plus
+
+ # the count is in the range 1-31
+ lsr a0,d0
+
+ mov +32,a1
+ sub a0,a1,a1 # a1 = 32 - count
+ asl a1,d1,a1 # get underflow from MSW -> LSW
+
+ or_lsr a1,d0,a0,d1 # insert underflow into LSW and
+ # shift the MSW
+ rets
+
+ .balign L1_CACHE_BYTES
+ # the count is in the range 32-63
+__lshrdi3_32plus:
+ lsr a0,d1,d0
+ clr d1
+__lshrdi3_zero:
+ rets
+
+ .size __lshrdi3, .-__lshrdi3
--- /dev/null
+/* ashrdi3.c extracted from gcc-2.7.2/libgcc2.c which is: */
+/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public Licence as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public Licence for more details.
+
+You should have received a copy of the GNU General Public Licence
+along with GNU CC; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+#define BITS_PER_UNIT 8
+
+typedef int SItype __attribute__((mode(SI)));
+typedef unsigned int USItype __attribute__((mode(SI)));
+typedef int DItype __attribute__((mode(DI)));
+typedef int word_type __attribute__((mode(__word__)));
+
+struct DIstruct {
+ SItype low;
+ SItype high;
+};
+
+union DIunion {
+ struct DIstruct s;
+ DItype ll;
+};
+
+DItype __ashrdi3(DItype u, word_type b)
+{
+ union DIunion w;
+ union DIunion uu;
+ word_type bm;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+
+ bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
+ if (bm <= 0) {
+ /* w.s.high = 1..1 or 0..0 */
+ w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1);
+ w.s.low = uu.s.high >> -bm;
+ } else {
+ USItype carries = (USItype)uu.s.high << bm;
+ w.s.high = uu.s.high >> b;
+ w.s.low = ((USItype)uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
--- /dev/null
+/* MN10300 Non-trivial bit operations
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <asm/bitops.h>
+#include <asm/system.h>
+
+/*
+ * try flipping a bit using BSET and BCLR
+ */
+void change_bit(int nr, volatile void *addr)
+{
+ if (test_bit(nr, addr))
+ goto try_clear_bit;
+
+try_set_bit:
+ if (!test_and_set_bit(nr, addr))
+ return;
+
+try_clear_bit:
+ if (test_and_clear_bit(nr, addr))
+ return;
+
+ goto try_set_bit;
+}
+
+/*
+ * try flipping a bit using BSET and BCLR and returning the old value
+ */
+int test_and_change_bit(int nr, volatile void *addr)
+{
+ if (test_bit(nr, addr))
+ goto try_clear_bit;
+
+try_set_bit:
+ if (!test_and_set_bit(nr, addr))
+ return 0;
+
+try_clear_bit:
+ if (test_and_clear_bit(nr, addr))
+ return 1;
+
+ goto try_set_bit;
+}
--- /dev/null
+/* MN10300 Optimised checksumming wrappers
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <asm/byteorder.h>
+#include <asm/uaccess.h>
+#include <asm/checksum.h>
+#include "internal.h"
+
+static inline unsigned short from32to16(__wsum sum)
+{
+ asm(" add %1,%0 \n"
+ " addc 0xffff,%0 \n"
+ : "=r" (sum)
+ : "r" (sum << 16), "0" (sum & 0xffff0000)
+ );
+ return sum >> 16;
+}
+
+__sum16 ip_fast_csum(const void *iph, unsigned int ihl)
+{
+ return ~do_csum(iph, ihl * 4);
+}
+EXPORT_SYMBOL(ip_fast_csum);
+
+__wsum csum_partial(const void *buff, int len, __wsum sum)
+{
+ __wsum result;
+
+ result = do_csum(buff, len);
+ result += sum;
+ if (sum > result)
+ result++;
+ return result;
+}
+EXPORT_SYMBOL(csum_partial);
+
+__sum16 ip_compute_csum(const void *buff, int len)
+{
+ return ~from32to16(do_csum(buff, len));
+}
+EXPORT_SYMBOL(ip_compute_csum);
+
+__wsum csum_partial_copy(const void *src, void *dst, int len, __wsum sum)
+{
+ copy_from_user(dst, src, len);
+ return csum_partial(dst, len, sum);
+}
+EXPORT_SYMBOL(csum_partial_copy);
+
+__wsum csum_partial_copy_nocheck(const void *src, void *dst,
+ int len, __wsum sum)
+{
+ sum = csum_partial(src, len, sum);
+ memcpy(dst, src, len);
+ return sum;
+}
+EXPORT_SYMBOL(csum_partial_copy_nocheck);
+
+__wsum csum_partial_copy_from_user(const void *src, void *dst,
+ int len, __wsum sum,
+ int *err_ptr)
+{
+ int missing;
+
+ missing = copy_from_user(dst, src, len);
+ if (missing) {
+ memset(dst + len - missing, 0, missing);
+ *err_ptr = -EFAULT;
+ }
+
+ return csum_partial(dst, len, sum);
+}
+EXPORT_SYMBOL(csum_partial_copy_from_user);
+
+__wsum csum_and_copy_to_user(const void *src, void *dst,
+ int len, __wsum sum,
+ int *err_ptr)
+{
+ int missing;
+
+ missing = copy_to_user(dst, src, len);
+ if (missing) {
+ memset(dst + len - missing, 0, missing);
+ *err_ptr = -EFAULT;
+ }
+
+ return csum_partial(src, len, sum);
+}
+EXPORT_SYMBOL(csum_and_copy_to_user);
--- /dev/null
+/* MN10300 Short delay interpolation routines
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <asm/div64.h>
+
+/*
+ * basic delay loop
+ */
+void __delay(unsigned long loops)
+{
+ int d0;
+
+ asm volatile(
+ " bra 1f \n"
+ " .align 4 \n"
+ "1: bra 2f \n"
+ " .align 4 \n"
+ "2: add -1,%0 \n"
+ " bne 2b \n"
+ : "=&d" (d0)
+ : "0" (loops));
+}
+EXPORT_SYMBOL(__delay);
+
+/*
+ * handle a delay specified in terms of microseconds
+ */
+void __udelay(unsigned long usecs)
+{
+ signed long ioclk, stop;
+
+ /* usecs * CLK / 1E6 */
+ stop = __muldiv64u(usecs, MN10300_TSCCLK, 1000000);
+ stop = TMTSCBC - stop;
+
+ do {
+ ioclk = TMTSCBC;
+ } while (stop < ioclk);
+}
+EXPORT_SYMBOL(__udelay);
--- /dev/null
+/* Optimised simple memory checksum
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <asm/cache.h>
+
+ .section .text
+ .balign L1_CACHE_BYTES
+
+###############################################################################
+#
+# unsigned int do_csum(const unsigned char *buff, size_t len)
+#
+###############################################################################
+ .globl do_csum
+ .type do_csum,@function
+do_csum:
+ movm [d2,d3],(sp)
+ mov d0,(12,sp)
+ mov d1,(16,sp)
+ mov d1,d2 # count
+ mov d0,a0 # buff
+ clr d1 # accumulator
+
+ cmp +0,d2
+ beq do_csum_done # return if zero-length buffer
+
+ # 4-byte align the buffer pointer
+ btst +3,a0
+ beq do_csum_now_4b_aligned
+
+ btst +1,a0
+ beq do_csum_addr_not_odd
+ movbu (a0),d0
+ inc a0
+ asl +8,d0
+ add d0,d1
+ addc +0,d1
+ add -1,d2
+do_csum_addr_not_odd:
+
+ cmp +2,d2
+ bcs do_csum_fewer_than_4
+ btst +2,a0
+ beq do_csum_now_4b_aligned
+ movhu (a0+),d0
+ add d0,d1
+ addc +0,d1
+ add -2,d2
+ cmp +4,d2
+ bcs do_csum_fewer_than_4
+
+do_csum_now_4b_aligned:
+ # we want to checksum as much as we can in chunks of 32 bytes
+ cmp +31,d2
+ bls do_csum_remainder # 4-byte aligned remainder
+
+ add -32,d2
+ mov +32,d3
+
+do_csum_loop:
+ mov (a0+),d0
+ add d0,d1
+ mov (a0+),e0
+ addc e0,d1
+ mov (a0+),e1
+ addc e1,d1
+ mov (a0+),e3
+ addc e3,d1
+ mov (a0+),d0
+ addc d0,d1
+ mov (a0+),e0
+ addc e0,d1
+ mov (a0+),e1
+ addc e1,d1
+ mov (a0+),e3
+ addc e3,d1
+ addc +0,d1
+
+ sub d3,d2
+ bcc do_csum_loop
+
+ add d3,d2
+ beq do_csum_done
+
+do_csum_remainder:
+ # cut 16-31 bytes down to 0-15
+ cmp +16,d2
+ bcs do_csum_fewer_than_16
+ mov (a0+),d0
+ add d0,d1
+ mov (a0+),e0
+ addc e0,d1
+ mov (a0+),e1
+ addc e1,d1
+ mov (a0+),e3
+ addc e3,d1
+ addc +0,d1
+ add -16,d2
+ beq do_csum_done
+
+do_csum_fewer_than_16:
+ # copy the remaining whole words
+ cmp +4,d2
+ bcs do_csum_fewer_than_4
+ cmp +8,d2
+ bcs do_csum_one_word
+ cmp +12,d2
+ bcs do_csum_two_words
+ mov (a0+),d0
+ add d0,d1
+ addc +0,d1
+do_csum_two_words:
+ mov (a0+),d0
+ add d0,d1
+ addc +0,d1
+do_csum_one_word:
+ mov (a0+),d0
+ add d0,d1
+ addc +0,d1
+
+do_csum_fewer_than_4:
+ and +3,d2
+ beq do_csum_done
+ xor_cmp d0,d0,+2,d2
+ bcs do_csum_fewer_than_2
+ movhu (a0+),d0
+do_csum_fewer_than_2:
+ and +1,d2
+ beq do_csum_add_last_bit
+ movbu (a0),d3
+ add d3,d0
+do_csum_add_last_bit:
+ add d0,d1
+ addc +0,d1
+
+do_csum_done:
+ # compress the checksum down to 16 bits
+ mov +0xffff0000,d2
+ and d1,d2
+ asl +16,d1
+ add d2,d1,d0
+ addc +0xffff,d0
+ lsr +16,d0
+
+ # flip the halves of the word result if the buffer was oddly aligned
+ mov (12,sp),d1
+ and +1,d1
+ beq do_csum_not_oddly_aligned
+ swaph d0,d0 # exchange bits 15:8 with 7:0
+
+do_csum_not_oddly_aligned:
+ ret [d2,d3],8
+
+do_csum_end:
+ .size do_csum, do_csum_end-do_csum
--- /dev/null
+/* Internal definitions for the arch part of the kernel library
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+/*
+ * do_csum.S
+ */
+extern unsigned int do_csum(const unsigned char *, size_t);
--- /dev/null
+/* lshrdi3.c extracted from gcc-2.7.2/libgcc2.c which is: */
+/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public Licence as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public Licence for more details.
+
+You should have received a copy of the GNU General Public Licence
+along with GNU CC; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+#define BITS_PER_UNIT 8
+
+typedef int SItype __attribute__((mode(SI)));
+typedef unsigned int USItype __attribute__((mode(SI)));
+typedef int DItype __attribute__((mode(DI)));
+typedef int word_type __attribute__((mode(__word__)));
+
+struct DIstruct {
+ SItype low;
+ SItype high;
+};
+
+union DIunion {
+ struct DIstruct s;
+ DItype ll;
+};
+
+DItype __lshrdi3(DItype u, word_type b)
+{
+ union DIunion w;
+ word_type bm;
+ union DIunion uu;
+
+ if (b == 0)
+ return u;
+
+ uu.ll = u;
+
+ bm = (sizeof(SItype) * BITS_PER_UNIT) - b;
+ if (bm <= 0) {
+ w.s.high = 0;
+ w.s.low = (USItype) uu.s.high >> -bm;
+ } else {
+ USItype carries = (USItype) uu.s.high << bm;
+ w.s.high = (USItype) uu.s.high >> b;
+ w.s.low = ((USItype) uu.s.low >> b) | carries;
+ }
+
+ return w.ll;
+}
--- /dev/null
+/* MN10300 Optimised simple memory to memory copy
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <asm/cache.h>
+
+ .section .text
+ .balign L1_CACHE_BYTES
+
+###############################################################################
+#
+# void *memcpy(void *dst, const void *src, size_t n)
+#
+###############################################################################
+ .globl memcpy
+ .type memcpy,@function
+memcpy:
+ movm [d2,d3],(sp)
+ mov d0,(12,sp)
+ mov d1,(16,sp)
+ mov (20,sp),d2 # count
+ mov d0,a0 # dst
+ mov d1,a1 # src
+ mov d0,e3 # the return value
+
+ cmp +0,d2
+ beq memcpy_done # return if zero-length copy
+
+ # see if the three parameters are all four-byte aligned
+ or d0,d1,d3
+ or d2,d3
+ and +3,d3
+ bne memcpy_1 # jump if not
+
+ # we want to transfer as much as we can in chunks of 32 bytes
+ cmp +31,d2
+ bls memcpy_4_remainder # 4-byte aligned remainder
+
+ movm [exreg1],(sp)
+ add -32,d2
+ mov +32,d3
+
+memcpy_4_loop:
+ mov (a1+),d0
+ mov (a1+),d1
+ mov (a1+),e0
+ mov (a1+),e1
+ mov (a1+),e4
+ mov (a1+),e5
+ mov (a1+),e6
+ mov (a1+),e7
+ mov d0,(a0+)
+ mov d1,(a0+)
+ mov e0,(a0+)
+ mov e1,(a0+)
+ mov e4,(a0+)
+ mov e5,(a0+)
+ mov e6,(a0+)
+ mov e7,(a0+)
+
+ sub d3,d2
+ bcc memcpy_4_loop
+
+ movm (sp),[exreg1]
+ add d3,d2
+ beq memcpy_4_no_remainder
+
+memcpy_4_remainder:
+ # cut 4-7 words down to 0-3
+ cmp +16,d2
+ bcs memcpy_4_three_or_fewer_words
+ mov (a1+),d0
+ mov (a1+),d1
+ mov (a1+),e0
+ mov (a1+),e1
+ mov d0,(a0+)
+ mov d1,(a0+)
+ mov e0,(a0+)
+ mov e1,(a0+)
+ add -16,d2
+ beq memcpy_4_no_remainder
+
+ # copy the remaining 1, 2 or 3 words
+memcpy_4_three_or_fewer_words:
+ cmp +8,d2
+ bcs memcpy_4_one_word
+ beq memcpy_4_two_words
+ mov (a1+),d0
+ mov d0,(a0+)
+memcpy_4_two_words:
+ mov (a1+),d0
+ mov d0,(a0+)
+memcpy_4_one_word:
+ mov (a1+),d0
+ mov d0,(a0+)
+
+memcpy_4_no_remainder:
+ # check we copied the correct amount
+ # TODO: REMOVE CHECK
+ sub e3,a0,d2
+ mov (20,sp),d1
+ cmp d2,d1
+ beq memcpy_done
+ break
+ break
+ break
+
+memcpy_done:
+ mov e3,a0
+ ret [d2,d3],8
+
+ # handle misaligned copying
+memcpy_1:
+ add -1,d2
+ mov +1,d3
+ setlb # setlb requires the next insns
+ # to occupy exactly 4 bytes
+
+ sub d3,d2
+ movbu (a1),d0
+ movbu d0,(a0)
+ add_add d3,a1,d3,a0
+ lcc
+
+ mov e3,a0
+ ret [d2,d3],8
+
+memcpy_end:
+ .size memcpy, memcpy_end-memcpy
--- /dev/null
+/* MN10300 Optimised simple memory to memory copy, with support for overlapping
+ * regions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <asm/cache.h>
+
+ .section .text
+ .balign L1_CACHE_BYTES
+
+###############################################################################
+#
+# void *memmove(void *dst, const void *src, size_t n)
+#
+###############################################################################
+ .globl memmove
+ .type memmove,@function
+memmove:
+ # fall back to memcpy if dst < src to work bottom up
+ cmp d1,d0
+ bcs memmove_memcpy
+
+ # work top down
+ movm [d2,d3],(sp)
+ mov d0,(12,sp)
+ mov d1,(16,sp)
+ mov (20,sp),d2 # count
+ add d0,d2,a0 # dst end
+ add d1,d2,a1 # src end
+ mov d0,e3 # the return value
+
+ cmp +0,d2
+ beq memmove_done # return if zero-length copy
+
+ # see if the three parameters are all four-byte aligned
+ or d0,d1,d3
+ or d2,d3
+ and +3,d3
+ bne memmove_1 # jump if not
+
+ # we want to transfer as much as we can in chunks of 32 bytes
+ add -4,a1
+ cmp +31,d2
+ bls memmove_4_remainder # 4-byte aligned remainder
+
+ add -32,d2
+ mov +32,d3
+
+memmove_4_loop:
+ mov (a1),d0
+ sub_sub +4,a1,+4,a0
+ mov d0,(a0)
+ mov (a1),d1
+ sub_sub +4,a1,+4,a0
+ mov d1,(a0)
+
+ mov (a1),d0
+ sub_sub +4,a1,+4,a0
+ mov d0,(a0)
+ mov (a1),d1
+ sub_sub +4,a1,+4,a0
+ mov d1,(a0)
+
+ mov (a1),d0
+ sub_sub +4,a1,+4,a0
+ mov d0,(a0)
+ mov (a1),d1
+ sub_sub +4,a1,+4,a0
+ mov d1,(a0)
+
+ mov (a1),d0
+ sub_sub +4,a1,+4,a0
+ mov d0,(a0)
+ mov (a1),d1
+ sub_sub +4,a1,+4,a0
+ mov d1,(a0)
+
+ sub d3,d2
+ bcc memmove_4_loop
+
+ add d3,d2
+ beq memmove_4_no_remainder
+
+memmove_4_remainder:
+ # cut 4-7 words down to 0-3
+ cmp +16,d2
+ bcs memmove_4_three_or_fewer_words
+ mov (a1),d0
+ sub_sub +4,a1,+4,a0
+ mov d0,(a0)
+ mov (a1),d1
+ sub_sub +4,a1,+4,a0
+ mov d1,(a0)
+ mov (a1),e0
+ sub_sub +4,a1,+4,a0
+ mov e0,(a0)
+ mov (a1),e1
+ sub_sub +4,a1,+4,a0
+ mov e1,(a0)
+ add -16,d2
+ beq memmove_4_no_remainder
+
+ # copy the remaining 1, 2 or 3 words
+memmove_4_three_or_fewer_words:
+ cmp +8,d2
+ bcs memmove_4_one_word
+ beq memmove_4_two_words
+ mov (a1),d0
+ sub_sub +4,a1,+4,a0
+ mov d0,(a0)
+memmove_4_two_words:
+ mov (a1),d0
+ sub_sub +4,a1,+4,a0
+ mov d0,(a0)
+memmove_4_one_word:
+ mov (a1),d0
+ sub_sub +4,a1,+4,a0
+ mov d0,(a0)
+
+memmove_4_no_remainder:
+ # check we copied the correct amount
+ # TODO: REMOVE CHECK
+ sub e3,a0,d2
+ beq memmove_done
+ break
+ break
+ break
+
+memmove_done:
+ mov e3,a0
+ ret [d2,d3],8
+
+ # handle misaligned copying
+memmove_1:
+ add -1,a1
+ add -1,d2
+ mov +1,d3
+ setlb # setlb requires the next insns
+ # to occupy exactly 4 bytes
+
+ sub d3,d2
+ movbu (a1),d0
+ sub_sub d3,a1,d3,a0
+ movbu d0,(a0)
+ lcc
+
+ mov e3,a0
+ ret [d2,d3],8
+
+memmove_memcpy:
+ jmp memcpy
+
+memmove_end:
+ .size memmove, memmove_end-memmove
--- /dev/null
+/* Optimised simple memory fill
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <asm/cache.h>
+
+ .section .text
+ .balign L1_CACHE_BYTES
+
+###############################################################################
+#
+# void *memset(void *dst, int c, size_t n)
+#
+###############################################################################
+ .globl memset
+ .type memset,@function
+memset:
+ movm [d2,d3],(sp)
+ mov d0,(12,sp)
+ mov d1,(16,sp)
+ mov (20,sp),d2 # count
+ mov d0,a0 # dst
+ mov d0,e3 # the return value
+
+ cmp +0,d2
+ beq memset_done # return if zero-length fill
+
+ # see if the region parameters are four-byte aligned
+ or d0,d2,d3
+ and +3,d3
+ bne memset_1 # jump if not
+
+ extbu d1
+ mov_asl d1,d3,8,d1
+ or_asl d1,d3,8,d1
+ or_asl d1,d3,8,d1
+ or d3,d1
+
+ # we want to transfer as much as we can in chunks of 32 bytes
+ cmp +31,d2
+ bls memset_4_remainder # 4-byte aligned remainder
+
+ add -32,d2
+ mov +32,d3
+
+memset_4_loop:
+ mov d1,(a0+)
+ mov d1,(a0+)
+ mov d1,(a0+)
+ mov d1,(a0+)
+ mov d1,(a0+)
+ mov d1,(a0+)
+ mov d1,(a0+)
+ mov d1,(a0+)
+
+ sub d3,d2
+ bcc memset_4_loop
+
+ add d3,d2
+ beq memset_4_no_remainder
+
+memset_4_remainder:
+ # cut 4-7 words down to 0-3
+ cmp +16,d2
+ bcs memset_4_three_or_fewer_words
+ mov d1,(a0+)
+ mov d1,(a0+)
+ mov d1,(a0+)
+ mov d1,(a0+)
+ add -16,d2
+ beq memset_4_no_remainder
+
+ # copy the remaining 1, 2 or 3 words
+memset_4_three_or_fewer_words:
+ cmp +8,d2
+ bcs memset_4_one_word
+ beq memset_4_two_words
+ mov d1,(a0+)
+memset_4_two_words:
+ mov d1,(a0+)
+memset_4_one_word:
+ mov d1,(a0+)
+
+memset_4_no_remainder:
+ # check we set the correct amount
+ # TODO: REMOVE CHECK
+ sub e3,a0,d2
+ mov (20,sp),d1
+ cmp d2,d1
+ beq memset_done
+ break
+ break
+ break
+
+memset_done:
+ mov e3,a0
+ ret [d2,d3],8
+
+ # handle misaligned copying
+memset_1:
+ add -1,d2
+ mov +1,d3
+ setlb # setlb requires the next insns
+ # to occupy exactly 4 bytes
+
+ sub d3,d2
+ movbu d1,(a0)
+ inc a0
+ lcc
+
+ mov e3,a0
+ ret [d2,d3],8
+
+memset_end:
+ .size memset, memset_end-memset
--- /dev/null
+/* More subroutines needed by GCC output code on some machines. */
+/* Compile this one with gcc. */
+/* Copyright (C) 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
+ 2000, 2001 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public Licence as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+In addition to the permissions in the GNU General Public Licence, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file into combinations with other programs,
+and to distribute those combinations without any restriction coming
+from the use of this file. (The General Public Licence restrictions
+do apply in other respects; for example, they cover modification of
+the file, and distribution when not linked into a combine
+executable.)
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public Licence for more details.
+
+You should have received a copy of the GNU General Public Licence
+along with GNU CC; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+/* It is incorrect to include config.h here, because this file is being
+ compiled for the target, and hence definitions concerning only the host
+ do not apply. */
+
+#include <linux/types.h>
+
+union DWunion {
+ s64 ll;
+ struct {
+ s32 low;
+ s32 high;
+ } s;
+};
+
+s64 __negdi2(s64 u)
+{
+ union DWunion w;
+ union DWunion uu;
+
+ uu.ll = u;
+
+ w.s.low = -uu.s.low;
+ w.s.high = -uu.s.high - ((u32) w.s.low > 0);
+
+ return w.ll;
+}
--- /dev/null
+/* MN10300 Userspace accessor functions
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <asm/uaccess.h>
+
+unsigned long
+__generic_copy_to_user(void *to, const void *from, unsigned long n)
+{
+ if (access_ok(VERIFY_WRITE, to, n))
+ __copy_user(to, from, n);
+ return n;
+}
+
+unsigned long
+__generic_copy_from_user(void *to, const void *from, unsigned long n)
+{
+ if (access_ok(VERIFY_READ, from, n))
+ __copy_user_zeroing(to, from, n);
+ return n;
+}
+
+/*
+ * Copy a null terminated string from userspace.
+ */
+#define __do_strncpy_from_user(dst, src, count, res) \
+do { \
+ int w; \
+ asm volatile( \
+ " mov %1,%0\n" \
+ " cmp 0,%1\n" \
+ " beq 2f\n" \
+ "0:\n" \
+ " movbu (%5),%2\n" \
+ "1:\n" \
+ " movbu %2,(%6)\n" \
+ " inc %5\n" \
+ " inc %6\n" \
+ " cmp 0,%2\n" \
+ " beq 2f\n" \
+ " add -1,%1\n" \
+ " bne 0b\n" \
+ "2:\n" \
+ " sub %1,%0\n" \
+ "3:\n" \
+ " .section .fixup,\"ax\"\n" \
+ "4:\n" \
+ " mov %3,%0\n" \
+ " jmp 3b\n" \
+ " .previous\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,4b\n" \
+ " .long 1b,4b\n" \
+ " .previous" \
+ :"=&r"(res), "=r"(count), "=&r"(w) \
+ :"i"(-EFAULT), "1"(count), "a"(src), "a"(dst) \
+ :"memory"); \
+} while (0)
+
+long
+__strncpy_from_user(char *dst, const char *src, long count)
+{
+ long res;
+ __do_strncpy_from_user(dst, src, count, res);
+ return res;
+}
+
+long
+strncpy_from_user(char *dst, const char *src, long count)
+{
+ long res = -EFAULT;
+ if (access_ok(VERIFY_READ, src, 1))
+ __do_strncpy_from_user(dst, src, count, res);
+ return res;
+}
+
+
+/*
+ * Clear a userspace memory
+ */
+#define __do_clear_user(addr, size) \
+do { \
+ int w; \
+ asm volatile( \
+ " cmp 0,%0\n" \
+ " beq 1f\n" \
+ " clr %1\n" \
+ "0: movbu %1,(%3,%2)\n" \
+ " inc %3\n" \
+ " cmp %0,%3\n" \
+ " bne 0b\n" \
+ "1:\n" \
+ " sub %3,%0\n" \
+ "2:\n" \
+ ".section .fixup,\"ax\"\n" \
+ "3: jmp 2b\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,3b\n" \
+ ".previous\n" \
+ : "+r"(size), "=&r"(w) \
+ : "a"(addr), "d"(0) \
+ : "memory"); \
+} while (0)
+
+unsigned long
+__clear_user(void *to, unsigned long n)
+{
+ __do_clear_user(to, n);
+ return n;
+}
+
+unsigned long
+clear_user(void *to, unsigned long n)
+{
+ if (access_ok(VERIFY_WRITE, to, n))
+ __do_clear_user(to, n);
+ return n;
+}
+
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return 0 on exception, a value greater than N if too long
+ */
+long strnlen_user(const char *s, long n)
+{
+ unsigned long res, w;
+
+ if (!__addr_ok(s))
+ return 0;
+
+ if (n < 0 || n + (u_long) s > current_thread_info()->addr_limit.seg)
+ n = current_thread_info()->addr_limit.seg - (u_long)s;
+
+ asm volatile(
+ "0: cmp %4,%0\n"
+ " beq 2f\n"
+ "1: movbu (%0,%3),%1\n"
+ " inc %0\n"
+ " cmp 0,%1\n"
+ " beq 3f\n"
+ " bra 0b\n"
+ "2: clr %0\n"
+ "3:\n"
+ ".section .fixup,\"ax\"\n"
+ "4: jmp 2b\n"
+ ".previous\n"
+ ".section __ex_table,\"a\"\n"
+ " .balign 4\n"
+ " .long 1b,4b\n"
+ ".previous\n"
+ :"=d"(res), "=&r"(w)
+ :"0"(0), "a"(s), "r"(n)
+ :"memory");
+ return res;
+}
--- /dev/null
+#
+# Makefile for the MN10300-specific memory management code
+#
+
+obj-y := \
+ init.o fault.o pgtable.o extable.o tlb-mn10300.o mmu-context.o \
+ misalignment.o dma-alloc.o
+
+ifneq ($(CONFIG_MN10300_CACHE_DISABLED),y)
+obj-y += cache.o cache-mn10300.o
+ifeq ($(CONFIG_MN10300_CACHE_WBACK),y)
+obj-y += cache-flush-mn10300.o
+endif
+endif
--- /dev/null
+/* MN10300 CPU core caching routines
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/smp.h>
+#include <asm/page.h>
+#include <asm/cache.h>
+
+ .am33_2
+ .globl mn10300_dcache_flush
+ .globl mn10300_dcache_flush_page
+ .globl mn10300_dcache_flush_range
+ .globl mn10300_dcache_flush_range2
+ .globl mn10300_dcache_flush_inv
+ .globl mn10300_dcache_flush_inv_page
+ .globl mn10300_dcache_flush_inv_range
+ .globl mn10300_dcache_flush_inv_range2
+
+###############################################################################
+#
+# void mn10300_dcache_flush(void)
+# Flush the entire data cache back to RAM
+#
+###############################################################################
+ ALIGN
+mn10300_dcache_flush:
+ movhu (CHCTR),d0
+ btst CHCTR_DCEN,d0
+ beq mn10300_dcache_flush_end
+
+ # read the addresses tagged in the cache's tag RAM and attempt to flush
+ # those addresses specifically
+ # - we rely on the hardware to filter out invalid tag entry addresses
+ mov DCACHE_TAG(0,0),a0 # dcache tag RAM access address
+ mov DCACHE_PURGE(0,0),a1 # dcache purge request address
+ mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of entries
+
+mn10300_dcache_flush_loop:
+ mov (a0),d0
+ and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0
+ or L1_CACHE_TAG_VALID,d0 # retain valid entries in the
+ # cache
+ mov d0,(a1) # conditional purge
+
+mn10300_dcache_flush_skip:
+ add L1_CACHE_BYTES,a0
+ add L1_CACHE_BYTES,a1
+ add -1,d1
+ bne mn10300_dcache_flush_loop
+
+mn10300_dcache_flush_end:
+ ret [],0
+
+###############################################################################
+#
+# void mn10300_dcache_flush_page(unsigned start)
+# void mn10300_dcache_flush_range(unsigned start, unsigned end)
+# void mn10300_dcache_flush_range2(unsigned start, unsigned size)
+# Flush a range of addresses on a page in the dcache
+#
+###############################################################################
+ ALIGN
+mn10300_dcache_flush_page:
+ mov PAGE_SIZE,d1
+mn10300_dcache_flush_range2:
+ add d0,d1
+mn10300_dcache_flush_range:
+ movm [d2,d3],(sp)
+
+ movhu (CHCTR),d2
+ btst CHCTR_DCEN,d2
+ beq mn10300_dcache_flush_range_end
+
+ # round start addr down
+ and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0
+ mov d0,a1
+
+ add L1_CACHE_BYTES,d1 # round end addr up
+ and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1
+
+ # write a request to flush all instances of an address from the cache
+ mov DCACHE_PURGE(0,0),a0
+ mov a1,d0
+ and L1_CACHE_TAG_ENTRY,d0
+ add d0,a0 # starting dcache purge control
+ # reg address
+
+ sub a1,d1
+ lsr L1_CACHE_SHIFT,d1 # total number of entries to
+ # examine
+
+ or L1_CACHE_TAG_VALID,a1 # retain valid entries in the
+ # cache
+
+mn10300_dcache_flush_range_loop:
+ mov a1,(L1_CACHE_WAYDISP*0,a0) # conditionally purge this line
+ # all ways
+
+ add L1_CACHE_BYTES,a0
+ add L1_CACHE_BYTES,a1
+ and ~L1_CACHE_WAYDISP,a0 # make sure way stay on way 0
+ add -1,d1
+ bne mn10300_dcache_flush_range_loop
+
+mn10300_dcache_flush_range_end:
+ ret [d2,d3],8
+
+###############################################################################
+#
+# void mn10300_dcache_flush_inv(void)
+# Flush the entire data cache and invalidate all entries
+#
+###############################################################################
+ ALIGN
+mn10300_dcache_flush_inv:
+ movhu (CHCTR),d0
+ btst CHCTR_DCEN,d0
+ beq mn10300_dcache_flush_inv_end
+
+ # hit each line in the dcache with an unconditional purge
+ mov DCACHE_PURGE(0,0),a1 # dcache purge request address
+ mov L1_CACHE_NWAYS*L1_CACHE_NENTRIES,d1 # total number of entries
+
+mn10300_dcache_flush_inv_loop:
+ mov (a1),d0 # unconditional purge
+
+ add L1_CACHE_BYTES,a1
+ add -1,d1
+ bne mn10300_dcache_flush_inv_loop
+
+mn10300_dcache_flush_inv_end:
+ ret [],0
+
+###############################################################################
+#
+# void mn10300_dcache_flush_inv_page(unsigned start)
+# void mn10300_dcache_flush_inv_range(unsigned start, unsigned end)
+# void mn10300_dcache_flush_inv_range2(unsigned start, unsigned size)
+# Flush and invalidate a range of addresses on a page in the dcache
+#
+###############################################################################
+ ALIGN
+mn10300_dcache_flush_inv_page:
+ mov PAGE_SIZE,d1
+mn10300_dcache_flush_inv_range2:
+ add d0,d1
+mn10300_dcache_flush_inv_range:
+ movm [d2,d3],(sp)
+ movhu (CHCTR),d2
+ btst CHCTR_DCEN,d2
+ beq mn10300_dcache_flush_inv_range_end
+
+ and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start
+ # addr down
+ mov d0,a1
+
+ add L1_CACHE_BYTES,d1 # round end addr up
+ and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1
+
+ # write a request to flush and invalidate all instances of an address
+ # from the cache
+ mov DCACHE_PURGE(0,0),a0
+ mov a1,d0
+ and L1_CACHE_TAG_ENTRY,d0
+ add d0,a0 # starting dcache purge control
+ # reg address
+
+ sub a1,d1
+ lsr L1_CACHE_SHIFT,d1 # total number of entries to
+ # examine
+
+mn10300_dcache_flush_inv_range_loop:
+ mov a1,(L1_CACHE_WAYDISP*0,a0) # conditionally purge this line
+ # in all ways
+
+ add L1_CACHE_BYTES,a0
+ add L1_CACHE_BYTES,a1
+ and ~L1_CACHE_WAYDISP,a0 # make sure way stay on way 0
+ add -1,d1
+ bne mn10300_dcache_flush_inv_range_loop
+
+mn10300_dcache_flush_inv_range_end:
+ ret [d2,d3],8
--- /dev/null
+/* MN10300 CPU core caching routines
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/smp.h>
+#include <asm/page.h>
+#include <asm/cache.h>
+
+#define mn10300_dcache_inv_range_intr_interval \
+ +((1 << MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL) - 1)
+
+#if mn10300_dcache_inv_range_intr_interval > 0xff
+#error MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL must be 8 or less
+#endif
+
+ .am33_2
+
+ .globl mn10300_icache_inv
+ .globl mn10300_dcache_inv
+ .globl mn10300_dcache_inv_range
+ .globl mn10300_dcache_inv_range2
+ .globl mn10300_dcache_inv_page
+
+###############################################################################
+#
+# void mn10300_icache_inv(void)
+# Invalidate the entire icache
+#
+###############################################################################
+ ALIGN
+mn10300_icache_inv:
+ mov CHCTR,a0
+
+ movhu (a0),d0
+ btst CHCTR_ICEN,d0
+ beq mn10300_icache_inv_end
+
+ mov epsw,d1
+ and ~EPSW_IE,epsw
+ nop
+ nop
+
+ # disable the icache
+ and ~CHCTR_ICEN,d0
+ movhu d0,(a0)
+
+ # and wait for it to calm down
+ setlb
+ movhu (a0),d0
+ btst CHCTR_ICBUSY,d0
+ lne
+
+ # invalidate
+ or CHCTR_ICINV,d0
+ movhu d0,(a0)
+
+ # wait for the cache to finish
+ mov CHCTR,a0
+ setlb
+ movhu (a0),d0
+ btst CHCTR_ICBUSY,d0
+ lne
+
+ # and reenable it
+ and ~CHCTR_ICINV,d0
+ or CHCTR_ICEN,d0
+ movhu d0,(a0)
+ movhu (a0),d0
+
+ mov d1,epsw
+
+mn10300_icache_inv_end:
+ ret [],0
+
+###############################################################################
+#
+# void mn10300_dcache_inv(void)
+# Invalidate the entire dcache
+#
+###############################################################################
+ ALIGN
+mn10300_dcache_inv:
+ mov CHCTR,a0
+
+ movhu (a0),d0
+ btst CHCTR_DCEN,d0
+ beq mn10300_dcache_inv_end
+
+ mov epsw,d1
+ and ~EPSW_IE,epsw
+ nop
+ nop
+
+ # disable the dcache
+ and ~CHCTR_DCEN,d0
+ movhu d0,(a0)
+
+ # and wait for it to calm down
+ setlb
+ movhu (a0),d0
+ btst CHCTR_DCBUSY,d0
+ lne
+
+ # invalidate
+ or CHCTR_DCINV,d0
+ movhu d0,(a0)
+
+ # wait for the cache to finish
+ mov CHCTR,a0
+ setlb
+ movhu (a0),d0
+ btst CHCTR_DCBUSY,d0
+ lne
+
+ # and reenable it
+ and ~CHCTR_DCINV,d0
+ or CHCTR_DCEN,d0
+ movhu d0,(a0)
+ movhu (a0),d0
+
+ mov d1,epsw
+
+mn10300_dcache_inv_end:
+ ret [],0
+
+###############################################################################
+#
+# void mn10300_dcache_inv_range(unsigned start, unsigned end)
+# void mn10300_dcache_inv_range2(unsigned start, unsigned size)
+# void mn10300_dcache_inv_page(unsigned start)
+# Invalidate a range of addresses on a page in the dcache
+#
+###############################################################################
+ ALIGN
+mn10300_dcache_inv_page:
+ mov PAGE_SIZE,d1
+mn10300_dcache_inv_range2:
+ add d0,d1
+mn10300_dcache_inv_range:
+ movm [d2,d3,a2],(sp)
+ mov CHCTR,a2
+
+ movhu (a2),d2
+ btst CHCTR_DCEN,d2
+ beq mn10300_dcache_inv_range_end
+
+ and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d0 # round start
+ # addr down
+ mov d0,a1
+
+ add L1_CACHE_BYTES,d1 # round end addr up
+ and L1_CACHE_TAG_ADDRESS|L1_CACHE_TAG_ENTRY,d1
+
+ clr d2 # we're going to clear tag ram
+ # entries
+
+ # read the tags from the tag RAM, and if they indicate a valid dirty
+ # cache line then invalidate that line
+ mov DCACHE_TAG(0,0),a0
+ mov a1,d0
+ and L1_CACHE_TAG_ENTRY,d0
+ add d0,a0 # starting dcache tag RAM
+ # access address
+
+ sub a1,d1
+ lsr L1_CACHE_SHIFT,d1 # total number of entries to
+ # examine
+
+ and ~(L1_CACHE_DISPARITY-1),a1 # determine comparator base
+
+mn10300_dcache_inv_range_outer_loop:
+ # disable interrupts
+ mov epsw,d3
+ and ~EPSW_IE,epsw
+ nop # note that reading CHCTR and
+ # AND'ing D0 occupy two delay
+ # slots after disabling
+ # interrupts
+
+ # disable the dcache
+ movhu (a2),d0
+ and ~CHCTR_DCEN,d0
+ movhu d0,(a2)
+
+ # and wait for it to calm down
+ setlb
+ movhu (a2),d0
+ btst CHCTR_DCBUSY,d0
+ lne
+
+mn10300_dcache_inv_range_loop:
+
+ # process the way 0 slot
+ mov (L1_CACHE_WAYDISP*0,a0),d0 # read the tag in the way 0 slot
+ btst L1_CACHE_TAG_VALID,d0
+ beq mn10300_dcache_inv_range_skip_0 # jump if this cacheline is not
+ # valid
+
+ xor a1,d0
+ lsr 12,d0
+ bne mn10300_dcache_inv_range_skip_0 # jump if not this cacheline
+
+ mov d2,(a0) # kill the tag
+
+mn10300_dcache_inv_range_skip_0:
+
+ # process the way 1 slot
+ mov (L1_CACHE_WAYDISP*1,a0),d0 # read the tag in the way 1 slot
+ btst L1_CACHE_TAG_VALID,d0
+ beq mn10300_dcache_inv_range_skip_1 # jump if this cacheline is not
+ # valid
+
+ xor a1,d0
+ lsr 12,d0
+ bne mn10300_dcache_inv_range_skip_1 # jump if not this cacheline
+
+ mov d2,(a0) # kill the tag
+
+mn10300_dcache_inv_range_skip_1:
+
+ # process the way 2 slot
+ mov (L1_CACHE_WAYDISP*2,a0),d0 # read the tag in the way 2 slot
+ btst L1_CACHE_TAG_VALID,d0
+ beq mn10300_dcache_inv_range_skip_2 # jump if this cacheline is not
+ # valid
+
+ xor a1,d0
+ lsr 12,d0
+ bne mn10300_dcache_inv_range_skip_2 # jump if not this cacheline
+
+ mov d2,(a0) # kill the tag
+
+mn10300_dcache_inv_range_skip_2:
+
+ # process the way 3 slot
+ mov (L1_CACHE_WAYDISP*3,a0),d0 # read the tag in the way 3 slot
+ btst L1_CACHE_TAG_VALID,d0
+ beq mn10300_dcache_inv_range_skip_3 # jump if this cacheline is not
+ # valid
+
+ xor a1,d0
+ lsr 12,d0
+ bne mn10300_dcache_inv_range_skip_3 # jump if not this cacheline
+
+ mov d2,(a0) # kill the tag
+
+mn10300_dcache_inv_range_skip_3:
+
+ # approx every N steps we re-enable the cache and see if there are any
+ # interrupts to be processed
+ # we also break out if we've reached the end of the loop
+ # (the bottom nibble of the count is zero in both cases)
+ add L1_CACHE_BYTES,a0
+ add L1_CACHE_BYTES,a1
+ add -1,d1
+ btst mn10300_dcache_inv_range_intr_interval,d1
+ bne mn10300_dcache_inv_range_loop
+
+ # wait for the cache to finish what it's doing
+ setlb
+ movhu (a2),d0
+ btst CHCTR_DCBUSY,d0
+ lne
+
+ # and reenable it
+ or CHCTR_DCEN,d0
+ movhu d0,(a2)
+ movhu (a2),d0
+
+ # re-enable interrupts
+ # - we don't bother with delay NOPs as we'll have enough instructions
+ # before we disable interrupts again to give the interrupts a chance
+ # to happen
+ mov d3,epsw
+
+ # go around again if the counter hasn't yet reached zero
+ add 0,d1
+ bne mn10300_dcache_inv_range_outer_loop
+
+mn10300_dcache_inv_range_end:
+ ret [d2,d3,a2],12
--- /dev/null
+/* MN10300 Cache flushing routines
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+#include <linux/threads.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <asm/uaccess.h>
+
+EXPORT_SYMBOL(mn10300_icache_inv);
+EXPORT_SYMBOL(mn10300_dcache_inv);
+EXPORT_SYMBOL(mn10300_dcache_inv_range);
+EXPORT_SYMBOL(mn10300_dcache_inv_range2);
+EXPORT_SYMBOL(mn10300_dcache_inv_page);
+
+#ifdef CONFIG_MN10300_CACHE_WBACK
+EXPORT_SYMBOL(mn10300_dcache_flush);
+EXPORT_SYMBOL(mn10300_dcache_flush_inv);
+EXPORT_SYMBOL(mn10300_dcache_flush_inv_range);
+EXPORT_SYMBOL(mn10300_dcache_flush_inv_range2);
+EXPORT_SYMBOL(mn10300_dcache_flush_inv_page);
+EXPORT_SYMBOL(mn10300_dcache_flush_range);
+EXPORT_SYMBOL(mn10300_dcache_flush_range2);
+EXPORT_SYMBOL(mn10300_dcache_flush_page);
+#endif
+
+/*
+ * write a page back from the dcache and invalidate the icache so that we can
+ * run code from it that we've just written into it
+ */
+void flush_icache_page(struct vm_area_struct *vma, struct page *page)
+{
+ mn10300_dcache_flush_page(page_to_phys(page));
+ mn10300_icache_inv();
+}
+EXPORT_SYMBOL(flush_icache_page);
+
+/*
+ * write some code we've just written back from the dcache and invalidate the
+ * icache so that we can run that code
+ */
+void flush_icache_range(unsigned long start, unsigned long end)
+{
+#ifdef CONFIG_MN10300_CACHE_WBACK
+ unsigned long addr, size, off;
+ struct page *page;
+ pgd_t *pgd;
+ pud_t *pud;
+ pmd_t *pmd;
+ pte_t *ppte, pte;
+
+ for (; start < end; start += size) {
+ /* work out how much of the page to flush */
+ off = start & (PAGE_SIZE - 1);
+
+ size = end - start;
+ if (size > PAGE_SIZE - off)
+ size = PAGE_SIZE - off;
+
+ /* get the physical address the page is mapped to from the page
+ * tables */
+ pgd = pgd_offset(current->mm, start);
+ if (!pgd || !pgd_val(*pgd))
+ continue;
+
+ pud = pud_offset(pgd, start);
+ if (!pud || !pud_val(*pud))
+ continue;
+
+ pmd = pmd_offset(pud, start);
+ if (!pmd || !pmd_val(*pmd))
+ continue;
+
+ ppte = pte_offset_map(pmd, start);
+ if (!ppte)
+ continue;
+ pte = *ppte;
+ pte_unmap(ppte);
+
+ if (pte_none(pte))
+ continue;
+
+ page = pte_page(pte);
+ if (!page)
+ continue;
+
+ addr = page_to_phys(page);
+
+ /* flush the dcache and invalidate the icache coverage on that
+ * region */
+ mn10300_dcache_flush_range2(addr + off, size);
+ }
+#endif
+
+ mn10300_icache_inv();
+}
+EXPORT_SYMBOL(flush_icache_range);
+
+/*
+ * allow userspace to flush the instruction cache
+ */
+asmlinkage long sys_cacheflush(unsigned long start, unsigned long end)
+{
+ if (end < start)
+ return -EINVAL;
+
+ flush_icache_range(start, end);
+ return 0;
+}
--- /dev/null
+/* MN10300 Dynamic DMA mapping support
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ * Derived from: arch/i386/kernel/pci-dma.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/string.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+
+void *dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, int gfp)
+{
+ unsigned long addr;
+ void *ret;
+
+ /* ignore region specifiers */
+ gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
+
+ if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
+ gfp |= GFP_DMA;
+
+ addr = __get_free_pages(gfp, get_order(size));
+ if (!addr)
+ return NULL;
+
+ /* map the coherent memory through the uncached memory window */
+ ret = (void *) (addr | 0x20000000);
+
+ /* fill the memory with obvious rubbish */
+ memset((void *) addr, 0xfb, size);
+
+ /* write back and evict all cache lines covering this region */
+ mn10300_dcache_flush_inv_range2(virt_to_phys((void *) addr), PAGE_SIZE);
+
+ *dma_handle = virt_to_bus((void *) addr);
+ return ret;
+}
+EXPORT_SYMBOL(dma_alloc_coherent);
+
+void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+ dma_addr_t dma_handle)
+{
+ unsigned long addr = (unsigned long) vaddr & ~0x20000000;
+
+ free_pages(addr, get_order(size));
+}
+EXPORT_SYMBOL(dma_free_coherent);
--- /dev/null
+/* MN10300 In-kernel exception handling
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <asm/uaccess.h>
+
+int fixup_exception(struct pt_regs *regs)
+{
+ const struct exception_table_entry *fixup;
+
+ fixup = search_exception_tables(regs->pc);
+ if (fixup) {
+ regs->pc = fixup->fixup;
+ return 1;
+ }
+
+ return 0;
+}
--- /dev/null
+/* MN10300 MMU Fault handler
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Modified by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/mman.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/vt_kern.h> /* For unblank_screen() */
+
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/pgalloc.h>
+#include <asm/hardirq.h>
+#include <asm/gdb-stub.h>
+#include <asm/cpu-regs.h>
+
+/*
+ * Unlock any spinlocks which will prevent us from getting the
+ * message out
+ */
+void bust_spinlocks(int yes)
+{
+ if (yes) {
+ oops_in_progress = 1;
+#ifdef CONFIG_SMP
+ /* Many serial drivers do __global_cli() */
+ global_irq_lock = 0;
+#endif
+ } else {
+ int loglevel_save = console_loglevel;
+#ifdef CONFIG_VT
+ unblank_screen();
+#endif
+ oops_in_progress = 0;
+ /*
+ * OK, the message is on the console. Now we call printk()
+ * without oops_in_progress set so that printk will give klogd
+ * a poke. Hold onto your hats...
+ */
+ console_loglevel = 15; /* NMI oopser may have shut the console
+ * up */
+ printk(" ");
+ console_loglevel = loglevel_save;
+ }
+}
+
+void do_BUG(const char *file, int line)
+{
+ bust_spinlocks(1);
+ printk(KERN_EMERG "------------[ cut here ]------------\n");
+ printk(KERN_EMERG "kernel BUG at %s:%d!\n", file, line);
+}
+
+#if 0
+static void print_pagetable_entries(pgd_t *pgdir, unsigned long address)
+{
+ pgd_t *pgd;
+ pmd_t *pmd;
+ pte_t *pte;
+
+ pgd = pgdir + __pgd_offset(address);
+ printk(KERN_DEBUG "pgd entry %p: %016Lx\n",
+ pgd, (long long) pgd_val(*pgd));
+
+ if (!pgd_present(*pgd)) {
+ printk(KERN_DEBUG "... pgd not present!\n");
+ return;
+ }
+ pmd = pmd_offset(pgd, address);
+ printk(KERN_DEBUG "pmd entry %p: %016Lx\n",
+ pmd, (long long)pmd_val(*pmd));
+
+ if (!pmd_present(*pmd)) {
+ printk(KERN_DEBUG "... pmd not present!\n");
+ return;
+ }
+ pte = pte_offset(pmd, address);
+ printk(KERN_DEBUG "pte entry %p: %016Lx\n",
+ pte, (long long) pte_val(*pte));
+
+ if (!pte_present(*pte))
+ printk(KERN_DEBUG "... pte not present!\n");
+}
+#endif
+
+asmlinkage void monitor_signal(struct pt_regs *);
+
+/*
+ * This routine handles page faults. It determines the address,
+ * and the problem, and then passes it off to one of the appropriate
+ * routines.
+ *
+ * fault_code:
+ * - LSW: either MMUFCR_IFC or MMUFCR_DFC as appropriate
+ * - MSW: 0 if data access, 1 if instruction access
+ * - bit 0: TLB miss flag
+ * - bit 1: initial write
+ * - bit 2: page invalid
+ * - bit 3: protection violation
+ * - bit 4: accessor (0=user 1=kernel)
+ * - bit 5: 0=read 1=write
+ * - bit 6-8: page protection spec
+ * - bit 9: illegal address
+ * - bit 16: 0=data 1=ins
+ *
+ */
+asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long fault_code,
+ unsigned long address)
+{
+ struct vm_area_struct *vma;
+ struct task_struct *tsk;
+ struct mm_struct *mm;
+ unsigned long page;
+ siginfo_t info;
+ int write, fault;
+
+#ifdef CONFIG_GDBSTUB
+ /* handle GDB stub causing a fault */
+ if (gdbstub_busy) {
+ gdbstub_exception(regs, TBR & TBR_INT_CODE);
+ return;
+ }
+#endif
+
+#if 0
+ printk(KERN_DEBUG "--- do_page_fault(%p,%s:%04lx,%08lx)\n",
+ regs,
+ fault_code & 0x10000 ? "ins" : "data",
+ fault_code & 0xffff, address);
+#endif
+
+ tsk = current;
+
+ /*
+ * We fault-in kernel-space virtual memory on-demand. The
+ * 'reference' page table is init_mm.pgd.
+ *
+ * NOTE! We MUST NOT take any locks for this case. We may
+ * be in an interrupt or a critical region, and should
+ * only copy the information from the master page table,
+ * nothing more.
+ *
+ * This verifies that the fault happens in kernel space
+ * and that the fault was a page not present (invalid) error
+ */
+ if (address >= VMALLOC_START && address < VMALLOC_END &&
+ (fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_SR &&
+ (fault_code & MMUFCR_xFC_PGINVAL) == MMUFCR_xFC_PGINVAL
+ )
+ goto vmalloc_fault;
+
+ mm = tsk->mm;
+ info.si_code = SEGV_MAPERR;
+
+ /*
+ * If we're in an interrupt or have no user
+ * context, we must not take the fault..
+ */
+ if (in_interrupt() || !mm)
+ goto no_context;
+
+ down_read(&mm->mmap_sem);
+
+ vma = find_vma(mm, address);
+ if (!vma)
+ goto bad_area;
+ if (vma->vm_start <= address)
+ goto good_area;
+ if (!(vma->vm_flags & VM_GROWSDOWN))
+ goto bad_area;
+
+ if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR) {
+ /* accessing the stack below the stack pointer is always a
+ * bug */
+ if ((address & PAGE_MASK) + 2 * PAGE_SIZE < regs->sp) {
+#if 0
+ printk(KERN_WARNING
+ "[%d] ### Access below stack @%lx (sp=%lx)\n",
+ current->pid, address, regs->sp);
+ printk(KERN_WARNING
+ "vma [%08x - %08x]\n",
+ vma->vm_start, vma->vm_end);
+ show_registers(regs);
+ printk(KERN_WARNING
+ "[%d] ### Code: [%08lx]"
+ " %02x %02x %02x %02x %02x %02x %02x %02x\n",
+ current->pid,
+ regs->pc,
+ ((u8 *) regs->pc)[0],
+ ((u8 *) regs->pc)[1],
+ ((u8 *) regs->pc)[2],
+ ((u8 *) regs->pc)[3],
+ ((u8 *) regs->pc)[4],
+ ((u8 *) regs->pc)[5],
+ ((u8 *) regs->pc)[6],
+ ((u8 *) regs->pc)[7]
+ );
+#endif
+ goto bad_area;
+ }
+ }
+
+ if (expand_stack(vma, address))
+ goto bad_area;
+
+/*
+ * Ok, we have a good vm_area for this memory access, so
+ * we can handle it..
+ */
+good_area:
+ info.si_code = SEGV_ACCERR;
+ write = 0;
+ switch (fault_code & (MMUFCR_xFC_PGINVAL|MMUFCR_xFC_TYPE)) {
+ default: /* 3: write, present */
+ case MMUFCR_xFC_TYPE_WRITE:
+#ifdef TEST_VERIFY_AREA
+ if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_SR)
+ printk(KERN_DEBUG "WP fault at %08lx\n", regs->pc);
+#endif
+ /* write to absent page */
+ case MMUFCR_xFC_PGINVAL | MMUFCR_xFC_TYPE_WRITE:
+ if (!(vma->vm_flags & VM_WRITE))
+ goto bad_area;
+ write++;
+ break;
+
+ /* read from protected page */
+ case MMUFCR_xFC_TYPE_READ:
+ goto bad_area;
+
+ /* read from absent page present */
+ case MMUFCR_xFC_PGINVAL | MMUFCR_xFC_TYPE_READ:
+ if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
+ goto bad_area;
+ break;
+ }
+
+ /*
+ * If for any reason at all we couldn't handle the fault,
+ * make sure we exit gracefully rather than endlessly redo
+ * the fault.
+ */
+ fault = handle_mm_fault(mm, vma, address, write);
+ if (unlikely(fault & VM_FAULT_ERROR)) {
+ if (fault & VM_FAULT_OOM)
+ goto out_of_memory;
+ else if (fault & VM_FAULT_SIGBUS)
+ goto do_sigbus;
+ BUG();
+ }
+ if (fault & VM_FAULT_MAJOR)
+ current->maj_flt++;
+ else
+ current->min_flt++;
+
+ up_read(&mm->mmap_sem);
+ return;
+
+/*
+ * Something tried to access memory that isn't in our memory map..
+ * Fix it, but check if it's kernel or user first..
+ */
+bad_area:
+ up_read(&mm->mmap_sem);
+ monitor_signal(regs);
+
+ /* User mode accesses just cause a SIGSEGV */
+ if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR) {
+ info.si_signo = SIGSEGV;
+ info.si_errno = 0;
+ /* info.si_code has been set above */
+ info.si_addr = (void *)address;
+ force_sig_info(SIGSEGV, &info, tsk);
+ return;
+ }
+
+no_context:
+ monitor_signal(regs);
+ /* Are we prepared to handle this kernel fault? */
+ if (fixup_exception(regs))
+ return;
+
+/*
+ * Oops. The kernel tried to access some bad page. We'll have to
+ * terminate things with extreme prejudice.
+ */
+
+ bust_spinlocks(1);
+
+ if (address < PAGE_SIZE)
+ printk(KERN_ALERT
+ "Unable to handle kernel NULL pointer dereference");
+ else
+ printk(KERN_ALERT
+ "Unable to handle kernel paging request");
+ printk(" at virtual address %08lx\n", address);
+ printk(" printing pc:\n");
+ printk(KERN_ALERT "%08lx\n", regs->pc);
+
+#ifdef CONFIG_GDBSTUB
+ gdbstub_intercept(
+ regs, fault_code & 0x00010000 ? EXCEP_IAERROR : EXCEP_DAERROR);
+#endif
+
+ page = PTBR;
+ page = ((unsigned long *) __va(page))[address >> 22];
+ printk(KERN_ALERT "*pde = %08lx\n", page);
+ if (page & 1) {
+ page &= PAGE_MASK;
+ address &= 0x003ff000;
+ page = ((unsigned long *) __va(page))[address >> PAGE_SHIFT];
+ printk(KERN_ALERT "*pte = %08lx\n", page);
+ }
+
+ die("Oops", regs, fault_code);
+ do_exit(SIGKILL);
+
+/*
+ * We ran out of memory, or some other thing happened to us that made
+ * us unable to handle the page fault gracefully.
+ */
+out_of_memory:
+ up_read(&mm->mmap_sem);
+ monitor_signal(regs);
+ printk(KERN_ALERT "VM: killing process %s\n", tsk->comm);
+ if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_USR)
+ do_exit(SIGKILL);
+ goto no_context;
+
+do_sigbus:
+ up_read(&mm->mmap_sem);
+ monitor_signal(regs);
+
+ /*
+ * Send a sigbus, regardless of whether we were in kernel
+ * or user mode.
+ */
+ info.si_signo = SIGBUS;
+ info.si_errno = 0;
+ info.si_code = BUS_ADRERR;
+ info.si_addr = (void *)address;
+ force_sig_info(SIGBUS, &info, tsk);
+
+ /* Kernel mode? Handle exceptions or die */
+ if ((fault_code & MMUFCR_xFC_ACCESS) == MMUFCR_xFC_ACCESS_SR)
+ goto no_context;
+ return;
+
+vmalloc_fault:
+ {
+ /*
+ * Synchronize this task's top level page-table
+ * with the 'reference' page table.
+ *
+ * Do _not_ use "tsk" here. We might be inside
+ * an interrupt in the middle of a task switch..
+ */
+ int index = pgd_index(address);
+ pgd_t *pgd, *pgd_k;
+ pud_t *pud, *pud_k;
+ pmd_t *pmd, *pmd_k;
+ pte_t *pte_k;
+
+ pgd_k = init_mm.pgd + index;
+
+ if (!pgd_present(*pgd_k))
+ goto no_context;
+
+ pud_k = pud_offset(pgd_k, address);
+ if (!pud_present(*pud_k))
+ goto no_context;
+
+ pmd_k = pmd_offset(pud_k, address);
+ if (!pmd_present(*pmd_k))
+ goto no_context;
+
+ pgd = (pgd_t *) PTBR + index;
+ pud = pud_offset(pgd, address);
+ pmd = pmd_offset(pud, address);
+ set_pmd(pmd, *pmd_k);
+
+ pte_k = pte_offset_kernel(pmd_k, address);
+ if (!pte_present(*pte_k))
+ goto no_context;
+ return;
+ }
+}
--- /dev/null
+/* MN10300 Memory management initialisation
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Modified by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/ptrace.h>
+#include <linux/mman.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/swap.h>
+#include <linux/smp.h>
+#include <linux/init.h>
+#include <linux/initrd.h>
+#include <linux/highmem.h>
+#include <linux/pagemap.h>
+#include <linux/bootmem.h>
+
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/dma.h>
+#include <asm/tlb.h>
+#include <asm/sections.h>
+
+DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
+
+unsigned long highstart_pfn, highend_pfn;
+
+/*
+ * set up paging
+ */
+void __init paging_init(void)
+{
+ unsigned long zones_size[MAX_NR_ZONES] = {0,};
+ pte_t *ppte;
+ int loop;
+
+ /* main kernel space -> RAM mapping is handled as 1:1 transparent by
+ * the MMU */
+ memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
+ memset(kernel_vmalloc_ptes, 0, sizeof(kernel_vmalloc_ptes));
+
+ /* load the VMALLOC area PTE table addresses into the kernel PGD */
+ ppte = kernel_vmalloc_ptes;
+ for (loop = VMALLOC_START / (PAGE_SIZE * PTRS_PER_PTE);
+ loop < VMALLOC_END / (PAGE_SIZE * PTRS_PER_PTE);
+ loop++
+ ) {
+ set_pgd(swapper_pg_dir + loop, __pgd(__pa(ppte) | _PAGE_TABLE));
+ ppte += PAGE_SIZE / sizeof(pte_t);
+ }
+
+ /* declare the sizes of the RAM zones (only use the normal zone) */
+ zones_size[ZONE_NORMAL] =
+ (contig_page_data.bdata->node_low_pfn) -
+ (contig_page_data.bdata->node_boot_start >> PAGE_SHIFT);
+
+ /* pass the memory from the bootmem allocator to the main allocator */
+ free_area_init(zones_size);
+
+ __flush_tlb_all();
+}
+
+/*
+ * transfer all the memory from the bootmem allocator to the runtime allocator
+ */
+void __init mem_init(void)
+{
+ int codesize, reservedpages, datasize, initsize;
+ int tmp;
+
+ if (!mem_map)
+ BUG();
+
+#define START_PFN (contig_page_data.bdata->node_boot_start >> PAGE_SHIFT)
+#define MAX_LOW_PFN (contig_page_data.bdata->node_low_pfn)
+
+ max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
+ high_memory = (void *) __va(MAX_LOW_PFN * PAGE_SIZE);
+
+ /* clear the zero-page */
+ memset(empty_zero_page, 0, PAGE_SIZE);
+
+ /* this will put all low memory onto the freelists */
+ totalram_pages += free_all_bootmem();
+
+ reservedpages = 0;
+ for (tmp = 0; tmp < num_physpages; tmp++)
+ if (PageReserved(&mem_map[tmp]))
+ reservedpages++;
+
+ codesize = (unsigned long) &_etext - (unsigned long) &_stext;
+ datasize = (unsigned long) &_edata - (unsigned long) &_etext;
+ initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
+
+ printk(KERN_INFO
+ "Memory: %luk/%luk available"
+ " (%dk kernel code, %dk reserved, %dk data, %dk init,"
+ " %ldk highmem)\n",
+ (unsigned long) nr_free_pages() << (PAGE_SHIFT - 10),
+ max_mapnr << (PAGE_SHIFT - 10),
+ codesize >> 10,
+ reservedpages << (PAGE_SHIFT - 10),
+ datasize >> 10,
+ initsize >> 10,
+ (unsigned long) (totalhigh_pages << (PAGE_SHIFT - 10))
+ );
+}
+
+/*
+ *
+ */
+void free_init_pages(char *what, unsigned long begin, unsigned long end)
+{
+ unsigned long addr;
+
+ for (addr = begin; addr < end; addr += PAGE_SIZE) {
+ ClearPageReserved(virt_to_page(addr));
+ init_page_count(virt_to_page(addr));
+ memset((void *) addr, 0xcc, PAGE_SIZE);
+ free_page(addr);
+ totalram_pages++;
+ }
+ printk(KERN_INFO "Freeing %s: %ldk freed\n", what, (end - begin) >> 10);
+}
+
+/*
+ * recycle memory containing stuff only required for initialisation
+ */
+void free_initmem(void)
+{
+ free_init_pages("unused kernel memory",
+ (unsigned long) &__init_begin,
+ (unsigned long) &__init_end);
+}
+
+/*
+ * dispose of the memory on which the initial ramdisk resided
+ */
+#ifdef CONFIG_BLK_DEV_INITRD
+void free_initrd_mem(unsigned long start, unsigned long end)
+{
+ free_init_pages("initrd memory", start, end);
+}
+#endif
--- /dev/null
+/* MN10300 Misalignment fixup handler
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/errno.h>
+#include <linux/ptrace.h>
+#include <linux/timer.h>
+#include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/smp_lock.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/atomic.h>
+#include <asm/smp.h>
+#include <asm/pgalloc.h>
+#include <asm/cpu-regs.h>
+#include <asm/busctl-regs.h>
+#include <asm/fpu.h>
+#include <asm/gdb-stub.h>
+#include <asm/asm-offsets.h>
+
+#if 0
+#define kdebug(FMT, ...) printk(KERN_DEBUG FMT, ##__VA_ARGS__)
+#else
+#define kdebug(FMT, ...) do {} while (0)
+#endif
+
+static int misalignment_addr(unsigned long *registers, unsigned params,
+ unsigned opcode, unsigned disp,
+ void **_address, unsigned long **_postinc);
+
+static int misalignment_reg(unsigned long *registers, unsigned params,
+ unsigned opcode, unsigned disp,
+ unsigned long **_register);
+
+static inline unsigned int_log2(unsigned x)
+{
+ unsigned y;
+ asm("bsch %1,%0" : "=r"(y) : "r"(x), "0"(0));
+ return y;
+}
+#define log2(x) int_log2(x)
+
+static const unsigned Dreg_index[] = {
+ REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
+};
+
+static const unsigned Areg_index[] = {
+ REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2
+};
+
+static const unsigned Rreg_index[] = {
+ REG_E0 >> 2, REG_E1 >> 2, REG_E2 >> 2, REG_E3 >> 2,
+ REG_E4 >> 2, REG_E5 >> 2, REG_E6 >> 2, REG_E7 >> 2,
+ REG_A0 >> 2, REG_A1 >> 2, REG_A2 >> 2, REG_A3 >> 2,
+ REG_D0 >> 2, REG_D1 >> 2, REG_D2 >> 2, REG_D3 >> 2
+};
+
+enum format_id {
+ FMT_S0,
+ FMT_S1,
+ FMT_S2,
+ FMT_S4,
+ FMT_D0,
+ FMT_D1,
+ FMT_D2,
+ FMT_D4,
+ FMT_D6,
+ FMT_D7,
+ FMT_D8,
+ FMT_D9,
+};
+
+struct {
+ u_int8_t opsz, dispsz;
+} format_tbl[16] = {
+ [FMT_S0] = { 8, 0 },
+ [FMT_S1] = { 8, 8 },
+ [FMT_S2] = { 8, 16 },
+ [FMT_S4] = { 8, 32 },
+ [FMT_D0] = { 16, 0 },
+ [FMT_D1] = { 16, 8 },
+ [FMT_D2] = { 16, 16 },
+ [FMT_D4] = { 16, 32 },
+ [FMT_D6] = { 24, 0 },
+ [FMT_D7] = { 24, 8 },
+ [FMT_D8] = { 24, 24 },
+ [FMT_D9] = { 24, 32 },
+};
+
+enum value_id {
+ DM0, /* data reg in opcode in bits 0-1 */
+ DM1, /* data reg in opcode in bits 2-3 */
+ DM2, /* data reg in opcode in bits 4-5 */
+ AM0, /* addr reg in opcode in bits 0-1 */
+ AM1, /* addr reg in opcode in bits 2-3 */
+ AM2, /* addr reg in opcode in bits 4-5 */
+ RM0, /* reg in opcode in bits 0-3 */
+ RM1, /* reg in opcode in bits 2-5 */
+ RM2, /* reg in opcode in bits 4-7 */
+ RM4, /* reg in opcode in bits 8-11 */
+ RM6, /* reg in opcode in bits 12-15 */
+
+ RD0, /* reg in displacement in bits 0-3 */
+ RD2, /* reg in displacement in bits 4-7 */
+
+ SP, /* stack pointer */
+
+ SD8, /* 8-bit signed displacement */
+ SD16, /* 16-bit signed displacement */
+ SD24, /* 24-bit signed displacement */
+ SIMM4_2, /* 4-bit signed displacement in opcode bits 4-7 */
+ SIMM8, /* 8-bit signed immediate */
+ IMM24, /* 24-bit unsigned immediate */
+ IMM32, /* 32-bit unsigned immediate */
+ IMM32_HIGH8, /* 32-bit unsigned immediate, high 8-bits in opcode */
+
+ DN0 = DM0,
+ DN1 = DM1,
+ DN2 = DM2,
+ AN0 = AM0,
+ AN1 = AM1,
+ AN2 = AM2,
+ RN0 = RM0,
+ RN1 = RM1,
+ RN2 = RM2,
+ RN4 = RM4,
+ RN6 = RM6,
+ DI = DM1,
+ RI = RM2,
+
+};
+
+struct mn10300_opcode {
+ const char *name;
+ u_int32_t opcode;
+ u_int32_t opmask;
+ unsigned exclusion;
+
+ enum format_id format;
+
+ unsigned cpu_mask;
+#define AM33 330
+
+ unsigned params[2];
+#define MEM(ADDR) (0x80000000 | (ADDR))
+#define MEM2(ADDR1, ADDR2) (0x80000000 | (ADDR1) << 8 | (ADDR2))
+#define MEMINC(ADDR) (0x81000000 | (ADDR))
+#define MEMINC2(ADDR, INC) (0x81000000 | (ADDR) << 8 | (INC))
+};
+
+/* LIBOPCODES EXCERPT
+ Assemble Matsushita MN10300 instructions.
+ Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public Licence as published by
+ the Free Software Foundation; either version 2 of the Licence, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public Licence for more details.
+
+ You should have received a copy of the GNU General Public Licence
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+*/
+static const struct mn10300_opcode mn10300_opcodes[] = {
+{ "mov", 0x60, 0xf0, 0, FMT_S0, 0, {DM1, MEM(AN0)}},
+{ "mov", 0x70, 0xf0, 0, FMT_S0, 0, {MEM(AM0), DN1}},
+{ "mov", 0xf000, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), AN1}},
+{ "mov", 0xf010, 0xfff0, 0, FMT_D0, 0, {AM1, MEM(AN0)}},
+{ "mov", 0xf300, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
+{ "mov", 0xf340, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
+{ "mov", 0xf380, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), AN2}},
+{ "mov", 0xf3c0, 0xffc0, 0, FMT_D0, 0, {AM2, MEM2(DI, AN0)}},
+{ "mov", 0xf80000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
+{ "mov", 0xf81000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
+{ "mov", 0xf82000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8,AM0), AN1}},
+{ "mov", 0xf83000, 0xfff000, 0, FMT_D1, 0, {AM1, MEM2(SD8, AN0)}},
+{ "mov", 0xf8f000, 0xfffc00, 0, FMT_D1, AM33, {MEM2(SD8, AM0), SP}},
+{ "mov", 0xf8f400, 0xfffc00, 0, FMT_D1, AM33, {SP, MEM2(SD8, AN0)}},
+{ "mov", 0xf90a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
+{ "mov", 0xf91a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
+{ "mov", 0xf96a00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
+{ "mov", 0xf97a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
+{ "mov", 0xfa000000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
+{ "mov", 0xfa100000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
+{ "mov", 0xfa200000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), AN1}},
+{ "mov", 0xfa300000, 0xfff00000, 0, FMT_D2, 0, {AM1, MEM2(SD16, AN0)}},
+{ "mov", 0xfb0a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
+{ "mov", 0xfb1a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
+{ "mov", 0xfb6a0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
+{ "mov", 0xfb7a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
+{ "mov", 0xfb8e0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
+{ "mov", 0xfb9e0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
+{ "mov", 0xfc000000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
+{ "mov", 0xfc100000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
+{ "mov", 0xfc200000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), AN1}},
+{ "mov", 0xfc300000, 0xfff00000, 0, FMT_D4, 0, {AM1, MEM2(IMM32,AN0)}},
+{ "mov", 0xfd0a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
+{ "mov", 0xfd1a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
+{ "mov", 0xfd6a0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
+{ "mov", 0xfd7a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
+{ "mov", 0xfe0a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
+{ "mov", 0xfe1a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
+{ "mov", 0xfe6a0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
+{ "mov", 0xfe7a0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
+
+{ "movhu", 0xf060, 0xfff0, 0, FMT_D0, 0, {MEM(AM0), DN1}},
+{ "movhu", 0xf070, 0xfff0, 0, FMT_D0, 0, {DM1, MEM(AN0)}},
+{ "movhu", 0xf480, 0xffc0, 0, FMT_D0, 0, {MEM2(DI, AM0), DN2}},
+{ "movhu", 0xf4c0, 0xffc0, 0, FMT_D0, 0, {DM2, MEM2(DI, AN0)}},
+{ "movhu", 0xf86000, 0xfff000, 0, FMT_D1, 0, {MEM2(SD8, AM0), DN1}},
+{ "movhu", 0xf87000, 0xfff000, 0, FMT_D1, 0, {DM1, MEM2(SD8, AN0)}},
+{ "movhu", 0xf94a00, 0xffff00, 0, FMT_D6, AM33, {MEM(RM0), RN2}},
+{ "movhu", 0xf95a00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEM(RN0)}},
+{ "movhu", 0xf9ea00, 0xffff00, 0x12, FMT_D6, AM33, {MEMINC(RM0), RN2}},
+{ "movhu", 0xf9fa00, 0xffff00, 0, FMT_D6, AM33, {RM2, MEMINC(RN0)}},
+{ "movhu", 0xfa600000, 0xfff00000, 0, FMT_D2, 0, {MEM2(SD16, AM0), DN1}},
+{ "movhu", 0xfa700000, 0xfff00000, 0, FMT_D2, 0, {DM1, MEM2(SD16, AN0)}},
+{ "movhu", 0xfb4a0000, 0xffff0000, 0, FMT_D7, AM33, {MEM2(SD8, RM0), RN2}},
+{ "movhu", 0xfb5a0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEM2(SD8, RN0)}},
+{ "movhu", 0xfbce0000, 0xffff000f, 0, FMT_D7, AM33, {MEM2(RI, RM0), RD2}},
+{ "movhu", 0xfbde0000, 0xffff000f, 0, FMT_D7, AM33, {RD2, MEM2(RI, RN0)}},
+{ "movhu", 0xfbea0000, 0xffff0000, 0x22, FMT_D7, AM33, {MEMINC2 (RM0, SIMM8), RN2}},
+{ "movhu", 0xfbfa0000, 0xffff0000, 0, FMT_D7, AM33, {RM2, MEMINC2 (RN0, SIMM8)}},
+{ "movhu", 0xfc600000, 0xfff00000, 0, FMT_D4, 0, {MEM2(IMM32,AM0), DN1}},
+{ "movhu", 0xfc700000, 0xfff00000, 0, FMT_D4, 0, {DM1, MEM2(IMM32,AN0)}},
+{ "movhu", 0xfd4a0000, 0xffff0000, 0, FMT_D8, AM33, {MEM2(SD24, RM0), RN2}},
+{ "movhu", 0xfd5a0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEM2(SD24, RN0)}},
+{ "movhu", 0xfdea0000, 0xffff0000, 0x22, FMT_D8, AM33, {MEMINC2 (RM0, IMM24), RN2}},
+{ "movhu", 0xfdfa0000, 0xffff0000, 0, FMT_D8, AM33, {RM2, MEMINC2 (RN0, IMM24)}},
+{ "movhu", 0xfe4a0000, 0xffff0000, 0, FMT_D9, AM33, {MEM2(IMM32_HIGH8,RM0), RN2}},
+{ "movhu", 0xfe5a0000, 0xffff0000, 0, FMT_D9, AM33, {RM2, MEM2(IMM32_HIGH8, RN0)}},
+{ "movhu", 0xfeea0000, 0xffff0000, 0x22, FMT_D9, AM33, {MEMINC2 (RM0, IMM32_HIGH8), RN2}},
+{ "movhu", 0xfefa0000, 0xffff0000, 0, FMT_D9, AM33, {RN2, MEMINC2 (RM0, IMM32_HIGH8)}},
+{ 0, 0, 0, 0, 0, 0, {0}},
+};
+
+/*
+ * fix up misalignment problems where possible
+ */
+asmlinkage void misalignment(struct pt_regs *regs, enum exception_code code)
+{
+ const struct exception_table_entry *fixup;
+ const struct mn10300_opcode *pop;
+ unsigned long *registers = (unsigned long *) regs;
+ unsigned long data, *store, *postinc;
+ mm_segment_t seg;
+ siginfo_t info;
+ uint32_t opcode, disp, noc, xo, xm;
+ uint8_t *pc, byte;
+ void *address;
+ unsigned tmp, npop;
+
+ kdebug("MISALIGN at %lx\n", regs->pc);
+
+ if (in_interrupt())
+ die("Misalignment trap in interrupt context", regs, code);
+
+ if (regs->epsw & EPSW_IE)
+ asm volatile("or %0,epsw" : : "i"(EPSW_IE));
+
+ seg = get_fs();
+ set_fs(KERNEL_DS);
+
+ fixup = search_exception_tables(regs->pc);
+
+ /* first thing to do is to match the opcode */
+ pc = (u_int8_t *) regs->pc;
+
+ if (__get_user(byte, pc) != 0)
+ goto fetch_error;
+ opcode = byte;
+ noc = 8;
+
+ for (pop = mn10300_opcodes; pop->name; pop++) {
+ npop = log2(pop->opcode | pop->opmask);
+ if (npop <= 0 || npop > 31)
+ continue;
+ npop = (npop + 8) & ~7;
+
+ got_more_bits:
+ if (npop == noc) {
+ if ((opcode & pop->opmask) == pop->opcode)
+ goto found_opcode;
+ } else if (npop > noc) {
+ xo = pop->opcode >> (npop - noc);
+ xm = pop->opmask >> (npop - noc);
+
+ if ((opcode & xm) != xo)
+ continue;
+
+ /* we've got a partial match (an exact match on the
+ * first N bytes), so we need to get some more data */
+ pc++;
+ if (__get_user(byte, pc) != 0)
+ goto fetch_error;
+ opcode = opcode << 8 | byte;
+ noc += 8;
+ goto got_more_bits;
+ } else {
+ /* there's already been a partial match as long as the
+ * complete match we're now considering, so this one
+ * should't match */
+ continue;
+ }
+ }
+
+ /* didn't manage to find a fixup */
+ if (!user_mode(regs))
+ printk(KERN_CRIT "MISALIGN: %lx: unsupported instruction %x\n",
+ regs->pc, opcode);
+
+failed:
+ set_fs(seg);
+ if (die_if_no_fixup("misalignment error", regs, code))
+ return;
+
+ info.si_signo = SIGBUS;
+ info.si_errno = 0;
+ info.si_code = BUS_ADRALN;
+ info.si_addr = (void *) regs->pc;
+ force_sig_info(SIGBUS, &info, current);
+ return;
+
+ /* error reading opcodes */
+fetch_error:
+ if (!user_mode(regs))
+ printk(KERN_CRIT
+ "MISALIGN: %p: fault whilst reading instruction data\n",
+ pc);
+ goto failed;
+
+bad_addr_mode:
+ if (!user_mode(regs))
+ printk(KERN_CRIT
+ "MISALIGN: %lx: unsupported addressing mode %x\n",
+ regs->pc, opcode);
+ goto failed;
+
+bad_reg_mode:
+ if (!user_mode(regs))
+ printk(KERN_CRIT
+ "MISALIGN: %lx: unsupported register mode %x\n",
+ regs->pc, opcode);
+ goto failed;
+
+unsupported_instruction:
+ if (!user_mode(regs))
+ printk(KERN_CRIT
+ "MISALIGN: %lx: unsupported instruction %x (%s)\n",
+ regs->pc, opcode, pop->name);
+ goto failed;
+
+transfer_failed:
+ set_fs(seg);
+ if (fixup) {
+ regs->pc = fixup->fixup;
+ return;
+ }
+ if (die_if_no_fixup("misalignment fixup", regs, code))
+ return;
+
+ info.si_signo = SIGSEGV;
+ info.si_errno = 0;
+ info.si_code = 0;
+ info.si_addr = (void *) regs->pc;
+ force_sig_info(SIGSEGV, &info, current);
+ return;
+
+ /* we matched the opcode */
+found_opcode:
+ kdebug("MISALIGN: %lx: %x==%x { %x, %x }\n",
+ regs->pc, opcode, pop->opcode, pop->params[0], pop->params[1]);
+
+ tmp = format_tbl[pop->format].opsz;
+ if (tmp > noc)
+ BUG(); /* match was less complete than it ought to have been */
+
+ if (tmp < noc) {
+ tmp = noc - tmp;
+ opcode >>= tmp;
+ pc -= tmp >> 3;
+ }
+
+ /* grab the extra displacement (note it's LSB first) */
+ disp = 0;
+ tmp = format_tbl[pop->format].dispsz >> 3;
+ while (tmp > 0) {
+ tmp--;
+ disp <<= 8;
+
+ pc++;
+ if (__get_user(byte, pc) != 0)
+ goto fetch_error;
+ disp |= byte;
+ }
+
+ set_fs(KERNEL_XDS);
+ if (fixup || regs->epsw & EPSW_nSL)
+ set_fs(seg);
+
+ tmp = (pop->params[0] ^ pop->params[1]) & 0x80000000;
+ if (!tmp) {
+ if (!user_mode(regs))
+ printk(KERN_CRIT
+ "MISALIGN: %lx:"
+ " insn not move to/from memory %x\n",
+ regs->pc, opcode);
+ goto failed;
+ }
+
+ if (pop->params[0] & 0x80000000) {
+ /* move memory to register */
+ if (!misalignment_addr(registers, pop->params[0], opcode, disp,
+ &address, &postinc))
+ goto bad_addr_mode;
+
+ if (!misalignment_reg(registers, pop->params[1], opcode, disp,
+ &store))
+ goto bad_reg_mode;
+
+ if (strcmp(pop->name, "mov") == 0) {
+ kdebug("FIXUP: mov (%p),DARn\n", address);
+ if (copy_from_user(&data, (void *) address, 4) != 0)
+ goto transfer_failed;
+ if (pop->params[0] & 0x1000000)
+ *postinc += 4;
+ } else if (strcmp(pop->name, "movhu") == 0) {
+ kdebug("FIXUP: movhu (%p),DARn\n", address);
+ data = 0;
+ if (copy_from_user(&data, (void *) address, 2) != 0)
+ goto transfer_failed;
+ if (pop->params[0] & 0x1000000)
+ *postinc += 2;
+ } else {
+ goto unsupported_instruction;
+ }
+
+ *store = data;
+ } else {
+ /* move register to memory */
+ if (!misalignment_reg(registers, pop->params[0], opcode, disp,
+ &store))
+ goto bad_reg_mode;
+
+ if (!misalignment_addr(registers, pop->params[1], opcode, disp,
+ &address, &postinc))
+ goto bad_addr_mode;
+
+ data = *store;
+
+ if (strcmp(pop->name, "mov") == 0) {
+ kdebug("FIXUP: mov %lx,(%p)\n", data, address);
+ if (copy_to_user((void *) address, &data, 4) != 0)
+ goto transfer_failed;
+ if (pop->params[1] & 0x1000000)
+ *postinc += 4;
+ } else if (strcmp(pop->name, "movhu") == 0) {
+ kdebug("FIXUP: movhu %hx,(%p)\n",
+ (uint16_t) data, address);
+ if (copy_to_user((void *) address, &data, 2) != 0)
+ goto transfer_failed;
+ if (pop->params[1] & 0x1000000)
+ *postinc += 2;
+ } else {
+ goto unsupported_instruction;
+ }
+ }
+
+ tmp = format_tbl[pop->format].opsz + format_tbl[pop->format].dispsz;
+ regs->pc += tmp >> 3;
+
+ set_fs(seg);
+ return;
+}
+
+/*
+ * determine the address that was being accessed
+ */
+static int misalignment_addr(unsigned long *registers, unsigned params,
+ unsigned opcode, unsigned disp,
+ void **_address, unsigned long **_postinc)
+{
+ unsigned long *postinc = NULL, address = 0, tmp;
+
+ params &= 0x7fffffff;
+
+ do {
+ switch (params & 0xff) {
+ case DM0:
+ postinc = ®isters[Dreg_index[opcode & 0x03]];
+ address += *postinc;
+ break;
+ case DM1:
+ postinc = ®isters[Dreg_index[opcode >> 2 & 0x0c]];
+ address += *postinc;
+ break;
+ case DM2:
+ postinc = ®isters[Dreg_index[opcode >> 4 & 0x30]];
+ address += *postinc;
+ break;
+ case AM0:
+ postinc = ®isters[Areg_index[opcode & 0x03]];
+ address += *postinc;
+ break;
+ case AM1:
+ postinc = ®isters[Areg_index[opcode >> 2 & 0x0c]];
+ address += *postinc;
+ break;
+ case AM2:
+ postinc = ®isters[Areg_index[opcode >> 4 & 0x30]];
+ address += *postinc;
+ break;
+ case RM0:
+ postinc = ®isters[Rreg_index[opcode & 0x0f]];
+ address += *postinc;
+ break;
+ case RM1:
+ postinc = ®isters[Rreg_index[opcode >> 2 & 0x0f]];
+ address += *postinc;
+ break;
+ case RM2:
+ postinc = ®isters[Rreg_index[opcode >> 4 & 0x0f]];
+ address += *postinc;
+ break;
+ case RM4:
+ postinc = ®isters[Rreg_index[opcode >> 8 & 0x0f]];
+ address += *postinc;
+ break;
+ case RM6:
+ postinc = ®isters[Rreg_index[opcode >> 12 & 0x0f]];
+ address += *postinc;
+ break;
+ case RD0:
+ postinc = ®isters[Rreg_index[disp & 0x0f]];
+ address += *postinc;
+ break;
+ case RD2:
+ postinc = ®isters[Rreg_index[disp >> 4 & 0x0f]];
+ address += *postinc;
+ break;
+
+ case SD8:
+ case SIMM8:
+ address += (int32_t) (int8_t) (disp & 0xff);
+ break;
+ case SD16:
+ address += (int32_t) (int16_t) (disp & 0xffff);
+ break;
+ case SD24:
+ tmp = disp << 8;
+ asm("asr 8,%0" : "=r"(tmp) : "0"(tmp));
+ address += tmp;
+ break;
+ case SIMM4_2:
+ tmp = opcode >> 4 & 0x0f;
+ tmp <<= 28;
+ asm("asr 28,%0" : "=r"(tmp) : "0"(tmp));
+ address += tmp;
+ break;
+ case IMM24:
+ address += disp & 0x00ffffff;
+ break;
+ case IMM32:
+ case IMM32_HIGH8:
+ address += disp;
+ break;
+ default:
+ return 0;
+ }
+ } while ((params >>= 8));
+
+ *_address = (void *) address;
+ *_postinc = postinc;
+ return 1;
+}
+
+/*
+ * determine the register that is acting as source/dest
+ */
+static int misalignment_reg(unsigned long *registers, unsigned params,
+ unsigned opcode, unsigned disp,
+ unsigned long **_register)
+{
+ params &= 0x7fffffff;
+
+ if (params & 0xffffff00)
+ return 0;
+
+ switch (params & 0xff) {
+ case DM0:
+ *_register = ®isters[Dreg_index[opcode & 0x03]];
+ break;
+ case DM1:
+ *_register = ®isters[Dreg_index[opcode >> 2 & 0x03]];
+ break;
+ case DM2:
+ *_register = ®isters[Dreg_index[opcode >> 4 & 0x03]];
+ break;
+ case AM0:
+ *_register = ®isters[Areg_index[opcode & 0x03]];
+ break;
+ case AM1:
+ *_register = ®isters[Areg_index[opcode >> 2 & 0x03]];
+ break;
+ case AM2:
+ *_register = ®isters[Areg_index[opcode >> 4 & 0x03]];
+ break;
+ case RM0:
+ *_register = ®isters[Rreg_index[opcode & 0x0f]];
+ break;
+ case RM1:
+ *_register = ®isters[Rreg_index[opcode >> 2 & 0x0f]];
+ break;
+ case RM2:
+ *_register = ®isters[Rreg_index[opcode >> 4 & 0x0f]];
+ break;
+ case RM4:
+ *_register = ®isters[Rreg_index[opcode >> 8 & 0x0f]];
+ break;
+ case RM6:
+ *_register = ®isters[Rreg_index[opcode >> 12 & 0x0f]];
+ break;
+ case RD0:
+ *_register = ®isters[Rreg_index[disp & 0x0f]];
+ break;
+ case RD2:
+ *_register = ®isters[Rreg_index[disp >> 4 & 0x0f]];
+ break;
+ case SP:
+ *_register = ®isters[REG_SP >> 2];
+ break;
+
+ default:
+ return 0;
+ }
+
+ return 1;
+}
--- /dev/null
+/* MN10300 MMU context allocation and management
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/mmu_context.h>
+#include <asm/tlbflush.h>
+
+/*
+ * list of the MMU contexts last allocated on each CPU
+ */
+unsigned long mmu_context_cache[NR_CPUS] = {
+ [0 ... NR_CPUS - 1] = MMU_CONTEXT_FIRST_VERSION * 2 - 1,
+};
+
+/*
+ * flush the specified TLB entry
+ */
+void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
+{
+ unsigned long pteu, cnx, flags;
+
+ addr &= PAGE_MASK;
+
+ /* make sure the context doesn't migrate and defend against
+ * interference from vmalloc'd regions */
+ local_irq_save(flags);
+
+ cnx = mm_context(vma->vm_mm);
+
+ if (cnx != MMU_NO_CONTEXT) {
+ pteu = addr | (cnx & 0x000000ffUL);
+ IPTEU = pteu;
+ DPTEU = pteu;
+ if (IPTEL & xPTEL_V)
+ IPTEL = 0;
+ if (DPTEL & xPTEL_V)
+ DPTEL = 0;
+ }
+
+ local_irq_restore(flags);
+}
+
+/*
+ * preemptively set a TLB entry
+ */
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+{
+ unsigned long pteu, ptel, cnx, flags;
+
+ addr &= PAGE_MASK;
+ ptel = pte_val(pte) & ~(xPTEL_UNUSED1 | xPTEL_UNUSED2);
+
+ /* make sure the context doesn't migrate and defend against
+ * interference from vmalloc'd regions */
+ local_irq_save(flags);
+
+ cnx = mm_context(vma->vm_mm);
+
+ if (cnx != MMU_NO_CONTEXT) {
+ pteu = addr | (cnx & 0x000000ffUL);
+ if (!(pte_val(pte) & _PAGE_NX)) {
+ IPTEU = pteu;
+ if (IPTEL & xPTEL_V)
+ IPTEL = ptel;
+ }
+ DPTEU = pteu;
+ if (DPTEL & xPTEL_V)
+ DPTEL = ptel;
+ }
+
+ local_irq_restore(flags);
+}
--- /dev/null
+/* MN10300 Page table management
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Modified by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/sched.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/mm.h>
+#include <linux/swap.h>
+#include <linux/smp.h>
+#include <linux/highmem.h>
+#include <linux/slab.h>
+#include <linux/pagemap.h>
+#include <linux/spinlock.h>
+#include <linux/quicklist.h>
+
+#include <asm/system.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/tlb.h>
+#include <asm/tlbflush.h>
+
+void show_mem(void)
+{
+ unsigned long i;
+ int free = 0, total = 0, reserved = 0, shared = 0;
+
+ int cached = 0;
+ printk(KERN_INFO "Mem-info:\n");
+ show_free_areas();
+ i = max_mapnr;
+ while (i-- > 0) {
+ total++;
+ if (PageReserved(mem_map + i))
+ reserved++;
+ else if (PageSwapCache(mem_map + i))
+ cached++;
+ else if (!page_count(mem_map + i))
+ free++;
+ else
+ shared += page_count(mem_map + i) - 1;
+ }
+ printk(KERN_INFO "%d pages of RAM\n", total);
+ printk(KERN_INFO "%d free pages\n", free);
+ printk(KERN_INFO "%d reserved pages\n", reserved);
+ printk(KERN_INFO "%d pages shared\n", shared);
+ printk(KERN_INFO "%d pages swap cached\n", cached);
+}
+
+/*
+ * Associate a large virtual page frame with a given physical page frame
+ * and protection flags for that frame. pfn is for the base of the page,
+ * vaddr is what the page gets mapped to - both must be properly aligned.
+ * The pmd must already be instantiated. Assumes PAE mode.
+ */
+void set_pmd_pfn(unsigned long vaddr, unsigned long pfn, pgprot_t flags)
+{
+ pgd_t *pgd;
+ pud_t *pud;
+ pmd_t *pmd;
+
+ if (vaddr & (PMD_SIZE-1)) { /* vaddr is misaligned */
+ printk(KERN_ERR "set_pmd_pfn: vaddr misaligned\n");
+ return; /* BUG(); */
+ }
+ if (pfn & (PTRS_PER_PTE-1)) { /* pfn is misaligned */
+ printk(KERN_ERR "set_pmd_pfn: pfn misaligned\n");
+ return; /* BUG(); */
+ }
+ pgd = swapper_pg_dir + pgd_index(vaddr);
+ if (pgd_none(*pgd)) {
+ printk(KERN_ERR "set_pmd_pfn: pgd_none\n");
+ return; /* BUG(); */
+ }
+ pud = pud_offset(pgd, vaddr);
+ pmd = pmd_offset(pud, vaddr);
+ set_pmd(pmd, pfn_pmd(pfn, flags));
+ /*
+ * It's enough to flush this one mapping.
+ * (PGE mappings get flushed as well)
+ */
+ __flush_tlb_one(vaddr);
+}
+
+pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
+{
+ pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT);
+ if (pte)
+ clear_page(pte);
+ return pte;
+}
+
+struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+ struct page *pte;
+
+#ifdef CONFIG_HIGHPTE
+ pte = alloc_pages(GFP_KERNEL|__GFP_HIGHMEM|__GFP_REPEAT, 0);
+#else
+ pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0);
+#endif
+ if (pte)
+ clear_highpage(pte);
+ return pte;
+}
+
+/*
+ * List of all pgd's needed for non-PAE so it can invalidate entries
+ * in both cached and uncached pgd's; not needed for PAE since the
+ * kernel pmd is shared. If PAE were not to share the pmd a similar
+ * tactic would be needed. This is essentially codepath-based locking
+ * against pageattr.c; it is the unique case in which a valid change
+ * of kernel pagetables can't be lazily synchronized by vmalloc faults.
+ * vmalloc faults work because attached pagetables are never freed.
+ * If the locking proves to be non-performant, a ticketing scheme with
+ * checks at dup_mmap(), exec(), and other mmlist addition points
+ * could be used. The locking scheme was chosen on the basis of
+ * manfred's recommendations and having no core impact whatsoever.
+ * -- wli
+ */
+DEFINE_SPINLOCK(pgd_lock);
+struct page *pgd_list;
+
+static inline void pgd_list_add(pgd_t *pgd)
+{
+ struct page *page = virt_to_page(pgd);
+ page->index = (unsigned long) pgd_list;
+ if (pgd_list)
+ set_page_private(pgd_list, (unsigned long) &page->index);
+ pgd_list = page;
+ set_page_private(page, (unsigned long) &pgd_list);
+}
+
+static inline void pgd_list_del(pgd_t *pgd)
+{
+ struct page *next, **pprev, *page = virt_to_page(pgd);
+ next = (struct page *) page->index;
+ pprev = (struct page **) page_private(page);
+ *pprev = next;
+ if (next)
+ set_page_private(next, (unsigned long) pprev);
+}
+
+void pgd_ctor(void *pgd)
+{
+ unsigned long flags;
+
+ if (PTRS_PER_PMD == 1)
+ spin_lock_irqsave(&pgd_lock, flags);
+
+ memcpy((pgd_t *)pgd + USER_PTRS_PER_PGD,
+ swapper_pg_dir + USER_PTRS_PER_PGD,
+ (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+
+ if (PTRS_PER_PMD > 1)
+ return;
+
+ pgd_list_add(pgd);
+ spin_unlock_irqrestore(&pgd_lock, flags);
+ memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
+}
+
+/* never called when PTRS_PER_PMD > 1 */
+void pgd_dtor(void *pgd)
+{
+ unsigned long flags; /* can be called from interrupt context */
+
+ spin_lock_irqsave(&pgd_lock, flags);
+ pgd_list_del(pgd);
+ spin_unlock_irqrestore(&pgd_lock, flags);
+}
+
+pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+ return quicklist_alloc(0, GFP_KERNEL, pgd_ctor);
+}
+
+void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+ quicklist_free(0, pgd_dtor, pgd);
+}
+
+void __init pgtable_cache_init(void)
+{
+}
+
+void check_pgt_cache(void)
+{
+ quicklist_trim(0, pgd_dtor, 25, 16);
+}
--- /dev/null
+###############################################################################
+#
+# TLB loading functions
+#
+# Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+# Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+# Modified by David Howells (dhowells@redhat.com)
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public Licence
+# as published by the Free Software Foundation; either version
+# 2 of the Licence, or (at your option) any later version.
+#
+###############################################################################
+#include <linux/sys.h>
+#include <linux/linkage.h>
+#include <asm/smp.h>
+#include <asm/intctl-regs.h>
+#include <asm/frame.inc>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+###############################################################################
+#
+# Instruction TLB Miss handler entry point
+#
+###############################################################################
+ .type itlb_miss,@function
+ENTRY(itlb_miss)
+ and ~EPSW_NMID,epsw
+#ifdef CONFIG_GDBSTUB
+ movm [d2,d3,a2],(sp)
+#else
+ or EPSW_nAR,epsw # switch D0-D3 & A0-A3 to the alternate
+ # register bank
+ nop
+ nop
+ nop
+#endif
+
+ mov (IPTEU),d3
+ mov (PTBR),a2
+ mov d3,d2
+ and 0xffc00000,d2
+ lsr 20,d2
+ mov (a2,d2),a2 # PTD *ptd = PGD[addr 31..22]
+ btst _PAGE_VALID,a2
+ beq itlb_miss_fault # jump if doesn't point anywhere
+
+ and ~(PAGE_SIZE-1),a2
+ mov d3,d2
+ and 0x003ff000,d2
+ lsr 10,d2
+ add d2,a2
+ mov (a2),d2 # get pte from PTD[addr 21..12]
+ btst _PAGE_VALID,d2
+ beq itlb_miss_fault # jump if doesn't point to a page
+ # (might be a swap id)
+ bset _PAGE_ACCESSED,(0,a2)
+ and ~(xPTEL_UNUSED1|xPTEL_UNUSED2),d2
+itlb_miss_set:
+ mov d2,(IPTEL) # change the TLB
+#ifdef CONFIG_GDBSTUB
+ movm (sp),[d2,d3,a2]
+#endif
+ rti
+
+itlb_miss_fault:
+ mov _PAGE_VALID,d2 # force address error handler to be
+ # invoked
+ bra itlb_miss_set
+
+ .size itlb_miss, . - itlb_miss
+
+###############################################################################
+#
+# Data TLB Miss handler entry point
+#
+###############################################################################
+ .type dtlb_miss,@function
+ENTRY(dtlb_miss)
+ and ~EPSW_NMID,epsw
+#ifdef CONFIG_GDBSTUB
+ movm [d2,d3,a2],(sp)
+#else
+ or EPSW_nAR,epsw # switch D0-D3 & A0-A3 to the alternate
+ # register bank
+ nop
+ nop
+ nop
+#endif
+
+ mov (DPTEU),d3
+ mov (PTBR),a2
+ mov d3,d2
+ and 0xffc00000,d2
+ lsr 20,d2
+ mov (a2,d2),a2 # PTD *ptd = PGD[addr 31..22]
+ btst _PAGE_VALID,a2
+ beq dtlb_miss_fault # jump if doesn't point anywhere
+
+ and ~(PAGE_SIZE-1),a2
+ mov d3,d2
+ and 0x003ff000,d2
+ lsr 10,d2
+ add d2,a2
+ mov (a2),d2 # get pte from PTD[addr 21..12]
+ btst _PAGE_VALID,d2
+ beq dtlb_miss_fault # jump if doesn't point to a page
+ # (might be a swap id)
+ bset _PAGE_ACCESSED,(0,a2)
+ and ~(xPTEL_UNUSED1|xPTEL_UNUSED2),d2
+dtlb_miss_set:
+ mov d2,(DPTEL) # change the TLB
+#ifdef CONFIG_GDBSTUB
+ movm (sp),[d2,d3,a2]
+#endif
+ rti
+
+dtlb_miss_fault:
+ mov _PAGE_VALID,d2 # force address error handler to be
+ # invoked
+ bra dtlb_miss_set
+ .size dtlb_miss, . - dtlb_miss
+
+###############################################################################
+#
+# Instruction TLB Address Error handler entry point
+#
+###############################################################################
+ .type itlb_aerror,@function
+ENTRY(itlb_aerror)
+ and ~EPSW_NMID,epsw
+ add -4,sp
+ SAVE_ALL
+ add -4,sp # need to pass three params
+
+ # calculate the fault code
+ movhu (MMUFCR_IFC),d1
+ or 0x00010000,d1 # it's an instruction fetch
+
+ # determine the page address
+ mov (IPTEU),a2
+ mov a2,d0
+ and PAGE_MASK,d0
+ mov d0,(12,sp)
+
+ clr d0
+ mov d0,(IPTEL)
+
+ and ~EPSW_NMID,epsw
+ or EPSW_IE,epsw
+ mov fp,d0
+ call do_page_fault[],0 # do_page_fault(regs,code,addr
+
+ jmp ret_from_exception
+ .size itlb_aerror, . - itlb_aerror
+
+###############################################################################
+#
+# Data TLB Address Error handler entry point
+#
+###############################################################################
+ .type dtlb_aerror,@function
+ENTRY(dtlb_aerror)
+ and ~EPSW_NMID,epsw
+ add -4,sp
+ mov d1,(sp)
+
+ movhu (MMUFCR_DFC),d1 # is it the initial valid write
+ # to this page?
+ and MMUFCR_xFC_INITWR,d1
+ beq dtlb_pagefault # jump if not
+
+ mov (DPTEL),d1 # set the dirty bit
+ # (don't replace with BSET!)
+ or _PAGE_DIRTY,d1
+ mov d1,(DPTEL)
+ mov (sp),d1
+ add 4,sp
+ rti
+
+ ALIGN
+dtlb_pagefault:
+ mov (sp),d1
+ SAVE_ALL
+ add -4,sp # need to pass three params
+
+ # calculate the fault code
+ movhu (MMUFCR_DFC),d1
+
+ # determine the page address
+ mov (DPTEU),a2
+ mov a2,d0
+ and PAGE_MASK,d0
+ mov d0,(12,sp)
+
+ clr d0
+ mov d0,(DPTEL)
+
+ and ~EPSW_NMID,epsw
+ or EPSW_IE,epsw
+ mov fp,d0
+ call do_page_fault[],0 # do_page_fault(regs,code,addr
+
+ jmp ret_from_exception
+ .size dtlb_aerror, . - dtlb_aerror
--- /dev/null
+
+menu "Profiling support"
+ depends on EXPERIMENTAL
+
+config PROFILING
+ bool "Profiling support (EXPERIMENTAL)"
+ help
+ Say Y here to enable the extended profiling support mechanisms used
+ by profilers such as OProfile.
+
+
+config OPROFILE
+ tristate "OProfile system profiling (EXPERIMENTAL)"
+ depends on PROFILING
+ help
+ OProfile is a profiling system capable of profiling the
+ whole system, include the kernel, kernel modules, libraries,
+ and applications.
+
+ If unsure, say N.
+
+endmenu
+
--- /dev/null
+#
+# Makefile for the MN10300-specific profiling code
+#
+obj-$(CONFIG_OPROFILE) += oprofile.o
+
+DRIVER_OBJS = $(addprefix ../../../drivers/oprofile/, \
+ oprof.o cpu_buffer.o buffer_sync.o \
+ event_buffer.o oprofile_files.o \
+ oprofilefs.o oprofile_stats.o \
+ timer_int.o )
+
+oprofile-y := $(DRIVER_OBJS) op_model_null.o
+
--- /dev/null
+/* Null profiling driver
+ *
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * Licence. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/kernel.h>
+#include <linux/oprofile.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+
+int __init oprofile_arch_init(struct oprofile_operations *ops)
+{
+ return -ENODEV;
+}
+
+void oprofile_arch_exit(void)
+{
+}
+
--- /dev/null
+#
+# Makefile for the MN103E010 processor chip specific code
+#
+obj-y := proc-init.o
+
--- /dev/null
+/* MN103E010 Processor initialisation
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <asm/rtc.h>
+
+/*
+ * initialise the on-silicon processor peripherals
+ */
+asmlinkage void __init processor_init(void)
+{
+ int loop;
+
+ /* set up the exception table first */
+ for (loop = 0x000; loop < 0x400; loop += 8)
+ __set_intr_stub(loop, __common_exception);
+
+ __set_intr_stub(EXCEP_ITLBMISS, itlb_miss);
+ __set_intr_stub(EXCEP_DTLBMISS, dtlb_miss);
+ __set_intr_stub(EXCEP_IAERROR, itlb_aerror);
+ __set_intr_stub(EXCEP_DAERROR, dtlb_aerror);
+ __set_intr_stub(EXCEP_BUSERROR, raw_bus_error);
+ __set_intr_stub(EXCEP_DOUBLE_FAULT, double_fault);
+ __set_intr_stub(EXCEP_SYSCALL0, system_call);
+
+ __set_intr_stub(EXCEP_NMI, nmi_handler);
+ __set_intr_stub(EXCEP_WDT, nmi_handler);
+ __set_intr_stub(EXCEP_IRQ_LEVEL0, irq_handler);
+ __set_intr_stub(EXCEP_IRQ_LEVEL1, irq_handler);
+ __set_intr_stub(EXCEP_IRQ_LEVEL2, irq_handler);
+ __set_intr_stub(EXCEP_IRQ_LEVEL3, irq_handler);
+ __set_intr_stub(EXCEP_IRQ_LEVEL4, irq_handler);
+ __set_intr_stub(EXCEP_IRQ_LEVEL5, irq_handler);
+ __set_intr_stub(EXCEP_IRQ_LEVEL6, irq_handler);
+
+ IVAR0 = EXCEP_IRQ_LEVEL0;
+ IVAR1 = EXCEP_IRQ_LEVEL1;
+ IVAR2 = EXCEP_IRQ_LEVEL2;
+ IVAR3 = EXCEP_IRQ_LEVEL3;
+ IVAR4 = EXCEP_IRQ_LEVEL4;
+ IVAR5 = EXCEP_IRQ_LEVEL5;
+ IVAR6 = EXCEP_IRQ_LEVEL6;
+
+ mn10300_dcache_flush_inv();
+ mn10300_icache_inv();
+
+ /* disable all interrupts and set to priority 6 (lowest) */
+ for (loop = 0; loop < NR_IRQS; loop++)
+ GxICR(loop) = GxICR_LEVEL_6 | GxICR_DETECT;
+
+ /* clear the timers */
+ TM0MD = 0;
+ TM1MD = 0;
+ TM2MD = 0;
+ TM3MD = 0;
+ TM4MD = 0;
+ TM5MD = 0;
+ TM6MD = 0;
+ TM6MDA = 0;
+ TM6MDB = 0;
+ TM7MD = 0;
+ TM8MD = 0;
+ TM9MD = 0;
+ TM10MD = 0;
+ TM11MD = 0;
+
+ calibrate_clock();
+}
--- /dev/null
+###############################################################################
+#
+# Makefile for the ASB2303 board
+#
+###############################################################################
+obj-y := unit-init.o smc91111.o flash.o leds.o
--- /dev/null
+/* Handle mapping of the flash on the ASB2303 board
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+
+#define ASB2303_PROM_ADDR 0xA0000000 /* Boot PROM */
+#define ASB2303_PROM_SIZE (2 * 1024 * 1024)
+#define ASB2303_FLASH_ADDR 0xA4000000 /* System Flash */
+#define ASB2303_FLASH_SIZE (32 * 1024 * 1024)
+#define ASB2303_CONFIG_ADDR 0xA6000000 /* System Config EEPROM */
+#define ASB2303_CONFIG_SIZE (8 * 1024)
+
+/*
+ * default MTD partition table for both main flash devices, expected to be
+ * overridden by RedBoot
+ */
+static struct mtd_partition asb2303_partitions[] = {
+ {
+ .name = "Bootloader",
+ .size = 0x00040000,
+ .offset = 0,
+ .mask_flags = MTD_CAP_ROM /* force read-only */
+ }, {
+ .name = "Kernel",
+ .size = 0x00400000,
+ .offset = 0x00040000,
+ }, {
+ .name = "Filesystem",
+ .size = MTDPART_SIZ_FULL,
+ .offset = 0x00440000
+ }
+};
+
+/*
+ * the ASB2303 Boot PROM definition
+ */
+static struct physmap_flash_data asb2303_bootprom_data = {
+ .width = 2,
+ .nr_parts = 1,
+ .parts = asb2303_partitions,
+};
+
+static struct resource asb2303_bootprom_resource = {
+ .start = ASB2303_PROM_ADDR,
+ .end = ASB2303_PROM_ADDR + ASB2303_PROM_SIZE,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device asb2303_bootprom = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev.platform_data = &asb2303_bootprom_data,
+ .num_resources = 1,
+ .resource = &asb2303_bootprom_resource,
+};
+
+/*
+ * the ASB2303 System Flash definition
+ */
+static struct physmap_flash_data asb2303_sysflash_data = {
+ .width = 4,
+ .nr_parts = 1,
+ .parts = asb2303_partitions,
+};
+
+static struct resource asb2303_sysflash_resource = {
+ .start = ASB2303_FLASH_ADDR,
+ .end = ASB2303_FLASH_ADDR + ASB2303_FLASH_SIZE,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device asb2303_sysflash = {
+ .name = "physmap-flash",
+ .id = 1,
+ .dev.platform_data = &asb2303_sysflash_data,
+ .num_resources = 1,
+ .resource = &asb2303_sysflash_resource,
+};
+
+/*
+ * register the ASB2303 flashes
+ */
+static int __init asb2303_mtd_init(void)
+{
+ platform_device_register(&asb2303_bootprom);
+ platform_device_register(&asb2303_sysflash);
+ return 0;
+}
+
+module_init(asb2303_mtd_init);
--- /dev/null
+/* ASB2303 peripheral 7-segment LEDs x1 support
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/intctl-regs.h>
+#include <asm/rtc-regs.h>
+#include <asm/unit/leds.h>
+
+#if 0
+static const u8 asb2303_led_hex_tbl[16] = {
+ 0x80, 0xf2, 0x48, 0x60, 0x32, 0x24, 0x04, 0xf0,
+ 0x00, 0x20, 0x10, 0x06, 0x8c, 0x42, 0x0c, 0x1c
+};
+#endif
+
+static const u8 asb2303_led_chase_tbl[6] = {
+ ~0x02, /* top - segA */
+ ~0x04, /* right top - segB */
+ ~0x08, /* right bottom - segC */
+ ~0x10, /* bottom - segD */
+ ~0x20, /* left bottom - segE */
+ ~0x40, /* left top - segF */
+};
+
+static unsigned asb2303_led_chase;
+
+void peripheral_leds_display_exception(enum exception_code code)
+{
+ ASB2303_GPIO0DEF = 0x5555; /* configure as an output port */
+ ASB2303_7SEGLEDS = 0x6d; /* triple horizontal bar */
+}
+
+void peripheral_leds_led_chase(void)
+{
+ ASB2303_GPIO0DEF = 0x5555; /* configure as an output port */
+ ASB2303_7SEGLEDS = asb2303_led_chase_tbl[asb2303_led_chase];
+ asb2303_led_chase++;
+ if (asb2303_led_chase >= 6)
+ asb2303_led_chase = 0;
+}
--- /dev/null
+/* ASB2303 initialisation
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/io.h>
+#include <asm/timex.h>
+#include <asm/processor.h>
+#include <asm/intctl-regs.h>
+#include <asm/unit/smc91111.h>
+
+static struct resource smc91c111_resources[] = {
+ [0] = {
+ .start = SMC91111_BASE,
+ .end = SMC91111_BASE_END,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = SMC91111_IRQ,
+ .end = SMC91111_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device smc91c111_device = {
+ .name = "smc91x",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(smc91c111_resources),
+ .resource = smc91c111_resources,
+};
+
+/*
+ * add platform devices
+ */
+static int __init unit_device_init(void)
+{
+ platform_device_register(&smc91c111_device);
+ return 0;
+}
+
+device_initcall(unit_device_init);
--- /dev/null
+/* ASB2303 initialisation
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/device.h>
+
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/processor.h>
+#include <asm/irq.h>
+#include <asm/intctl-regs.h>
+
+/*
+ * initialise some of the unit hardware before gdbstub is set up
+ */
+asmlinkage void __init unit_init(void)
+{
+ /* set up the external interrupts */
+ SET_XIRQ_TRIGGER(0, XIRQ_TRIGGER_HILEVEL);
+ SET_XIRQ_TRIGGER(2, XIRQ_TRIGGER_LOWLEVEL);
+ SET_XIRQ_TRIGGER(3, XIRQ_TRIGGER_HILEVEL);
+ SET_XIRQ_TRIGGER(4, XIRQ_TRIGGER_LOWLEVEL);
+ SET_XIRQ_TRIGGER(5, XIRQ_TRIGGER_LOWLEVEL);
+}
+
+/*
+ * initialise the rest of the unit hardware after gdbstub is ready
+ */
+void __init unit_setup(void)
+{
+}
+
+/*
+ * initialise the external interrupts used by a unit of this type
+ */
+void __init unit_init_IRQ(void)
+{
+ unsigned int extnum;
+
+ for (extnum = 0; extnum < NR_XIRQS; extnum++) {
+ switch (GET_XIRQ_TRIGGER(extnum)) {
+ case XIRQ_TRIGGER_HILEVEL:
+ case XIRQ_TRIGGER_LOWLEVEL:
+ set_irq_handler(XIRQ2IRQ(extnum), handle_level_irq);
+ break;
+ default:
+ break;
+ }
+ }
+}
--- /dev/null
+###############################################################################
+#
+# Makefile for the ASB2305 board
+#
+###############################################################################
+obj-y := unit-init.o leds.o
+
+obj-$(CONFIG_PCI) += pci.o pci-asb2305.o pci-irq.o pci-iomap.o
--- /dev/null
+/* ASB2305 Peripheral 7-segment LEDs x4 support
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/cpu/intctl-regs.h>
+#include <asm/cpu/rtc-regs.h>
+#include <asm/unit/leds.h>
+
+static const u8 asb2305_led_hex_tbl[16] = {
+ 0x80, 0xf2, 0x48, 0x60, 0x32, 0x24, 0x04, 0xf0,
+ 0x00, 0x20, 0x10, 0x06, 0x8c, 0x42, 0x0c, 0x1c
+};
+
+static const u32 asb2305_led_chase_tbl[6] = {
+ ~0x02020202, /* top - segA */
+ ~0x04040404, /* right top - segB */
+ ~0x08080808, /* right bottom - segC */
+ ~0x10101010, /* bottom - segD */
+ ~0x20202020, /* left bottom - segE */
+ ~0x40404040, /* left top - segF */
+};
+
+static unsigned asb2305_led_chase;
+
+void peripheral_leds7x4_display_dec(unsigned int val, unsigned int points)
+{
+ u32 leds;
+
+ leds = asb2305_led_hex_tbl[(val/1000) % 10];
+ leds <<= 8;
+ leds |= asb2305_led_hex_tbl[(val/100) % 10];
+ leds <<= 8;
+ leds |= asb2305_led_hex_tbl[(val/10) % 10];
+ leds <<= 8;
+ leds |= asb2305_led_hex_tbl[val % 10];
+ leds |= points^0x01010101;
+
+ ASB2305_7SEGLEDS = leds;
+}
+
+void peripheral_leds7x4_display_hex(unsigned int val, unsigned int points)
+{
+ u32 leds;
+
+ leds = asb2305_led_hex_tbl[(val/1000) % 10];
+ leds <<= 8;
+ leds |= asb2305_led_hex_tbl[(val/100) % 10];
+ leds <<= 8;
+ leds |= asb2305_led_hex_tbl[(val/10) % 10];
+ leds <<= 8;
+ leds |= asb2305_led_hex_tbl[val % 10];
+ leds |= points^0x01010101;
+
+ ASB2305_7SEGLEDS = leds;
+}
+
+void peripheral_leds_display_exception(enum exception_code code)
+{
+ u32 leds;
+
+ leds = asb2305_led_hex_tbl[(code/0x100) % 0x10];
+ leds <<= 8;
+ leds |= asb2305_led_hex_tbl[(code/0x10) % 0x10];
+ leds <<= 8;
+ leds |= asb2305_led_hex_tbl[code % 0x10];
+ leds |= 0x6d010101;
+
+ ASB2305_7SEGLEDS = leds;
+}
+
+void peripheral_leds7x4_display_minssecs(unsigned int time, unsigned int points)
+{
+ u32 leds;
+
+ leds = asb2305_led_hex_tbl[(time/600) % 6];
+ leds <<= 8;
+ leds |= asb2305_led_hex_tbl[(time/60) % 10];
+ leds <<= 8;
+ leds |= asb2305_led_hex_tbl[(time/10) % 6];
+ leds <<= 8;
+ leds |= asb2305_led_hex_tbl[time % 10];
+ leds |= points^0x01010101;
+
+ ASB2305_7SEGLEDS = leds;
+}
+
+void peripheral_leds7x4_display_rtc(void)
+{
+ unsigned int clock;
+ u8 mins, secs;
+
+ mins = RTMCR;
+ secs = RTSCR;
+
+ clock = ((mins & 0xf0) >> 4);
+ clock *= 10;
+ clock += (mins & 0x0f);
+ clock *= 6;
+
+ clock += ((secs & 0xf0) >> 4);
+ clock *= 10;
+ clock += (secs & 0x0f);
+
+ peripheral_leds7x4_display_minssecs(clock, 0);
+}
+
+void peripheral_leds_led_chase(void)
+{
+ ASB2305_7SEGLEDS = asb2305_led_chase_tbl[asb2305_led_chase];
+ asb2305_led_chase++;
+ if (asb2305_led_chase >= 6)
+ asb2305_led_chase = 0;
+}
--- /dev/null
+/* ASB2305 PCI resource stuff
+ *
+ * Copyright (C) 2001 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ * - Derived from arch/i386/pci-i386.c
+ * - Copyright 1997--2000 Martin Mares <mj@suse.cz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/errno.h>
+#include "pci-asb2305.h"
+
+/*
+ * We need to avoid collisions with `mirrored' VGA ports
+ * and other strange ISA hardware, so we always want the
+ * addresses to be allocated in the 0x000-0x0ff region
+ * modulo 0x400.
+ *
+ * Why? Because some silly external IO cards only decode
+ * the low 10 bits of the IO address. The 0x00-0xff region
+ * is reserved for motherboard devices that decode all 16
+ * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
+ * but we want to try to avoid allocating at 0x2900-0x2bff
+ * which might have be mirrored at 0x0100-0x03ff..
+ */
+void pcibios_align_resource(void *data, struct resource *res,
+ resource_size_t size, resource_size_t align)
+{
+#if 0
+ struct pci_dev *dev = data;
+
+ printk(KERN_DEBUG
+ "### PCIBIOS_ALIGN_RESOURCE(%s,,{%08lx-%08lx,%08lx},%lx)\n",
+ pci_name(dev),
+ res->start,
+ res->end,
+ res->flags,
+ size
+ );
+#endif
+
+ if (res->flags & IORESOURCE_IO) {
+ unsigned long start = res->start;
+
+ if (start & 0x300) {
+ start = (start + 0x3ff) & ~0x3ff;
+ res->start = start;
+ }
+ }
+}
+
+
+/*
+ * Handle resources of PCI devices. If the world were perfect, we could
+ * just allocate all the resource regions and do nothing more. It isn't.
+ * On the other hand, we cannot just re-allocate all devices, as it would
+ * require us to know lots of host bridge internals. So we attempt to
+ * keep as much of the original configuration as possible, but tweak it
+ * when it's found to be wrong.
+ *
+ * Known BIOS problems we have to work around:
+ * - I/O or memory regions not configured
+ * - regions configured, but not enabled in the command register
+ * - bogus I/O addresses above 64K used
+ * - expansion ROMs left enabled (this may sound harmless, but given
+ * the fact the PCI specs explicitly allow address decoders to be
+ * shared between expansion ROMs and other resource regions, it's
+ * at least dangerous)
+ *
+ * Our solution:
+ * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
+ * This gives us fixed barriers on where we can allocate.
+ * (2) Allocate resources for all enabled devices. If there is
+ * a collision, just mark the resource as unallocated. Also
+ * disable expansion ROMs during this step.
+ * (3) Try to allocate resources for disabled devices. If the
+ * resources were assigned correctly, everything goes well,
+ * if they weren't, they won't disturb allocation of other
+ * resources.
+ * (4) Assign new addresses to resources which were either
+ * not configured at all or misconfigured. If explicitly
+ * requested by the user, configure expansion ROM address
+ * as well.
+ */
+static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
+{
+ struct pci_bus *bus;
+ struct pci_dev *dev;
+ int idx;
+ struct resource *r, *pr;
+
+ /* Depth-First Search on bus tree */
+ list_for_each_entry(bus, bus_list, node) {
+ dev = bus->self;
+ if (dev) {
+ for (idx = PCI_BRIDGE_RESOURCES;
+ idx < PCI_NUM_RESOURCES;
+ idx++) {
+ r = &dev->resource[idx];
+ if (!r->flags)
+ continue;
+ pr = pci_find_parent_resource(dev, r);
+ if (!r->start ||
+ !pr ||
+ request_resource(pr, r) < 0) {
+ printk(KERN_ERR "PCI:"
+ " Cannot allocate resource"
+ " region %d of bridge %s\n",
+ idx, pci_name(dev));
+ /* Something is wrong with the region.
+ * Invalidate the resource to prevent
+ * child resource allocations in this
+ * range. */
+ r->flags = 0;
+ }
+ }
+ }
+ pcibios_allocate_bus_resources(&bus->children);
+ }
+}
+
+static void __init pcibios_allocate_resources(int pass)
+{
+ struct pci_dev *dev = NULL;
+ int idx, disabled;
+ u16 command;
+ struct resource *r, *pr;
+
+ for_each_pci_dev(dev) {
+ pci_read_config_word(dev, PCI_COMMAND, &command);
+ for (idx = 0; idx < 6; idx++) {
+ r = &dev->resource[idx];
+ if (r->parent) /* Already allocated */
+ continue;
+ if (!r->start) /* Address not assigned */
+ continue;
+ if (r->flags & IORESOURCE_IO)
+ disabled = !(command & PCI_COMMAND_IO);
+ else
+ disabled = !(command & PCI_COMMAND_MEMORY);
+ if (pass == disabled) {
+ DBG("PCI[%s]: Resource %08lx-%08lx"
+ " (f=%lx, d=%d, p=%d)\n",
+ pci_name(dev), r->start, r->end, r->flags,
+ disabled, pass);
+ pr = pci_find_parent_resource(dev, r);
+ if (!pr || request_resource(pr, r) < 0) {
+ printk(KERN_ERR "PCI:"
+ " Cannot allocate resource"
+ " region %d of device %s\n",
+ idx, pci_name(dev));
+ /* We'll assign a new address later */
+ r->end -= r->start;
+ r->start = 0;
+ }
+ }
+ }
+ if (!pass) {
+ r = &dev->resource[PCI_ROM_RESOURCE];
+ if (r->flags & IORESOURCE_ROM_ENABLE) {
+ /* Turn the ROM off, leave the resource region,
+ * but keep it unregistered. */
+ u32 reg;
+ DBG("PCI: Switching off ROM of %s\n",
+ pci_name(dev));
+ r->flags &= ~IORESOURCE_ROM_ENABLE;
+ pci_read_config_dword(
+ dev, dev->rom_base_reg, ®);
+ pci_write_config_dword(
+ dev, dev->rom_base_reg,
+ reg & ~PCI_ROM_ADDRESS_ENABLE);
+ }
+ }
+ }
+}
+
+static int __init pcibios_assign_resources(void)
+{
+ struct pci_dev *dev = NULL;
+ struct resource *r, *pr;
+
+ if (!(pci_probe & PCI_ASSIGN_ROMS)) {
+ /* Try to use BIOS settings for ROMs, otherwise let
+ pci_assign_unassigned_resources() allocate the new
+ addresses. */
+ for_each_pci_dev(dev) {
+ r = &dev->resource[PCI_ROM_RESOURCE];
+ if (!r->flags || !r->start)
+ continue;
+ pr = pci_find_parent_resource(dev, r);
+ if (!pr || request_resource(pr, r) < 0) {
+ r->end -= r->start;
+ r->start = 0;
+ }
+ }
+ }
+
+ pci_assign_unassigned_resources();
+
+ return 0;
+}
+
+fs_initcall(pcibios_assign_resources);
+
+void __init pcibios_resource_survey(void)
+{
+ DBG("PCI: Allocating resources\n");
+ pcibios_allocate_bus_resources(&pci_root_buses);
+ pcibios_allocate_resources(0);
+ pcibios_allocate_resources(1);
+}
+
+int pcibios_enable_resources(struct pci_dev *dev, int mask)
+{
+ u16 cmd, old_cmd;
+ int idx;
+ struct resource *r;
+
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ old_cmd = cmd;
+
+ for (idx = 0; idx < 6; idx++) {
+ /* Only set up the requested stuff */
+ if (!(mask & (1 << idx)))
+ continue;
+
+ r = &dev->resource[idx];
+
+ if (!r->start && r->end) {
+ printk(KERN_ERR
+ "PCI: Device %s not available because of"
+ " resource collisions\n",
+ pci_name(dev));
+ return -EINVAL;
+ }
+
+ if (r->flags & IORESOURCE_IO)
+ cmd |= PCI_COMMAND_IO;
+ if (r->flags & IORESOURCE_MEM)
+ cmd |= PCI_COMMAND_MEMORY;
+ }
+
+ if (dev->resource[PCI_ROM_RESOURCE].start)
+ cmd |= PCI_COMMAND_MEMORY;
+
+ if (cmd != old_cmd)
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+
+ return 0;
+}
+
+/*
+ * If we set up a device for bus mastering, we need to check the latency
+ * timer as certain crappy BIOSes forget to set it properly.
+ */
+unsigned int pcibios_max_latency = 255;
+
+void pcibios_set_master(struct pci_dev *dev)
+{
+ u8 lat;
+
+ pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
+
+ if (lat < 16)
+ lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
+ else if (lat > pcibios_max_latency)
+ lat = pcibios_max_latency;
+ else
+ return;
+
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
+}
+
+int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+ enum pci_mmap_state mmap_state, int write_combine)
+{
+ unsigned long prot;
+
+ /* Leave vm_pgoff as-is, the PCI space address is the physical
+ * address on this platform.
+ */
+ vma->vm_flags |= VM_LOCKED | VM_IO;
+
+ prot = pgprot_val(vma->vm_page_prot);
+ prot &= ~_PAGE_CACHE;
+ vma->vm_page_prot = __pgprot(prot);
+
+ /* Write-combine setting is ignored */
+ if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
+ vma->vm_end - vma->vm_start,
+ vma->vm_page_prot))
+ return -EAGAIN;
+
+ return 0;
+}
--- /dev/null
+/* ASB2305 Arch-specific PCI declarations
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ * Derived from: arch/i386/kernel/pci-i386.h: (c) 1999 Martin Mares <mj@ucw.cz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _PCI_ASB2305_H
+#define _PCI_ASB2305_H
+
+#undef DEBUG
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+#define PCI_PROBE_BIOS 1
+#define PCI_PROBE_CONF1 2
+#define PCI_PROBE_CONF2 4
+#define PCI_NO_SORT 0x100
+#define PCI_BIOS_SORT 0x200
+#define PCI_NO_CHECKS 0x400
+#define PCI_ASSIGN_ROMS 0x1000
+#define PCI_BIOS_IRQ_SCAN 0x2000
+
+extern unsigned int pci_probe;
+
+/* pci-asb2305.c */
+
+extern unsigned int pcibios_max_latency;
+
+extern void pcibios_resource_survey(void);
+extern int pcibios_enable_resources(struct pci_dev *dev, int mask);
+
+/* pci.c */
+
+extern int pcibios_last_bus;
+extern struct pci_bus *pci_root_bus;
+extern struct pci_ops *pci_root_ops;
+
+extern struct irq_routing_table *pcibios_get_irq_routing_table(void);
+extern int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
+
+/* pci-irq.c */
+
+struct irq_info {
+ u8 bus, devfn; /* Bus, device and function */
+ struct {
+ u8 link; /* IRQ line ID, chipset dependent,
+ * 0=not routed */
+ u16 bitmap; /* Available IRQs */
+ } __attribute__((packed)) irq[4];
+ u8 slot; /* Slot number, 0=onboard */
+ u8 rfu;
+} __attribute__((packed));
+
+struct irq_routing_table {
+ u32 signature; /* PIRQ_SIGNATURE should be here */
+ u16 version; /* PIRQ_VERSION */
+ u16 size; /* Table size in bytes */
+ u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
+ u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
+ u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
+ u32 miniport_data; /* Crap */
+ u8 rfu[11];
+ u8 checksum; /* Modulo 256 checksum must give zero */
+ struct irq_info slots[0];
+} __attribute__((packed));
+
+extern unsigned int pcibios_irq_mask;
+
+extern void pcibios_irq_init(void);
+extern void pcibios_fixup_irqs(void);
+extern void pcibios_enable_irq(struct pci_dev *dev);
+
+#endif /* PCI_ASB2305_H */
--- /dev/null
+/* ASB2305 PCI I/O mapping handler
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/pci.h>
+#include <linux/module.h>
+
+/*
+ * Create a virtual mapping cookie for a PCI BAR (memory or IO)
+ */
+void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
+{
+ unsigned long start = pci_resource_start(dev, bar);
+ unsigned long len = pci_resource_len(dev, bar);
+ unsigned long flags = pci_resource_flags(dev, bar);
+
+ if (!len || !start)
+ return NULL;
+
+ if ((flags & IORESOURCE_IO) || (flags & IORESOURCE_MEM))
+ return (void __iomem *) start;
+
+ return NULL;
+}
+EXPORT_SYMBOL(pci_iomap);
--- /dev/null
+/* PCI IRQ routing on the MN103E010 based ASB2305
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ *
+ * This is simple: All PCI interrupts route through the CPU's XIRQ1 pin [IRQ 35]
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <asm/io.h>
+#include <asm/smp.h>
+#include "pci-asb2305.h"
+
+void __init pcibios_irq_init(void)
+{
+}
+
+void __init pcibios_fixup_irqs(void)
+{
+ struct pci_dev *dev = NULL;
+ u8 line, pin;
+
+ while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+ pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+ if (pin) {
+ dev->irq = XIRQ1;
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
+ dev->irq);
+ }
+ pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &line);
+ }
+}
+
+void __init pcibios_penalize_isa_irq(int irq)
+{
+}
+
+void pcibios_enable_irq(struct pci_dev *dev)
+{
+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
+}
--- /dev/null
+/* ASB2305 PCI support
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ * Derived from arch/i386/kernel/pci-pc.c
+ * (c) 1999--2000 Martin Mares <mj@suse.cz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include "pci-asb2305.h"
+
+unsigned int pci_probe = 1;
+
+int pcibios_last_bus = -1;
+struct pci_bus *pci_root_bus;
+struct pci_ops *pci_root_ops;
+
+/*
+ * Functions for accessing PCI configuration space
+ */
+
+#define CONFIG_CMD(bus, devfn, where) \
+ (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
+
+#define MEM_PAGING_REG (*(volatile __u32 *) 0xBFFFFFF4)
+#define CONFIG_ADDRESS (*(volatile __u32 *) 0xBFFFFFF8)
+#define CONFIG_DATAL(X) (*(volatile __u32 *) 0xBFFFFFFC)
+#define CONFIG_DATAW(X) (*(volatile __u16 *) (0xBFFFFFFC + ((X) & 2)))
+#define CONFIG_DATAB(X) (*(volatile __u8 *) (0xBFFFFFFC + ((X) & 3)))
+
+#define BRIDGEREGB(X) (*(volatile __u8 *) (0xBE040000 + (X)))
+#define BRIDGEREGW(X) (*(volatile __u16 *) (0xBE040000 + (X)))
+#define BRIDGEREGL(X) (*(volatile __u32 *) (0xBE040000 + (X)))
+
+static inline int __query(const struct pci_bus *bus, unsigned int devfn)
+{
+#if 0
+ return bus->number == 0 && (devfn == PCI_DEVFN(0, 0));
+ return bus->number == 1;
+ return bus->number == 0 &&
+ (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(3, 0));
+#endif
+ return 1;
+}
+
+/*
+ * translate Linuxcentric addresses to PCI bus addresses
+ */
+void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
+ struct resource *res)
+{
+ if (res->flags & IORESOURCE_IO) {
+ region->start = (res->start & 0x00ffffff);
+ region->end = (res->end & 0x00ffffff);
+ }
+
+ if (res->flags & IORESOURCE_MEM) {
+ region->start = (res->start & 0x03ffffff) | MEM_PAGING_REG;
+ region->end = (res->end & 0x03ffffff) | MEM_PAGING_REG;
+ }
+
+#if 0
+ printk(KERN_DEBUG "RES->BUS: %lx-%lx => %lx-%lx\n",
+ res->start, res->end, region->start, region->end);
+#endif
+}
+EXPORT_SYMBOL(pcibios_resource_to_bus);
+
+/*
+ * translate PCI bus addresses to Linuxcentric addresses
+ */
+void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+ struct pci_bus_region *region)
+{
+ if (res->flags & IORESOURCE_IO) {
+ res->start = (region->start & 0x00ffffff) | 0xbe000000;
+ res->end = (region->end & 0x00ffffff) | 0xbe000000;
+ }
+
+ if (res->flags & IORESOURCE_MEM) {
+ res->start = (region->start & 0x03ffffff) | 0xb8000000;
+ res->end = (region->end & 0x03ffffff) | 0xb8000000;
+ }
+
+#if 0
+ printk(KERN_INFO "BUS->RES: %lx-%lx => %lx-%lx\n",
+ region->start, region->end, res->start, res->end);
+#endif
+}
+EXPORT_SYMBOL(pcibios_bus_to_resource);
+
+/*
+ *
+ */
+static int pci_ampci_read_config_byte(struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *_value)
+{
+ u32 rawval, value;
+
+ if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
+ value = BRIDGEREGB(where);
+ __pcbdebug("=> %02hx", &BRIDGEREGL(where), value);
+ } else {
+ CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
+ rawval = CONFIG_ADDRESS;
+ value = CONFIG_DATAB(where);
+ if (__query(bus, devfn))
+ __pcidebug("=> %02hx", bus, devfn, where, value);
+ }
+
+ *_value = value;
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_ampci_read_config_word(struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *_value)
+{
+ u32 rawval, value;
+
+ if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
+ value = BRIDGEREGW(where);
+ __pcbdebug("=> %04hx", &BRIDGEREGL(where), value);
+ } else {
+ CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
+ rawval = CONFIG_ADDRESS;
+ value = CONFIG_DATAW(where);
+ if (__query(bus, devfn))
+ __pcidebug("=> %04hx", bus, devfn, where, value);
+ }
+
+ *_value = value;
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_ampci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *_value)
+{
+ u32 rawval, value;
+
+ if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
+ value = BRIDGEREGL(where);
+ __pcbdebug("=> %08x", &BRIDGEREGL(where), value);
+ } else {
+ CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
+ rawval = CONFIG_ADDRESS;
+ value = CONFIG_DATAL(where);
+ if (__query(bus, devfn))
+ __pcidebug("=> %08x", bus, devfn, where, value);
+ }
+
+ *_value = value;
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_ampci_write_config_byte(struct pci_bus *bus, unsigned int devfn,
+ int where, u8 value)
+{
+ u32 rawval;
+
+ if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
+ __pcbdebug("<= %02x", &BRIDGEREGB(where), value);
+ BRIDGEREGB(where) = value;
+ } else {
+ if (bus->number == 0 &&
+ (devfn == PCI_DEVFN(2, 0) && devfn == PCI_DEVFN(3, 0))
+ )
+ __pcidebug("<= %02x", bus, devfn, where, value);
+ CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
+ rawval = CONFIG_ADDRESS;
+ CONFIG_DATAB(where) = value;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_ampci_write_config_word(struct pci_bus *bus, unsigned int devfn,
+ int where, u16 value)
+{
+ u32 rawval;
+
+ if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
+ __pcbdebug("<= %04hx", &BRIDGEREGW(where), value);
+ BRIDGEREGW(where) = value;
+ } else {
+ if (__query(bus, devfn))
+ __pcidebug("<= %04hx", bus, devfn, where, value);
+ CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
+ rawval = CONFIG_ADDRESS;
+ CONFIG_DATAW(where) = value;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_ampci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
+ int where, u32 value)
+{
+ u32 rawval;
+
+ if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
+ __pcbdebug("<= %08x", &BRIDGEREGL(where), value);
+ BRIDGEREGL(where) = value;
+ } else {
+ if (__query(bus, devfn))
+ __pcidebug("<= %08x", bus, devfn, where, value);
+ CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
+ rawval = CONFIG_ADDRESS;
+ CONFIG_DATAL(where) = value;
+ }
+ return PCIBIOS_SUCCESSFUL;
+}
+
+static int pci_ampci_read_config(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 *val)
+{
+ switch (size) {
+ case 1:
+ return pci_ampci_read_config_byte(bus, devfn, where, val);
+ case 2:
+ return pci_ampci_read_config_word(bus, devfn, where, val);
+ case 4:
+ return pci_ampci_read_config_dword(bus, devfn, where, val);
+ default:
+ BUG();
+ return -EOPNOTSUPP;
+ }
+}
+
+static int pci_ampci_write_config(struct pci_bus *bus, unsigned int devfn,
+ int where, int size, u32 val)
+{
+ switch (size) {
+ case 1:
+ return pci_ampci_write_config_byte(bus, devfn, where, val);
+ case 2:
+ return pci_ampci_write_config_word(bus, devfn, where, val);
+ case 4:
+ return pci_ampci_write_config_dword(bus, devfn, where, val);
+ default:
+ BUG();
+ return -EOPNOTSUPP;
+ }
+}
+
+static struct pci_ops pci_direct_ampci = {
+ pci_ampci_read_config,
+ pci_ampci_write_config,
+};
+
+/*
+ * Before we decide to use direct hardware access mechanisms, we try to do some
+ * trivial checks to ensure it at least _seems_ to be working -- we just test
+ * whether bus 00 contains a host bridge (this is similar to checking
+ * techniques used in XFree86, but ours should be more reliable since we
+ * attempt to make use of direct access hints provided by the PCI BIOS).
+ *
+ * This should be close to trivial, but it isn't, because there are buggy
+ * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
+ */
+static int __init pci_sanity_check(struct pci_ops *o)
+{
+ struct pci_bus bus; /* Fake bus and device */
+ u32 x;
+
+ bus.number = 0;
+
+ if ((!o->read(&bus, 0, PCI_CLASS_DEVICE, 2, &x) &&
+ (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)) ||
+ (!o->read(&bus, 0, PCI_VENDOR_ID, 2, &x) &&
+ (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)))
+ return 1;
+
+ printk(KERN_ERROR "PCI: Sanity check failed\n");
+ return 0;
+}
+
+static int __init pci_check_direct(void)
+{
+ unsigned long flags;
+
+ local_irq_save(flags);
+
+ /*
+ * Check if access works.
+ */
+ if (pci_sanity_check(&pci_direct_ampci)) {
+ local_irq_restore(flags);
+ printk(KERN_INFO "PCI: Using configuration ampci\n");
+ request_mem_region(0xBE040000, 256, "AMPCI bridge");
+ request_mem_region(0xBFFFFFF4, 12, "PCI ampci");
+ return 0;
+ }
+
+ local_irq_restore(flags);
+ return -ENODEV;
+}
+
+static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
+{
+ unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
+ struct resource *devr = &dev->resource[idx];
+
+ if (dev->bus) {
+ for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
+ struct resource *busr = dev->bus->resource[i];
+
+ if (!busr || (busr->flags ^ devr->flags) & type_mask)
+ continue;
+
+ if (devr->start &&
+ devr->start >= busr->start &&
+ devr->end <= busr->end)
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
+{
+ struct pci_bus_region region;
+ int i;
+ int limit;
+
+ if (dev->bus->number != 0)
+ return;
+
+ limit = (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) ?
+ PCI_BRIDGE_RESOURCES : PCI_NUM_RESOURCES;
+
+ for (i = 0; i < limit; i++) {
+ if (!dev->resource[i].flags)
+ continue;
+
+ region.start = dev->resource[i].start;
+ region.end = dev->resource[i].end;
+ pcibios_bus_to_resource(dev, &dev->resource[i], ®ion);
+ if (is_valid_resource(dev, i))
+ pci_claim_resource(dev, i);
+ }
+}
+
+/*
+ * Called after each bus is probed, but before its children
+ * are examined.
+ */
+void __devinit pcibios_fixup_bus(struct pci_bus *bus)
+{
+ struct pci_dev *dev;
+
+ if (bus->self) {
+ pci_read_bridge_bases(bus);
+ pcibios_fixup_device_resources(bus->self);
+ }
+
+ list_for_each_entry(dev, &bus->devices, bus_list)
+ pcibios_fixup_device_resources(dev);
+}
+
+/*
+ * Initialization. Try all known PCI access methods. Note that we support
+ * using both PCI BIOS and direct access: in such cases, we use I/O ports
+ * to access config space, but we still keep BIOS order of cards to be
+ * compatible with 2.0.X. This should go away some day.
+ */
+static int __init pcibios_init(void)
+{
+ ioport_resource.start = 0xA0000000;
+ ioport_resource.end = 0xDFFFFFFF;
+ iomem_resource.start = 0xA0000000;
+ iomem_resource.end = 0xDFFFFFFF;
+
+ if (!pci_probe)
+ return 0;
+
+ if (pci_check_direct() < 0) {
+ printk(KERN_WARNING "PCI: No PCI bus detected\n");
+ return 0;
+ }
+
+ printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n",
+ MEM_PAGING_REG);
+
+ {
+#if 0
+ static struct pci_bus am33_root_bus = {
+ .children = LIST_HEAD_INIT(am33_root_bus.children),
+ .devices = LIST_HEAD_INIT(am33_root_bus.devices),
+ .number = 0,
+ .secondary = 0,
+ .resource = { &ioport_resource, &iomem_resource },
+ };
+
+ am33_root_bus.ops = pci_root_ops;
+ list_add_tail(&am33_root_bus.node, &pci_root_buses);
+
+ am33_root_bus.subordinate = pci_do_scan_bus(0);
+
+ pci_root_bus = &am33_root_bus;
+#else
+ pci_root_bus = pci_scan_bus(0, &pci_direct_ampci, NULL);
+#endif
+ }
+
+ pcibios_irq_init();
+ pcibios_fixup_irqs();
+#if 0
+ pcibios_resource_survey();
+#endif
+ return 0;
+}
+
+arch_initcall(pcibios_init);
+
+char *__init pcibios_setup(char *str)
+{
+ if (!strcmp(str, "off")) {
+ pci_probe = 0;
+ return NULL;
+
+ } else if (!strncmp(str, "lastbus=", 8)) {
+ pcibios_last_bus = simple_strtol(str+8, NULL, 0);
+ return NULL;
+ }
+
+ return str;
+}
+
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+ int err;
+
+ err = pcibios_enable_resources(dev, mask);
+ if (err == 0)
+ pcibios_enable_irq(dev);
+ return err;
+}
+
+/*
+ * disable the ethernet chipset
+ */
+static void __init unit_disable_pcnet(struct pci_bus *bus, struct pci_ops *o)
+{
+ u32 x;
+
+ bus->number = 0;
+
+ o->read (bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, &x);
+ x |= PCI_COMMAND_MASTER |
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+ PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
+ o->write(bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, x);
+ o->read (bus, PCI_DEVFN(2, 0), PCI_COMMAND, 2, &x);
+ o->write(bus, PCI_DEVFN(2, 0), PCI_BASE_ADDRESS_0, 4, 0x00030001);
+ o->read (bus, PCI_DEVFN(2, 0), PCI_BASE_ADDRESS_0, 4, &x);
+
+#define RDP (*(volatile u32 *) 0xBE030010)
+#define RAP (*(volatile u32 *) 0xBE030014)
+#define __set_RAP(X) do { RAP = (X); x = RAP; } while (0)
+#define __set_RDP(X) do { RDP = (X); x = RDP; } while (0)
+#define __get_RDP() ({ RDP & 0xffff; })
+
+ __set_RAP(0);
+ __set_RDP(0x0004); /* CSR0 = STOP */
+
+ __set_RAP(88); /* check CSR88 indicates an Am79C973 */
+ BUG_ON(__get_RDP() != 0x5003);
+
+ for (x = 0; x < 100; x++)
+ asm volatile("nop");
+
+ __set_RDP(0x0004); /* CSR0 = STOP */
+}
+
+/*
+ * initialise the unit hardware
+ */
+asmlinkage void __init unit_pci_init(void)
+{
+ struct pci_bus bus; /* Fake bus and device */
+ struct pci_ops *o = &pci_direct_ampci;
+ u32 x;
+
+ set_intr_level(XIRQ1, GxICR_LEVEL_3);
+
+ memset(&bus, 0, sizeof(bus));
+
+ MEM_PAGING_REG = 0xE8000000;
+
+ /* we need to set up the bridge _now_ or we won't be able to access the
+ * PCI config registers
+ */
+ BRIDGEREGW(PCI_COMMAND) |=
+ PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
+ PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER;
+ BRIDGEREGW(PCI_STATUS) = 0xF800;
+ BRIDGEREGB(PCI_LATENCY_TIMER) = 0x10;
+ BRIDGEREGL(PCI_BASE_ADDRESS_0) = 0x80000000;
+ BRIDGEREGB(PCI_INTERRUPT_LINE) = 1;
+ BRIDGEREGL(0x48) = 0x98000000; /* AMPCI base addr */
+ BRIDGEREGB(0x41) = 0x00; /* secondary bus
+ * number */
+ BRIDGEREGB(0x42) = 0x01; /* subordinate bus
+ * number */
+ BRIDGEREGB(0x44) = 0x01;
+ BRIDGEREGL(0x50) = 0x00000001;
+ BRIDGEREGL(0x58) = 0x00001002;
+ BRIDGEREGL(0x5C) = 0x00000011;
+
+ /* we also need to set up the PCI-PCI bridge */
+ bus.number = 0;
+
+ /* IO: 0x00000000-0x00020000 */
+ o->read (&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, &x);
+ x |= PCI_COMMAND_MASTER |
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
+ PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
+ o->write(&bus, PCI_DEVFN(3, 0), PCI_COMMAND, 2, x);
+
+ o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x);
+ o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x);
+ o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x);
+ o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x);
+
+ o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, 0x01);
+ o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE, 1, &x);
+ o->write(&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, 0x00020000);
+ o->read (&bus, PCI_DEVFN(3, 0), PCI_IO_BASE_UPPER16, 4, &x);
+ o->write(&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, 0xEBB0EA00);
+ o->read (&bus, PCI_DEVFN(3, 0), PCI_MEMORY_BASE, 4, &x);
+ o->write(&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, 0xE9F0E800);
+ o->read (&bus, PCI_DEVFN(3, 0), PCI_PREF_MEMORY_BASE, 4, &x);
+
+ unit_disable_pcnet(&bus, o);
+}
--- /dev/null
+/* ASB2305 Initialisation
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/param.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <asm/io.h>
+#include <asm/setup.h>
+#include <asm/processor.h>
+#include <asm/cpu/intctl-regs.h>
+#include <asm/cpu/rtc-regs.h>
+#include <asm/cpu/serial-regs.h>
+#include <asm/unit/serial.h>
+
+/*
+ * initialise some of the unit hardware before gdbstub is set up
+ */
+asmlinkage void __init unit_init(void)
+{
+#ifndef CONFIG_GDBSTUB_ON_TTYSx
+ /* set the 16550 interrupt line to level 3 if not being used for GDB */
+ set_intr_level(XIRQ0, GxICR_LEVEL_3);
+#endif
+}
+
+/*
+ * initialise the rest of the unit hardware after gdbstub is ready
+ */
+void __init unit_setup(void)
+{
+#ifdef CONFIG_PCI
+ unit_pci_init();
+#endif
+}
+
+/*
+ * initialise the external interrupts used by a unit of this type
+ */
+void __init unit_init_IRQ(void)
+{
+ unsigned int extnum;
+
+ for (extnum = 0; extnum < NR_XIRQS; extnum++) {
+ switch (GET_XIRQ_TRIGGER(extnum)) {
+ case XIRQ_TRIGGER_HILEVEL:
+ case XIRQ_TRIGGER_LOWLEVEL:
+ set_irq_handler(XIRQ2IRQ(extnum), handle_level_irq);
+ break;
+ default:
+ break;
+ }
+ }
+}
bool
default y
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
# unless you want to implement ACPI on PA-RISC ... ;-)
config PM
bool
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = c_start,
.next = c_next,
.stop = c_stop,
config ARCH_ENABLE_MEMORY_HOTPLUG
def_bool y
+config ARCH_HAS_WALK_MEMORY
+ def_bool y
+
+config ARCH_ENABLE_MEMORY_HOTREMOVE
+ def_bool y
+
config KEXEC
bool "kexec system call (EXPERIMENTAL)"
depends on (PPC_PRPMC2800 || PPC_MULTIPLATFORM) && EXPERIMENTAL
return __add_pages(zone, start_pfn, nr_pages);
}
+#ifdef CONFIG_MEMORY_HOTREMOVE
+int remove_memory(u64 start, u64 size)
+{
+ unsigned long start_pfn, end_pfn;
+ int ret;
+
+ start_pfn = start >> PAGE_SHIFT;
+ end_pfn = start_pfn + (size >> PAGE_SHIFT);
+ ret = offline_pages(start_pfn, end_pfn, 120 * HZ);
+ if (ret)
+ goto out;
+ /* Arch-specific calls go here - next patch */
+out:
+ return ret;
+}
+#endif /* CONFIG_MEMORY_HOTREMOVE */
+
+/*
+ * walk_memory_resource() needs to make sure there is no holes in a given
+ * memory range. On PPC64, since this range comes from /sysfs, the range
+ * is guaranteed to be valid, non-overlapping and can not contain any
+ * holes. By the time we get here (memory add or remove), /proc/device-tree
+ * is updated and correct. Only reason we need to check against device-tree
+ * would be if we allow user-land to specify a memory range through a
+ * system call/ioctl etc. instead of doing offline/online through /sysfs.
+ */
+int
+walk_memory_resource(unsigned long start_pfn, unsigned long nr_pages, void *arg,
+ int (*func)(unsigned long, unsigned long, void *))
+{
+ return (*func)(start_pfn, nr_pages, arg);
+}
+
#endif /* CONFIG_MEMORY_HOTPLUG */
void show_mem(void)
return pte;
}
-struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
struct page *ptepage;
#ifdef CONFIG_HIGHPTE
- gfp_t flags = GFP_KERNEL | __GFP_HIGHMEM | __GFP_REPEAT;
+ gfp_t flags = GFP_KERNEL | __GFP_HIGHMEM | __GFP_REPEAT | __GFP_ZERO;
#else
- gfp_t flags = GFP_KERNEL | __GFP_REPEAT;
+ gfp_t flags = GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO;
#endif
ptepage = alloc_pages(flags, 0);
- if (ptepage)
- clear_highpage(ptepage);
+ if (!ptepage)
+ return NULL;
+ pgtable_page_ctor(ptepage);
return ptepage;
}
free_page((unsigned long)pte);
}
-void pte_free(struct mm_struct *mm, struct page *ptepage)
+void pte_free(struct mm_struct *mm, pgtable_t ptepage)
{
#ifdef CONFIG_SMP
hash_page_sync();
#endif
+ pgtable_page_dtor(ptepage);
__free_page(ptepage);
}
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/notifier.h>
+#include <linux/of.h>
#include <linux/of_platform.h>
#include <asm/prom.h>
static u64 cell_iommu_get_fixed_address(struct device *dev)
{
u64 cpu_addr, size, best_size, pci_addr = OF_BAD_ADDR;
- struct device_node *tmp, *np;
+ struct device_node *np;
const u32 *ranges = NULL;
int i, len, best;
- np = dev->archdata.of_node;
- of_node_get(np);
- ranges = of_get_property(np, "dma-ranges", &len);
- while (!ranges && np) {
- tmp = of_get_parent(np);
- of_node_put(np);
- np = tmp;
+ np = of_node_get(dev->archdata.of_node);
+ while (np) {
ranges = of_get_property(np, "dma-ranges", &len);
+ if (ranges)
+ break;
+ np = of_get_next_parent(np);
}
if (!ranges) {
if (!dev->dma_mask || !dma_supported(dev, dma_mask))
return -EIO;
- if (dma_mask == DMA_BIT_MASK(64)) {
- if (cell_iommu_get_fixed_address(dev) == OF_BAD_ADDR)
- dev_dbg(dev, "iommu: 64-bit OK, but bad addr\n");
- else {
- dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n");
- set_dma_ops(dev, &dma_iommu_fixed_ops);
- cell_dma_dev_setup(dev);
- }
+ if (dma_mask == DMA_BIT_MASK(64) &&
+ cell_iommu_get_fixed_address(dev) != OF_BAD_ADDR)
+ {
+ dev_dbg(dev, "iommu: 64-bit OK, using fixed ops\n");
+ set_dma_ops(dev, &dma_iommu_fixed_ops);
} else {
dev_dbg(dev, "iommu: not 64-bit, using default ops\n");
set_dma_ops(dev, get_pci_dma_ops());
}
+ cell_dma_dev_setup(dev);
+
*dev->dma_mask = dma_mask;
return 0;
return -1;
}
+ /* We must have dma-ranges properties for fixed mapping to work */
+ for (np = NULL; (np = of_find_all_nodes(np));) {
+ if (of_find_property(np, "dma-ranges", NULL))
+ break;
+ }
+ of_node_put(np);
+
+ if (!np) {
+ pr_debug("iommu: no dma-ranges found, no fixed mapping\n");
+ return -1;
+ }
+
/* The default setup is to have the fixed mapping sit after the
* dynamic region, so find the top of the largest IOMMU window
* on any axon, then add the size of RAM and that's our max value.
dsize = htab_size_bytes;
}
- pr_debug("iommu: setting up %d, dynamic window %lx-%lx " \
- "fixed window %lx-%lx\n", iommu->nid, dbase,
+ printk(KERN_DEBUG "iommu: node %d, dynamic window 0x%lx-0x%lx "
+ "fixed window 0x%lx-0x%lx\n", iommu->nid, dbase,
dbase + dsize, fbase, fbase + fsize);
cell_iommu_setup_page_tables(iommu, dbase, dsize, fbase, fsize);
dma_iommu_ops.set_dma_mask = dma_set_mask_and_switch;
set_pci_dma_ops(&dma_iommu_ops);
- printk(KERN_DEBUG "IOMMU fixed mapping established.\n");
-
return 0;
}
spin_lock(&ctx->csa.register_lock);
ctx->csa.prob.spu_runcntl_RW = val;
if (val & SPU_RUNCNTL_RUNNABLE) {
+ ctx->csa.prob.spu_status_R &=
+ ~SPU_STATUS_STOPPED_BY_STOP &
+ ~SPU_STATUS_STOPPED_BY_HALT &
+ ~SPU_STATUS_SINGLE_STEP &
+ ~SPU_STATUS_INVALID_INSTR &
+ ~SPU_STATUS_INVALID_CH;
ctx->csa.prob.spu_status_R |= SPU_STATUS_RUNNING;
} else {
ctx->csa.prob.spu_status_R &= ~SPU_STATUS_RUNNING;
u64 ea, dsisr, access;
unsigned long flags;
unsigned flt = 0;
- int ret, ret2;
+ int ret;
/*
* dar and dsisr get passed from the registers
ret = spu_handle_mm_fault(current->mm, ea, dsisr, &flt);
/*
- * If spu_acquire fails due to a pending signal we just want to return
- * EINTR to userspace even if that means missing the dma restart or
- * updating the page fault statistics.
+ * This is nasty: we need the state_mutex for all the bookkeeping even
+ * if the syscall was interrupted by a signal. ewww.
*/
- ret2 = spu_acquire(ctx);
- if (ret2)
- goto out;
+ mutex_lock(&ctx->state_mutex);
/*
* Clear dsisr under ctxt lock after handling the fault, so that
} else
spufs_handle_event(ctx, ea, SPE_EVENT_SPE_DATA_STORAGE);
- out:
spuctx_switch_state(ctx, SPU_UTIL_SYSTEM);
return ret;
}
{
struct spu_context *ctx = vma->vm_file->private_data;
unsigned long area, offset = address - vma->vm_start;
+ int ret = 0;
spu_context_nospu_trace(spufs_ps_nopfn__enter, ctx);
if (ctx->state == SPU_STATE_SAVED) {
up_read(¤t->mm->mmap_sem);
spu_context_nospu_trace(spufs_ps_nopfn__sleep, ctx);
- spufs_wait(ctx->run_wq, ctx->state == SPU_STATE_RUNNABLE);
+ ret = spufs_wait(ctx->run_wq, ctx->state == SPU_STATE_RUNNABLE);
spu_context_trace(spufs_ps_nopfn__wake, ctx, ctx->spu);
down_read(¤t->mm->mmap_sem);
} else {
spu_context_trace(spufs_ps_nopfn__insert, ctx, ctx->spu);
}
- spu_release(ctx);
+ if (!ret)
+ spu_release(ctx);
return NOPFN_REFAULT;
}
if (!i->i_openers++)
ctx->cntl = inode->i_mapping;
mutex_unlock(&ctx->mapping_lock);
- return spufs_attr_open(inode, file, spufs_cntl_get,
+ return simple_attr_open(inode, file, spufs_cntl_get,
spufs_cntl_set, "0x%08lx");
}
struct spufs_inode_info *i = SPUFS_I(inode);
struct spu_context *ctx = i->i_ctx;
- spufs_attr_release(inode, file);
+ simple_attr_release(inode, file);
mutex_lock(&ctx->mapping_lock);
if (!--i->i_openers)
static const struct file_operations spufs_cntl_fops = {
.open = spufs_cntl_open,
.release = spufs_cntl_release,
- .read = spufs_attr_read,
- .write = spufs_attr_write,
+ .read = simple_attr_read,
+ .write = simple_attr_write,
.mmap = spufs_cntl_mmap,
};
count = spu_acquire(ctx);
if (count)
- return count;
+ goto out;
/* wait only for the first element */
count = 0;
if (file->f_flags & O_NONBLOCK) {
- if (!spu_ibox_read(ctx, &ibox_data))
+ if (!spu_ibox_read(ctx, &ibox_data)) {
count = -EAGAIN;
+ goto out_unlock;
+ }
} else {
count = spufs_wait(ctx->ibox_wq, spu_ibox_read(ctx, &ibox_data));
+ if (count)
+ goto out;
}
- if (count)
- goto out;
/* if we can't write at all, return -EFAULT */
count = __put_user(ibox_data, udata);
if (count)
- goto out;
+ goto out_unlock;
for (count = 4, udata++; (count + 4) <= len; count += 4, udata++) {
int ret;
break;
}
-out:
+out_unlock:
spu_release(ctx);
-
+out:
return count;
}
count = spu_acquire(ctx);
if (count)
- return count;
+ goto out;
/*
* make sure we can at least write one element, by waiting
*/
count = 0;
if (file->f_flags & O_NONBLOCK) {
- if (!spu_wbox_write(ctx, wbox_data))
+ if (!spu_wbox_write(ctx, wbox_data)) {
count = -EAGAIN;
+ goto out_unlock;
+ }
} else {
count = spufs_wait(ctx->wbox_wq, spu_wbox_write(ctx, wbox_data));
+ if (count)
+ goto out;
}
- if (count)
- goto out;
/* write as much as possible */
for (count = 4, udata++; (count + 4) <= len; count += 4, udata++) {
break;
}
-out:
+out_unlock:
spu_release(ctx);
+out:
return count;
}
} else {
ret = spufs_wait(ctx->mfc_wq,
spufs_read_mfc_tagstatus(ctx, &status));
+ if (ret)
+ goto out;
}
spu_release(ctx);
- if (ret)
- goto out;
-
ret = 4;
if (copy_to_user(buffer, &status, 4))
ret = -EFAULT;
int status;
ret = spufs_wait(ctx->mfc_wq,
spu_send_mfc_command(ctx, cmd, &status));
+ if (ret)
+ goto out;
if (status)
ret = status;
}
ret = spu_acquire(ctx);
if (ret)
- return ret;
+ goto out;
#if 0
/* this currently hangs */
ret = spufs_wait(ctx->mfc_wq,
goto out;
ret = spufs_wait(ctx->mfc_wq,
ctx->ops->read_mfc_tagstatus(ctx) == ctx->tagwait);
-out:
+ if (ret)
+ goto out;
#else
ret = 0;
#endif
spu_release(ctx);
-
+out:
return ret;
}
.statfs = simple_statfs,
.delete_inode = spufs_delete_inode,
.drop_inode = generic_delete_inode,
+ .show_options = generic_show_options,
};
+ save_mount_options(sb, data);
+
sb->s_maxbytes = MAX_LFS_FILESIZE;
sb->s_blocksize = PAGE_CACHE_SIZE;
sb->s_blocksize_bits = PAGE_CACHE_SHIFT;
stopped = SPU_STATUS_INVALID_INSTR | SPU_STATUS_SINGLE_STEP |
SPU_STATUS_STOPPED_BY_HALT | SPU_STATUS_STOPPED_BY_STOP;
- if (*stat & stopped)
+ if (!(*stat & SPU_STATUS_RUNNING) && (*stat & stopped))
return 1;
dsisr = ctx->csa.dsisr;
do {
ret = spufs_wait(ctx->stop_wq, spu_stopped(ctx, &status));
- if (unlikely(ret))
+ if (unlikely(ret)) {
+ /*
+ * This is nasty: we need the state_mutex for all the
+ * bookkeeping even if the syscall was interrupted by
+ * a signal. ewww.
+ */
+ mutex_lock(&ctx->state_mutex);
break;
+ }
spu = ctx->spu;
if (unlikely(test_and_clear_bit(SPU_SCHED_NOTIFY_ACTIVE,
&ctx->sched_flags))) {
SPU_STATUS_STOPPED_BY_HALT |
SPU_STATUS_SINGLE_STEP)));
- if ((status & SPU_STATUS_STOPPED_BY_STOP) &&
- (((status >> SPU_STOP_STATUS_SHIFT) & 0x3f00) == 0x2100) &&
- (ctx->state == SPU_STATE_RUNNABLE))
- ctx->stats.libassist++;
-
-
spu_disable_spu(ctx);
ret = spu_run_fini(ctx, npc, &status);
spu_yield(ctx);
+ if ((status & SPU_STATUS_STOPPED_BY_STOP) &&
+ (((status >> SPU_STOP_STATUS_SHIFT) & 0x3f00) == 0x2100))
+ ctx->stats.libassist++;
+
if ((ret == 0) ||
((ret == -ERESTARTSYS) &&
((status & SPU_STATUS_STOPPED_BY_HALT) ||
* Same as wait_event_interruptible(), except that here
* we need to call spu_release(ctx) before sleeping, and
* then spu_acquire(ctx) when awoken.
+ *
+ * Returns with state_mutex re-acquired when successfull or
+ * with -ERESTARTSYS and the state_mutex dropped when interrupted.
*/
#define spufs_wait(wq, condition) \
prepare_to_wait(&(wq), &__wait, TASK_INTERRUPTIBLE); \
if (condition) \
break; \
+ spu_release(ctx); \
if (signal_pending(current)) { \
__ret = -ERESTARTSYS; \
break; \
} \
- spu_release(ctx); \
schedule(); \
__ret = spu_acquire(ctx); \
if (__ret) \
/* Locate core99 Uni-N */
uninorth_node = of_find_node_by_name(NULL, "uni-n");
+ uninorth_maj = 1;
+
/* Locate G5 u3 */
if (uninorth_node == NULL) {
uninorth_node = of_find_node_by_name(NULL, "u3");
uninorth_node = of_find_node_by_name(NULL, "u4");
uninorth_maj = 4;
}
- if (uninorth_node == NULL)
+ if (uninorth_node == NULL) {
+ uninorth_maj = 0;
return;
+ }
addrp = of_get_property(uninorth_node, "reg", NULL);
if (addrp == NULL)
pmac_agp_resume(pmac_agp_bridge);
}
EXPORT_SYMBOL(pmac_resume_agp_for_card);
+
+int pmac_get_uninorth_variant(void)
+{
+ return uninorth_maj;
+}
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start =c_start,
.next = c_next,
.stop = c_stop,
return pte;
}
-struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
struct page *ptepage;
#endif
ptepage = alloc_pages(flags, 0);
- if (ptepage)
+ if (ptepage) {
clear_highpage(ptepage);
+ pgtable_page_ctor(ptepage);
+ }
return ptepage;
}
free_page((unsigned long)pte);
}
-void pte_free(struct mm_struct *mm, struct page *ptepage)
+void pte_free(struct mm_struct *mm, pgtable_t ptepage)
{
#ifdef CONFIG_SMP
hash_page_sync();
#endif
+ pgtable_page_dtor(ptepage);
__free_page(ptepage);
}
#include <linux/smp.h>
#include <linux/init.h>
#include <linux/interrupt.h>
+#include <linux/seq_file.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/kdebug.h>
}
/* This is called from fs/proc/array.c */
-char *task_show_regs(struct task_struct *task, char *buffer)
+void task_show_regs(struct seq_file *m, struct task_struct *task)
{
struct pt_regs *regs;
regs = task_pt_regs(task);
- buffer += sprintf(buffer, "task: %p, ksp: %p\n",
+ seq_printf(m, "task: %p, ksp: %p\n",
task, (void *)task->thread.ksp);
- buffer += sprintf(buffer, "User PSW : %p %p\n",
+ seq_printf(m, "User PSW : %p %p\n",
(void *) regs->psw.mask, (void *)regs->psw.addr);
- buffer += sprintf(buffer, "User GPRS: " FOURLONG,
+ seq_printf(m, "User GPRS: " FOURLONG,
regs->gprs[0], regs->gprs[1],
regs->gprs[2], regs->gprs[3]);
- buffer += sprintf(buffer, " " FOURLONG,
+ seq_printf(m, " " FOURLONG,
regs->gprs[4], regs->gprs[5],
regs->gprs[6], regs->gprs[7]);
- buffer += sprintf(buffer, " " FOURLONG,
+ seq_printf(m, " " FOURLONG,
regs->gprs[8], regs->gprs[9],
regs->gprs[10], regs->gprs[11]);
- buffer += sprintf(buffer, " " FOURLONG,
+ seq_printf(m, " " FOURLONG,
regs->gprs[12], regs->gprs[13],
regs->gprs[14], regs->gprs[15]);
- buffer += sprintf(buffer, "User ACRS: %08x %08x %08x %08x\n",
+ seq_printf(m, "User ACRS: %08x %08x %08x %08x\n",
task->thread.acrs[0], task->thread.acrs[1],
task->thread.acrs[2], task->thread.acrs[3]);
- buffer += sprintf(buffer, " %08x %08x %08x %08x\n",
+ seq_printf(m, " %08x %08x %08x %08x\n",
task->thread.acrs[4], task->thread.acrs[5],
task->thread.acrs[6], task->thread.acrs[7]);
- buffer += sprintf(buffer, " %08x %08x %08x %08x\n",
+ seq_printf(m, " %08x %08x %08x %08x\n",
task->thread.acrs[8], task->thread.acrs[9],
task->thread.acrs[10], task->thread.acrs[11]);
- buffer += sprintf(buffer, " %08x %08x %08x %08x\n",
+ seq_printf(m, " %08x %08x %08x %08x\n",
task->thread.acrs[12], task->thread.acrs[13],
task->thread.acrs[14], task->thread.acrs[15]);
- return buffer;
}
static DEFINE_SPINLOCK(die_lock);
clear_table(table, _PAGE_TYPE_EMPTY, PAGE_SIZE);
page->index = (addr_t) table;
}
+ pgtable_page_ctor(page);
table = (unsigned long *) page_to_phys(page);
clear_table(table, _PAGE_TYPE_EMPTY, PAGE_SIZE);
return table;
{
unsigned long *shadow = get_shadow_pte(table);
+ pgtable_page_dtor(virt_to_page(table));
if (shadow)
free_page((unsigned long) shadow);
free_page((unsigned long) table);
config ARCH_NO_VIRT_TO_BUS
def_bool y
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
source "init/Kconfig"
menu "System type"
ssize_t (*store)(const char *buf, size_t count);
};
-#define to_sq_sysfs_attr(attr) container_of(attr, struct sq_sysfs_attr, attr)
+#define to_sq_sysfs_attr(a) container_of(a, struct sq_sysfs_attr, attr)
static ssize_t sq_sysfs_show(struct kobject *kobj, struct attribute *attr,
char *buf)
config OF
def_bool y
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
+config HZ
+ int
+ default 100
+
source "init/Kconfig"
menu "General machine setup"
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/smp.h>
#include <linux/reboot.h>
#include <linux/delay.h>
return 0;
}
-/*
- * fill in the user structure for a core dump..
- */
-void dump_thread(struct pt_regs * regs, struct user * dump)
-{
- unsigned long first_stack_page;
-
- dump->magic = SUNOS_CORE_MAGIC;
- dump->len = sizeof(struct user);
- dump->regs.psr = regs->psr;
- dump->regs.pc = regs->pc;
- dump->regs.npc = regs->npc;
- dump->regs.y = regs->y;
- /* fuck me plenty */
- memcpy(&dump->regs.regs[0], ®s->u_regs[1], (sizeof(unsigned long) * 15));
- dump->uexec = current->thread.core_exec;
- dump->u_tsize = (((unsigned long) current->mm->end_code) -
- ((unsigned long) current->mm->start_code)) & ~(PAGE_SIZE - 1);
- dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1)));
- dump->u_dsize -= dump->u_tsize;
- dump->u_dsize &= ~(PAGE_SIZE - 1);
- first_stack_page = (regs->u_regs[UREG_FP] & ~(PAGE_SIZE - 1));
- dump->u_ssize = (TASK_SIZE - first_stack_page) & ~(PAGE_SIZE - 1);
- memcpy(&dump->fpu.fpstatus.fregs.regs[0], ¤t->thread.float_regs[0], (sizeof(unsigned long) * 32));
- dump->fpu.fpstatus.fsr = current->thread.fsr;
- dump->fpu.fpstatus.flags = dump->fpu.fpstatus.extra = 0;
- dump->fpu.fpstatus.fpq_count = current->thread.fpqdepth;
- memcpy(&dump->fpu.fpstatus.fpq[0], ¤t->thread.fpqueue[0],
- ((sizeof(unsigned long) * 2) * 16));
- dump->sigcode = 0;
-}
-
/*
* fill in the fpu structure for a core dump.
*/
#include <linux/initrd.h>
#include <asm/smp.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/screen_info.h>
#include <linux/delay.h>
#include <linux/fs.h>
#ifdef CONFIG_PCI
#include <asm/ebus.h>
#endif
-#include <asm/a.out.h>
#include <asm/io-unit.h>
#include <asm/bug.h>
EXPORT_SYMBOL(svr4_setcontext);
EXPORT_SYMBOL(svr4_getcontext);
-EXPORT_SYMBOL(dump_thread);
-
/* prom symbols */
EXPORT_SYMBOL(idprom);
EXPORT_SYMBOL(prom_root_node);
#include <asm/system.h>
#include <asm/page.h>
#include <asm/pgtable.h>
-#include <asm/a.out.h>
#include <asm/mmu_context.h>
#include <asm/oplib.h>
#include <asm/sbus.h>
#include <asm/asi.h>
#include <asm/msi.h>
-#include <asm/a.out.h>
#include <asm/mmu_context.h>
#include <asm/io-unit.h>
#include <asm/cacheflush.h>
return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
}
-static struct page *
+static pgtable_t
srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
unsigned long pte;
+ struct page *page;
if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
return NULL;
- return pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
+ page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
+ pgtable_page_ctor(page);
+ return page;
}
static void srmmu_free_pte_fast(pte_t *pte)
srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
}
-static void srmmu_pte_free(struct page *pte)
+static void srmmu_pte_free(pgtable_t pte)
{
unsigned long p;
+ pgtable_page_dtor(pte);
p = (unsigned long)page_address(pte); /* Cached address (for test) */
if (p == 0)
BUG();
return pte;
}
-static struct page *sun4c_pte_alloc_one(struct mm_struct *mm, unsigned long address)
+static pgtable_t sun4c_pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
- pte_t *pte = sun4c_pte_alloc_one_kernel(mm, address);
+ pte_t *pte;
+ struct page *page;
+
+ pte = sun4c_pte_alloc_one_kernel(mm, address);
if (pte == NULL)
return NULL;
- return virt_to_page(pte);
+ page = virt_to_page(pte);
+ pgtable_page_ctor(page);
+ return page;
}
static inline void sun4c_free_pte_fast(pte_t *pte)
pgtable_cache_size++;
}
-static void sun4c_pte_free(struct page *pte)
+static void sun4c_pte_free(pgtable_t pte)
{
+ pgtable_page_dtor(pte);
sun4c_free_pte_fast(page_address(pte));
}
bool
def_bool y
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
choice
prompt "Kernel page size"
default SPARC64_PAGE_SIZE_8KB
bool
depends on SPARC32_COMPAT
default y
-
-config BINFMT_ELF32
- bool "Kernel support for 32-bit ELF binaries"
- depends on SPARC32_COMPAT
- help
- This allows you to run 32-bit Linux/ELF binaries on your Ultra.
- Everybody wants this; say Y.
+ select COMPAT_BINFMT_ELF
config BINFMT_AOUT32
bool "Kernel support for 32-bit (ie. SunOS) a.out binaries"
- depends on SPARC32_COMPAT
+ depends on SPARC32_COMPAT && ARCH_SUPPORTS_AOUT
help
This allows you to run 32-bit a.out format binaries on your Ultra.
If you want to run SunOS binaries (see SunOS binary emulation below)
obj-$(CONFIG_PCI_MSI) += pci_msi.o
obj-$(CONFIG_SMP) += smp.o trampoline.o hvtramp.o
obj-$(CONFIG_SPARC32_COMPAT) += sys32.o sys_sparc32.o signal32.o
-obj-$(CONFIG_BINFMT_ELF32) += binfmt_elf32.o
obj-$(CONFIG_BINFMT_AOUT32) += binfmt_aout32.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_US3_FREQ) += us3_cpufreq.o
#include <asm/uaccess.h>
#include <asm/pgalloc.h>
#include <asm/mmu_context.h>
+#include <asm/a.out-core.h>
static int load_aout32_binary(struct linux_binprm *, struct pt_regs * regs);
static int load_aout32_library(struct file*);
current->flags |= PF_DUMPCORE;
strncpy(dump.u_comm, current->comm, sizeof(dump.u_comm));
dump.signal = signr;
- dump_thread(regs, &dump);
+ aout_dump_thread(regs, &dump);
/* If the size of the dump file exceeds the rlimit, then see what would happen
if we wrote the stack, but not the data area. */
+++ /dev/null
-/*
- * binfmt_elf32.c: Support 32-bit Sparc ELF binaries on Ultra.
- *
- * Copyright (C) 1995, 1996, 1997, 1998, 2008 David S. Miller (davem@davemloft.net)
- * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek (jj@ultra.linux.cz)
- */
-
-#define ELF_ARCH EM_SPARC
-#define ELF_CLASS ELFCLASS32
-#define ELF_DATA ELFDATA2MSB;
-
-/* Format is:
- * G0 --> G7
- * O0 --> O7
- * L0 --> L7
- * I0 --> I7
- * PSR, PC, nPC, Y, WIM, TBR
- */
-typedef unsigned int elf_greg_t;
-#define ELF_NGREG 38
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct {
- union {
- unsigned int pr_regs[32];
- unsigned long pr_dregs[16];
- } pr_fr;
- unsigned int __unused;
- unsigned int pr_fsr;
- unsigned char pr_qcnt;
- unsigned char pr_q_entrysize;
- unsigned char pr_en;
- unsigned int pr_q[64];
-} elf_fpregset_t;
-
-/* UltraSparc extensions. Still unused, but will be eventually. */
-typedef struct {
- unsigned int pr_type;
- unsigned int pr_align;
- union {
- struct {
- union {
- unsigned int pr_regs[32];
- unsigned long pr_dregs[16];
- long double pr_qregs[8];
- } pr_xfr;
- } pr_v8p;
- unsigned int pr_xfsr;
- unsigned int pr_fprs;
- unsigned int pr_xg[8];
- unsigned int pr_xo[8];
- unsigned long pr_tstate;
- unsigned int pr_filler[8];
- } pr_un;
-} elf_xregset_t;
-
-#define elf_check_arch(x) (((x)->e_machine == EM_SPARC) || ((x)->e_machine == EM_SPARC32PLUS))
-
-#define ELF_ET_DYN_BASE 0x70000000
-
-
-#include <asm/processor.h>
-#include <linux/module.h>
-#include <linux/elfcore.h>
-#include <linux/compat.h>
-
-#define elf_prstatus elf_prstatus32
-struct elf_prstatus32
-{
- struct elf_siginfo pr_info; /* Info associated with signal */
- short pr_cursig; /* Current signal */
- unsigned int pr_sigpend; /* Set of pending signals */
- unsigned int pr_sighold; /* Set of held signals */
- pid_t pr_pid;
- pid_t pr_ppid;
- pid_t pr_pgrp;
- pid_t pr_sid;
- struct compat_timeval pr_utime; /* User time */
- struct compat_timeval pr_stime; /* System time */
- struct compat_timeval pr_cutime; /* Cumulative user time */
- struct compat_timeval pr_cstime; /* Cumulative system time */
- elf_gregset_t pr_reg; /* GP registers */
- int pr_fpvalid; /* True if math co-processor being used. */
-};
-
-#define elf_prpsinfo elf_prpsinfo32
-struct elf_prpsinfo32
-{
- char pr_state; /* numeric process state */
- char pr_sname; /* char for pr_state */
- char pr_zomb; /* zombie */
- char pr_nice; /* nice val */
- unsigned int pr_flag; /* flags */
- u16 pr_uid;
- u16 pr_gid;
- pid_t pr_pid, pr_ppid, pr_pgrp, pr_sid;
- /* Lots missing */
- char pr_fname[16]; /* filename of executable */
- char pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */
-};
-
-#include <linux/highuid.h>
-
-#undef NEW_TO_OLD_UID
-#undef NEW_TO_OLD_GID
-#define NEW_TO_OLD_UID(uid) ((uid) > 65535) ? (u16)overflowuid : (u16)(uid)
-#define NEW_TO_OLD_GID(gid) ((gid) > 65535) ? (u16)overflowgid : (u16)(gid)
-
-#include <linux/time.h>
-
-#undef cputime_to_timeval
-#define cputime_to_timeval cputime_to_compat_timeval
-static inline void
-cputime_to_compat_timeval(const cputime_t cputime, struct compat_timeval *value)
-{
- unsigned long jiffies = cputime_to_jiffies(cputime);
- value->tv_usec = (jiffies % HZ) * (1000000L / HZ);
- value->tv_sec = jiffies / HZ;
-}
-
-#undef start_thread
-#define start_thread start_thread32
-#define init_elf_binfmt init_elf32_binfmt
-
-MODULE_DESCRIPTION("Binary format loader for compatibility with 32bit SparcLinux binaries on the Ultra");
-MODULE_AUTHOR("Eric Youngdale, David S. Miller, Jakub Jelinek");
-
-#undef MODULE_DESCRIPTION
-#undef MODULE_AUTHOR
-
-#include <asm/a.out.h>
-
-#undef TASK_SIZE
-#define TASK_SIZE STACK_TOP32
-
-#include "../../../fs/binfmt_elf.c"
.set_affinity = sun4v_virt_set_affinity,
};
-static void fastcall pre_flow_handler(unsigned int virt_irq,
+static void pre_flow_handler(unsigned int virt_irq,
struct irq_desc *desc)
{
struct irq_handler_data *data = get_irq_chip_data(virt_irq);
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/reboot.h>
#include <linux/delay.h>
#include <linux/compat.h>
return retval;
}
-/*
- * fill in the user structure for a core dump..
- */
-void dump_thread(struct pt_regs * regs, struct user * dump)
-{
- /* Only should be used for SunOS and ancient a.out
- * SparcLinux binaries... Not worth implementing.
- */
- memset(dump, 0, sizeof(struct user));
-}
-
typedef struct {
union {
unsigned int pr_regs[32];
return &user_sparc64_view;
}
-long arch_ptrace(struct task_struct *child, long request, long addr, long data)
+struct compat_fps {
+ unsigned int regs[32];
+ unsigned int fsr;
+ unsigned int flags;
+ unsigned int extra;
+ unsigned int fpqd;
+ struct compat_fq {
+ unsigned int insnaddr;
+ unsigned int insn;
+ } fpq[16];
+};
+
+long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
+ compat_ulong_t caddr, compat_ulong_t cdata)
{
- long addr2 = task_pt_regs(current)->u_regs[UREG_I4];
- const struct user_regset_view *view;
+ const struct user_regset_view *view = task_user_regset_view(child);
+ compat_ulong_t caddr2 = task_pt_regs(current)->u_regs[UREG_I4];
+ struct pt_regs32 __user *pregs;
+ struct compat_fps __user *fps;
+ unsigned long addr2 = caddr2;
+ unsigned long addr = caddr;
+ unsigned long data = cdata;
int ret;
- if (test_thread_flag(TIF_32BIT))
- addr2 &= 0xffffffffUL;
+ pregs = (struct pt_regs32 __user *) addr;
+ fps = (struct compat_fps __user *) addr;
- view = task_user_regset_view(child);
-
- switch(request) {
+ switch (request) {
case PTRACE_PEEKUSR:
ret = (addr != 0) ? -EIO : 0;
break;
- case PTRACE_PEEKTEXT: /* read word at location addr. */
- case PTRACE_PEEKDATA: {
- unsigned long tmp64;
- unsigned int tmp32;
- int copied;
-
- ret = -EIO;
- if (test_thread_flag(TIF_32BIT)) {
- copied = access_process_vm(child, addr,
- &tmp32, sizeof(tmp32), 0);
- if (copied == sizeof(tmp32))
- ret = put_user(tmp32,
- (unsigned int __user *) data);
- } else {
- copied = access_process_vm(child, addr,
- &tmp64, sizeof(tmp64), 0);
- if (copied == sizeof(tmp64))
- ret = put_user(tmp64,
- (unsigned long __user *) data);
- }
- break;
- }
-
- case PTRACE_POKETEXT: /* write the word at location addr. */
- case PTRACE_POKEDATA: {
- unsigned long tmp64;
- unsigned int tmp32;
- int copied;
-
- ret = -EIO;
- if (test_thread_flag(TIF_32BIT)) {
- tmp32 = data;
- copied = access_process_vm(child, addr,
- &tmp32, sizeof(tmp32), 1);
- if (copied == sizeof(tmp32))
- ret = 0;
- } else {
- tmp64 = data;
- copied = access_process_vm(child, addr,
- &tmp64, sizeof(tmp64), 1);
- if (copied == sizeof(tmp64))
- ret = 0;
- }
- break;
- }
-
- case PTRACE_GETREGS: {
- struct pt_regs32 __user *pregs =
- (struct pt_regs32 __user *) addr;
-
+ case PTRACE_GETREGS:
ret = copy_regset_to_user(child, view, REGSET_GENERAL,
32 * sizeof(u32),
4 * sizeof(u32),
15 * sizeof(u32),
&pregs->u_regs[0]);
break;
- }
-
- case PTRACE_GETREGS64: {
- struct pt_regs __user *pregs = (struct pt_regs __user *) addr;
-
- ret = copy_regset_to_user(child, view, REGSET_GENERAL,
- 1 * sizeof(u64),
- 15 * sizeof(u64),
- &pregs->u_regs[0]);
- if (!ret) {
- /* XXX doesn't handle 'y' register correctly XXX */
- ret = copy_regset_to_user(child, view, REGSET_GENERAL,
- 32 * sizeof(u64),
- 4 * sizeof(u64),
- &pregs->tstate);
- }
- break;
- }
-
- case PTRACE_SETREGS: {
- struct pt_regs32 __user *pregs =
- (struct pt_regs32 __user *) addr;
+ case PTRACE_SETREGS:
ret = copy_regset_from_user(child, view, REGSET_GENERAL,
32 * sizeof(u32),
4 * sizeof(u32),
15 * sizeof(u32),
&pregs->u_regs[0]);
break;
- }
-
- case PTRACE_SETREGS64: {
- struct pt_regs __user *pregs = (struct pt_regs __user *) addr;
-
- ret = copy_regset_from_user(child, view, REGSET_GENERAL,
- 1 * sizeof(u64),
- 15 * sizeof(u64),
- &pregs->u_regs[0]);
- if (!ret) {
- /* XXX doesn't handle 'y' register correctly XXX */
- ret = copy_regset_from_user(child, view, REGSET_GENERAL,
- 32 * sizeof(u64),
- 4 * sizeof(u64),
- &pregs->tstate);
- }
- break;
- }
-
- case PTRACE_GETFPREGS: {
- struct fps {
- unsigned int regs[32];
- unsigned int fsr;
- unsigned int flags;
- unsigned int extra;
- unsigned int fpqd;
- struct fq {
- unsigned int insnaddr;
- unsigned int insn;
- } fpq[16];
- };
- struct fps __user *fps = (struct fps __user *) addr;
+ case PTRACE_GETFPREGS:
ret = copy_regset_to_user(child, view, REGSET_FP,
0 * sizeof(u32),
32 * sizeof(u32),
ret = -EFAULT;
}
break;
- }
-
- case PTRACE_GETFPREGS64: {
- struct fps {
- unsigned int regs[64];
- unsigned long fsr;
- };
- struct fps __user *fps = (struct fps __user *) addr;
-
- ret = copy_regset_to_user(child, view, REGSET_FP,
- 0 * sizeof(u64),
- 33 * sizeof(u64),
- fps);
- break;
- }
-
- case PTRACE_SETFPREGS: {
- struct fps {
- unsigned int regs[32];
- unsigned int fsr;
- unsigned int flags;
- unsigned int extra;
- unsigned int fpqd;
- struct fq {
- unsigned int insnaddr;
- unsigned int insn;
- } fpq[16];
- };
- struct fps __user *fps = (struct fps __user *) addr;
+ case PTRACE_SETFPREGS:
ret = copy_regset_from_user(child, view, REGSET_FP,
0 * sizeof(u32),
32 * sizeof(u32),
1 * sizeof(u32),
&fps->fsr);
break;
+
+ case PTRACE_READTEXT:
+ case PTRACE_READDATA:
+ ret = ptrace_readdata(child, addr,
+ (char __user *)addr2, data);
+ if (ret == data)
+ ret = 0;
+ else if (ret >= 0)
+ ret = -EIO;
+ break;
+
+ case PTRACE_WRITETEXT:
+ case PTRACE_WRITEDATA:
+ ret = ptrace_writedata(child, (char __user *) addr2,
+ addr, data);
+ if (ret == data)
+ ret = 0;
+ else if (ret >= 0)
+ ret = -EIO;
+ break;
+
+ default:
+ ret = compat_ptrace_request(child, request, addr, data);
+ break;
}
- case PTRACE_SETFPREGS64: {
- struct fps {
- unsigned int regs[64];
- unsigned long fsr;
- };
- struct fps __user *fps = (struct fps __user *) addr;
+ return ret;
+}
+
+struct fps {
+ unsigned int regs[64];
+ unsigned long fsr;
+};
+
+long arch_ptrace(struct task_struct *child, long request, long addr, long data)
+{
+ const struct user_regset_view *view = task_user_regset_view(child);
+ struct pt_regs __user *pregs = (struct pt_regs __user *) addr;
+ unsigned long addr2 = task_pt_regs(current)->u_regs[UREG_I4];
+ struct fps __user *fps = (struct fps __user *) addr;
+ int ret;
+
+ switch (request) {
+ case PTRACE_PEEKUSR:
+ ret = (addr != 0) ? -EIO : 0;
+ break;
+ case PTRACE_GETREGS64:
+ ret = copy_regset_to_user(child, view, REGSET_GENERAL,
+ 1 * sizeof(u64),
+ 15 * sizeof(u64),
+ &pregs->u_regs[0]);
+ if (!ret) {
+ /* XXX doesn't handle 'y' register correctly XXX */
+ ret = copy_regset_to_user(child, view, REGSET_GENERAL,
+ 32 * sizeof(u64),
+ 4 * sizeof(u64),
+ &pregs->tstate);
+ }
+ break;
+
+ case PTRACE_SETREGS64:
+ ret = copy_regset_from_user(child, view, REGSET_GENERAL,
+ 1 * sizeof(u64),
+ 15 * sizeof(u64),
+ &pregs->u_regs[0]);
+ if (!ret) {
+ /* XXX doesn't handle 'y' register correctly XXX */
+ ret = copy_regset_from_user(child, view, REGSET_GENERAL,
+ 32 * sizeof(u64),
+ 4 * sizeof(u64),
+ &pregs->tstate);
+ }
+ break;
+
+ case PTRACE_GETFPREGS64:
+ ret = copy_regset_to_user(child, view, REGSET_FP,
+ 0 * sizeof(u64),
+ 33 * sizeof(u64),
+ fps);
+ break;
+
+ case PTRACE_SETFPREGS64:
ret = copy_regset_to_user(child, view, REGSET_FP,
0 * sizeof(u64),
33 * sizeof(u64),
fps);
break;
- }
case PTRACE_READTEXT:
case PTRACE_READDATA:
ret = -EIO;
break;
- case PTRACE_GETEVENTMSG: {
- if (test_thread_flag(TIF_32BIT))
- ret = put_user(child->ptrace_message,
- (unsigned int __user *) data);
- else
- ret = put_user(child->ptrace_message,
- (unsigned long __user *) data);
- break;
- }
-
default:
ret = ptrace_request(child, request, addr, data);
break;
#include <linux/slab.h>
#include <asm/smp.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/screen_info.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <asm/ebus.h>
#include <asm/isa.h>
#endif
-#include <asm/a.out.h>
#include <asm/ns87303.h>
#include <asm/timer.h>
#include <asm/cpudata.h>
#include <asm/uaccess.h>
#include <asm/utrap.h>
#include <asm/perfctr.h>
-#include <asm/a.out.h>
#include <asm/unistd.h>
/* #define DEBUG_UNIMP_SYSCALL */
#include <asm/fpumacro.h>
#include <asm/semaphore.h>
#include <asm/mmu_context.h>
-#include <asm/a.out.h>
#include <asm/compat_signal.h>
asmlinkage long sys32_chown16(const char __user * filename, u16 user, u16 group)
/*10*/ .word sys_unlink, sunos_execv, sys_chdir, sys32_chown16, sys32_mknod
/*15*/ .word sys_chmod, sys32_lchown16, sparc_brk, sys32_perfctr, sys32_lseek
/*20*/ .word sys_getpid, sys_capget, sys_capset, sys32_setuid16, sys32_getuid16
-/*25*/ .word sys32_vmsplice, sys_ptrace, sys_alarm, sys32_sigaltstack, sys32_pause
+/*25*/ .word sys32_vmsplice, compat_sys_ptrace, sys_alarm, sys32_sigaltstack, sys32_pause
/*30*/ .word compat_sys_utime, sys_lchown, sys_fchown, sys32_access, sys32_nice
.word sys_chown, sys_sync, sys32_kill, compat_sys_newstat, sys32_sendfile
/*40*/ .word compat_sys_newlstat, sys_dup, sys_pipe, compat_sys_times, sys_getuid
switch (cmd) {
case 0: /* getpgrp */
- return task_pgrp_nr(current);
+ return task_pgrp_vnr(current);
case 1: /* setpgrp */
{
int (*sys_setpgid)(pid_t,pid_t) =
ret = sys_setpgid(0, 0);
if (ret) return ret;
proc_clear_tty(current);
- return task_pgrp_nr(current);
+ return task_pgrp_vnr(current);
}
case 2: /* getsid */
{
depends on SMP
default "32"
-config NEST_LEVEL
- int "Nesting level"
- default "0"
- help
- This is set to the number of layers of UMLs that this UML will be run
- in. Normally, this is zero, meaning that it will run directly on the
- host. Setting it to one will build a UML that can run inside a UML
- that is running on the host. Generally, if you intend this UML to run
- inside another UML, set CONFIG_NEST_LEVEL to one more than the host
- UML.
-
config HIGHMEM
bool "Highmem support (EXPERIMENTAL)"
depends on !64BIT && EXPERIMENTAL
bool
default y
-choice
- prompt "Host memory split"
- default HOST_VMSPLIT_3G
- help
- This is needed when the host kernel on which you run has a non-default
- (like 2G/2G) memory split, instead of the customary 3G/1G. If you did
- not recompile your own kernel but use the default distro's one, you can
- safely accept the "Default split" option.
-
- It can be enabled on recent (>=2.6.16-rc2) vanilla kernels via
- CONFIG_VM_SPLIT_*, or on previous kernels with special patches (-ck
- patchset by Con Kolivas, or other ones) - option names match closely the
- host CONFIG_VM_SPLIT_* ones.
-
- A lower setting (where 1G/3G is lowest and 3G/1G is higher) will
- tolerate even more "normal" host kernels, but an higher setting will be
- stricter.
-
- So, if you do not know what to do here, say 'Default split'.
-
-config HOST_VMSPLIT_3G
- bool "Default split (3G/1G user/kernel host split)"
-config HOST_VMSPLIT_3G_OPT
- bool "3G/1G user/kernel host split (for full 1G low memory)"
-config HOST_VMSPLIT_2G
- bool "2G/2G user/kernel host split"
-config HOST_VMSPLIT_1G
- bool "1G/3G user/kernel host split"
-endchoice
-
-config TOP_ADDR
- hex
- default 0xB0000000 if HOST_VMSPLIT_3G_OPT
- default 0x78000000 if HOST_VMSPLIT_2G
- default 0x40000000 if HOST_VMSPLIT_1G
- default 0xC0000000
-
config 3_LEVEL_PGTABLES
bool "Three-level pagetables (EXPERIMENTAL)"
default n
bool
default y
+config ARCH_SUPPORTS_AOUT
+ def_bool y
bool
default y
-config TOP_ADDR
- hex
- default 0x7fc0000000
-
config 3_LEVEL_PGTABLES
bool
default y
bool
default y
+config ARCH_SUPPORTS_AOUT
+ def_bool y
KBUILD_CFLAGS += $(KERNEL_DEFINES)
KBUILD_CFLAGS += $(call cc-option,-fno-unit-at-a-time,)
-# These are needed for clean and mrproper, since in that case .config is not
-# included; the values here are meaningless
-
-CONFIG_NEST_LEVEL ?= 0
-
-SIZE = ($(CONFIG_NEST_LEVEL) * 0x20000000)
-
PHONY += linux
all: linux
CONFIG_KERNEL_STACK_ORDER ?= 2
STACK_SIZE := $(shell echo $$[ 4096 * (1 << $(CONFIG_KERNEL_STACK_ORDER)) ] )
-ifndef START
- START = $(shell echo $$[ $(TOP_ADDR) - $(SIZE) ] )
-endif
-
CPPFLAGS_vmlinux.lds = -U$(SUBARCH) -DSTART=$(START) -DELF_ARCH=$(ELF_ARCH) \
-DELF_FORMAT="$(ELF_FORMAT)" -DKERNEL_STACK_SIZE=$(STACK_SIZE)
CONFIG_UML_X86=y
# CONFIG_64BIT is not set
CONFIG_SEMAPHORE_SLEEPERS=y
-# CONFIG_HOST_2G_2G is not set
-CONFIG_TOP_ADDR=0xc0000000
# CONFIG_3_LEVEL_PGTABLES is not set
CONFIG_ARCH_HAS_SC_SIGNALS=y
CONFIG_ARCH_REUSE_HOST_VSYSCALL_AREA=y
# CONFIG_HPPFS is not set
CONFIG_MCONSOLE=y
CONFIG_MAGIC_SYSRQ=y
-CONFIG_NEST_LEVEL=0
# CONFIG_HIGHMEM is not set
CONFIG_KERNEL_STACK_ORDER=0
extern unsigned long _unprotected_end;
extern unsigned long brk_start;
+extern unsigned long host_task_size;
+
extern int linux_main(int argc, char **argv);
extern void (*sig_info[])(int, struct uml_pt_regs *);
extern int os_arch_prctl(int pid, int code, unsigned long *addr);
/* tty.c */
-int get_pty(void);
+extern int get_pty(void);
+
+/* sys-$ARCH/task_size.c */
+extern unsigned long os_get_task_size(void);
#endif
+++ /dev/null
-/*
- * Copyright (C) 2000, 2001, 2002 Jeff Dike (jdike@karaya.com)
- * Licensed under the GPL
- */
-
-#ifndef __TEMPFILE_H__
-#define __TEMPFILE_H__
-
-extern int make_tempfile(const char *template, char **tempname, int do_unlink);
-
-#endif
typedef struct mm_context {
struct mm_id id;
struct uml_ldt ldt;
+ struct page **stub_pages;
} mm_context_t;
extern void __switch_mm(struct mm_id * mm_idp);
ret = unmap(¤t->mm->context.id, 0, STUB_START, 0, &data);
ret = ret || unmap(¤t->mm->context.id, STUB_END,
- TASK_SIZE - STUB_END, 1, &data);
+ host_task_size - STUB_END, 1, &data);
if (ret) {
printk(KERN_ERR "flush_thread - clearing address space failed, "
"err = %d\n", ret);
#include "linux/module.h"
#include "linux/syscalls.h"
-#include "asm/a.out.h"
#include "asm/tlbflush.h"
#include "asm/uaccess.h"
#include "as-layout.h"
EXPORT_SYMBOL(os_rcv_fd);
EXPORT_SYMBOL(run_helper);
EXPORT_SYMBOL(start_thread);
-EXPORT_SYMBOL(dump_thread);
#ifdef CONFIG_SMP
return pte;
}
-struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
struct page *pte;
pte = alloc_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
+ if (pte)
+ pgtable_page_ctor(pte);
return pte;
}
default_idle();
}
-void dump_thread(struct pt_regs *regs, struct user *u)
-{
-}
-
int __cant_sleep(void) {
return in_atomic() || irqs_disabled() || in_interrupt();
/* Is in_interrupt() really needed? */
goto out_free;
}
+ to_mm->stub_pages = NULL;
+
return 0;
out_free:
pages[0] = virt_to_page(&__syscall_stub_start);
pages[1] = virt_to_page(mm->context.id.stack);
+ mm->context.stub_pages = pages;
/* dup_mmap already holds mmap_sem */
err = install_special_mapping(mm, STUB_START, STUB_END - STUB_START,
{
pte_t *pte;
+ if (mm->context.stub_pages != NULL)
+ kfree(mm->context.stub_pages);
pte = virt_to_pte(mm, STUB_CODE);
if (pte != NULL)
pte_clear(mm, STUB_CODE, pte);
};
/* Set during early boot */
+unsigned long task_size;
+EXPORT_SYMBOL(task_size);
+
+unsigned long host_task_size;
+
unsigned long brk_start;
unsigned long end_iomem;
EXPORT_SYMBOL(end_iomem);
if (have_root == 0)
add_arg(DEFAULT_COMMAND_LINE);
+ host_task_size = os_get_task_size();
+ /*
+ * TASK_SIZE needs to be PGDIR_SIZE aligned or else exit_mmap craps
+ * out
+ */
+ task_size = host_task_size & PGDIR_MASK;
+
/* OS sanity checks that need to happen before the kernel runs */
os_early_checks();
highmem = 0;
iomem_size = (iomem_size + PAGE_SIZE - 1) & PAGE_MASK;
- max_physmem = CONFIG_TOP_ADDR - uml_physmem - iomem_size - MIN_VMALLOC;
+ max_physmem = TASK_SIZE - uml_physmem - iomem_size - MIN_VMALLOC;
/*
* Zones have to begin on a 1 << MAX_ORDER page boundary,
}
virtmem_size = physmem_size;
- avail = CONFIG_TOP_ADDR - start_vm;
+ avail = TASK_SIZE - start_vm;
if (physmem_size > avail)
virtmem_size = avail;
end_vm = start_vm + virtmem_size;
if (actual != req->offset)
return -errno;
- switch(req->type) {
+ switch (req->type) {
case AIO_READ:
n = read(req->io_fd, req->buf, req->len);
break;
* Licensed under the GPL.
*/
-#include "linux/init.h"
+#include <linux/init.h>
#include <linux/netdevice.h>
#include "etap.h"
#include "net_kern.h"
epri->control_fd = -1;
epri->dev = dev;
- printk("ethertap backend - %s", epri->dev_name);
+ printk(KERN_INFO "ethertap backend - %s", epri->dev_name);
if (epri->gate_addr != NULL)
- printk(", IP = %s", epri->gate_addr);
- printk("\n");
+ printk(KERN_CONT ", IP = %s", epri->gate_addr);
+ printk(KERN_CONT "\n");
}
static int etap_read(int fd, struct sk_buff *skb, struct uml_net_private *lp)
tpri->fd = -1;
tpri->dev = dev;
- printk("TUN/TAP backend - ");
+ printk(KERN_INFO "TUN/TAP backend - ");
if (tpri->gate_addr != NULL)
- printk("IP = %s", tpri->gate_addr);
- printk("\n");
+ printk(KERN_CONT "IP = %s", tpri->gate_addr);
+ printk(KERN_CONT "\n");
}
static int tuntap_read(int fd, struct sk_buff *skb, struct uml_net_private *lp)
/*
- * Copyright (C) 2002 Jeff Dike (jdike@karaya.com)
+ * Copyright (C) 2002 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
* Licensed under the GPL
*/
#define DEV_NULL "/dev/null"
#endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only. This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
+/*
+ * Copyright (C) 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
+ * Licensed under the GPL
+ */
+
#include <stdio.h>
-#include <stdlib.h>
#include <stddef.h>
-#include <stdarg.h>
+#include <stdlib.h>
#include <unistd.h>
#include <errno.h>
-#include <string.h>
#include <fcntl.h>
-#include <sys/types.h>
+#include <string.h>
#include <sys/mman.h>
-#include <sys/statfs.h>
-#include "user.h"
-#include "mem_user.h"
+#include <sys/param.h>
#include "init.h"
-#include "os.h"
-#include "tempfile.h"
#include "kern_constants.h"
-
-#include <sys/param.h>
+#include "os.h"
+#include "user.h"
/* Modified by which_tmpdir, which is called during early boot */
static char *default_tmpdir = "/tmp";
int i;
char *dir = NULL;
- if(tempdir != NULL) /* We've already been called */
+ if (tempdir != NULL)
+ /* We've already been called */
return;
- for(i = 0; dirs[i]; i++){
+ for (i = 0; dirs[i]; i++) {
dir = getenv(dirs[i]);
- if((dir != NULL) && (*dir != '\0'))
+ if ((dir != NULL) && (*dir != '\0'))
break;
}
- if((dir == NULL) || (*dir == '\0'))
+ if ((dir == NULL) || (*dir == '\0'))
dir = default_tmpdir;
tempdir = malloc(strlen(dir) + 2);
- if(tempdir == NULL){
+ if (tempdir == NULL) {
fprintf(stderr, "Failed to malloc tempdir, "
"errno = %d\n", errno);
return;
strcat(tempdir, "/");
}
-/* This will return 1, with the first character in buf being the
+/*
+ * This will return 1, with the first character in buf being the
* character following the next instance of c in the file. This will
* read the file as needed. If there's an error, -errno is returned;
* if the end of the file is reached, 0 is returned.
size_t len;
char *ptr;
- while((ptr = strchr(buf, c)) == NULL){
+ while ((ptr = strchr(buf, c)) == NULL) {
n = read(fd, buf, size - 1);
- if(n == 0)
+ if (n == 0)
return 0;
- else if(n < 0)
+ else if (n < 0)
return -errno;
buf[n] = '\0';
len = strlen(ptr);
memmove(buf, ptr, len + 1);
- /* Refill the buffer so that if there's a partial string that we care
+ /*
+ * Refill the buffer so that if there's a partial string that we care
* about, it will be completed, and we can recognize it.
*/
n = read(fd, &buf[len], size - len - 1);
- if(n < 0)
+ if (n < 0)
return -errno;
buf[len + n] = '\0';
/* which_tmpdir is called only during early boot */
static int checked_tmpdir = 0;
-/* Look for a tmpfs mounted at /dev/shm. I couldn't find a cleaner
+/*
+ * Look for a tmpfs mounted at /dev/shm. I couldn't find a cleaner
* way to do this than to parse /proc/mounts. statfs will return the
* same filesystem magic number and fs id for both /dev and /dev/shm
* when they are both tmpfs, so you can't tell if they are different
int fd, found;
char buf[128] = { '\0' };
- if(checked_tmpdir)
+ if (checked_tmpdir)
return;
checked_tmpdir = 1;
printf("Checking for tmpfs mount on /dev/shm...");
fd = open("/proc/mounts", O_RDONLY);
- if(fd < 0){
+ if (fd < 0) {
printf("failed to open /proc/mounts, errno = %d\n", errno);
return;
}
- while(1){
+ while (1) {
found = next(fd, buf, ARRAY_SIZE(buf), ' ');
- if(found != 1)
+ if (found != 1)
break;
- if(!strncmp(buf, "/dev/shm", strlen("/dev/shm")))
+ if (!strncmp(buf, "/dev/shm", strlen("/dev/shm")))
goto found;
found = next(fd, buf, ARRAY_SIZE(buf), '\n');
- if(found != 1)
+ if (found != 1)
break;
}
err:
- if(found == 0)
+ if (found == 0)
printf("nothing mounted on /dev/shm\n");
- else if(found < 0)
+ else if (found < 0)
printf("read returned errno %d\n", -found);
out:
found:
found = next(fd, buf, ARRAY_SIZE(buf), ' ');
- if(found != 1)
+ if (found != 1)
goto err;
- if(strncmp(buf, "tmpfs", strlen("tmpfs"))){
+ if (strncmp(buf, "tmpfs", strlen("tmpfs"))) {
printf("not tmpfs\n");
goto out;
}
goto out;
}
-/*
- * This proc still used in tt-mode
- * (file: kernel/tt/ptproxy/proxy.c, proc: start_debugger).
- * So it isn't 'static' yet.
- */
-int __init make_tempfile(const char *template, char **out_tempname,
- int do_unlink)
+static int __init make_tempfile(const char *template, char **out_tempname,
+ int do_unlink)
{
char *tempname;
int fd;
which_tmpdir();
tempname = malloc(MAXPATHLEN);
- if (!tempname)
- goto out;
+ if (tempname == NULL)
+ return -1;
find_tempdir();
+ if ((tempdir == NULL) || (strlen(tempdir) >= MAXPATHLEN))
+ return -1;
+
if (template[0] != '/')
strcpy(tempname, tempdir);
else
tempname[0] = '\0';
strncat(tempname, template, MAXPATHLEN-1-strlen(tempname));
fd = mkstemp(tempname);
- if(fd < 0){
+ if (fd < 0) {
fprintf(stderr, "open - cannot create %s: %s\n", tempname,
strerror(errno));
goto out;
}
- if(do_unlink && (unlink(tempname) < 0)){
+ if (do_unlink && (unlink(tempname) < 0)) {
perror("unlink");
goto out;
}
- if(out_tempname){
+ if (out_tempname) {
*out_tempname = tempname;
- } else {
+ } else
free(tempname);
- }
return fd;
out:
free(tempname);
#define TEMPNAME_TEMPLATE "vm_file-XXXXXX"
-/*
- * This proc is used in start_up.c
- * So it isn't 'static'.
- */
-int __init create_tmp_file(unsigned long long len)
+static int __init create_tmp_file(unsigned long long len)
{
int fd, err;
char zero;
fd = make_tempfile(TEMPNAME_TEMPLATE, NULL, 1);
- if(fd < 0) {
+ if (fd < 0)
exit(1);
- }
err = fchmod(fd, 0777);
- if(err < 0){
+ if (err < 0) {
perror("fchmod");
exit(1);
}
- /* Seek to len - 1 because writing a character there will
+ /*
+ * Seek to len - 1 because writing a character there will
* increase the file size by one byte, to the desired length.
*/
if (lseek64(fd, len - 1, SEEK_SET) < 0) {
zero = 0;
err = write(fd, &zero, 1);
- if(err != 1){
+ if (err != 1) {
perror("write");
exit(1);
}
fd = create_tmp_file(len);
err = os_set_exec_close(fd);
- if(err < 0){
+ if (err < 0) {
errno = -err;
perror("exec_close");
}
PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE, fd, 0);
printf("Checking PROT_EXEC mmap in %s...",tempdir);
fflush(stdout);
- if(addr == MAP_FAILED){
+ if (addr == MAP_FAILED) {
err = errno;
perror("failed");
close(fd);
- if(err == EPERM)
+ if (err == EPERM)
printf("%s must be not mounted noexec\n",tempdir);
exit(1);
}
goto out_unmap;
}
- printk("OK\n");
+ printk(UM_KERN_CONT "OK\n");
ok = 1;
out_unmap:
* interrupts may have arrived and we need to re-enable them and
* recheck signals_pending.
*/
- while(1) {
+ while (1) {
/*
* Save and reset save_pending after enabling signals. This
* way, signals_pending won't be changed while we're reading it.
int local_using_sysemu;
if (getitimer(ITIMER_VIRTUAL, &timer))
- printk("Failed to get itimer, errno = %d\n", errno);
+ printk(UM_KERN_ERR "Failed to get itimer, errno = %d\n", errno);
nsecs = timer.it_value.tv_sec * UM_NSEC_PER_SEC +
timer.it_value.tv_usec * UM_NSEC_PER_USEC;
nsecs += os_nsecs();
if (WIFSTOPPED(status)) {
int sig = WSTOPSIG(status);
- switch(sig) {
+ switch (sig) {
case SIGSEGV:
if (PTRACE_FULL_FAULTINFO ||
!ptrace_faultinfo) {
* after returning to the jumper.
*/
n = setjmp(initial_jmpbuf);
- switch(n) {
+ switch (n) {
case INIT_JMP_NEW_THREAD:
(*switch_buf)[0].JB_IP = (unsigned long) new_thread_handler;
(*switch_buf)[0].JB_SP = (unsigned long) stack +
# Licensed under the GPL
#
-obj-y = registers.o signal.o tls.o
+obj-y = registers.o signal.o task_size.o tls.o
USER_OBJS := $(obj-y)
int err;
err = ptrace(PTRACE_GETFPXREGS, pid, 0, fpx_regs);
- if(!err)
+ if (!err)
return;
- if(errno != EIO)
+ if (errno != EIO)
panic("check_ptrace : PTRACE_GETFPXREGS failed, errno = %d",
errno);
--- /dev/null
+#include <stdio.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/mman.h>
+#include "longjmp.h"
+#include "kern_constants.h"
+
+static jmp_buf buf;
+
+static void segfault(int sig)
+{
+ longjmp(buf, 1);
+}
+
+static int page_ok(unsigned long page)
+{
+ unsigned long *address = (unsigned long *) (page << UM_KERN_PAGE_SHIFT);
+ unsigned long n = ~0UL;
+ void *mapped = NULL;
+ int ok = 0;
+
+ /*
+ * First see if the page is readable. If it is, it may still
+ * be a VDSO, so we go on to see if it's writable. If not
+ * then try mapping memory there. If that fails, then we're
+ * still in the kernel area. As a sanity check, we'll fail if
+ * the mmap succeeds, but gives us an address different from
+ * what we wanted.
+ */
+ if (setjmp(buf) == 0)
+ n = *address;
+ else {
+ mapped = mmap(address, UM_KERN_PAGE_SIZE,
+ PROT_READ | PROT_WRITE,
+ MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
+ if (mapped == MAP_FAILED)
+ return 0;
+ if (mapped != address)
+ goto out;
+ }
+
+ /*
+ * Now, is it writeable? If so, then we're in user address
+ * space. If not, then try mprotecting it and try the write
+ * again.
+ */
+ if (setjmp(buf) == 0) {
+ *address = n;
+ ok = 1;
+ goto out;
+ } else if (mprotect(address, UM_KERN_PAGE_SIZE,
+ PROT_READ | PROT_WRITE) != 0)
+ goto out;
+
+ if (setjmp(buf) == 0) {
+ *address = n;
+ ok = 1;
+ }
+
+ out:
+ if (mapped != NULL)
+ munmap(mapped, UM_KERN_PAGE_SIZE);
+ return ok;
+}
+
+unsigned long os_get_task_size(void)
+{
+ struct sigaction sa, old;
+ unsigned long bottom = 0;
+ /*
+ * A 32-bit UML on a 64-bit host gets confused about the VDSO at
+ * 0xffffe000. It is mapped, is readable, can be reprotected writeable
+ * and written. However, exec discovers later that it can't be
+ * unmapped. So, just set the highest address to be checked to just
+ * below it. This might waste some address space on 4G/4G 32-bit
+ * hosts, but shouldn't hurt otherwise.
+ */
+ unsigned long top = 0xffffd000 >> UM_KERN_PAGE_SHIFT;
+ unsigned long test;
+
+ printf("Locating the top of the address space ... ");
+ fflush(stdout);
+
+ /*
+ * We're going to be longjmping out of the signal handler, so
+ * SA_DEFER needs to be set.
+ */
+ sa.sa_handler = segfault;
+ sigemptyset(&sa.sa_mask);
+ sa.sa_flags = SA_NODEFER;
+ sigaction(SIGSEGV, &sa, &old);
+
+ if (!page_ok(bottom)) {
+ fprintf(stderr, "Address 0x%x no good?\n",
+ bottom << UM_KERN_PAGE_SHIFT);
+ exit(1);
+ }
+
+ /* This could happen with a 4G/4G split */
+ if (page_ok(top))
+ goto out;
+
+ do {
+ test = bottom + (top - bottom) / 2;
+ if (page_ok(test))
+ bottom = test;
+ else
+ top = test;
+ } while (top - bottom > 1);
+
+out:
+ /* Restore the old SIGSEGV handling */
+ sigaction(SIGSEGV, &old, NULL);
+
+ top <<= UM_KERN_PAGE_SHIFT;
+ printf("0x%x\n", top);
+ fflush(stdout);
+
+ return top;
+}
# Licensed under the GPL
#
-obj-y = registers.o prctl.o signal.o
+obj-y = registers.o prctl.o signal.o task_size.o
USER_OBJS := $(obj-y)
/*
- * Copyright (C) 2006-2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
+ * Copyright (C) 2006 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
* Licensed under the GPL
*/
#include <sys/ptrace.h>
#define __FRAME_OFFSETS
#include <asm/ptrace.h>
+#include "kern_constants.h"
#include "longjmp.h"
#include "user.h"
int save_fp_registers(int pid, unsigned long *fp_regs)
{
- if(ptrace(PTRACE_GETFPREGS, pid, 0, fp_regs) < 0)
+ if (ptrace(PTRACE_GETFPREGS, pid, 0, fp_regs) < 0)
return -errno;
return 0;
}
int restore_fp_registers(int pid, unsigned long *fp_regs)
{
- if(ptrace(PTRACE_SETFPREGS, pid, 0, fp_regs) < 0)
+ if (ptrace(PTRACE_SETFPREGS, pid, 0, fp_regs) < 0)
return -errno;
return 0;
}
unsigned long get_thread_reg(int reg, jmp_buf *buf)
{
- switch(reg){
- case RIP: return buf[0]->__rip;
- case RSP: return buf[0]->__rsp;
- case RBP: return buf[0]->__rbp;
+ switch (reg) {
+ case RIP:
+ return buf[0]->__rip;
+ case RSP:
+ return buf[0]->__rsp;
+ case RBP:
+ return buf[0]->__rbp;
default:
- printk("get_thread_regs - unknown register %d\n", reg);
+ printk(UM_KERN_ERR "get_thread_regs - unknown register %d\n",
+ reg);
return 0;
}
}
--- /dev/null
+unsigned long os_get_task_size(unsigned long shift)
+{
+ /* The old value of CONFIG_TOP_ADDR */
+ return 0x7fc0000000;
+}
/*
* Copyright (C) 2001 Chris Emerson (cemerson@chiark.greenend.org.uk)
- * Copyright (C) 2001, 2002 Jeff Dike (jdike@karaya.com)
+ * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
* Licensed under the GPL
*/
jmp_buf jbuf;
*fault_catcher = &jbuf;
- if(UML_SETJMP(&jbuf) == 0){
+ if (UML_SETJMP(&jbuf) == 0) {
(*op)(to, from, n);
ret = 0;
*faulted_out = 0;
* good; so the versions of these symbols will always match
*/
#define EXPORT_SYMBOL_PROTO(sym) \
- int sym(void); \
- EXPORT_SYMBOL(sym);
+ int sym(void); \
+ EXPORT_SYMBOL(sym);
extern void readdir64(void) __attribute__((weak));
EXPORT_SYMBOL(readdir64);
/*
- * Copyright (C) 2000, 2001, 2002 Jeff Dike (jdike@karaya.com)
+ * Copyright (C) 2000 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
* Licensed under the GPL
*/
#include <stdio.h>
#include <stdlib.h>
-#include <unistd.h>
-#include <limits.h>
-#include <sys/mman.h>
-#include <sys/stat.h>
-#include <sys/utsname.h>
-#include <sys/param.h>
-#include <sys/time.h>
-#include "asm/types.h"
-#include <ctype.h>
-#include <signal.h>
-#include <wait.h>
#include <errno.h>
-#include <stdarg.h>
-#include <sched.h>
-#include <termios.h>
+#include <signal.h>
#include <string.h>
-#include "kern_util.h"
-#include "user.h"
-#include "mem_user.h"
-#include "init.h"
-#include "ptrace_user.h"
-#include "uml-config.h"
-#include "os.h"
-#include "longjmp.h"
+#include <termios.h>
+#include <wait.h>
+#include <sys/mman.h>
+#include <sys/utsname.h>
#include "kern_constants.h"
+#include "os.h"
+#include "user.h"
void stack_protections(unsigned long address)
{
- if(mprotect((void *) address, UM_THREAD_SIZE,
+ if (mprotect((void *) address, UM_THREAD_SIZE,
PROT_READ | PROT_WRITE | PROT_EXEC) < 0)
panic("protecting stack failed, errno = %d", errno);
}
int err;
CATCH_EINTR(err = tcgetattr(fd, &tt));
- if(err < 0)
+ if (err < 0)
return -errno;
cfmakeraw(&tt);
CATCH_EINTR(err = tcsetattr(fd, TCSADRAIN, &tt));
- if(err < 0)
+ if (err < 0)
return -errno;
- /* XXX tcsetattr could have applied only some changes
- * (and cfmakeraw() is a set of changes) */
+ /*
+ * XXX tcsetattr could have applied only some changes
+ * (and cfmakeraw() is a set of changes)
+ */
return 0;
}
bool
default n
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
# Turn off some random 386 crap that can affect device config
config ISA
bool
bool
default !V850E_CACHE && !V850E2_CACHE
+ # HZ depends on the platform
+ config HZ
+ int
+ default 24 if V850E_SIM || V850E2_SIM85E2
+ default 122 if V850E2_FPGA85E2C
+ default 100
+
#### Misc config
config ROM_KERNEL
{
}
-struct seq_operations cpuinfo_op = {
+const struct seq_operations cpuinfo_op = {
.start = cpuinfo_start,
.next = cpuinfo_next,
.stop = cpuinfo_stop,
bool
default X86_64
+config ARCH_SUPPORTS_AOUT
+ def_bool y
+
# Use the generic interrupt handling code in kernel/irq/:
config GENERIC_HARDIRQS
bool
config IA32_AOUT
tristate "IA32 a.out support"
- depends on IA32_EMULATION
+ depends on IA32_EMULATION && ARCH_SUPPORTS_AOUT
help
Support old a.out binaries in the 32bit emulation.
#include <linux/slab.h>
#include <linux/vmalloc.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/interrupt.h>
#include <linux/utsname.h>
#include <linux/delay.h>
return err;
}
-/*
- * fill in the user structure for a core dump..
- */
-void dump_thread(struct pt_regs * regs, struct user * dump)
-{
- u16 gs;
-
-/* changed the size calculations - should hopefully work better. lbt */
- dump->magic = CMAGIC;
- dump->start_code = 0;
- dump->start_stack = regs->sp & ~(PAGE_SIZE - 1);
- dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
- dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1))) >> PAGE_SHIFT;
- dump->u_dsize -= dump->u_tsize;
- dump->u_ssize = 0;
- dump->u_debugreg[0] = current->thread.debugreg0;
- dump->u_debugreg[1] = current->thread.debugreg1;
- dump->u_debugreg[2] = current->thread.debugreg2;
- dump->u_debugreg[3] = current->thread.debugreg3;
- dump->u_debugreg[4] = 0;
- dump->u_debugreg[5] = 0;
- dump->u_debugreg[6] = current->thread.debugreg6;
- dump->u_debugreg[7] = current->thread.debugreg7;
-
- if (dump->start_stack < TASK_SIZE)
- dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;
-
- dump->regs.bx = regs->bx;
- dump->regs.cx = regs->cx;
- dump->regs.dx = regs->dx;
- dump->regs.si = regs->si;
- dump->regs.di = regs->di;
- dump->regs.bp = regs->bp;
- dump->regs.ax = regs->ax;
- dump->regs.ds = (u16)regs->ds;
- dump->regs.es = (u16)regs->es;
- dump->regs.fs = (u16)regs->fs;
- savesegment(gs,gs);
- dump->regs.orig_ax = regs->orig_ax;
- dump->regs.ip = regs->ip;
- dump->regs.cs = (u16)regs->cs;
- dump->regs.flags = regs->flags;
- dump->regs.sp = regs->sp;
- dump->regs.ss = (u16)regs->ss;
-
- dump->u_fpvalid = dump_fpu (regs, &dump->i387);
-}
-EXPORT_SYMBOL(dump_thread);
-
#ifdef CONFIG_SECCOMP
static void hard_disable_TSC(void)
{
#include <linux/smp.h>
#include <linux/slab.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/interrupt.h>
#include <linux/utsname.h>
#include <linux/delay.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/screen_info.h>
#include <linux/ioport.h>
#include <linux/delay.h>
reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
}
local_irq_save(flags);
- /* start meauring cycles, incrementing from 0 */
+ /* start measuring cycles, incrementing from 0 */
wrmsrl(MSR_K7_PERFCTR0 + i, 0);
wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76);
rdtscl(tsc_start);
return (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
}
-struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
struct page *pte;
#else
pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
#endif
+ if (pte)
+ pgtable_page_ctor(pte);
return pte;
}
void __pte_free_tlb(struct mmu_gather *tlb, struct page *pte)
{
+ pgtable_page_dtor(pte);
paravirt_release_pt(page_to_pfn(pte));
tlb_remove_page(tlb, pte);
}
config NO_IOPORT
def_bool y
+config HZ
+ int
+ default 100
+
source "init/Kconfig"
menu "Processor type and features"
{
}
-struct seq_operations cpuinfo_op =
+const struct seq_operations cpuinfo_op =
{
start: c_start,
next: c_next,
return;
if (!new_io) {
- __disk_stat_inc(rq->rq_disk, merges[rw]);
+ __all_stat_inc(rq->rq_disk, merges[rw], rq->sector);
} else {
+ struct hd_struct *part = get_part(rq->rq_disk, rq->sector);
disk_round_stats(rq->rq_disk);
rq->rq_disk->in_flight++;
+ if (part) {
+ part_round_stats(part);
+ part->in_flight++;
+ }
}
}
}
EXPORT_SYMBOL(blk_get_backing_dev_info);
+/*
+ * We can't just memset() the structure, since the allocation path
+ * already stored some information in the request.
+ */
void rq_init(struct request_queue *q, struct request *rq)
{
INIT_LIST_HEAD(&rq->queuelist);
INIT_LIST_HEAD(&rq->donelist);
-
- rq->errors = 0;
+ rq->q = q;
+ rq->sector = rq->hard_sector = (sector_t) -1;
+ rq->nr_sectors = rq->hard_nr_sectors = 0;
+ rq->current_nr_sectors = rq->hard_cur_sectors = 0;
rq->bio = rq->biotail = NULL;
INIT_HLIST_NODE(&rq->hash);
RB_CLEAR_NODE(&rq->rb_node);
+ rq->rq_disk = NULL;
+ rq->nr_phys_segments = 0;
+ rq->nr_hw_segments = 0;
rq->ioprio = 0;
+ rq->special = NULL;
rq->buffer = NULL;
+ rq->tag = -1;
+ rq->errors = 0;
rq->ref_count = 1;
- rq->q = q;
- rq->special = NULL;
+ rq->cmd_len = 0;
+ memset(rq->cmd, 0, sizeof(rq->cmd));
rq->data_len = 0;
+ rq->sense_len = 0;
rq->data = NULL;
- rq->nr_phys_segments = 0;
rq->sense = NULL;
rq->end_io = NULL;
rq->end_io_data = NULL;
- rq->completion_data = NULL;
rq->next_rq = NULL;
}
}
EXPORT_SYMBOL_GPL(disk_round_stats);
+void part_round_stats(struct hd_struct *part)
+{
+ unsigned long now = jiffies;
+
+ if (now == part->stamp)
+ return;
+
+ if (part->in_flight) {
+ __part_stat_add(part, time_in_queue,
+ part->in_flight * (now - part->stamp));
+ __part_stat_add(part, io_ticks, (now - part->stamp));
+ }
+ part->stamp = now;
+}
+
/*
* queue lock must be held
*/
if (bio_sectors(bio) && bdev != bdev->bd_contains) {
struct hd_struct *p = bdev->bd_part;
- const int rw = bio_data_dir(bio);
-
- p->sectors[rw] += bio_sectors(bio);
- p->ios[rw]++;
bio->bi_sector += p->start_sect;
bio->bi_bdev = bdev->bd_contains;
if (blk_fs_request(req) && req->rq_disk) {
const int rw = rq_data_dir(req);
- disk_stat_add(req->rq_disk, sectors[rw], nr_bytes >> 9);
+ all_stat_add(req->rq_disk, sectors[rw],
+ nr_bytes >> 9, req->sector);
}
total_bytes = bio_nbytes = 0;
if (disk && blk_fs_request(req) && req != &req->q->bar_rq) {
unsigned long duration = jiffies - req->start_time;
const int rw = rq_data_dir(req);
+ struct hd_struct *part = get_part(disk, req->sector);
- __disk_stat_inc(disk, ios[rw]);
- __disk_stat_add(disk, ticks[rw], duration);
+ __all_stat_inc(disk, ios[rw], req->sector);
+ __all_stat_add(disk, ticks[rw], duration, req->sector);
disk_round_stats(disk);
disk->in_flight--;
+ if (part) {
+ part_round_stats(part);
+ part->in_flight--;
+ }
}
if (req->end_io)
elv_merge_requests(q, req, next);
if (req->rq_disk) {
+ struct hd_struct *part
+ = get_part(req->rq_disk, req->sector);
disk_round_stats(req->rq_disk);
req->rq_disk->in_flight--;
+ if (part) {
+ part_round_stats(part);
+ part->in_flight--;
+ }
}
req->ioprio = ioprio_best(req->ioprio, next->ioprio);
for (n = 0; n < gp->minors - 1; n++) {
struct hd_struct *hd = gp->part[n];
- if (hd && hd->nr_sects)
- seq_printf(s, "%4d %4d %s %u %u %u %u\n",
- gp->major, n + gp->first_minor + 1,
- disk_name(gp, n + 1, buf),
- hd->ios[0], hd->sectors[0],
- hd->ios[1], hd->sectors[1]);
+ if (!hd || !hd->nr_sects)
+ continue;
+
+ preempt_disable();
+ part_round_stats(hd);
+ preempt_enable();
+ seq_printf(s, "%4d %4d %s %lu %lu %llu "
+ "%u %lu %lu %llu %u %u %u %u\n",
+ gp->major, n + gp->first_minor + 1,
+ disk_name(gp, n + 1, buf),
+ part_stat_read(hd, ios[0]),
+ part_stat_read(hd, merges[0]),
+ (unsigned long long)part_stat_read(hd, sectors[0]),
+ jiffies_to_msecs(part_stat_read(hd, ticks[0])),
+ part_stat_read(hd, ios[1]),
+ part_stat_read(hd, merges[1]),
+ (unsigned long long)part_stat_read(hd, sectors[1]),
+ jiffies_to_msecs(part_stat_read(hd, ticks[1])),
+ hd->in_flight,
+ jiffies_to_msecs(part_stat_read(hd, io_ticks)),
+ jiffies_to_msecs(part_stat_read(hd, time_in_queue))
+ );
}
return 0;
config ACPI_WMI
tristate "WMI (EXPERIMENTAL)"
+ depends on X86
depends on EXPERIMENTAL
help
- This driver adds support for the ACPI-WMI mapper device (PNP0C14)
- found on some systems.
+ This driver adds support for the ACPI-WMI (Windows Management
+ Instrumentation) mapper device (PNP0C14) found on some systems.
+
+ ACPI-WMI is a proprietary extension to ACPI to expose parts of the
+ ACPI firmware to userspace - this is done through various vendor
+ defined methods and data blocks in a PNP0C14 device, which are then
+ made available for userspace to call.
+
+ The implementation of this in Linux currently only exposes this to
+ other kernel space drivers.
+
+ This driver is a required dependency to build the firmware specific
+ drivers needed on many machines, including Acer and HP laptops.
- NOTE: You will need another driver or userspace application on top of
- this to actually use anything defined in the ACPI-WMI mapper.
+ It is safe to enable this driver even if your DSDT doesn't define
+ any ACPI-WMI devices.
config ACPI_ASUS
tristate "ASUS/Medion Laptop Extras"
* DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad T61"),
* _OSI(Linux) is a NOP:
* DMI_MATCH(DMI_PRODUCT_VERSION, "3000 N100"),
+ * _OSI(Linux) effect unknown
+ * DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X61"),
*/
{
.callback = dmi_enable_osi_linux,
},
{
.callback = dmi_unknown_osi_linux,
+ .ident = "Lenovo ThinkPad X61",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
+ DMI_MATCH(DMI_PRODUCT_VERSION, "ThinkPad X61"),
+ },
+ },
+ {
+ .callback = dmi_unknown_osi_linux,
.ident = "Lenovo 3000 V100",
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_NAME, "NEC VERSA M360"),
},
},
+ /* Panasonic */
+ {
+ .callback = dmi_unknown_osi_linux,
+ .ident = "Panasonic",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Matsushita"),
+ /* Toughbook CF-52 */
+ DMI_MATCH(DMI_PRODUCT_NAME, "CF-52CCABVBG"),
+ },
+ },
/*
* Disable OSI(Linux) warnings on all "Samsung Electronics"
*
struct kstat stat;
char *ramfs_dsdt_name = "/DSDT.aml";
- printk(KERN_INFO PREFIX "Checking initramfs for custom DSDT");
+ printk(KERN_INFO PREFIX "Checking initramfs for custom DSDT\n");
/*
* Never do this at home, only the user-space is allowed to open a file.
static DEFINE_MUTEX(performance_mutex);
+/* Use cpufreq debug layer for _PPC changes. */
+#define cpufreq_printk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_CORE, \
+ "cpufreq-core", msg)
+
/*
* _PPC support is implemented as a CPUfreq policy notifier:
* This means each time a CPUfreq driver registered also with
return -ENODEV;
}
+ cpufreq_printk("CPU %d: _PPC is %d - frequency %s limited\n", pr->id,
+ (int)ppc, ppc ? "" : "not");
+
pr->performance_platform_limit = (int)ppc;
return 0;
If unsure, say N.
config BLK_DEV_RAM
- tristate "RAM disk support"
+ tristate "RAM block device support"
---help---
Saying Y here will allow you to use a portion of your RAM memory as
a block device, so that you can make file systems on it, read and
The default value is 4096 kilobytes. Only change this if you know
what you are doing.
-config BLK_DEV_RAM_BLOCKSIZE
- int "Default RAM disk block size (bytes)"
+config BLK_DEV_XIP
+ bool "Support XIP filesystems on RAM block device"
depends on BLK_DEV_RAM
- default "1024"
+ default n
help
- The default value is 1024 bytes. PAGE_SIZE is a much more
- efficient choice however. The default is kept to ensure initrd
- setups function - apparently needed by the rd_load_image routine
- that supposes the filesystem in the image uses a 1024 blocksize.
+ Support XIP filesystems (such as ext2 with XIP support on) on
+ top of block ram device. This will slightly enlarge the kernel, and
+ will prevent RAM block device backing store memory from being
+ allocated from highmem (only a problem for highmem systems).
config CDROM_PKTCDVD
tristate "Packet writing on CD/DVD media"
obj-$(CONFIG_PS3_DISK) += ps3disk.o
obj-$(CONFIG_ATARI_FLOPPY) += ataflop.o
obj-$(CONFIG_AMIGA_Z2RAM) += z2ram.o
-obj-$(CONFIG_BLK_DEV_RAM) += rd.o
+obj-$(CONFIG_BLK_DEV_RAM) += brd.o
obj-$(CONFIG_BLK_DEV_LOOP) += loop.o
obj-$(CONFIG_BLK_DEV_PS2) += ps2esdi.o
obj-$(CONFIG_BLK_DEV_XD) += xd.o
-/* Copyright (c) 2006 Coraid, Inc. See COPYING for GPL terms. */
-#define VERSION "32"
+/* Copyright (c) 2007 Coraid, Inc. See COPYING for GPL terms. */
+#define VERSION "47"
#define AOE_MAJOR 152
#define DEVICE_NAME "aoe"
DEVFL_EXT = (1<<2), /* device accepts lba48 commands */
DEVFL_CLOSEWAIT = (1<<3), /* device is waiting for all closes to revalidate */
DEVFL_GDALLOC = (1<<4), /* need to alloc gendisk */
- DEVFL_PAUSE = (1<<5),
+ DEVFL_KICKME = (1<<5), /* slow polling network card catch */
DEVFL_NEWSIZE = (1<<6), /* need to update dev size in block layer */
- DEVFL_MAXBCNT = (1<<7), /* d->maxbcnt is not changeable */
- DEVFL_KICKME = (1<<8),
BUFFL_FAIL = 1,
};
DEFAULTBCNT = 2 * 512, /* 2 sectors */
NPERSHELF = 16, /* number of slots per shelf address */
FREETAG = -1,
- MIN_BUFS = 8,
+ MIN_BUFS = 16,
+ NTARGETS = 8,
+ NAOEIFS = 8,
+ NSKBPOOLMAX = 128,
+
+ TIMERTICK = HZ / 10,
+ MINTIMER = HZ >> 2,
+ MAXTIMER = HZ << 1,
+ HELPWAIT = 20,
};
struct buf {
struct list_head bufs;
- ulong start_time; /* for disk stats */
+ ulong stime; /* for disk stats */
ulong flags;
ulong nframesout;
- char *bufaddr;
ulong resid;
ulong bv_resid;
+ ulong bv_off;
sector_t sector;
struct bio *bio;
struct bio_vec *bv;
struct sk_buff *skb;
};
+struct aoeif {
+ struct net_device *nd;
+ unsigned char lost;
+ unsigned char lostjumbo;
+ ushort maxbcnt;
+};
+
+struct aoetgt {
+ unsigned char addr[6];
+ ushort nframes;
+ struct frame *frames;
+ struct aoeif ifs[NAOEIFS];
+ struct aoeif *ifp; /* current aoeif in use */
+ ushort nout;
+ ushort maxout;
+ u16 lasttag; /* last tag sent */
+ u16 useme;
+ ulong lastwadj; /* last window adjustment */
+ int wpkts, rpkts;
+ int dataref;
+};
+
struct aoedev {
struct aoedev *next;
- unsigned char addr[6]; /* remote mac addr */
- ushort flags;
ulong sysminor;
ulong aoemajor;
- ulong aoeminor;
+ u16 aoeminor;
+ u16 flags;
u16 nopen; /* (bd_openers isn't available without sleeping) */
- u16 lasttag; /* last tag sent */
u16 rttavg; /* round trip average of requests/responses */
u16 mintimer;
u16 fw_ver; /* version of blade's firmware */
- u16 maxbcnt;
struct work_struct work;/* disk create work struct */
struct gendisk *gd;
struct request_queue blkq;
sector_t ssize;
struct timer_list timer;
spinlock_t lock;
- struct net_device *ifp; /* interface ed is attached to */
struct sk_buff *sendq_hd; /* packets needing to be sent, list head */
struct sk_buff *sendq_tl;
+ struct sk_buff *skbpool_hd;
+ struct sk_buff *skbpool_tl;
+ int nskbpool;
mempool_t *bufpool; /* for deadlock-free Buf allocation */
struct list_head bufq; /* queue of bios to work on */
struct buf *inprocess; /* the one we're currently working on */
- ushort lostjumbo;
- ushort nframes; /* number of frames below */
- struct frame *frames;
+ struct aoetgt *targets[NTARGETS];
+ struct aoetgt **tgt; /* target in use when working */
+ struct aoetgt **htgt; /* target needing rexmit assistance */
};
void aoecmd_ata_rsp(struct sk_buff *);
void aoecmd_cfg_rsp(struct sk_buff *);
void aoecmd_sleepwork(struct work_struct *);
-struct sk_buff *new_skb(ulong);
+void aoecmd_cleanslate(struct aoedev *);
+struct sk_buff *aoecmd_ata_id(struct aoedev *);
int aoedev_init(void);
void aoedev_exit(void);
struct aoedev *aoedev_by_aoeaddr(int maj, int min);
-struct aoedev *aoedev_by_sysminor_m(ulong sysminor, ulong bufcnt);
+struct aoedev *aoedev_by_sysminor_m(ulong sysminor);
void aoedev_downdev(struct aoedev *d);
int aoedev_isbusy(struct aoedev *d);
+int aoedev_flush(const char __user *str, size_t size);
int aoenet_init(void);
void aoenet_exit(void);
int is_aoe_netif(struct net_device *ifp);
int set_aoe_iflist(const char __user *str, size_t size);
-u64 mac_addr(char addr[6]);
+unsigned long long mac_addr(char addr[6]);
-/* Copyright (c) 2006 Coraid, Inc. See COPYING for GPL terms. */
+/* Copyright (c) 2007 Coraid, Inc. See COPYING for GPL terms. */
/*
* aoeblk.c
* block device routines
return snprintf(page, PAGE_SIZE,
"%s%s\n",
(d->flags & DEVFL_UP) ? "up" : "down",
- (d->flags & DEVFL_PAUSE) ? ",paused" :
+ (d->flags & DEVFL_KICKME) ? ",kickme" :
(d->nopen && !(d->flags & DEVFL_UP)) ? ",closewait" : "");
/* I'd rather see nopen exported so we can ditch closewait */
}
{
struct gendisk *disk = dev_to_disk(dev);
struct aoedev *d = disk->private_data;
+ struct aoetgt *t = d->targets[0];
- return snprintf(page, PAGE_SIZE, "%012llx\n",
- (unsigned long long)mac_addr(d->addr));
+ if (t == NULL)
+ return snprintf(page, PAGE_SIZE, "none\n");
+ return snprintf(page, PAGE_SIZE, "%012llx\n", mac_addr(t->addr));
}
static ssize_t aoedisk_show_netif(struct device *dev,
struct device_attribute *attr, char *page)
{
struct gendisk *disk = dev_to_disk(dev);
struct aoedev *d = disk->private_data;
+ struct net_device *nds[8], **nd, **nnd, **ne;
+ struct aoetgt **t, **te;
+ struct aoeif *ifp, *e;
+ char *p;
+
+ memset(nds, 0, sizeof nds);
+ nd = nds;
+ ne = nd + ARRAY_SIZE(nds);
+ t = d->targets;
+ te = t + NTARGETS;
+ for (; t < te && *t; t++) {
+ ifp = (*t)->ifs;
+ e = ifp + NAOEIFS;
+ for (; ifp < e && ifp->nd; ifp++) {
+ for (nnd = nds; nnd < nd; nnd++)
+ if (*nnd == ifp->nd)
+ break;
+ if (nnd == nd && nd != ne)
+ *nd++ = ifp->nd;
+ }
+ }
- return snprintf(page, PAGE_SIZE, "%s\n", d->ifp->name);
+ ne = nd;
+ nd = nds;
+ if (*nd == NULL)
+ return snprintf(page, PAGE_SIZE, "none\n");
+ for (p = page; nd < ne; nd++)
+ p += snprintf(p, PAGE_SIZE - (p-page), "%s%s",
+ p == page ? "" : ",", (*nd)->name);
+ p += snprintf(p, PAGE_SIZE - (p-page), "\n");
+ return p-page;
}
/* firmware version */
static ssize_t aoedisk_show_fwver(struct device *dev,
blk_queue_bounce(q, &bio);
+ if (bio == NULL) {
+ printk(KERN_ERR "aoe: bio is NULL\n");
+ BUG();
+ return 0;
+ }
d = bio->bi_bdev->bd_disk->private_data;
+ if (d == NULL) {
+ printk(KERN_ERR "aoe: bd_disk->private_data is NULL\n");
+ BUG();
+ bio_endio(bio, -ENXIO);
+ return 0;
+ } else if (bio->bi_io_vec == NULL) {
+ printk(KERN_ERR "aoe: bi_io_vec is NULL\n");
+ BUG();
+ bio_endio(bio, -ENXIO);
+ return 0;
+ }
buf = mempool_alloc(d->bufpool, GFP_NOIO);
if (buf == NULL) {
printk(KERN_INFO "aoe: buf allocation failure\n");
}
memset(buf, 0, sizeof(*buf));
INIT_LIST_HEAD(&buf->bufs);
- buf->start_time = jiffies;
+ buf->stime = jiffies;
buf->bio = bio;
buf->resid = bio->bi_size;
buf->sector = bio->bi_sector;
buf->bv = &bio->bi_io_vec[bio->bi_idx];
- WARN_ON(buf->bv->bv_len == 0);
buf->bv_resid = buf->bv->bv_len;
- buf->bufaddr = page_address(buf->bv->bv_page) + buf->bv->bv_offset;
+ WARN_ON(buf->bv_resid == 0);
+ buf->bv_off = buf->bv->bv_offset;
spin_lock_irqsave(&d->lock, flags);
if ((d->flags & DEVFL_UP) == 0) {
- printk(KERN_INFO "aoe: device %ld.%ld is not up\n",
+ printk(KERN_INFO "aoe: device %ld.%d is not up\n",
d->aoemajor, d->aoeminor);
spin_unlock_irqrestore(&d->lock, flags);
mempool_free(buf, d->bufpool);
gd = alloc_disk(AOE_PARTITIONS);
if (gd == NULL) {
- printk(KERN_ERR "aoe: cannot allocate disk structure for %ld.%ld\n",
+ printk(KERN_ERR
+ "aoe: cannot allocate disk structure for %ld.%d\n",
d->aoemajor, d->aoeminor);
goto err;
}
d->bufpool = mempool_create_slab_pool(MIN_BUFS, buf_pool_cache);
if (d->bufpool == NULL) {
- printk(KERN_ERR "aoe: cannot allocate bufpool for %ld.%ld\n",
+ printk(KERN_ERR "aoe: cannot allocate bufpool for %ld.%d\n",
d->aoemajor, d->aoeminor);
goto err_disk;
}
gd->fops = &aoe_bdops;
gd->private_data = d;
gd->capacity = d->ssize;
- snprintf(gd->disk_name, sizeof gd->disk_name, "etherd/e%ld.%ld",
+ snprintf(gd->disk_name, sizeof gd->disk_name, "etherd/e%ld.%d",
d->aoemajor, d->aoeminor);
gd->queue = &d->blkq;
-/* Copyright (c) 2006 Coraid, Inc. See COPYING for GPL terms. */
+/* Copyright (c) 2007 Coraid, Inc. See COPYING for GPL terms. */
/*
* aoechr.c
* AoE character device driver
#include <linux/hdreg.h>
#include <linux/blkdev.h>
+#include <linux/delay.h>
#include "aoe.h"
enum {
MINOR_DISCOVER,
MINOR_INTERFACES,
MINOR_REVALIDATE,
+ MINOR_FLUSH,
MSGSZ = 2048,
NMSG = 100, /* message backlog to retain */
};
{ MINOR_DISCOVER, "discover" },
{ MINOR_INTERFACES, "interfaces" },
{ MINOR_REVALIDATE, "revalidate" },
+ { MINOR_FLUSH, "flush" },
};
static int
int major, minor, n;
ulong flags;
struct aoedev *d;
+ struct sk_buff *skb;
char buf[16];
if (size >= sizeof buf)
d = aoedev_by_aoeaddr(major, minor);
if (!d)
return -EINVAL;
-
spin_lock_irqsave(&d->lock, flags);
- d->flags &= ~DEVFL_MAXBCNT;
- d->flags |= DEVFL_PAUSE;
+ aoecmd_cleanslate(d);
+loop:
+ skb = aoecmd_ata_id(d);
spin_unlock_irqrestore(&d->lock, flags);
+ /* try again if we are able to sleep a bit,
+ * otherwise give up this revalidation
+ */
+ if (!skb && !msleep_interruptible(200)) {
+ spin_lock_irqsave(&d->lock, flags);
+ goto loop;
+ }
+ aoenet_xmit(skb);
aoecmd_cfg(major, minor);
-
return 0;
}
break;
case MINOR_REVALIDATE:
ret = revalidate(buf, cnt);
+ break;
+ case MINOR_FLUSH:
+ ret = aoedev_flush(buf, cnt);
}
if (ret == 0)
ret = cnt;
ulong flags;
n = (unsigned long) filp->private_data;
- switch (n) {
- case MINOR_ERR:
- spin_lock_irqsave(&emsgs_lock, flags);
-loop:
- em = emsgs + emsgs_head_idx;
- if ((em->flags & EMFL_VALID) == 0) {
- if (filp->f_flags & O_NDELAY) {
- spin_unlock_irqrestore(&emsgs_lock, flags);
- return -EAGAIN;
- }
- nblocked_emsgs_readers++;
+ if (n != MINOR_ERR)
+ return -EFAULT;
+
+ spin_lock_irqsave(&emsgs_lock, flags);
+ for (;;) {
+ em = emsgs + emsgs_head_idx;
+ if ((em->flags & EMFL_VALID) != 0)
+ break;
+ if (filp->f_flags & O_NDELAY) {
spin_unlock_irqrestore(&emsgs_lock, flags);
+ return -EAGAIN;
+ }
+ nblocked_emsgs_readers++;
- n = down_interruptible(&emsgs_sema);
+ spin_unlock_irqrestore(&emsgs_lock, flags);
+
+ n = down_interruptible(&emsgs_sema);
- spin_lock_irqsave(&emsgs_lock, flags);
+ spin_lock_irqsave(&emsgs_lock, flags);
- nblocked_emsgs_readers--;
+ nblocked_emsgs_readers--;
- if (n) {
- spin_unlock_irqrestore(&emsgs_lock, flags);
- return -ERESTARTSYS;
- }
- goto loop;
- }
- if (em->len > cnt) {
+ if (n) {
spin_unlock_irqrestore(&emsgs_lock, flags);
- return -EAGAIN;
+ return -ERESTARTSYS;
}
- mp = em->msg;
- len = em->len;
- em->msg = NULL;
- em->flags &= ~EMFL_VALID;
+ }
+ if (em->len > cnt) {
+ spin_unlock_irqrestore(&emsgs_lock, flags);
+ return -EAGAIN;
+ }
+ mp = em->msg;
+ len = em->len;
+ em->msg = NULL;
+ em->flags &= ~EMFL_VALID;
- emsgs_head_idx++;
- emsgs_head_idx %= ARRAY_SIZE(emsgs);
+ emsgs_head_idx++;
+ emsgs_head_idx %= ARRAY_SIZE(emsgs);
- spin_unlock_irqrestore(&emsgs_lock, flags);
+ spin_unlock_irqrestore(&emsgs_lock, flags);
- n = copy_to_user(buf, mp, len);
- kfree(mp);
- return n == 0 ? len : -EFAULT;
- default:
- return -EFAULT;
- }
+ n = copy_to_user(buf, mp, len);
+ kfree(mp);
+ return n == 0 ? len : -EFAULT;
}
static const struct file_operations aoe_fops = {
-/* Copyright (c) 2006 Coraid, Inc. See COPYING for GPL terms. */
+/* Copyright (c) 2007 Coraid, Inc. See COPYING for GPL terms. */
/*
* aoecmd.c
* Filesystem request handling methods
#include <linux/skbuff.h>
#include <linux/netdevice.h>
#include <linux/genhd.h>
+#include <linux/moduleparam.h>
#include <net/net_namespace.h>
#include <asm/unaligned.h>
#include "aoe.h"
-#define TIMERTICK (HZ / 10)
-#define MINTIMER (2 * TIMERTICK)
-#define MAXTIMER (HZ << 1)
-
static int aoe_deadsecs = 60 * 3;
module_param(aoe_deadsecs, int, 0644);
MODULE_PARM_DESC(aoe_deadsecs, "After aoe_deadsecs seconds, give up and fail dev.");
-struct sk_buff *
+static int aoe_maxout = 16;
+module_param(aoe_maxout, int, 0644);
+MODULE_PARM_DESC(aoe_maxout,
+ "Only aoe_maxout outstanding packets for every MAC on eX.Y.");
+
+static struct sk_buff *
new_skb(ulong len)
{
struct sk_buff *skb;
}
static struct frame *
-getframe(struct aoedev *d, int tag)
+getframe(struct aoetgt *t, int tag)
{
struct frame *f, *e;
- f = d->frames;
- e = f + d->nframes;
+ f = t->frames;
+ e = f + t->nframes;
for (; f<e; f++)
if (f->tag == tag)
return f;
* This driver reserves tag -1 to mean "unused frame."
*/
static int
-newtag(struct aoedev *d)
+newtag(struct aoetgt *t)
{
register ulong n;
n = jiffies & 0xffff;
- return n |= (++d->lasttag & 0x7fff) << 16;
+ return n |= (++t->lasttag & 0x7fff) << 16;
}
static int
-aoehdr_atainit(struct aoedev *d, struct aoe_hdr *h)
+aoehdr_atainit(struct aoedev *d, struct aoetgt *t, struct aoe_hdr *h)
{
- u32 host_tag = newtag(d);
+ u32 host_tag = newtag(t);
- memcpy(h->src, d->ifp->dev_addr, sizeof h->src);
- memcpy(h->dst, d->addr, sizeof h->dst);
+ memcpy(h->src, t->ifp->nd->dev_addr, sizeof h->src);
+ memcpy(h->dst, t->addr, sizeof h->dst);
h->type = __constant_cpu_to_be16(ETH_P_AOE);
h->verfl = AOE_HVER;
h->major = cpu_to_be16(d->aoemajor);
}
static void
-aoecmd_ata_rw(struct aoedev *d, struct frame *f)
+ifrotate(struct aoetgt *t)
+{
+ t->ifp++;
+ if (t->ifp >= &t->ifs[NAOEIFS] || t->ifp->nd == NULL)
+ t->ifp = t->ifs;
+ if (t->ifp->nd == NULL) {
+ printk(KERN_INFO "aoe: no interface to rotate to\n");
+ BUG();
+ }
+}
+
+static void
+skb_pool_put(struct aoedev *d, struct sk_buff *skb)
+{
+ if (!d->skbpool_hd)
+ d->skbpool_hd = skb;
+ else
+ d->skbpool_tl->next = skb;
+ d->skbpool_tl = skb;
+}
+
+static struct sk_buff *
+skb_pool_get(struct aoedev *d)
+{
+ struct sk_buff *skb;
+
+ skb = d->skbpool_hd;
+ if (skb && atomic_read(&skb_shinfo(skb)->dataref) == 1) {
+ d->skbpool_hd = skb->next;
+ skb->next = NULL;
+ return skb;
+ }
+ if (d->nskbpool < NSKBPOOLMAX
+ && (skb = new_skb(ETH_ZLEN))) {
+ d->nskbpool++;
+ return skb;
+ }
+ return NULL;
+}
+
+/* freeframe is where we do our load balancing so it's a little hairy. */
+static struct frame *
+freeframe(struct aoedev *d)
+{
+ struct frame *f, *e, *rf;
+ struct aoetgt **t;
+ struct sk_buff *skb;
+
+ if (d->targets[0] == NULL) { /* shouldn't happen, but I'm paranoid */
+ printk(KERN_ERR "aoe: NULL TARGETS!\n");
+ return NULL;
+ }
+ t = d->tgt;
+ t++;
+ if (t >= &d->targets[NTARGETS] || !*t)
+ t = d->targets;
+ for (;;) {
+ if ((*t)->nout < (*t)->maxout
+ && t != d->htgt
+ && (*t)->ifp->nd) {
+ rf = NULL;
+ f = (*t)->frames;
+ e = f + (*t)->nframes;
+ for (; f < e; f++) {
+ if (f->tag != FREETAG)
+ continue;
+ skb = f->skb;
+ if (!skb
+ && !(f->skb = skb = new_skb(ETH_ZLEN)))
+ continue;
+ if (atomic_read(&skb_shinfo(skb)->dataref)
+ != 1) {
+ if (!rf)
+ rf = f;
+ continue;
+ }
+gotone: skb_shinfo(skb)->nr_frags = skb->data_len = 0;
+ skb_trim(skb, 0);
+ d->tgt = t;
+ ifrotate(*t);
+ return f;
+ }
+ /* Work can be done, but the network layer is
+ holding our precious packets. Try to grab
+ one from the pool. */
+ f = rf;
+ if (f == NULL) { /* more paranoia */
+ printk(KERN_ERR
+ "aoe: freeframe: %s.\n",
+ "unexpected null rf");
+ d->flags |= DEVFL_KICKME;
+ return NULL;
+ }
+ skb = skb_pool_get(d);
+ if (skb) {
+ skb_pool_put(d, f->skb);
+ f->skb = skb;
+ goto gotone;
+ }
+ (*t)->dataref++;
+ if ((*t)->nout == 0)
+ d->flags |= DEVFL_KICKME;
+ }
+ if (t == d->tgt) /* we've looped and found nada */
+ break;
+ t++;
+ if (t >= &d->targets[NTARGETS] || !*t)
+ t = d->targets;
+ }
+ return NULL;
+}
+
+static int
+aoecmd_ata_rw(struct aoedev *d)
{
+ struct frame *f;
struct aoe_hdr *h;
struct aoe_atahdr *ah;
struct buf *buf;
+ struct bio_vec *bv;
+ struct aoetgt *t;
struct sk_buff *skb;
ulong bcnt;
- register sector_t sector;
char writebit, extbit;
writebit = 0x10;
extbit = 0x4;
+ f = freeframe(d);
+ if (f == NULL)
+ return 0;
+ t = *d->tgt;
buf = d->inprocess;
-
- sector = buf->sector;
- bcnt = buf->bv_resid;
- if (bcnt > d->maxbcnt)
- bcnt = d->maxbcnt;
-
+ bv = buf->bv;
+ bcnt = t->ifp->maxbcnt;
+ if (bcnt == 0)
+ bcnt = DEFAULTBCNT;
+ if (bcnt > buf->bv_resid)
+ bcnt = buf->bv_resid;
/* initialize the headers & frame */
skb = f->skb;
h = (struct aoe_hdr *) skb_mac_header(skb);
ah = (struct aoe_atahdr *) (h+1);
skb_put(skb, sizeof *h + sizeof *ah);
memset(h, 0, skb->len);
- f->tag = aoehdr_atainit(d, h);
+ f->tag = aoehdr_atainit(d, t, h);
+ t->nout++;
f->waited = 0;
f->buf = buf;
- f->bufaddr = buf->bufaddr;
+ f->bufaddr = page_address(bv->bv_page) + buf->bv_off;
f->bcnt = bcnt;
- f->lba = sector;
+ f->lba = buf->sector;
/* set up ata header */
ah->scnt = bcnt >> 9;
- put_lba(ah, sector);
+ put_lba(ah, buf->sector);
if (d->flags & DEVFL_EXT) {
ah->aflags |= AOEAFL_EXT;
} else {
ah->lba3 &= 0x0f;
ah->lba3 |= 0xe0; /* LBA bit + obsolete 0xa0 */
}
-
if (bio_data_dir(buf->bio) == WRITE) {
- skb_fill_page_desc(skb, 0, virt_to_page(f->bufaddr),
- offset_in_page(f->bufaddr), bcnt);
+ skb_fill_page_desc(skb, 0, bv->bv_page, buf->bv_off, bcnt);
ah->aflags |= AOEAFL_WRITE;
skb->len += bcnt;
skb->data_len = bcnt;
+ t->wpkts++;
} else {
+ t->rpkts++;
writebit = 0;
}
/* mark all tracking fields and load out */
buf->nframesout += 1;
- buf->bufaddr += bcnt;
+ buf->bv_off += bcnt;
buf->bv_resid -= bcnt;
-/* printk(KERN_DEBUG "aoe: bv_resid=%ld\n", buf->bv_resid); */
buf->resid -= bcnt;
buf->sector += bcnt >> 9;
if (buf->resid == 0) {
d->inprocess = NULL;
} else if (buf->bv_resid == 0) {
- buf->bv++;
- WARN_ON(buf->bv->bv_len == 0);
- buf->bv_resid = buf->bv->bv_len;
- buf->bufaddr = page_address(buf->bv->bv_page) + buf->bv->bv_offset;
+ buf->bv = ++bv;
+ buf->bv_resid = bv->bv_len;
+ WARN_ON(buf->bv_resid == 0);
+ buf->bv_off = bv->bv_offset;
}
- skb->dev = d->ifp;
+ skb->dev = t->ifp->nd;
skb = skb_clone(skb, GFP_ATOMIC);
- if (skb == NULL)
- return;
- if (d->sendq_hd)
- d->sendq_tl->next = skb;
- else
- d->sendq_hd = skb;
- d->sendq_tl = skb;
+ if (skb) {
+ if (d->sendq_hd)
+ d->sendq_tl->next = skb;
+ else
+ d->sendq_hd = skb;
+ d->sendq_tl = skb;
+ }
+ return 1;
}
/* some callers cannot sleep, and they can call this function,
return sl;
}
-static struct frame *
-freeframe(struct aoedev *d)
-{
- struct frame *f, *e;
- int n = 0;
-
- f = d->frames;
- e = f + d->nframes;
- for (; f<e; f++) {
- if (f->tag != FREETAG)
- continue;
- if (atomic_read(&skb_shinfo(f->skb)->dataref) == 1) {
- skb_shinfo(f->skb)->nr_frags = f->skb->data_len = 0;
- skb_trim(f->skb, 0);
- return f;
- }
- n++;
- }
- if (n == d->nframes) /* wait for network layer */
- d->flags |= DEVFL_KICKME;
-
- return NULL;
-}
-
-/* enters with d->lock held */
-void
-aoecmd_work(struct aoedev *d)
-{
- struct frame *f;
- struct buf *buf;
-
- if (d->flags & DEVFL_PAUSE) {
- if (!aoedev_isbusy(d))
- d->sendq_hd = aoecmd_cfg_pkts(d->aoemajor,
- d->aoeminor, &d->sendq_tl);
- return;
- }
-
-loop:
- f = freeframe(d);
- if (f == NULL)
- return;
- if (d->inprocess == NULL) {
- if (list_empty(&d->bufq))
- return;
- buf = container_of(d->bufq.next, struct buf, bufs);
- list_del(d->bufq.next);
-/*printk(KERN_DEBUG "aoe: bi_size=%ld\n", buf->bio->bi_size); */
- d->inprocess = buf;
- }
- aoecmd_ata_rw(d, f);
- goto loop;
-}
-
static void
-rexmit(struct aoedev *d, struct frame *f)
+resend(struct aoedev *d, struct aoetgt *t, struct frame *f)
{
struct sk_buff *skb;
struct aoe_hdr *h;
char buf[128];
u32 n;
- n = newtag(d);
+ ifrotate(t);
+ n = newtag(t);
+ skb = f->skb;
+ h = (struct aoe_hdr *) skb_mac_header(skb);
+ ah = (struct aoe_atahdr *) (h+1);
snprintf(buf, sizeof buf,
- "%15s e%ld.%ld oldtag=%08x@%08lx newtag=%08x\n",
- "retransmit",
- d->aoemajor, d->aoeminor, f->tag, jiffies, n);
+ "%15s e%ld.%d oldtag=%08x@%08lx newtag=%08x "
+ "s=%012llx d=%012llx nout=%d\n",
+ "retransmit", d->aoemajor, d->aoeminor, f->tag, jiffies, n,
+ mac_addr(h->src),
+ mac_addr(h->dst), t->nout);
aoechr_error(buf);
- skb = f->skb;
- h = (struct aoe_hdr *) skb_mac_header(skb);
- ah = (struct aoe_atahdr *) (h+1);
f->tag = n;
h->tag = cpu_to_be32(n);
- memcpy(h->dst, d->addr, sizeof h->dst);
- memcpy(h->src, d->ifp->dev_addr, sizeof h->src);
-
- n = DEFAULTBCNT / 512;
- if (ah->scnt > n) {
- ah->scnt = n;
+ memcpy(h->dst, t->addr, sizeof h->dst);
+ memcpy(h->src, t->ifp->nd->dev_addr, sizeof h->src);
+
+ switch (ah->cmdstat) {
+ default:
+ break;
+ case WIN_READ:
+ case WIN_READ_EXT:
+ case WIN_WRITE:
+ case WIN_WRITE_EXT:
+ put_lba(ah, f->lba);
+
+ n = f->bcnt;
+ if (n > DEFAULTBCNT)
+ n = DEFAULTBCNT;
+ ah->scnt = n >> 9;
if (ah->aflags & AOEAFL_WRITE) {
skb_fill_page_desc(skb, 0, virt_to_page(f->bufaddr),
- offset_in_page(f->bufaddr), DEFAULTBCNT);
- skb->len = sizeof *h + sizeof *ah + DEFAULTBCNT;
- skb->data_len = DEFAULTBCNT;
- }
- if (++d->lostjumbo > (d->nframes << 1))
- if (d->maxbcnt != DEFAULTBCNT) {
- printk(KERN_INFO "aoe: e%ld.%ld: too many lost jumbo on %s - using 1KB frames.\n",
- d->aoemajor, d->aoeminor, d->ifp->name);
- d->maxbcnt = DEFAULTBCNT;
- d->flags |= DEVFL_MAXBCNT;
+ offset_in_page(f->bufaddr), n);
+ skb->len = sizeof *h + sizeof *ah + n;
+ skb->data_len = n;
}
}
-
- skb->dev = d->ifp;
+ skb->dev = t->ifp->nd;
skb = skb_clone(skb, GFP_ATOMIC);
if (skb == NULL)
return;
return n;
}
+static struct aoeif *
+getif(struct aoetgt *t, struct net_device *nd)
+{
+ struct aoeif *p, *e;
+
+ p = t->ifs;
+ e = p + NAOEIFS;
+ for (; p < e; p++)
+ if (p->nd == nd)
+ return p;
+ return NULL;
+}
+
+static struct aoeif *
+addif(struct aoetgt *t, struct net_device *nd)
+{
+ struct aoeif *p;
+
+ p = getif(t, NULL);
+ if (!p)
+ return NULL;
+ p->nd = nd;
+ p->maxbcnt = DEFAULTBCNT;
+ p->lost = 0;
+ p->lostjumbo = 0;
+ return p;
+}
+
+static void
+ejectif(struct aoetgt *t, struct aoeif *ifp)
+{
+ struct aoeif *e;
+ ulong n;
+
+ e = t->ifs + NAOEIFS - 1;
+ n = (e - ifp) * sizeof *ifp;
+ memmove(ifp, ifp+1, n);
+ e->nd = NULL;
+}
+
+static int
+sthtith(struct aoedev *d)
+{
+ struct frame *f, *e, *nf;
+ struct sk_buff *skb;
+ struct aoetgt *ht = *d->htgt;
+
+ f = ht->frames;
+ e = f + ht->nframes;
+ for (; f < e; f++) {
+ if (f->tag == FREETAG)
+ continue;
+ nf = freeframe(d);
+ if (!nf)
+ return 0;
+ skb = nf->skb;
+ *nf = *f;
+ f->skb = skb;
+ f->tag = FREETAG;
+ nf->waited = 0;
+ ht->nout--;
+ (*d->tgt)->nout++;
+ resend(d, *d->tgt, nf);
+ }
+ /* he's clean, he's useless. take away his interfaces */
+ memset(ht->ifs, 0, sizeof ht->ifs);
+ d->htgt = NULL;
+ return 1;
+}
+
+static inline unsigned char
+ata_scnt(unsigned char *packet) {
+ struct aoe_hdr *h;
+ struct aoe_atahdr *ah;
+
+ h = (struct aoe_hdr *) packet;
+ ah = (struct aoe_atahdr *) (h+1);
+ return ah->scnt;
+}
+
static void
rexmit_timer(ulong vp)
{
struct aoedev *d;
+ struct aoetgt *t, **tt, **te;
+ struct aoeif *ifp;
struct frame *f, *e;
struct sk_buff *sl;
register long timeout;
spin_unlock_irqrestore(&d->lock, flags);
return;
}
- f = d->frames;
- e = f + d->nframes;
- for (; f<e; f++) {
- if (f->tag != FREETAG && tsince(f->tag) >= timeout) {
+ tt = d->targets;
+ te = tt + NTARGETS;
+ for (; tt < te && *tt; tt++) {
+ t = *tt;
+ f = t->frames;
+ e = f + t->nframes;
+ for (; f < e; f++) {
+ if (f->tag == FREETAG
+ || tsince(f->tag) < timeout)
+ continue;
n = f->waited += timeout;
n /= HZ;
- if (n > aoe_deadsecs) { /* waited too long for response */
+ if (n > aoe_deadsecs) {
+ /* waited too long. device failure. */
aoedev_downdev(d);
break;
}
- rexmit(d, f);
+
+ if (n > HELPWAIT /* see if another target can help */
+ && (tt != d->targets || d->targets[1]))
+ d->htgt = tt;
+
+ if (t->nout == t->maxout) {
+ if (t->maxout > 1)
+ t->maxout--;
+ t->lastwadj = jiffies;
+ }
+
+ ifp = getif(t, f->skb->dev);
+ if (ifp && ++ifp->lost > (t->nframes << 1)
+ && (ifp != t->ifs || t->ifs[1].nd)) {
+ ejectif(t, ifp);
+ ifp = NULL;
+ }
+
+ if (ata_scnt(skb_mac_header(f->skb)) > DEFAULTBCNT / 512
+ && ifp && ++ifp->lostjumbo > (t->nframes << 1)
+ && ifp->maxbcnt != DEFAULTBCNT) {
+ printk(KERN_INFO
+ "aoe: e%ld.%d: "
+ "too many lost jumbo on "
+ "%s:%012llx - "
+ "falling back to %d frames.\n",
+ d->aoemajor, d->aoeminor,
+ ifp->nd->name, mac_addr(t->addr),
+ DEFAULTBCNT);
+ ifp->maxbcnt = 0;
+ }
+ resend(d, t, f);
+ }
+
+ /* window check */
+ if (t->nout == t->maxout
+ && t->maxout < t->nframes
+ && (jiffies - t->lastwadj)/HZ > 10) {
+ t->maxout++;
+ t->lastwadj = jiffies;
}
}
- if (d->flags & DEVFL_KICKME) {
+
+ if (d->sendq_hd) {
+ n = d->rttavg <<= 1;
+ if (n > MAXTIMER)
+ d->rttavg = MAXTIMER;
+ }
+
+ if (d->flags & DEVFL_KICKME || d->htgt) {
d->flags &= ~DEVFL_KICKME;
aoecmd_work(d);
}
sl = d->sendq_hd;
d->sendq_hd = d->sendq_tl = NULL;
- if (sl) {
- n = d->rttavg <<= 1;
- if (n > MAXTIMER)
- d->rttavg = MAXTIMER;
- }
d->timer.expires = jiffies + TIMERTICK;
add_timer(&d->timer);
aoenet_xmit(sl);
}
+/* enters with d->lock held */
+void
+aoecmd_work(struct aoedev *d)
+{
+ struct buf *buf;
+loop:
+ if (d->htgt && !sthtith(d))
+ return;
+ if (d->inprocess == NULL) {
+ if (list_empty(&d->bufq))
+ return;
+ buf = container_of(d->bufq.next, struct buf, bufs);
+ list_del(d->bufq.next);
+ d->inprocess = buf;
+ }
+ if (aoecmd_ata_rw(d))
+ goto loop;
+}
+
/* this function performs work that has been deferred until sleeping is OK
*/
void
}
static void
-ataid_complete(struct aoedev *d, unsigned char *id)
+ataid_complete(struct aoedev *d, struct aoetgt *t, unsigned char *id)
{
u64 ssize;
u16 n;
}
if (d->ssize != ssize)
- printk(KERN_INFO "aoe: %012llx e%lu.%lu v%04x has %llu sectors\n",
- (unsigned long long)mac_addr(d->addr),
+ printk(KERN_INFO
+ "aoe: %012llx e%ld.%d v%04x has %llu sectors\n",
+ mac_addr(t->addr),
d->aoemajor, d->aoeminor,
d->fw_ver, (long long)ssize);
d->ssize = ssize;
d->geo.start = 0;
+ if (d->flags & (DEVFL_GDALLOC|DEVFL_NEWSIZE))
+ return;
if (d->gd != NULL) {
d->gd->capacity = ssize;
d->flags |= DEVFL_NEWSIZE;
- } else {
- if (d->flags & DEVFL_GDALLOC) {
- printk(KERN_ERR "aoe: can't schedule work for e%lu.%lu, %s\n",
- d->aoemajor, d->aoeminor,
- "it's already on! This shouldn't happen.\n");
- return;
- }
+ } else
d->flags |= DEVFL_GDALLOC;
- }
schedule_work(&d->work);
}
d->rttavg += n >> 2;
}
+static struct aoetgt *
+gettgt(struct aoedev *d, char *addr)
+{
+ struct aoetgt **t, **e;
+
+ t = d->targets;
+ e = t + NTARGETS;
+ for (; t < e && *t; t++)
+ if (memcmp((*t)->addr, addr, sizeof((*t)->addr)) == 0)
+ return *t;
+ return NULL;
+}
+
+static inline void
+diskstats(struct gendisk *disk, struct bio *bio, ulong duration, sector_t sector)
+{
+ unsigned long n_sect = bio->bi_size >> 9;
+ const int rw = bio_data_dir(bio);
+
+ all_stat_inc(disk, ios[rw], sector);
+ all_stat_add(disk, ticks[rw], duration, sector);
+ all_stat_add(disk, sectors[rw], n_sect, sector);
+ all_stat_add(disk, io_ticks, duration, sector);
+}
+
void
aoecmd_ata_rsp(struct sk_buff *skb)
{
struct frame *f;
struct buf *buf;
struct sk_buff *sl;
+ struct aoetgt *t;
+ struct aoeif *ifp;
register long n;
ulong flags;
char ebuf[128];
spin_lock_irqsave(&d->lock, flags);
n = be32_to_cpu(get_unaligned(&hin->tag));
- f = getframe(d, n);
+ t = gettgt(d, hin->src);
+ if (t == NULL) {
+ printk(KERN_INFO "aoe: can't find target e%ld.%d:%012llx\n",
+ d->aoemajor, d->aoeminor, mac_addr(hin->src));
+ spin_unlock_irqrestore(&d->lock, flags);
+ return;
+ }
+ f = getframe(t, n);
if (f == NULL) {
calc_rttavg(d, -tsince(n));
spin_unlock_irqrestore(&d->lock, flags);
ahout = (struct aoe_atahdr *) (hout+1);
buf = f->buf;
- if (ahout->cmdstat == WIN_IDENTIFY)
- d->flags &= ~DEVFL_PAUSE;
if (ahin->cmdstat & 0xa9) { /* these bits cleared on success */
printk(KERN_ERR
- "aoe: ata error cmd=%2.2Xh stat=%2.2Xh from e%ld.%ld\n",
+ "aoe: ata error cmd=%2.2Xh stat=%2.2Xh from e%ld.%d\n",
ahout->cmdstat, ahin->cmdstat,
d->aoemajor, d->aoeminor);
if (buf)
buf->flags |= BUFFL_FAIL;
} else {
+ if (d->htgt && t == *d->htgt) /* I'll help myself, thank you. */
+ d->htgt = NULL;
n = ahout->scnt << 9;
switch (ahout->cmdstat) {
case WIN_READ:
case WIN_READ_EXT:
if (skb->len - sizeof *hin - sizeof *ahin < n) {
printk(KERN_ERR
- "aoe: runt data size in read. skb->len=%d\n",
- skb->len);
+ "aoe: %s. skb->len=%d need=%ld\n",
+ "runt data size in read", skb->len, n);
/* fail frame f? just returning will rexmit. */
spin_unlock_irqrestore(&d->lock, flags);
return;
memcpy(f->bufaddr, ahin+1, n);
case WIN_WRITE:
case WIN_WRITE_EXT:
+ ifp = getif(t, skb->dev);
+ if (ifp) {
+ ifp->lost = 0;
+ if (n > DEFAULTBCNT)
+ ifp->lostjumbo = 0;
+ }
if (f->bcnt -= n) {
- skb = f->skb;
+ f->lba += n >> 9;
f->bufaddr += n;
- put_lba(ahout, f->lba += ahout->scnt);
- n = f->bcnt;
- if (n > DEFAULTBCNT)
- n = DEFAULTBCNT;
- ahout->scnt = n >> 9;
- if (ahout->aflags & AOEAFL_WRITE) {
- skb_fill_page_desc(skb, 0,
- virt_to_page(f->bufaddr),
- offset_in_page(f->bufaddr), n);
- skb->len = sizeof *hout + sizeof *ahout + n;
- skb->data_len = n;
- }
- f->tag = newtag(d);
- hout->tag = cpu_to_be32(f->tag);
- skb->dev = d->ifp;
- skb = skb_clone(skb, GFP_ATOMIC);
- spin_unlock_irqrestore(&d->lock, flags);
- if (skb)
- aoenet_xmit(skb);
- return;
+ resend(d, t, f);
+ goto xmit;
}
- if (n > DEFAULTBCNT)
- d->lostjumbo = 0;
break;
case WIN_IDENTIFY:
if (skb->len - sizeof *hin - sizeof *ahin < 512) {
spin_unlock_irqrestore(&d->lock, flags);
return;
}
- ataid_complete(d, (char *) (ahin+1));
+ ataid_complete(d, t, (char *) (ahin+1));
break;
default:
printk(KERN_INFO
}
}
- if (buf) {
- buf->nframesout -= 1;
- if (buf->nframesout == 0 && buf->resid == 0) {
- unsigned long duration = jiffies - buf->start_time;
- unsigned long n_sect = buf->bio->bi_size >> 9;
- struct gendisk *disk = d->gd;
- const int rw = bio_data_dir(buf->bio);
-
- disk_stat_inc(disk, ios[rw]);
- disk_stat_add(disk, ticks[rw], duration);
- disk_stat_add(disk, sectors[rw], n_sect);
- disk_stat_add(disk, io_ticks, duration);
- n = (buf->flags & BUFFL_FAIL) ? -EIO : 0;
- bio_endio(buf->bio, n);
- mempool_free(buf, d->bufpool);
- }
+ if (buf && --buf->nframesout == 0 && buf->resid == 0) {
+ diskstats(d->gd, buf->bio, jiffies - buf->stime, buf->sector);
+ n = (buf->flags & BUFFL_FAIL) ? -EIO : 0;
+ bio_endio(buf->bio, n);
+ mempool_free(buf, d->bufpool);
}
f->buf = NULL;
f->tag = FREETAG;
+ t->nout--;
aoecmd_work(d);
+xmit:
sl = d->sendq_hd;
d->sendq_hd = d->sendq_tl = NULL;
aoenet_xmit(sl);
}
-/*
- * Since we only call this in one place (and it only prepares one frame)
- * we just return the skb. Usually we'd chain it up to the aoedev sendq.
- */
-static struct sk_buff *
+struct sk_buff *
aoecmd_ata_id(struct aoedev *d)
{
struct aoe_hdr *h;
struct aoe_atahdr *ah;
struct frame *f;
struct sk_buff *skb;
+ struct aoetgt *t;
f = freeframe(d);
- if (f == NULL) {
- printk(KERN_ERR "aoe: can't get a frame. This shouldn't happen.\n");
+ if (f == NULL)
return NULL;
- }
+
+ t = *d->tgt;
/* initialize the headers & frame */
skb = f->skb;
ah = (struct aoe_atahdr *) (h+1);
skb_put(skb, sizeof *h + sizeof *ah);
memset(h, 0, skb->len);
- f->tag = aoehdr_atainit(d, h);
+ f->tag = aoehdr_atainit(d, t, h);
+ t->nout++;
f->waited = 0;
/* set up ata header */
ah->cmdstat = WIN_IDENTIFY;
ah->lba3 = 0xa0;
- skb->dev = d->ifp;
+ skb->dev = t->ifp->nd;
d->rttavg = MAXTIMER;
d->timer.function = rexmit_timer;
return skb_clone(skb, GFP_ATOMIC);
}
+static struct aoetgt *
+addtgt(struct aoedev *d, char *addr, ulong nframes)
+{
+ struct aoetgt *t, **tt, **te;
+ struct frame *f, *e;
+
+ tt = d->targets;
+ te = tt + NTARGETS;
+ for (; tt < te && *tt; tt++)
+ ;
+
+ if (tt == te) {
+ printk(KERN_INFO
+ "aoe: device addtgt failure; too many targets\n");
+ return NULL;
+ }
+ t = kcalloc(1, sizeof *t, GFP_ATOMIC);
+ f = kcalloc(nframes, sizeof *f, GFP_ATOMIC);
+ if (!t || !f) {
+ kfree(f);
+ kfree(t);
+ printk(KERN_INFO "aoe: cannot allocate memory to add target\n");
+ return NULL;
+ }
+
+ t->nframes = nframes;
+ t->frames = f;
+ e = f + nframes;
+ for (; f < e; f++)
+ f->tag = FREETAG;
+ memcpy(t->addr, addr, sizeof t->addr);
+ t->ifp = t->ifs;
+ t->maxout = t->nframes;
+ return *tt = t;
+}
+
void
aoecmd_cfg_rsp(struct sk_buff *skb)
{
struct aoedev *d;
struct aoe_hdr *h;
struct aoe_cfghdr *ch;
+ struct aoetgt *t;
+ struct aoeif *ifp;
ulong flags, sysminor, aoemajor;
struct sk_buff *sl;
- enum { MAXFRAMES = 16 };
u16 n;
h = (struct aoe_hdr *) skb_mac_header(skb);
}
n = be16_to_cpu(ch->bufcnt);
- if (n > MAXFRAMES) /* keep it reasonable */
- n = MAXFRAMES;
+ if (n > aoe_maxout) /* keep it reasonable */
+ n = aoe_maxout;
- d = aoedev_by_sysminor_m(sysminor, n);
+ d = aoedev_by_sysminor_m(sysminor);
if (d == NULL) {
printk(KERN_INFO "aoe: device sysminor_m failure\n");
return;
spin_lock_irqsave(&d->lock, flags);
- /* permit device to migrate mac and network interface */
- d->ifp = skb->dev;
- memcpy(d->addr, h->src, sizeof d->addr);
- if (!(d->flags & DEVFL_MAXBCNT)) {
- n = d->ifp->mtu;
+ t = gettgt(d, h->src);
+ if (!t) {
+ t = addtgt(d, h->src, n);
+ if (!t) {
+ spin_unlock_irqrestore(&d->lock, flags);
+ return;
+ }
+ }
+ ifp = getif(t, skb->dev);
+ if (!ifp) {
+ ifp = addif(t, skb->dev);
+ if (!ifp) {
+ printk(KERN_INFO
+ "aoe: device addif failure; "
+ "too many interfaces?\n");
+ spin_unlock_irqrestore(&d->lock, flags);
+ return;
+ }
+ }
+ if (ifp->maxbcnt) {
+ n = ifp->nd->mtu;
n -= sizeof (struct aoe_hdr) + sizeof (struct aoe_atahdr);
n /= 512;
if (n > ch->scnt)
n = ch->scnt;
n = n ? n * 512 : DEFAULTBCNT;
- if (n != d->maxbcnt) {
+ if (n != ifp->maxbcnt) {
printk(KERN_INFO
- "aoe: e%ld.%ld: setting %d byte data frames on %s\n",
- d->aoemajor, d->aoeminor, n, d->ifp->name);
- d->maxbcnt = n;
+ "aoe: e%ld.%d: setting %d%s%s:%012llx\n",
+ d->aoemajor, d->aoeminor, n,
+ " byte data frames on ", ifp->nd->name,
+ mac_addr(t->addr));
+ ifp->maxbcnt = n;
}
}
/* don't change users' perspective */
- if (d->nopen && !(d->flags & DEVFL_PAUSE)) {
+ if (d->nopen) {
spin_unlock_irqrestore(&d->lock, flags);
return;
}
- d->flags |= DEVFL_PAUSE; /* force pause */
- d->mintimer = MINTIMER;
d->fw_ver = be16_to_cpu(ch->fwver);
- /* check for already outstanding ataid */
- sl = aoedev_isbusy(d) == 0 ? aoecmd_ata_id(d) : NULL;
+ sl = aoecmd_ata_id(d);
spin_unlock_irqrestore(&d->lock, flags);
aoenet_xmit(sl);
}
+void
+aoecmd_cleanslate(struct aoedev *d)
+{
+ struct aoetgt **t, **te;
+ struct aoeif *p, *e;
+
+ d->mintimer = MINTIMER;
+
+ t = d->targets;
+ te = t + NTARGETS;
+ for (; t < te && *t; t++) {
+ (*t)->maxout = (*t)->nframes;
+ p = (*t)->ifs;
+ e = p + NAOEIFS;
+ for (; p < e; p++) {
+ p->lostjumbo = 0;
+ p->lost = 0;
+ p->maxbcnt = DEFAULTBCNT;
+ }
+ }
+}
-/* Copyright (c) 2006 Coraid, Inc. See COPYING for GPL terms. */
+/* Copyright (c) 2007 Coraid, Inc. See COPYING for GPL terms. */
/*
* aoedev.c
* AoE device utility functions; maintains device list.
#include <linux/hdreg.h>
#include <linux/blkdev.h>
#include <linux/netdevice.h>
+#include <linux/delay.h>
#include "aoe.h"
+static void dummy_timer(ulong);
+static void aoedev_freedev(struct aoedev *);
+static void freetgt(struct aoedev *d, struct aoetgt *t);
+static void skbpoolfree(struct aoedev *d);
+
static struct aoedev *devlist;
-static spinlock_t devlist_lock;
+static DEFINE_SPINLOCK(devlist_lock);
int
aoedev_isbusy(struct aoedev *d)
{
+ struct aoetgt **t, **te;
struct frame *f, *e;
- f = d->frames;
- e = f + d->nframes;
- do {
- if (f->tag != FREETAG)
- return 1;
- } while (++f < e);
-
+ t = d->targets;
+ te = t + NTARGETS;
+ for (; t < te && *t; t++) {
+ f = (*t)->frames;
+ e = f + (*t)->nframes;
+ for (; f < e; f++)
+ if (f->tag != FREETAG)
+ return 1;
+ }
return 0;
}
add_timer(&d->timer);
}
-/* called with devlist lock held */
-static struct aoedev *
-aoedev_newdev(ulong nframes)
-{
- struct aoedev *d;
- struct frame *f, *e;
-
- d = kzalloc(sizeof *d, GFP_ATOMIC);
- f = kcalloc(nframes, sizeof *f, GFP_ATOMIC);
- switch (!d || !f) {
- case 0:
- d->nframes = nframes;
- d->frames = f;
- e = f + nframes;
- for (; f<e; f++) {
- f->tag = FREETAG;
- f->skb = new_skb(ETH_ZLEN);
- if (!f->skb)
- break;
- }
- if (f == e)
- break;
- while (f > d->frames) {
- f--;
- dev_kfree_skb(f->skb);
- }
- default:
- if (f)
- kfree(f);
- if (d)
- kfree(d);
- return NULL;
- }
- INIT_WORK(&d->work, aoecmd_sleepwork);
- spin_lock_init(&d->lock);
- init_timer(&d->timer);
- d->timer.data = (ulong) d;
- d->timer.function = dummy_timer;
- d->timer.expires = jiffies + HZ;
- add_timer(&d->timer);
- d->bufpool = NULL; /* defer to aoeblk_gdalloc */
- INIT_LIST_HEAD(&d->bufq);
- d->next = devlist;
- devlist = d;
-
- return d;
-}
-
void
aoedev_downdev(struct aoedev *d)
{
+ struct aoetgt **t, **te;
struct frame *f, *e;
struct buf *buf;
struct bio *bio;
- f = d->frames;
- e = f + d->nframes;
- for (; f<e; f->tag = FREETAG, f->buf = NULL, f++) {
- if (f->tag == FREETAG || f->buf == NULL)
- continue;
- buf = f->buf;
- bio = buf->bio;
- if (--buf->nframesout == 0) {
- mempool_free(buf, d->bufpool);
- bio_endio(bio, -EIO);
+ t = d->targets;
+ te = t + NTARGETS;
+ for (; t < te && *t; t++) {
+ f = (*t)->frames;
+ e = f + (*t)->nframes;
+ for (; f < e; f->tag = FREETAG, f->buf = NULL, f++) {
+ if (f->tag == FREETAG || f->buf == NULL)
+ continue;
+ buf = f->buf;
+ bio = buf->bio;
+ if (--buf->nframesout == 0
+ && buf != d->inprocess) {
+ mempool_free(buf, d->bufpool);
+ bio_endio(bio, -EIO);
+ }
}
- skb_shinfo(f->skb)->nr_frags = f->skb->data_len = 0;
+ (*t)->maxout = (*t)->nframes;
+ (*t)->nout = 0;
+ }
+ buf = d->inprocess;
+ if (buf) {
+ bio = buf->bio;
+ mempool_free(buf, d->bufpool);
+ bio_endio(bio, -EIO);
}
d->inprocess = NULL;
+ d->htgt = NULL;
while (!list_empty(&d->bufq)) {
buf = container_of(d->bufq.next, struct buf, bufs);
if (d->gd)
d->gd->capacity = 0;
- d->flags &= ~(DEVFL_UP | DEVFL_PAUSE);
+ d->flags &= ~DEVFL_UP;
+}
+
+static void
+aoedev_freedev(struct aoedev *d)
+{
+ struct aoetgt **t, **e;
+
+ if (d->gd) {
+ aoedisk_rm_sysfs(d);
+ del_gendisk(d->gd);
+ put_disk(d->gd);
+ }
+ t = d->targets;
+ e = t + NTARGETS;
+ for (; t < e && *t; t++)
+ freetgt(d, *t);
+ if (d->bufpool)
+ mempool_destroy(d->bufpool);
+ skbpoolfree(d);
+ kfree(d);
+}
+
+int
+aoedev_flush(const char __user *str, size_t cnt)
+{
+ ulong flags;
+ struct aoedev *d, **dd;
+ struct aoedev *rmd = NULL;
+ char buf[16];
+ int all = 0;
+
+ if (cnt >= 3) {
+ if (cnt > sizeof buf)
+ cnt = sizeof buf;
+ if (copy_from_user(buf, str, cnt))
+ return -EFAULT;
+ all = !strncmp(buf, "all", 3);
+ }
+
+ flush_scheduled_work();
+ spin_lock_irqsave(&devlist_lock, flags);
+ dd = &devlist;
+ while ((d = *dd)) {
+ spin_lock(&d->lock);
+ if ((!all && (d->flags & DEVFL_UP))
+ || (d->flags & (DEVFL_GDALLOC|DEVFL_NEWSIZE))
+ || d->nopen) {
+ spin_unlock(&d->lock);
+ dd = &d->next;
+ continue;
+ }
+ *dd = d->next;
+ aoedev_downdev(d);
+ d->flags |= DEVFL_TKILL;
+ spin_unlock(&d->lock);
+ d->next = rmd;
+ rmd = d;
+ }
+ spin_unlock_irqrestore(&devlist_lock, flags);
+ while ((d = rmd)) {
+ rmd = d->next;
+ del_timer_sync(&d->timer);
+ aoedev_freedev(d); /* must be able to sleep */
+ }
+ return 0;
+}
+
+/* I'm not really sure that this is a realistic problem, but if the
+network driver goes gonzo let's just leak memory after complaining. */
+static void
+skbfree(struct sk_buff *skb)
+{
+ enum { Sms = 100, Tms = 3*1000};
+ int i = Tms / Sms;
+
+ if (skb == NULL)
+ return;
+ while (atomic_read(&skb_shinfo(skb)->dataref) != 1 && i-- > 0)
+ msleep(Sms);
+ if (i <= 0) {
+ printk(KERN_ERR
+ "aoe: %s holds ref: %s\n",
+ skb->dev ? skb->dev->name : "netif",
+ "cannot free skb -- memory leaked.");
+ return;
+ }
+ skb_shinfo(skb)->nr_frags = skb->data_len = 0;
+ skb_trim(skb, 0);
+ dev_kfree_skb(skb);
+}
+
+static void
+skbpoolfree(struct aoedev *d)
+{
+ struct sk_buff *skb;
+
+ while ((skb = d->skbpool_hd)) {
+ d->skbpool_hd = skb->next;
+ skb->next = NULL;
+ skbfree(skb);
+ }
+ d->skbpool_tl = NULL;
}
/* find it or malloc it */
struct aoedev *
-aoedev_by_sysminor_m(ulong sysminor, ulong bufcnt)
+aoedev_by_sysminor_m(ulong sysminor)
{
struct aoedev *d;
ulong flags;
for (d=devlist; d; d=d->next)
if (d->sysminor == sysminor)
break;
-
- if (d == NULL) {
- d = aoedev_newdev(bufcnt);
- if (d == NULL) {
- spin_unlock_irqrestore(&devlist_lock, flags);
- printk(KERN_INFO "aoe: aoedev_newdev failure.\n");
- return NULL;
- }
- d->sysminor = sysminor;
- d->aoemajor = AOEMAJOR(sysminor);
- d->aoeminor = AOEMINOR(sysminor);
- }
-
+ if (d)
+ goto out;
+ d = kcalloc(1, sizeof *d, GFP_ATOMIC);
+ if (!d)
+ goto out;
+ INIT_WORK(&d->work, aoecmd_sleepwork);
+ spin_lock_init(&d->lock);
+ init_timer(&d->timer);
+ d->timer.data = (ulong) d;
+ d->timer.function = dummy_timer;
+ d->timer.expires = jiffies + HZ;
+ add_timer(&d->timer);
+ d->bufpool = NULL; /* defer to aoeblk_gdalloc */
+ d->tgt = d->targets;
+ INIT_LIST_HEAD(&d->bufq);
+ d->sysminor = sysminor;
+ d->aoemajor = AOEMAJOR(sysminor);
+ d->aoeminor = AOEMINOR(sysminor);
+ d->mintimer = MINTIMER;
+ d->next = devlist;
+ devlist = d;
+ out:
spin_unlock_irqrestore(&devlist_lock, flags);
return d;
}
static void
-aoedev_freedev(struct aoedev *d)
+freetgt(struct aoedev *d, struct aoetgt *t)
{
struct frame *f, *e;
- if (d->gd) {
- aoedisk_rm_sysfs(d);
- del_gendisk(d->gd);
- put_disk(d->gd);
- }
- f = d->frames;
- e = f + d->nframes;
- for (; f<e; f++) {
- skb_shinfo(f->skb)->nr_frags = 0;
- dev_kfree_skb(f->skb);
- }
- kfree(d->frames);
- if (d->bufpool)
- mempool_destroy(d->bufpool);
- kfree(d);
+ f = t->frames;
+ e = f + t->nframes;
+ for (; f < e; f++)
+ skbfree(f->skb);
+ kfree(t->frames);
+ kfree(t);
}
void
int __init
aoedev_init(void)
{
- spin_lock_init(&devlist_lock);
return 0;
}
-
-/* Copyright (c) 2006 Coraid, Inc. See COPYING for GPL terms. */
+/* Copyright (c) 2007 Coraid, Inc. See COPYING for GPL terms. */
/*
* aoemain.c
* Module initialization routines, discover timer
-/* Copyright (c) 2006 Coraid, Inc. See COPYING for GPL terms. */
+/* Copyright (c) 2007 Coraid, Inc. See COPYING for GPL terms. */
/*
* aoenet.c
* Ethernet portion of AoE driver
return 0;
}
-u64
+unsigned long long
mac_addr(char addr[6])
{
__be64 n = 0;
memcpy(p + 2, addr, 6); /* (sizeof addr != 6) */
- return __be64_to_cpu(n);
+ return (unsigned long long) __be64_to_cpu(n);
}
void
if (n > NECODES)
n = 0;
if (net_ratelimit())
- printk(KERN_ERR "aoe: error packet from %d.%d; ecode=%d '%s'\n",
- be16_to_cpu(get_unaligned(&h->major)), h->minor,
- h->err, aoe_errlist[n]);
+ printk(KERN_ERR
+ "%s%d.%d@%s; ecode=%d '%s'\n",
+ "aoe: error packet from ",
+ be16_to_cpu(get_unaligned(&h->major)),
+ h->minor, skb->dev->name,
+ h->err, aoe_errlist[n]);
goto exit;
}
--- /dev/null
+/*
+ * Ram backed block device driver.
+ *
+ * Copyright (C) 2007 Nick Piggin
+ * Copyright (C) 2007 Novell Inc.
+ *
+ * Parts derived from drivers/block/rd.c, and drivers/block/loop.c, copyright
+ * of their respective owners.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/major.h>
+#include <linux/blkdev.h>
+#include <linux/bio.h>
+#include <linux/highmem.h>
+#include <linux/gfp.h>
+#include <linux/radix-tree.h>
+#include <linux/buffer_head.h> /* invalidate_bh_lrus() */
+
+#include <asm/uaccess.h>
+
+#define SECTOR_SHIFT 9
+#define PAGE_SECTORS_SHIFT (PAGE_SHIFT - SECTOR_SHIFT)
+#define PAGE_SECTORS (1 << PAGE_SECTORS_SHIFT)
+
+/*
+ * Each block ramdisk device has a radix_tree brd_pages of pages that stores
+ * the pages containing the block device's contents. A brd page's ->index is
+ * its offset in PAGE_SIZE units. This is similar to, but in no way connected
+ * with, the kernel's pagecache or buffer cache (which sit above our block
+ * device).
+ */
+struct brd_device {
+ int brd_number;
+ int brd_refcnt;
+ loff_t brd_offset;
+ loff_t brd_sizelimit;
+ unsigned brd_blocksize;
+
+ struct request_queue *brd_queue;
+ struct gendisk *brd_disk;
+ struct list_head brd_list;
+
+ /*
+ * Backing store of pages and lock to protect it. This is the contents
+ * of the block device.
+ */
+ spinlock_t brd_lock;
+ struct radix_tree_root brd_pages;
+};
+
+/*
+ * Look up and return a brd's page for a given sector.
+ */
+static struct page *brd_lookup_page(struct brd_device *brd, sector_t sector)
+{
+ pgoff_t idx;
+ struct page *page;
+
+ /*
+ * The page lifetime is protected by the fact that we have opened the
+ * device node -- brd pages will never be deleted under us, so we
+ * don't need any further locking or refcounting.
+ *
+ * This is strictly true for the radix-tree nodes as well (ie. we
+ * don't actually need the rcu_read_lock()), however that is not a
+ * documented feature of the radix-tree API so it is better to be
+ * safe here (we don't have total exclusion from radix tree updates
+ * here, only deletes).
+ */
+ rcu_read_lock();
+ idx = sector >> PAGE_SECTORS_SHIFT; /* sector to page index */
+ page = radix_tree_lookup(&brd->brd_pages, idx);
+ rcu_read_unlock();
+
+ BUG_ON(page && page->index != idx);
+
+ return page;
+}
+
+/*
+ * Look up and return a brd's page for a given sector.
+ * If one does not exist, allocate an empty page, and insert that. Then
+ * return it.
+ */
+static struct page *brd_insert_page(struct brd_device *brd, sector_t sector)
+{
+ pgoff_t idx;
+ struct page *page;
+ gfp_t gfp_flags;
+
+ page = brd_lookup_page(brd, sector);
+ if (page)
+ return page;
+
+ /*
+ * Must use NOIO because we don't want to recurse back into the
+ * block or filesystem layers from page reclaim.
+ *
+ * Cannot support XIP and highmem, because our ->direct_access
+ * routine for XIP must return memory that is always addressable.
+ * If XIP was reworked to use pfns and kmap throughout, this
+ * restriction might be able to be lifted.
+ */
+ gfp_flags = GFP_NOIO | __GFP_ZERO;
+#ifndef CONFIG_BLK_DEV_XIP
+ gfp_flags |= __GFP_HIGHMEM;
+#endif
+ page = alloc_page(GFP_NOIO | __GFP_HIGHMEM | __GFP_ZERO);
+ if (!page)
+ return NULL;
+
+ if (radix_tree_preload(GFP_NOIO)) {
+ __free_page(page);
+ return NULL;
+ }
+
+ spin_lock(&brd->brd_lock);
+ idx = sector >> PAGE_SECTORS_SHIFT;
+ if (radix_tree_insert(&brd->brd_pages, idx, page)) {
+ __free_page(page);
+ page = radix_tree_lookup(&brd->brd_pages, idx);
+ BUG_ON(!page);
+ BUG_ON(page->index != idx);
+ } else
+ page->index = idx;
+ spin_unlock(&brd->brd_lock);
+
+ radix_tree_preload_end();
+
+ return page;
+}
+
+/*
+ * Free all backing store pages and radix tree. This must only be called when
+ * there are no other users of the device.
+ */
+#define FREE_BATCH 16
+static void brd_free_pages(struct brd_device *brd)
+{
+ unsigned long pos = 0;
+ struct page *pages[FREE_BATCH];
+ int nr_pages;
+
+ do {
+ int i;
+
+ nr_pages = radix_tree_gang_lookup(&brd->brd_pages,
+ (void **)pages, pos, FREE_BATCH);
+
+ for (i = 0; i < nr_pages; i++) {
+ void *ret;
+
+ BUG_ON(pages[i]->index < pos);
+ pos = pages[i]->index;
+ ret = radix_tree_delete(&brd->brd_pages, pos);
+ BUG_ON(!ret || ret != pages[i]);
+ __free_page(pages[i]);
+ }
+
+ pos++;
+
+ /*
+ * This assumes radix_tree_gang_lookup always returns as
+ * many pages as possible. If the radix-tree code changes,
+ * so will this have to.
+ */
+ } while (nr_pages == FREE_BATCH);
+}
+
+/*
+ * copy_to_brd_setup must be called before copy_to_brd. It may sleep.
+ */
+static int copy_to_brd_setup(struct brd_device *brd, sector_t sector, size_t n)
+{
+ unsigned int offset = (sector & (PAGE_SECTORS-1)) << SECTOR_SHIFT;
+ size_t copy;
+
+ copy = min_t(size_t, n, PAGE_SIZE - offset);
+ if (!brd_insert_page(brd, sector))
+ return -ENOMEM;
+ if (copy < n) {
+ sector += copy >> SECTOR_SHIFT;
+ if (!brd_insert_page(brd, sector))
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+/*
+ * Copy n bytes from src to the brd starting at sector. Does not sleep.
+ */
+static void copy_to_brd(struct brd_device *brd, const void *src,
+ sector_t sector, size_t n)
+{
+ struct page *page;
+ void *dst;
+ unsigned int offset = (sector & (PAGE_SECTORS-1)) << SECTOR_SHIFT;
+ size_t copy;
+
+ copy = min_t(size_t, n, PAGE_SIZE - offset);
+ page = brd_lookup_page(brd, sector);
+ BUG_ON(!page);
+
+ dst = kmap_atomic(page, KM_USER1);
+ memcpy(dst + offset, src, copy);
+ kunmap_atomic(dst, KM_USER1);
+
+ if (copy < n) {
+ src += copy;
+ sector += copy >> SECTOR_SHIFT;
+ copy = n - copy;
+ page = brd_lookup_page(brd, sector);
+ BUG_ON(!page);
+
+ dst = kmap_atomic(page, KM_USER1);
+ memcpy(dst, src, copy);
+ kunmap_atomic(dst, KM_USER1);
+ }
+}
+
+/*
+ * Copy n bytes to dst from the brd starting at sector. Does not sleep.
+ */
+static void copy_from_brd(void *dst, struct brd_device *brd,
+ sector_t sector, size_t n)
+{
+ struct page *page;
+ void *src;
+ unsigned int offset = (sector & (PAGE_SECTORS-1)) << SECTOR_SHIFT;
+ size_t copy;
+
+ copy = min_t(size_t, n, PAGE_SIZE - offset);
+ page = brd_lookup_page(brd, sector);
+ if (page) {
+ src = kmap_atomic(page, KM_USER1);
+ memcpy(dst, src + offset, copy);
+ kunmap_atomic(src, KM_USER1);
+ } else
+ memset(dst, 0, copy);
+
+ if (copy < n) {
+ dst += copy;
+ sector += copy >> SECTOR_SHIFT;
+ copy = n - copy;
+ page = brd_lookup_page(brd, sector);
+ if (page) {
+ src = kmap_atomic(page, KM_USER1);
+ memcpy(dst, src, copy);
+ kunmap_atomic(src, KM_USER1);
+ } else
+ memset(dst, 0, copy);
+ }
+}
+
+/*
+ * Process a single bvec of a bio.
+ */
+static int brd_do_bvec(struct brd_device *brd, struct page *page,
+ unsigned int len, unsigned int off, int rw,
+ sector_t sector)
+{
+ void *mem;
+ int err = 0;
+
+ if (rw != READ) {
+ err = copy_to_brd_setup(brd, sector, len);
+ if (err)
+ goto out;
+ }
+
+ mem = kmap_atomic(page, KM_USER0);
+ if (rw == READ) {
+ copy_from_brd(mem + off, brd, sector, len);
+ flush_dcache_page(page);
+ } else
+ copy_to_brd(brd, mem + off, sector, len);
+ kunmap_atomic(mem, KM_USER0);
+
+out:
+ return err;
+}
+
+static int brd_make_request(struct request_queue *q, struct bio *bio)
+{
+ struct block_device *bdev = bio->bi_bdev;
+ struct brd_device *brd = bdev->bd_disk->private_data;
+ int rw;
+ struct bio_vec *bvec;
+ sector_t sector;
+ int i;
+ int err = -EIO;
+
+ sector = bio->bi_sector;
+ if (sector + (bio->bi_size >> SECTOR_SHIFT) >
+ get_capacity(bdev->bd_disk))
+ goto out;
+
+ rw = bio_rw(bio);
+ if (rw == READA)
+ rw = READ;
+
+ bio_for_each_segment(bvec, bio, i) {
+ unsigned int len = bvec->bv_len;
+ err = brd_do_bvec(brd, bvec->bv_page, len,
+ bvec->bv_offset, rw, sector);
+ if (err)
+ break;
+ sector += len >> SECTOR_SHIFT;
+ }
+
+out:
+ bio_endio(bio, err);
+
+ return 0;
+}
+
+#ifdef CONFIG_BLK_DEV_XIP
+static int brd_direct_access (struct block_device *bdev, sector_t sector,
+ unsigned long *data)
+{
+ struct brd_device *brd = bdev->bd_disk->private_data;
+ struct page *page;
+
+ if (!brd)
+ return -ENODEV;
+ if (sector & (PAGE_SECTORS-1))
+ return -EINVAL;
+ if (sector + PAGE_SECTORS > get_capacity(bdev->bd_disk))
+ return -ERANGE;
+ page = brd_insert_page(brd, sector);
+ if (!page)
+ return -ENOMEM;
+ *data = (unsigned long)page_address(page);
+
+ return 0;
+}
+#endif
+
+static int brd_ioctl(struct inode *inode, struct file *file,
+ unsigned int cmd, unsigned long arg)
+{
+ int error;
+ struct block_device *bdev = inode->i_bdev;
+ struct brd_device *brd = bdev->bd_disk->private_data;
+
+ if (cmd != BLKFLSBUF)
+ return -ENOTTY;
+
+ /*
+ * ram device BLKFLSBUF has special semantics, we want to actually
+ * release and destroy the ramdisk data.
+ */
+ mutex_lock(&bdev->bd_mutex);
+ error = -EBUSY;
+ if (bdev->bd_openers <= 1) {
+ /*
+ * Invalidate the cache first, so it isn't written
+ * back to the device.
+ *
+ * Another thread might instantiate more buffercache here,
+ * but there is not much we can do to close that race.
+ */
+ invalidate_bh_lrus();
+ truncate_inode_pages(bdev->bd_inode->i_mapping, 0);
+ brd_free_pages(brd);
+ error = 0;
+ }
+ mutex_unlock(&bdev->bd_mutex);
+
+ return error;
+}
+
+static struct block_device_operations brd_fops = {
+ .owner = THIS_MODULE,
+ .ioctl = brd_ioctl,
+#ifdef CONFIG_BLK_DEV_XIP
+ .direct_access = brd_direct_access,
+#endif
+};
+
+/*
+ * And now the modules code and kernel interface.
+ */
+static int rd_nr;
+int rd_size = CONFIG_BLK_DEV_RAM_SIZE;
+module_param(rd_nr, int, 0);
+MODULE_PARM_DESC(rd_nr, "Maximum number of brd devices");
+module_param(rd_size, int, 0);
+MODULE_PARM_DESC(rd_size, "Size of each RAM disk in kbytes.");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_BLOCKDEV_MAJOR(RAMDISK_MAJOR);
+
+#ifndef MODULE
+/* Legacy boot options - nonmodular */
+static int __init ramdisk_size(char *str)
+{
+ rd_size = simple_strtol(str, NULL, 0);
+ return 1;
+}
+static int __init ramdisk_size2(char *str)
+{
+ return ramdisk_size(str);
+}
+__setup("ramdisk=", ramdisk_size);
+__setup("ramdisk_size=", ramdisk_size2);
+#endif
+
+/*
+ * The device scheme is derived from loop.c. Keep them in synch where possible
+ * (should share code eventually).
+ */
+static LIST_HEAD(brd_devices);
+static DEFINE_MUTEX(brd_devices_mutex);
+
+static struct brd_device *brd_alloc(int i)
+{
+ struct brd_device *brd;
+ struct gendisk *disk;
+
+ brd = kzalloc(sizeof(*brd), GFP_KERNEL);
+ if (!brd)
+ goto out;
+ brd->brd_number = i;
+ spin_lock_init(&brd->brd_lock);
+ INIT_RADIX_TREE(&brd->brd_pages, GFP_ATOMIC);
+
+ brd->brd_queue = blk_alloc_queue(GFP_KERNEL);
+ if (!brd->brd_queue)
+ goto out_free_dev;
+ blk_queue_make_request(brd->brd_queue, brd_make_request);
+ blk_queue_max_sectors(brd->brd_queue, 1024);
+ blk_queue_bounce_limit(brd->brd_queue, BLK_BOUNCE_ANY);
+
+ disk = brd->brd_disk = alloc_disk(1);
+ if (!disk)
+ goto out_free_queue;
+ disk->major = RAMDISK_MAJOR;
+ disk->first_minor = i;
+ disk->fops = &brd_fops;
+ disk->private_data = brd;
+ disk->queue = brd->brd_queue;
+ sprintf(disk->disk_name, "ram%d", i);
+ set_capacity(disk, rd_size * 2);
+
+ return brd;
+
+out_free_queue:
+ blk_cleanup_queue(brd->brd_queue);
+out_free_dev:
+ kfree(brd);
+out:
+ return NULL;
+}
+
+static void brd_free(struct brd_device *brd)
+{
+ put_disk(brd->brd_disk);
+ blk_cleanup_queue(brd->brd_queue);
+ brd_free_pages(brd);
+ kfree(brd);
+}
+
+static struct brd_device *brd_init_one(int i)
+{
+ struct brd_device *brd;
+
+ list_for_each_entry(brd, &brd_devices, brd_list) {
+ if (brd->brd_number == i)
+ goto out;
+ }
+
+ brd = brd_alloc(i);
+ if (brd) {
+ add_disk(brd->brd_disk);
+ list_add_tail(&brd->brd_list, &brd_devices);
+ }
+out:
+ return brd;
+}
+
+static void brd_del_one(struct brd_device *brd)
+{
+ list_del(&brd->brd_list);
+ del_gendisk(brd->brd_disk);
+ brd_free(brd);
+}
+
+static struct kobject *brd_probe(dev_t dev, int *part, void *data)
+{
+ struct brd_device *brd;
+ struct kobject *kobj;
+
+ mutex_lock(&brd_devices_mutex);
+ brd = brd_init_one(dev & MINORMASK);
+ kobj = brd ? get_disk(brd->brd_disk) : ERR_PTR(-ENOMEM);
+ mutex_unlock(&brd_devices_mutex);
+
+ *part = 0;
+ return kobj;
+}
+
+static int __init brd_init(void)
+{
+ int i, nr;
+ unsigned long range;
+ struct brd_device *brd, *next;
+
+ /*
+ * brd module now has a feature to instantiate underlying device
+ * structure on-demand, provided that there is an access dev node.
+ * However, this will not work well with user space tool that doesn't
+ * know about such "feature". In order to not break any existing
+ * tool, we do the following:
+ *
+ * (1) if rd_nr is specified, create that many upfront, and this
+ * also becomes a hard limit.
+ * (2) if rd_nr is not specified, create 1 rd device on module
+ * load, user can further extend brd device by create dev node
+ * themselves and have kernel automatically instantiate actual
+ * device on-demand.
+ */
+ if (rd_nr > 1UL << MINORBITS)
+ return -EINVAL;
+
+ if (rd_nr) {
+ nr = rd_nr;
+ range = rd_nr;
+ } else {
+ nr = CONFIG_BLK_DEV_RAM_COUNT;
+ range = 1UL << MINORBITS;
+ }
+
+ if (register_blkdev(RAMDISK_MAJOR, "ramdisk"))
+ return -EIO;
+
+ for (i = 0; i < nr; i++) {
+ brd = brd_alloc(i);
+ if (!brd)
+ goto out_free;
+ list_add_tail(&brd->brd_list, &brd_devices);
+ }
+
+ /* point of no return */
+
+ list_for_each_entry(brd, &brd_devices, brd_list)
+ add_disk(brd->brd_disk);
+
+ blk_register_region(MKDEV(RAMDISK_MAJOR, 0), range,
+ THIS_MODULE, brd_probe, NULL, NULL);
+
+ printk(KERN_INFO "brd: module loaded\n");
+ return 0;
+
+out_free:
+ list_for_each_entry_safe(brd, next, &brd_devices, brd_list) {
+ list_del(&brd->brd_list);
+ brd_free(brd);
+ }
+
+ unregister_blkdev(RAMDISK_MAJOR, "brd");
+ return -ENOMEM;
+}
+
+static void __exit brd_exit(void)
+{
+ unsigned long range;
+ struct brd_device *brd, *next;
+
+ range = rd_nr ? rd_nr : 1UL << MINORBITS;
+
+ list_for_each_entry_safe(brd, next, &brd_devices, brd_list)
+ brd_del_one(brd);
+
+ blk_unregister_region(MKDEV(RAMDISK_MAJOR, 0), range);
+ unregister_blkdev(RAMDISK_MAJOR, "ramdisk");
+}
+
+module_init(brd_init);
+module_exit(brd_exit);
+
#endif /* NDEBUG */
static unsigned int nbds_max = 16;
-static struct nbd_device nbd_dev[MAX_NBD];
+static struct nbd_device *nbd_dev;
/*
* Use just one lock (or at most 1 per NIC). Two arguments for this:
BUILD_BUG_ON(sizeof(struct nbd_request) != 28);
- if (nbds_max > MAX_NBD) {
- printk(KERN_CRIT "nbd: cannot allocate more than %u nbds; %u requested.\n", MAX_NBD,
- nbds_max);
- return -EINVAL;
- }
+ nbd_dev = kcalloc(nbds_max, sizeof(*nbd_dev), GFP_KERNEL);
+ if (!nbd_dev)
+ return -ENOMEM;
for (i = 0; i < nbds_max; i++) {
struct gendisk *disk = alloc_disk(1);
+++ /dev/null
-/*
- * ramdisk.c - Multiple RAM disk driver - gzip-loading version - v. 0.8 beta.
- *
- * (C) Chad Page, Theodore Ts'o, et. al, 1995.
- *
- * This RAM disk is designed to have filesystems created on it and mounted
- * just like a regular floppy disk.
- *
- * It also does something suggested by Linus: use the buffer cache as the
- * RAM disk data. This makes it possible to dynamically allocate the RAM disk
- * buffer - with some consequences I have to deal with as I write this.
- *
- * This code is based on the original ramdisk.c, written mostly by
- * Theodore Ts'o (TYT) in 1991. The code was largely rewritten by
- * Chad Page to use the buffer cache to store the RAM disk data in
- * 1995; Theodore then took over the driver again, and cleaned it up
- * for inclusion in the mainline kernel.
- *
- * The original CRAMDISK code was written by Richard Lyons, and
- * adapted by Chad Page to use the new RAM disk interface. Theodore
- * Ts'o rewrote it so that both the compressed RAM disk loader and the
- * kernel decompressor uses the same inflate.c codebase. The RAM disk
- * loader now also loads into a dynamic (buffer cache based) RAM disk,
- * not the old static RAM disk. Support for the old static RAM disk has
- * been completely removed.
- *
- * Loadable module support added by Tom Dyas.
- *
- * Further cleanups by Chad Page (page0588@sundance.sjsu.edu):
- * Cosmetic changes in #ifdef MODULE, code movement, etc.
- * When the RAM disk module is removed, free the protected buffers
- * Default RAM disk size changed to 2.88 MB
- *
- * Added initrd: Werner Almesberger & Hans Lermen, Feb '96
- *
- * 4/25/96 : Made RAM disk size a parameter (default is now 4 MB)
- * - Chad Page
- *
- * Add support for fs images split across >1 disk, Paul Gortmaker, Mar '98
- *
- * Make block size and block size shift for RAM disks a global macro
- * and set blk_size for -ENOSPC, Werner Fink <werner@suse.de>, Apr '99
- */
-
-#include <linux/string.h>
-#include <linux/slab.h>
-#include <asm/atomic.h>
-#include <linux/bio.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/pagemap.h>
-#include <linux/blkdev.h>
-#include <linux/genhd.h>
-#include <linux/buffer_head.h> /* for invalidate_bdev() */
-#include <linux/backing-dev.h>
-#include <linux/blkpg.h>
-#include <linux/writeback.h>
-#include <linux/log2.h>
-
-#include <asm/uaccess.h>
-
-/* Various static variables go here. Most are used only in the RAM disk code.
- */
-
-static struct gendisk *rd_disks[CONFIG_BLK_DEV_RAM_COUNT];
-static struct block_device *rd_bdev[CONFIG_BLK_DEV_RAM_COUNT];/* Protected device data */
-static struct request_queue *rd_queue[CONFIG_BLK_DEV_RAM_COUNT];
-
-/*
- * Parameters for the boot-loading of the RAM disk. These are set by
- * init/main.c (from arguments to the kernel command line) or from the
- * architecture-specific setup routine (from the stored boot sector
- * information).
- */
-int rd_size = CONFIG_BLK_DEV_RAM_SIZE; /* Size of the RAM disks */
-/*
- * It would be very desirable to have a soft-blocksize (that in the case
- * of the ramdisk driver is also the hardblocksize ;) of PAGE_SIZE because
- * doing that we'll achieve a far better MM footprint. Using a rd_blocksize of
- * BLOCK_SIZE in the worst case we'll make PAGE_SIZE/BLOCK_SIZE buffer-pages
- * unfreeable. With a rd_blocksize of PAGE_SIZE instead we are sure that only
- * 1 page will be protected. Depending on the size of the ramdisk you
- * may want to change the ramdisk blocksize to achieve a better or worse MM
- * behaviour. The default is still BLOCK_SIZE (needed by rd_load_image that
- * supposes the filesystem in the image uses a BLOCK_SIZE blocksize).
- */
-static int rd_blocksize = CONFIG_BLK_DEV_RAM_BLOCKSIZE;
-
-/*
- * Copyright (C) 2000 Linus Torvalds.
- * 2000 Transmeta Corp.
- * aops copied from ramfs.
- */
-
-/*
- * If a ramdisk page has buffers, some may be uptodate and some may be not.
- * To bring the page uptodate we zero out the non-uptodate buffers. The
- * page must be locked.
- */
-static void make_page_uptodate(struct page *page)
-{
- if (page_has_buffers(page)) {
- struct buffer_head *bh = page_buffers(page);
- struct buffer_head *head = bh;
-
- do {
- if (!buffer_uptodate(bh)) {
- memset(bh->b_data, 0, bh->b_size);
- /*
- * akpm: I'm totally undecided about this. The
- * buffer has just been magically brought "up to
- * date", but nobody should want to be reading
- * it anyway, because it hasn't been used for
- * anything yet. It is still in a "not read
- * from disk yet" state.
- *
- * But non-uptodate buffers against an uptodate
- * page are against the rules. So do it anyway.
- */
- set_buffer_uptodate(bh);
- }
- } while ((bh = bh->b_this_page) != head);
- } else {
- memset(page_address(page), 0, PAGE_CACHE_SIZE);
- }
- flush_dcache_page(page);
- SetPageUptodate(page);
-}
-
-static int ramdisk_readpage(struct file *file, struct page *page)
-{
- if (!PageUptodate(page))
- make_page_uptodate(page);
- unlock_page(page);
- return 0;
-}
-
-static int ramdisk_prepare_write(struct file *file, struct page *page,
- unsigned offset, unsigned to)
-{
- if (!PageUptodate(page))
- make_page_uptodate(page);
- return 0;
-}
-
-static int ramdisk_commit_write(struct file *file, struct page *page,
- unsigned offset, unsigned to)
-{
- set_page_dirty(page);
- return 0;
-}
-
-/*
- * ->writepage to the blockdev's mapping has to redirty the page so that the
- * VM doesn't go and steal it. We return AOP_WRITEPAGE_ACTIVATE so that the VM
- * won't try to (pointlessly) write the page again for a while.
- *
- * Really, these pages should not be on the LRU at all.
- */
-static int ramdisk_writepage(struct page *page, struct writeback_control *wbc)
-{
- if (!PageUptodate(page))
- make_page_uptodate(page);
- SetPageDirty(page);
- if (wbc->for_reclaim)
- return AOP_WRITEPAGE_ACTIVATE;
- unlock_page(page);
- return 0;
-}
-
-/*
- * This is a little speedup thing: short-circuit attempts to write back the
- * ramdisk blockdev inode to its non-existent backing store.
- */
-static int ramdisk_writepages(struct address_space *mapping,
- struct writeback_control *wbc)
-{
- return 0;
-}
-
-/*
- * ramdisk blockdev pages have their own ->set_page_dirty() because we don't
- * want them to contribute to dirty memory accounting.
- */
-static int ramdisk_set_page_dirty(struct page *page)
-{
- if (!TestSetPageDirty(page))
- return 1;
- return 0;
-}
-
-/*
- * releasepage is called by pagevec_strip/try_to_release_page if
- * buffers_heads_over_limit is true. Without a releasepage function
- * try_to_free_buffers is called instead. That can unset the dirty
- * bit of our ram disk pages, which will be eventually freed, even
- * if the page is still in use.
- */
-static int ramdisk_releasepage(struct page *page, gfp_t dummy)
-{
- return 0;
-}
-
-static const struct address_space_operations ramdisk_aops = {
- .readpage = ramdisk_readpage,
- .prepare_write = ramdisk_prepare_write,
- .commit_write = ramdisk_commit_write,
- .writepage = ramdisk_writepage,
- .set_page_dirty = ramdisk_set_page_dirty,
- .writepages = ramdisk_writepages,
- .releasepage = ramdisk_releasepage,
-};
-
-static int rd_blkdev_pagecache_IO(int rw, struct bio_vec *vec, sector_t sector,
- struct address_space *mapping)
-{
- pgoff_t index = sector >> (PAGE_CACHE_SHIFT - 9);
- unsigned int vec_offset = vec->bv_offset;
- int offset = (sector << 9) & ~PAGE_CACHE_MASK;
- int size = vec->bv_len;
- int err = 0;
-
- do {
- int count;
- struct page *page;
- char *src;
- char *dst;
-
- count = PAGE_CACHE_SIZE - offset;
- if (count > size)
- count = size;
- size -= count;
-
- page = grab_cache_page(mapping, index);
- if (!page) {
- err = -ENOMEM;
- goto out;
- }
-
- if (!PageUptodate(page))
- make_page_uptodate(page);
-
- index++;
-
- if (rw == READ) {
- src = kmap_atomic(page, KM_USER0) + offset;
- dst = kmap_atomic(vec->bv_page, KM_USER1) + vec_offset;
- } else {
- src = kmap_atomic(vec->bv_page, KM_USER0) + vec_offset;
- dst = kmap_atomic(page, KM_USER1) + offset;
- }
- offset = 0;
- vec_offset += count;
-
- memcpy(dst, src, count);
-
- kunmap_atomic(src, KM_USER0);
- kunmap_atomic(dst, KM_USER1);
-
- if (rw == READ)
- flush_dcache_page(vec->bv_page);
- else
- set_page_dirty(page);
- unlock_page(page);
- put_page(page);
- } while (size);
-
- out:
- return err;
-}
-
-/*
- * Basically, my strategy here is to set up a buffer-head which can't be
- * deleted, and make that my Ramdisk. If the request is outside of the
- * allocated size, we must get rid of it...
- *
- * 19-JAN-1998 Richard Gooch <rgooch@atnf.csiro.au> Added devfs support
- *
- */
-static int rd_make_request(struct request_queue *q, struct bio *bio)
-{
- struct block_device *bdev = bio->bi_bdev;
- struct address_space * mapping = bdev->bd_inode->i_mapping;
- sector_t sector = bio->bi_sector;
- unsigned long len = bio->bi_size >> 9;
- int rw = bio_data_dir(bio);
- struct bio_vec *bvec;
- int ret = 0, i;
-
- if (sector + len > get_capacity(bdev->bd_disk))
- goto fail;
-
- if (rw==READA)
- rw=READ;
-
- bio_for_each_segment(bvec, bio, i) {
- ret |= rd_blkdev_pagecache_IO(rw, bvec, sector, mapping);
- sector += bvec->bv_len >> 9;
- }
- if (ret)
- goto fail;
-
- bio_endio(bio, 0);
- return 0;
-fail:
- bio_io_error(bio);
- return 0;
-}
-
-static int rd_ioctl(struct inode *inode, struct file *file,
- unsigned int cmd, unsigned long arg)
-{
- int error;
- struct block_device *bdev = inode->i_bdev;
-
- if (cmd != BLKFLSBUF)
- return -ENOTTY;
-
- /*
- * special: we want to release the ramdisk memory, it's not like with
- * the other blockdevices where this ioctl only flushes away the buffer
- * cache
- */
- error = -EBUSY;
- mutex_lock(&bdev->bd_mutex);
- if (bdev->bd_openers <= 2) {
- truncate_inode_pages(bdev->bd_inode->i_mapping, 0);
- error = 0;
- }
- mutex_unlock(&bdev->bd_mutex);
- return error;
-}
-
-/*
- * This is the backing_dev_info for the blockdev inode itself. It doesn't need
- * writeback and it does not contribute to dirty memory accounting.
- */
-static struct backing_dev_info rd_backing_dev_info = {
- .ra_pages = 0, /* No readahead */
- .capabilities = BDI_CAP_NO_ACCT_DIRTY | BDI_CAP_NO_WRITEBACK | BDI_CAP_MAP_COPY,
- .unplug_io_fn = default_unplug_io_fn,
-};
-
-/*
- * This is the backing_dev_info for the files which live atop the ramdisk
- * "device". These files do need writeback and they do contribute to dirty
- * memory accounting.
- */
-static struct backing_dev_info rd_file_backing_dev_info = {
- .ra_pages = 0, /* No readahead */
- .capabilities = BDI_CAP_MAP_COPY, /* Does contribute to dirty memory */
- .unplug_io_fn = default_unplug_io_fn,
-};
-
-static int rd_open(struct inode *inode, struct file *filp)
-{
- unsigned unit = iminor(inode);
-
- if (rd_bdev[unit] == NULL) {
- struct block_device *bdev = inode->i_bdev;
- struct address_space *mapping;
- unsigned bsize;
- gfp_t gfp_mask;
-
- inode = igrab(bdev->bd_inode);
- rd_bdev[unit] = bdev;
- bdev->bd_openers++;
- bsize = bdev_hardsect_size(bdev);
- bdev->bd_block_size = bsize;
- inode->i_blkbits = blksize_bits(bsize);
- inode->i_size = get_capacity(bdev->bd_disk)<<9;
-
- mapping = inode->i_mapping;
- mapping->a_ops = &ramdisk_aops;
- mapping->backing_dev_info = &rd_backing_dev_info;
- bdev->bd_inode_backing_dev_info = &rd_file_backing_dev_info;
-
- /*
- * Deep badness. rd_blkdev_pagecache_IO() needs to allocate
- * pagecache pages within a request_fn. We cannot recur back
- * into the filesystem which is mounted atop the ramdisk, because
- * that would deadlock on fs locks. And we really don't want
- * to reenter rd_blkdev_pagecache_IO when we're already within
- * that function.
- *
- * So we turn off __GFP_FS and __GFP_IO.
- *
- * And to give this thing a hope of working, turn on __GFP_HIGH.
- * Hopefully, there's enough regular memory allocation going on
- * for the page allocator emergency pools to keep the ramdisk
- * driver happy.
- */
- gfp_mask = mapping_gfp_mask(mapping);
- gfp_mask &= ~(__GFP_FS|__GFP_IO);
- gfp_mask |= __GFP_HIGH;
- mapping_set_gfp_mask(mapping, gfp_mask);
- }
-
- return 0;
-}
-
-static struct block_device_operations rd_bd_op = {
- .owner = THIS_MODULE,
- .open = rd_open,
- .ioctl = rd_ioctl,
-};
-
-/*
- * Before freeing the module, invalidate all of the protected buffers!
- */
-static void __exit rd_cleanup(void)
-{
- int i;
-
- for (i = 0; i < CONFIG_BLK_DEV_RAM_COUNT; i++) {
- struct block_device *bdev = rd_bdev[i];
- rd_bdev[i] = NULL;
- if (bdev) {
- invalidate_bdev(bdev);
- blkdev_put(bdev);
- }
- del_gendisk(rd_disks[i]);
- put_disk(rd_disks[i]);
- blk_cleanup_queue(rd_queue[i]);
- }
- unregister_blkdev(RAMDISK_MAJOR, "ramdisk");
-
- bdi_destroy(&rd_file_backing_dev_info);
- bdi_destroy(&rd_backing_dev_info);
-}
-
-/*
- * This is the registration and initialization section of the RAM disk driver
- */
-static int __init rd_init(void)
-{
- int i;
- int err;
-
- err = bdi_init(&rd_backing_dev_info);
- if (err)
- goto out2;
-
- err = bdi_init(&rd_file_backing_dev_info);
- if (err) {
- bdi_destroy(&rd_backing_dev_info);
- goto out2;
- }
-
- err = -ENOMEM;
-
- if (rd_blocksize > PAGE_SIZE || rd_blocksize < 512 ||
- !is_power_of_2(rd_blocksize)) {
- printk("RAMDISK: wrong blocksize %d, reverting to defaults\n",
- rd_blocksize);
- rd_blocksize = BLOCK_SIZE;
- }
-
- for (i = 0; i < CONFIG_BLK_DEV_RAM_COUNT; i++) {
- rd_disks[i] = alloc_disk(1);
- if (!rd_disks[i])
- goto out;
-
- rd_queue[i] = blk_alloc_queue(GFP_KERNEL);
- if (!rd_queue[i]) {
- put_disk(rd_disks[i]);
- goto out;
- }
- }
-
- if (register_blkdev(RAMDISK_MAJOR, "ramdisk")) {
- err = -EIO;
- goto out;
- }
-
- for (i = 0; i < CONFIG_BLK_DEV_RAM_COUNT; i++) {
- struct gendisk *disk = rd_disks[i];
-
- blk_queue_make_request(rd_queue[i], &rd_make_request);
- blk_queue_hardsect_size(rd_queue[i], rd_blocksize);
-
- /* rd_size is given in kB */
- disk->major = RAMDISK_MAJOR;
- disk->first_minor = i;
- disk->fops = &rd_bd_op;
- disk->queue = rd_queue[i];
- disk->flags |= GENHD_FL_SUPPRESS_PARTITION_INFO;
- sprintf(disk->disk_name, "ram%d", i);
- set_capacity(disk, rd_size * 2);
- add_disk(rd_disks[i]);
- }
-
- /* rd_size is given in kB */
- printk("RAMDISK driver initialized: "
- "%d RAM disks of %dK size %d blocksize\n",
- CONFIG_BLK_DEV_RAM_COUNT, rd_size, rd_blocksize);
-
- return 0;
-out:
- while (i--) {
- put_disk(rd_disks[i]);
- blk_cleanup_queue(rd_queue[i]);
- }
- bdi_destroy(&rd_backing_dev_info);
- bdi_destroy(&rd_file_backing_dev_info);
-out2:
- return err;
-}
-
-module_init(rd_init);
-module_exit(rd_cleanup);
-
-/* options - nonmodular */
-#ifndef MODULE
-static int __init ramdisk_size(char *str)
-{
- rd_size = simple_strtol(str,NULL,0);
- return 1;
-}
-static int __init ramdisk_blocksize(char *str)
-{
- rd_blocksize = simple_strtol(str,NULL,0);
- return 1;
-}
-__setup("ramdisk_size=", ramdisk_size);
-__setup("ramdisk_blocksize=", ramdisk_blocksize);
-#endif
-
-/* options - modular */
-module_param(rd_size, int, 0);
-MODULE_PARM_DESC(rd_size, "Size of each RAM disk in kbytes.");
-module_param(rd_blocksize, int, 0);
-MODULE_PARM_DESC(rd_blocksize, "Blocksize of each RAM disk in bytes.");
-MODULE_ALIAS_BLOCKDEV_MAJOR(RAMDISK_MAJOR);
-
-MODULE_LICENSE("GPL");
#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002
#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003
#endif
-#define MAX_PCI_DEVICE_NUM 3
static char *applicom_pci_devnames[] = {
"PCI board",
};
static struct pci_device_id applicom_pci_tbl[] = {
- { PCI_VENDOR_ID_APPLICOM, PCI_DEVICE_ID_APPLICOM_PCIGENERIC,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
- { PCI_VENDOR_ID_APPLICOM, PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
- { PCI_VENDOR_ID_APPLICOM, PCI_DEVICE_ID_APPLICOM_PCI2000PFB,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
+ { PCI_VDEVICE(APPLICOM, PCI_DEVICE_ID_APPLICOM_PCIGENERIC) },
+ { PCI_VDEVICE(APPLICOM, PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN) },
+ { PCI_VDEVICE(APPLICOM, PCI_DEVICE_ID_APPLICOM_PCI2000PFB) },
{ 0 }
};
MODULE_DEVICE_TABLE(pci, applicom_pci_tbl);
while ( (dev = pci_get_class(PCI_CLASS_OTHERS << 16, dev))) {
- if (dev->vendor != PCI_VENDOR_ID_APPLICOM)
- continue;
-
- if (dev->device > MAX_PCI_DEVICE_NUM || dev->device == 0)
+ if (!pci_match_id(applicom_pci_tbl, dev))
continue;
if (pci_enable_device(dev))
return -EIO;
- RamIO = ioremap(dev->resource[0].start, LEN_RAM_IO);
+ RamIO = ioremap(pci_resource_start(dev, 0), LEN_RAM_IO);
if (!RamIO) {
printk(KERN_INFO "ac.o: Failed to ioremap PCI memory "
"space at 0x%llx\n",
- (unsigned long long)dev->resource[0].start);
+ (unsigned long long)pci_resource_start(dev, 0));
pci_disable_device(dev);
return -EIO;
}
printk(KERN_INFO "Applicom %s found at mem 0x%llx, irq %d\n",
applicom_pci_devnames[dev->device-1],
- (unsigned long long)dev->resource[0].start,
+ (unsigned long long)pci_resource_start(dev, 0),
dev->irq);
- boardno = ac_register_board(dev->resource[0].start, RamIO,0);
+ boardno = ac_register_board(pci_resource_start(dev, 0),
+ RamIO, 0);
if (!boardno) {
printk(KERN_INFO "ac.o: PCI Applicom device doesn't have correct signature.\n");
iounmap(RamIO);
static int moxa_tiocmset(struct tty_struct *tty, struct file *file,
unsigned int set, unsigned int clear);
static void moxa_poll(unsigned long);
-static void moxa_set_tty_param(struct tty_struct *);
+static void moxa_set_tty_param(struct tty_struct *, struct ktermios *);
static int moxa_block_till_ready(struct tty_struct *, struct file *,
struct moxa_port *);
static void moxa_setup_empty_event(struct tty_struct *);
ch->tty = tty;
if (!(ch->asyncflags & ASYNC_INITIALIZED)) {
ch->statusflags = 0;
- moxa_set_tty_param(tty);
+ moxa_set_tty_param(tty, tty->termios);
MoxaPortLineCtrl(ch->port, 1, 1);
MoxaPortEnable(ch->port);
ch->asyncflags |= ASYNC_INITIALIZED;
if (ch == NULL)
return;
- moxa_set_tty_param(tty);
+ moxa_set_tty_param(tty, old_termios);
if (!(old_termios->c_cflag & CLOCAL) &&
(tty->termios->c_cflag & CLOCAL))
wake_up_interruptible(&ch->open_wait);
/******************************************************************************/
-static void moxa_set_tty_param(struct tty_struct *tty)
+static void moxa_set_tty_param(struct tty_struct *tty, struct ktermios *old_termios)
{
register struct ktermios *ts;
struct moxa_port *ch;
- int rts, cts, txflow, rxflow, xany;
+ int rts, cts, txflow, rxflow, xany, baud;
ch = (struct moxa_port *) tty->driver_data;
ts = tty->termios;
rxflow = 1;
if (ts->c_iflag & IXANY)
xany = 1;
+
+ /* Clear the features we don't support */
+ ts->c_cflag &= ~CMSPAR;
MoxaPortFlowCtrl(ch->port, rts, cts, txflow, rxflow, xany);
- MoxaPortSetTermio(ch->port, ts, tty_get_baud_rate(tty));
+ baud = MoxaPortSetTermio(ch->port, ts, tty_get_baud_rate(tty));
+ if (baud == -1)
+ baud = tty_termios_baud_rate(old_termios);
+ /* Not put the baud rate into the termios data */
+ tty_encode_baud_rate(tty, baud, baud);
}
static int moxa_block_till_ready(struct tty_struct *tty, struct file *filp,
if (baud >= 921600L)
return (-1);
}
- MoxaPortSetBaud(port, baud);
+ baud = MoxaPortSetBaud(port, baud);
if (termio->c_iflag & (IXON | IXOFF | IXANY)) {
writeb(termio->c_cc[VSTART], ofsAddr + FuncArg);
moxa_wait_finish(ofsAddr);
}
- return (0);
+ return (baud);
}
int MoxaPortGetLineOut(int port, int *dtrState, int *rtsState)
/*
* n_tty.c --- implements the N_TTY line discipline.
- *
+ *
* This code used to be in tty_io.c, but things are getting hairy
* enough that it made sense to split things off. (The N_TTY
* processing has changed so much that it's hardly recognizable,
*
* Note that the open routine for N_TTY is guaranteed never to return
* an error. This is because Linux will fall back to setting a line
- * to N_TTY if it can not switch to any other line discipline.
+ * to N_TTY if it can not switch to any other line discipline.
*
* Written by Theodore Ts'o, Copyright 1994.
- *
+ *
* This file also contains code originally written by Linus Torvalds,
* Copyright 1991, 1992, 1993, and by Julian Cowley, Copyright 1994.
- *
+ *
* This file may be redistributed under the terms of the GNU General Public
* License.
*
* Reduced memory usage for older ARM systems - Russell King.
*
- * 2000/01/20 Fixed SMP locking on put_tty_queue using bits of
+ * 2000/01/20 Fixed SMP locking on put_tty_queue using bits of
* the patch by Andrew J. Kroll <ag784@freenet.buffalo.edu>
* who actually finally proved there really was a race.
*
* Can sleep, may be called under the atomic_read_lock mutex but
* this is not guaranteed.
*/
-
-static void check_unthrottle(struct tty_struct * tty)
+
+static void check_unthrottle(struct tty_struct *tty)
{
if (tty->count &&
- test_and_clear_bit(TTY_THROTTLED, &tty->flags) &&
+ test_and_clear_bit(TTY_THROTTLED, &tty->flags) &&
tty->driver->unthrottle)
tty->driver->unthrottle(tty);
}
* reset_buffer_flags - reset buffer state
* @tty: terminal to reset
*
- * Reset the read buffer counters, clear the flags,
+ * Reset the read buffer counters, clear the flags,
* and make sure the driver is unthrottled. Called
* from n_tty_open() and n_tty_flush_buffer().
*/
* FIXME: tty->ctrl_status is not spinlocked and relies on
* lock_kernel() still.
*/
-
-static void n_tty_flush_buffer(struct tty_struct * tty)
+
+static void n_tty_flush_buffer(struct tty_struct *tty)
{
/* clear everything and unthrottle the driver */
reset_buffer_flags(tty);
-
+
if (!tty->link)
return;
* @tty: tty device
*
* Report the number of characters buffered to be delivered to user
- * at this instant in time.
+ * at this instant in time.
*/
-
+
static ssize_t n_tty_chars_in_buffer(struct tty_struct *tty)
{
unsigned long flags;
* character. We use this to correctly compute the on screen size
* of the character when printing
*/
-
+
static inline int is_utf8_continuation(unsigned char c)
{
return (c & 0xc0) == 0x80;
* Returns true if the utf8 character 'c' is a multibyte continuation
* character and the terminal is in unicode mode.
*/
-
+
static inline int is_continuation(unsigned char c, struct tty_struct *tty)
{
return I_IUTF8(tty) && is_utf8_continuation(c);
* Called from both the receive and transmit sides and can be called
* re-entrantly. Relies on lock_kernel() still.
*/
-
+
static int opost(unsigned char c, struct tty_struct *tty)
{
int space, spaces;
*
* Called from write_chan under the tty layer write lock.
*/
-
-static ssize_t opost_block(struct tty_struct * tty,
- const unsigned char * buf, unsigned int nr)
+
+static ssize_t opost_block(struct tty_struct *tty,
+ const unsigned char *buf, unsigned int nr)
{
int space;
int i;
break_out:
if (tty->driver->flush_chars)
tty->driver->flush_chars(tty);
- i = tty->driver->write(tty, buf, i);
+ i = tty->driver->write(tty, buf, i);
return i;
}
*
* Queue a byte to the driver layer for output
*/
-
+
static inline void put_char(unsigned char c, struct tty_struct *tty)
{
tty->driver->put_char(tty, c);
* @c: unicode byte to echo
* @tty: terminal device
*
- * Echo user input back onto the screen. This must be called only when
+ * Echo user input back onto the screen. This must be called only when
* L_ECHO(tty) is true. Called from the driver receive_buf path.
*/
* present in the stream from the driver layer. Handles the complexities
* of UTF-8 multibyte symbols.
*/
-
+
static void eraser(unsigned char c, struct tty_struct *tty)
{
enum { ERASE, WERASE, KILL } kill_type;
/* should never happen */
if (tty->column > 0x80000000)
- tty->column = 0;
+ tty->column = 0;
/* Now backup to that column. */
while (tty->column > col) {
* settings and character used. Called from the driver receive_buf
* path so serialized.
*/
-
+
static inline void isig(int sig, struct tty_struct *tty, int flush)
{
if (tty->pgrp)
*
* Called from the receive_buf path so single threaded.
*/
-
+
static inline void n_tty_receive_break(struct tty_struct *tty)
{
if (I_IGNBRK(tty))
* need locking as num_overrun and overrun_time are function
* private.
*/
-
+
static inline void n_tty_receive_overrun(struct tty_struct *tty)
{
char buf[64];
static inline void n_tty_receive_parity_error(struct tty_struct *tty,
unsigned char c)
{
- if (I_IGNPAR(tty)) {
+ if (I_IGNPAR(tty))
return;
- }
if (I_PARMRK(tty)) {
put_tty_queue('\377', tty);
put_tty_queue('\0', tty);
* @c: character
*
* Process an individual character of input received from the driver.
- * This is serialized with respect to itself by the rules for the
+ * This is serialized with respect to itself by the rules for the
* driver above.
*/
put_tty_queue(c, tty);
return;
}
-
+
if (I_ISTRIP(tty))
c &= 0x7f;
if (I_IUCLC(tty) && L_IEXTEN(tty))
put_tty_queue(c, tty);
return;
}
-
+
if (c == '\r') {
if (I_IGNCR(tty))
return;
goto handle_newline;
}
if (c == EOF_CHAR(tty)) {
- if (tty->canon_head != tty->read_head)
- set_bit(TTY_PUSH, &tty->flags);
+ if (tty->canon_head != tty->read_head)
+ set_bit(TTY_PUSH, &tty->flags);
c = __DISABLED_CHAR;
goto handle_newline;
}
if (I_PARMRK(tty) && c == (unsigned char) '\377')
put_tty_queue(c, tty);
- handle_newline:
+handle_newline:
spin_lock_irqsave(&tty->read_lock, flags);
set_bit(tty->read_head, tty->read_flags);
put_tty_queue_nolock(c, tty);
return;
}
}
-
+
finish_erasing(tty);
if (L_ECHO(tty)) {
if (tty->read_cnt >= N_TTY_BUF_SIZE-1) {
put_tty_queue(c, tty);
put_tty_queue(c, tty);
-}
+}
/**
static void n_tty_write_wakeup(struct tty_struct *tty)
{
- if (tty->fasync)
- {
- set_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
+ if (tty->fasync) {
+ set_bit(TTY_DO_WRITE_WAKEUP, &tty->flags);
kill_fasync(&tty->fasync, SIGIO, POLL_OUT);
}
- return;
}
/**
* not from interrupt context. The driver is responsible for making
* calls one at a time and in order (or using flush_to_ldisc)
*/
-
+
static void n_tty_receive_buf(struct tty_struct *tty, const unsigned char *cp,
char *fp, int count)
{
tty->read_cnt += i;
spin_unlock_irqrestore(&tty->read_lock, cpuflags);
} else {
- for (i=count, p = cp, f = fp; i; i--, p++) {
+ for (i = count, p = cp, f = fp; i; i--, p++) {
if (f)
flags = *f++;
switch (flags) {
n_tty_receive_overrun(tty);
break;
default:
- printk("%s: unknown flag %d\n",
+ printk(KERN_ERR "%s: unknown flag %d\n",
tty_name(tty, buf), flags);
break;
}
int is_ignored(int sig)
{
return (sigismember(¤t->blocked, sig) ||
- current->sighand->action[sig-1].sa.sa_handler == SIG_IGN);
+ current->sighand->action[sig-1].sa.sa_handler == SIG_IGN);
}
/**
*
* Called by the tty layer when the user changes termios flags so
* that the line discipline can plan ahead. This function cannot sleep
- * and is protected from re-entry by the tty layer. The user is
+ * and is protected from re-entry by the tty layer. The user is
* guaranteed that this function will not be re-entered or in progress
* when the ldisc is closed.
*/
-
-static void n_tty_set_termios(struct tty_struct *tty, struct ktermios * old)
+
+static void n_tty_set_termios(struct tty_struct *tty, struct ktermios *old)
{
if (!tty)
return;
-
+
tty->icanon = (L_ICANON(tty) != 0);
if (test_bit(TTY_HW_COOK_IN, &tty->flags)) {
tty->raw = 1;
* n_tty_close - close the ldisc for this tty
* @tty: device
*
- * Called from the terminal layer when this line discipline is
- * being shut down, either because of a close or becsuse of a
+ * Called from the terminal layer when this line discipline is
+ * being shut down, either because of a close or becsuse of a
* discipline change. The function will not be called while other
* ldisc methods are in progress.
*/
-
+
static void n_tty_close(struct tty_struct *tty)
{
n_tty_flush_buffer(tty);
* n_tty_open - open an ldisc
* @tty: terminal to open
*
- * Called when this line discipline is being attached to the
+ * Called when this line discipline is being attached to the
* terminal device. Can sleep. Called serialized so that no
* other events will occur in parallel. No further open will occur
* until a close.
* Called under the tty->atomic_read_lock sem
*
*/
-
+
static int copy_from_read_buf(struct tty_struct *tty,
unsigned char __user **b,
size_t *nr)
return retval;
}
-extern ssize_t redirected_tty_write(struct file *,const char *,size_t,loff_t *);
+extern ssize_t redirected_tty_write(struct file *, const char *,
+ size_t, loff_t *);
/**
* job_control - check job control
* @file: file handle
*
* Perform job control management checks on this file/tty descriptor
- * and if appropriate send any needed signals and return a negative
+ * and if appropriate send any needed signals and return a negative
* error code if action should be taken.
*/
-
+
static int job_control(struct tty_struct *tty, struct file *file)
{
/* Job control check -- must be done at start and after
if (file->f_op->write != redirected_tty_write &&
current->signal->tty == tty) {
if (!tty->pgrp)
- printk("read_chan: no tty->pgrp!\n");
+ printk(KERN_ERR "read_chan: no tty->pgrp!\n");
else if (task_pgrp(current) != tty->pgrp) {
if (is_ignored(SIGTTIN) ||
is_current_pgrp_orphaned())
}
return 0;
}
-
+
/**
* read_chan - read function for tty
*
* This code must be sure never to sleep through a hangup.
*/
-
+
static ssize_t read_chan(struct tty_struct *tty, struct file *file,
unsigned char __user *buf, size_t nr)
{
do_it_again:
if (!tty->read_buf) {
- printk("n_tty_read_chan: called with read_buf == NULL?!?\n");
+ printk(KERN_ERR "n_tty_read_chan: read_buf == NULL?!?\n");
return -EIO;
}
c = job_control(tty, file);
- if(c < 0)
+ if (c < 0)
return c;
-
+
minimum = time = 0;
timeout = MAX_SCHEDULE_TIMEOUT;
if (!tty->icanon) {
if (file->f_flags & O_NONBLOCK) {
if (!mutex_trylock(&tty->atomic_read_lock))
return -EAGAIN;
- }
- else {
+ } else {
if (mutex_lock_interruptible(&tty->atomic_read_lock))
return -ERESTARTSYS;
}
so that any interrupt will set the state back to
TASK_RUNNING. */
set_current_state(TASK_INTERRUPTIBLE);
-
+
if (((minimum - (b - buf)) < tty->minimum_to_wake) &&
((minimum - (b - buf)) >= 1))
tty->minimum_to_wake = (minimum - (b - buf));
-
+
if (!input_available_p(tty, 0)) {
if (test_bit(TTY_OTHER_CLOSED, &tty->flags)) {
retval = -EIO;
if (tty->icanon) {
/* N.B. avoid overrun if nr == 0 */
while (nr && tty->read_cnt) {
- int eol;
+ int eol;
eol = test_and_clear_bit(tty->read_tail,
tty->read_flags);
if (size) {
retval = size;
if (nr)
- clear_bit(TTY_PUSH, &tty->flags);
+ clear_bit(TTY_PUSH, &tty->flags);
} else if (test_and_clear_bit(TTY_PUSH, &tty->flags))
goto do_it_again;
*
* This code must be sure never to sleep through a hangup.
*/
-
-static ssize_t write_chan(struct tty_struct * tty, struct file * file,
- const unsigned char * buf, size_t nr)
+
+static ssize_t write_chan(struct tty_struct *tty, struct file *file,
+ const unsigned char *buf, size_t nr)
{
const unsigned char *b = buf;
DECLARE_WAITQUEUE(wait, current);
* recompute the new limits. Possibly set_termios should issue
* a read wakeup to fix this bug.
*/
-
-static unsigned int normal_poll(struct tty_struct * tty, struct file * file, poll_table *wait)
+
+static unsigned int normal_poll(struct tty_struct *tty, struct file *file,
+ poll_table *wait)
{
unsigned int mask = 0;
unsigned rocketMode;
int bits, baud, divisor;
CHANNEL_t *cp;
+ struct ktermios *t = info->tty->termios;
- if (!info->tty || !info->tty->termios)
- return;
cp = &info->channel;
- cflag = info->tty->termios->c_cflag;
+ cflag = t->c_cflag;
/* Byte size and parity */
if ((cflag & CSIZE) == CS8) {
baud = 9600;
divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
if ((divisor >= 8192 || divisor < 0) && old_termios) {
- info->tty->termios->c_cflag &= ~CBAUD;
- info->tty->termios->c_cflag |=
- (old_termios->c_cflag & CBAUD);
- baud = tty_get_baud_rate(info->tty);
+ baud = tty_termios_baud_rate(old_termios);
if (!baud)
baud = 9600;
divisor = (rp_baud_base[info->board] / baud) - 1;
info->cps = baud / bits;
sSetBaud(cp, divisor);
+ /* FIXME: Should really back compute a baud rate from the divisor */
+ tty_encode_baud_rate(info->tty, baud, baud);
+
if (cflag & CRTSCTS) {
info->intmask |= DELTA_CTS;
sEnCTSFlowCtl(cp);
cflag = tty->termios->c_cflag;
- if (cflag == old_termios->c_cflag)
- return;
-
/*
* This driver doesn't support CS5 or CS6
*/
if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
tty->termios->c_cflag =
((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
+ /* Or CMSPAR */
+ tty->termios->c_cflag &= ~CMSPAR;
configure_r_port(info, old_termios);
{
int reset;
+ if (!capable(CAP_SYS_ADMIN))
+ return -EPERM;
+
if (copy_from_user(&reset, arg, sizeof (int)))
return -EFAULT;
if (reset)
{
struct tty_audit_buf *buf;
- buf = kmalloc(sizeof (*buf), GFP_KERNEL);
+ buf = kmalloc(sizeof(*buf), GFP_KERNEL);
if (!buf)
goto err;
if (PAGE_SIZE != N_TTY_BUF_SIZE)
* Also restructured routines so that there is more of a separation
* between the high-level tty routines (tty_io.c and tty_ioctl.c) and
* the low-level tty routines (serial.c, pty.c, console.c). This
- * makes for cleaner and more compact code. -TYT, 9/17/92
+ * makes for cleaner and more compact code. -TYT, 9/17/92
*
* Modified by Fred N. van Kempen, 01/29/93, to add line disciplines
* which can be dynamically activated and de-activated by the line
*
* New TIOCLINUX variants added.
* -- mj@k332.feld.cvut.cz, 19-Nov-95
- *
+ *
* Restrict vt switching via ioctl()
* -- grif@cs.ucr.edu, 5-Dec-95
*
* -- Russell King <rmk@arm.linux.org.uk>
*
* Move do_SAK() into process context. Less stack use in devfs functions.
- * alloc_tty_struct() always uses kmalloc() -- Andrew Morton <andrewm@uow.edu.eu> 17Mar01
+ * alloc_tty_struct() always uses kmalloc()
+ * -- Andrew Morton <andrewm@uow.edu.eu> 17Mar01
*/
#include <linux/types.h>
/* This list gets poked at by procfs and various bits of boot up code. This
could do with some rationalisation such as pulling the tty proc function
into this file */
-
+
LIST_HEAD(tty_drivers); /* linked list of tty drivers */
/* Mutex to protect creating and releasing a tty. This is shared with
#ifdef CONFIG_UNIX98_PTYS
extern struct tty_driver *ptm_driver; /* Unix98 pty masters; for /dev/ptmx */
-extern int pty_limit; /* Config limit on Unix98 ptys */
+extern int pty_limit; /* Config limit on Unix98 ptys */
static DEFINE_IDR(allocated_ptys);
static DEFINE_MUTEX(allocated_ptys_lock);
static int ptmx_open(struct inode *, struct file *);
static ssize_t tty_read(struct file *, char __user *, size_t, loff_t *);
static ssize_t tty_write(struct file *, const char __user *, size_t, loff_t *);
-ssize_t redirected_tty_write(struct file *, const char __user *, size_t, loff_t *);
+ssize_t redirected_tty_write(struct file *, const char __user *,
+ size_t, loff_t *);
static unsigned int tty_poll(struct file *, poll_table *);
static int tty_open(struct inode *, struct file *);
static int tty_release(struct inode *, struct file *);
-int tty_ioctl(struct inode * inode, struct file * file,
+int tty_ioctl(struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg);
#ifdef CONFIG_COMPAT
-static long tty_compat_ioctl(struct file * file, unsigned int cmd,
+static long tty_compat_ioctl(struct file *file, unsigned int cmd,
unsigned long arg);
#else
#define tty_compat_ioctl NULL
#endif
-static int tty_fasync(int fd, struct file * filp, int on);
+static int tty_fasync(int fd, struct file *filp, int on);
static void release_tty(struct tty_struct *tty, int idx);
static void __proc_set_tty(struct task_struct *tsk, struct tty_struct *tty);
static void proc_set_tty(struct task_struct *tsk, struct tty_struct *tty);
#ifdef CHECK_TTY_COUNT
struct list_head *p;
int count = 0;
-
+
file_list_lock();
list_for_each(p, &tty->tty_files) {
count++;
static void tty_buffer_free_all(struct tty_struct *tty)
{
struct tty_buffer *thead;
- while((thead = tty->buf.head) != NULL) {
+ while ((thead = tty->buf.head) != NULL) {
tty->buf.head = thead->next;
kfree(thead);
}
- while((thead = tty->buf.free) != NULL) {
+ while ((thead = tty->buf.free) != NULL) {
tty->buf.free = thead->next;
kfree(thead);
}
if (tty->buf.memory_used + size > 65536)
return NULL;
p = kmalloc(sizeof(struct tty_buffer) + 2 * size, GFP_ATOMIC);
- if(p == NULL)
+ if (p == NULL)
return NULL;
p->used = 0;
p->size = size;
tty->buf.memory_used -= b->size;
WARN_ON(tty->buf.memory_used < 0);
- if(b->size >= 512)
+ if (b->size >= 512)
kfree(b);
else {
b->next = tty->buf.free;
{
struct tty_buffer *thead;
- while((thead = tty->buf.head) != NULL) {
+ while ((thead = tty->buf.head) != NULL) {
tty->buf.head = thead->next;
tty_buffer_free(tty, thead);
}
static struct tty_buffer *tty_buffer_find(struct tty_struct *tty, size_t size)
{
struct tty_buffer **tbh = &tty->buf.free;
- while((*tbh) != NULL) {
+ while ((*tbh) != NULL) {
struct tty_buffer *t = *tbh;
- if(t->size >= size) {
+ if (t->size >= size) {
*tbh = t->next;
t->next = NULL;
t->used = 0;
tbh = &((*tbh)->next);
}
/* Round the buffer size out */
- size = (size + 0xFF) & ~ 0xFF;
+ size = (size + 0xFF) & ~0xFF;
return tty_buffer_alloc(tty, size);
/* Should possibly check if this fails for the largest buffer we
have queued and recycle that ? */
int space = tty_buffer_request_room(tty, size - copied);
struct tty_buffer *tb = tty->buf.tail;
/* If there is no space then tb may be NULL */
- if(unlikely(space == 0))
+ if (unlikely(space == 0))
break;
memcpy(tb->char_buf_ptr + tb->used, chars, space);
memset(tb->flag_buf_ptr + tb->used, TTY_NORMAL, space);
int space = tty_buffer_request_room(tty, size - copied);
struct tty_buffer *tb = tty->buf.tail;
/* If there is no space then tb may be NULL */
- if(unlikely(space == 0))
+ if (unlikely(space == 0))
break;
memcpy(tb->char_buf_ptr + tb->used, chars, space);
memcpy(tb->flag_buf_ptr + tb->used, flags, space);
* Locking: May call functions taking tty->buf.lock
*/
-int tty_prepare_flip_string(struct tty_struct *tty, unsigned char **chars, size_t size)
+int tty_prepare_flip_string(struct tty_struct *tty, unsigned char **chars,
+ size_t size)
{
int space = tty_buffer_request_room(tty, size);
if (likely(space)) {
* Locking: May call functions taking tty->buf.lock
*/
-int tty_prepare_flip_string_flags(struct tty_struct *tty, unsigned char **chars, char **flags, size_t size)
+int tty_prepare_flip_string_flags(struct tty_struct *tty,
+ unsigned char **chars, char **flags, size_t size)
{
int space = tty_buffer_request_room(tty, size);
if (likely(space)) {
* @num: line discipline number
*
* This is probably overkill for real world processors but
- * they are not on hot paths so a little discipline won't do
+ * they are not on hot paths so a little discipline won't do
* any harm.
*
* Locking: takes termios_mutex
*/
-
+
static void tty_set_termios_ldisc(struct tty_struct *tty, int num)
{
mutex_lock(&tty->termios_mutex);
* must be taken with irqs off because there are hangup path
* callers who will do ldisc lookups and cannot sleep.
*/
-
+
static DEFINE_SPINLOCK(tty_ldisc_lock);
static DECLARE_WAIT_QUEUE_HEAD(tty_ldisc_wait);
-static struct tty_ldisc tty_ldiscs[NR_LDISCS]; /* line disc dispatch table */
+/* Line disc dispatch table */
+static struct tty_ldisc tty_ldiscs[NR_LDISCS];
/**
* tty_register_ldisc - install a line discipline
{
unsigned long flags;
int ret = 0;
-
+
if (disc < N_TTY || disc >= NR_LDISCS)
return -EINVAL;
-
+
spin_lock_irqsave(&tty_ldisc_lock, flags);
tty_ldiscs[disc] = *new_ldisc;
tty_ldiscs[disc].num = disc;
tty_ldiscs[disc].flags |= LDISC_FLAG_DEFINED;
tty_ldiscs[disc].refcount = 0;
spin_unlock_irqrestore(&tty_ldisc_lock, flags);
-
+
return ret;
}
EXPORT_SYMBOL(tty_register_ldisc);
if (disc < N_TTY || disc >= NR_LDISCS)
return NULL;
-
+
spin_lock_irqsave(&tty_ldisc_lock, flags);
ld = &tty_ldiscs[disc];
/* Check the entry is defined */
- if(ld->flags & LDISC_FLAG_DEFINED)
- {
+ if (ld->flags & LDISC_FLAG_DEFINED) {
/* If the module is being unloaded we can't use it */
if (!try_module_get(ld->owner))
- ld = NULL;
+ ld = NULL;
else /* lock it */
ld->refcount++;
- }
- else
+ } else
ld = NULL;
spin_unlock_irqrestore(&tty_ldisc_lock, flags);
return ld;
{
struct tty_ldisc *ld;
unsigned long flags;
-
+
BUG_ON(disc < N_TTY || disc >= NR_LDISCS);
-
+
spin_lock_irqsave(&tty_ldisc_lock, flags);
ld = &tty_ldiscs[disc];
BUG_ON(ld->refcount == 0);
module_put(ld->owner);
spin_unlock_irqrestore(&tty_ldisc_lock, flags);
}
-
+
EXPORT_SYMBOL_GPL(tty_ldisc_put);
/**
unsigned long flags;
struct tty_ldisc *ld;
int ret = 0;
-
+
spin_lock_irqsave(&tty_ldisc_lock, flags);
ld = &tty->ldisc;
- if(test_bit(TTY_LDISC, &tty->flags))
- {
+ if (test_bit(TTY_LDISC, &tty->flags)) {
ld->refcount++;
ret = 1;
}
* tty_ldisc_ref_wait - wait for the tty ldisc
* @tty: tty device
*
- * Dereference the line discipline for the terminal and take a
- * reference to it. If the line discipline is in flux then
+ * Dereference the line discipline for the terminal and take a
+ * reference to it. If the line discipline is in flux then
* wait patiently until it changes.
*
* Note: Must not be called from an IRQ/timer context. The caller
*
* Locking: call functions take tty_ldisc_lock
*/
-
+
struct tty_ldisc *tty_ldisc_ref_wait(struct tty_struct *tty)
{
/* wait_event is a macro */
wait_event(tty_ldisc_wait, tty_ldisc_try(tty));
- if(tty->ldisc.refcount == 0)
+ if (tty->ldisc.refcount == 0)
printk(KERN_ERR "tty_ldisc_ref_wait\n");
return &tty->ldisc;
}
* tty_ldisc_ref - get the tty ldisc
* @tty: tty device
*
- * Dereference the line discipline for the terminal and take a
- * reference to it. If the line discipline is in flux then
+ * Dereference the line discipline for the terminal and take a
+ * reference to it. If the line discipline is in flux then
* return NULL. Can be called from IRQ and timer functions.
*
* Locking: called functions take tty_ldisc_lock
*/
-
+
struct tty_ldisc *tty_ldisc_ref(struct tty_struct *tty)
{
- if(tty_ldisc_try(tty))
+ if (tty_ldisc_try(tty))
return &tty->ldisc;
return NULL;
}
*
* Locking: takes tty_ldisc_lock
*/
-
+
void tty_ldisc_deref(struct tty_ldisc *ld)
{
unsigned long flags;
BUG_ON(ld == NULL);
-
+
spin_lock_irqsave(&tty_ldisc_lock, flags);
- if(ld->refcount == 0)
+ if (ld->refcount == 0)
printk(KERN_ERR "tty_ldisc_deref: no references.\n");
else
ld->refcount--;
- if(ld->refcount == 0)
+ if (ld->refcount == 0)
wake_up(&tty_ldisc_wait);
spin_unlock_irqrestore(&tty_ldisc_lock, flags);
}
set_bit(TTY_LDISC, &tty->flags);
wake_up(&tty_ldisc_wait);
}
-
+
/**
* tty_set_ldisc - set line discipline
* @tty: the terminal to set
* Locking: takes tty_ldisc_lock.
* called functions take termios_mutex
*/
-
+
static int tty_set_ldisc(struct tty_struct *tty, int ldisc)
{
int retval = 0;
spin_lock_irqsave(&tty_ldisc_lock, flags);
if (tty->ldisc.refcount || (o_tty && o_tty->ldisc.refcount)) {
- if(tty->ldisc.refcount) {
+ if (tty->ldisc.refcount) {
/* Free the new ldisc we grabbed. Must drop the lock
first. */
spin_unlock_irqrestore(&tty_ldisc_lock, flags);
* There are several reasons we may be busy, including
* random momentary I/O traffic. We must therefore
* retry. We could distinguish between blocking ops
- * and retries if we made tty_ldisc_wait() smarter. That
- * is up for discussion.
+ * and retries if we made tty_ldisc_wait() smarter.
+ * That is up for discussion.
*/
if (wait_event_interruptible(tty_ldisc_wait, tty->ldisc.refcount == 0) < 0)
return -ERESTARTSYS;
goto restart;
}
- if(o_tty && o_tty->ldisc.refcount) {
+ if (o_tty && o_tty->ldisc.refcount) {
spin_unlock_irqrestore(&tty_ldisc_lock, flags);
tty_ldisc_put(ldisc);
if (wait_event_interruptible(tty_ldisc_wait, o_tty->ldisc.refcount == 0) < 0)
goto restart;
}
}
-
- /* if the TTY_LDISC bit is set, then we are racing against another ldisc change */
-
+ /*
+ * If the TTY_LDISC bit is set, then we are racing against
+ * another ldisc change
+ */
if (!test_bit(TTY_LDISC, &tty->flags)) {
spin_unlock_irqrestore(&tty_ldisc_lock, flags);
tty_ldisc_put(ldisc);
/*
* Wait for ->hangup_work and ->buf.work handlers to terminate
*/
-
flush_scheduled_work();
/* Shutdown the current discipline. */
if (tty->ldisc.close)
/* At this point we hold a reference to the new ldisc and a
a reference to the old ldisc. If we ended up flipping back
to the existing ldisc we have two references to it */
-
+
if (tty->ldisc.num != o_ldisc.num && tty->driver->set_ldisc)
tty->driver->set_ldisc(tty);
-
+
tty_ldisc_put(o_ldisc.num);
-
+
/*
* Allow ldisc referencing to occur as soon as the driver
* ldisc callback completes.
*/
-
+
tty_ldisc_enable(tty);
if (o_tty)
tty_ldisc_enable(o_tty);
-
+
/* Restart it in case no characters kick it off. Safe if
already running */
if (work)
* Locking: none
*/
-int tty_check_change(struct tty_struct * tty)
+int tty_check_change(struct tty_struct *tty)
{
if (current->signal->tty != tty)
return 0;
EXPORT_SYMBOL(tty_check_change);
-static ssize_t hung_up_tty_read(struct file * file, char __user * buf,
+static ssize_t hung_up_tty_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
return 0;
}
-static ssize_t hung_up_tty_write(struct file * file, const char __user * buf,
+static ssize_t hung_up_tty_write(struct file *file, const char __user *buf,
size_t count, loff_t *ppos)
{
return -EIO;
}
/* No kernel lock held - none needed ;) */
-static unsigned int hung_up_tty_poll(struct file * filp, poll_table * wait)
+static unsigned int hung_up_tty_poll(struct file *filp, poll_table *wait)
{
return POLLIN | POLLOUT | POLLERR | POLLHUP | POLLRDNORM | POLLWRNORM;
}
-static int hung_up_tty_ioctl(struct inode * inode, struct file * file,
+static int hung_up_tty_ioctl(struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg)
{
return cmd == TIOCSPGRP ? -ENOTTY : -EIO;
}
-static long hung_up_tty_compat_ioctl(struct file * file,
+static long hung_up_tty_compat_ioctl(struct file *file,
unsigned int cmd, unsigned long arg)
{
return cmd == TIOCSPGRP ? -ENOTTY : -EIO;
* informs the line discipline if present that the driver is ready
* to receive more output data.
*/
-
+
void tty_wakeup(struct tty_struct *tty)
{
struct tty_ldisc *ld;
-
+
if (test_bit(TTY_DO_WRITE_WAKEUP, &tty->flags)) {
ld = tty_ldisc_ref(tty);
- if(ld) {
- if(ld->write_wakeup)
+ if (ld) {
+ if (ld->write_wakeup)
ld->write_wakeup(tty);
tty_ldisc_deref(ld);
}
* Flush the line discipline queue (if any) for this tty. If there
* is no line discipline active this is a no-op.
*/
-
+
void tty_ldisc_flush(struct tty_struct *tty)
{
struct tty_ldisc *ld = tty_ldisc_ref(tty);
- if(ld) {
- if(ld->flush_buffer)
+ if (ld) {
+ if (ld->flush_buffer)
ld->flush_buffer(tty);
tty_ldisc_deref(ld);
}
tty->termios->c_ospeed = tty_termios_baud_rate(tty->termios);
mutex_unlock(&tty->termios_mutex);
}
-
+
/**
* do_tty_hangup - actual handler for hangup events
* @work: tty device
{
struct tty_struct *tty =
container_of(work, struct tty_struct, hangup_work);
- struct file * cons_filp = NULL;
+ struct file *cons_filp = NULL;
struct file *filp, *f = NULL;
struct task_struct *p;
struct tty_ldisc *ld;
redirect = NULL;
}
spin_unlock(&redirect_lock);
-
+
check_tty_count(tty, "do_tty_hangup");
file_list_lock();
/* This breaks for file handles being sent over AF_UNIX sockets ? */
filp->f_op = &hung_up_tty_fops;
}
file_list_unlock();
-
- /* FIXME! What are the locking issues here? This may me overdoing things..
- * this question is especially important now that we've removed the irqlock. */
-
+ /*
+ * FIXME! What are the locking issues here? This may me overdoing
+ * things... This question is especially important now that we've
+ * removed the irqlock.
+ */
ld = tty_ldisc_ref(tty);
- if(ld != NULL) /* We may have no line discipline at this point */
- {
+ if (ld != NULL) {
+ /* We may have no line discipline at this point */
if (ld->flush_buffer)
ld->flush_buffer(tty);
if (tty->driver->flush_buffer)
if (ld->hangup)
ld->hangup(tty);
}
-
- /* FIXME: Once we trust the LDISC code better we can wait here for
- ldisc completion and fix the driver call race */
-
+ /*
+ * FIXME: Once we trust the LDISC code better we can wait here for
+ * ldisc completion and fix the driver call race
+ */
wake_up_interruptible(&tty->write_wait);
wake_up_interruptible(&tty->read_wait);
-
/*
* Shutdown the current line discipline, and reset it to
* N_TTY.
*/
if (tty->driver->flags & TTY_DRIVER_RESET_TERMIOS)
tty_reset_termios(tty);
-
/* Defer ldisc switch */
/* tty_deferred_ldisc_switch(N_TTY);
-
+
This should get done automatically when the port closes and
tty_release is called */
-
+
read_lock(&tasklist_lock);
if (tty->session) {
do_each_pid_task(tty->session, PIDTYPE_SID, p) {
tty->pgrp = NULL;
tty->ctrl_status = 0;
/*
- * If one of the devices matches a console pointer, we
- * cannot just call hangup() because that will cause
- * tty->count and state->count to go out of sync.
- * So we just call close() the right number of times.
+ * If one of the devices matches a console pointer, we
+ * cannot just call hangup() because that will cause
+ * tty->count and state->count to go out of sync.
+ * So we just call close() the right number of times.
*/
if (cons_filp) {
if (tty->driver->close)
tty->driver->close(tty, cons_filp);
} else if (tty->driver->hangup)
(tty->driver->hangup)(tty);
-
- /* We don't want to have driver/ldisc interactions beyond
- the ones we did here. The driver layer expects no
- calls after ->hangup() from the ldisc side. However we
- can't yet guarantee all that */
-
+ /*
+ * We don't want to have driver/ldisc interactions beyond
+ * the ones we did here. The driver layer expects no
+ * calls after ->hangup() from the ldisc side. However we
+ * can't yet guarantee all that.
+ */
set_bit(TTY_HUPPED, &tty->flags);
if (ld) {
tty_ldisc_enable(tty);
* schedule a hangup sequence to run after this event.
*/
-void tty_hangup(struct tty_struct * tty)
+void tty_hangup(struct tty_struct *tty)
{
#ifdef TTY_DEBUG_HANGUP
char buf[64];
-
printk(KERN_DEBUG "%s hangup...\n", tty_name(tty, buf));
#endif
schedule_work(&tty->hangup_work);
* is complete. That guarantee is necessary for security reasons.
*/
-void tty_vhangup(struct tty_struct * tty)
+void tty_vhangup(struct tty_struct *tty)
{
#ifdef TTY_DEBUG_HANGUP
char buf[64];
#endif
do_tty_hangup(&tty->hangup_work);
}
+
EXPORT_SYMBOL(tty_vhangup);
/**
* loss
*/
-int tty_hung_up_p(struct file * filp)
+int tty_hung_up_p(struct file *filp)
{
return (filp->f_op == &hung_up_tty_fops);
}
EXPORT_SYMBOL(tty_hung_up_p);
/**
- * is_tty - checker whether file is a TTY
+ * is_tty - checker whether file is a TTY
+ * @filp: file handle that may be a tty
+ *
+ * Check if the file handle is a tty handle.
*/
+
int is_tty(struct file *filp)
{
return filp->f_op->read == tty_read
put_pid(old_pgrp);
}
mutex_unlock(&tty_mutex);
- unlock_kernel();
+ unlock_kernel();
return;
}
if (tty_pgrp) {
}
if (tty->driver->start)
(tty->driver->start)(tty);
-
/* If we have a running line discipline it may need kicking */
tty_wakeup(tty);
}
* in new code. Multiple read calls may be outstanding in parallel.
*/
-static ssize_t tty_read(struct file * file, char __user * buf, size_t count,
+static ssize_t tty_read(struct file *file, char __user *buf, size_t count,
loff_t *ppos)
{
int i;
- struct tty_struct * tty;
+ struct tty_struct *tty;
struct inode *inode;
struct tty_ldisc *ld;
ld = tty_ldisc_ref_wait(tty);
lock_kernel();
if (ld->read)
- i = (ld->read)(tty,file,buf,count);
+ i = (ld->read)(tty, file, buf, count);
else
i = -EIO;
tty_ldisc_deref(ld);
{
ssize_t ret, written = 0;
unsigned int chunk;
-
+
ret = tty_write_lock(tty, file->f_flags & O_NDELAY);
if (ret < 0)
return ret;
* kernel lock for historical reasons. New code should not rely on this.
*/
-static ssize_t tty_write(struct file * file, const char __user * buf, size_t count,
- loff_t *ppos)
+static ssize_t tty_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *ppos)
{
- struct tty_struct * tty;
+ struct tty_struct *tty;
struct inode *inode = file->f_path.dentry->d_inode;
ssize_t ret;
struct tty_ldisc *ld;
-
+
tty = (struct tty_struct *)file->private_data;
if (tty_paranoia_check(tty, inode, "tty_write"))
return -EIO;
- if (!tty || !tty->driver->write || (test_bit(TTY_IO_ERROR, &tty->flags)))
- return -EIO;
+ if (!tty || !tty->driver->write ||
+ (test_bit(TTY_IO_ERROR, &tty->flags)))
+ return -EIO;
- ld = tty_ldisc_ref_wait(tty);
+ ld = tty_ldisc_ref_wait(tty);
if (!ld->write)
ret = -EIO;
else
return ret;
}
-ssize_t redirected_tty_write(struct file * file, const char __user * buf, size_t count,
- loff_t *ppos)
+ssize_t redirected_tty_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *ppos)
{
struct file *p = NULL;
fput(p);
return res;
}
-
return tty_write(file, buf, count, ppos);
}
int i = index + driver->name_base;
/* ->name is initialized to "ttyp", but "tty" is expected */
sprintf(p, "%s%c%x",
- driver->subtype == PTY_TYPE_SLAVE ? "tty" : driver->name,
- ptychar[i >> 4 & 0xf], i & 0xf);
+ driver->subtype == PTY_TYPE_SLAVE ? "tty" : driver->name,
+ ptychar[i >> 4 & 0xf], i & 0xf);
}
/**
* First time open is complex, especially for PTY devices.
* This code guarantees that either everything succeeds and the
* TTY is ready for operation, or else the table slots are vacated
- * and the allocated memory released. (Except that the termios
+ * and the allocated memory released. (Except that the termios
* and locked termios may be retained.)
*/
ltp = o_ltp = NULL;
tty = alloc_tty_struct();
- if(!tty)
+ if (!tty)
goto fail_no_mem;
initialize_tty_struct(tty);
tty->driver = driver;
/*
* Everything allocated ... set up the o_tty structure.
*/
- if (!(driver->other->flags & TTY_DRIVER_DEVPTS_MEM)) {
+ if (!(driver->other->flags & TTY_DRIVER_DEVPTS_MEM))
driver->other->ttys[idx] = o_tty;
- }
if (!*o_tp_loc)
*o_tp_loc = o_tp;
if (!*o_ltp_loc)
o_tty->link = tty;
}
- /*
+ /*
* All structures have been allocated, so now we install them.
* Failures after this point use release_tty to clean up, so
* there's no need to null out the local pointers.
*/
- if (!(driver->flags & TTY_DRIVER_DEVPTS_MEM)) {
+ if (!(driver->flags & TTY_DRIVER_DEVPTS_MEM))
driver->ttys[idx] = tty;
- }
-
+
if (!*tp_loc)
*tp_loc = tp;
if (!*ltp_loc)
driver->refcount++;
tty->count++;
- /*
+ /*
* Structures all installed ... call the ldisc open routines.
* If we fail here just call release_tty to clean up. No need
* to decrement the use counts, as release_tty doesn't care.
if (driver->type == TTY_DRIVER_TYPE_PTY &&
driver->subtype == PTY_TYPE_MASTER) {
/*
- * special case for PTY masters: only one open permitted,
+ * special case for PTY masters: only one open permitted,
* and the slave side open count is incremented as well.
*/
if (tty->count) {
tty->driver = driver; /* N.B. why do this every time?? */
/* FIXME */
- if(!test_bit(TTY_LDISC, &tty->flags))
+ if (!test_bit(TTY_LDISC, &tty->flags))
printk(KERN_ERR "init_dev but no ldisc\n");
success:
*ret_tty = tty;
-
+
/* All paths come through here to release the mutex */
end_init:
return retval;
* WSH 09/09/97: rewritten to avoid some nasty race conditions that could
* lead to double frees or releasing memory still in use.
*/
-static void release_dev(struct file * filp)
+static void release_dev(struct file *filp)
{
struct tty_struct *tty, *o_tty;
int pty_master, tty_closing, o_tty_closing, do_sleep;
int idx;
char buf[64];
unsigned long flags;
-
+
tty = (struct tty_struct *)filp->private_data;
- if (tty_paranoia_check(tty, filp->f_path.dentry->d_inode, "release_dev"))
+ if (tty_paranoia_check(tty, filp->f_path.dentry->d_inode,
+ "release_dev"))
return;
check_tty_count(tty, "release_dev");
idx, tty->name);
return;
}
- if (o_tty->termios_locked !=
+ if (o_tty->termios_locked !=
tty->driver->other->termios_locked[idx]) {
printk(KERN_DEBUG "release_dev: other->termios_locked["
"%d] not o_termios_locked for (%s)\n",
while (1) {
/* Guard against races with tty->count changes elsewhere and
opens on /dev/tty */
-
+
mutex_lock(&tty_mutex);
tty_closing = tty->count <= 1;
o_tty_closing = o_tty &&
"active!\n", tty_name(tty, buf));
mutex_unlock(&tty_mutex);
schedule();
- }
+ }
/*
- * The closing flags are now consistent with the open counts on
- * both sides, and we've completed the last operation that could
+ * The closing flags are now consistent with the open counts on
+ * both sides, and we've completed the last operation that could
* block, so it's safe to proceed with closing.
*/
if (pty_master) {
tty->count, tty_name(tty, buf));
tty->count = 0;
}
-
+
/*
* We've decremented tty->count, so we need to remove this file
* descriptor off the tty->tty_files list; this serves two
* case of a pty we may have to wait around for the other side
* to close, and TTY_CLOSING makes sure we can't be reopened.
*/
- if(tty_closing)
+ if (tty_closing)
set_bit(TTY_CLOSING, &tty->flags);
- if(o_tty_closing)
+ if (o_tty_closing)
set_bit(TTY_CLOSING, &o_tty->flags);
/*
/* check whether both sides are closing ... */
if (!tty_closing || (o_tty && !o_tty_closing))
return;
-
+
#ifdef TTY_DEBUG_HANGUP
printk(KERN_DEBUG "freeing tty structure...");
#endif
/*
* Wait for ->hangup_work and ->buf.work handlers to terminate
*/
-
+
flush_scheduled_work();
-
+
/*
* Wait for any short term users (we know they are just driver
* side waiters as the file is closing so user count on the file
* side is zero.
*/
spin_lock_irqsave(&tty_ldisc_lock, flags);
- while(tty->ldisc.refcount)
- {
+ while (tty->ldisc.refcount) {
spin_unlock_irqrestore(&tty_ldisc_lock, flags);
wait_event(tty_ldisc_wait, tty->ldisc.refcount == 0);
spin_lock_irqsave(&tty_ldisc_lock, flags);
if (tty->ldisc.close)
(tty->ldisc.close)(tty);
tty_ldisc_put(tty->ldisc.num);
-
+
/*
* Switch the line discipline back
*/
tty_ldisc_assign(tty, tty_ldisc_get(N_TTY));
- tty_set_termios_ldisc(tty,N_TTY);
+ tty_set_termios_ldisc(tty, N_TTY);
if (o_tty) {
/* FIXME: could o_tty be in setldisc here ? */
clear_bit(TTY_LDISC, &o_tty->flags);
(o_tty->ldisc.close)(o_tty);
tty_ldisc_put(o_tty->ldisc.num);
tty_ldisc_assign(o_tty, tty_ldisc_get(N_TTY));
- tty_set_termios_ldisc(o_tty,N_TTY);
+ tty_set_termios_ldisc(o_tty, N_TTY);
}
/*
* The release_tty function takes care of the details of clearing
* ->siglock protects ->signal/->sighand
*/
-static int tty_open(struct inode * inode, struct file * filp)
+static int tty_open(struct inode *inode, struct file *filp)
{
struct tty_struct *tty;
int noctty, retval;
unsigned short saved_flags = filp->f_flags;
nonseekable_open(inode, filp);
-
+
retry_open:
noctty = filp->f_flags & O_NOCTTY;
index = -1;
retval = 0;
-
+
mutex_lock(&tty_mutex);
- if (device == MKDEV(TTYAUX_MAJOR,0)) {
+ if (device == MKDEV(TTYAUX_MAJOR, 0)) {
tty = get_current_tty();
if (!tty) {
mutex_unlock(&tty_mutex);
goto got_driver;
}
#ifdef CONFIG_VT
- if (device == MKDEV(TTY_MAJOR,0)) {
+ if (device == MKDEV(TTY_MAJOR, 0)) {
extern struct tty_driver *console_driver;
driver = console_driver;
index = fg_console;
goto got_driver;
}
#endif
- if (device == MKDEV(TTYAUX_MAJOR,1)) {
+ if (device == MKDEV(TTYAUX_MAJOR, 1)) {
driver = console_device(&index);
if (driver) {
/* Don't let /dev/console block */
}
filp->f_flags = saved_flags;
- if (!retval && test_bit(TTY_EXCLUSIVE, &tty->flags) && !capable(CAP_SYS_ADMIN))
+ if (!retval && test_bit(TTY_EXCLUSIVE, &tty->flags) &&
+ !capable(CAP_SYS_ADMIN))
retval = -EBUSY;
if (retval) {
* Allocate a unix98 pty master device from the ptmx driver.
*
* Locking: tty_mutex protects theinit_dev work. tty->count should
- protect the rest.
+ * protect the rest.
* allocated_ptys_lock handles the list of free pty numbers
*/
-static int ptmx_open(struct inode * inode, struct file * filp)
+static int ptmx_open(struct inode *inode, struct file *filp)
{
struct tty_struct *tty;
int retval;
mutex_lock(&tty_mutex);
retval = init_dev(ptm_driver, index, &tty);
mutex_unlock(&tty_mutex);
-
+
if (retval)
goto out;
* Takes bkl. See release_dev
*/
-static int tty_release(struct inode * inode, struct file * filp)
+static int tty_release(struct inode *inode, struct file *filp)
{
lock_kernel();
release_dev(filp);
* may be re-entered freely by other callers.
*/
-static unsigned int tty_poll(struct file * filp, poll_table * wait)
+static unsigned int tty_poll(struct file *filp, poll_table *wait)
{
- struct tty_struct * tty;
+ struct tty_struct *tty;
struct tty_ldisc *ld;
int ret = 0;
tty = (struct tty_struct *)filp->private_data;
if (tty_paranoia_check(tty, filp->f_path.dentry->d_inode, "tty_poll"))
return 0;
-
+
ld = tty_ldisc_ref_wait(tty);
if (ld->poll)
ret = (ld->poll)(tty, filp, wait);
return ret;
}
-static int tty_fasync(int fd, struct file * filp, int on)
+static int tty_fasync(int fd, struct file *filp, int on)
{
- struct tty_struct * tty;
+ struct tty_struct *tty;
int retval;
tty = (struct tty_struct *)filp->private_data;
if (tty_paranoia_check(tty, filp->f_path.dentry->d_inode, "tty_fasync"))
return 0;
-
+
retval = fasync_helper(fd, filp, on, &tty->fasync);
if (retval <= 0)
return retval;
{
char ch, mbz = 0;
struct tty_ldisc *ld;
-
+
if ((current->signal->tty != tty) && !capable(CAP_SYS_ADMIN))
return -EPERM;
if (get_user(ch, p))
* is consistent.
*/
-static int tiocgwinsz(struct tty_struct *tty, struct winsize __user * arg)
+static int tiocgwinsz(struct tty_struct *tty, struct winsize __user *arg)
{
int err;
*/
static int tiocswinsz(struct tty_struct *tty, struct tty_struct *real_tty,
- struct winsize __user * arg)
+ struct winsize __user *arg)
{
struct winsize tmp_ws;
if (vc_lock_resize(tty->driver_data, tmp_ws.ws_col,
tmp_ws.ws_row)) {
mutex_unlock(&tty->termios_mutex);
- return -ENXIO;
+ return -ENXIO;
}
}
#endif
* This tty is already the controlling
* tty for another session group!
*/
- if ((arg == 1) && capable(CAP_SYS_ADMIN)) {
+ if (arg == 1 && capable(CAP_SYS_ADMIN)) {
/*
* Steal it away
*/
/*
* Split this up, as gcc can choke on it otherwise..
*/
-int tty_ioctl(struct inode * inode, struct file * file,
+int tty_ioctl(struct inode *inode, struct file *file,
unsigned int cmd, unsigned long arg)
{
struct tty_struct *tty, *real_tty;
void __user *p = (void __user *)arg;
int retval;
struct tty_ldisc *ld;
-
+
tty = (struct tty_struct *)file->private_data;
if (tty_paranoia_check(tty, inode, "tty_ioctl"))
return -EINVAL;
* Break handling by driver
*/
if (!tty->driver->break_ctl) {
- switch(cmd) {
+ switch (cmd) {
case TIOCSBRK:
case TIOCCBRK:
if (tty->driver->ioctl)
return tty->driver->ioctl(tty, file, cmd, arg);
return -EINVAL;
-
+
/* These two ioctl's always return success; even if */
/* the driver doesn't support them. */
case TCSBRK:
case TIOCSBRK:
case TIOCCBRK:
case TCSBRK:
- case TCSBRKP:
+ case TCSBRKP:
retval = tty_check_change(tty);
if (retval)
return retval;
}
switch (cmd) {
- case TIOCSTI:
- return tiocsti(tty, p);
- case TIOCGWINSZ:
- return tiocgwinsz(tty, p);
- case TIOCSWINSZ:
- return tiocswinsz(tty, real_tty, p);
- case TIOCCONS:
- return real_tty!=tty ? -EINVAL : tioccons(file);
- case FIONBIO:
- return fionbio(file, p);
- case TIOCEXCL:
- set_bit(TTY_EXCLUSIVE, &tty->flags);
- return 0;
- case TIOCNXCL:
- clear_bit(TTY_EXCLUSIVE, &tty->flags);
- return 0;
- case TIOCNOTTY:
- if (current->signal->tty != tty)
- return -ENOTTY;
- no_tty();
- return 0;
- case TIOCSCTTY:
- return tiocsctty(tty, arg);
- case TIOCGPGRP:
- return tiocgpgrp(tty, real_tty, p);
- case TIOCSPGRP:
- return tiocspgrp(tty, real_tty, p);
- case TIOCGSID:
- return tiocgsid(tty, real_tty, p);
- case TIOCGETD:
- /* FIXME: check this is ok */
- return put_user(tty->ldisc.num, (int __user *)p);
- case TIOCSETD:
- return tiocsetd(tty, p);
+ case TIOCSTI:
+ return tiocsti(tty, p);
+ case TIOCGWINSZ:
+ return tiocgwinsz(tty, p);
+ case TIOCSWINSZ:
+ return tiocswinsz(tty, real_tty, p);
+ case TIOCCONS:
+ return real_tty != tty ? -EINVAL : tioccons(file);
+ case FIONBIO:
+ return fionbio(file, p);
+ case TIOCEXCL:
+ set_bit(TTY_EXCLUSIVE, &tty->flags);
+ return 0;
+ case TIOCNXCL:
+ clear_bit(TTY_EXCLUSIVE, &tty->flags);
+ return 0;
+ case TIOCNOTTY:
+ if (current->signal->tty != tty)
+ return -ENOTTY;
+ no_tty();
+ return 0;
+ case TIOCSCTTY:
+ return tiocsctty(tty, arg);
+ case TIOCGPGRP:
+ return tiocgpgrp(tty, real_tty, p);
+ case TIOCSPGRP:
+ return tiocspgrp(tty, real_tty, p);
+ case TIOCGSID:
+ return tiocgsid(tty, real_tty, p);
+ case TIOCGETD:
+ /* FIXME: check this is ok */
+ return put_user(tty->ldisc.num, (int __user *)p);
+ case TIOCSETD:
+ return tiocsetd(tty, p);
#ifdef CONFIG_VT
- case TIOCLINUX:
- return tioclinux(tty, arg);
+ case TIOCLINUX:
+ return tioclinux(tty, arg);
#endif
- /*
- * Break handling
- */
- case TIOCSBRK: /* Turn break on, unconditionally */
- tty->driver->break_ctl(tty, -1);
- return 0;
-
- case TIOCCBRK: /* Turn break off, unconditionally */
- tty->driver->break_ctl(tty, 0);
- return 0;
- case TCSBRK: /* SVID version: non-zero arg --> no break */
- /* non-zero arg means wait for all output data
- * to be sent (performed above) but don't send break.
- * This is used by the tcdrain() termios function.
- */
- if (!arg)
- return send_break(tty, 250);
- return 0;
- case TCSBRKP: /* support for POSIX tcsendbreak() */
- return send_break(tty, arg ? arg*100 : 250);
-
- case TIOCMGET:
- return tty_tiocmget(tty, file, p);
+ /*
+ * Break handling
+ */
+ case TIOCSBRK: /* Turn break on, unconditionally */
+ tty->driver->break_ctl(tty, -1);
+ return 0;
- case TIOCMSET:
- case TIOCMBIC:
- case TIOCMBIS:
- return tty_tiocmset(tty, file, cmd, p);
- case TCFLSH:
- switch (arg) {
- case TCIFLUSH:
- case TCIOFLUSH:
- /* flush tty buffer and allow ldisc to process ioctl */
- tty_buffer_flush(tty);
- break;
- }
+ case TIOCCBRK: /* Turn break off, unconditionally */
+ tty->driver->break_ctl(tty, 0);
+ return 0;
+ case TCSBRK: /* SVID version: non-zero arg --> no break */
+ /* non-zero arg means wait for all output data
+ * to be sent (performed above) but don't send break.
+ * This is used by the tcdrain() termios function.
+ */
+ if (!arg)
+ return send_break(tty, 250);
+ return 0;
+ case TCSBRKP: /* support for POSIX tcsendbreak() */
+ return send_break(tty, arg ? arg*100 : 250);
+
+ case TIOCMGET:
+ return tty_tiocmget(tty, file, p);
+ case TIOCMSET:
+ case TIOCMBIC:
+ case TIOCMBIS:
+ return tty_tiocmset(tty, file, cmd, p);
+ case TCFLSH:
+ switch (arg) {
+ case TCIFLUSH:
+ case TCIOFLUSH:
+ /* flush tty buffer and allow ldisc to process ioctl */
+ tty_buffer_flush(tty);
break;
+ }
+ break;
}
if (tty->driver->ioctl) {
retval = (tty->driver->ioctl)(tty, file, cmd, arg);
}
#ifdef CONFIG_COMPAT
-static long tty_compat_ioctl(struct file * file, unsigned int cmd,
+static long tty_compat_ioctl(struct file *file, unsigned int cmd,
unsigned long arg)
{
struct inode *inode = file->f_dentry->d_inode;
* prevent trojan horses by killing all processes associated with this
* tty when the user hits the "Secure Attention Key". Required for
* super-paranoid applications --- see the Orange Book for more details.
- *
+ *
* This code could be nicer; ideally it should send a HUP, wait a few
* seconds, then send a INT, and then a KILL signal. But you then
* have to coordinate with the init process, since all processes associated
int i;
struct file *filp;
struct fdtable *fdt;
-
+
if (!tty)
return;
session = tty->session;
-
+
tty_ldisc_flush(tty);
if (tty->driver->flush_buffer)
tty->driver->flush_buffer(tty);
-
+
read_lock(&tasklist_lock);
/* Kill the entire session */
do_each_pid_task(session, PIDTYPE_SID, p) {
*/
spin_lock(&p->files->file_lock);
fdt = files_fdtable(p->files);
- for (i=0; i < fdt->max_fds; i++) {
+ for (i = 0; i < fdt->max_fds; i++) {
filp = fcheck_files(p->files, i);
if (!filp)
continue;
* while invoking the line discipline receive_buf method. The
* receive_buf method is single threaded for each tty instance.
*/
-
+
static void flush_to_ldisc(struct work_struct *work)
{
struct tty_struct *tty =
return;
spin_lock_irqsave(&tty->buf.lock, flags);
- set_bit(TTY_FLUSHING, &tty->flags); /* So we know a flush is running */
+ /* So we know a flush is running */
+ set_bit(TTY_FLUSHING, &tty->flags);
head = tty->buf.head;
if (head != NULL) {
tty->buf.head = NULL;
void tty_unregister_device(struct tty_driver *driver, unsigned index)
{
- device_destroy(tty_class, MKDEV(driver->major, driver->minor_start) + index);
+ device_destroy(tty_class,
+ MKDEV(driver->major, driver->minor_start) + index);
}
EXPORT_SYMBOL(tty_register_device);
int tty_register_driver(struct tty_driver *driver)
{
int error;
- int i;
+ int i;
dev_t dev;
void **p = NULL;
}
if (!driver->major) {
- error = alloc_chrdev_region(&dev, driver->minor_start, driver->num,
- driver->name);
+ error = alloc_chrdev_region(&dev, driver->minor_start,
+ driver->num, driver->name);
if (!error) {
driver->major = MAJOR(dev);
driver->minor_start = MINOR(dev);
if (p) {
driver->ttys = (struct tty_struct **)p;
driver->termios = (struct ktermios **)(p + driver->num);
- driver->termios_locked = (struct ktermios **)(p + driver->num * 2);
+ driver->termios_locked = (struct ktermios **)
+ (p + driver->num * 2);
} else {
driver->ttys = NULL;
driver->termios = NULL;
if (!driver->put_char)
driver->put_char = tty_default_put_char;
-
+
mutex_lock(&tty_mutex);
list_add(&driver->tty_drivers, &tty_drivers);
mutex_unlock(&tty_mutex);
-
- if ( !(driver->flags & TTY_DRIVER_DYNAMIC_DEV) ) {
- for(i = 0; i < driver->num; i++)
+
+ if (!(driver->flags & TTY_DRIVER_DYNAMIC_DEV)) {
+ for (i = 0; i < driver->num; i++)
tty_register_device(driver, i, NULL);
}
proc_tty_register_driver(driver);
(void) tty_register_ldisc(N_TTY, &tty_ldisc_N_TTY);
/*
- * set up the console device so that later boot sequences can
+ * set up the console device so that later boot sequences can
* inform about problems etc..
*/
call = __con_initcall_start;
* Locking: none
*/
-void tty_wait_until_sent(struct tty_struct * tty, long timeout)
+void tty_wait_until_sent(struct tty_struct *tty, long timeout)
{
#ifdef TTY_DEBUG_WAIT_UNTIL_SENT
char buf[64];
-
+
printk(KERN_DEBUG "%s wait until sent...\n", tty_name(tty, buf));
#endif
if (!tty->driver->chars_in_buffer)
if (tty->driver->wait_until_sent)
tty->driver->wait_until_sent(tty, timeout);
}
-
EXPORT_SYMBOL(tty_wait_until_sent);
static void unset_locked_termios(struct ktermios *termios,
struct ktermios *locked)
{
int i;
-
-#define NOSET_MASK(x,y,z) (x = ((x) & ~(z)) | ((y) & (z)))
+
+#define NOSET_MASK(x, y, z) (x = ((x) & ~(z)) | ((y) & (z)))
if (!locked) {
printk(KERN_WARNING "Warning?!? termios_locked is NULL.\n");
NOSET_MASK(termios->c_cflag, old->c_cflag, locked->c_cflag);
NOSET_MASK(termios->c_lflag, old->c_lflag, locked->c_lflag);
termios->c_line = locked->c_line ? old->c_line : termios->c_line;
- for (i=0; i < NCCS; i++)
+ for (i = 0; i < NCCS; i++)
termios->c_cc[i] = locked->c_cc[i] ?
old->c_cc[i] : termios->c_cc[i];
/* FIXME: What should we do for i/ospeed */
}
return baud_table[cbaud];
}
-
EXPORT_SYMBOL(tty_termios_baud_rate);
/**
return tty_termios_baud_rate(termios);
#endif
}
-
EXPORT_SYMBOL(tty_termios_input_baud_rate);
/**
return baud;
}
-
EXPORT_SYMBOL(tty_get_baud_rate);
/**
new->c_ispeed = old->c_ispeed;
new->c_ospeed = old->c_ospeed;
}
-
EXPORT_SYMBOL(tty_termios_copy_hw);
/**
* Locking: termios_sem
*/
-static void change_termios(struct tty_struct * tty, struct ktermios * new_termios)
+static void change_termios(struct tty_struct *tty, struct ktermios *new_termios)
{
int canon_change;
struct ktermios old_termios = *tty->termios;
struct tty_ldisc *ld;
-
+
/*
* Perform the actual termios internal changes under lock.
*/
-
+
/* FIXME: we need to decide on some locking/ordering semantics
for the set_termios notification eventually */
tty->canon_data = 0;
tty->erasing = 0;
}
-
+
/* This bit should be in the ldisc code */
if (canon_change && !L_ICANON(tty) && tty->read_cnt)
/* Get characters left over from canonical mode. */
wake_up_interruptible(&tty->link->read_wait);
}
}
-
+
if (tty->driver->set_termios)
(*tty->driver->set_termios)(tty, &old_termios);
else
* Called functions take ldisc and termios_sem locks
*/
-static int set_termios(struct tty_struct * tty, void __user *arg, int opt)
+static int set_termios(struct tty_struct *tty, void __user *arg, int opt)
{
struct ktermios tmp_termios;
struct tty_ldisc *ld;
return -EFAULT;
#endif
- /* If old style Bfoo values are used then load c_ispeed/c_ospeed with the real speed
- so its unconditionally usable */
+ /* If old style Bfoo values are used then load c_ispeed/c_ospeed
+ * with the real speed so its unconditionally usable */
tmp_termios.c_ispeed = tty_termios_input_baud_rate(&tmp_termios);
tmp_termios.c_ospeed = tty_termios_baud_rate(&tmp_termios);
ld = tty_ldisc_ref(tty);
-
+
if (ld != NULL) {
if ((opt & TERMIOS_FLUSH) && ld->flush_buffer)
ld->flush_buffer(tty);
tty_ldisc_deref(ld);
}
-
+
if (opt & TERMIOS_WAIT) {
tty_wait_until_sent(tty, 0);
if (signal_pending(current))
return 0;
}
-static int get_termio(struct tty_struct * tty, struct termio __user * termio)
+static int get_termio(struct tty_struct *tty, struct termio __user *termio)
{
if (kernel_termios_to_user_termio(termio, tty->termios))
return -EFAULT;
return 0;
}
-static unsigned long inq_canon(struct tty_struct * tty)
+static unsigned long inq_canon(struct tty_struct *tty)
{
int nr, head, tail;
*
* The "sg_flags" translation is a joke..
*/
-static int get_sgflags(struct tty_struct * tty)
+static int get_sgflags(struct tty_struct *tty)
{
int flags = 0;
return flags;
}
-static int get_sgttyb(struct tty_struct * tty, struct sgttyb __user * sgttyb)
+static int get_sgttyb(struct tty_struct *tty, struct sgttyb __user *sgttyb)
{
struct sgttyb tmp;
tmp.sg_kill = tty->termios->c_cc[VKILL];
tmp.sg_flags = get_sgflags(tty);
mutex_unlock(&tty->termios_mutex);
-
+
return copy_to_user(sgttyb, &tmp, sizeof(tmp)) ? -EFAULT : 0;
}
-static void set_sgflags(struct ktermios * termios, int flags)
+static void set_sgflags(struct ktermios *termios, int flags)
{
termios->c_iflag = ICRNL | IXON;
termios->c_oflag = 0;
* Locking: termios_sem
*/
-static int set_sgttyb(struct tty_struct * tty, struct sgttyb __user * sgttyb)
+static int set_sgttyb(struct tty_struct *tty, struct sgttyb __user *sgttyb)
{
int retval;
struct sgttyb tmp;
retval = tty_check_change(tty);
if (retval)
return retval;
-
+
if (copy_from_user(&tmp, sgttyb, sizeof(tmp)))
return -EFAULT;
set_sgflags(&termios, tmp.sg_flags);
/* Try and encode into Bfoo format */
#ifdef BOTHER
- tty_termios_encode_baud_rate(&termios, termios.c_ispeed, termios.c_ospeed);
+ tty_termios_encode_baud_rate(&termios, termios.c_ispeed,
+ termios.c_ospeed);
#endif
mutex_unlock(&tty->termios_mutex);
change_termios(tty, &termios);
#endif
#ifdef TIOCGETC
-static int get_tchars(struct tty_struct * tty, struct tchars __user * tchars)
+static int get_tchars(struct tty_struct *tty, struct tchars __user *tchars)
{
struct tchars tmp;
return copy_to_user(tchars, &tmp, sizeof(tmp)) ? -EFAULT : 0;
}
-static int set_tchars(struct tty_struct * tty, struct tchars __user * tchars)
+static int set_tchars(struct tty_struct *tty, struct tchars __user *tchars)
{
struct tchars tmp;
#endif
#ifdef TIOCGLTC
-static int get_ltchars(struct tty_struct * tty, struct ltchars __user * ltchars)
+static int get_ltchars(struct tty_struct *tty, struct ltchars __user *ltchars)
{
struct ltchars tmp;
tmp.t_suspc = tty->termios->c_cc[VSUSP];
- tmp.t_dsuspc = tty->termios->c_cc[VSUSP]; /* what is dsuspc anyway? */
+ /* what is dsuspc anyway? */
+ tmp.t_dsuspc = tty->termios->c_cc[VSUSP];
tmp.t_rprntc = tty->termios->c_cc[VREPRINT];
- tmp.t_flushc = tty->termios->c_cc[VEOL2]; /* what is flushc anyway? */
+ /* what is flushc anyway? */
+ tmp.t_flushc = tty->termios->c_cc[VEOL2];
tmp.t_werasc = tty->termios->c_cc[VWERASE];
tmp.t_lnextc = tty->termios->c_cc[VLNEXT];
return copy_to_user(ltchars, &tmp, sizeof(tmp)) ? -EFAULT : 0;
}
-static int set_ltchars(struct tty_struct * tty, struct ltchars __user * ltchars)
+static int set_ltchars(struct tty_struct *tty, struct ltchars __user *ltchars)
{
struct ltchars tmp;
return -EFAULT;
tty->termios->c_cc[VSUSP] = tmp.t_suspc;
- tty->termios->c_cc[VEOL2] = tmp.t_dsuspc; /* what is dsuspc anyway? */
+ /* what is dsuspc anyway? */
+ tty->termios->c_cc[VEOL2] = tmp.t_dsuspc;
tty->termios->c_cc[VREPRINT] = tmp.t_rprntc;
- tty->termios->c_cc[VEOL2] = tmp.t_flushc; /* what is flushc anyway? */
+ /* what is flushc anyway? */
+ tty->termios->c_cc[VEOL2] = tmp.t_flushc;
tty->termios->c_cc[VWERASE] = tmp.t_werasc;
tty->termios->c_cc[VLNEXT] = tmp.t_lnextc;
return 0;
* consistent mode setting.
*/
-int tty_mode_ioctl(struct tty_struct * tty, struct file *file,
+int tty_mode_ioctl(struct tty_struct *tty, struct file *file,
unsigned int cmd, unsigned long arg)
{
- struct tty_struct * real_tty;
+ struct tty_struct *real_tty;
void __user *p = (void __user *)arg;
if (tty->driver->type == TTY_DRIVER_TYPE_PTY &&
switch (cmd) {
#ifdef TIOCGETP
- case TIOCGETP:
- return get_sgttyb(real_tty, (struct sgttyb __user *) arg);
- case TIOCSETP:
- case TIOCSETN:
- return set_sgttyb(real_tty, (struct sgttyb __user *) arg);
+ case TIOCGETP:
+ return get_sgttyb(real_tty, (struct sgttyb __user *) arg);
+ case TIOCSETP:
+ case TIOCSETN:
+ return set_sgttyb(real_tty, (struct sgttyb __user *) arg);
#endif
#ifdef TIOCGETC
- case TIOCGETC:
- return get_tchars(real_tty, p);
- case TIOCSETC:
- return set_tchars(real_tty, p);
+ case TIOCGETC:
+ return get_tchars(real_tty, p);
+ case TIOCSETC:
+ return set_tchars(real_tty, p);
#endif
#ifdef TIOCGLTC
- case TIOCGLTC:
- return get_ltchars(real_tty, p);
- case TIOCSLTC:
- return set_ltchars(real_tty, p);
+ case TIOCGLTC:
+ return get_ltchars(real_tty, p);
+ case TIOCSLTC:
+ return set_ltchars(real_tty, p);
#endif
- case TCSETSF:
- return set_termios(real_tty, p, TERMIOS_FLUSH | TERMIOS_WAIT | TERMIOS_OLD);
- case TCSETSW:
- return set_termios(real_tty, p, TERMIOS_WAIT | TERMIOS_OLD);
- case TCSETS:
- return set_termios(real_tty, p, TERMIOS_OLD);
+ case TCSETSF:
+ return set_termios(real_tty, p, TERMIOS_FLUSH | TERMIOS_WAIT | TERMIOS_OLD);
+ case TCSETSW:
+ return set_termios(real_tty, p, TERMIOS_WAIT | TERMIOS_OLD);
+ case TCSETS:
+ return set_termios(real_tty, p, TERMIOS_OLD);
#ifndef TCGETS2
- case TCGETS:
- if (kernel_termios_to_user_termios((struct termios __user *)arg, real_tty->termios))
- return -EFAULT;
- return 0;
+ case TCGETS:
+ if (kernel_termios_to_user_termios((struct termios __user *)arg, real_tty->termios))
+ return -EFAULT;
+ return 0;
#else
- case TCGETS:
- if (kernel_termios_to_user_termios_1((struct termios __user *)arg, real_tty->termios))
- return -EFAULT;
- return 0;
- case TCGETS2:
- if (kernel_termios_to_user_termios((struct termios2 __user *)arg, real_tty->termios))
- return -EFAULT;
- return 0;
- case TCSETSF2:
- return set_termios(real_tty, p, TERMIOS_FLUSH | TERMIOS_WAIT);
- case TCSETSW2:
- return set_termios(real_tty, p, TERMIOS_WAIT);
- case TCSETS2:
- return set_termios(real_tty, p, 0);
+ case TCGETS:
+ if (kernel_termios_to_user_termios_1((struct termios __user *)arg, real_tty->termios))
+ return -EFAULT;
+ return 0;
+ case TCGETS2:
+ if (kernel_termios_to_user_termios((struct termios2 __user *)arg, real_tty->termios))
+ return -EFAULT;
+ return 0;
+ case TCSETSF2:
+ return set_termios(real_tty, p, TERMIOS_FLUSH | TERMIOS_WAIT);
+ case TCSETSW2:
+ return set_termios(real_tty, p, TERMIOS_WAIT);
+ case TCSETS2:
+ return set_termios(real_tty, p, 0);
#endif
- case TCGETA:
- return get_termio(real_tty, p);
- case TCSETAF:
- return set_termios(real_tty, p, TERMIOS_FLUSH | TERMIOS_WAIT | TERMIOS_TERMIO);
- case TCSETAW:
- return set_termios(real_tty, p, TERMIOS_WAIT | TERMIOS_TERMIO);
- case TCSETA:
- return set_termios(real_tty, p, TERMIOS_TERMIO);
+ case TCGETA:
+ return get_termio(real_tty, p);
+ case TCSETAF:
+ return set_termios(real_tty, p, TERMIOS_FLUSH | TERMIOS_WAIT | TERMIOS_TERMIO);
+ case TCSETAW:
+ return set_termios(real_tty, p, TERMIOS_WAIT | TERMIOS_TERMIO);
+ case TCSETA:
+ return set_termios(real_tty, p, TERMIOS_TERMIO);
#ifndef TCGETS2
- case TIOCGLCKTRMIOS:
- if (kernel_termios_to_user_termios((struct termios __user *)arg, real_tty->termios_locked))
- return -EFAULT;
- return 0;
-
- case TIOCSLCKTRMIOS:
- if (!capable(CAP_SYS_ADMIN))
- return -EPERM;
- if (user_termios_to_kernel_termios(real_tty->termios_locked, (struct termios __user *) arg))
- return -EFAULT;
- return 0;
+ case TIOCGLCKTRMIOS:
+ if (kernel_termios_to_user_termios((struct termios __user *)arg, real_tty->termios_locked))
+ return -EFAULT;
+ return 0;
+ case TIOCSLCKTRMIOS:
+ if (!capable(CAP_SYS_ADMIN))
+ return -EPERM;
+ if (user_termios_to_kernel_termios(real_tty->termios_locked,
+ (struct termios __user *) arg))
+ return -EFAULT;
+ return 0;
#else
- case TIOCGLCKTRMIOS:
- if (kernel_termios_to_user_termios_1((struct termios __user *)arg, real_tty->termios_locked))
- return -EFAULT;
- return 0;
-
- case TIOCSLCKTRMIOS:
- if (!capable(CAP_SYS_ADMIN))
- return -EPERM;
- if (user_termios_to_kernel_termios_1(real_tty->termios_locked, (struct termios __user *) arg))
- return -EFAULT;
+ case TIOCGLCKTRMIOS:
+ if (kernel_termios_to_user_termios_1((struct termios __user *)arg, real_tty->termios_locked))
+ return -EFAULT;
+ return 0;
+ case TIOCSLCKTRMIOS:
+ if (!capable(CAP_SYS_ADMIN))
+ return -EPERM;
+ if (user_termios_to_kernel_termios_1(real_tty->termios_locked,
+ (struct termios __user *) arg))
+ return -EFAULT;
return 0;
#endif
- case TIOCGSOFTCAR:
- return put_user(C_CLOCAL(tty) ? 1 : 0, (int __user *)arg);
- case TIOCSSOFTCAR:
- if (get_user(arg, (unsigned int __user *) arg))
- return -EFAULT;
- mutex_lock(&tty->termios_mutex);
- tty->termios->c_cflag =
- ((tty->termios->c_cflag & ~CLOCAL) |
- (arg ? CLOCAL : 0));
- mutex_unlock(&tty->termios_mutex);
- return 0;
- default:
- return -ENOIOCTLCMD;
+ case TIOCGSOFTCAR:
+ return put_user(C_CLOCAL(tty) ? 1 : 0,
+ (int __user *)arg);
+ case TIOCSSOFTCAR:
+ if (get_user(arg, (unsigned int __user *) arg))
+ return -EFAULT;
+ mutex_lock(&tty->termios_mutex);
+ tty->termios->c_cflag =
+ ((tty->termios->c_cflag & ~CLOCAL) |
+ (arg ? CLOCAL : 0));
+ mutex_unlock(&tty->termios_mutex);
+ return 0;
+ default:
+ return -ENOIOCTLCMD;
}
}
-
EXPORT_SYMBOL_GPL(tty_mode_ioctl);
int tty_perform_flush(struct tty_struct *tty, unsigned long arg)
tty_ldisc_deref(ld);
return 0;
}
-
EXPORT_SYMBOL_GPL(tty_perform_flush);
-int n_tty_ioctl(struct tty_struct * tty, struct file * file,
+int n_tty_ioctl(struct tty_struct *tty, struct file *file,
unsigned int cmd, unsigned long arg)
{
- struct tty_struct * real_tty;
+ struct tty_struct *real_tty;
int retval;
if (tty->driver->type == TTY_DRIVER_TYPE_PTY &&
real_tty = tty;
switch (cmd) {
- case TCXONC:
- retval = tty_check_change(tty);
- if (retval)
- return retval;
- switch (arg) {
- case TCOOFF:
- if (!tty->flow_stopped) {
- tty->flow_stopped = 1;
- stop_tty(tty);
- }
- break;
- case TCOON:
- if (tty->flow_stopped) {
- tty->flow_stopped = 0;
- start_tty(tty);
- }
- break;
- case TCIOFF:
- if (STOP_CHAR(tty) != __DISABLED_CHAR)
- return send_prio_char(tty, STOP_CHAR(tty));
- break;
- case TCION:
- if (START_CHAR(tty) != __DISABLED_CHAR)
- return send_prio_char(tty, START_CHAR(tty));
- break;
- default:
- return -EINVAL;
+ case TCXONC:
+ retval = tty_check_change(tty);
+ if (retval)
+ return retval;
+ switch (arg) {
+ case TCOOFF:
+ if (!tty->flow_stopped) {
+ tty->flow_stopped = 1;
+ stop_tty(tty);
}
- return 0;
- case TCFLSH:
- return tty_perform_flush(tty, arg);
- case TIOCOUTQ:
- return put_user(tty->driver->chars_in_buffer ?
- tty->driver->chars_in_buffer(tty) : 0,
- (int __user *) arg);
- case TIOCINQ:
- retval = tty->read_cnt;
- if (L_ICANON(tty))
- retval = inq_canon(tty);
- return put_user(retval, (unsigned int __user *) arg);
- case TIOCPKT:
- {
- int pktmode;
-
- if (tty->driver->type != TTY_DRIVER_TYPE_PTY ||
- tty->driver->subtype != PTY_TYPE_MASTER)
- return -ENOTTY;
- if (get_user(pktmode, (int __user *) arg))
- return -EFAULT;
- if (pktmode) {
- if (!tty->packet) {
- tty->packet = 1;
- tty->link->ctrl_status = 0;
- }
- } else
- tty->packet = 0;
- return 0;
- }
+ break;
+ case TCOON:
+ if (tty->flow_stopped) {
+ tty->flow_stopped = 0;
+ start_tty(tty);
+ }
+ break;
+ case TCIOFF:
+ if (STOP_CHAR(tty) != __DISABLED_CHAR)
+ return send_prio_char(tty, STOP_CHAR(tty));
+ break;
+ case TCION:
+ if (START_CHAR(tty) != __DISABLED_CHAR)
+ return send_prio_char(tty, START_CHAR(tty));
+ break;
default:
- /* Try the mode commands */
- return tty_mode_ioctl(tty, file, cmd, arg);
+ return -EINVAL;
}
+ return 0;
+ case TCFLSH:
+ return tty_perform_flush(tty, arg);
+ case TIOCOUTQ:
+ return put_user(tty->driver->chars_in_buffer ?
+ tty->driver->chars_in_buffer(tty) : 0,
+ (int __user *) arg);
+ case TIOCINQ:
+ retval = tty->read_cnt;
+ if (L_ICANON(tty))
+ retval = inq_canon(tty);
+ return put_user(retval, (unsigned int __user *) arg);
+ case TIOCPKT:
+ {
+ int pktmode;
+
+ if (tty->driver->type != TTY_DRIVER_TYPE_PTY ||
+ tty->driver->subtype != PTY_TYPE_MASTER)
+ return -ENOTTY;
+ if (get_user(pktmode, (int __user *) arg))
+ return -EFAULT;
+ if (pktmode) {
+ if (!tty->packet) {
+ tty->packet = 1;
+ tty->link->ctrl_status = 0;
+ }
+ } else
+ tty->packet = 0;
+ return 0;
+ }
+ default:
+ /* Try the mode commands */
+ return tty_mode_ioctl(tty, file, cmd, arg);
+ }
}
-
EXPORT_SYMBOL(n_tty_ioctl);
int dca_sysfs_add_req(struct dca_provider *dca, struct device *dev, int slot)
{
- struct class_device *cd;
+ struct device *cd;
- cd = class_device_create(dca_class, dca->cd, MKDEV(0, slot + 1),
- dev, "requester%d", slot);
+ cd = device_create(dca_class, dca->cd, MKDEV(0, slot + 1),
+ "requester%d", slot);
if (IS_ERR(cd))
return PTR_ERR(cd);
return 0;
void dca_sysfs_remove_req(struct dca_provider *dca, int slot)
{
- class_device_destroy(dca_class, MKDEV(0, slot + 1));
+ device_destroy(dca_class, MKDEV(0, slot + 1));
}
int dca_sysfs_add_provider(struct dca_provider *dca, struct device *dev)
{
- struct class_device *cd;
+ struct device *cd;
int err = 0;
idr_try_again:
return err;
}
- cd = class_device_create(dca_class, NULL, MKDEV(0, 0),
- dev, "dca%d", dca->id);
+ cd = device_create(dca_class, dev, MKDEV(0, 0), "dca%d", dca->id);
if (IS_ERR(cd)) {
spin_lock(&dca_idr_lock);
idr_remove(&dca_idr, dca->id);
void dca_sysfs_remove_provider(struct dca_provider *dca)
{
- class_device_unregister(dca->cd);
+ device_unregister(dca->cd);
dca->cd = NULL;
spin_lock(&dca_idr_lock);
idr_remove(&dca_idr, dca->id);
list_add(&dev->list, &dmi_devices);
}
+static void __init dmi_save_extended_devices(const struct dmi_header *dm)
+{
+ const u8 *d = (u8*) dm + 5;
+ struct dmi_device *dev;
+
+ /* Skip disabled device */
+ if ((*d & 0x80) == 0)
+ return;
+
+ dev = dmi_alloc(sizeof(*dev));
+ if (!dev) {
+ printk(KERN_ERR "dmi_save_extended_devices: out of memory.\n");
+ return;
+ }
+
+ dev->type = *d-- & 0x7f;
+ dev->name = dmi_string(dm, *d);
+ dev->device_data = NULL;
+
+ list_add(&dev->list, &dmi_devices);
+}
+
/*
* Process a DMI table entry. Right now all we care about are the BIOS
* and machine entries. For 2.5 we should pull the smbus controller info
break;
case 38: /* IPMI Device Information */
dmi_save_ipmi_device(dm);
+ break;
+ case 41: /* Onboard Devices Extended Information */
+ dmi_save_extended_devices(dm);
}
}
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/tty.h>
#include <linux/major.h>
#include <linux/interrupt.h>
static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
{
- int offset = n * sizeof (struct mlx4_cqe);
-
- if (buf->buf.nbufs == 1)
- return buf->buf.u.direct.buf + offset;
- else
- return buf->buf.u.page_list[offset >> PAGE_SHIFT].buf +
- (offset & (PAGE_SIZE - 1));
+ return mlx4_buf_offset(&buf->buf, n * sizeof (struct mlx4_cqe));
}
static void *get_cqe(struct mlx4_ib_cq *cq, int n)
is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
MLX4_CQE_OPCODE_ERROR;
+ if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_OPCODE_NOP &&
+ is_send)) {
+ printk(KERN_WARNING "Completion for NOP opcode detected!\n");
+ return -EINVAL;
+ }
+
if (!*cur_qp ||
(be32_to_cpu(cqe->my_qpn) & 0xffffff) != (*cur_qp)->mqp.qpn) {
/*
if (is_send) {
wq = &(*cur_qp)->sq;
- wqe_ctr = be16_to_cpu(cqe->wqe_index);
- wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
+ if (!(*cur_qp)->sq_signal_bits) {
+ wqe_ctr = be16_to_cpu(cqe->wqe_index);
+ wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
+ }
wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
++wq->tail;
} else if ((*cur_qp)->ibqp.srq) {
u32 doorbell_qpn;
__be32 sq_signal_bits;
+ unsigned sq_next_wqe;
+ int sq_max_wqes_per_wr;
int sq_spare_wqes;
struct mlx4_ib_wq sq;
* SOFTWARE.
*/
+#include <linux/log2.h>
+
#include <rdma/ib_cache.h>
#include <rdma/ib_pack.h>
static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
{
- if (qp->buf.nbufs == 1)
- return qp->buf.u.direct.buf + offset;
- else
- return qp->buf.u.page_list[offset >> PAGE_SHIFT].buf +
- (offset & (PAGE_SIZE - 1));
+ return mlx4_buf_offset(&qp->buf, offset);
}
static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
/*
* Stamp a SQ WQE so that it is invalid if prefetched by marking the
- * first four bytes of every 64 byte chunk with 0xffffffff, except for
- * the very first chunk of the WQE.
+ * first four bytes of every 64 byte chunk with
+ * 0x7FFFFFF | (invalid_ownership_value << 31).
+ *
+ * When the max work request size is less than or equal to the WQE
+ * basic block size, as an optimization, we can stamp all WQEs with
+ * 0xffffffff, and skip the very first chunk of each WQE.
*/
-static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
+static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
{
- u32 *wqe = get_send_wqe(qp, n);
+ u32 *wqe;
int i;
+ int s;
+ int ind;
+ void *buf;
+ __be32 stamp;
+
+ s = roundup(size, 1U << qp->sq.wqe_shift);
+ if (qp->sq_max_wqes_per_wr > 1) {
+ for (i = 0; i < s; i += 64) {
+ ind = (i >> qp->sq.wqe_shift) + n;
+ stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
+ cpu_to_be32(0xffffffff);
+ buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
+ wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
+ *wqe = stamp;
+ }
+ } else {
+ buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
+ for (i = 64; i < s; i += 64) {
+ wqe = buf + i;
+ *wqe = 0xffffffff;
+ }
+ }
+}
+
+static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
+{
+ struct mlx4_wqe_ctrl_seg *ctrl;
+ struct mlx4_wqe_inline_seg *inl;
+ void *wqe;
+ int s;
+
+ ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
+ s = sizeof(struct mlx4_wqe_ctrl_seg);
- for (i = 16; i < 1 << (qp->sq.wqe_shift - 2); i += 16)
- wqe[i] = 0xffffffff;
+ if (qp->ibqp.qp_type == IB_QPT_UD) {
+ struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
+ struct mlx4_av *av = (struct mlx4_av *)dgram->av;
+ memset(dgram, 0, sizeof *dgram);
+ av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
+ s += sizeof(struct mlx4_wqe_datagram_seg);
+ }
+
+ /* Pad the remainder of the WQE with an inline data segment. */
+ if (size > s) {
+ inl = wqe + s;
+ inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
+ }
+ ctrl->srcrb_flags = 0;
+ ctrl->fence_size = size / 16;
+ /*
+ * Make sure descriptor is fully written before setting ownership bit
+ * (because HW can start executing as soon as we do).
+ */
+ wmb();
+
+ ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
+ (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
+
+ stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
+}
+
+/* Post NOP WQE to prevent wrap-around in the middle of WR */
+static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
+{
+ unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
+ if (unlikely(s < qp->sq_max_wqes_per_wr)) {
+ post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
+ ind += s;
+ }
+ return ind;
}
static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
enum ib_qp_type type, struct mlx4_ib_qp *qp)
{
+ int s;
+
/* Sanity check SQ size before proceeding */
if (cap->max_send_wr > dev->dev->caps.max_wqes ||
cap->max_send_sge > dev->dev->caps.max_sq_sg ||
cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
return -EINVAL;
- qp->sq.wqe_shift = ilog2(roundup_pow_of_two(max(cap->max_send_sge *
- sizeof (struct mlx4_wqe_data_seg),
- cap->max_inline_data +
- sizeof (struct mlx4_wqe_inline_seg)) +
- send_wqe_overhead(type)));
- qp->sq.max_gs = ((1 << qp->sq.wqe_shift) - send_wqe_overhead(type)) /
- sizeof (struct mlx4_wqe_data_seg);
+ s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
+ cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
+ send_wqe_overhead(type);
/*
- * We need to leave 2 KB + 1 WQE of headroom in the SQ to
- * allow HW to prefetch.
+ * Hermon supports shrinking WQEs, such that a single work
+ * request can include multiple units of 1 << wqe_shift. This
+ * way, work requests can differ in size, and do not have to
+ * be a power of 2 in size, saving memory and speeding up send
+ * WR posting. Unfortunately, if we do this then the
+ * wqe_index field in CQEs can't be used to look up the WR ID
+ * anymore, so we do this only if selective signaling is off.
+ *
+ * Further, on 32-bit platforms, we can't use vmap() to make
+ * the QP buffer virtually contigious. Thus we have to use
+ * constant-sized WRs to make sure a WR is always fully within
+ * a single page-sized chunk.
+ *
+ * Finally, we use NOP work requests to pad the end of the
+ * work queue, to avoid wrap-around in the middle of WR. We
+ * set NEC bit to avoid getting completions with error for
+ * these NOP WRs, but since NEC is only supported starting
+ * with firmware 2.2.232, we use constant-sized WRs for older
+ * firmware.
+ *
+ * And, since MLX QPs only support SEND, we use constant-sized
+ * WRs in this case.
+ *
+ * We look for the smallest value of wqe_shift such that the
+ * resulting number of wqes does not exceed device
+ * capabilities.
+ *
+ * We set WQE size to at least 64 bytes, this way stamping
+ * invalidates each WQE.
*/
- qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + 1;
- qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr + qp->sq_spare_wqes);
+ if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
+ qp->sq_signal_bits && BITS_PER_LONG == 64 &&
+ type != IB_QPT_SMI && type != IB_QPT_GSI)
+ qp->sq.wqe_shift = ilog2(64);
+ else
+ qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
+
+ for (;;) {
+ if (1 << qp->sq.wqe_shift > dev->dev->caps.max_sq_desc_sz)
+ return -EINVAL;
+
+ qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
+
+ /*
+ * We need to leave 2 KB + 1 WR of headroom in the SQ to
+ * allow HW to prefetch.
+ */
+ qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
+ qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
+ qp->sq_max_wqes_per_wr +
+ qp->sq_spare_wqes);
+
+ if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
+ break;
+
+ if (qp->sq_max_wqes_per_wr <= 1)
+ return -EINVAL;
+
+ ++qp->sq.wqe_shift;
+ }
+
+ qp->sq.max_gs = ((qp->sq_max_wqes_per_wr << qp->sq.wqe_shift) -
+ send_wqe_overhead(type)) / sizeof (struct mlx4_wqe_data_seg);
qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
(qp->sq.wqe_cnt << qp->sq.wqe_shift);
qp->sq.offset = 0;
}
- cap->max_send_wr = qp->sq.max_post = qp->sq.wqe_cnt - qp->sq_spare_wqes;
+ cap->max_send_wr = qp->sq.max_post =
+ (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
cap->max_send_sge = qp->sq.max_gs;
/* We don't support inline sends for kernel QPs (yet) */
cap->max_inline_data = 0;
qp->rq.tail = 0;
qp->sq.head = 0;
qp->sq.tail = 0;
+ qp->sq_next_wqe = 0;
+
+ if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
+ qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
+ else
+ qp->sq_signal_bits = 0;
err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
if (err)
*/
qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
- if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
- qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
- else
- qp->sq_signal_bits = 0;
-
qp->mqp.event = mlx4_ib_qp_event;
return 0;
ctrl = get_send_wqe(qp, i);
ctrl->owner_opcode = cpu_to_be32(1 << 31);
- stamp_send_wqe(qp, i);
+ stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
}
}
qp->rq.tail = 0;
qp->sq.head = 0;
qp->sq.tail = 0;
+ qp->sq_next_wqe = 0;
if (!ibqp->srq)
*qp->db.db = 0;
}
unsigned long flags;
int nreq;
int err = 0;
- int ind;
- int size;
+ unsigned ind;
+ int uninitialized_var(stamp);
+ int uninitialized_var(size);
int i;
spin_lock_irqsave(&qp->sq.lock, flags);
- ind = qp->sq.head;
+ ind = qp->sq_next_wqe;
for (nreq = 0; wr; ++nreq, wr = wr->next) {
if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
}
ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
- qp->sq.wrid[ind & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
+ qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
ctrl->srcrb_flags =
(wr->send_flags & IB_SEND_SIGNALED ?
ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
(ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
+ stamp = ind + qp->sq_spare_wqes;
+ ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
+
/*
* We can improve latency by not stamping the last
* send queue WQE until after ringing the doorbell, so
* only stamp here if there are still more WQEs to post.
+ *
+ * Same optimization applies to padding with NOP wqe
+ * in case of WQE shrinking (used to prevent wrap-around
+ * in the middle of WR).
*/
- if (wr->next)
- stamp_send_wqe(qp, (ind + qp->sq_spare_wqes) &
- (qp->sq.wqe_cnt - 1));
+ if (wr->next) {
+ stamp_send_wqe(qp, stamp, size * 16);
+ ind = pad_wraparound(qp, ind);
+ }
- ++ind;
}
out:
*/
mmiowb();
- stamp_send_wqe(qp, (ind + qp->sq_spare_wqes - 1) &
- (qp->sq.wqe_cnt - 1));
+ stamp_send_wqe(qp, stamp, size * 16);
+
+ ind = pad_wraparound(qp, ind);
+ qp->sq_next_wqe = ind;
}
spin_unlock_irqrestore(&qp->sq.lock, flags);
static void *get_wqe(struct mlx4_ib_srq *srq, int n)
{
- int offset = n << srq->msrq.wqe_shift;
-
- if (srq->buf.nbufs == 1)
- return srq->buf.u.direct.buf + offset;
- else
- return srq->buf.u.page_list[offset >> PAGE_SHIFT].buf +
- (offset & (PAGE_SIZE - 1));
+ return mlx4_buf_offset(&srq->buf, n << srq->msrq.wqe_shift);
}
static void mlx4_ib_srq_event(struct mlx4_srq *srq, enum mlx4_event type)
struct ipoib_tx_buf {
struct sk_buff *skb;
- u64 mapping;
+ u64 mapping[MAX_SKB_FRAGS + 1];
};
struct ib_cm_id;
struct ipoib_tx_buf *tx_ring;
unsigned tx_head;
unsigned tx_tail;
- struct ib_sge tx_sge;
+ struct ib_sge tx_sge[MAX_SKB_FRAGS + 1];
struct ib_send_wr tx_wr;
unsigned tx_outstanding;
{
struct ib_send_wr *bad_wr;
- priv->tx_sge.addr = addr;
- priv->tx_sge.length = len;
+ priv->tx_sge[0].addr = addr;
+ priv->tx_sge[0].length = len;
priv->tx_wr.wr_id = wr_id | IPOIB_OP_CM;
return;
}
- tx_req->mapping = addr;
+ tx_req->mapping[0] = addr;
if (unlikely(post_send(priv, tx, tx->tx_head & (ipoib_sendq_size - 1),
addr, skb->len))) {
tx_req = &tx->tx_ring[wr_id];
- ib_dma_unmap_single(priv->ca, tx_req->mapping, tx_req->skb->len, DMA_TO_DEVICE);
+ ib_dma_unmap_single(priv->ca, tx_req->mapping[0], tx_req->skb->len, DMA_TO_DEVICE);
/* FIXME: is this right? Shouldn't we only increment on success? */
++dev->stats.tx_packets;
while ((int) p->tx_tail - (int) p->tx_head < 0) {
tx_req = &p->tx_ring[p->tx_tail & (ipoib_sendq_size - 1)];
- ib_dma_unmap_single(priv->ca, tx_req->mapping, tx_req->skb->len,
+ ib_dma_unmap_single(priv->ca, tx_req->mapping[0], tx_req->skb->len,
DMA_TO_DEVICE);
dev_kfree_skb_any(tx_req->skb);
++p->tx_tail;
"for buf %d\n", wr_id);
}
+static int ipoib_dma_map_tx(struct ib_device *ca,
+ struct ipoib_tx_buf *tx_req)
+{
+ struct sk_buff *skb = tx_req->skb;
+ u64 *mapping = tx_req->mapping;
+ int i;
+
+ mapping[0] = ib_dma_map_single(ca, skb->data, skb_headlen(skb),
+ DMA_TO_DEVICE);
+ if (unlikely(ib_dma_mapping_error(ca, mapping[0])))
+ return -EIO;
+
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+ mapping[i + 1] = ib_dma_map_page(ca, frag->page,
+ frag->page_offset, frag->size,
+ DMA_TO_DEVICE);
+ if (unlikely(ib_dma_mapping_error(ca, mapping[i + 1])))
+ goto partial_error;
+ }
+ return 0;
+
+partial_error:
+ ib_dma_unmap_single(ca, mapping[0], skb_headlen(skb), DMA_TO_DEVICE);
+
+ for (; i > 0; --i) {
+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
+ ib_dma_unmap_page(ca, mapping[i], frag->size, DMA_TO_DEVICE);
+ }
+ return -EIO;
+}
+
+static void ipoib_dma_unmap_tx(struct ib_device *ca,
+ struct ipoib_tx_buf *tx_req)
+{
+ struct sk_buff *skb = tx_req->skb;
+ u64 *mapping = tx_req->mapping;
+ int i;
+
+ ib_dma_unmap_single(ca, mapping[0], skb_headlen(skb), DMA_TO_DEVICE);
+
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+ ib_dma_unmap_page(ca, mapping[i + 1], frag->size,
+ DMA_TO_DEVICE);
+ }
+}
+
static void ipoib_ib_handle_tx_wc(struct net_device *dev, struct ib_wc *wc)
{
struct ipoib_dev_priv *priv = netdev_priv(dev);
tx_req = &priv->tx_ring[wr_id];
- ib_dma_unmap_single(priv->ca, tx_req->mapping,
- tx_req->skb->len, DMA_TO_DEVICE);
+ ipoib_dma_unmap_tx(priv->ca, tx_req);
++dev->stats.tx_packets;
dev->stats.tx_bytes += tx_req->skb->len;
static inline int post_send(struct ipoib_dev_priv *priv,
unsigned int wr_id,
struct ib_ah *address, u32 qpn,
- u64 addr, int len)
+ u64 *mapping, int headlen,
+ skb_frag_t *frags,
+ int nr_frags)
{
struct ib_send_wr *bad_wr;
+ int i;
- priv->tx_sge.addr = addr;
- priv->tx_sge.length = len;
-
- priv->tx_wr.wr_id = wr_id;
- priv->tx_wr.wr.ud.remote_qpn = qpn;
- priv->tx_wr.wr.ud.ah = address;
+ priv->tx_sge[0].addr = mapping[0];
+ priv->tx_sge[0].length = headlen;
+ for (i = 0; i < nr_frags; ++i) {
+ priv->tx_sge[i + 1].addr = mapping[i + 1];
+ priv->tx_sge[i + 1].length = frags[i].size;
+ }
+ priv->tx_wr.num_sge = nr_frags + 1;
+ priv->tx_wr.wr_id = wr_id;
+ priv->tx_wr.wr.ud.remote_qpn = qpn;
+ priv->tx_wr.wr.ud.ah = address;
return ib_post_send(priv->qp, &priv->tx_wr, &bad_wr);
}
{
struct ipoib_dev_priv *priv = netdev_priv(dev);
struct ipoib_tx_buf *tx_req;
- u64 addr;
if (unlikely(skb->len > priv->mcast_mtu + IPOIB_ENCAP_LEN)) {
ipoib_warn(priv, "packet len %d (> %d) too long to send, dropping\n",
*/
tx_req = &priv->tx_ring[priv->tx_head & (ipoib_sendq_size - 1)];
tx_req->skb = skb;
- addr = ib_dma_map_single(priv->ca, skb->data, skb->len,
- DMA_TO_DEVICE);
- if (unlikely(ib_dma_mapping_error(priv->ca, addr))) {
+ if (unlikely(ipoib_dma_map_tx(priv->ca, tx_req))) {
++dev->stats.tx_errors;
dev_kfree_skb_any(skb);
return;
}
- tx_req->mapping = addr;
if (unlikely(post_send(priv, priv->tx_head & (ipoib_sendq_size - 1),
- address->ah, qpn, addr, skb->len))) {
+ address->ah, qpn,
+ tx_req->mapping, skb_headlen(skb),
+ skb_shinfo(skb)->frags, skb_shinfo(skb)->nr_frags))) {
ipoib_warn(priv, "post_send failed\n");
++dev->stats.tx_errors;
- ib_dma_unmap_single(priv->ca, addr, skb->len, DMA_TO_DEVICE);
+ ipoib_dma_unmap_tx(priv->ca, tx_req);
dev_kfree_skb_any(skb);
} else {
dev->trans_start = jiffies;
while ((int) priv->tx_tail - (int) priv->tx_head < 0) {
tx_req = &priv->tx_ring[priv->tx_tail &
(ipoib_sendq_size - 1)];
- ib_dma_unmap_single(priv->ca,
- tx_req->mapping,
- tx_req->skb->len,
- DMA_TO_DEVICE);
+ ipoib_dma_unmap_tx(priv->ca, tx_req);
dev_kfree_skb_any(tx_req->skb);
++priv->tx_tail;
--priv->tx_outstanding;
dev->addr_len = INFINIBAND_ALEN;
dev->type = ARPHRD_INFINIBAND;
dev->tx_queue_len = ipoib_sendq_size * 2;
- dev->features = NETIF_F_VLAN_CHALLENGED | NETIF_F_LLTX;
+ dev->features = (NETIF_F_VLAN_CHALLENGED |
+ NETIF_F_LLTX |
+ NETIF_F_HIGHDMA);
/* MTU will be reset when mcast join happens */
dev->mtu = IPOIB_PACKET_SIZE - IPOIB_ENCAP_LEN;
};
int ret, size;
+ int i;
priv->pd = ib_alloc_pd(priv->ca);
if (IS_ERR(priv->pd)) {
init_attr.send_cq = priv->cq;
init_attr.recv_cq = priv->cq;
+ if (dev->features & NETIF_F_SG)
+ init_attr.cap.max_send_sge = MAX_SKB_FRAGS + 1;
+
priv->qp = ib_create_qp(priv->pd, &init_attr);
if (IS_ERR(priv->qp)) {
printk(KERN_WARNING "%s: failed to create QP\n", ca->name);
priv->dev->dev_addr[2] = (priv->qp->qp_num >> 8) & 0xff;
priv->dev->dev_addr[3] = (priv->qp->qp_num ) & 0xff;
- priv->tx_sge.lkey = priv->mr->lkey;
+ for (i = 0; i < MAX_SKB_FRAGS + 1; ++i)
+ priv->tx_sge[i].lkey = priv->mr->lkey;
priv->tx_wr.opcode = IB_WR_SEND;
- priv->tx_wr.sg_list = &priv->tx_sge;
- priv->tx_wr.num_sge = 1;
+ priv->tx_wr.sg_list = priv->tx_sge;
priv->tx_wr.send_flags = IB_SEND_SIGNALED;
return 0;
/*
- * $Id: analog.c,v 1.68 2002/01/22 20:18:32 vojtech Exp $
- *
* Copyright (c) 1996-2001 Vojtech Pavlik
*/
#define GET_TIME(x) do { x = get_cycles(); } while (0)
#define DELTA(x,y) ((y)-(x))
#define TIME_NAME "PCC"
+#elif defined(CONFIG_MN10300)
+#define GET_TIME(x) do { x = get_cycles(); } while (0)
+#define DELTA(x, y) ((x) - (y))
+#define TIME_NAME "TSC"
#else
#define FAKE_TIME
static unsigned long analog_faketime = 0;
gid_t gid = 0;
umode_t mode = 0600;
char *this_char;
+ char *new_opt = kstrdup(data, GFP_KERNEL);
this_char = NULL;
while ((this_char = strsep(&data, ",")) != NULL) {
return -EINVAL;
}
}
+
+ kfree(s->s_options);
+ s->s_options = new_opt;
+
config.setuid = setuid;
config.setgid = setgid;
config.uid = uid;
config.gid = gid;
config.mode = mode;
+
return 0;
}
{
.statfs = simple_statfs,
.remount_fs = capifs_remount,
+ .show_options = generic_show_options,
};
-void __devinit
-Amd7930_init(struct IsdnCardState *cs)
+void Amd7930_init(struct IsdnCardState *cs)
{
WORD *ptr;
BYTE cmd, cnt;
comment "LED drivers"
+config LEDS_ATMEL_PWM
+ tristate "LED Support using Atmel PWM outputs"
+ depends on LEDS_CLASS && ATMEL_PWM
+ help
+ This option enables support for LEDs driven using outputs
+ of the dedicated PWM controller found on newer Atmel SOCs.
+
config LEDS_CORGI
tristate "LED Support for the Sharp SL-C7x0 series"
depends on LEDS_CLASS && PXA_SHARP_C7xx
obj-$(CONFIG_LEDS_TRIGGERS) += led-triggers.o
# LED Platform Drivers
+obj-$(CONFIG_LEDS_ATMEL_PWM) += leds-atmel-pwm.o
obj-$(CONFIG_LEDS_CORGI) += leds-corgi.o
obj-$(CONFIG_LEDS_LOCOMO) += leds-locomo.o
obj-$(CONFIG_LEDS_SPITZ) += leds-spitz.o
--- /dev/null
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/io.h>
+#include <linux/atmel_pwm.h>
+
+
+struct pwmled {
+ struct led_classdev cdev;
+ struct pwm_channel pwmc;
+ struct gpio_led *desc;
+ u32 mult;
+ u8 active_low;
+};
+
+
+/*
+ * For simplicity, we use "brightness" as if it were a linear function
+ * of PWM duty cycle. However, a logarithmic function of duty cycle is
+ * probably a better match for perceived brightness: two is half as bright
+ * as four, four is half as bright as eight, etc
+ */
+static void pwmled_brightness(struct led_classdev *cdev, enum led_brightness b)
+{
+ struct pwmled *led;
+
+ /* update the duty cycle for the *next* period */
+ led = container_of(cdev, struct pwmled, cdev);
+ pwm_channel_writel(&led->pwmc, PWM_CUPD, led->mult * (unsigned) b);
+}
+
+/*
+ * NOTE: we reuse the platform_data structure of GPIO leds,
+ * but repurpose its "gpio" number as a PWM channel number.
+ */
+static int __init pwmled_probe(struct platform_device *pdev)
+{
+ const struct gpio_led_platform_data *pdata;
+ struct pwmled *leds;
+ unsigned i;
+ int status;
+
+ pdata = pdev->dev.platform_data;
+ if (!pdata || pdata->num_leds < 1)
+ return -ENODEV;
+
+ leds = kcalloc(pdata->num_leds, sizeof(*leds), GFP_KERNEL);
+ if (!leds)
+ return -ENOMEM;
+
+ for (i = 0; i < pdata->num_leds; i++) {
+ struct pwmled *led = leds + i;
+ const struct gpio_led *dat = pdata->leds + i;
+ u32 tmp;
+
+ led->cdev.name = dat->name;
+ led->cdev.brightness = LED_OFF;
+ led->cdev.brightness_set = pwmled_brightness;
+ led->cdev.default_trigger = dat->default_trigger;
+
+ led->active_low = dat->active_low;
+
+ status = pwm_channel_alloc(dat->gpio, &led->pwmc);
+ if (status < 0)
+ goto err;
+
+ /*
+ * Prescale clock by 2^x, so PWM counts in low MHz.
+ * Start each cycle with the LED active, so increasing
+ * the duty cycle gives us more time on (== brighter).
+ */
+ tmp = 5;
+ if (!led->active_low)
+ tmp |= PWM_CPR_CPOL;
+ pwm_channel_writel(&led->pwmc, PWM_CMR, tmp);
+
+ /*
+ * Pick a period so PWM cycles at 100+ Hz; and a multiplier
+ * for scaling duty cycle: brightness * mult.
+ */
+ tmp = (led->pwmc.mck / (1 << 5)) / 100;
+ tmp /= 255;
+ led->mult = tmp;
+ pwm_channel_writel(&led->pwmc, PWM_CDTY,
+ led->cdev.brightness * 255);
+ pwm_channel_writel(&led->pwmc, PWM_CPRD,
+ LED_FULL * tmp);
+
+ pwm_channel_enable(&led->pwmc);
+
+ /* Hand it over to the LED framework */
+ status = led_classdev_register(&pdev->dev, &led->cdev);
+ if (status < 0) {
+ pwm_channel_free(&led->pwmc);
+ goto err;
+ }
+ }
+
+ platform_set_drvdata(pdev, leds);
+ return 0;
+
+err:
+ if (i > 0) {
+ for (i = i - 1; i >= 0; i--) {
+ led_classdev_unregister(&leds[i].cdev);
+ pwm_channel_free(&leds[i].pwmc);
+ }
+ }
+ kfree(leds);
+
+ return status;
+}
+
+static int __exit pwmled_remove(struct platform_device *pdev)
+{
+ const struct gpio_led_platform_data *pdata;
+ struct pwmled *leds;
+ unsigned i;
+
+ pdata = pdev->dev.platform_data;
+ leds = platform_get_drvdata(pdev);
+
+ for (i = 0; i < pdata->num_leds; i++) {
+ struct pwmled *led = leds + i;
+
+ led_classdev_unregister(&led->cdev);
+ pwm_channel_free(&led->pwmc);
+ }
+
+ kfree(leds);
+ platform_set_drvdata(pdev, NULL);
+ return 0;
+}
+
+static struct platform_driver pwmled_driver = {
+ .driver = {
+ .name = "leds-atmel-pwm",
+ .owner = THIS_MODULE,
+ },
+ /* REVISIT add suspend() and resume() methods */
+ .remove = __exit_p(pwmled_remove),
+};
+
+static int __init modinit(void)
+{
+ return platform_driver_probe(&pwmled_driver, pwmled_probe);
+}
+module_init(modinit);
+
+static void __exit modexit(void)
+{
+ platform_driver_unregister(&pwmled_driver);
+}
+module_exit(modexit);
+
+MODULE_DESCRIPTION("Driver for LEDs with PWM-controlled brightness");
+MODULE_LICENSE("GPL");
/* Since the virtio infrastructure hands us a pointer to the virtio_device all
* the time, it helps to have a curt macro to get a pointer to the struct
* lguest_device it's enclosed in. */
-#define to_lgdev(vdev) container_of(vdev, struct lguest_device, vdev)
+#define to_lgdev(vd) container_of(vd, struct lguest_device, vdev)
/*D:130
* Device configurations
u32 cmd_buf_abs; /* command buffer absolute */
struct list_head cmd_list;
struct smu_cmd *cmd_cur; /* pending command */
+ int broken_nap;
struct list_head cmd_i2c_list;
struct smu_i2c_cmd *cmd_i2c_cur; /* pending i2c command */
struct timer_list i2c_timer;
fend = faddr + smu->cmd_buf->length + 2;
flush_inval_dcache_range(faddr, fend);
+
+ /* We also disable NAP mode for the duration of the command
+ * on U3 based machines.
+ * This is slightly racy as it can be written back to 1 by a sysctl
+ * but that never happens in practice. There seem to be an issue with
+ * U3 based machines such as the iMac G5 where napping for the
+ * whole duration of the command prevents the SMU from fetching it
+ * from memory. This might be related to the strange i2c based
+ * mechanism the SMU uses to access memory.
+ */
+ if (smu->broken_nap)
+ powersave_nap = 0;
+
/* This isn't exactly a DMA mapping here, I suspect
* the SMU is actually communicating with us via i2c to the
* northbridge or the CPU to access RAM.
misc = cmd->misc;
mb();
cmd->status = rc;
+
+ /* Re-enable NAP mode */
+ if (smu->broken_nap)
+ powersave_nap = 1;
bail:
/* Start next command if any */
smu_start_cmd();
if (np == NULL)
return -ENODEV;
- printk(KERN_INFO "SMU driver %s %s\n", VERSION, AUTHOR);
+ printk(KERN_INFO "SMU: Driver %s %s\n", VERSION, AUTHOR);
if (smu_cmdbuf_abs == 0) {
printk(KERN_ERR "SMU: Command buffer not allocated !\n");
goto fail;
}
+ /* U3 has an issue with NAP mode when issuing SMU commands */
+ smu->broken_nap = pmac_get_uninorth_variant() < 4;
+ if (smu->broken_nap)
+ printk(KERN_INFO "SMU: using NAP mode workaround\n");
+
sys_ctrler = SYS_CTRLER_SMU;
return 0;
if MISC_DEVICES
+config ATMEL_PWM
+ tristate "Atmel AT32/AT91 PWM support"
+ depends on AVR32 || ARCH_AT91
+ help
+ This option enables device driver support for the PWM channels
+ on certain Atmel prcoessors. Pulse Width Modulation is used for
+ purposes including software controlled power-efficent backlights
+ on LCD displays, motor control, and waveform generation.
+
config IBM_ASM
tristate "Device driver for IBM RSA service processor"
depends on X86 && PCI && INPUT && EXPERIMENTAL
depends on X86
depends on EXPERIMENTAL
depends on ACPI
- depends on ACPI_WMI
depends on LEDS_CLASS
depends on BACKLIGHT_CLASS_DEVICE
+ select ACPI_WMI
---help---
This is a driver for newer Acer (and Wistron) laptops. It adds
wireless radio and bluetooth control, and on some laptops,
tristate "HP Compaq TC1100 Tablet WMI Extras"
depends on X86 && !X86_64
depends on ACPI
- depends on ACPI_WMI
+ select ACPI_WMI
---help---
This is a driver for the WMI extensions (wireless and bluetooth power
control) of the HP Compaq TC1100 tablet.
config INTEL_MENLOW
tristate "Thermal Management driver for Intel menlow platform"
depends on ACPI_THERMAL
+ depends on X86
---help---
ACPI thermal management enhancement driver on
Intel Menlow platform.
obj-$(CONFIG_MSI_LAPTOP) += msi-laptop.o
obj-$(CONFIG_ACER_WMI) += acer-wmi.o
obj-$(CONFIG_ASUS_LAPTOP) += asus-laptop.o
+obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
obj-$(CONFIG_TC1100_WMI) += tc1100-wmi.o
obj-$(CONFIG_LKDTM) += lkdtm.o
--- /dev/null
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/atmel_pwm.h>
+
+
+/*
+ * This is a simple driver for the PWM controller found in various newer
+ * Atmel SOCs, including the AVR32 series and the AT91sam9263.
+ *
+ * Chips with current Linux ports have only 4 PWM channels, out of max 32.
+ * AT32UC3A and AT32UC3B chips have 7 channels (but currently no Linux).
+ * Docs are inconsistent about the width of the channel counter registers;
+ * it's at least 16 bits, but several places say 20 bits.
+ */
+#define PWM_NCHAN 4 /* max 32 */
+
+struct pwm {
+ spinlock_t lock;
+ struct platform_device *pdev;
+ u32 mask;
+ int irq;
+ void __iomem *base;
+ struct clk *clk;
+ struct pwm_channel *channel[PWM_NCHAN];
+ void (*handler[PWM_NCHAN])(struct pwm_channel *);
+};
+
+
+/* global PWM controller registers */
+#define PWM_MR 0x00
+#define PWM_ENA 0x04
+#define PWM_DIS 0x08
+#define PWM_SR 0x0c
+#define PWM_IER 0x10
+#define PWM_IDR 0x14
+#define PWM_IMR 0x18
+#define PWM_ISR 0x1c
+
+static inline void pwm_writel(const struct pwm *p, unsigned offset, u32 val)
+{
+ __raw_writel(val, p->base + offset);
+}
+
+static inline u32 pwm_readl(const struct pwm *p, unsigned offset)
+{
+ return __raw_readl(p->base + offset);
+}
+
+static inline void __iomem *pwmc_regs(const struct pwm *p, int index)
+{
+ return p->base + 0x200 + index * 0x20;
+}
+
+static struct pwm *pwm;
+
+static void pwm_dumpregs(struct pwm_channel *ch, char *tag)
+{
+ struct device *dev = &pwm->pdev->dev;
+
+ dev_dbg(dev, "%s: mr %08x, sr %08x, imr %08x\n",
+ tag,
+ pwm_readl(pwm, PWM_MR),
+ pwm_readl(pwm, PWM_SR),
+ pwm_readl(pwm, PWM_IMR));
+ dev_dbg(dev,
+ "pwm ch%d - mr %08x, dty %u, prd %u, cnt %u\n",
+ ch->index,
+ pwm_channel_readl(ch, PWM_CMR),
+ pwm_channel_readl(ch, PWM_CDTY),
+ pwm_channel_readl(ch, PWM_CPRD),
+ pwm_channel_readl(ch, PWM_CCNT));
+}
+
+
+/**
+ * pwm_channel_alloc - allocate an unused PWM channel
+ * @index: identifies the channel
+ * @ch: structure to be initialized
+ *
+ * Drivers allocate PWM channels according to the board's wiring, and
+ * matching board-specific setup code. Returns zero or negative errno.
+ */
+int pwm_channel_alloc(int index, struct pwm_channel *ch)
+{
+ unsigned long flags;
+ int status = 0;
+
+ /* insist on PWM init, with this signal pinned out */
+ if (!pwm || !(pwm->mask & 1 << index))
+ return -ENODEV;
+
+ if (index < 0 || index >= PWM_NCHAN || !ch)
+ return -EINVAL;
+ memset(ch, 0, sizeof *ch);
+
+ spin_lock_irqsave(&pwm->lock, flags);
+ if (pwm->channel[index])
+ status = -EBUSY;
+ else {
+ clk_enable(pwm->clk);
+
+ ch->regs = pwmc_regs(pwm, index);
+ ch->index = index;
+
+ /* REVISIT: ap7000 seems to go 2x as fast as we expect!! */
+ ch->mck = clk_get_rate(pwm->clk);
+
+ pwm->channel[index] = ch;
+ pwm->handler[index] = NULL;
+
+ /* channel and irq are always disabled when we return */
+ pwm_writel(pwm, PWM_DIS, 1 << index);
+ pwm_writel(pwm, PWM_IDR, 1 << index);
+ }
+ spin_unlock_irqrestore(&pwm->lock, flags);
+ return status;
+}
+EXPORT_SYMBOL(pwm_channel_alloc);
+
+static int pwmcheck(struct pwm_channel *ch)
+{
+ int index;
+
+ if (!pwm)
+ return -ENODEV;
+ if (!ch)
+ return -EINVAL;
+ index = ch->index;
+ if (index < 0 || index >= PWM_NCHAN || pwm->channel[index] != ch)
+ return -EINVAL;
+
+ return index;
+}
+
+/**
+ * pwm_channel_free - release a previously allocated channel
+ * @ch: the channel being released
+ *
+ * The channel is completely shut down (counter and IRQ disabled),
+ * and made available for re-use. Returns zero, or negative errno.
+ */
+int pwm_channel_free(struct pwm_channel *ch)
+{
+ unsigned long flags;
+ int t;
+
+ spin_lock_irqsave(&pwm->lock, flags);
+ t = pwmcheck(ch);
+ if (t >= 0) {
+ pwm->channel[t] = NULL;
+ pwm->handler[t] = NULL;
+
+ /* channel and irq are always disabled when we return */
+ pwm_writel(pwm, PWM_DIS, 1 << t);
+ pwm_writel(pwm, PWM_IDR, 1 << t);
+
+ clk_disable(pwm->clk);
+ t = 0;
+ }
+ spin_unlock_irqrestore(&pwm->lock, flags);
+ return t;
+}
+EXPORT_SYMBOL(pwm_channel_free);
+
+int __pwm_channel_onoff(struct pwm_channel *ch, int enabled)
+{
+ unsigned long flags;
+ int t;
+
+ /* OMITTED FUNCTIONALITY: starting several channels in synch */
+
+ spin_lock_irqsave(&pwm->lock, flags);
+ t = pwmcheck(ch);
+ if (t >= 0) {
+ pwm_writel(pwm, enabled ? PWM_ENA : PWM_DIS, 1 << t);
+ t = 0;
+ pwm_dumpregs(ch, enabled ? "enable" : "disable");
+ }
+ spin_unlock_irqrestore(&pwm->lock, flags);
+
+ return t;
+}
+EXPORT_SYMBOL(__pwm_channel_onoff);
+
+/**
+ * pwm_clk_alloc - allocate and configure CLKA or CLKB
+ * @prescale: from 0..10, the power of two used to divide MCK
+ * @div: from 1..255, the linear divisor to use
+ *
+ * Returns PWM_CPR_CLKA, PWM_CPR_CLKB, or negative errno. The allocated
+ * clock will run with a period of (2^prescale * div) / MCK, or twice as
+ * long if center aligned PWM output is used. The clock must later be
+ * deconfigured using pwm_clk_free().
+ */
+int pwm_clk_alloc(unsigned prescale, unsigned div)
+{
+ unsigned long flags;
+ u32 mr;
+ u32 val = (prescale << 8) | div;
+ int ret = -EBUSY;
+
+ if (prescale >= 10 || div == 0 || div > 255)
+ return -EINVAL;
+
+ spin_lock_irqsave(&pwm->lock, flags);
+ mr = pwm_readl(pwm, PWM_MR);
+ if ((mr & 0xffff) == 0) {
+ mr |= val;
+ ret = PWM_CPR_CLKA;
+ }
+ if ((mr & (0xffff << 16)) == 0) {
+ mr |= val << 16;
+ ret = PWM_CPR_CLKB;
+ }
+ if (ret > 0)
+ pwm_writel(pwm, PWM_MR, mr);
+ spin_unlock_irqrestore(&pwm->lock, flags);
+ return ret;
+}
+EXPORT_SYMBOL(pwm_clk_alloc);
+
+/**
+ * pwm_clk_free - deconfigure and release CLKA or CLKB
+ *
+ * Reverses the effect of pwm_clk_alloc().
+ */
+void pwm_clk_free(unsigned clk)
+{
+ unsigned long flags;
+ u32 mr;
+
+ spin_lock_irqsave(&pwm->lock, flags);
+ mr = pwm_readl(pwm, PWM_MR);
+ if (clk == PWM_CPR_CLKA)
+ pwm_writel(pwm, PWM_MR, mr & ~(0xffff << 0));
+ if (clk == PWM_CPR_CLKB)
+ pwm_writel(pwm, PWM_MR, mr & ~(0xffff << 16));
+ spin_unlock_irqrestore(&pwm->lock, flags);
+}
+EXPORT_SYMBOL(pwm_clk_free);
+
+/**
+ * pwm_channel_handler - manage channel's IRQ handler
+ * @ch: the channel
+ * @handler: the handler to use, possibly NULL
+ *
+ * If the handler is non-null, the handler will be called after every
+ * period of this PWM channel. If the handler is null, this channel
+ * won't generate an IRQ.
+ */
+int pwm_channel_handler(struct pwm_channel *ch,
+ void (*handler)(struct pwm_channel *ch))
+{
+ unsigned long flags;
+ int t;
+
+ spin_lock_irqsave(&pwm->lock, flags);
+ t = pwmcheck(ch);
+ if (t >= 0) {
+ pwm->handler[t] = handler;
+ pwm_writel(pwm, handler ? PWM_IER : PWM_IDR, 1 << t);
+ t = 0;
+ }
+ spin_unlock_irqrestore(&pwm->lock, flags);
+
+ return t;
+}
+EXPORT_SYMBOL(pwm_channel_handler);
+
+static irqreturn_t pwm_irq(int id, void *_pwm)
+{
+ struct pwm *p = _pwm;
+ irqreturn_t handled = IRQ_NONE;
+ u32 irqstat;
+ int index;
+
+ spin_lock(&p->lock);
+
+ /* ack irqs, then handle them */
+ irqstat = pwm_readl(pwm, PWM_ISR);
+
+ while (irqstat) {
+ struct pwm_channel *ch;
+ void (*handler)(struct pwm_channel *ch);
+
+ index = ffs(irqstat) - 1;
+ irqstat &= ~(1 << index);
+ ch = pwm->channel[index];
+ handler = pwm->handler[index];
+ if (handler && ch) {
+ spin_unlock(&p->lock);
+ handler(ch);
+ spin_lock(&p->lock);
+ handled = IRQ_HANDLED;
+ }
+ }
+
+ spin_unlock(&p->lock);
+ return handled;
+}
+
+static int __init pwm_probe(struct platform_device *pdev)
+{
+ struct resource *r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ int irq = platform_get_irq(pdev, 0);
+ u32 *mp = pdev->dev.platform_data;
+ struct pwm *p;
+ int status = -EIO;
+
+ if (pwm)
+ return -EBUSY;
+ if (!r || irq < 0 || !mp || !*mp)
+ return -ENODEV;
+ if (*mp & ~((1<<PWM_NCHAN)-1)) {
+ dev_warn(&pdev->dev, "mask 0x%x ... more than %d channels\n",
+ *mp, PWM_NCHAN);
+ return -EINVAL;
+ }
+
+ p = kzalloc(sizeof(*p), GFP_KERNEL);
+ if (!p)
+ return -ENOMEM;
+
+ spin_lock_init(&p->lock);
+ p->pdev = pdev;
+ p->mask = *mp;
+ p->irq = irq;
+ p->base = ioremap(r->start, r->end - r->start + 1);
+ if (!p->base)
+ goto fail;
+ p->clk = clk_get(&pdev->dev, "mck");
+ if (IS_ERR(p->clk)) {
+ status = PTR_ERR(p->clk);
+ p->clk = NULL;
+ goto fail;
+ }
+
+ status = request_irq(irq, pwm_irq, 0, pdev->name, p);
+ if (status < 0)
+ goto fail;
+
+ pwm = p;
+ platform_set_drvdata(pdev, p);
+
+ return 0;
+
+fail:
+ if (p->clk)
+ clk_put(p->clk);
+ if (p->base)
+ iounmap(p->base);
+
+ kfree(p);
+ return status;
+}
+
+static int __exit pwm_remove(struct platform_device *pdev)
+{
+ struct pwm *p = platform_get_drvdata(pdev);
+
+ if (p != pwm)
+ return -EINVAL;
+
+ clk_enable(pwm->clk);
+ pwm_writel(pwm, PWM_DIS, (1 << PWM_NCHAN) - 1);
+ pwm_writel(pwm, PWM_IDR, (1 << PWM_NCHAN) - 1);
+ clk_disable(pwm->clk);
+
+ pwm = NULL;
+
+ free_irq(p->irq, p);
+ clk_put(p->clk);
+ iounmap(p->base);
+ kfree(p);
+
+ return 0;
+}
+
+static struct platform_driver atmel_pwm_driver = {
+ .driver = {
+ .name = "atmel_pwm",
+ .owner = THIS_MODULE,
+ },
+ .remove = __exit_p(pwm_remove),
+
+ /* NOTE: PWM can keep running in AVR32 "idle" and "frozen" states;
+ * and all AT91sam9263 states, albeit at reduced clock rate if
+ * MCK becomes the slow clock (i.e. what Linux labels STR).
+ */
+};
+
+static int __init pwm_init(void)
+{
+ return platform_driver_probe(&atmel_pwm_driver, pwm_probe);
+}
+module_init(pwm_init);
+
+static void __exit pwm_exit(void)
+{
+ platform_driver_unregister(&atmel_pwm_driver);
+}
+module_exit(pwm_exit);
+
+MODULE_DESCRIPTION("Driver for AT32/AT91 PWM module");
+MODULE_LICENSE("GPL");
tristate "SMC 91C9x/91C1xxx support"
select CRC32
select MII
- depends on ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || SOC_AU1X00 || BLACKFIN
+ depends on ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || \
+ SOC_AU1X00 || BLACKFIN || MN10300
help
This is a driver for SMC's 91x series of Ethernet chipsets,
including the SMC91C94 and the SMC91C111. Say Y if you want it
-/* $Id: ethernet.c,v 1.31 2004/10/18 14:49:03 starvik Exp $
- *
+/*
* e100net.c: A network driver for the ETRAX 100LX network controller.
*
* Copyright (c) 1998-2002 Axis Communications AB.
*
* The outline of this driver comes from skeleton.c.
*
- * $Log: ethernet.c,v $
- * Revision 1.31 2004/10/18 14:49:03 starvik
- * Use RX interrupt as random source
- *
- * Revision 1.30 2004/09/29 10:44:04 starvik
- * Enabed MAC-address output again
- *
- * Revision 1.29 2004/08/24 07:14:05 starvik
- * Make use of generic MDIO interface and constants.
- *
- * Revision 1.28 2004/08/20 09:37:11 starvik
- * Added support for Intel LXT972A. Creds to Randy Scarborough.
- *
- * Revision 1.27 2004/08/16 12:37:22 starvik
- * Merge of Linux 2.6.8
- *
- * Revision 1.25 2004/06/21 10:29:57 starvik
- * Merge of Linux 2.6.7
- *
- * Revision 1.23 2004/06/09 05:29:22 starvik
- * Avoid any race where R_DMA_CH1_FIRST is NULL (may trigger cache bug).
- *
- * Revision 1.22 2004/05/14 07:58:03 starvik
- * Merge of changes from 2.4
- *
- * Revision 1.20 2004/03/11 11:38:40 starvik
- * Merge of Linux 2.6.4
- *
- * Revision 1.18 2003/12/03 13:45:46 starvik
- * Use hardware pad for short packets to prevent information leakage.
- *
- * Revision 1.17 2003/07/04 08:27:37 starvik
- * Merge of Linux 2.5.74
- *
- * Revision 1.16 2003/04/24 08:28:22 starvik
- * New LED behaviour: LED off when no link
- *
- * Revision 1.15 2003/04/09 05:20:47 starvik
- * Merge of Linux 2.5.67
- *
- * Revision 1.13 2003/03/06 16:11:01 henriken
- * Off by one error in group address register setting.
- *
- * Revision 1.12 2003/02/27 17:24:19 starvik
- * Corrected Rev to Revision
- *
- * Revision 1.11 2003/01/24 09:53:21 starvik
- * Oops. Initialize GA to 0, not to 1
- *
- * Revision 1.10 2003/01/24 09:50:55 starvik
- * Initialize GA_0 and GA_1 to 0 to avoid matching of unwanted packets
- *
- * Revision 1.9 2002/12/13 07:40:58 starvik
- * Added basic ethtool interface
- * Handled out of memory when allocating new buffers
- *
- * Revision 1.8 2002/12/11 13:13:57 starvik
- * Added arch/ to v10 specific includes
- * Added fix from Linux 2.4 in serial.c (flush_to_flip_buffer)
- *
- * Revision 1.7 2002/11/26 09:41:42 starvik
- * Added e100_set_config (standard interface to set media type)
- * Added protection against preemptive scheduling
- * Added standard MII ioctls
- *
- * Revision 1.6 2002/11/21 07:18:18 starvik
- * Timers must be initialized in 2.5.48
- *
- * Revision 1.5 2002/11/20 11:56:11 starvik
- * Merge of Linux 2.5.48
- *
- * Revision 1.4 2002/11/18 07:26:46 starvik
- * Linux 2.5 port of latest Linux 2.4 ethernet driver
- *
- * Revision 1.33 2002/10/02 20:16:17 hp
- * SETF, SETS: Use underscored IO_x_ macros rather than incorrect token concatenation
- *
- * Revision 1.32 2002/09/16 06:05:58 starvik
- * Align memory returned by dev_alloc_skb
- * Moved handling of sent packets to interrupt to avoid reference counting problem
- *
- * Revision 1.31 2002/09/10 13:28:23 larsv
- * Return -EINVAL for unknown ioctls to avoid confusing tools that tests
- * for supported functionality by issuing special ioctls, i.e. wireless
- * extensions.
- *
- * Revision 1.30 2002/05/07 18:50:08 johana
- * Correct spelling in comments.
- *
- * Revision 1.29 2002/05/06 05:38:49 starvik
- * Performance improvements:
- * Large packets are not copied (breakpoint set to 256 bytes)
- * The cache bug workaround is delayed until half of the receive list
- * has been used
- * Added transmit list
- * Transmit interrupts are only enabled when transmit queue is full
- *
- * Revision 1.28.2.1 2002/04/30 08:15:51 starvik
- * Performance improvements:
- * Large packets are not copied (breakpoint set to 256 bytes)
- * The cache bug workaround is delayed until half of the receive list
- * has been used.
- * Added transmit list
- * Transmit interrupts are only enabled when transmit queue is full
- *
- * Revision 1.28 2002/04/22 11:47:21 johana
- * Fix according to 2.4.19-pre7. time_after/time_before and
- * missing end of comment.
- * The patch has a typo for ethernet.c in e100_clear_network_leds(),
- * that is fixed here.
- *
- * Revision 1.27 2002/04/12 11:55:11 bjornw
- * Added TODO
- *
- * Revision 1.26 2002/03/15 17:11:02 bjornw
- * Use prepare_rx_descriptor after the CPU has touched the receiving descs
- *
- * Revision 1.25 2002/03/08 13:07:53 bjornw
- * Unnecessary spinlock removed
- *
- * Revision 1.24 2002/02/20 12:57:43 fredriks
- * Replaced MIN() with min().
- *
- * Revision 1.23 2002/02/20 10:58:14 fredriks
- * Strip the Ethernet checksum (4 bytes) before forwarding a frame to upper layers.
- *
- * Revision 1.22 2002/01/30 07:48:22 matsfg
- * Initiate R_NETWORK_TR_CTRL
- *
- * Revision 1.21 2001/11/23 11:54:49 starvik
- * Added IFF_PROMISC and IFF_ALLMULTI handling in set_multicast_list
- * Removed compiler warnings
- *
- * Revision 1.20 2001/11/12 19:26:00 pkj
- * * Corrected e100_negotiate() to not assign half to current_duplex when
- * it was supposed to compare them...
- * * Cleaned up failure handling in e100_open().
- * * Fixed compiler warnings.
- *
- * Revision 1.19 2001/11/09 07:43:09 starvik
- * Added full duplex support
- * Added ioctl to set speed and duplex
- * Clear LED timer only runs when LED is lit
- *
- * Revision 1.18 2001/10/03 14:40:43 jonashg
- * Update rx_bytes counter.
- *
- * Revision 1.17 2001/06/11 12:43:46 olof
- * Modified defines for network LED behavior
- *
- * Revision 1.16 2001/05/30 06:12:46 markusl
- * TxDesc.next should not be set to NULL
- *
- * Revision 1.15 2001/05/29 10:27:04 markusl
- * Updated after review remarks:
- * +Use IO_EXTRACT
- * +Handle underrun
- *
- * Revision 1.14 2001/05/29 09:20:14 jonashg
- * Use driver name on printk output so one can tell which driver that complains.
- *
- * Revision 1.13 2001/05/09 12:35:59 johana
- * Use DMA_NBR and IRQ_NBR defines from dma.h and irq.h
- *
- * Revision 1.12 2001/04/05 11:43:11 tobiasa
- * Check dev before panic.
- *
- * Revision 1.11 2001/04/04 11:21:05 markusl
- * Updated according to review remarks
- *
- * Revision 1.10 2001/03/26 16:03:06 bjornw
- * Needs linux/config.h
- *
- * Revision 1.9 2001/03/19 14:47:48 pkj
- * * Make sure there is always a pause after the network LEDs are
- * changed so they will not look constantly lit during heavy traffic.
- * * Always use HZ when setting times relative to jiffies.
- * * Use LED_NETWORK_SET() when setting the network LEDs.
- *
- * Revision 1.8 2001/02/27 13:52:48 bjornw
- * malloc.h -> slab.h
- *
- * Revision 1.7 2001/02/23 13:46:38 bjornw
- * Spellling check
- *
- * Revision 1.6 2001/01/26 15:21:04 starvik
- * Don't disable interrupts while reading MDIO registers (MDIO is slow)
- * Corrected promiscuous mode
- * Improved deallocation of IRQs ("ifconfig eth0 down" now works)
- *
- * Revision 1.5 2000/11/29 17:22:22 bjornw
- * Get rid of the udword types legacy stuff
- *
- * Revision 1.4 2000/11/22 16:36:09 bjornw
- * Please marketing by using the correct case when spelling Etrax.
- *
- * Revision 1.3 2000/11/21 16:43:04 bjornw
- * Minor short->int change
- *
- * Revision 1.2 2000/11/08 14:27:57 bjornw
- * 2.4 port
- *
- * Revision 1.1 2000/11/06 13:56:00 bjornw
- * Verbatim copy of the 1.24 version of e100net.c from elinux
- *
- * Revision 1.24 2000/10/04 15:55:23 bjornw
- * * Use virt_to_phys etc. for DMA addresses
- * * Removed bogus CHECKSUM_UNNECESSARY
- *
- *
*/
#include <linux/ethtool.h>
#include <asm/arch/svinto.h>/* DMA and register descriptions */
-#include <asm/io.h> /* LED_* I/O functions */
+#include <asm/io.h> /* CRIS_LED_* I/O functions */
#include <asm/irq.h>
#include <asm/dma.h>
#include <asm/system.h>
if (!current_speed) {
/* Make LED red, link is down */
#if defined(CONFIG_ETRAX_NETWORK_RED_ON_NO_CONNECTION)
- LED_NETWORK_SET(LED_RED);
+ CRIS_LED_NETWORK_SET(CRIS_LED_RED);
#else
- LED_NETWORK_SET(LED_OFF);
+ CRIS_LED_NETWORK_SET(CRIS_LED_OFF);
#endif
} else if (light_leds) {
if (current_speed == 10) {
- LED_NETWORK_SET(LED_ORANGE);
+ CRIS_LED_NETWORK_SET(CRIS_LED_ORANGE);
} else {
- LED_NETWORK_SET(LED_GREEN);
+ CRIS_LED_NETWORK_SET(CRIS_LED_GREEN);
}
} else {
- LED_NETWORK_SET(LED_OFF);
+ CRIS_LED_NETWORK_SET(CRIS_LED_OFF);
}
}
buf->nbufs = 1;
buf->npages = 1;
buf->page_shift = get_order(size) + PAGE_SHIFT;
- buf->u.direct.buf = dma_alloc_coherent(&dev->pdev->dev,
+ buf->direct.buf = dma_alloc_coherent(&dev->pdev->dev,
size, &t, GFP_KERNEL);
- if (!buf->u.direct.buf)
+ if (!buf->direct.buf)
return -ENOMEM;
- buf->u.direct.map = t;
+ buf->direct.map = t;
while (t & ((1 << buf->page_shift) - 1)) {
--buf->page_shift;
buf->npages *= 2;
}
- memset(buf->u.direct.buf, 0, size);
+ memset(buf->direct.buf, 0, size);
} else {
int i;
buf->nbufs = (size + PAGE_SIZE - 1) / PAGE_SIZE;
buf->npages = buf->nbufs;
buf->page_shift = PAGE_SHIFT;
- buf->u.page_list = kzalloc(buf->nbufs * sizeof *buf->u.page_list,
+ buf->page_list = kzalloc(buf->nbufs * sizeof *buf->page_list,
GFP_KERNEL);
- if (!buf->u.page_list)
+ if (!buf->page_list)
return -ENOMEM;
for (i = 0; i < buf->nbufs; ++i) {
- buf->u.page_list[i].buf =
+ buf->page_list[i].buf =
dma_alloc_coherent(&dev->pdev->dev, PAGE_SIZE,
&t, GFP_KERNEL);
- if (!buf->u.page_list[i].buf)
+ if (!buf->page_list[i].buf)
goto err_free;
- buf->u.page_list[i].map = t;
+ buf->page_list[i].map = t;
- memset(buf->u.page_list[i].buf, 0, PAGE_SIZE);
+ memset(buf->page_list[i].buf, 0, PAGE_SIZE);
+ }
+
+ if (BITS_PER_LONG == 64) {
+ struct page **pages;
+ pages = kmalloc(sizeof *pages * buf->nbufs, GFP_KERNEL);
+ if (!pages)
+ goto err_free;
+ for (i = 0; i < buf->nbufs; ++i)
+ pages[i] = virt_to_page(buf->page_list[i].buf);
+ buf->direct.buf = vmap(pages, buf->nbufs, VM_MAP, PAGE_KERNEL);
+ kfree(pages);
+ if (!buf->direct.buf)
+ goto err_free;
}
}
int i;
if (buf->nbufs == 1)
- dma_free_coherent(&dev->pdev->dev, size, buf->u.direct.buf,
- buf->u.direct.map);
+ dma_free_coherent(&dev->pdev->dev, size, buf->direct.buf,
+ buf->direct.map);
else {
+ if (BITS_PER_LONG == 64)
+ vunmap(buf->direct.buf);
+
for (i = 0; i < buf->nbufs; ++i)
- if (buf->u.page_list[i].buf)
+ if (buf->page_list[i].buf)
dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
- buf->u.page_list[i].buf,
- buf->u.page_list[i].map);
- kfree(buf->u.page_list);
+ buf->page_list[i].buf,
+ buf->page_list[i].map);
+ kfree(buf->page_list);
}
}
EXPORT_SYMBOL_GPL(mlx4_buf_free);
for (i = 0; i < buf->npages; ++i)
if (buf->nbufs == 1)
- page_list[i] = buf->u.direct.map + (i << buf->page_shift);
+ page_list[i] = buf->direct.map + (i << buf->page_shift);
else
- page_list[i] = buf->u.page_list[i].map;
+ page_list[i] = buf->page_list[i].map;
err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
#define SMC_IRQ_FLAGS (-1) /* from resource */
+#elif defined(CONFIG_MN10300)
+
+/*
+ * MN10300/AM33 configuration
+ */
+
+#include <asm/unit/smc91111.h>
+
#else
+/*
+ * Default configuration
+ */
+
#define SMC_CAN_USE_8BIT 1
#define SMC_CAN_USE_16BIT 1
#define SMC_CAN_USE_32BIT 1
static int x25_asy_open_tty(struct tty_struct *tty)
{
struct x25_asy *sl = (struct x25_asy *) tty->disc_data;
+ struct tty_ldisc *ld;
int err;
/* First make sure we're not already connected. */
if (tty->driver->flush_buffer) {
tty->driver->flush_buffer(tty);
}
- if (tty->ldisc.flush_buffer) {
- tty->ldisc.flush_buffer(tty);
- }
+ tty_ldisc_flush(tty);
/* Restore default settings */
sl->dev->type = ARPHRD_X25;
config PARPORT_PC
tristate "PC-style hardware"
- depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && (!M68K || ISA)
+ depends on (!SPARC64 || PCI) && !SPARC32 && !M32R && !FRV && \
+ (!M68K || ISA) && !MN10300
---help---
You should say Y here if you have a PC-style parallel port. All
IBM PC compatible computers and some Alphas have PC-style
/* Event 59: set nSelectIn (nAStrb) high */
parport_frob_control (port, PARPORT_CONTROL_SELECT,
- PARPORT_CONTROL_SELECT);
+ 0);
/* Event 60: wait for Busy to go low */
if (parport_poll_peripheral (port, PARPORT_STATUS_BUSY,
obj-$(CONFIG_PPC) += setup-bus.o
obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
obj-$(CONFIG_X86_VISWS) += setup-irq.o
+obj-$(CONFIG_MN10300) += setup-bus.o
#
# ACPI Related PCI FW Functions
DMA_TLB_PSI_FLUSH, non_present_entry_flush);
}
+static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
+{
+ u32 pmen;
+ unsigned long flags;
+
+ spin_lock_irqsave(&iommu->register_lock, flags);
+ pmen = readl(iommu->reg + DMAR_PMEN_REG);
+ pmen &= ~DMA_PMEN_EPM;
+ writel(pmen, iommu->reg + DMAR_PMEN_REG);
+
+ /* wait for the protected region status bit to clear */
+ IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
+ readl, !(pmen & DMA_PMEN_PRS), pmen);
+
+ spin_unlock_irqrestore(&iommu->register_lock, flags);
+}
+
static int iommu_enable_translation(struct intel_iommu *iommu)
{
u32 sts;
/* iommu interrupt handling. Most stuff are MSI-like. */
-static char *fault_reason_strings[] =
+static const char *fault_reason_strings[] =
{
"Software",
"Present bit in root entry is clear",
"non-zero reserved fields in RTP",
"non-zero reserved fields in CTP",
"non-zero reserved fields in PTE",
- "Unknown"
};
-#define MAX_FAULT_REASON_IDX ARRAY_SIZE(fault_reason_strings) - 1
+#define MAX_FAULT_REASON_IDX (ARRAY_SIZE(fault_reason_strings) - 1)
-char *dmar_get_fault_reason(u8 fault_reason)
+const char *dmar_get_fault_reason(u8 fault_reason)
{
- if (fault_reason >= MAX_FAULT_REASON_IDX)
- return fault_reason_strings[MAX_FAULT_REASON_IDX - 1];
+ if (fault_reason > MAX_FAULT_REASON_IDX)
+ return "Unknown";
else
return fault_reason_strings[fault_reason];
}
static int iommu_page_fault_do_one(struct intel_iommu *iommu, int type,
u8 fault_reason, u16 source_id, u64 addr)
{
- char *reason;
+ const char *reason;
reason = dmar_get_fault_reason(fault_reason);
iommu_flush_context_global(iommu, 0);
iommu_flush_iotlb_global(iommu, 0);
+ iommu_disable_protect_mem_regions(iommu);
+
ret = iommu_enable_translation(iommu);
if (ret)
goto error;
#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
#define DMA_TLB_MAX_SIZE (0x3f)
+/* PMEN_REG */
+#define DMA_PMEN_EPM (((u32)1)<<31)
+#define DMA_PMEN_PRS (((u32)1)<<0)
+
/* GCMD_REG */
#define DMA_GCMD_TE (((u32)1) << 31)
#define DMA_GCMD_SRTP (((u32)1) << 30)
return au_io_out_map[offset];
}
-#elif defined (CONFIG_SERIAL_8250_RM9K)
+#elif defined(CONFIG_SERIAL_8250_RM9K)
static const u8
regmap_in[8] = {
serial_outp(up, UART_DLM, value >> 8 & 0xff);
}
-#if defined (CONFIG_SERIAL_8250_AU1X00)
+#if defined(CONFIG_SERIAL_8250_AU1X00)
/* Au1x00 haven't got a standard divisor latch */
static int serial_dl_read(struct uart_8250_port *up)
{
else
_serial_dl_write(up, value);
}
-#elif defined (CONFIG_SERIAL_8250_RM9K)
+#elif defined(CONFIG_SERIAL_8250_RM9K)
static int serial_dl_read(struct uart_8250_port *up)
{
return (up->port.iotype == UPIO_RM9000) ?
irqs = probe_irq_on();
serial_outp(up, UART_MCR, 0);
- udelay (10);
- if (up->port.flags & UPF_FOURPORT) {
+ udelay(10);
+ if (up->port.flags & UPF_FOURPORT) {
serial_outp(up, UART_MCR,
UART_MCR_DTR | UART_MCR_RTS);
} else {
(void)serial_inp(up, UART_IIR);
(void)serial_inp(up, UART_MSR);
serial_outp(up, UART_TX, 0xFF);
- udelay (20);
+ udelay(20);
irq = probe_irq_off(irqs);
serial_outp(up, UART_MCR, save_mcr);
uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
- ignore_char:
+ignore_char:
lsr = serial_inp(up, UART_LSR);
} while ((lsr & UART_LSR_DR) && (max_count-- > 0));
spin_unlock(&up->port.lock);
serial_out(up, UART_IER, ier);
/* Standard timer interval plus 0.2s to keep the port running */
- mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout) + HZ/5);
+ mod_timer(&up->timer,
+ jiffies + poll_timeout(up->port.timeout) + HZ / 5);
}
static unsigned int serial8250_tx_empty(struct uart_port *port)
up->timer.function = serial8250_backup_timeout;
up->timer.data = (unsigned long)up;
mod_timer(&up->timer, jiffies +
- poll_timeout(up->port.timeout) + HZ/5);
+ poll_timeout(up->port.timeout) + HZ / 5);
}
}
}
serial8250_set_mctrl(&up->port, up->port.mctrl);
spin_unlock_irqrestore(&up->port.lock, flags);
+ tty_termios_encode_baud_rate(termios, baud, baud);
}
static void
serial_out(port, UART_TX, c);
}
-static void __init early_serial8250_write(struct console *console, const char *s, unsigned int count)
+static void __init early_serial8250_write(struct console *console,
+ const char *s, unsigned int count)
{
struct uart_port *port = &early_device.port;
unsigned int ier;
serial_out(port, UART_LCR, c & ~UART_LCR_DLAB);
}
-static int __init parse_options(struct early_serial8250_device *device, char *options)
+static int __init parse_options(struct early_serial8250_device *device,
+ char *options)
{
struct uart_port *port = &device->port;
int mmio, length;
port->iotype = UPIO_MEM;
port->mapbase = simple_strtoul(options + 5, &options, 0);
#ifdef CONFIG_FIX_EARLYCON_MEM
- set_fixmap_nocache(FIX_EARLYCON_MEM_BASE, port->mapbase & PAGE_MASK);
- port->membase = (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
+ set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
+ port->mapbase & PAGE_MASK);
+ port->membase =
+ (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
port->membase += port->mapbase & ~PAGE_MASK;
#else
port->membase = ioremap(port->mapbase, 64);
} else
return -EINVAL;
- if ((options = strchr(options, ','))) {
+ options = strchr(options, ',');
+ if (options) {
options++;
device->baud = simple_strtoul(options, NULL, 0);
length = min(strcspn(options, " "), sizeof(device->options));
printk(KERN_INFO "Early serial console at %s 0x%llx (options '%s')\n",
mmio ? "MMIO" : "I/O port",
mmio ? (unsigned long long) port->mapbase
- : (unsigned long long) port->iobase,
+ : (unsigned long long) port->iobase,
device->options);
return 0;
}
if (device->port.membase || device->port.iobase)
return 0;
- if ((err = parse_options(device, options)) < 0)
+ err = parse_options(device, options);
+ if (err < 0)
return err;
init_port(device);
}
options = strchr(cmdline, ',') + 1;
- if ((err = early_serial8250_setup(options)) < 0)
+ err = early_serial8250_setup(options);
+ if (err < 0)
return err;
register_console(&early_serial8250_console);
#include "8250.h"
-static int __init
-serial_init_chip(struct parisc_device *dev)
+static int __init serial_init_chip(struct parisc_device *dev)
{
struct uart_port port;
unsigned long address;
* what we have here is a missing parent device, so tell
* the user what they're missing.
*/
- if (parisc_parent(dev)->id.hw_type != HPHW_IOA) {
- printk(KERN_INFO "Serial: device 0x%lx not configured.\n"
+ if (parisc_parent(dev)->id.hw_type != HPHW_IOA)
+ printk(KERN_INFO
+ "Serial: device 0x%lx not configured.\n"
"Enable support for Wax, Lasi, Asp or Dino.\n",
dev->hpa.start);
- }
return -ENODEV;
}
address = dev->hpa.start;
- if (dev->id.sversion != 0x8d) {
+ if (dev->id.sversion != 0x8d)
address += 0x800;
- }
memset(&port, 0, sizeof(port));
port.iotype = UPIO_MEM;
err = serial8250_register_port(&port);
if (err < 0) {
- printk(KERN_WARNING "serial8250_register_port returned error %d\n", err);
+ printk(KERN_WARNING
+ "serial8250_register_port returned error %d\n", err);
iounmap(port.membase);
return err;
}
-
+
return 0;
}
#ifdef CONFIG_HPDCA
static int __devinit hpdca_init_one(struct dio_dev *d,
- const struct dio_device_id *ent);
+ const struct dio_device_id *ent);
static void __devexit hpdca_remove_one(struct dio_dev *d);
static struct dio_device_id hpdca_dio_tbl[] = {
#ifdef CONFIG_SERIAL_8250_CONSOLE
/*
- * Parse the bootinfo to find descriptions for headless console and
+ * Parse the bootinfo to find descriptions for headless console and
* debug serial ports and register them with the 8250 driver.
* This function should be called before serial_console_init() is called
* to make sure the serial console will be available for use. IA-64 kernel
printk(KERN_WARNING "Serial console is APCI but support is disabled (CONFIG_HPAPCI)!\n");
return 0;
#endif
- }
- else {
+ } else {
#ifdef CONFIG_HPDCA
unsigned long pa = dio_scodetophysaddr(scode);
- if (!pa) {
+ if (!pa)
return 0;
- }
printk(KERN_INFO "Serial console is HP DCA at select code %d\n", scode);
/* Enable board-interrupts */
out_8(pa + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
- if (DIO_ID(pa + DIO_VIRADDRBASE) & 0x80) {
+ if (DIO_ID(pa + DIO_VIRADDRBASE) & 0x80)
add_preferred_console("ttyS", port.line, "9600n8");
- }
#else
printk(KERN_WARNING "Serial console is DCA but support is disabled (CONFIG_HPDCA)!\n");
return 0;
#endif
}
- if (early_serial_setup(&port) < 0) {
+ if (early_serial_setup(&port) < 0)
printk(KERN_WARNING "hp300_setup_serial_console(): early_serial_setup() failed.\n");
- }
-
return 0;
}
#endif /* CONFIG_SERIAL_8250_CONSOLE */
#ifdef CONFIG_HPDCA
static int __devinit hpdca_init_one(struct dio_dev *d,
- const struct dio_device_id *ent)
+ const struct dio_device_id *ent)
{
struct uart_port port;
int line;
static int __init hp300_8250_init(void)
{
- static int called = 0;
+ static int called;
#ifdef CONFIG_HPAPCI
int line;
unsigned long base;
* Port 1 is either the console or the DCA.
*/
for (i = 1; i < 4; i++) {
- /* Port 1 is the console on a 425e, on other machines it's mapped to
- * DCA.
+ /* Port 1 is the console on a 425e, on other machines it's
+ * mapped to DCA.
*/
#ifdef CONFIG_SERIAL_8250_CONSOLE
- if (i == 1) {
+ if (i == 1)
continue;
- }
#endif
/* Create new serial device */
/* Memory mapped I/O */
uport.iotype = UPIO_MEM;
- uport.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
+ uport.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ \
+ | UPF_BOOT_AUTOCONF;
/* XXX - no interrupt support yet */
uport.irq = 0;
uport.uartclk = HPAPCI_BAUD_BASE * 16;
line = serial8250_register_port(&uport);
if (line < 0) {
- printk(KERN_NOTICE "8250_hp300: register_serial() APCI %d"
- " irq %d failed\n", i, uport.irq);
+ printk(KERN_NOTICE "8250_hp300: register_serial() APCI"
+ " %d irq %d failed\n", i, uport.irq);
kfree(port);
continue;
}
}
static struct plat_serial8250_port hub6_data[] = {
- HUB6(0,0),
- HUB6(0,1),
- HUB6(0,2),
- HUB6(0,3),
- HUB6(0,4),
- HUB6(0,5),
- HUB6(1,0),
- HUB6(1,1),
- HUB6(1,2),
- HUB6(1,3),
- HUB6(1,4),
- HUB6(1,5),
+ HUB6(0, 0),
+ HUB6(0, 1),
+ HUB6(0, 2),
+ HUB6(0, 3),
+ HUB6(0, 4),
+ HUB6(0, 5),
+ HUB6(1, 0),
+ HUB6(1, 1),
+ HUB6(1, 2),
+ HUB6(1, 3),
+ HUB6(1, 4),
+ HUB6(1, 5),
{ },
};
struct uart_port *port, int idx)
{
unsigned int bar, offset = board->first_offset;
-
+
bar = FL_GET_BASE(board->flags);
if (idx < 4)
bar += idx;
return -ENODEV;
/* is firmware started? */
- pci_read_config_dword(dev, 0x44, (void*) &oldval);
- if (oldval == 0x00001000L) { /* RESET value */
+ pci_read_config_dword(dev, 0x44, (void *)&oldval);
+ if (oldval == 0x00001000L) { /* RESET value */
printk(KERN_DEBUG "Local i960 firmware missing");
return -ENODEV;
}
irq_config = 0x41;
if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
- dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) {
+ dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
irq_config = 0x43;
- }
+
if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
- (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
+ (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
/*
* As the megawolf cards have the int pins active
* high, and have 2 UART chips, both ints must be
* deep FIFOs
*/
irq_config = 0x5b;
- }
-
/*
* enable/disable interrupts
*/
{
u8 __iomem *p;
- p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
+ p = ioremap(pci_resource_start(dev, 0), pci_resource_len(dev, 0));
if (p == NULL)
return -ENOMEM;
/* Set bit-4 Control Register (UART RESET) in to reset the uarts */
- writeb(0x10,p + OCT_REG_CR_OFF);
+ writeb(0x10, p + OCT_REG_CR_OFF);
udelay(50);
- writeb(0x0,p + OCT_REG_CR_OFF);
+ writeb(0x0, p + OCT_REG_CR_OFF);
/* Set bit-2 (INTENABLE) of Control Register */
writeb(0x4, p + OCT_REG_CR_OFF);
{
u8 __iomem *p;
- p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
- if (p != NULL) {
+ p = ioremap(pci_resource_start(dev, 0), pci_resource_len(dev, 0));
+ /* FIXME: What if resource_len < OCT_REG_CR_OFF */
+ if (p != NULL)
writeb(0, p + OCT_REG_CR_OFF);
- }
iounmap(p);
}
* with other OSes (like M$ DOS).
*
* SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
- *
+ *
* There is two family of SIIG serial cards with different PCI
* interface chip and different configuration methods:
* - 10x cards have control registers in IO and/or memory space;
static const unsigned short timedia_dual_port[] = {
0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
- 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
- 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
+ 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
+ 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
0xD079, 0
};
static const unsigned short timedia_quad_port[] = {
- 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
- 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
+ 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
+ 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
0xB157, 0
};
static const unsigned short timedia_eight_port[] = {
- 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
+ 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
};
ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
/* write INTCBAR - ioport */
- pci_write_config_dword(dev, ITE_887x_INTCBAR, inta_addr[i]);
+ pci_write_config_dword(dev, ITE_887x_INTCBAR,
+ inta_addr[i]);
ret = inb(inta_addr[i]);
if (ret != 0xff) {
/* ioport connected */
if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
return 1;
-
+
return setup_port(priv, port, bar, offset, board->reg_shift);
}
.init = pci_plx9050_init,
.setup = pci_default_setup,
.exit = __devexit_p(pci_plx9050_exit),
- },
+ },
{
.vendor = PCI_VENDOR_ID_PANACOM,
.device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
quirk_id_matches(quirk->device, dev->device) &&
quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
quirk_id_matches(quirk->subdevice, dev->subsystem_device))
- break;
+ break;
return quirk;
}
};
static const struct pci_device_id softmodem_blacklist[] = {
- { PCI_VDEVICE ( AL, 0x5457 ), }, /* ALi Corporation M5457 AC'97 Modem */
+ { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
};
/*
{
const struct pci_device_id *blacklist;
int num_iomem, num_port, first_port = -1, i;
-
+
/*
* If it is not a communications device or the programming
* interface is greater than 6, give up.
*
* (Should we try to make guesses for multiport serial devices
- * later?)
+ * later?)
*/
if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
break;
#ifdef SERIAL_DEBUG_PCI
- printk("Setup PCI port: port %x, irq %d, type %d\n",
+ printk(KERN_DEBUG "Setup PCI port: port %x, irq %d, type %d\n",
serial_port.iobase, serial_port.irq, serial_port.iotype);
#endif
-
+
priv->line[i] = serial8250_register_port(&serial_port);
if (priv->line[i] < 0) {
printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
break;
}
}
-
priv->nr = i;
-
return priv;
- err_deinit:
+err_deinit:
if (quirk->exit)
quirk->exit(dev);
- err_out:
+err_out:
return priv;
}
EXPORT_SYMBOL_GPL(pciserial_init_ports);
pbn_b0_8_1843200_200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_1_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_2_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_4_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_2_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_bt_4_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_8_115200 },
{ PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
/*
* VScom SPCOM800, from sl@s.pl
*/
- { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_8_921600 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b2_4_921600 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_KEYSPAN,
pbn_b2_4_115200 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIFAST,
- PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
+ PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
pbn_b2_4_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIFAST,
- PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
+ PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
pbn_b2_8_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIFAST,
- PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
+ PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
pbn_b2_16_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIFAST,
- PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
+ PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
pbn_b2_16_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIRAS,
- PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
+ PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
pbn_b2_4_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_CHASE_PCIRAS,
- PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
+ PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
pbn_b2_8_460800 },
{ PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
PCI_SUBVENDOR_ID_EXSYS,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_8_115200 },
{ PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
- PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
+ PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
+ 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
- PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
+ PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
+ 0, 0,
pbn_b0_4_1152000 },
/*
* Digitan DS560-558, from jimd@esoft.com
*/
{ PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b1_1_115200 },
/*
* The 400L and 800L have a custom setup quirk.
*/
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_1_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_2_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
- PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_b0_4_921600 },
{ PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
console is the device which receives all kernel messages and
warnings and which allows logins in single user mode).
+config SERIAL_ATMEL_PDC
+ bool "Support DMA transfers on AT91 / AT32 serial port"
+ depends on SERIAL_ATMEL
+ default y
+ help
+ Say Y here if you wish to use the PDC to do DMA transfers to
+ and from the Atmel AT91 / AT32 serial port. In order to
+ actually use DMA transfers, make sure that the use_dma_tx
+ and use_dma_rx members in the atmel_uart_data struct is set
+ appropriately for each port.
+
+ Note that break and error handling currently doesn't work
+ properly when DMA is enabled. Make sure that ports where
+ this matters don't use DMA.
+
config SERIAL_ATMEL_TTYAT
bool "Install as device ttyATn instead of ttySn"
depends on SERIAL_ATMEL=y
* Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
*
+ * DMA support added by Chip Coldwell.
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
#include <linux/sysrq.h>
#include <linux/tty_flip.h>
#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
#include <linux/atmel_pdc.h>
#include <linux/atmel_serial.h>
#include <asm/arch/gpio.h>
#endif
+#define PDC_BUFFER_SIZE 512
+/* Revisit: We should calculate this based on the actual port settings */
+#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
+
#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif
#define ATMEL_ISR_PASS_LIMIT 256
+/* UART registers. CR is write-only, hence no GET macro */
#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
-// #define UART_GET_CR(port) __raw_readl((port)->membase + ATMEL_US_CR) // is write-only
-
/* PDC registers */
#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
-//#define UART_PUT_TNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNPR)
-//#define UART_PUT_TNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TNCR)
static int (*atmel_open_hook)(struct uart_port *);
static void (*atmel_close_hook)(struct uart_port *);
+struct atmel_dma_buffer {
+ unsigned char *buf;
+ dma_addr_t dma_addr;
+ unsigned int dma_size;
+ unsigned int ofs;
+};
+
+struct atmel_uart_char {
+ u16 status;
+ u16 ch;
+};
+
+#define ATMEL_SERIAL_RINGSIZE 1024
+
/*
* We wrap our port structure around the generic uart_port.
*/
struct clk *clk; /* uart clock */
unsigned short suspended; /* is port suspended? */
int break_active; /* break being received */
+
+ short use_dma_rx; /* enable PDC receiver */
+ short pdc_rx_idx; /* current PDC RX buffer */
+ struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
+
+ short use_dma_tx; /* enable PDC transmitter */
+ struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
+
+ struct tasklet_struct tasklet;
+ unsigned int irq_status;
+ unsigned int irq_status_prev;
+
+ struct circ_buf rx_ring;
};
static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
static struct console atmel_console;
#endif
+static inline struct atmel_uart_port *
+to_atmel_uart_port(struct uart_port *uart)
+{
+ return container_of(uart, struct atmel_uart_port, uart);
+}
+
+#ifdef CONFIG_SERIAL_ATMEL_PDC
+static bool atmel_use_dma_rx(struct uart_port *port)
+{
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+
+ return atmel_port->use_dma_rx;
+}
+
+static bool atmel_use_dma_tx(struct uart_port *port)
+{
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+
+ return atmel_port->use_dma_tx;
+}
+#else
+static bool atmel_use_dma_rx(struct uart_port *port)
+{
+ return false;
+}
+
+static bool atmel_use_dma_tx(struct uart_port *port)
+{
+ return false;
+}
+#endif
+
/*
* Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
*/
#ifdef CONFIG_ARCH_AT91RM9200
if (cpu_is_at91rm9200()) {
/*
- * AT91RM9200 Errata #39: RTS0 is not internally connected to PA21.
- * We need to drive the pin manually.
+ * AT91RM9200 Errata #39: RTS0 is not internally connected
+ * to PA21. We need to drive the pin manually.
*/
if (port->mapbase == AT91RM9200_BASE_US0) {
if (mctrl & TIOCM_RTS)
*/
static void atmel_stop_tx(struct uart_port *port)
{
- UART_PUT_IDR(port, ATMEL_US_TXRDY);
+ if (atmel_use_dma_tx(port)) {
+ /* disable PDC transmit */
+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
+ UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
+ } else
+ UART_PUT_IDR(port, ATMEL_US_TXRDY);
}
/*
*/
static void atmel_start_tx(struct uart_port *port)
{
- UART_PUT_IER(port, ATMEL_US_TXRDY);
+ if (atmel_use_dma_tx(port)) {
+ if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
+ /* The transmitter is already running. Yes, we
+ really need this.*/
+ return;
+
+ UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
+ /* re-enable PDC transmit */
+ UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
+ } else
+ UART_PUT_IER(port, ATMEL_US_TXRDY);
}
/*
*/
static void atmel_stop_rx(struct uart_port *port)
{
- UART_PUT_IDR(port, ATMEL_US_RXRDY);
+ if (atmel_use_dma_rx(port)) {
+ /* disable PDC receive */
+ UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
+ UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
+ } else
+ UART_PUT_IDR(port, ATMEL_US_RXRDY);
}
/*
*/
static void atmel_enable_ms(struct uart_port *port)
{
- UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
+ UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
+ | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
}
/*
UART_PUT_CR(port, ATMEL_US_STPBRK); /* stop break */
}
+/*
+ * Stores the incoming character in the ring buffer
+ */
+static void
+atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
+ unsigned int ch)
+{
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ struct circ_buf *ring = &atmel_port->rx_ring;
+ struct atmel_uart_char *c;
+
+ if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
+ /* Buffer overflow, ignore char */
+ return;
+
+ c = &((struct atmel_uart_char *)ring->buf)[ring->head];
+ c->status = status;
+ c->ch = ch;
+
+ /* Make sure the character is stored before we update head. */
+ smp_wmb();
+
+ ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
+}
+
+/*
+ * Deal with parity, framing and overrun errors.
+ */
+static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
+{
+ /* clear error */
+ UART_PUT_CR(port, ATMEL_US_RSTSTA);
+
+ if (status & ATMEL_US_RXBRK) {
+ /* ignore side-effect */
+ status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
+ port->icount.brk++;
+ }
+ if (status & ATMEL_US_PARE)
+ port->icount.parity++;
+ if (status & ATMEL_US_FRAME)
+ port->icount.frame++;
+ if (status & ATMEL_US_OVRE)
+ port->icount.overrun++;
+}
+
/*
* Characters received (called from interrupt handler)
*/
static void atmel_rx_chars(struct uart_port *port)
{
- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
- struct tty_struct *tty = port->info->tty;
- unsigned int status, ch, flg;
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ unsigned int status, ch;
status = UART_GET_CSR(port);
while (status & ATMEL_US_RXRDY) {
ch = UART_GET_CHAR(port);
- port->icount.rx++;
-
- flg = TTY_NORMAL;
-
/*
* note that the error handling code is
* out of the main execution path
if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
| ATMEL_US_OVRE | ATMEL_US_RXBRK)
|| atmel_port->break_active)) {
- UART_PUT_CR(port, ATMEL_US_RSTSTA); /* clear error */
+
+ /* clear error */
+ UART_PUT_CR(port, ATMEL_US_RSTSTA);
+
if (status & ATMEL_US_RXBRK
&& !atmel_port->break_active) {
- status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); /* ignore side-effect */
- port->icount.brk++;
atmel_port->break_active = 1;
UART_PUT_IER(port, ATMEL_US_RXBRK);
- if (uart_handle_break(port))
- goto ignore_char;
} else {
/*
* This is either the end-of-break
status &= ~ATMEL_US_RXBRK;
atmel_port->break_active = 0;
}
- if (status & ATMEL_US_PARE)
- port->icount.parity++;
- if (status & ATMEL_US_FRAME)
- port->icount.frame++;
- if (status & ATMEL_US_OVRE)
- port->icount.overrun++;
-
- status &= port->read_status_mask;
-
- if (status & ATMEL_US_RXBRK)
- flg = TTY_BREAK;
- else if (status & ATMEL_US_PARE)
- flg = TTY_PARITY;
- else if (status & ATMEL_US_FRAME)
- flg = TTY_FRAME;
}
- if (uart_handle_sysrq_char(port, ch))
- goto ignore_char;
-
- uart_insert_char(port, status, ATMEL_US_OVRE, ch, flg);
-
- ignore_char:
+ atmel_buffer_rx_char(port, status, ch);
status = UART_GET_CSR(port);
}
- tty_flip_buffer_push(tty);
+ tasklet_schedule(&atmel_port->tasklet);
}
/*
- * Transmit characters (called from interrupt handler)
+ * Transmit characters (called from tasklet with TXRDY interrupt
+ * disabled)
*/
static void atmel_tx_chars(struct uart_port *port)
{
struct circ_buf *xmit = &port->info->xmit;
- if (port->x_char) {
+ if (port->x_char && UART_GET_CSR(port) & ATMEL_US_TXRDY) {
UART_PUT_CHAR(port, port->x_char);
port->icount.tx++;
port->x_char = 0;
- return;
}
- if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
- atmel_stop_tx(port);
+ if (uart_circ_empty(xmit) || uart_tx_stopped(port))
return;
- }
while (UART_GET_CSR(port) & ATMEL_US_TXRDY) {
UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
uart_write_wakeup(port);
- if (uart_circ_empty(xmit))
- atmel_stop_tx(port);
+ if (!uart_circ_empty(xmit))
+ UART_PUT_IER(port, ATMEL_US_TXRDY);
+}
+
+/*
+ * receive interrupt handler.
+ */
+static void
+atmel_handle_receive(struct uart_port *port, unsigned int pending)
+{
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+
+ if (atmel_use_dma_rx(port)) {
+ /*
+ * PDC receive. Just schedule the tasklet and let it
+ * figure out the details.
+ *
+ * TODO: We're not handling error flags correctly at
+ * the moment.
+ */
+ if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
+ UART_PUT_IDR(port, (ATMEL_US_ENDRX
+ | ATMEL_US_TIMEOUT));
+ tasklet_schedule(&atmel_port->tasklet);
+ }
+
+ if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
+ ATMEL_US_FRAME | ATMEL_US_PARE))
+ atmel_pdc_rxerr(port, pending);
+ }
+
+ /* Interrupt receive */
+ if (pending & ATMEL_US_RXRDY)
+ atmel_rx_chars(port);
+ else if (pending & ATMEL_US_RXBRK) {
+ /*
+ * End of break detected. If it came along with a
+ * character, atmel_rx_chars will handle it.
+ */
+ UART_PUT_CR(port, ATMEL_US_RSTSTA);
+ UART_PUT_IDR(port, ATMEL_US_RXBRK);
+ atmel_port->break_active = 0;
+ }
+}
+
+/*
+ * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
+ */
+static void
+atmel_handle_transmit(struct uart_port *port, unsigned int pending)
+{
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+
+ if (atmel_use_dma_tx(port)) {
+ /* PDC transmit */
+ if (pending & (ATMEL_US_ENDTX | ATMEL_US_TXBUFE)) {
+ UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
+ tasklet_schedule(&atmel_port->tasklet);
+ }
+ } else {
+ /* Interrupt transmit */
+ if (pending & ATMEL_US_TXRDY) {
+ UART_PUT_IDR(port, ATMEL_US_TXRDY);
+ tasklet_schedule(&atmel_port->tasklet);
+ }
+ }
+}
+
+/*
+ * status flags interrupt handler.
+ */
+static void
+atmel_handle_status(struct uart_port *port, unsigned int pending,
+ unsigned int status)
+{
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+
+ if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
+ | ATMEL_US_CTSIC)) {
+ atmel_port->irq_status = status;
+ tasklet_schedule(&atmel_port->tasklet);
+ }
}
/*
static irqreturn_t atmel_interrupt(int irq, void *dev_id)
{
struct uart_port *port = dev_id;
- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
unsigned int status, pending, pass_counter = 0;
- status = UART_GET_CSR(port);
- pending = status & UART_GET_IMR(port);
- while (pending) {
- /* Interrupt receive */
- if (pending & ATMEL_US_RXRDY)
- atmel_rx_chars(port);
- else if (pending & ATMEL_US_RXBRK) {
+ do {
+ status = UART_GET_CSR(port);
+ pending = status & UART_GET_IMR(port);
+ if (!pending)
+ break;
+
+ atmel_handle_receive(port, pending);
+ atmel_handle_status(port, pending, status);
+ atmel_handle_transmit(port, pending);
+ } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
+ */
+static void atmel_tx_dma(struct uart_port *port)
+{
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ struct circ_buf *xmit = &port->info->xmit;
+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
+ int count;
+
+ xmit->tail += pdc->ofs;
+ xmit->tail &= UART_XMIT_SIZE - 1;
+
+ port->icount.tx += pdc->ofs;
+ pdc->ofs = 0;
+
+ if (!uart_circ_empty(xmit)) {
+ /* more to transmit - setup next transfer */
+
+ /* disable PDC transmit */
+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
+ dma_sync_single_for_device(port->dev,
+ pdc->dma_addr,
+ pdc->dma_size,
+ DMA_TO_DEVICE);
+
+ count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
+ pdc->ofs = count;
+
+ UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
+ UART_PUT_TCR(port, count);
+ /* re-enable PDC transmit and interrupts */
+ UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
+ UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
+ } else {
+ /* nothing left to transmit - disable the transmitter */
+
+ /* disable PDC transmit */
+ UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
+ }
+
+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+}
+
+static void atmel_rx_from_ring(struct uart_port *port)
+{
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ struct circ_buf *ring = &atmel_port->rx_ring;
+ unsigned int flg;
+ unsigned int status;
+
+ while (ring->head != ring->tail) {
+ struct atmel_uart_char c;
+
+ /* Make sure c is loaded after head. */
+ smp_rmb();
+
+ c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
+
+ ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
+
+ port->icount.rx++;
+ status = c.status;
+ flg = TTY_NORMAL;
+
+ /*
+ * note that the error handling code is
+ * out of the main execution path
+ */
+ if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
+ | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
+ if (status & ATMEL_US_RXBRK) {
+ /* ignore side-effect */
+ status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
+
+ port->icount.brk++;
+ if (uart_handle_break(port))
+ continue;
+ }
+ if (status & ATMEL_US_PARE)
+ port->icount.parity++;
+ if (status & ATMEL_US_FRAME)
+ port->icount.frame++;
+ if (status & ATMEL_US_OVRE)
+ port->icount.overrun++;
+
+ status &= port->read_status_mask;
+
+ if (status & ATMEL_US_RXBRK)
+ flg = TTY_BREAK;
+ else if (status & ATMEL_US_PARE)
+ flg = TTY_PARITY;
+ else if (status & ATMEL_US_FRAME)
+ flg = TTY_FRAME;
+ }
+
+
+ if (uart_handle_sysrq_char(port, c.ch))
+ continue;
+
+ uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
+ }
+
+ /*
+ * Drop the lock here since it might end up calling
+ * uart_start(), which takes the lock.
+ */
+ spin_unlock(&port->lock);
+ tty_flip_buffer_push(port->info->tty);
+ spin_lock(&port->lock);
+}
+
+static void atmel_rx_from_dma(struct uart_port *port)
+{
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ struct tty_struct *tty = port->info->tty;
+ struct atmel_dma_buffer *pdc;
+ int rx_idx = atmel_port->pdc_rx_idx;
+ unsigned int head;
+ unsigned int tail;
+ unsigned int count;
+
+ do {
+ /* Reset the UART timeout early so that we don't miss one */
+ UART_PUT_CR(port, ATMEL_US_STTTO);
+
+ pdc = &atmel_port->pdc_rx[rx_idx];
+ head = UART_GET_RPR(port) - pdc->dma_addr;
+ tail = pdc->ofs;
+
+ /* If the PDC has switched buffers, RPR won't contain
+ * any address within the current buffer. Since head
+ * is unsigned, we just need a one-way comparison to
+ * find out.
+ *
+ * In this case, we just need to consume the entire
+ * buffer and resubmit it for DMA. This will clear the
+ * ENDRX bit as well, so that we can safely re-enable
+ * all interrupts below.
+ */
+ head = min(head, pdc->dma_size);
+
+ if (likely(head != tail)) {
+ dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
+ pdc->dma_size, DMA_FROM_DEVICE);
+
/*
- * End of break detected. If it came along
- * with a character, atmel_rx_chars will
- * handle it.
+ * head will only wrap around when we recycle
+ * the DMA buffer, and when that happens, we
+ * explicitly set tail to 0. So head will
+ * always be greater than tail.
*/
- UART_PUT_CR(port, ATMEL_US_RSTSTA);
- UART_PUT_IDR(port, ATMEL_US_RXBRK);
- atmel_port->break_active = 0;
+ count = head - tail;
+
+ tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
+
+ dma_sync_single_for_device(port->dev, pdc->dma_addr,
+ pdc->dma_size, DMA_FROM_DEVICE);
+
+ port->icount.rx += count;
+ pdc->ofs = head;
}
- // TODO: All reads to CSR will clear these interrupts!
- if (pending & ATMEL_US_RIIC) port->icount.rng++;
- if (pending & ATMEL_US_DSRIC) port->icount.dsr++;
- if (pending & ATMEL_US_DCDIC)
+ /*
+ * If the current buffer is full, we need to check if
+ * the next one contains any additional data.
+ */
+ if (head >= pdc->dma_size) {
+ pdc->ofs = 0;
+ UART_PUT_RNPR(port, pdc->dma_addr);
+ UART_PUT_RNCR(port, pdc->dma_size);
+
+ rx_idx = !rx_idx;
+ atmel_port->pdc_rx_idx = rx_idx;
+ }
+ } while (head >= pdc->dma_size);
+
+ /*
+ * Drop the lock here since it might end up calling
+ * uart_start(), which takes the lock.
+ */
+ spin_unlock(&port->lock);
+ tty_flip_buffer_push(tty);
+ spin_lock(&port->lock);
+
+ UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
+}
+
+/*
+ * tasklet handling tty stuff outside the interrupt handler.
+ */
+static void atmel_tasklet_func(unsigned long data)
+{
+ struct uart_port *port = (struct uart_port *)data;
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ unsigned int status;
+ unsigned int status_change;
+
+ /* The interrupt handler does not take the lock */
+ spin_lock(&port->lock);
+
+ if (atmel_use_dma_tx(port))
+ atmel_tx_dma(port);
+ else
+ atmel_tx_chars(port);
+
+ status = atmel_port->irq_status;
+ status_change = status ^ atmel_port->irq_status_prev;
+
+ if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
+ | ATMEL_US_DCD | ATMEL_US_CTS)) {
+ /* TODO: All reads to CSR will clear these interrupts! */
+ if (status_change & ATMEL_US_RI)
+ port->icount.rng++;
+ if (status_change & ATMEL_US_DSR)
+ port->icount.dsr++;
+ if (status_change & ATMEL_US_DCD)
uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
- if (pending & ATMEL_US_CTSIC)
+ if (status_change & ATMEL_US_CTS)
uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
- if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC | ATMEL_US_CTSIC))
- wake_up_interruptible(&port->info->delta_msr_wait);
- /* Interrupt transmit */
- if (pending & ATMEL_US_TXRDY)
- atmel_tx_chars(port);
+ wake_up_interruptible(&port->info->delta_msr_wait);
- if (pass_counter++ > ATMEL_ISR_PASS_LIMIT)
- break;
-
- status = UART_GET_CSR(port);
- pending = status & UART_GET_IMR(port);
+ atmel_port->irq_status_prev = status;
}
- return IRQ_HANDLED;
+
+ if (atmel_use_dma_rx(port))
+ atmel_rx_from_dma(port);
+ else
+ atmel_rx_from_ring(port);
+
+ spin_unlock(&port->lock);
}
/*
*/
static int atmel_startup(struct uart_port *port)
{
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ struct tty_struct *tty = port->info->tty;
int retval;
/*
/*
* Allocate the IRQ
*/
- retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED, "atmel_serial", port);
+ retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
+ tty ? tty->name : "atmel_serial", port);
if (retval) {
printk("atmel_serial: atmel_startup - Can't get irq\n");
return retval;
}
+ /*
+ * Initialize DMA (if necessary)
+ */
+ if (atmel_use_dma_rx(port)) {
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
+
+ pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
+ if (pdc->buf == NULL) {
+ if (i != 0) {
+ dma_unmap_single(port->dev,
+ atmel_port->pdc_rx[0].dma_addr,
+ PDC_BUFFER_SIZE,
+ DMA_FROM_DEVICE);
+ kfree(atmel_port->pdc_rx[0].buf);
+ }
+ free_irq(port->irq, port);
+ return -ENOMEM;
+ }
+ pdc->dma_addr = dma_map_single(port->dev,
+ pdc->buf,
+ PDC_BUFFER_SIZE,
+ DMA_FROM_DEVICE);
+ pdc->dma_size = PDC_BUFFER_SIZE;
+ pdc->ofs = 0;
+ }
+
+ atmel_port->pdc_rx_idx = 0;
+
+ UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
+ UART_PUT_RCR(port, PDC_BUFFER_SIZE);
+
+ UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
+ UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
+ }
+ if (atmel_use_dma_tx(port)) {
+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
+ struct circ_buf *xmit = &port->info->xmit;
+
+ pdc->buf = xmit->buf;
+ pdc->dma_addr = dma_map_single(port->dev,
+ pdc->buf,
+ UART_XMIT_SIZE,
+ DMA_TO_DEVICE);
+ pdc->dma_size = UART_XMIT_SIZE;
+ pdc->ofs = 0;
+ }
+
/*
* If there is a specific "open" function (to register
* control line interrupts)
* Finally, enable the serial port
*/
UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
- UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN); /* enable xmit & rcvr */
+ /* enable xmit & rcvr */
+ UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
- UART_PUT_IER(port, ATMEL_US_RXRDY); /* enable receive only */
+ if (atmel_use_dma_rx(port)) {
+ /* set UART timeout */
+ UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
+ UART_PUT_CR(port, ATMEL_US_STTTO);
+
+ UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
+ /* enable PDC controller */
+ UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
+ } else {
+ /* enable receive only */
+ UART_PUT_IER(port, ATMEL_US_RXRDY);
+ }
return 0;
}
*/
static void atmel_shutdown(struct uart_port *port)
{
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
+ /*
+ * Ensure everything is stopped.
+ */
+ atmel_stop_rx(port);
+ atmel_stop_tx(port);
+
+ /*
+ * Shut-down the DMA.
+ */
+ if (atmel_use_dma_rx(port)) {
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
+
+ dma_unmap_single(port->dev,
+ pdc->dma_addr,
+ pdc->dma_size,
+ DMA_FROM_DEVICE);
+ kfree(pdc->buf);
+ }
+ }
+ if (atmel_use_dma_tx(port)) {
+ struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
+
+ dma_unmap_single(port->dev,
+ pdc->dma_addr,
+ pdc->dma_size,
+ DMA_TO_DEVICE);
+ }
+
/*
* Disable all interrupts, port and break condition.
*/
/*
* Power / Clock management.
*/
-static void atmel_serial_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
+static void atmel_serial_pm(struct uart_port *port, unsigned int state,
+ unsigned int oldstate)
{
- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
switch (state) {
- case 0:
- /*
- * Enable the peripheral clock for this serial port.
- * This is called on uart_open() or a resume event.
- */
- clk_enable(atmel_port->clk);
- break;
- case 3:
- /*
- * Disable the peripheral clock for this serial port.
- * This is called on uart_close() or a suspend event.
- */
- clk_disable(atmel_port->clk);
- break;
- default:
- printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
+ case 0:
+ /*
+ * Enable the peripheral clock for this serial port.
+ * This is called on uart_open() or a resume event.
+ */
+ clk_enable(atmel_port->clk);
+ break;
+ case 3:
+ /*
+ * Disable the peripheral clock for this serial port.
+ * This is called on uart_close() or a suspend event.
+ */
+ clk_disable(atmel_port->clk);
+ break;
+ default:
+ printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
}
}
/*
* Change the port parameters
*/
-static void atmel_set_termios(struct uart_port *port, struct ktermios * termios, struct ktermios * old)
+static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
+ struct ktermios *old)
{
unsigned long flags;
unsigned int mode, imr, quot, baud;
/* Get current mode register */
- mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | ATMEL_US_PAR);
+ mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
+ | ATMEL_US_NBSTOP | ATMEL_US_PAR);
- baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
+ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
quot = uart_get_divisor(port, baud);
- if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
+ if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
quot /= 8;
mode |= ATMEL_US_USCLKS_MCK_DIV8;
}
/* parity */
if (termios->c_cflag & PARENB) {
- if (termios->c_cflag & CMSPAR) { /* Mark or Space parity */
+ /* Mark or Space parity */
+ if (termios->c_cflag & CMSPAR) {
if (termios->c_cflag & PARODD)
mode |= ATMEL_US_PAR_MARK;
else
mode |= ATMEL_US_PAR_SPACE;
- }
- else if (termios->c_cflag & PARODD)
+ } else if (termios->c_cflag & PARODD)
mode |= ATMEL_US_PAR_ODD;
else
mode |= ATMEL_US_PAR_EVEN;
- }
- else
+ } else
mode |= ATMEL_US_PAR_NONE;
spin_lock_irqsave(&port->lock, flags);
if (termios->c_iflag & (BRKINT | PARMRK))
port->read_status_mask |= ATMEL_US_RXBRK;
+ if (atmel_use_dma_rx(port))
+ /* need to enable error interrupts */
+ UART_PUT_IER(port, port->read_status_mask);
+
/*
* Characters to ignore
*/
if (termios->c_iflag & IGNPAR)
port->ignore_status_mask |= ATMEL_US_OVRE;
}
-
- // TODO: Ignore all characters if CREAD is set.
+ /* TODO: Ignore all characters if CREAD is set.*/
/* update the per-port timeout */
uart_update_timeout(port, termios->c_cflag, baud);
- /* disable interrupts and drain transmitter */
- imr = UART_GET_IMR(port); /* get interrupt mask */
- UART_PUT_IDR(port, -1); /* disable all interrupts */
- while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY)) { barrier(); }
+ /* save/disable interrupts and drain transmitter */
+ imr = UART_GET_IMR(port);
+ UART_PUT_IDR(port, -1);
+ while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
+ cpu_relax();
/* disable receiver and transmitter */
UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
/*
* Configure the port from the platform device resource info.
*/
-static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port, struct platform_device *pdev)
+static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
+ struct platform_device *pdev)
{
struct uart_port *port = &atmel_port->uart;
struct atmel_uart_data *data = pdev->dev.platform_data;
port->mapbase = pdev->resource[0].start;
port->irq = pdev->resource[1].start;
+ tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
+ (unsigned long)port);
+
+ memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
+
if (data->regs)
/* Already mapped by setup code */
port->membase = data->regs;
port->membase = NULL;
}
- if (!atmel_port->clk) { /* for console, the clock could already be configured */
+ /* for console, the clock could already be configured */
+ if (!atmel_port->clk) {
atmel_port->clk = clk_get(&pdev->dev, "usart");
clk_enable(atmel_port->clk);
port->uartclk = clk_get_rate(atmel_port->clk);
}
+
+ atmel_port->use_dma_rx = data->use_dma_rx;
+ atmel_port->use_dma_tx = data->use_dma_tx;
+ if (atmel_use_dma_tx(port))
+ port->fifosize = PDC_BUFFER_SIZE;
}
/*
atmel_pops.set_wake = fns->set_wake;
}
-
#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
static void atmel_console_putchar(struct uart_port *port, int ch)
{
while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
- barrier();
+ cpu_relax();
UART_PUT_CHAR(port, ch);
}
unsigned int status, imr;
/*
- * First, save IMR and then disable interrupts
+ * First, save IMR and then disable interrupts
*/
- imr = UART_GET_IMR(port); /* get interrupt mask */
+ imr = UART_GET_IMR(port);
UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY);
uart_console_write(port, s, count, atmel_console_putchar);
/*
- * Finally, wait for transmitter to become empty
- * and restore IMR
+ * Finally, wait for transmitter to become empty
+ * and restore IMR
*/
do {
status = UART_GET_CSR(port);
} while (!(status & ATMEL_US_TXRDY));
- UART_PUT_IER(port, imr); /* set interrupts back the way they were */
+ /* set interrupts back the way they were */
+ UART_PUT_IER(port, imr);
}
/*
- * If the port was already initialised (eg, by a boot loader), try to determine
- * the current setup.
+ * If the port was already initialised (eg, by a boot loader),
+ * try to determine the current setup.
*/
-static void __init atmel_console_get_options(struct uart_port *port, int *baud, int *parity, int *bits)
+static void __init atmel_console_get_options(struct uart_port *port, int *baud,
+ int *parity, int *bits)
{
unsigned int mr, quot;
-// TODO: CR is a write-only register
-// unsigned int cr;
-//
-// cr = UART_GET_CR(port) & (ATMEL_US_RXEN | ATMEL_US_TXEN);
-// if (cr == (ATMEL_US_RXEN | ATMEL_US_TXEN)) {
-// /* ok, the port was enabled */
-// }
+ /*
+ * If the baud rate generator isn't running, the port wasn't
+ * initialized by the boot loader.
+ */
+ quot = UART_GET_BRGR(port);
+ if (!quot)
+ return;
mr = UART_GET_MR(port) & ATMEL_US_CHRL;
if (mr == ATMEL_US_CHRL_8)
* lower than one of those, as it would make us fall through
* to a much lower baud rate than we really want.
*/
- quot = UART_GET_BRGR(port);
*baud = port->uartclk / (16 * (quot - 1));
}
int parity = 'n';
int flow = 'n';
- if (port->membase == 0) /* Port not initialized yet - delay setup */
+ if (port->membase == NULL) {
+ /* Port not initialized yet - delay setup */
return -ENODEV;
+ }
- UART_PUT_IDR(port, -1); /* disable interrupts */
+ UART_PUT_IDR(port, -1);
UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
static int __init atmel_console_init(void)
{
if (atmel_default_console_device) {
- add_preferred_console(ATMEL_DEVICENAME, atmel_default_console_device->id, NULL);
- atmel_init_port(&(atmel_ports[atmel_default_console_device->id]), atmel_default_console_device);
+ add_preferred_console(ATMEL_DEVICENAME,
+ atmel_default_console_device->id, NULL);
+ atmel_init_port(&atmel_ports[atmel_default_console_device->id],
+ atmel_default_console_device);
register_console(&atmel_console);
}
return 0;
}
+
console_initcall(atmel_console_init);
/*
*/
static int __init atmel_late_console_init(void)
{
- if (atmel_default_console_device && !(atmel_console.flags & CON_ENABLED))
+ if (atmel_default_console_device
+ && !(atmel_console.flags & CON_ENABLED))
register_console(&atmel_console);
return 0;
}
+
core_initcall(atmel_late_console_init);
+static inline bool atmel_is_console_port(struct uart_port *port)
+{
+ return port->cons && port->cons->index == port->line;
+}
+
#else
#define ATMEL_CONSOLE_DEVICE NULL
+
+static inline bool atmel_is_console_port(struct uart_port *port)
+{
+ return false;
+}
#endif
static struct uart_driver atmel_uart = {
- .owner = THIS_MODULE,
- .driver_name = "atmel_serial",
- .dev_name = ATMEL_DEVICENAME,
- .major = SERIAL_ATMEL_MAJOR,
- .minor = MINOR_START,
- .nr = ATMEL_MAX_UART,
- .cons = ATMEL_CONSOLE_DEVICE,
+ .owner = THIS_MODULE,
+ .driver_name = "atmel_serial",
+ .dev_name = ATMEL_DEVICENAME,
+ .major = SERIAL_ATMEL_MAJOR,
+ .minor = MINOR_START,
+ .nr = ATMEL_MAX_UART,
+ .cons = ATMEL_CONSOLE_DEVICE,
};
#ifdef CONFIG_PM
-static int atmel_serial_suspend(struct platform_device *pdev, pm_message_t state)
+static int atmel_serial_suspend(struct platform_device *pdev,
+ pm_message_t state)
{
struct uart_port *port = platform_get_drvdata(pdev);
- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
- if (device_may_wakeup(&pdev->dev) && !at91_suspend_entering_slow_clock())
+ if (device_may_wakeup(&pdev->dev)
+ && !at91_suspend_entering_slow_clock())
enable_irq_wake(port->irq);
else {
uart_suspend_port(&atmel_uart, port);
static int atmel_serial_resume(struct platform_device *pdev)
{
struct uart_port *port = platform_get_drvdata(pdev);
- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
if (atmel_port->suspended) {
uart_resume_port(&atmel_uart, port);
atmel_port->suspended = 0;
- }
- else
+ } else
disable_irq_wake(port->irq);
return 0;
static int __devinit atmel_serial_probe(struct platform_device *pdev)
{
struct atmel_uart_port *port;
+ void *data;
int ret;
+ BUILD_BUG_ON(!is_power_of_2(ATMEL_SERIAL_RINGSIZE));
+
port = &atmel_ports[pdev->id];
atmel_init_port(port, pdev);
+ if (!atmel_use_dma_rx(&port->uart)) {
+ ret = -ENOMEM;
+ data = kmalloc(sizeof(struct atmel_uart_char)
+ * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
+ if (!data)
+ goto err_alloc_ring;
+ port->rx_ring.buf = data;
+ }
+
ret = uart_add_one_port(&atmel_uart, &port->uart);
- if (!ret) {
- device_init_wakeup(&pdev->dev, 1);
- platform_set_drvdata(pdev, port);
+ if (ret)
+ goto err_add_port;
+
+ device_init_wakeup(&pdev->dev, 1);
+ platform_set_drvdata(pdev, port);
+
+ return 0;
+
+err_add_port:
+ kfree(port->rx_ring.buf);
+ port->rx_ring.buf = NULL;
+err_alloc_ring:
+ if (!atmel_is_console_port(&port->uart)) {
+ clk_disable(port->clk);
+ clk_put(port->clk);
+ port->clk = NULL;
}
return ret;
static int __devexit atmel_serial_remove(struct platform_device *pdev)
{
struct uart_port *port = platform_get_drvdata(pdev);
- struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
+ struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
int ret = 0;
- clk_disable(atmel_port->clk);
- clk_put(atmel_port->clk);
-
device_init_wakeup(&pdev->dev, 0);
platform_set_drvdata(pdev, NULL);
- if (port) {
- ret = uart_remove_one_port(&atmel_uart, port);
- kfree(port);
- }
+ ret = uart_remove_one_port(&atmel_uart, port);
+
+ tasklet_kill(&atmel_port->tasklet);
+ kfree(atmel_port->rx_ring.buf);
+
+ /* "port" is allocated statically, so we shouldn't free it */
+
+ clk_disable(atmel_port->clk);
+ clk_put(atmel_port->clk);
return ret;
}
#define uart_console(port) (0)
#endif
-static void uart_change_speed(struct uart_state *state, struct ktermios *old_termios);
+static void uart_change_speed(struct uart_state *state,
+ struct ktermios *old_termios);
static void uart_wait_until_sent(struct tty_struct *tty, int timeout);
static void uart_change_pm(struct uart_state *state, int pm_state);
spin_unlock_irqrestore(&port->lock, flags);
}
-#define uart_set_mctrl(port,set) uart_update_mctrl(port,set,0)
-#define uart_clear_mctrl(port,clear) uart_update_mctrl(port,0,clear)
+#define uart_set_mctrl(port, set) uart_update_mctrl(port, set, 0)
+#define uart_clear_mctrl(port, clear) uart_update_mctrl(port, 0, clear)
/*
* Startup the port. This will be called once per open. All calls
break;
default:
bits = 10;
- break; // CS8
+ break; /* CS8 */
}
if (cflag & CSTOPB)
tmp.close_delay = state->close_delay / 10;
tmp.closing_wait = state->closing_wait == USF_CLOSING_WAIT_NONE ?
ASYNC_CLOSING_WAIT_NONE :
- state->closing_wait / 10;
+ state->closing_wait / 10;
tmp.custom_divisor = port->custom_divisor;
tmp.hub6 = port->hub6;
tmp.io_type = port->iotype;
* We failed anyway.
*/
retval = -EBUSY;
- goto exit; // Added to return the correct error -Ram Gupta
+ /* Added to return the correct error -Ram Gupta */
+ goto exit;
}
}
((uart_circ_chars_pending(&state->info->xmit) > 0) &&
!state->info->tty->stopped && !state->info->tty->hw_stopped))
result &= ~TIOCSER_TEMT;
-
+
return put_user(result, value);
}
((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) ||
((arg & TIOCM_CD) && (cnow.dcd != cprev.dcd)) ||
((arg & TIOCM_CTS) && (cnow.cts != cprev.cts))) {
- ret = 0;
- break;
+ ret = 0;
+ break;
}
schedule();
return ret;
}
-static void uart_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
+static void uart_set_termios(struct tty_struct *tty,
+ struct ktermios *old_termios)
{
struct uart_state *state = tty->driver_data;
unsigned long flags;
{
struct uart_state *state = tty->driver_data;
struct uart_port *port;
-
+
BUG_ON(!kernel_locked());
if (!state || !state->port)
uart_shutdown(state);
uart_flush_buffer(tty);
- tty_ldisc_flush(tty);
-
+ tty_ldisc_flush(tty);
+
tty->closing = 0;
state->info->tty = NULL;
expire = jiffies + timeout;
pr_debug("uart_wait_until_sent(%d), jiffies=%lu, expire=%lu...\n",
- port->line, jiffies, expire);
+ port->line, jiffies, expire);
/*
* Check whether the transmitter is empty every 'char_time'.
* have set TTY_IO_ERROR for a non-existant port.
*/
if ((filp->f_flags & O_NONBLOCK) ||
- (info->tty->termios->c_cflag & CLOCAL) ||
- (info->tty->flags & (1 << TTY_IO_ERROR))) {
+ (info->tty->termios->c_cflag & CLOCAL) ||
+ (info->tty->flags & (1 << TTY_IO_ERROR)))
break;
- }
/*
* Set DTR to allow modem to know we're waiting. Do
}
/*
- * In 2.4.5, calls to uart_open are serialised by the BKL in
- * linux/fs/devices.c:chrdev_open()
+ * calls to uart_open are serialised by the BKL in
+ * fs/char_dev.c:chrdev_open()
* Note that if this fails, then uart_close() _will_ be called.
*
* In time, we want to scrap the "opening nonpresent ports"
port->line, uart_type(port),
mmio ? "mmio:0x" : "port:",
mmio ? (unsigned long long)port->mapbase
- : (unsigned long long) port->iobase,
+ : (unsigned long long) port->iobase,
port->irq);
if (port->type == PORT_UNKNOWN) {
return ret + 1;
}
- if(capable(CAP_SYS_ADMIN))
- {
+ if (capable(CAP_SYS_ADMIN)) {
mutex_lock(&state->mutex);
pm_state = state->pm_state;
if (pm_state)
if (port->icount.overrun)
ret += sprintf(buf + ret, " oe:%d",
port->icount.overrun);
-
-#define INFOBIT(bit,str) \
+
+#define INFOBIT(bit, str) \
if (port->mctrl & (bit)) \
strncat(stat_buf, (str), sizeof(stat_buf) - \
strlen(stat_buf) - 2)
-#define STATBIT(bit,str) \
+#define STATBIT(bit, str) \
if (status & (bit)) \
strncat(stat_buf, (str), sizeof(stat_buf) - \
strlen(stat_buf) - 2)
if (stat_buf[0])
stat_buf[0] = ' ';
strcat(stat_buf, "\n");
-
+
ret += sprintf(buf + ret, stat_buf);
} else {
strcat(buf, "\n");
/*
* Wait for the transmitter to empty.
*/
- for (tries = 3; !ops->tx_empty(port) && tries; tries--) {
+ for (tries = 3; !ops->tx_empty(port) && tries; tries--)
msleep(10);
- }
if (!tries)
- printk(KERN_ERR "%s%s%s%d: Unable to drain transmitter\n",
+ printk(KERN_ERR "%s%s%s%d: Unable to drain "
+ "transmitter\n",
port->dev ? port->dev->bus_id : "",
port->dev ? ": " : "",
drv->dev_name, port->line);
Generic Thermal Sysfs driver offers a generic mechanism for
thermal management. Usually it's made up of one or more thermal
zone and cooling device.
- each thermal zone contains its own temperature, trip points,
+ Each thermal zone contains its own temperature, trip points,
cooling devices.
All platforms with ACPI thermal support can use this driver.
- If you want this support, you should say Y here
+ If you want this support, you should say Y here.
}
static struct device_attribute dev_attr_cdev_type =
- __ATTR(type, 0444, thermal_cooling_device_type_show, NULL);
+__ATTR(type, 0444, thermal_cooling_device_type_show, NULL);
static DEVICE_ATTR(max_state, 0444,
thermal_cooling_device_max_state_show, NULL);
static DEVICE_ATTR(cur_state, 0644,
static ssize_t
thermal_cooling_device_trip_point_show(struct device *dev,
- struct device_attribute *attr, char *buf)
+ struct device_attribute *attr, char *buf)
{
struct thermal_cooling_device_instance *instance;
/**
* thermal_zone_bind_cooling_device - bind a cooling device to a thermal zone
- * this function is usually called in the thermal zone device .bind callback.
* @tz: thermal zone device
* @trip: indicates which trip point the cooling devices is
* associated with in this thermal zone.
* @cdev: thermal cooling device
+ *
+ * This function is usually called in the thermal zone device .bind callback.
*/
int thermal_zone_bind_cooling_device(struct thermal_zone_device *tz,
int trip,
struct thermal_cooling_device_instance *pos;
int result;
- if (trip >= tz->trips ||
- (trip < 0 && trip != THERMAL_TRIPS_NONE))
+ if (trip >= tz->trips || (trip < 0 && trip != THERMAL_TRIPS_NONE))
return -EINVAL;
if (!tz || !cdev)
kfree(dev);
return result;
}
+
EXPORT_SYMBOL(thermal_zone_bind_cooling_device);
/**
* thermal_zone_unbind_cooling_device - unbind a cooling device from a thermal zone
- * this function is usually called in the thermal zone device .unbind callback.
* @tz: thermal zone device
* @trip: indicates which trip point the cooling devices is
* associated with in this thermal zone.
* @cdev: thermal cooling device
+ *
+ * This function is usually called in the thermal zone device .unbind callback.
*/
int thermal_zone_unbind_cooling_device(struct thermal_zone_device *tz,
int trip,
mutex_lock(&tz->lock);
list_for_each_entry_safe(pos, next, &tz->cooling_devices, node) {
- if (pos->tz == tz && pos->trip == trip
- && pos->cdev == cdev) {
+ if (pos->tz == tz && pos->trip == trip && pos->cdev == cdev) {
list_del(&pos->node);
mutex_unlock(&tz->lock);
goto unbind;
kfree(pos);
return 0;
}
+
EXPORT_SYMBOL(thermal_zone_unbind_cooling_device);
static void thermal_release(struct device *dev)
* @ops: standard thermal cooling devices callbacks.
*/
struct thermal_cooling_device *thermal_cooling_device_register(char *type,
- void *devdata, struct thermal_cooling_device_ops *ops)
+ void *devdata,
+ struct
+ thermal_cooling_device_ops
+ *ops)
{
struct thermal_cooling_device *cdev;
struct thermal_zone_device *pos;
return NULL;
if (!ops || !ops->get_max_state || !ops->get_cur_state ||
- !ops->set_cur_state)
+ !ops->set_cur_state)
return NULL;
cdev = kzalloc(sizeof(struct thermal_cooling_device), GFP_KERNEL);
/* sys I/F */
if (type) {
- result = device_create_file(&cdev->device,
- &dev_attr_cdev_type);
+ result = device_create_file(&cdev->device, &dev_attr_cdev_type);
if (result)
goto unregister;
}
device_unregister(&cdev->device);
return NULL;
}
+
EXPORT_SYMBOL(thermal_cooling_device_register);
/**
* thermal_cooling_device_unregister - removes the registered thermal cooling device
- *
* @cdev: the thermal cooling device to remove.
*
* thermal_cooling_device_unregister() must be called when the device is no
}
mutex_unlock(&thermal_list_lock);
if (cdev->type[0])
- device_remove_file(&cdev->device,
- &dev_attr_cdev_type);
+ device_remove_file(&cdev->device, &dev_attr_cdev_type);
device_remove_file(&cdev->device, &dev_attr_max_state);
device_remove_file(&cdev->device, &dev_attr_cur_state);
device_unregister(&cdev->device);
return;
}
+
EXPORT_SYMBOL(thermal_cooling_device_unregister);
/**
* longer needed.
*/
struct thermal_zone_device *thermal_zone_device_register(char *type,
- int trips, void *devdata,
- struct thermal_zone_device_ops *ops)
+ int trips,
+ void *devdata, struct
+ thermal_zone_device_ops
+ *ops)
{
struct thermal_zone_device *tz;
struct thermal_cooling_device *pos;
list_add_tail(&tz->node, &thermal_tz_list);
if (ops->bind)
list_for_each_entry(pos, &thermal_cdev_list, node) {
- result = ops->bind(tz, pos);
- if (result)
- break;
+ result = ops->bind(tz, pos);
+ if (result)
+ break;
}
mutex_unlock(&thermal_list_lock);
device_unregister(&tz->device);
return NULL;
}
+
EXPORT_SYMBOL(thermal_zone_device_register);
/**
* thermal_device_unregister - removes the registered thermal zone device
- *
* @tz: the thermal zone device to remove
*/
void thermal_zone_device_unregister(struct thermal_zone_device *tz)
device_unregister(&tz->device);
return;
}
+
EXPORT_SYMBOL(thermal_zone_device_unregister);
static int __init thermal_init(void)
}
static DEVICE_ATTR (function, S_IRUGO, show_function, NULL);
-static ssize_t
-show_registers (struct device *_dev, struct device_attribute *attr, char *buf)
+static ssize_t net2280_show_registers(struct device *_dev,
+ struct device_attribute *attr, char *buf)
{
struct net2280 *dev;
char *next;
return PAGE_SIZE - size;
}
-static DEVICE_ATTR (registers, S_IRUGO, show_registers, NULL);
+static DEVICE_ATTR(registers, S_IRUGO, net2280_show_registers, NULL);
static ssize_t
show_queues (struct device *_dev, struct device_attribute *attr, char *buf)
config VGA_CONSOLE
bool "VGA text console" if EMBEDDED || !X86
- depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN && !AVR32
+ depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN && !AVR32 && !MN10300
default y
help
Saying Y here will allow you to use Linux in text mode through a
config BINFMT_AOUT
tristate "Kernel support for a.out and ECOFF binaries"
- depends on X86_32 || ALPHA || ARM || M68K || SPARC32
+ depends on ARCH_SUPPORTS_AOUT && \
+ (X86_32 || ALPHA || ARM || M68K || SPARC32)
---help---
A.out (Assembler.OUTput) is a set of formats for libraries and
executables used in the earliest versions of UNIX. Linux used
#include <linux/vfs.h>
#include <linux/parser.h>
#include <linux/bitops.h>
+#include <linux/mount.h>
+#include <linux/seq_file.h>
#include <asm/uaccess.h>
#include <asm/system.h>
#include "dir_f.h"
#include "dir_fplus.h"
+#define ADFS_DEFAULT_OWNER_MASK S_IRWXU
+#define ADFS_DEFAULT_OTHER_MASK (S_IRWXG | S_IRWXO)
+
void __adfs_error(struct super_block *sb, const char *function, const char *fmt, ...)
{
char error_buf[128];
sb->s_fs_info = NULL;
}
+static int adfs_show_options(struct seq_file *seq, struct vfsmount *mnt)
+{
+ struct adfs_sb_info *asb = ADFS_SB(mnt->mnt_sb);
+
+ if (asb->s_uid != 0)
+ seq_printf(seq, ",uid=%u", asb->s_uid);
+ if (asb->s_gid != 0)
+ seq_printf(seq, ",gid=%u", asb->s_gid);
+ if (asb->s_owner_mask != ADFS_DEFAULT_OWNER_MASK)
+ seq_printf(seq, ",ownmask=%o", asb->s_owner_mask);
+ if (asb->s_other_mask != ADFS_DEFAULT_OTHER_MASK)
+ seq_printf(seq, ",othmask=%o", asb->s_other_mask);
+
+ return 0;
+}
+
enum {Opt_uid, Opt_gid, Opt_ownmask, Opt_othmask, Opt_err};
static match_table_t tokens = {
.put_super = adfs_put_super,
.statfs = adfs_statfs,
.remount_fs = adfs_remount,
+ .show_options = adfs_show_options,
};
static struct adfs_discmap *adfs_read_map(struct super_block *sb, struct adfs_discrecord *dr)
/* set default options */
asb->s_uid = 0;
asb->s_gid = 0;
- asb->s_owner_mask = S_IRWXU;
- asb->s_other_mask = S_IRWXG | S_IRWXO;
+ asb->s_owner_mask = ADFS_DEFAULT_OWNER_MASK;
+ asb->s_other_mask = ADFS_DEFAULT_OTHER_MASK;
if (parse_options(sb, data))
goto error;
.write_super = affs_write_super,
.statfs = affs_statfs,
.remount_fs = affs_remount,
+ .show_options = generic_show_options,
};
enum {
u8 sig[4];
int ret = -EINVAL;
+ save_mount_options(sb, data);
+
pr_debug("AFFS: read_super(%s)\n",data ? (const char *)data : "no options");
sb->s_magic = AFFS_SUPER_MAGIC;
int root_block;
unsigned long mount_flags;
int res = 0;
+ char *new_opts = kstrdup(data, GFP_KERNEL);
pr_debug("AFFS: remount(flags=0x%x,opts=\"%s\")\n",*flags,data);
*flags |= MS_NODIRATIME;
- if (!parse_options(data,&uid,&gid,&mode,&reserved,&root_block,
- &blocksize,&sbi->s_prefix,sbi->s_volume,&mount_flags))
+ if (!parse_options(data, &uid, &gid, &mode, &reserved, &root_block,
+ &blocksize, &sbi->s_prefix, sbi->s_volume,
+ &mount_flags)) {
+ kfree(new_opts);
return -EINVAL;
+ }
+ kfree(sb->s_options);
+ sb->s_options = new_opts;
+
sbi->s_flags = mount_flags;
sbi->s_mode = mode;
sbi->s_uid = uid;
int afs_permission(struct inode *inode, int mask, struct nameidata *nd)
{
struct afs_vnode *vnode = AFS_FS_I(inode);
- afs_access_t access;
+ afs_access_t uninitialized_var(access);
struct key *key;
int ret;
.clear_inode = afs_clear_inode,
.umount_begin = afs_umount_begin,
.put_super = afs_put_super,
+ .show_options = generic_show_options,
};
static struct kmem_cache *afs_inode_cachep;
struct super_block *sb;
struct afs_volume *vol;
struct key *key;
+ char *new_opts = kstrdup(options, GFP_KERNEL);
int ret;
_enter(",,%s,%p", dev_name, options);
deactivate_super(sb);
goto error;
}
+ sb->s_options = new_opts;
sb->s_flags |= MS_ACTIVE;
} else {
_debug("reuse");
+ kfree(new_opts);
ASSERTCMP(sb->s_flags, &, MS_ACTIVE);
}
afs_put_volume(params.volume);
afs_put_cell(params.cell);
key_put(params.key);
+ kfree(new_opts);
_leave(" = %d", ret);
return ret;
}
/* wait_on_sync_kiocb:
* Waits on the given sync kiocb to complete.
*/
-ssize_t fastcall wait_on_sync_kiocb(struct kiocb *iocb)
+ssize_t wait_on_sync_kiocb(struct kiocb *iocb)
{
while (iocb->ki_users) {
set_current_state(TASK_UNINTERRUPTIBLE);
* go away, they will call put_ioctx and release any pinned memory
* associated with the request (held via struct page * references).
*/
-void fastcall exit_aio(struct mm_struct *mm)
+void exit_aio(struct mm_struct *mm)
{
struct kioctx *ctx = mm->ioctx_list;
mm->ioctx_list = NULL;
* Called when the last user of an aio context has gone away,
* and the struct needs to be freed.
*/
-void fastcall __put_ioctx(struct kioctx *ctx)
+void __put_ioctx(struct kioctx *ctx)
{
unsigned nr_events = ctx->max_reqs;
* This prevents races between the aio code path referencing the
* req (after submitting it) and aio_complete() freeing the req.
*/
-static struct kiocb *__aio_get_req(struct kioctx *ctx);
-static struct kiocb fastcall *__aio_get_req(struct kioctx *ctx)
+static struct kiocb *__aio_get_req(struct kioctx *ctx)
{
struct kiocb *req = NULL;
struct aio_ring *ring;
* Returns true if this put was the last user of the kiocb,
* false if the request is still in use.
*/
-int fastcall aio_put_req(struct kiocb *req)
+int aio_put_req(struct kiocb *req)
{
struct kioctx *ctx = req->ki_ctx;
int ret;
* The retry is usually executed by aio workqueue
* threads (See aio_kick_handler).
*/
-void fastcall kick_iocb(struct kiocb *iocb)
+void kick_iocb(struct kiocb *iocb)
{
/* sync iocbs are easy: they can only ever be executing from a
* single context. */
* Returns true if this is the last user of the request. The
* only other user of the request can be the cancellation code.
*/
-int fastcall aio_complete(struct kiocb *iocb, long res, long res2)
+int aio_complete(struct kiocb *iocb, long res, long res2)
{
struct kioctx *ctx = iocb->ki_ctx;
struct aio_ring_info *info;
opcode = IOCB_CMD_PWRITEV;
}
+ /* This matches the pread()/pwrite() logic */
+ if (iocb->ki_pos < 0)
+ return -EINVAL;
+
do {
ret = rw_op(iocb, &iocb->ki_iovec[iocb->ki_cur_seg],
iocb->ki_nr_segs - iocb->ki_cur_seg,
if ((ret == 0) || (iocb->ki_left == 0))
ret = iocb->ki_nbytes - iocb->ki_left;
+ /* If we managed to write some out we return that, rather than
+ * the eventual error. */
+ if (opcode == IOCB_CMD_PWRITEV
+ && ret < 0 && ret != -EIOCBQUEUED && ret != -EIOCBRETRY
+ && iocb->ki_nbytes - iocb->ki_left)
+ ret = iocb->ki_nbytes - iocb->ki_left;
+
return ret;
}
return 1;
}
-int fastcall io_submit_one(struct kioctx *ctx, struct iocb __user *user_iocb,
+int io_submit_one(struct kioctx *ctx, struct iocb __user *user_iocb,
struct iocb *iocb)
{
struct kiocb *req;
static const struct super_operations autofs_sops = {
.statfs = simple_statfs,
+ .show_options = generic_show_options,
};
enum {Opt_err, Opt_fd, Opt_uid, Opt_gid, Opt_pgrp, Opt_minproto, Opt_maxproto};
int minproto, maxproto;
pid_t pgid;
+ save_mount_options(s, data);
+
sbi = kzalloc(sizeof(*sbi), GFP_KERNEL);
if (!sbi)
goto fail_unlock;
static int autofs4_show_options(struct seq_file *m, struct vfsmount *mnt)
{
struct autofs_sb_info *sbi = autofs4_sbi(mnt->mnt_sb);
+ struct inode *root_inode = mnt->mnt_sb->s_root->d_inode;
if (!sbi)
return 0;
seq_printf(m, ",fd=%d", sbi->pipefd);
+ if (root_inode->i_uid != 0)
+ seq_printf(m, ",uid=%u", root_inode->i_uid);
+ if (root_inode->i_gid != 0)
+ seq_printf(m, ",gid=%u", root_inode->i_gid);
seq_printf(m, ",pgrp=%d", sbi->oz_pgrp);
seq_printf(m, ",timeout=%lu", sbi->exp_timeout/HZ);
seq_printf(m, ",minproto=%d", sbi->min_proto);
.put_super = befs_put_super, /* uninit super */
.statfs = befs_statfs, /* statfs */
.remount_fs = befs_remount,
+ .show_options = generic_show_options,
};
/* slab cache for befs_inode_info objects */
befs_super_block *disk_sb;
struct inode *root;
long ret = -EINVAL;
-
const unsigned long sb_block = 0;
const off_t x86_sb_off = 512;
+ save_mount_options(sb, data);
+
sb->s_fs_info = kmalloc(sizeof (*befs_sb), GFP_KERNEL);
if (sb->s_fs_info == NULL) {
printk(KERN_ERR
#include <asm/system.h>
#include <asm/uaccess.h>
#include <asm/cacheflush.h>
+#include <asm/a.out-core.h>
static int load_aout_binary(struct linux_binprm *, struct pt_regs * regs);
static int load_aout_library(struct file*);
dump.u_ar0 = offsetof(struct user, regs);
#endif
dump.signal = signr;
- dump_thread(regs, &dump);
+ aout_dump_thread(regs, &dump);
/* If the size of the dump file exceeds the rlimit, then see what would happen
if we wrote the stack, but not the data area. */
static int
create_elf_tables(struct linux_binprm *bprm, struct elfhdr *exec,
- int interp_aout, unsigned long load_addr,
- unsigned long interp_load_addr)
+ unsigned long load_addr, unsigned long interp_load_addr)
{
unsigned long p = bprm->p;
int argc = bprm->argc;
sp = STACK_ADD(p, ei_index);
- items = (argc + 1) + (envc + 1);
- if (interp_aout) {
- items += 3; /* a.out interpreters require argv & envp too */
- } else {
- items += 1; /* ELF interpreters only put argc on the stack */
- }
+ items = (argc + 1) + (envc + 1) + 1;
bprm->p = STACK_ROUND(sp, items);
/* Point sp at the lowest address on the stack */
/* Now, let's put argc (and argv, envp if appropriate) on the stack */
if (__put_user(argc, sp++))
return -EFAULT;
- if (interp_aout) {
- argv = sp + 2;
- envp = argv + argc + 1;
- if (__put_user((elf_addr_t)(unsigned long)argv, sp++) ||
- __put_user((elf_addr_t)(unsigned long)envp, sp++))
- return -EFAULT;
- } else {
- argv = sp;
- envp = argv + argc + 1;
- }
+ argv = sp;
+ envp = argv + argc + 1;
/* Populate argv and envp */
p = current->mm->arg_end = current->mm->arg_start;
return error;
}
-static unsigned long load_aout_interp(struct exec *interp_ex,
- struct file *interpreter)
-{
- unsigned long text_data, elf_entry = ~0UL;
- char __user * addr;
- loff_t offset;
-
- current->mm->end_code = interp_ex->a_text;
- text_data = interp_ex->a_text + interp_ex->a_data;
- current->mm->end_data = text_data;
- current->mm->brk = interp_ex->a_bss + text_data;
-
- switch (N_MAGIC(*interp_ex)) {
- case OMAGIC:
- offset = 32;
- addr = (char __user *)0;
- break;
- case ZMAGIC:
- case QMAGIC:
- offset = N_TXTOFF(*interp_ex);
- addr = (char __user *)N_TXTADDR(*interp_ex);
- break;
- default:
- goto out;
- }
-
- down_write(¤t->mm->mmap_sem);
- do_brk(0, text_data);
- up_write(¤t->mm->mmap_sem);
- if (!interpreter->f_op || !interpreter->f_op->read)
- goto out;
- if (interpreter->f_op->read(interpreter, addr, text_data, &offset) < 0)
- goto out;
- flush_icache_range((unsigned long)addr,
- (unsigned long)addr + text_data);
-
- down_write(¤t->mm->mmap_sem);
- do_brk(ELF_PAGESTART(text_data + ELF_MIN_ALIGN - 1),
- interp_ex->a_bss);
- up_write(¤t->mm->mmap_sem);
- elf_entry = interp_ex->a_entry;
-
-out:
- return elf_entry;
-}
-
/*
* These are the functions used to load ELF style executables and shared
* libraries. There is no binary dependent code anywhere else.
*/
#define INTERPRETER_NONE 0
-#define INTERPRETER_AOUT 1
#define INTERPRETER_ELF 2
#ifndef STACK_RND_MASK
unsigned long load_addr = 0, load_bias = 0;
int load_addr_set = 0;
char * elf_interpreter = NULL;
- unsigned int interpreter_type = INTERPRETER_NONE;
unsigned long error;
struct elf_phdr *elf_ppnt, *elf_phdata;
unsigned long elf_bss, elf_brk;
unsigned long interp_load_addr = 0;
unsigned long start_code, end_code, start_data, end_data;
unsigned long reloc_func_desc = 0;
- char passed_fileno[6];
struct files_struct *files;
int executable_stack = EXSTACK_DEFAULT;
unsigned long def_flags = 0;
/* Some simple consistency checks for the interpreter */
if (elf_interpreter) {
- static int warn;
- interpreter_type = INTERPRETER_ELF | INTERPRETER_AOUT;
-
- /* Now figure out which format our binary is */
- if ((N_MAGIC(loc->interp_ex) != OMAGIC) &&
- (N_MAGIC(loc->interp_ex) != ZMAGIC) &&
- (N_MAGIC(loc->interp_ex) != QMAGIC))
- interpreter_type = INTERPRETER_ELF;
-
- if (memcmp(loc->interp_elf_ex.e_ident, ELFMAG, SELFMAG) != 0)
- interpreter_type &= ~INTERPRETER_ELF;
-
- if (interpreter_type == INTERPRETER_AOUT && warn < 10) {
- printk(KERN_WARNING "a.out ELF interpreter %s is "
- "deprecated and will not be supported "
- "after Linux 2.6.25\n", elf_interpreter);
- warn++;
- }
-
retval = -ELIBBAD;
- if (!interpreter_type)
+ /* Not an ELF interpreter */
+ if (memcmp(loc->interp_elf_ex.e_ident, ELFMAG, SELFMAG) != 0)
goto out_free_dentry;
-
- /* Make sure only one type was selected */
- if ((interpreter_type & INTERPRETER_ELF) &&
- interpreter_type != INTERPRETER_ELF) {
- // FIXME - ratelimit this before re-enabling
- // printk(KERN_WARNING "ELF: Ambiguous type, using ELF\n");
- interpreter_type = INTERPRETER_ELF;
- }
/* Verify the interpreter has a valid arch */
- if ((interpreter_type == INTERPRETER_ELF) &&
- !elf_check_arch(&loc->interp_elf_ex))
+ if (!elf_check_arch(&loc->interp_elf_ex))
goto out_free_dentry;
} else {
/* Executables without an interpreter also need a personality */
SET_PERSONALITY(loc->elf_ex, 0);
}
- /* OK, we are done with that, now set up the arg stuff,
- and then start this sucker up */
- if ((!bprm->sh_bang) && (interpreter_type == INTERPRETER_AOUT)) {
- char *passed_p = passed_fileno;
- sprintf(passed_fileno, "%d", elf_exec_fileno);
-
- if (elf_interpreter) {
- retval = copy_strings_kernel(1, &passed_p, bprm);
- if (retval)
- goto out_free_dentry;
- bprm->argc++;
- }
- }
-
/* Flush all traces of the currently running executable */
retval = flush_old_exec(bprm);
if (retval)
}
if (elf_interpreter) {
- if (interpreter_type == INTERPRETER_AOUT) {
- elf_entry = load_aout_interp(&loc->interp_ex,
- interpreter);
- } else {
- unsigned long uninitialized_var(interp_map_addr);
-
- elf_entry = load_elf_interp(&loc->interp_elf_ex,
- interpreter,
- &interp_map_addr,
- load_bias);
- if (!IS_ERR((void *)elf_entry)) {
- /*
- * load_elf_interp() returns relocation
- * adjustment
- */
- interp_load_addr = elf_entry;
- elf_entry += loc->interp_elf_ex.e_entry;
- }
+ unsigned long uninitialized_var(interp_map_addr);
+
+ elf_entry = load_elf_interp(&loc->interp_elf_ex,
+ interpreter,
+ &interp_map_addr,
+ load_bias);
+ if (!IS_ERR((void *)elf_entry)) {
+ /*
+ * load_elf_interp() returns relocation
+ * adjustment
+ */
+ interp_load_addr = elf_entry;
+ elf_entry += loc->interp_elf_ex.e_entry;
}
if (BAD_ADDR(elf_entry)) {
force_sig(SIGSEGV, current);
kfree(elf_phdata);
- if (interpreter_type != INTERPRETER_AOUT)
- sys_close(elf_exec_fileno);
+ sys_close(elf_exec_fileno);
set_binfmt(&elf_format);
compute_creds(bprm);
current->flags &= ~PF_FORKNOEXEC;
retval = create_elf_tables(bprm, &loc->elf_ex,
- (interpreter_type == INTERPRETER_AOUT),
load_addr, interp_load_addr);
if (retval < 0) {
send_sig(SIGKILL, current, 0);
goto out;
}
/* N.B. passed_fileno might not be initialized? */
- if (interpreter_type == INTERPRETER_AOUT)
- current->mm->arg_start += strlen(passed_fileno) + 1;
current->mm->end_code = end_code;
current->mm->start_code = start_code;
current->mm->start_data = start_data;
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/mman.h>
-#include <linux/a.out.h>
#include <linux/errno.h>
#include <linux/signal.h>
#include <linux/string.h>
#include <linux/personality.h>
#include <linux/init.h>
-#include <asm/a.out.h>
#include <asm/uaccess.h>
#include <asm/pgtable.h>
return 0;
}
-void fastcall __lock_buffer(struct buffer_head *bh)
+void __lock_buffer(struct buffer_head *bh)
{
wait_on_bit_lock(&bh->b_state, BH_Lock, sync_buffer,
TASK_UNINTERRUPTIBLE);
}
EXPORT_SYMBOL(__lock_buffer);
-void fastcall unlock_buffer(struct buffer_head *bh)
+void unlock_buffer(struct buffer_head *bh)
{
smp_mb__before_clear_bit();
clear_buffer_locked(bh);
} else {
BUG_ON(mapping->assoc_mapping != buffer_mapping);
}
- if (list_empty(&bh->b_assoc_buffers)) {
+ if (!bh->b_assoc_map) {
spin_lock(&buffer_mapping->private_lock);
list_move_tail(&bh->b_assoc_buffers,
&mapping->private_list);
{
struct buffer_head *bh;
struct list_head tmp;
+ struct address_space *mapping;
int err = 0, err2;
INIT_LIST_HEAD(&tmp);
spin_lock(lock);
while (!list_empty(list)) {
bh = BH_ENTRY(list->next);
+ mapping = bh->b_assoc_map;
__remove_assoc_queue(bh);
+ /* Avoid race with mark_buffer_dirty_inode() which does
+ * a lockless check and we rely on seeing the dirty bit */
+ smp_mb();
if (buffer_dirty(bh) || buffer_locked(bh)) {
list_add(&bh->b_assoc_buffers, &tmp);
+ bh->b_assoc_map = mapping;
if (buffer_dirty(bh)) {
get_bh(bh);
spin_unlock(lock);
while (!list_empty(&tmp)) {
bh = BH_ENTRY(tmp.prev);
- list_del_init(&bh->b_assoc_buffers);
get_bh(bh);
+ mapping = bh->b_assoc_map;
+ __remove_assoc_queue(bh);
+ /* Avoid race with mark_buffer_dirty_inode() which does
+ * a lockless check and we rely on seeing the dirty bit */
+ smp_mb();
+ if (buffer_dirty(bh)) {
+ list_add(&bh->b_assoc_buffers,
+ &bh->b_assoc_map->private_list);
+ bh->b_assoc_map = mapping;
+ }
spin_unlock(lock);
wait_on_buffer(bh);
if (!buffer_uptodate(bh))
* mark_buffer_dirty() is atomic. It takes bh->b_page->mapping->private_lock,
* mapping->tree_lock and the global inode_lock.
*/
-void fastcall mark_buffer_dirty(struct buffer_head *bh)
+void mark_buffer_dirty(struct buffer_head *bh)
{
WARN_ON_ONCE(!buffer_uptodate(bh));
if (!buffer_dirty(bh) && !test_set_buffer_dirty(bh))
void __bforget(struct buffer_head *bh)
{
clear_buffer_dirty(bh);
- if (!list_empty(&bh->b_assoc_buffers)) {
+ if (bh->b_assoc_map) {
struct address_space *buffer_mapping = bh->b_page->mapping;
spin_lock(&buffer_mapping->private_lock);
{
on_each_cpu(invalidate_bh_lru, NULL, 1, 1);
}
+EXPORT_SYMBOL_GPL(invalidate_bh_lrus);
void set_bh_page(struct buffer_head *bh,
struct page *page, unsigned long offset)
do {
struct buffer_head *next = bh->b_this_page;
- if (!list_empty(&bh->b_assoc_buffers))
+ if (bh->b_assoc_map)
__remove_assoc_queue(bh);
bh = next;
} while (bh != head);
/*
* Called every time a character special file is opened
*/
-int chrdev_open(struct inode * inode, struct file * filp)
+static int chrdev_open(struct inode *inode, struct file *filp)
{
struct cdev *p;
struct cdev *new = NULL;
.follow_link = debugfs_follow_link,
};
-static void debugfs_u8_set(void *data, u64 val)
+static int debugfs_u8_set(void *data, u64 val)
{
*(u8 *)data = val;
+ return 0;
}
-static u64 debugfs_u8_get(void *data)
+static int debugfs_u8_get(void *data, u64 *val)
{
- return *(u8 *)data;
+ *val = *(u8 *)data;
+ return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_u8, debugfs_u8_get, debugfs_u8_set, "%llu\n");
}
EXPORT_SYMBOL_GPL(debugfs_create_u8);
-static void debugfs_u16_set(void *data, u64 val)
+static int debugfs_u16_set(void *data, u64 val)
{
*(u16 *)data = val;
+ return 0;
}
-static u64 debugfs_u16_get(void *data)
+static int debugfs_u16_get(void *data, u64 *val)
{
- return *(u16 *)data;
+ *val = *(u16 *)data;
+ return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_u16, debugfs_u16_get, debugfs_u16_set, "%llu\n");
}
EXPORT_SYMBOL_GPL(debugfs_create_u16);
-static void debugfs_u32_set(void *data, u64 val)
+static int debugfs_u32_set(void *data, u64 val)
{
*(u32 *)data = val;
+ return 0;
}
-static u64 debugfs_u32_get(void *data)
+static int debugfs_u32_get(void *data, u64 *val)
{
- return *(u32 *)data;
+ *val = *(u32 *)data;
+ return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_u32, debugfs_u32_get, debugfs_u32_set, "%llu\n");
}
EXPORT_SYMBOL_GPL(debugfs_create_u32);
-static void debugfs_u64_set(void *data, u64 val)
+static int debugfs_u64_set(void *data, u64 val)
{
*(u64 *)data = val;
+ return 0;
}
-static u64 debugfs_u64_get(void *data)
+static int debugfs_u64_get(void *data, u64 *val)
{
- return *(u64 *)data;
+ *val = *(u64 *)data;
+ return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_u64, debugfs_u64_get, debugfs_u64_set, "%llu\n");
#include <linux/devpts_fs.h>
#include <linux/parser.h>
#include <linux/fsnotify.h>
+#include <linux/seq_file.h>
#define DEVPTS_SUPER_MAGIC 0x1cd1
+#define DEVPTS_DEFAULT_MODE 0600
+
static struct vfsmount *devpts_mnt;
static struct dentry *devpts_root;
uid_t uid;
gid_t gid;
umode_t mode;
-} config = {.mode = 0600};
+} config = {.mode = DEVPTS_DEFAULT_MODE};
enum {
Opt_uid, Opt_gid, Opt_mode,
config.setgid = 0;
config.uid = 0;
config.gid = 0;
- config.mode = 0600;
+ config.mode = DEVPTS_DEFAULT_MODE;
while ((p = strsep(&data, ",")) != NULL) {
substring_t args[MAX_OPT_ARGS];
case Opt_mode:
if (match_octal(&args[0], &option))
return -EINVAL;
- config.mode = option & ~S_IFMT;
+ config.mode = option & S_IALLUGO;
break;
default:
printk(KERN_ERR "devpts: called with bogus options\n");
return 0;
}
+static int devpts_show_options(struct seq_file *seq, struct vfsmount *vfs)
+{
+ if (config.setuid)
+ seq_printf(seq, ",uid=%u", config.uid);
+ if (config.setgid)
+ seq_printf(seq, ",gid=%u", config.gid);
+ seq_printf(seq, ",mode=%03o", config.mode);
+
+ return 0;
+}
+
static const struct super_operations devpts_sops = {
.statfs = simple_statfs,
.remount_fs = devpts_remount,
+ .show_options = devpts_show_options,
};
static int
dlm_user_add_ast(lkb, type);
return;
}
- DLM_ASSERT(lkb->lkb_astaddr != DLM_FAKE_USER_AST, dlm_print_lkb(lkb););
spin_lock(&ast_queue_lock);
if (!(lkb->lkb_ast_type & (AST_COMP | AST_BAST))) {
struct dlm_ls *ls = NULL;
struct dlm_rsb *r = NULL;
struct dlm_lkb *lkb;
- void (*cast) (long param);
- void (*bast) (long param, int mode);
+ void (*cast) (void *astparam);
+ void (*bast) (void *astparam, int mode);
int type = 0, found, bmode;
for (;;) {
if (!found)
break;
- cast = lkb->lkb_astaddr;
- bast = lkb->lkb_bastaddr;
+ cast = lkb->lkb_astfn;
+ bast = lkb->lkb_bastfn;
bmode = lkb->lkb_bastmode;
if ((type & AST_COMP) && cast)
},
};
-int dlm_config_init(void)
+int __init dlm_config_init(void)
{
config_group_init(&clusters_root.subsys.su_group);
mutex_init(&clusters_root.subsys.su_mutex);
static void print_lock(struct seq_file *s, struct dlm_lkb *lkb, struct dlm_rsb *r)
{
- struct dlm_user_args *ua;
unsigned int waiting = 0;
uint64_t xid = 0;
if (lkb->lkb_flags & DLM_IFL_USER) {
- ua = (struct dlm_user_args *) lkb->lkb_astparam;
- if (ua)
- xid = ua->xid;
+ if (lkb->lkb_ua)
+ xid = lkb->lkb_ua->xid;
}
if (lkb->lkb_timestamp)
debugfs_remove(ls->ls_debug_locks_dentry);
}
-int dlm_register_debugfs(void)
+int __init dlm_register_debugfs(void)
{
mutex_init(&debug_buf_lock);
dlm_root = debugfs_create_dir("dlm", NULL);
last_len = 0;
for (;;) {
+ int left;
error = dlm_recovery_stopped(ls);
if (error)
goto out_free;
* pick namelen/name pairs out of received buffer
*/
- b = ls->ls_recover_buf + sizeof(struct dlm_rcom);
+ b = ls->ls_recover_buf->rc_buf;
+ left = ls->ls_recover_buf->rc_header.h_length;
+ left -= sizeof(struct dlm_rcom);
for (;;) {
- memcpy(&namelen, b, sizeof(uint16_t));
- namelen = be16_to_cpu(namelen);
- b += sizeof(uint16_t);
+ __be16 v;
+
+ error = -EINVAL;
+ if (left < sizeof(__be16))
+ goto out_free;
+
+ memcpy(&v, b, sizeof(__be16));
+ namelen = be16_to_cpu(v);
+ b += sizeof(__be16);
+ left -= sizeof(__be16);
/* namelen of 0xFFFFF marks end of names for
this node; namelen of 0 marks end of the
if (!namelen)
break;
+ if (namelen > left)
+ goto out_free;
+
+ if (namelen > DLM_RESNAME_MAXLEN)
+ goto out_free;
+
error = -ENOMEM;
de = get_free_de(ls, namelen);
if (!de)
memcpy(de->name, b, namelen);
memcpy(last_name, b, namelen);
b += namelen;
+ left -= namelen;
add_entry_to_hash(ls, de);
count++;
write_unlock(&ls->ls_dirtbl[bucket].lock);
+ if (namelen > DLM_RESNAME_MAXLEN)
+ return -EINVAL;
+
de = kzalloc(sizeof(struct dlm_direntry) + namelen, GFP_KERNEL);
if (!de)
return -ENOMEM;
} \
}
-#define DLM_FAKE_USER_AST ERR_PTR(-EINVAL)
-
struct dlm_direntry {
struct list_head list;
struct dlm_args {
uint32_t flags;
- void *astaddr;
- long astparam;
- void *bastaddr;
+ void (*astfn) (void *astparam);
+ void *astparam;
+ void (*bastfn) (void *astparam, int mode);
int mode;
struct dlm_lksb *lksb;
unsigned long timeout;
char *lkb_lvbptr;
struct dlm_lksb *lkb_lksb; /* caller's status block */
- void *lkb_astaddr; /* caller's ast function */
- void *lkb_bastaddr; /* caller's bast function */
- long lkb_astparam; /* caller's ast arg */
+ void (*lkb_astfn) (void *astparam);
+ void (*lkb_bastfn) (void *astparam, int mode);
+ union {
+ void *lkb_astparam; /* caller's ast arg */
+ struct dlm_user_args *lkb_ua;
+ };
};
char rc_buf[0];
};
+union dlm_packet {
+ struct dlm_header header; /* common to other two */
+ struct dlm_message message;
+ struct dlm_rcom rcom;
+};
+
struct rcom_config {
- uint32_t rf_lvblen;
- uint32_t rf_lsflags;
- uint64_t rf_unused;
+ __le32 rf_lvblen;
+ __le32 rf_lsflags;
+ __le64 rf_unused;
};
struct rcom_lock {
- uint32_t rl_ownpid;
- uint32_t rl_lkid;
- uint32_t rl_remid;
- uint32_t rl_parent_lkid;
- uint32_t rl_parent_remid;
- uint32_t rl_exflags;
- uint32_t rl_flags;
- uint32_t rl_lvbseq;
- int rl_result;
+ __le32 rl_ownpid;
+ __le32 rl_lkid;
+ __le32 rl_remid;
+ __le32 rl_parent_lkid;
+ __le32 rl_parent_remid;
+ __le32 rl_exflags;
+ __le32 rl_flags;
+ __le32 rl_lvbseq;
+ __le32 rl_result;
int8_t rl_rqmode;
int8_t rl_grmode;
int8_t rl_status;
int8_t rl_asts;
- uint16_t rl_wait_type;
- uint16_t rl_namelen;
+ __le16 rl_wait_type;
+ __le16 rl_namelen;
char rl_name[DLM_RESNAME_MAXLEN];
char rl_lvb[0];
};
struct rw_semaphore ls_recv_active; /* block dlm_recv */
struct list_head ls_requestqueue;/* queue remote requests */
struct mutex ls_requestqueue_mutex;
- char *ls_recover_buf;
+ struct dlm_rcom *ls_recover_buf;
int ls_recover_nodeid; /* for debugging */
uint64_t ls_rcom_seq;
spinlock_t ls_rcom_spin;
{
struct dlm_rsb *r, *tmp;
uint32_t hash, bucket;
- int error = 0;
+ int error = -EINVAL;
+
+ if (namelen > DLM_RESNAME_MAXLEN)
+ goto out;
if (dlm_no_directory(ls))
flags |= R_CREATE;
+ error = 0;
hash = jhash(name, namelen, 0);
bucket = hash & (ls->ls_rsbtbl_size - 1);
b = dlm_lvb_operations[lkb->lkb_grmode + 1][lkb->lkb_rqmode + 1];
if (b == 1) {
int len = receive_extralen(ms);
+ if (len > DLM_RESNAME_MAXLEN)
+ len = DLM_RESNAME_MAXLEN;
memcpy(lkb->lkb_lvbptr, ms->m_extra, len);
lkb->lkb_lvbseq = ms->m_lvbseq;
}
*/
list_for_each_entry_safe(lkb, s, &r->res_grantqueue, lkb_statequeue) {
- if (lkb->lkb_bastaddr && lock_requires_bast(lkb, high, cw)) {
+ if (lkb->lkb_bastfn && lock_requires_bast(lkb, high, cw)) {
if (cw && high == DLM_LOCK_PR)
queue_bast(r, lkb, DLM_LOCK_CW);
else
struct dlm_lkb *gr;
list_for_each_entry(gr, head, lkb_statequeue) {
- if (gr->lkb_bastaddr && modes_require_bast(gr, lkb)) {
+ if (gr->lkb_bastfn && modes_require_bast(gr, lkb)) {
queue_bast(r, gr, lkb->lkb_rqmode);
gr->lkb_highbast = lkb->lkb_rqmode;
}
}
static int set_lock_args(int mode, struct dlm_lksb *lksb, uint32_t flags,
- int namelen, unsigned long timeout_cs, void *ast,
- void *astarg, void *bast, struct dlm_args *args)
+ int namelen, unsigned long timeout_cs,
+ void (*ast) (void *astparam),
+ void *astparam,
+ void (*bast) (void *astparam, int mode),
+ struct dlm_args *args)
{
int rv = -EINVAL;
an active lkb cannot be modified before locking the rsb */
args->flags = flags;
- args->astaddr = ast;
- args->astparam = (long) astarg;
- args->bastaddr = bast;
+ args->astfn = ast;
+ args->astparam = astparam;
+ args->bastfn = bast;
args->timeout = timeout_cs;
args->mode = mode;
args->lksb = lksb;
return -EINVAL;
args->flags = flags;
- args->astparam = (long) astarg;
+ args->astparam = astarg;
return 0;
}
lkb->lkb_exflags = args->flags;
lkb->lkb_sbflags = 0;
- lkb->lkb_astaddr = args->astaddr;
+ lkb->lkb_astfn = args->astfn;
lkb->lkb_astparam = args->astparam;
- lkb->lkb_bastaddr = args->bastaddr;
+ lkb->lkb_bastfn = args->bastfn;
lkb->lkb_rqmode = args->mode;
lkb->lkb_lksb = args->lksb;
lkb->lkb_lvbptr = args->lksb->sb_lvbptr;
/* m_result and m_bastmode are set from function args,
not from lkb fields */
- if (lkb->lkb_bastaddr)
+ if (lkb->lkb_bastfn)
ms->m_asts |= AST_BAST;
- if (lkb->lkb_astaddr)
+ if (lkb->lkb_astfn)
ms->m_asts |= AST_COMP;
/* compare with switch in create_message; send_remove() doesn't
if (!lkb->lkb_lvbptr)
return -ENOMEM;
len = receive_extralen(ms);
+ if (len > DLM_RESNAME_MAXLEN)
+ len = DLM_RESNAME_MAXLEN;
memcpy(lkb->lkb_lvbptr, ms->m_extra, len);
}
return 0;
}
+static void fake_bastfn(void *astparam, int mode)
+{
+ log_print("fake_bastfn should not be called");
+}
+
+static void fake_astfn(void *astparam)
+{
+ log_print("fake_astfn should not be called");
+}
+
static int receive_request_args(struct dlm_ls *ls, struct dlm_lkb *lkb,
struct dlm_message *ms)
{
lkb->lkb_remid = ms->m_lkid;
lkb->lkb_grmode = DLM_LOCK_IV;
lkb->lkb_rqmode = ms->m_rqmode;
- lkb->lkb_bastaddr = (void *) (long) (ms->m_asts & AST_BAST);
- lkb->lkb_astaddr = (void *) (long) (ms->m_asts & AST_COMP);
+
+ lkb->lkb_bastfn = (ms->m_asts & AST_BAST) ? &fake_bastfn : NULL;
+ lkb->lkb_astfn = (ms->m_asts & AST_COMP) ? &fake_astfn : NULL;
if (lkb->lkb_exflags & DLM_LKF_VALBLK) {
/* lkb was just created so there won't be an lvb yet */
int nodeid)
{
if (dlm_locking_stopped(ls)) {
- dlm_add_requestqueue(ls, nodeid, (struct dlm_header *) ms);
+ dlm_add_requestqueue(ls, nodeid, ms);
} else {
dlm_wait_requestqueue(ls);
_receive_message(ls, ms);
standard locking activity) or an RCOM (recovery message sent as part of
lockspace recovery). */
-void dlm_receive_buffer(struct dlm_header *hd, int nodeid)
+void dlm_receive_buffer(union dlm_packet *p, int nodeid)
{
- struct dlm_message *ms = (struct dlm_message *) hd;
- struct dlm_rcom *rc = (struct dlm_rcom *) hd;
+ struct dlm_header *hd = &p->header;
struct dlm_ls *ls;
int type = 0;
switch (hd->h_cmd) {
case DLM_MSG:
- dlm_message_in(ms);
- type = ms->m_type;
+ dlm_message_in(&p->message);
+ type = p->message.m_type;
break;
case DLM_RCOM:
- dlm_rcom_in(rc);
- type = rc->rc_type;
+ dlm_rcom_in(&p->rcom);
+ type = p->rcom.rc_type;
break;
default:
log_print("invalid h_cmd %d from %u", hd->h_cmd, nodeid);
hd->h_lockspace, nodeid, hd->h_cmd, type);
if (hd->h_cmd == DLM_RCOM && type == DLM_RCOM_STATUS)
- dlm_send_ls_not_ready(nodeid, rc);
+ dlm_send_ls_not_ready(nodeid, &p->rcom);
return;
}
down_read(&ls->ls_recv_active);
if (hd->h_cmd == DLM_MSG)
- dlm_receive_message(ls, ms, nodeid);
+ dlm_receive_message(ls, &p->message, nodeid);
else
- dlm_receive_rcom(ls, rc, nodeid);
+ dlm_receive_rcom(ls, &p->rcom, nodeid);
up_read(&ls->ls_recv_active);
dlm_put_lockspace(ls);
return NULL;
}
+/* needs at least dlm_rcom + rcom_lock */
static int receive_rcom_lock_args(struct dlm_ls *ls, struct dlm_lkb *lkb,
struct dlm_rsb *r, struct dlm_rcom *rc)
{
struct rcom_lock *rl = (struct rcom_lock *) rc->rc_buf;
- int lvblen;
lkb->lkb_nodeid = rc->rc_header.h_nodeid;
- lkb->lkb_ownpid = rl->rl_ownpid;
- lkb->lkb_remid = rl->rl_lkid;
- lkb->lkb_exflags = rl->rl_exflags;
- lkb->lkb_flags = rl->rl_flags & 0x0000FFFF;
+ lkb->lkb_ownpid = le32_to_cpu(rl->rl_ownpid);
+ lkb->lkb_remid = le32_to_cpu(rl->rl_lkid);
+ lkb->lkb_exflags = le32_to_cpu(rl->rl_exflags);
+ lkb->lkb_flags = le32_to_cpu(rl->rl_flags) & 0x0000FFFF;
lkb->lkb_flags |= DLM_IFL_MSTCPY;
- lkb->lkb_lvbseq = rl->rl_lvbseq;
+ lkb->lkb_lvbseq = le32_to_cpu(rl->rl_lvbseq);
lkb->lkb_rqmode = rl->rl_rqmode;
lkb->lkb_grmode = rl->rl_grmode;
/* don't set lkb_status because add_lkb wants to itself */
- lkb->lkb_bastaddr = (void *) (long) (rl->rl_asts & AST_BAST);
- lkb->lkb_astaddr = (void *) (long) (rl->rl_asts & AST_COMP);
+ lkb->lkb_bastfn = (rl->rl_asts & AST_BAST) ? &fake_bastfn : NULL;
+ lkb->lkb_astfn = (rl->rl_asts & AST_COMP) ? &fake_astfn : NULL;
if (lkb->lkb_exflags & DLM_LKF_VALBLK) {
+ int lvblen = rc->rc_header.h_length - sizeof(struct dlm_rcom) -
+ sizeof(struct rcom_lock);
+ if (lvblen > ls->ls_lvblen)
+ return -EINVAL;
lkb->lkb_lvbptr = dlm_allocate_lvb(ls);
if (!lkb->lkb_lvbptr)
return -ENOMEM;
- lvblen = rc->rc_header.h_length - sizeof(struct dlm_rcom) -
- sizeof(struct rcom_lock);
memcpy(lkb->lkb_lvbptr, rl->rl_lvb, lvblen);
}
The real granted mode of these converting locks cannot be determined
until all locks have been rebuilt on the rsb (recover_conversion) */
- if (rl->rl_wait_type == DLM_MSG_CONVERT && middle_conversion(lkb)) {
+ if (rl->rl_wait_type == cpu_to_le16(DLM_MSG_CONVERT) &&
+ middle_conversion(lkb)) {
rl->rl_status = DLM_LKSTS_CONVERT;
lkb->lkb_grmode = DLM_LOCK_IV;
rsb_set_flag(r, RSB_RECOVER_CONVERT);
the given values and send back our lkid. We send back our lkid by sending
back the rcom_lock struct we got but with the remid field filled in. */
+/* needs at least dlm_rcom + rcom_lock */
int dlm_recover_master_copy(struct dlm_ls *ls, struct dlm_rcom *rc)
{
struct rcom_lock *rl = (struct rcom_lock *) rc->rc_buf;
goto out;
}
- error = find_rsb(ls, rl->rl_name, rl->rl_namelen, R_MASTER, &r);
+ error = find_rsb(ls, rl->rl_name, le16_to_cpu(rl->rl_namelen),
+ R_MASTER, &r);
if (error)
goto out;
lock_rsb(r);
- lkb = search_remid(r, rc->rc_header.h_nodeid, rl->rl_lkid);
+ lkb = search_remid(r, rc->rc_header.h_nodeid, le32_to_cpu(rl->rl_lkid));
if (lkb) {
error = -EEXIST;
goto out_remid;
out_remid:
/* this is the new value returned to the lock holder for
saving in its process-copy lkb */
- rl->rl_remid = lkb->lkb_id;
+ rl->rl_remid = cpu_to_le32(lkb->lkb_id);
out_unlock:
unlock_rsb(r);
put_rsb(r);
out:
if (error)
- log_debug(ls, "recover_master_copy %d %x", error, rl->rl_lkid);
- rl->rl_result = error;
+ log_debug(ls, "recover_master_copy %d %x", error,
+ le32_to_cpu(rl->rl_lkid));
+ rl->rl_result = cpu_to_le32(error);
return error;
}
+/* needs at least dlm_rcom + rcom_lock */
int dlm_recover_process_copy(struct dlm_ls *ls, struct dlm_rcom *rc)
{
struct rcom_lock *rl = (struct rcom_lock *) rc->rc_buf;
struct dlm_lkb *lkb;
int error;
- error = find_lkb(ls, rl->rl_lkid, &lkb);
+ error = find_lkb(ls, le32_to_cpu(rl->rl_lkid), &lkb);
if (error) {
- log_error(ls, "recover_process_copy no lkid %x", rl->rl_lkid);
+ log_error(ls, "recover_process_copy no lkid %x",
+ le32_to_cpu(rl->rl_lkid));
return error;
}
DLM_ASSERT(is_process_copy(lkb), dlm_print_lkb(lkb););
- error = rl->rl_result;
+ error = le32_to_cpu(rl->rl_result);
r = lkb->lkb_resource;
hold_rsb(r);
log_debug(ls, "master copy exists %x", lkb->lkb_id);
/* fall through */
case 0:
- lkb->lkb_remid = rl->rl_remid;
+ lkb->lkb_remid = le32_to_cpu(rl->rl_remid);
break;
default:
log_error(ls, "dlm_recover_process_copy unknown error %d %x",
lock and that lkb_astparam is the dlm_user_args structure. */
error = set_lock_args(mode, &ua->lksb, flags, namelen, timeout_cs,
- DLM_FAKE_USER_AST, ua, DLM_FAKE_USER_AST, &args);
+ fake_astfn, ua, fake_bastfn, &args);
lkb->lkb_flags |= DLM_IFL_USER;
ua->old_mode = DLM_LOCK_IV;
/* user can change the params on its lock when it converts it, or
add an lvb that didn't exist before */
- ua = (struct dlm_user_args *)lkb->lkb_astparam;
+ ua = lkb->lkb_ua;
if (flags & DLM_LKF_VALBLK && !ua->lksb.sb_lvbptr) {
ua->lksb.sb_lvbptr = kzalloc(DLM_USER_LVB_LEN, GFP_KERNEL);
ua->old_mode = lkb->lkb_grmode;
error = set_lock_args(mode, &ua->lksb, flags, 0, timeout_cs,
- DLM_FAKE_USER_AST, ua, DLM_FAKE_USER_AST, &args);
+ fake_astfn, ua, fake_bastfn, &args);
if (error)
goto out_put;
if (error)
goto out;
- ua = (struct dlm_user_args *)lkb->lkb_astparam;
+ ua = lkb->lkb_ua;
if (lvb_in && ua->lksb.sb_lvbptr)
memcpy(ua->lksb.sb_lvbptr, lvb_in, DLM_USER_LVB_LEN);
if (error)
goto out;
- ua = (struct dlm_user_args *)lkb->lkb_astparam;
+ ua = lkb->lkb_ua;
if (ua_tmp->castparam)
ua->castparam = ua_tmp->castparam;
ua->user_lksb = ua_tmp->user_lksb;
if (error)
goto out;
- ua = (struct dlm_user_args *)lkb->lkb_astparam;
+ ua = lkb->lkb_ua;
error = set_unlock_args(flags, ua, &args);
if (error)
static int orphan_proc_lock(struct dlm_ls *ls, struct dlm_lkb *lkb)
{
- struct dlm_user_args *ua = (struct dlm_user_args *)lkb->lkb_astparam;
struct dlm_args args;
int error;
list_add_tail(&lkb->lkb_ownqueue, &ls->ls_orphans);
mutex_unlock(&ls->ls_orphans_mutex);
- set_unlock_args(0, ua, &args);
+ set_unlock_args(0, lkb->lkb_ua, &args);
error = cancel_lock(ls, lkb, &args);
if (error == -DLM_ECANCEL)
static int unlock_proc_lock(struct dlm_ls *ls, struct dlm_lkb *lkb)
{
- struct dlm_user_args *ua = (struct dlm_user_args *)lkb->lkb_astparam;
struct dlm_args args;
int error;
- set_unlock_args(DLM_LKF_FORCEUNLOCK, ua, &args);
+ set_unlock_args(DLM_LKF_FORCEUNLOCK, lkb->lkb_ua, &args);
error = unlock_lock(ls, lkb, &args);
if (error == -DLM_EUNLOCK)
void dlm_dump_rsb(struct dlm_rsb *r);
void dlm_print_lkb(struct dlm_lkb *lkb);
void dlm_receive_message_saved(struct dlm_ls *ls, struct dlm_message *ms);
-void dlm_receive_buffer(struct dlm_header *hd, int nodeid);
+void dlm_receive_buffer(union dlm_packet *p, int nodeid);
int dlm_modes_compat(int mode1, int mode2);
void dlm_put_rsb(struct dlm_rsb *r);
void dlm_hold_rsb(struct dlm_rsb *r);
}
-int dlm_lockspace_init(void)
+int __init dlm_lockspace_init(void)
{
ls_count = 0;
mutex_init(&ls_lock);
static struct kmem_cache *lkb_cache;
-int dlm_memory_init(void)
+int __init dlm_memory_init(void)
{
int ret = 0;
{
if (lkb->lkb_flags & DLM_IFL_USER) {
struct dlm_user_args *ua;
- ua = (struct dlm_user_args *)lkb->lkb_astparam;
+ ua = lkb->lkb_ua;
if (ua) {
if (ua->lksb.sb_lvbptr)
kfree(ua->lksb.sb_lvbptr);
union {
unsigned char __buf[DLM_INBUF_LEN];
/* this is to force proper alignment on some arches */
- struct dlm_header dlm;
+ union dlm_packet p;
} __tmp;
- struct dlm_header *msg = &__tmp.dlm;
+ union dlm_packet *p = &__tmp.p;
int ret = 0;
int err = 0;
uint16_t msglen;
message may wrap around the end of the buffer back to the
start, so we need to use a temp buffer and copy_from_cb. */
- copy_from_cb(msg, base, offset, sizeof(struct dlm_header),
+ copy_from_cb(p, base, offset, sizeof(struct dlm_header),
limit);
- msglen = le16_to_cpu(msg->h_length);
- lockspace = msg->h_lockspace;
+ msglen = le16_to_cpu(p->header.h_length);
+ lockspace = p->header.h_lockspace;
err = -EINVAL;
if (msglen < sizeof(struct dlm_header))
break;
+ if (p->header.h_cmd == DLM_MSG) {
+ if (msglen < sizeof(struct dlm_message))
+ break;
+ } else {
+ if (msglen < sizeof(struct dlm_rcom))
+ break;
+ }
err = -E2BIG;
if (msglen > dlm_config.ci_buffer_size) {
log_print("message size %d from %d too big, buf len %d",
in the buffer on the stack (which should work for most
ordinary messages). */
- if (msglen > DLM_INBUF_LEN && msg == &__tmp.dlm) {
- msg = kmalloc(dlm_config.ci_buffer_size, GFP_KERNEL);
- if (msg == NULL)
+ if (msglen > sizeof(__tmp) && p == &__tmp.p) {
+ p = kmalloc(dlm_config.ci_buffer_size, GFP_KERNEL);
+ if (p == NULL)
return ret;
}
- copy_from_cb(msg, base, offset, msglen, limit);
+ copy_from_cb(p, base, offset, msglen, limit);
- BUG_ON(lockspace != msg->h_lockspace);
+ BUG_ON(lockspace != p->header.h_lockspace);
ret += msglen;
offset += msglen;
offset &= (limit - 1);
len -= msglen;
- dlm_receive_buffer(msg, nodeid);
+ dlm_receive_buffer(p, nodeid);
}
- if (msg != &__tmp.dlm)
- kfree(msg);
+ if (p != &__tmp.p)
+ kfree(p);
return err ? err : ret;
}
.doit = user_cmd,
};
-int dlm_netlink_init(void)
+int __init dlm_netlink_init(void)
{
int rv;
return rv;
}
-void dlm_netlink_exit(void)
+void __exit dlm_netlink_exit(void)
{
genl_unregister_ops(&family, &dlm_nl_ops);
genl_unregister_family(&family);
static void fill_data(struct dlm_lock_data *data, struct dlm_lkb *lkb)
{
struct dlm_rsb *r = lkb->lkb_resource;
- struct dlm_user_args *ua = (struct dlm_user_args *) lkb->lkb_astparam;
memset(data, 0, sizeof(struct dlm_lock_data));
data->grmode = lkb->lkb_grmode;
data->rqmode = lkb->lkb_rqmode;
data->timestamp = lkb->lkb_timestamp;
- if (ua)
- data->xid = ua->xid;
+ if (lkb->lkb_ua)
+ data->xid = lkb->lkb_ua->xid;
if (r) {
data->lockspace_id = r->res_ls->ls_global_id;
data->resource_namelen = r->res_length;
static void make_config(struct dlm_ls *ls, struct rcom_config *rf)
{
- rf->rf_lvblen = ls->ls_lvblen;
- rf->rf_lsflags = ls->ls_exflags;
+ rf->rf_lvblen = cpu_to_le32(ls->ls_lvblen);
+ rf->rf_lsflags = cpu_to_le32(ls->ls_exflags);
}
static int check_config(struct dlm_ls *ls, struct dlm_rcom *rc, int nodeid)
{
struct rcom_config *rf = (struct rcom_config *) rc->rc_buf;
+ size_t conf_size = sizeof(struct dlm_rcom) + sizeof(struct rcom_config);
if ((rc->rc_header.h_version & 0xFFFF0000) != DLM_HEADER_MAJOR) {
log_error(ls, "version mismatch: %x nodeid %d: %x",
return -EPROTO;
}
- if (rf->rf_lvblen != ls->ls_lvblen ||
- rf->rf_lsflags != ls->ls_exflags) {
+ if (rc->rc_header.h_length < conf_size) {
+ log_error(ls, "config too short: %d nodeid %d",
+ rc->rc_header.h_length, nodeid);
+ return -EPROTO;
+ }
+
+ if (le32_to_cpu(rf->rf_lvblen) != ls->ls_lvblen ||
+ le32_to_cpu(rf->rf_lsflags) != ls->ls_exflags) {
log_error(ls, "config mismatch: %d,%x nodeid %d: %d,%x",
- ls->ls_lvblen, ls->ls_exflags,
- nodeid, rf->rf_lvblen, rf->rf_lsflags);
+ ls->ls_lvblen, ls->ls_exflags, nodeid,
+ le32_to_cpu(rf->rf_lvblen),
+ le32_to_cpu(rf->rf_lsflags));
return -EPROTO;
}
return 0;
ls->ls_recover_nodeid = nodeid;
if (nodeid == dlm_our_nodeid()) {
- rc = (struct dlm_rcom *) ls->ls_recover_buf;
+ rc = ls->ls_recover_buf;
rc->rc_result = dlm_recover_status(ls);
goto out;
}
if (error)
goto out;
- rc = (struct dlm_rcom *) ls->ls_recover_buf;
+ rc = ls->ls_recover_buf;
if (rc->rc_result == -ESRCH) {
/* we pretend the remote lockspace exists with 0 status */
{
struct dlm_rcom *rc;
struct dlm_mhandle *mh;
- int error = 0, len = sizeof(struct dlm_rcom);
+ int error = 0;
+ int max_size = dlm_config.ci_buffer_size - sizeof(struct dlm_rcom);
ls->ls_recover_nodeid = nodeid;
if (nodeid == dlm_our_nodeid()) {
dlm_copy_master_names(ls, last_name, last_len,
- ls->ls_recover_buf + len,
- dlm_config.ci_buffer_size - len, nodeid);
+ ls->ls_recover_buf->rc_buf,
+ max_size, nodeid);
goto out;
}
{
memset(rl, 0, sizeof(*rl));
- rl->rl_ownpid = lkb->lkb_ownpid;
- rl->rl_lkid = lkb->lkb_id;
- rl->rl_exflags = lkb->lkb_exflags;
- rl->rl_flags = lkb->lkb_flags;
- rl->rl_lvbseq = lkb->lkb_lvbseq;
+ rl->rl_ownpid = cpu_to_le32(lkb->lkb_ownpid);
+ rl->rl_lkid = cpu_to_le32(lkb->lkb_id);
+ rl->rl_exflags = cpu_to_le32(lkb->lkb_exflags);
+ rl->rl_flags = cpu_to_le32(lkb->lkb_flags);
+ rl->rl_lvbseq = cpu_to_le32(lkb->lkb_lvbseq);
rl->rl_rqmode = lkb->lkb_rqmode;
rl->rl_grmode = lkb->lkb_grmode;
rl->rl_status = lkb->lkb_status;
- rl->rl_wait_type = lkb->lkb_wait_type;
+ rl->rl_wait_type = cpu_to_le16(lkb->lkb_wait_type);
- if (lkb->lkb_bastaddr)
+ if (lkb->lkb_bastfn)
rl->rl_asts |= AST_BAST;
- if (lkb->lkb_astaddr)
+ if (lkb->lkb_astfn)
rl->rl_asts |= AST_COMP;
- rl->rl_namelen = r->res_length;
+ rl->rl_namelen = cpu_to_le16(r->res_length);
memcpy(rl->rl_name, r->res_name, r->res_length);
/* FIXME: might we have an lvb without DLM_LKF_VALBLK set ?
return error;
}
+/* needs at least dlm_rcom + rcom_lock */
static void receive_rcom_lock(struct dlm_ls *ls, struct dlm_rcom *rc_in)
{
struct dlm_rcom *rc;
rc->rc_result = -ESRCH;
rf = (struct rcom_config *) rc->rc_buf;
- rf->rf_lvblen = -1;
+ rf->rf_lvblen = cpu_to_le32(~0U);
dlm_rcom_out(rc);
dlm_lowcomms_commit_buffer(mh);
void dlm_receive_rcom(struct dlm_ls *ls, struct dlm_rcom *rc, int nodeid)
{
+ int lock_size = sizeof(struct dlm_rcom) + sizeof(struct rcom_lock);
+
if (dlm_recovery_stopped(ls) && (rc->rc_type != DLM_RCOM_STATUS)) {
log_debug(ls, "ignoring recovery message %x from %d",
rc->rc_type, nodeid);
break;
case DLM_RCOM_LOCK:
+ if (rc->rc_header.h_length < lock_size)
+ goto Eshort;
receive_rcom_lock(ls, rc);
break;
break;
case DLM_RCOM_LOCK_REPLY:
+ if (rc->rc_header.h_length < lock_size)
+ goto Eshort;
dlm_recover_process_copy(ls, rc);
break;
default:
log_error(ls, "receive_rcom bad type %d", rc->rc_type);
}
- out:
+out:
return;
+Eshort:
+ log_error(ls, "recovery message %x from %d is too short",
+ rc->rc_type, nodeid);
}
static int wait_status_all(struct dlm_ls *ls, uint32_t wait_status)
{
- struct dlm_rcom *rc = (struct dlm_rcom *) ls->ls_recover_buf;
+ struct dlm_rcom *rc = ls->ls_recover_buf;
struct dlm_member *memb;
int error = 0, delay;
static int wait_status_low(struct dlm_ls *ls, uint32_t wait_status)
{
- struct dlm_rcom *rc = (struct dlm_rcom *) ls->ls_recover_buf;
+ struct dlm_rcom *rc = ls->ls_recover_buf;
int error = 0, delay = 0, nodeid = ls->ls_low_nodeid;
for (;;) {
struct rq_entry {
struct list_head list;
int nodeid;
- char request[0];
+ struct dlm_message request;
};
/*
* lockspace is enabled on some while still suspended on others.
*/
-void dlm_add_requestqueue(struct dlm_ls *ls, int nodeid, struct dlm_header *hd)
+void dlm_add_requestqueue(struct dlm_ls *ls, int nodeid, struct dlm_message *ms)
{
struct rq_entry *e;
- int length = hd->h_length;
+ int length = ms->m_header.h_length - sizeof(struct dlm_message);
e = kmalloc(sizeof(struct rq_entry) + length, GFP_KERNEL);
if (!e) {
}
e->nodeid = nodeid;
- memcpy(e->request, hd, length);
+ memcpy(&e->request, ms, ms->m_header.h_length);
mutex_lock(&ls->ls_requestqueue_mutex);
list_add_tail(&e->list, &ls->ls_requestqueue);
e = list_entry(ls->ls_requestqueue.next, struct rq_entry, list);
mutex_unlock(&ls->ls_requestqueue_mutex);
- dlm_receive_message_saved(ls, (struct dlm_message *)e->request);
+ dlm_receive_message_saved(ls, &e->request);
mutex_lock(&ls->ls_requestqueue_mutex);
list_del(&e->list);
mutex_lock(&ls->ls_requestqueue_mutex);
list_for_each_entry_safe(e, safe, &ls->ls_requestqueue, list) {
- ms = (struct dlm_message *) e->request;
+ ms = &e->request;
if (purge_request(ls, ms, e->nodeid)) {
list_del(&e->list);
#ifndef __REQUESTQUEUE_DOT_H__
#define __REQUESTQUEUE_DOT_H__
-void dlm_add_requestqueue(struct dlm_ls *ls, int nodeid, struct dlm_header *hd);
+void dlm_add_requestqueue(struct dlm_ls *ls, int nodeid, struct dlm_message *ms);
int dlm_process_requestqueue(struct dlm_ls *ls);
void dlm_wait_requestqueue(struct dlm_ls *ls);
void dlm_purge_requestqueue(struct dlm_ls *ls);
static void compat_input(struct dlm_write_request *kb,
struct dlm_write_request32 *kb32,
- int max_namelen)
+ size_t count)
{
kb->version[0] = kb32->version[0];
kb->version[1] = kb32->version[1];
kb->cmd == DLM_USER_REMOVE_LOCKSPACE) {
kb->i.lspace.flags = kb32->i.lspace.flags;
kb->i.lspace.minor = kb32->i.lspace.minor;
- strcpy(kb->i.lspace.name, kb32->i.lspace.name);
+ memcpy(kb->i.lspace.name, kb32->i.lspace.name, count -
+ offsetof(struct dlm_write_request32, i.lspace.name));
} else if (kb->cmd == DLM_USER_PURGE) {
kb->i.purge.nodeid = kb32->i.purge.nodeid;
kb->i.purge.pid = kb32->i.purge.pid;
kb->i.lock.bastaddr = (void *)(long)kb32->i.lock.bastaddr;
kb->i.lock.lksb = (void *)(long)kb32->i.lock.lksb;
memcpy(kb->i.lock.lvb, kb32->i.lock.lvb, DLM_USER_LVB_LEN);
- if (kb->i.lock.namelen <= max_namelen)
- memcpy(kb->i.lock.name, kb32->i.lock.name,
- kb->i.lock.namelen);
- else
- kb->i.lock.namelen = max_namelen;
+ memcpy(kb->i.lock.name, kb32->i.lock.name, count -
+ offsetof(struct dlm_write_request32, i.lock.name));
}
}
if (lkb->lkb_flags & (DLM_IFL_ORPHAN | DLM_IFL_DEAD))
goto out;
- DLM_ASSERT(lkb->lkb_astparam, dlm_print_lkb(lkb););
- ua = (struct dlm_user_args *)lkb->lkb_astparam;
+ DLM_ASSERT(lkb->lkb_ua, dlm_print_lkb(lkb););
+ ua = lkb->lkb_ua;
proc = ua->proc;
if (type == AST_BAST && ua->bastaddr == NULL)
#endif
return -EINVAL;
- kbuf = kmalloc(count, GFP_KERNEL);
+ kbuf = kzalloc(count + 1, GFP_KERNEL);
if (!kbuf)
return -ENOMEM;
if (!kbuf->is64bit) {
struct dlm_write_request32 *k32buf;
k32buf = (struct dlm_write_request32 *)kbuf;
- kbuf = kmalloc(count + (sizeof(struct dlm_write_request) -
+ kbuf = kmalloc(count + 1 + (sizeof(struct dlm_write_request) -
sizeof(struct dlm_write_request32)), GFP_KERNEL);
if (!kbuf)
return -ENOMEM;
if (proc)
set_bit(DLM_PROC_FLAGS_COMPAT, &proc->flags);
- compat_input(kbuf, k32buf,
- count - sizeof(struct dlm_write_request32));
+ compat_input(kbuf, k32buf, count + 1);
kfree(k32buf);
}
#endif
{
struct dlm_user_proc *proc = file->private_data;
struct dlm_lkb *lkb;
- struct dlm_user_args *ua;
DECLARE_WAITQUEUE(wait, current);
int error, type=0, bmode=0, removed = 0;
}
spin_unlock(&proc->asts_spin);
- ua = (struct dlm_user_args *)lkb->lkb_astparam;
- error = copy_result_to_user(ua,
+ error = copy_result_to_user(lkb->lkb_ua,
test_bit(DLM_PROC_FLAGS_COMPAT, &proc->flags),
type, bmode, buf, count);
.minor = MISC_DYNAMIC_MINOR,
};
-int dlm_user_init(void)
+int __init dlm_user_init(void)
{
int error;
ms->m_result = from_dlm_errno(le32_to_cpu(ms->m_result));
}
-static void rcom_lock_out(struct rcom_lock *rl)
-{
- rl->rl_ownpid = cpu_to_le32(rl->rl_ownpid);
- rl->rl_lkid = cpu_to_le32(rl->rl_lkid);
- rl->rl_remid = cpu_to_le32(rl->rl_remid);
- rl->rl_parent_lkid = cpu_to_le32(rl->rl_parent_lkid);
- rl->rl_parent_remid = cpu_to_le32(rl->rl_parent_remid);
- rl->rl_exflags = cpu_to_le32(rl->rl_exflags);
- rl->rl_flags = cpu_to_le32(rl->rl_flags);
- rl->rl_lvbseq = cpu_to_le32(rl->rl_lvbseq);
- rl->rl_result = cpu_to_le32(rl->rl_result);
- rl->rl_wait_type = cpu_to_le16(rl->rl_wait_type);
- rl->rl_namelen = cpu_to_le16(rl->rl_namelen);
-}
-
-static void rcom_lock_in(struct rcom_lock *rl)
-{
- rl->rl_ownpid = le32_to_cpu(rl->rl_ownpid);
- rl->rl_lkid = le32_to_cpu(rl->rl_lkid);
- rl->rl_remid = le32_to_cpu(rl->rl_remid);
- rl->rl_parent_lkid = le32_to_cpu(rl->rl_parent_lkid);
- rl->rl_parent_remid = le32_to_cpu(rl->rl_parent_remid);
- rl->rl_exflags = le32_to_cpu(rl->rl_exflags);
- rl->rl_flags = le32_to_cpu(rl->rl_flags);
- rl->rl_lvbseq = le32_to_cpu(rl->rl_lvbseq);
- rl->rl_result = le32_to_cpu(rl->rl_result);
- rl->rl_wait_type = le16_to_cpu(rl->rl_wait_type);
- rl->rl_namelen = le16_to_cpu(rl->rl_namelen);
-}
-
-static void rcom_config_out(struct rcom_config *rf)
-{
- rf->rf_lvblen = cpu_to_le32(rf->rf_lvblen);
- rf->rf_lsflags = cpu_to_le32(rf->rf_lsflags);
-}
-
-static void rcom_config_in(struct rcom_config *rf)
-{
- rf->rf_lvblen = le32_to_cpu(rf->rf_lvblen);
- rf->rf_lsflags = le32_to_cpu(rf->rf_lsflags);
-}
-
void dlm_rcom_out(struct dlm_rcom *rc)
{
- int type = rc->rc_type;
-
header_out(&rc->rc_header);
rc->rc_type = cpu_to_le32(rc->rc_type);
rc->rc_id = cpu_to_le64(rc->rc_id);
rc->rc_seq = cpu_to_le64(rc->rc_seq);
rc->rc_seq_reply = cpu_to_le64(rc->rc_seq_reply);
-
- if ((type == DLM_RCOM_LOCK) || (type == DLM_RCOM_LOCK_REPLY))
- rcom_lock_out((struct rcom_lock *) rc->rc_buf);
-
- else if (type == DLM_RCOM_STATUS_REPLY)
- rcom_config_out((struct rcom_config *) rc->rc_buf);
}
void dlm_rcom_in(struct dlm_rcom *rc)
{
- int type;
-
header_in(&rc->rc_header);
rc->rc_type = le32_to_cpu(rc->rc_type);
rc->rc_id = le64_to_cpu(rc->rc_id);
rc->rc_seq = le64_to_cpu(rc->rc_seq);
rc->rc_seq_reply = le64_to_cpu(rc->rc_seq_reply);
-
- type = rc->rc_type;
-
- if ((type == DLM_RCOM_LOCK) || (type == DLM_RCOM_LOCK_REPLY))
- rcom_lock_in((struct rcom_lock *) rc->rc_buf);
-
- else if (type == DLM_RCOM_STATUS_REPLY)
- rcom_config_in((struct rcom_config *) rc->rc_buf);
}
-
if (error)
goto exit;
- file = nameidata_to_filp(&nd, O_RDONLY);
+ file = nameidata_to_filp(&nd, O_RDONLY|O_LARGEFILE);
error = PTR_ERR(file);
if (IS_ERR(file))
goto out;
int err = vfs_permission(&nd, MAY_EXEC);
file = ERR_PTR(err);
if (!err) {
- file = nameidata_to_filp(&nd, O_RDONLY);
+ file = nameidata_to_filp(&nd,
+ O_RDONLY|O_LARGEFILE);
if (!IS_ERR(file)) {
err = deny_write_access(file);
if (err) {
zap_other_threads(tsk);
read_unlock(&tasklist_lock);
- /*
- * Account for the thread group leader hanging around:
- */
- count = 1;
- if (!thread_group_leader(tsk)) {
- count = 2;
- /*
- * The SIGALRM timer survives the exec, but needs to point
- * at us as the new group leader now. We have a race with
- * a timer firing now getting the old leader, so we need to
- * synchronize with any firing (by calling del_timer_sync)
- * before we can safely let the old group leader die.
- */
- sig->tsk = tsk;
- spin_unlock_irq(lock);
- if (hrtimer_cancel(&sig->real_timer))
- hrtimer_restart(&sig->real_timer);
- spin_lock_irq(lock);
- }
-
+ /* Account for the thread group leader hanging around: */
+ count = thread_group_leader(tsk) ? 1 : 2;
sig->notify_count = count;
while (atomic_read(&sig->count) > count) {
__set_current_state(TASK_UNINTERRUPTIBLE);
{
int try,retval;
struct linux_binfmt *fmt;
-#ifdef __alpha__
+#if defined(__alpha__) && defined(CONFIG_ARCH_SUPPORTS_AOUT)
/* handle /sbin/loader.. */
{
struct exec * eh = (struct exec *) bprm->buf;
/* inode.c */
extern struct inode *ext2_iget (struct super_block *, unsigned long);
extern int ext2_write_inode (struct inode *, int);
-extern void ext2_put_inode (struct inode *);
extern void ext2_delete_inode (struct inode *);
extern int ext2_sync_inode (struct inode *);
extern int ext2_get_block(struct inode *, sector_t, struct buffer_head *, int);
seq_puts(seq, ",xip");
#endif
+ if (!test_opt(sb, RESERVATION))
+ seq_puts(seq, ",noreservation");
+
return 0;
}
jbd_unlock_bh_state(bitmap_bh);
spin_lock(sb_bgl_lock(sbi, block_group));
- desc->bg_free_blocks_count =
- cpu_to_le16(le16_to_cpu(desc->bg_free_blocks_count) +
- group_freed);
+ le16_add_cpu(&desc->bg_free_blocks_count, group_freed);
spin_unlock(sb_bgl_lock(sbi, block_group));
percpu_counter_add(&sbi->s_freeblocks_counter, count);
ret_block, goal_hits, goal_attempts);
spin_lock(sb_bgl_lock(sbi, group_no));
- gdp->bg_free_blocks_count =
- cpu_to_le16(le16_to_cpu(gdp->bg_free_blocks_count)-num);
+ le16_add_cpu(&gdp->bg_free_blocks_count, -num);
spin_unlock(sb_bgl_lock(sbi, group_no));
percpu_counter_sub(&sbi->s_freeblocks_counter, num);
if (gdp) {
spin_lock(sb_bgl_lock(sbi, block_group));
- gdp->bg_free_inodes_count = cpu_to_le16(
- le16_to_cpu(gdp->bg_free_inodes_count) + 1);
+ le16_add_cpu(&gdp->bg_free_inodes_count, 1);
if (is_directory)
- gdp->bg_used_dirs_count = cpu_to_le16(
- le16_to_cpu(gdp->bg_used_dirs_count) - 1);
+ le16_add_cpu(&gdp->bg_used_dirs_count, -1);
spin_unlock(sb_bgl_lock(sbi, block_group));
percpu_counter_inc(&sbi->s_freeinodes_counter);
if (is_directory)
err = ext3_journal_get_write_access(handle, bh2);
if (err) goto fail;
spin_lock(sb_bgl_lock(sbi, group));
- gdp->bg_free_inodes_count =
- cpu_to_le16(le16_to_cpu(gdp->bg_free_inodes_count) - 1);
+ le16_add_cpu(&gdp->bg_free_inodes_count, -1);
if (S_ISDIR(mode)) {
- gdp->bg_used_dirs_count =
- cpu_to_le16(le16_to_cpu(gdp->bg_used_dirs_count) + 1);
+ le16_add_cpu(&gdp->bg_used_dirs_count, 1);
}
spin_unlock(sb_bgl_lock(sbi, group));
BUFFER_TRACE(bh2, "call ext3_journal_dirty_metadata");
EXT3_SB(sb)->s_gdb_count++;
kfree(o_group_desc);
- es->s_reserved_gdt_blocks =
- cpu_to_le16(le16_to_cpu(es->s_reserved_gdt_blocks) - 1);
+ le16_add_cpu(&es->s_reserved_gdt_blocks, -1);
ext3_journal_dirty_metadata(handle, EXT3_SB(sb)->s_sbh);
return 0;
* blocks/inodes before the group is live won't actually let us
* allocate the new space yet.
*/
- es->s_blocks_count = cpu_to_le32(le32_to_cpu(es->s_blocks_count) +
- input->blocks_count);
- es->s_inodes_count = cpu_to_le32(le32_to_cpu(es->s_inodes_count) +
- EXT3_INODES_PER_GROUP(sb));
+ le32_add_cpu(&es->s_blocks_count, input->blocks_count);
+ le32_add_cpu(&es->s_inodes_count, EXT3_INODES_PER_GROUP(sb));
/*
* We need to protect s_groups_count against other CPUs seeing
/* Update the reserved block counts only once the new group is
* active. */
- es->s_r_blocks_count = cpu_to_le32(le32_to_cpu(es->s_r_blocks_count) +
- input->reserved_blocks);
+ le32_add_cpu(&es->s_r_blocks_count, input->reserved_blocks);
/* Update the free space counts */
percpu_counter_add(&sbi->s_freeblocks_counter,
#endif
if (!(__s16) le16_to_cpu(es->s_max_mnt_count))
es->s_max_mnt_count = cpu_to_le16(EXT3_DFL_MAX_MNT_COUNT);
- es->s_mnt_count=cpu_to_le16(le16_to_cpu(es->s_mnt_count) + 1);
+ le16_add_cpu(&es->s_mnt_count, 1);
es->s_mtime = cpu_to_le32(get_seconds());
ext3_update_dynamic_rev(sb);
EXT3_SET_INCOMPAT_FEATURE(sb, EXT3_FEATURE_INCOMPAT_RECOVER);
get_bh(bh);
ext3_forget(handle, 1, inode, bh, bh->b_blocknr);
} else {
- BHDR(bh)->h_refcount = cpu_to_le32(
- le32_to_cpu(BHDR(bh)->h_refcount) - 1);
+ le32_add_cpu(&BHDR(bh)->h_refcount, -1);
error = ext3_journal_dirty_metadata(handle, bh);
if (IS_SYNC(inode))
handle->h_sync = 1;
if (error)
goto cleanup_dquot;
lock_buffer(new_bh);
- BHDR(new_bh)->h_refcount = cpu_to_le32(1 +
- le32_to_cpu(BHDR(new_bh)->h_refcount));
+ le32_add_cpu(&BHDR(new_bh)->h_refcount, 1);
ea_bdebug(new_bh, "reusing; refcount now=%d",
le32_to_cpu(BHDR(new_bh)->h_refcount));
unlock_buffer(new_bh);
if (!opts->numtail)
seq_puts(m, ",nonumtail");
}
+ if (sbi->options.flush)
+ seq_puts(m, ",flush");
return 0;
}
#include <asm/siginfo.h>
#include <asm/uaccess.h>
-void fastcall set_close_on_exec(unsigned int fd, int flag)
+void set_close_on_exec(unsigned int fd, int flag)
{
struct files_struct *files = current->files;
struct fdtable *fdt;
{
pid_t pid;
read_lock(&filp->f_owner.lock);
- pid = pid_nr_ns(filp->f_owner.pid, current->nsproxy->pid_ns);
+ pid = pid_vnr(filp->f_owner.pid);
if (filp->f_owner.pid_type == PIDTYPE_PGID)
pid = -pid;
read_unlock(&filp->f_owner.lock);
}
EXPORT_SYMBOL(init_file);
-void fastcall fput(struct file *file)
+void fput(struct file *file)
{
if (atomic_dec_and_test(&file->f_count))
__fput(file);
/* __fput is called from task context when aio completion releases the last
* last use of a struct file *. Do not use otherwise.
*/
-void fastcall __fput(struct file *file)
+void __fput(struct file *file)
{
struct dentry *dentry = file->f_path.dentry;
struct vfsmount *mnt = file->f_path.mnt;
mntput(mnt);
}
-struct file fastcall *fget(unsigned int fd)
+struct file *fget(unsigned int fd)
{
struct file *file;
struct files_struct *files = current->files;
* and a flag is returned to be passed to the corresponding fput_light().
* There must not be a cloning between an fget_light/fput_light pair.
*/
-struct file fastcall *fget_light(unsigned int fd, int *fput_needed)
+struct file *fget_light(unsigned int fd, int *fput_needed)
{
struct file *file;
struct files_struct *files = current->files;
int ret;
struct writeback_control wbc = {
.nr_to_write = LONG_MAX,
- .sync_mode = WB_SYNC_ALL,
+ .sync_mode = sync ? WB_SYNC_ALL : WB_SYNC_NONE,
.range_start = 0,
.range_end = LLONG_MAX,
};
#define FUSE_SUPER_MAGIC 0x65735546
+#define FUSE_DEFAULT_BLKSIZE 512
+
struct fuse_mount_data {
int fd;
unsigned rootmode;
char *p;
memset(d, 0, sizeof(struct fuse_mount_data));
d->max_read = ~0;
- d->blksize = 512;
+ d->blksize = FUSE_DEFAULT_BLKSIZE;
while ((p = strsep(&opt, ",")) != NULL) {
int token;
seq_puts(m, ",allow_other");
if (fc->max_read != ~0)
seq_printf(m, ",max_read=%u", fc->max_read);
+ if (mnt->mnt_sb->s_bdev &&
+ mnt->mnt_sb->s_blocksize != FUSE_DEFAULT_BLKSIZE)
+ seq_printf(m, ",blksize=%lu", mnt->mnt_sb->s_blocksize);
return 0;
}
struct super_block *sb = dentry->d_sb;
const char *astr;
const u16 *dstr;
- int casefold, decompose, size, dsize, len;
+ int casefold, decompose, size, len;
unsigned long hash;
wchar_t c;
u16 c2;
astr = str->name;
len = str->len;
while (len > 0) {
+ int uninitialized_var(dsize);
size = asc2unichar(sb, astr, len, &c);
astr += size;
len -= size;
#include <linux/mm.h>
#include <linux/pagemap.h>
#include <linux/statfs.h>
+#include <linux/seq_file.h>
#include "hostfs.h"
#include "init.h"
#include "kern.h"
kfree(HOSTFS_I(inode));
}
+static int hostfs_show_options(struct seq_file *seq, struct vfsmount *vfs)
+{
+ struct inode *root = vfs->mnt_sb->s_root->d_inode;
+ const char *root_path = HOSTFS_I(root)->host_filename;
+ size_t offset = strlen(root_ino) + 1;
+
+ if (strlen(root_path) > offset)
+ seq_printf(seq, ",%s", root_path + offset);
+
+ return 0;
+}
+
static const struct super_operations hostfs_sbops = {
.alloc_inode = hostfs_alloc_inode,
.drop_inode = generic_delete_inode,
.delete_inode = hostfs_delete_inode,
.destroy_inode = hostfs_destroy_inode,
.statfs = hostfs_statfs,
+ .show_options = hostfs_show_options,
};
int hostfs_readdir(struct file *file, void *ent, filldir_t filldir)
int lowercase, conv, eas, chk, errs, chkdsk, timeshift;
int o;
struct hpfs_sb_info *sbi = hpfs_sb(s);
+ char *new_opts = kstrdup(data, GFP_KERNEL);
*flags |= MS_NOATIME;
if (!(o = parse_opts(data, &uid, &gid, &umask, &lowercase, &conv,
&eas, &chk, &errs, &chkdsk, ×hift))) {
printk("HPFS: bad mount options.\n");
- return 1;
+ goto out_err;
}
if (o == 2) {
hpfs_help();
- return 1;
+ goto out_err;
}
if (timeshift != sbi->sb_timeshift) {
printk("HPFS: timeshift can't be changed using remount.\n");
- return 1;
+ goto out_err;
}
unmark_dirty(s);
if (!(*flags & MS_RDONLY)) mark_dirty(s);
+ kfree(s->s_options);
+ s->s_options = new_opts;
+
return 0;
+
+out_err:
+ kfree(new_opts);
+ return -EINVAL;
}
/* Super operations */
.put_super = hpfs_put_super,
.statfs = hpfs_statfs,
.remount_fs = hpfs_remount_fs,
+ .show_options = generic_show_options,
};
static int hpfs_fill_super(struct super_block *s, void *options, int silent)
int o;
+ save_mount_options(s, options);
+
sbi = kzalloc(sizeof(*sbi), GFP_KERNEL);
if (!sbi)
return -ENOMEM;
.delete_inode = hugetlbfs_delete_inode,
.drop_inode = hugetlbfs_drop_inode,
.put_super = hugetlbfs_put_super,
+ .show_options = generic_show_options,
};
static int
struct hugetlbfs_config config;
struct hugetlbfs_sb_info *sbinfo;
+ save_mount_options(sb, data);
+
config.nr_blocks = -1; /* No limit on size by default */
config.nr_inodes = -1; /* No limit on number of inodes by default */
config.uid = current->fsuid;
/* we can safely put the watch as we don't reference it while
* generating the event
*/
- if (mask & IN_IGNORED || mask & IN_ONESHOT)
+ if (mask & IN_IGNORED || w->mask & IN_ONESHOT)
put_inotify_watch(w); /* final put */
/* coalescing: drop this event if it is a dupe of the previous */
.put_super = isofs_put_super,
.statfs = isofs_statfs,
.remount_fs = isofs_remount,
+ .show_options = generic_show_options,
};
char nocompress;
unsigned char check;
unsigned int blocksize;
- mode_t mode;
+ mode_t fmode;
+ mode_t dmode;
gid_t gid;
uid_t uid;
char *iocharset;
Opt_block, Opt_check_r, Opt_check_s, Opt_cruft, Opt_gid, Opt_ignore,
Opt_iocharset, Opt_map_a, Opt_map_n, Opt_map_o, Opt_mode, Opt_nojoliet,
Opt_norock, Opt_sb, Opt_session, Opt_uid, Opt_unhide, Opt_utf8, Opt_err,
- Opt_nocompress, Opt_hide, Opt_showassoc,
+ Opt_nocompress, Opt_hide, Opt_showassoc, Opt_dmode,
};
static match_table_t tokens = {
{Opt_uid, "uid=%u"},
{Opt_gid, "gid=%u"},
{Opt_mode, "mode=%u"},
+ {Opt_dmode, "dmode=%u"},
{Opt_block, "block=%u"},
{Opt_ignore, "conv=binary"},
{Opt_ignore, "conv=b"},
popt->check = 'u'; /* unset */
popt->nocompress = 0;
popt->blocksize = 1024;
- popt->mode = S_IRUGO | S_IXUGO; /*
+ popt->fmode = popt->dmode = S_IRUGO | S_IXUGO; /*
* r-x for all. The disc could
* be shared with DOS machines so
* virtually anything could be
case Opt_mode:
if (match_int(&args[0], &option))
return 0;
- popt->mode = option;
+ popt->fmode = option;
+ break;
+ case Opt_dmode:
+ if (match_int(&args[0], &option))
+ return 0;
+ popt->dmode = option;
break;
case Opt_block:
if (match_int(&args[0], &option))
int table, error = -EINVAL;
unsigned int vol_desc_start;
+ save_mount_options(s, data);
+
sbi = kzalloc(sizeof(*sbi), GFP_KERNEL);
if (!sbi)
return -ENOMEM;
* on the disk as suid, so we merely allow them to set the default
* permissions.
*/
- sbi->s_mode = opt.mode & 0777;
+ sbi->s_fmode = opt.fmode & 0777;
+ sbi->s_dmode = opt.dmode & 0777;
/*
* Read the root inode, which _may_ result in changing
ei->i_file_format = isofs_file_normal;
if (de->flags[-high_sierra] & 2) {
- inode->i_mode = S_IRUGO | S_IXUGO | S_IFDIR;
+ inode->i_mode = sbi->s_dmode | S_IFDIR;
inode->i_nlink = 1; /*
* Set to 1. We know there are 2, but
* the find utility tries to optimize
*/
} else {
/* Everybody gets to read the file. */
- inode->i_mode = sbi->s_mode;
+ inode->i_mode = sbi->s_fmode | S_IFREG;
inode->i_nlink = 1;
- inode->i_mode |= S_IFREG;
}
inode->i_uid = sbi->s_uid;
inode->i_gid = sbi->s_gid;
unsigned char s_hide;
unsigned char s_showassoc;
- mode_t s_mode;
+ mode_t s_fmode;
+ mode_t s_dmode;
gid_t s_gid;
uid_t s_uid;
struct nls_table *s_nls_iocharset; /* Native language support table */
barrier_done = 1;
}
ret = sync_dirty_buffer(bh);
+ if (barrier_done)
+ clear_buffer_ordered(bh);
/* is it possible for another commit to fail at roughly
* the same time as this one? If so, we don't want to
* trust the barrier flag in the super, but instead want
spin_unlock(&journal->j_state_lock);
/* And try again, without the barrier */
- clear_buffer_ordered(bh);
set_buffer_uptodate(bh);
set_buffer_dirty(bh);
ret = sync_dirty_buffer(bh);
/* Simple attribute files */
struct simple_attr {
- u64 (*get)(void *);
- void (*set)(void *, u64);
+ int (*get)(void *, u64 *);
+ int (*set)(void *, u64);
char get_buf[24]; /* enough to store a u64 and "\n\0" */
char set_buf[24];
void *data;
/* simple_attr_open is called by an actual attribute open file operation
* to set the attribute specific access operations. */
int simple_attr_open(struct inode *inode, struct file *file,
- u64 (*get)(void *), void (*set)(void *, u64),
+ int (*get)(void *, u64 *), int (*set)(void *, u64),
const char *fmt)
{
struct simple_attr *attr;
return nonseekable_open(inode, file);
}
-int simple_attr_close(struct inode *inode, struct file *file)
+int simple_attr_release(struct inode *inode, struct file *file)
{
kfree(file->private_data);
return 0;
if (!attr->get)
return -EACCES;
- mutex_lock(&attr->mutex);
- if (*ppos) /* continued read */
+ ret = mutex_lock_interruptible(&attr->mutex);
+ if (ret)
+ return ret;
+
+ if (*ppos) { /* continued read */
size = strlen(attr->get_buf);
- else /* first read */
+ } else { /* first read */
+ u64 val;
+ ret = attr->get(attr->data, &val);
+ if (ret)
+ goto out;
+
size = scnprintf(attr->get_buf, sizeof(attr->get_buf),
- attr->fmt,
- (unsigned long long)attr->get(attr->data));
+ attr->fmt, (unsigned long long)val);
+ }
ret = simple_read_from_buffer(buf, len, ppos, attr->get_buf, size);
+out:
mutex_unlock(&attr->mutex);
return ret;
}
ssize_t ret;
attr = file->private_data;
-
if (!attr->set)
return -EACCES;
- mutex_lock(&attr->mutex);
+ ret = mutex_lock_interruptible(&attr->mutex);
+ if (ret)
+ return ret;
+
ret = -EFAULT;
size = min(sizeof(attr->set_buf) - 1, len);
if (copy_from_user(attr->set_buf, buf, size))
EXPORT_SYMBOL(simple_transaction_read);
EXPORT_SYMBOL(simple_transaction_release);
EXPORT_SYMBOL_GPL(simple_attr_open);
-EXPORT_SYMBOL_GPL(simple_attr_close);
+EXPORT_SYMBOL_GPL(simple_attr_release);
EXPORT_SYMBOL_GPL(simple_attr_read);
EXPORT_SYMBOL_GPL(simple_attr_write);
if (cfl) {
__locks_copy_lock(fl, cfl);
if (cfl->fl_nspid)
- fl->fl_pid = pid_nr_ns(cfl->fl_nspid,
- task_active_pid_ns(current));
+ fl->fl_pid = pid_vnr(cfl->fl_nspid);
} else
fl->fl_type = F_UNLCK;
unlock_kernel();
unsigned int fl_pid;
if (fl->fl_nspid)
- fl_pid = pid_nr_ns(fl->fl_nspid, task_active_pid_ns(current));
+ fl_pid = pid_vnr(fl->fl_nspid);
else
fl_pid = fl->fl_pid;
* any extra contention...
*/
-static int fastcall link_path_walk(const char *name, struct nameidata *nd);
+static int link_path_walk(const char *name, struct nameidata *nd);
/* In order to reduce some races, while at the same time doing additional
* checking and hopefully speeding things up, we copy filenames to the
* Returns 0 and nd will have valid dentry and mnt on success.
* Returns error and drops reference to input namei data on failure.
*/
-static fastcall int __link_path_walk(const char * name, struct nameidata *nd)
+static int __link_path_walk(const char *name, struct nameidata *nd)
{
struct path next;
struct inode *inode;
* Retry the whole path once, forcing real lookup requests
* instead of relying on the dcache.
*/
-static int fastcall link_path_walk(const char *name, struct nameidata *nd)
+static int link_path_walk(const char *name, struct nameidata *nd)
{
struct nameidata save = *nd;
int result;
return result;
}
-static int fastcall path_walk(const char * name, struct nameidata *nd)
+static int path_walk(const char *name, struct nameidata *nd)
{
current->total_link_count = 0;
return link_path_walk(name, nd);
}
/* Returns 0 and nd will be valid on success; Retuns error, otherwise. */
-static int fastcall do_path_lookup(int dfd, const char *name,
+static int do_path_lookup(int dfd, const char *name,
unsigned int flags, struct nameidata *nd)
{
int retval = 0;
goto out_fail;
}
-int fastcall path_lookup(const char *name, unsigned int flags,
+int path_lookup(const char *name, unsigned int flags,
struct nameidata *nd)
{
return do_path_lookup(AT_FDCWD, name, flags, nd);
return __lookup_hash(&this, base, NULL);
}
-int fastcall __user_walk_fd(int dfd, const char __user *name, unsigned flags,
+int __user_walk_fd(int dfd, const char __user *name, unsigned flags,
struct nameidata *nd)
{
char *tmp = getname(name);
return err;
}
-int fastcall __user_walk(const char __user *name, unsigned flags, struct nameidata *nd)
+int __user_walk(const char __user *name, unsigned flags, struct nameidata *nd)
{
return __user_walk_fd(AT_FDCWD, name, flags, nd);
}
EXPORT_SYMBOL(mnt_unpin);
+static inline void mangle(struct seq_file *m, const char *s)
+{
+ seq_escape(m, s, " \t\n\\");
+}
+
+/*
+ * Simple .show_options callback for filesystems which don't want to
+ * implement more complex mount option showing.
+ *
+ * See also save_mount_options().
+ */
+int generic_show_options(struct seq_file *m, struct vfsmount *mnt)
+{
+ const char *options = mnt->mnt_sb->s_options;
+
+ if (options != NULL && options[0]) {
+ seq_putc(m, ',');
+ mangle(m, options);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(generic_show_options);
+
+/*
+ * If filesystem uses generic_show_options(), this function should be
+ * called from the fill_super() callback.
+ *
+ * The .remount_fs callback usually needs to be handled in a special
+ * way, to make sure, that previous options are not overwritten if the
+ * remount fails.
+ *
+ * Also note, that if the filesystem's .remount_fs function doesn't
+ * reset all options to their default value, but changes only newly
+ * given options, then the displayed options will not reflect reality
+ * any more.
+ */
+void save_mount_options(struct super_block *sb, char *options)
+{
+ kfree(sb->s_options);
+ sb->s_options = kstrdup(options, GFP_KERNEL);
+}
+EXPORT_SYMBOL(save_mount_options);
+
/* iterator */
static void *m_start(struct seq_file *m, loff_t *pos)
{
up_read(&namespace_sem);
}
-static inline void mangle(struct seq_file *m, const char *s)
-{
- seq_escape(m, s, " \t\n\\");
-}
-
static int show_vfsmnt(struct seq_file *m, void *v)
{
struct vfsmount *mnt = list_entry(v, struct vfsmount, mnt_list);
/*
* recursively change the type of the mountpoint.
+ * noinline this do_mount helper to save do_mount stack space.
*/
-static int do_change_type(struct nameidata *nd, int flag)
+static noinline int do_change_type(struct nameidata *nd, int flag)
{
struct vfsmount *m, *mnt = nd->mnt;
int recurse = flag & MS_REC;
/*
* do loopback mount.
+ * noinline this do_mount helper to save do_mount stack space.
*/
-static int do_loopback(struct nameidata *nd, char *old_name, int recurse)
+static noinline int do_loopback(struct nameidata *nd, char *old_name,
+ int recurse)
{
struct nameidata old_nd;
struct vfsmount *mnt = NULL;
* change filesystem flags. dir should be a physical root of filesystem.
* If you've mounted a non-root directory somewhere and want to do remount
* on it - tough luck.
+ * noinline this do_mount helper to save do_mount stack space.
*/
-static int do_remount(struct nameidata *nd, int flags, int mnt_flags,
+static noinline int do_remount(struct nameidata *nd, int flags, int mnt_flags,
void *data)
{
int err;
return 0;
}
-static int do_move_mount(struct nameidata *nd, char *old_name)
+/*
+ * noinline this do_mount helper to save do_mount stack space.
+ */
+static noinline int do_move_mount(struct nameidata *nd, char *old_name)
{
struct nameidata old_nd, parent_nd;
struct vfsmount *p;
/*
* create a new mount for userspace and request it to be added into the
* namespace's tree
+ * noinline this do_mount helper to save do_mount stack space.
*/
-static int do_new_mount(struct nameidata *nd, char *type, int flags,
+static noinline int do_new_mount(struct nameidata *nd, char *type, int flags,
int mnt_flags, char *name, void *data)
{
struct vfsmount *mnt;
#include <linux/init.h>
#include <linux/smp_lock.h>
#include <linux/vfs.h>
+#include <linux/mount.h>
+#include <linux/seq_file.h>
#include <linux/ncp_fs.h>
#include "ncplib_kernel.h"
#include "getopt.h"
+#define NCP_DEFAULT_FILE_MODE 0600
+#define NCP_DEFAULT_DIR_MODE 0700
+#define NCP_DEFAULT_TIME_OUT 10
+#define NCP_DEFAULT_RETRY_COUNT 20
+
static void ncp_delete_inode(struct inode *);
static void ncp_put_super(struct super_block *);
static int ncp_statfs(struct dentry *, struct kstatfs *);
+static int ncp_show_options(struct seq_file *, struct vfsmount *);
static struct kmem_cache * ncp_inode_cachep;
.put_super = ncp_put_super,
.statfs = ncp_statfs,
.remount_fs = ncp_remount,
+ .show_options = ncp_show_options,
};
extern struct dentry_operations ncp_root_dentry_operations;
flush_scheduled_work();
}
+static int ncp_show_options(struct seq_file *seq, struct vfsmount *mnt)
+{
+ struct ncp_server *server = NCP_SBP(mnt->mnt_sb);
+ unsigned int tmp;
+
+ if (server->m.uid != 0)
+ seq_printf(seq, ",uid=%u", server->m.uid);
+ if (server->m.gid != 0)
+ seq_printf(seq, ",gid=%u", server->m.gid);
+ if (server->m.mounted_uid != 0)
+ seq_printf(seq, ",owner=%u", server->m.mounted_uid);
+ tmp = server->m.file_mode & S_IALLUGO;
+ if (tmp != NCP_DEFAULT_FILE_MODE)
+ seq_printf(seq, ",mode=0%o", tmp);
+ tmp = server->m.dir_mode & S_IALLUGO;
+ if (tmp != NCP_DEFAULT_DIR_MODE)
+ seq_printf(seq, ",dirmode=0%o", tmp);
+ if (server->m.time_out != NCP_DEFAULT_TIME_OUT * HZ / 100) {
+ tmp = server->m.time_out * 100 / HZ;
+ seq_printf(seq, ",timeout=%u", tmp);
+ }
+ if (server->m.retry_count != NCP_DEFAULT_RETRY_COUNT)
+ seq_printf(seq, ",retry=%u", server->m.retry_count);
+ if (server->m.flags != 0)
+ seq_printf(seq, ",flags=%lu", server->m.flags);
+ if (server->m.wdog_pid != NULL)
+ seq_printf(seq, ",wdogpid=%u", pid_vnr(server->m.wdog_pid));
+
+ return 0;
+}
+
static const struct ncp_option ncp_opts[] = {
{ "uid", OPT_INT, 'u' },
{ "gid", OPT_INT, 'g' },
data->mounted_uid = 0;
data->wdog_pid = NULL;
data->ncp_fd = ~0;
- data->time_out = 10;
- data->retry_count = 20;
+ data->time_out = NCP_DEFAULT_TIME_OUT;
+ data->retry_count = NCP_DEFAULT_RETRY_COUNT;
data->uid = 0;
data->gid = 0;
- data->file_mode = 0600;
- data->dir_mode = 0700;
+ data->file_mode = NCP_DEFAULT_FILE_MODE;
+ data->dir_mode = NCP_DEFAULT_DIR_MODE;
data->info_fd = -1;
data->mounted_vol[0] = 0;
.name = "ncpfs",
.get_sb = ncp_get_sb,
.kill_sb = kill_anon_super,
+ .fs_flags = FS_BINARY_MOUNTDATA,
};
static int __init init_ncp_fs(void)
+++ /dev/null
-/* -*- mode: c; c-basic-offset: 8; -*-
- * vim: noexpandtab sw=8 ts=8 sts=0:
- *
- * Copyright (C) 2005 Oracle. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this program; if not, write to the
- * Free Software Foundation, Inc., 59 Temple Place - Suite 330,
- * Boston, MA 021110-1307, USA.
- */
-
-#ifndef OCFS2_CLUSTER_ENDIAN_H
-#define OCFS2_CLUSTER_ENDIAN_H
-
-static inline void be32_add_cpu(__be32 *var, u32 val)
-{
- *var = cpu_to_be32(be32_to_cpu(*var) + val);
-}
-
-#endif /* OCFS2_CLUSTER_ENDIAN_H */
#include <linux/sysctl.h>
#include <linux/configfs.h>
-#include "endian.h"
#include "tcp.h"
#include "nodemanager.h"
#include "heartbeat.h"
#include "cluster/heartbeat.h"
#include "cluster/nodemanager.h"
#include "cluster/tcp.h"
-#include "cluster/endian.h"
#include "dlmapi.h"
#include "dlmcommon.h"
+++ /dev/null
-/* -*- mode: c; c-basic-offset: 8; -*-
- * vim: noexpandtab sw=8 ts=8 sts=0:
- *
- * Copyright (C) 2005 Oracle. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this program; if not, write to the
- * Free Software Foundation, Inc., 59 Temple Place - Suite 330,
- * Boston, MA 021110-1307, USA.
- */
-
-#ifndef OCFS2_ENDIAN_H
-#define OCFS2_ENDIAN_H
-
-static inline void le16_add_cpu(__le16 *var, u16 val)
-{
- *var = cpu_to_le16(le16_to_cpu(*var) + val);
-}
-
-static inline void le32_add_cpu(__le32 *var, u32 val)
-{
- *var = cpu_to_le32(le32_to_cpu(*var) + val);
-}
-
-static inline void le64_add_cpu(__le64 *var, u64 val)
-{
- *var = cpu_to_le64(le64_to_cpu(*var) + val);
-}
-
-static inline void be32_add_cpu(__be32 *var, u32 val)
-{
- *var = cpu_to_be32(be32_to_cpu(*var) + val);
-}
-
-#endif /* OCFS2_ENDIAN_H */
#include "dlm/dlmapi.h"
#include "ocfs2_fs.h"
-#include "endian.h"
#include "ocfs2_lockid.h"
/* Most user visible OCFS2 inodes will have very few pieces of
files->next_fd = fd;
}
-void fastcall put_unused_fd(unsigned int fd)
+void put_unused_fd(unsigned int fd)
{
struct files_struct *files = current->files;
spin_lock(&files->file_lock);
* will follow.
*/
-void fastcall fd_install(unsigned int fd, struct file * file)
+void fd_install(unsigned int fd, struct file *file)
{
struct files_struct *files = current->files;
struct fdtable *fdt;
prevent_tail_call(ret);
return ret;
}
-EXPORT_UNUSED_SYMBOL_GPL(sys_open); /* To be deleted for 2.6.25 */
asmlinkage long sys_openat(int dfd, const char __user *filename, int flags,
int mode)
#include <linux/fs.h>
#include <linux/kmod.h>
#include <linux/ctype.h>
+#include <linux/genhd.h>
#include "check.h"
{
struct hd_struct *p = dev_to_part(dev);
- return sprintf(buf, "%8u %8llu %8u %8llu\n",
- p->ios[0], (unsigned long long)p->sectors[0],
- p->ios[1], (unsigned long long)p->sectors[1]);
+ preempt_disable();
+ part_round_stats(p);
+ preempt_enable();
+ return sprintf(buf,
+ "%8lu %8lu %8llu %8u "
+ "%8lu %8lu %8llu %8u "
+ "%8u %8u %8u"
+ "\n",
+ part_stat_read(p, ios[READ]),
+ part_stat_read(p, merges[READ]),
+ (unsigned long long)part_stat_read(p, sectors[READ]),
+ jiffies_to_msecs(part_stat_read(p, ticks[READ])),
+ part_stat_read(p, ios[WRITE]),
+ part_stat_read(p, merges[WRITE]),
+ (unsigned long long)part_stat_read(p, sectors[WRITE]),
+ jiffies_to_msecs(part_stat_read(p, ticks[WRITE])),
+ p->in_flight,
+ jiffies_to_msecs(part_stat_read(p, io_ticks)),
+ jiffies_to_msecs(part_stat_read(p, time_in_queue)));
}
#ifdef CONFIG_FAIL_MAKE_REQUEST
static void part_release(struct device *dev)
{
struct hd_struct *p = dev_to_part(dev);
+ free_part_stats(p);
kfree(p);
}
disk->part[part-1] = NULL;
p->start_sect = 0;
p->nr_sects = 0;
- p->ios[0] = p->ios[1] = 0;
- p->sectors[0] = p->sectors[1] = 0;
+ part_stat_set_all(p, 0);
kobject_put(p->holder_dir);
device_del(&p->dev);
put_device(&p->dev);
if (!p)
return;
+ if (!init_part_stats(p)) {
+ kfree(p);
+ return;
+ }
p->start_sect = start;
p->nr_sects = len;
p->partno = part;
return -EBADF;
}
-static int
-pipe_ioctl(struct inode *pino, struct file *filp,
- unsigned int cmd, unsigned long arg)
+static long pipe_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
{
struct inode *inode = filp->f_path.dentry->d_inode;
struct pipe_inode_info *pipe;
.aio_read = pipe_read,
.write = bad_pipe_w,
.poll = pipe_poll,
- .ioctl = pipe_ioctl,
+ .unlocked_ioctl = pipe_ioctl,
.open = pipe_read_open,
.release = pipe_read_release,
.fasync = pipe_read_fasync,
.write = do_sync_write,
.aio_write = pipe_write,
.poll = pipe_poll,
- .ioctl = pipe_ioctl,
+ .unlocked_ioctl = pipe_ioctl,
.open = pipe_write_open,
.release = pipe_write_release,
.fasync = pipe_write_fasync,
.write = do_sync_write,
.aio_write = pipe_write,
.poll = pipe_poll,
- .ioctl = pipe_ioctl,
+ .unlocked_ioctl = pipe_ioctl,
.open = pipe_rdwr_open,
.release = pipe_rdwr_release,
.fasync = pipe_rdwr_fasync,
.aio_read = pipe_read,
.write = bad_pipe_w,
.poll = pipe_poll,
- .ioctl = pipe_ioctl,
+ .unlocked_ioctl = pipe_ioctl,
.open = pipe_read_open,
.release = pipe_read_release,
.fasync = pipe_read_fasync,
.write = do_sync_write,
.aio_write = pipe_write,
.poll = pipe_poll,
- .ioctl = pipe_ioctl,
+ .unlocked_ioctl = pipe_ioctl,
.open = pipe_write_open,
.release = pipe_write_release,
.fasync = pipe_write_fasync,
.write = do_sync_write,
.aio_write = pipe_write,
.poll = pipe_poll,
- .ioctl = pipe_ioctl,
+ .unlocked_ioctl = pipe_ioctl,
.open = pipe_rdwr_open,
.release = pipe_rdwr_release,
.fasync = pipe_rdwr_fasync,
#include <linux/cpuset.h>
#include <linux/rcupdate.h>
#include <linux/delayacct.h>
+#include <linux/seq_file.h>
#include <linux/pid_namespace.h>
#include <asm/pgtable.h>
do { memcpy(buffer, string, strlen(string)); \
buffer += strlen(string); } while (0)
-static inline char *task_name(struct task_struct *p, char *buf)
+static inline void task_name(struct seq_file *m, struct task_struct *p)
{
int i;
+ char *buf, *end;
char *name;
char tcomm[sizeof(p->comm)];
get_task_comm(tcomm, p);
- ADDBUF(buf, "Name:\t");
+ seq_printf(m, "Name:\t");
+ end = m->buf + m->size;
+ buf = m->buf + m->count;
name = tcomm;
i = sizeof(tcomm);
- do {
+ while (i && (buf < end)) {
unsigned char c = *name;
name++;
i--;
if (!c)
break;
if (c == '\\') {
- buf[1] = c;
- buf += 2;
+ buf++;
+ if (buf < end)
+ *buf++ = c;
continue;
}
if (c == '\n') {
- buf[0] = '\\';
- buf[1] = 'n';
- buf += 2;
+ *buf++ = '\\';
+ if (buf < end)
+ *buf++ = 'n';
continue;
}
buf++;
- } while (i);
- *buf = '\n';
- return buf+1;
+ }
+ m->count = buf - m->buf;
+ seq_printf(m, "\n");
}
/*
return *p;
}
-static inline char *task_state(struct task_struct *p, char *buffer)
+static inline void task_state(struct seq_file *m, struct pid_namespace *ns,
+ struct pid *pid, struct task_struct *p)
{
struct group_info *group_info;
int g;
struct fdtable *fdt = NULL;
- struct pid_namespace *ns;
pid_t ppid, tpid;
- ns = current->nsproxy->pid_ns;
rcu_read_lock();
ppid = pid_alive(p) ?
task_tgid_nr_ns(rcu_dereference(p->real_parent), ns) : 0;
tpid = pid_alive(p) && p->ptrace ?
task_pid_nr_ns(rcu_dereference(p->parent), ns) : 0;
- buffer += sprintf(buffer,
+ seq_printf(m,
"State:\t%s\n"
"Tgid:\t%d\n"
"Pid:\t%d\n"
"Gid:\t%d\t%d\t%d\t%d\n",
get_task_state(p),
task_tgid_nr_ns(p, ns),
- task_pid_nr_ns(p, ns),
+ pid_nr_ns(pid, ns),
ppid, tpid,
p->uid, p->euid, p->suid, p->fsuid,
p->gid, p->egid, p->sgid, p->fsgid);
task_lock(p);
if (p->files)
fdt = files_fdtable(p->files);
- buffer += sprintf(buffer,
+ seq_printf(m,
"FDSize:\t%d\n"
"Groups:\t",
fdt ? fdt->max_fds : 0);
task_unlock(p);
for (g = 0; g < min(group_info->ngroups, NGROUPS_SMALL); g++)
- buffer += sprintf(buffer, "%d ", GROUP_AT(group_info, g));
+ seq_printf(m, "%d ", GROUP_AT(group_info, g));
put_group_info(group_info);
- buffer += sprintf(buffer, "\n");
- return buffer;
+ seq_printf(m, "\n");
}
-static char *render_sigset_t(const char *header, sigset_t *set, char *buffer)
+static void render_sigset_t(struct seq_file *m, const char *header,
+ sigset_t *set)
{
- int i, len;
+ int i;
- len = strlen(header);
- memcpy(buffer, header, len);
- buffer += len;
+ seq_printf(m, "%s", header);
i = _NSIG;
do {
if (sigismember(set, i+2)) x |= 2;
if (sigismember(set, i+3)) x |= 4;
if (sigismember(set, i+4)) x |= 8;
- *buffer++ = (x < 10 ? '0' : 'a' - 10) + x;
+ seq_printf(m, "%x", x);
} while (i >= 4);
- *buffer++ = '\n';
- *buffer = 0;
- return buffer;
+ seq_printf(m, "\n");
}
static void collect_sigign_sigcatch(struct task_struct *p, sigset_t *ign,
}
}
-static inline char *task_sig(struct task_struct *p, char *buffer)
+static inline void task_sig(struct seq_file *m, struct task_struct *p)
{
unsigned long flags;
sigset_t pending, shpending, blocked, ignored, caught;
}
rcu_read_unlock();
- buffer += sprintf(buffer, "Threads:\t%d\n", num_threads);
- buffer += sprintf(buffer, "SigQ:\t%lu/%lu\n", qsize, qlim);
+ seq_printf(m, "Threads:\t%d\n", num_threads);
+ seq_printf(m, "SigQ:\t%lu/%lu\n", qsize, qlim);
/* render them all */
- buffer = render_sigset_t("SigPnd:\t", &pending, buffer);
- buffer = render_sigset_t("ShdPnd:\t", &shpending, buffer);
- buffer = render_sigset_t("SigBlk:\t", &blocked, buffer);
- buffer = render_sigset_t("SigIgn:\t", &ignored, buffer);
- buffer = render_sigset_t("SigCgt:\t", &caught, buffer);
-
- return buffer;
+ render_sigset_t(m, "SigPnd:\t", &pending);
+ render_sigset_t(m, "ShdPnd:\t", &shpending);
+ render_sigset_t(m, "SigBlk:\t", &blocked);
+ render_sigset_t(m, "SigIgn:\t", &ignored);
+ render_sigset_t(m, "SigCgt:\t", &caught);
}
-static char *render_cap_t(const char *header, kernel_cap_t *a, char *buffer)
+static void render_cap_t(struct seq_file *m, const char *header,
+ kernel_cap_t *a)
{
unsigned __capi;
- buffer += sprintf(buffer, "%s", header);
+ seq_printf(m, "%s", header);
CAP_FOR_EACH_U32(__capi) {
- buffer += sprintf(buffer, "%08x",
- a->cap[(_LINUX_CAPABILITY_U32S-1) - __capi]);
+ seq_printf(m, "%08x",
+ a->cap[(_LINUX_CAPABILITY_U32S-1) - __capi]);
}
- return buffer + sprintf(buffer, "\n");
+ seq_printf(m, "\n");
}
-static inline char *task_cap(struct task_struct *p, char *buffer)
+static inline void task_cap(struct seq_file *m, struct task_struct *p)
{
- buffer = render_cap_t("CapInh:\t", &p->cap_inheritable, buffer);
- buffer = render_cap_t("CapPrm:\t", &p->cap_permitted, buffer);
- return render_cap_t("CapEff:\t", &p->cap_effective, buffer);
+ render_cap_t(m, "CapInh:\t", &p->cap_inheritable);
+ render_cap_t(m, "CapPrm:\t", &p->cap_permitted);
+ render_cap_t(m, "CapEff:\t", &p->cap_effective);
}
-static inline char *task_context_switch_counts(struct task_struct *p,
- char *buffer)
+static inline void task_context_switch_counts(struct seq_file *m,
+ struct task_struct *p)
{
- return buffer + sprintf(buffer, "voluntary_ctxt_switches:\t%lu\n"
- "nonvoluntary_ctxt_switches:\t%lu\n",
- p->nvcsw,
- p->nivcsw);
+ seq_printf(m, "voluntary_ctxt_switches:\t%lu\n"
+ "nonvoluntary_ctxt_switches:\t%lu\n",
+ p->nvcsw,
+ p->nivcsw);
}
-int proc_pid_status(struct task_struct *task, char *buffer)
+int proc_pid_status(struct seq_file *m, struct pid_namespace *ns,
+ struct pid *pid, struct task_struct *task)
{
- char *orig = buffer;
struct mm_struct *mm = get_task_mm(task);
- buffer = task_name(task, buffer);
- buffer = task_state(task, buffer);
+ task_name(m, task);
+ task_state(m, ns, pid, task);
if (mm) {
- buffer = task_mem(mm, buffer);
+ task_mem(m, mm);
mmput(mm);
}
- buffer = task_sig(task, buffer);
- buffer = task_cap(task, buffer);
- buffer = cpuset_task_status_allowed(task, buffer);
+ task_sig(m, task);
+ task_cap(m, task);
+ cpuset_task_status_allowed(m, task);
#if defined(CONFIG_S390)
- buffer = task_show_regs(task, buffer);
+ task_show_regs(m, task);
#endif
- buffer = task_context_switch_counts(task, buffer);
- return buffer - orig;
+ task_context_switch_counts(m, task);
+ return 0;
}
/*
return p->gtime;
}
-static int do_task_stat(struct task_struct *task, char *buffer, int whole)
+static int do_task_stat(struct seq_file *m, struct pid_namespace *ns,
+ struct pid *pid, struct task_struct *task, int whole)
{
unsigned long vsize, eip, esp, wchan = ~0UL;
long priority, nice;
int tty_pgrp = -1, tty_nr = 0;
sigset_t sigign, sigcatch;
char state;
- int res;
pid_t ppid = 0, pgid = -1, sid = -1;
int num_threads = 0;
struct mm_struct *mm;
unsigned long rsslim = 0;
char tcomm[sizeof(task->comm)];
unsigned long flags;
- struct pid_namespace *ns;
-
- ns = current->nsproxy->pid_ns;
state = *get_task_state(task);
vsize = eip = esp = 0;
/* convert nsec -> ticks */
start_time = nsec_to_clock_t(start_time);
- res = sprintf(buffer, "%d (%s) %c %d %d %d %d %d %u %lu \
+ seq_printf(m, "%d (%s) %c %d %d %d %d %d %u %lu \
%lu %lu %lu %lu %lu %ld %ld %ld %ld %d 0 %llu %lu %ld %lu %lu %lu %lu %lu \
%lu %lu %lu %lu %lu %lu %lu %lu %d %d %u %u %llu %lu %ld\n",
- task_pid_nr_ns(task, ns),
+ pid_nr_ns(pid, ns),
tcomm,
state,
ppid,
cputime_to_clock_t(cgtime));
if (mm)
mmput(mm);
- return res;
+ return 0;
}
-int proc_tid_stat(struct task_struct *task, char *buffer)
+int proc_tid_stat(struct seq_file *m, struct pid_namespace *ns,
+ struct pid *pid, struct task_struct *task)
{
- return do_task_stat(task, buffer, 0);
+ return do_task_stat(m, ns, pid, task, 0);
}
-int proc_tgid_stat(struct task_struct *task, char *buffer)
+int proc_tgid_stat(struct seq_file *m, struct pid_namespace *ns,
+ struct pid *pid, struct task_struct *task)
{
- return do_task_stat(task, buffer, 1);
+ return do_task_stat(m, ns, pid, task, 1);
}
-int proc_pid_statm(struct task_struct *task, char *buffer)
+int proc_pid_statm(struct seq_file *m, struct pid_namespace *ns,
+ struct pid *pid, struct task_struct *task)
{
int size = 0, resident = 0, shared = 0, text = 0, lib = 0, data = 0;
struct mm_struct *mm = get_task_mm(task);
size = task_statm(mm, &shared, &text, &data, &resident);
mmput(mm);
}
+ seq_printf(m, "%d %d %d %d %d %d %d\n",
+ size, resident, shared, text, lib, data, 0);
- return sprintf(buffer, "%d %d %d %d %d %d %d\n",
- size, resident, shared, text, lib, data, 0);
+ return 0;
}
NOD(NAME, (S_IFREG|(MODE)), \
NULL, &proc_info_file_operations, \
{ .proc_read = &proc_##OTYPE } )
+#define ONE(NAME, MODE, OTYPE) \
+ NOD(NAME, (S_IFREG|(MODE)), \
+ NULL, &proc_single_file_operations, \
+ { .proc_show = &proc_##OTYPE } )
int maps_protect;
EXPORT_SYMBOL(maps_protect);
.setattr = proc_setattr,
};
-extern struct seq_operations mounts_op;
+extern const struct seq_operations mounts_op;
struct proc_mounts {
struct seq_file m;
int event;
.poll = mounts_poll,
};
-extern struct seq_operations mountstats_op;
+extern const struct seq_operations mountstats_op;
static int mountstats_open(struct inode *inode, struct file *file)
{
int ret = seq_open(file, &mountstats_op);
.read = proc_info_read,
};
+static int proc_single_show(struct seq_file *m, void *v)
+{
+ struct inode *inode = m->private;
+ struct pid_namespace *ns;
+ struct pid *pid;
+ struct task_struct *task;
+ int ret;
+
+ ns = inode->i_sb->s_fs_info;
+ pid = proc_pid(inode);
+ task = get_pid_task(pid, PIDTYPE_PID);
+ if (!task)
+ return -ESRCH;
+
+ ret = PROC_I(inode)->op.proc_show(m, ns, pid, task);
+
+ put_task_struct(task);
+ return ret;
+}
+
+static int proc_single_open(struct inode *inode, struct file *filp)
+{
+ int ret;
+ ret = single_open(filp, proc_single_show, NULL);
+ if (!ret) {
+ struct seq_file *m = filp->private_data;
+
+ m->private = inode;
+ }
+ return ret;
+}
+
+static const struct file_operations proc_single_file_operations = {
+ .open = proc_single_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
static int mem_open(struct inode* inode, struct file* file)
{
file->private_data = (void*)((long)current->self_exec_id);
static int proc_self_readlink(struct dentry *dentry, char __user *buffer,
int buflen)
{
+ struct pid_namespace *ns = dentry->d_sb->s_fs_info;
+ pid_t tgid = task_tgid_nr_ns(current, ns);
char tmp[PROC_NUMBUF];
- sprintf(tmp, "%d", task_tgid_vnr(current));
+ if (!tgid)
+ return -ENOENT;
+ sprintf(tmp, "%d", tgid);
return vfs_readlink(dentry,buffer,buflen,tmp);
}
static void *proc_self_follow_link(struct dentry *dentry, struct nameidata *nd)
{
+ struct pid_namespace *ns = dentry->d_sb->s_fs_info;
+ pid_t tgid = task_tgid_nr_ns(current, ns);
char tmp[PROC_NUMBUF];
- sprintf(tmp, "%d", task_tgid_vnr(current));
+ if (!tgid)
+ return ERR_PTR(-ENOENT);
+ sprintf(tmp, "%d", task_tgid_nr_ns(current, ns));
return ERR_PTR(vfs_follow_link(nd,tmp));
}
DIR("fdinfo", S_IRUSR|S_IXUSR, fdinfo),
REG("environ", S_IRUSR, environ),
INF("auxv", S_IRUSR, pid_auxv),
- INF("status", S_IRUGO, pid_status),
+ ONE("status", S_IRUGO, pid_status),
INF("limits", S_IRUSR, pid_limits),
#ifdef CONFIG_SCHED_DEBUG
REG("sched", S_IRUGO|S_IWUSR, pid_sched),
#endif
INF("cmdline", S_IRUGO, pid_cmdline),
- INF("stat", S_IRUGO, tgid_stat),
- INF("statm", S_IRUGO, pid_statm),
+ ONE("stat", S_IRUGO, tgid_stat),
+ ONE("statm", S_IRUGO, pid_statm),
REG("maps", S_IRUGO, maps),
#ifdef CONFIG_NUMA
REG("numa_maps", S_IRUGO, numa_maps),
DIR("fdinfo", S_IRUSR|S_IXUSR, fdinfo),
REG("environ", S_IRUSR, environ),
INF("auxv", S_IRUSR, pid_auxv),
- INF("status", S_IRUGO, pid_status),
+ ONE("status", S_IRUGO, pid_status),
INF("limits", S_IRUSR, pid_limits),
#ifdef CONFIG_SCHED_DEBUG
REG("sched", S_IRUGO|S_IWUSR, pid_sched),
#endif
INF("cmdline", S_IRUGO, pid_cmdline),
- INF("stat", S_IRUGO, tid_stat),
- INF("statm", S_IRUGO, pid_statm),
+ ONE("stat", S_IRUGO, tid_stat),
+ ONE("statm", S_IRUGO, pid_statm),
REG("maps", S_IRUGO, maps),
#ifdef CONFIG_NUMA
REG("numa_maps", S_IRUGO, numa_maps),
#include "internal.h"
-static ssize_t proc_file_read(struct file *file, char __user *buf,
- size_t nbytes, loff_t *ppos);
-static ssize_t proc_file_write(struct file *file, const char __user *buffer,
- size_t count, loff_t *ppos);
-static loff_t proc_file_lseek(struct file *, loff_t, int);
-
DEFINE_SPINLOCK(proc_subdir_lock);
static int proc_match(int len, const char *name, struct proc_dir_entry *de)
return !memcmp(name, de->name, len);
}
-static const struct file_operations proc_file_operations = {
- .llseek = proc_file_lseek,
- .read = proc_file_read,
- .write = proc_file_write,
-};
-
/* buffer size is one page but our output routines use some slack for overruns */
#define PROC_BLOCK_SIZE (PAGE_SIZE - 1024)
return retval;
}
+static const struct file_operations proc_file_operations = {
+ .llseek = proc_file_lseek,
+ .read = proc_file_read,
+ .write = proc_file_write,
+};
+
static int proc_notify_change(struct dentry *dentry, struct iattr *iattr)
{
struct inode *inode = dentry->d_inode;
spin_unlock(&proc_subdir_lock);
error = -EINVAL;
inode = proc_get_inode(dir->i_sb, ino, de);
- spin_lock(&proc_subdir_lock);
- break;
+ goto out_unlock;
}
}
}
spin_unlock(&proc_subdir_lock);
+out_unlock:
unlock_kernel();
if (inode) {
static int proc_register(struct proc_dir_entry * dir, struct proc_dir_entry * dp)
{
unsigned int i;
+ struct proc_dir_entry *tmp;
i = get_inode_number();
if (i == 0)
}
spin_lock(&proc_subdir_lock);
+
+ for (tmp = dir->subdir; tmp; tmp = tmp->next)
+ if (strcmp(tmp->name, dp->name) == 0) {
+ printk(KERN_WARNING "proc_dir_entry '%s' already "
+ "registered\n", dp->name);
+ dump_stack();
+ break;
+ }
+
dp->next = dir->subdir;
dp->parent = dir;
dir->subdir = dp;
return 0;
}
-static struct proc_dir_entry *proc_create(struct proc_dir_entry **parent,
+static struct proc_dir_entry *__proc_create(struct proc_dir_entry **parent,
const char *name,
mode_t mode,
nlink_t nlink)
{
struct proc_dir_entry *ent;
- ent = proc_create(&parent,name,
+ ent = __proc_create(&parent, name,
(S_IFLNK | S_IRUGO | S_IWUGO | S_IXUGO),1);
if (ent) {
{
struct proc_dir_entry *ent;
- ent = proc_create(&parent, name, S_IFDIR | mode, 2);
+ ent = __proc_create(&parent, name, S_IFDIR | mode, 2);
if (ent) {
if (proc_register(parent, ent) < 0) {
kfree(ent);
nlink = 1;
}
- ent = proc_create(&parent,name,mode,nlink);
+ ent = __proc_create(&parent, name, mode, nlink);
if (ent) {
if (proc_register(parent, ent) < 0) {
kfree(ent);
return ent;
}
+struct proc_dir_entry *proc_create(const char *name, mode_t mode,
+ struct proc_dir_entry *parent,
+ const struct file_operations *proc_fops)
+{
+ struct proc_dir_entry *pde;
+ nlink_t nlink;
+
+ if (S_ISDIR(mode)) {
+ if ((mode & S_IALLUGO) == 0)
+ mode |= S_IRUGO | S_IXUGO;
+ nlink = 2;
+ } else {
+ if ((mode & S_IFMT) == 0)
+ mode |= S_IFREG;
+ if ((mode & S_IALLUGO) == 0)
+ mode |= S_IRUGO;
+ nlink = 1;
+ }
+
+ pde = __proc_create(&parent, name, mode, nlink);
+ if (!pde)
+ goto out;
+ pde->proc_fops = proc_fops;
+ if (proc_register(parent, pde) < 0)
+ goto out_free;
+ return pde;
+out_free:
+ kfree(pde);
+out:
+ return NULL;
+}
+
void free_proc_entry(struct proc_dir_entry *de)
{
unsigned int ino = de->low_ino;
release_inode_number(ino);
- if (S_ISLNK(de->mode) && de->data)
+ if (S_ISLNK(de->mode))
kfree(de->data);
kfree(de);
}
de_put(&proc_root);
return -ENOMEM;
}
-MODULE_LICENSE("GPL");
extern int maps_protect;
-extern void create_seq_entry(char *name, mode_t mode, const struct file_operations *f);
+extern void create_seq_entry(char *name, mode_t mode,
+ const struct file_operations *f);
extern int proc_exe_link(struct inode *, struct dentry **, struct vfsmount **);
-extern int proc_tid_stat(struct task_struct *, char *);
-extern int proc_tgid_stat(struct task_struct *, char *);
-extern int proc_pid_status(struct task_struct *, char *);
-extern int proc_pid_statm(struct task_struct *, char *);
+extern int proc_tid_stat(struct seq_file *m, struct pid_namespace *ns,
+ struct pid *pid, struct task_struct *task);
+extern int proc_tgid_stat(struct seq_file *m, struct pid_namespace *ns,
+ struct pid *pid, struct task_struct *task);
+extern int proc_pid_status(struct seq_file *m, struct pid_namespace *ns,
+ struct pid *pid, struct task_struct *task);
+extern int proc_pid_statm(struct seq_file *m, struct pid_namespace *ns,
+ struct pid *pid, struct task_struct *task);
extern loff_t mem_lseek(struct file *file, loff_t offset, int orig);
extern const struct file_operations proc_maps_operations;
#include <linux/mm.h>
#include <linux/proc_fs.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/capability.h>
#include <linux/elf.h>
#include <linux/elfcore.h>
return rb_next((struct rb_node *) v);
}
-static struct seq_operations proc_nommu_vma_list_seqop = {
+static const struct seq_operations proc_nommu_vma_list_seqop = {
.start = nommu_vma_list_start,
.next = nommu_vma_list_next,
.stop = nommu_vma_list_stop,
#undef K
}
-extern struct seq_operations fragmentation_op;
+extern const struct seq_operations fragmentation_op;
static int fragmentation_open(struct inode *inode, struct file *file)
{
(void)inode;
.release = seq_release,
};
-extern struct seq_operations pagetypeinfo_op;
+extern const struct seq_operations pagetypeinfo_op;
static int pagetypeinfo_open(struct inode *inode, struct file *file)
{
return seq_open(file, &pagetypeinfo_op);
.release = seq_release,
};
-extern struct seq_operations zoneinfo_op;
+extern const struct seq_operations zoneinfo_op;
static int zoneinfo_open(struct inode *inode, struct file *file)
{
return seq_open(file, &zoneinfo_op);
return proc_calc_metrics(page, start, off, count, eof, len);
}
-extern struct seq_operations cpuinfo_op;
+extern const struct seq_operations cpuinfo_op;
static int cpuinfo_open(struct inode *inode, struct file *file)
{
return seq_open(file, &cpuinfo_op);
/* Nothing to do */
}
-static struct seq_operations devinfo_ops = {
+static const struct seq_operations devinfo_ops = {
.start = devinfo_start,
.next = devinfo_next,
.stop = devinfo_stop,
.release = seq_release,
};
-extern struct seq_operations vmstat_op;
+extern const struct seq_operations vmstat_op;
static int vmstat_open(struct inode *inode, struct file *file)
{
return seq_open(file, &vmstat_op);
#endif
#ifdef CONFIG_BLOCK
-extern struct seq_operations partitions_op;
+extern const struct seq_operations partitions_op;
static int partitions_open(struct inode *inode, struct file *file)
{
return seq_open(file, &partitions_op);
.release = seq_release,
};
-extern struct seq_operations diskstats_op;
+extern const struct seq_operations diskstats_op;
static int diskstats_open(struct inode *inode, struct file *file)
{
return seq_open(file, &diskstats_op);
#endif
#ifdef CONFIG_MODULES
-extern struct seq_operations modules_op;
+extern const struct seq_operations modules_op;
static int modules_open(struct inode *inode, struct file *file)
{
return seq_open(file, &modules_op);
};
#ifdef CONFIG_DEBUG_SLAB_LEAK
-extern struct seq_operations slabstats_op;
+extern const struct seq_operations slabstats_op;
static int slabstats_open(struct inode *inode, struct file *file)
{
unsigned long *n = kzalloc(PAGE_SIZE, GFP_KERNEL);
}
-static struct seq_operations int_seq_ops = {
+static const struct seq_operations int_seq_ops = {
.start = int_seq_start,
.next = int_seq_next,
.stop = int_seq_stop,
struct proc_dir_entry *proc_net_fops_create(struct net *net,
const char *name, mode_t mode, const struct file_operations *fops)
{
- struct proc_dir_entry *res;
-
- res = create_proc_entry(name, mode, net->proc_net);
- if (res)
- res->proc_fops = fops;
- return res;
+ return proc_create(name, mode, net->proc_net, fops);
}
EXPORT_SYMBOL_GPL(proc_net_fops_create);
static struct dentry_operations proc_sys_dentry_operations;
static const struct file_operations proc_sys_file_operations;
-static struct inode_operations proc_sys_inode_operations;
+static const struct inode_operations proc_sys_inode_operations;
static void proc_sys_refresh_inode(struct inode *inode, struct ctl_table *table)
{
.readdir = proc_sys_readdir,
};
-static struct inode_operations proc_sys_inode_operations = {
+static const struct inode_operations proc_sys_inode_operations = {
.lookup = proc_sys_lookup,
.permission = proc_sys_permission,
.setattr = proc_sys_setattr,
#include <linux/seq_file.h>
#include <linux/bitops.h>
-static int tty_ldiscs_read_proc(char *page, char **start, off_t off,
- int count, int *eof, void *data);
-
/*
* The /proc/tty directory inodes...
*/
mutex_unlock(&tty_mutex);
}
-static struct seq_operations tty_drivers_op = {
+static const struct seq_operations tty_drivers_op = {
.start = t_start,
.next = t_next,
.stop = t_stop,
EXPORT_SYMBOL(proc_symlink);
EXPORT_SYMBOL(proc_mkdir);
EXPORT_SYMBOL(create_proc_entry);
+EXPORT_SYMBOL(proc_create);
EXPORT_SYMBOL(remove_proc_entry);
EXPORT_SYMBOL(proc_root);
EXPORT_SYMBOL(proc_root_fs);
#include <linux/mempolicy.h>
#include <linux/swap.h>
#include <linux/swapops.h>
+#include <linux/seq_file.h>
#include <asm/elf.h>
#include <asm/uaccess.h>
#include <asm/tlbflush.h>
#include "internal.h"
-char *task_mem(struct mm_struct *mm, char *buffer)
+void task_mem(struct seq_file *m, struct mm_struct *mm)
{
unsigned long data, text, lib;
unsigned long hiwater_vm, total_vm, hiwater_rss, total_rss;
data = mm->total_vm - mm->shared_vm - mm->stack_vm;
text = (PAGE_ALIGN(mm->end_code) - (mm->start_code & PAGE_MASK)) >> 10;
lib = (mm->exec_vm << (PAGE_SHIFT-10)) - text;
- buffer += sprintf(buffer,
+ seq_printf(m,
"VmPeak:\t%8lu kB\n"
"VmSize:\t%8lu kB\n"
"VmLck:\t%8lu kB\n"
data << (PAGE_SHIFT-10),
mm->stack_vm << (PAGE_SHIFT-10), text, lib,
(PTRS_PER_PTE*sizeof(pte_t)*mm->nr_ptes) >> 10);
- return buffer;
}
unsigned long task_vsize(struct mm_struct *mm)
}
static int do_maps_open(struct inode *inode, struct file *file,
- struct seq_operations *ops)
+ const struct seq_operations *ops)
{
struct proc_maps_private *priv;
int ret = -ENOMEM;
return 0;
}
-static struct seq_operations proc_pid_maps_op = {
+static const struct seq_operations proc_pid_maps_op = {
.start = m_start,
.next = m_next,
.stop = m_stop,
return ret;
}
-static struct seq_operations proc_pid_smaps_op = {
+static const struct seq_operations proc_pid_smaps_op = {
.start = m_start,
.next = m_next,
.stop = m_stop,
return show_numa_map(m, v);
}
-static struct seq_operations proc_pid_numa_maps_op = {
+static const struct seq_operations proc_pid_numa_maps_op = {
.start = m_start,
.next = m_next,
.stop = m_stop,
* each process that owns it. Non-shared memory is counted
* accurately.
*/
-char *task_mem(struct mm_struct *mm, char *buffer)
+void task_mem(struct seq_file *m, struct mm_struct *mm)
{
struct vm_list_struct *vml;
unsigned long bytes = 0, sbytes = 0, slack = 0;
bytes += kobjsize(current); /* includes kernel stack */
- buffer += sprintf(buffer,
+ seq_printf(m,
"Mem:\t%8lu bytes\n"
"Slack:\t%8lu bytes\n"
"Shared:\t%8lu bytes\n",
bytes, slack, sbytes);
up_read(&mm->mmap_sem);
- return buffer;
}
unsigned long task_vsize(struct mm_struct *mm)
return vml ? vml->next : NULL;
}
-static struct seq_operations proc_pid_maps_ops = {
+static const struct seq_operations proc_pid_maps_ops = {
.start = m_start,
.next = m_next,
.stop = m_stop,
#include <linux/mm.h>
#include <linux/proc_fs.h>
#include <linux/user.h>
-#include <linux/a.out.h>
#include <linux/elf.h>
#include <linux/elfcore.h>
#include <linux/highmem.h>
return ret;
}
-EXPORT_UNUSED_SYMBOL_GPL(sys_read); /* to be deleted for 2.6.25 */
asmlinkage ssize_t sys_write(unsigned int fd, const char __user * buf, size_t count)
{
return show(m, v);
}
-static struct seq_operations r_ops = {
+static const struct seq_operations r_ops = {
.start = r_start,
.next = r_next,
.stop = r_stop,
.unlockfs = reiserfs_unlockfs,
.statfs = reiserfs_statfs,
.remount_fs = reiserfs_remount,
+ .show_options = generic_show_options,
#ifdef CONFIG_QUOTA
.quota_read = reiserfs_quota_read,
.quota_write = reiserfs_quota_write,
unsigned long safe_mask = 0;
unsigned int commit_max_age = (unsigned int)-1;
struct reiserfs_journal *journal = SB_JOURNAL(s);
+ char *new_opts = kstrdup(arg, GFP_KERNEL);
int err;
#ifdef CONFIG_QUOTA
int i;
REISERFS_SB(s)->s_qf_names[i] = NULL;
}
#endif
- return -EINVAL;
+ err = -EINVAL;
+ goto out_err;
}
handle_attrs(s);
}
if (blocks) {
- int rc = reiserfs_resize(s, blocks);
- if (rc != 0)
- return rc;
+ err = reiserfs_resize(s, blocks);
+ if (err != 0)
+ goto out_err;
}
if (*mount_flags & MS_RDONLY) {
/* remount read-only */
if (s->s_flags & MS_RDONLY)
/* it is read-only already */
- return 0;
+ goto out_ok;
/* try to remount file system with read-only permissions */
if (sb_umount_state(rs) == REISERFS_VALID_FS
|| REISERFS_SB(s)->s_mount_state != REISERFS_VALID_FS) {
- return 0;
+ goto out_ok;
}
err = journal_begin(&th, s, 10);
if (err)
- return err;
+ goto out_err;
/* Mounting a rw partition read-only. */
reiserfs_prepare_for_journal(s, SB_BUFFER_WITH_SB(s), 1);
/* remount read-write */
if (!(s->s_flags & MS_RDONLY)) {
reiserfs_xattr_init(s, *mount_flags);
- return 0; /* We are read-write already */
+ goto out_ok; /* We are read-write already */
}
- if (reiserfs_is_journal_aborted(journal))
- return journal->j_errno;
+ if (reiserfs_is_journal_aborted(journal)) {
+ err = journal->j_errno;
+ goto out_err;
+ }
handle_data_mode(s, mount_options);
handle_barrier_mode(s, mount_options);
s->s_flags &= ~MS_RDONLY; /* now it is safe to call journal_begin */
err = journal_begin(&th, s, 10);
if (err)
- return err;
+ goto out_err;
/* Mount a partition which is read-only, read-write */
reiserfs_prepare_for_journal(s, SB_BUFFER_WITH_SB(s), 1);
SB_JOURNAL(s)->j_must_wait = 1;
err = journal_end(&th, s, 10);
if (err)
- return err;
+ goto out_err;
s->s_dirt = 0;
if (!(*mount_flags & MS_RDONLY)) {
reiserfs_xattr_init(s, *mount_flags);
}
+out_ok:
+ kfree(s->s_options);
+ s->s_options = new_opts;
return 0;
+
+out_err:
+ kfree(new_opts);
+ return err;
}
static int read_super_block(struct super_block *s, int offset)
struct reiserfs_sb_info *sbi;
int errval = -EINVAL;
+ save_mount_options(s, data);
+
sbi = kzalloc(sizeof(struct reiserfs_sb_info), GFP_KERNEL);
if (!sbi) {
errval = -ENOMEM;
{
int partial;
+ if (!access_ok(VERIFY_READ, src, n))
+ return -EFAULT;
+
pagefault_disable();
partial = __copy_from_user_inatomic(dst, src, n);
pagefault_enable();
break;
}
+ if (unlikely(!access_ok(VERIFY_WRITE, base, len))) {
+ error = -EFAULT;
+ break;
+ }
+
sd.len = 0;
sd.total_len = len;
sd.flags = flags;
{
security_sb_free(s);
kfree(s->s_subtype);
+ kfree(s->s_options);
kfree(s);
}
mark_files_ro(sb);
else if (!fs_may_remount_ro(sb))
return -EBUSY;
+ DQUOT_OFF(sb);
}
if (sb->s_op->remount_fs) {
#include "udf_i.h"
#include "udf_sb.h"
-#define udf_clear_bit(nr,addr) ext2_clear_bit(nr,addr)
-#define udf_set_bit(nr,addr) ext2_set_bit(nr,addr)
+#define udf_clear_bit(nr, addr) ext2_clear_bit(nr, addr)
+#define udf_set_bit(nr, addr) ext2_set_bit(nr, addr)
#define udf_test_bit(nr, addr) ext2_test_bit(nr, addr)
#define udf_find_first_one_bit(addr, size) find_first_one_bit(addr, size)
-#define udf_find_next_one_bit(addr, size, offset) find_next_one_bit(addr, size, offset)
+#define udf_find_next_one_bit(addr, size, offset) \
+ find_next_one_bit(addr, size, offset)
#define leBPL_to_cpup(x) leNUM_to_cpup(BITS_PER_LONG, x)
-#define leNUM_to_cpup(x,y) xleNUM_to_cpup(x,y)
-#define xleNUM_to_cpup(x,y) (le ## x ## _to_cpup(y))
+#define leNUM_to_cpup(x, y) xleNUM_to_cpup(x, y)
+#define xleNUM_to_cpup(x, y) (le ## x ## _to_cpup(y))
#define uintBPL_t uint(BITS_PER_LONG)
#define uint(x) xuint(x)
#define xuint(x) __le ## x
result += BITS_PER_LONG;
}
while (size & ~(BITS_PER_LONG - 1)) {
- if ((tmp = leBPL_to_cpup(p++)))
+ tmp = leBPL_to_cpup(p++);
+ if (tmp)
goto found_middle;
result += BITS_PER_LONG;
size -= BITS_PER_LONG;
kernel_lb_addr loc;
loc.logicalBlockNum = bitmap->s_extPosition;
- loc.partitionReferenceNum = UDF_SB_PARTITION(sb);
+ loc.partitionReferenceNum = UDF_SB(sb)->s_partition;
bh = udf_tread(sb, udf_get_lb_pblock(sb, loc, block));
- if (!bh) {
+ if (!bh)
retval = -EIO;
- }
+
bitmap->s_block_bitmap[bitmap_nr] = bh;
return retval;
}
return slot;
}
+static bool udf_add_free_space(struct udf_sb_info *sbi,
+ u16 partition, u32 cnt)
+{
+ struct logicalVolIntegrityDesc *lvid;
+
+ if (sbi->s_lvid_bh)
+ return false;
+
+ lvid = (struct logicalVolIntegrityDesc *)sbi->s_lvid_bh->b_data;
+ lvid->freeSpaceTable[partition] = cpu_to_le32(le32_to_cpu(
+ lvid->freeSpaceTable[partition]) + cnt);
+ return true;
+}
+
static void udf_bitmap_free_blocks(struct super_block *sb,
struct inode *inode,
struct udf_bitmap *bitmap,
mutex_lock(&sbi->s_alloc_mutex);
if (bloc.logicalBlockNum < 0 ||
- (bloc.logicalBlockNum + count) > UDF_SB_PARTLEN(sb, bloc.partitionReferenceNum)) {
+ (bloc.logicalBlockNum + count) >
+ sbi->s_partmaps[bloc.partitionReferenceNum].s_partition_len) {
udf_debug("%d < %d || %d + %d > %d\n",
bloc.logicalBlockNum, 0, bloc.logicalBlockNum, count,
- UDF_SB_PARTLEN(sb, bloc.partitionReferenceNum));
+ sbi->s_partmaps[bloc.partitionReferenceNum].
+ s_partition_len);
goto error_return;
}
- block = bloc.logicalBlockNum + offset + (sizeof(struct spaceBitmapDesc) << 3);
+ block = bloc.logicalBlockNum + offset +
+ (sizeof(struct spaceBitmapDesc) << 3);
-do_more:
- overflow = 0;
- block_group = block >> (sb->s_blocksize_bits + 3);
- bit = block % (sb->s_blocksize << 3);
+ do {
+ overflow = 0;
+ block_group = block >> (sb->s_blocksize_bits + 3);
+ bit = block % (sb->s_blocksize << 3);
- /*
- * Check to see if we are freeing blocks across a group boundary.
- */
- if (bit + count > (sb->s_blocksize << 3)) {
- overflow = bit + count - (sb->s_blocksize << 3);
- count -= overflow;
- }
- bitmap_nr = load_block_bitmap(sb, bitmap, block_group);
- if (bitmap_nr < 0)
- goto error_return;
+ /*
+ * Check to see if we are freeing blocks across a group boundary.
+ */
+ if (bit + count > (sb->s_blocksize << 3)) {
+ overflow = bit + count - (sb->s_blocksize << 3);
+ count -= overflow;
+ }
+ bitmap_nr = load_block_bitmap(sb, bitmap, block_group);
+ if (bitmap_nr < 0)
+ goto error_return;
- bh = bitmap->s_block_bitmap[bitmap_nr];
- for (i = 0; i < count; i++) {
- if (udf_set_bit(bit + i, bh->b_data)) {
- udf_debug("bit %ld already set\n", bit + i);
- udf_debug("byte=%2x\n", ((char *)bh->b_data)[(bit + i) >> 3]);
- } else {
- if (inode)
- DQUOT_FREE_BLOCK(inode, 1);
- if (UDF_SB_LVIDBH(sb)) {
- UDF_SB_LVID(sb)->freeSpaceTable[UDF_SB_PARTITION(sb)] =
- cpu_to_le32(le32_to_cpu(UDF_SB_LVID(sb)->freeSpaceTable[UDF_SB_PARTITION(sb)]) + 1);
+ bh = bitmap->s_block_bitmap[bitmap_nr];
+ for (i = 0; i < count; i++) {
+ if (udf_set_bit(bit + i, bh->b_data)) {
+ udf_debug("bit %ld already set\n", bit + i);
+ udf_debug("byte=%2x\n",
+ ((char *)bh->b_data)[(bit + i) >> 3]);
+ } else {
+ if (inode)
+ DQUOT_FREE_BLOCK(inode, 1);
+ udf_add_free_space(sbi, sbi->s_partition, 1);
}
}
- }
- mark_buffer_dirty(bh);
- if (overflow) {
- block += count;
- count = overflow;
- goto do_more;
- }
+ mark_buffer_dirty(bh);
+ if (overflow) {
+ block += count;
+ count = overflow;
+ }
+ } while (overflow);
+
error_return:
sb->s_dirt = 1;
- if (UDF_SB_LVIDBH(sb))
- mark_buffer_dirty(UDF_SB_LVIDBH(sb));
+ if (sbi->s_lvid_bh)
+ mark_buffer_dirty(sbi->s_lvid_bh);
mutex_unlock(&sbi->s_alloc_mutex);
- return;
}
static int udf_bitmap_prealloc_blocks(struct super_block *sb,
int bit, block, block_group, group_start;
int nr_groups, bitmap_nr;
struct buffer_head *bh;
+ __u32 part_len;
mutex_lock(&sbi->s_alloc_mutex);
- if (first_block < 0 || first_block >= UDF_SB_PARTLEN(sb, partition))
+ part_len = sbi->s_partmaps[partition].s_partition_len;
+ if (first_block < 0 || first_block >= part_len)
goto out;
- if (first_block + block_count > UDF_SB_PARTLEN(sb, partition))
- block_count = UDF_SB_PARTLEN(sb, partition) - first_block;
+ if (first_block + block_count > part_len)
+ block_count = part_len - first_block;
-repeat:
- nr_groups = (UDF_SB_PARTLEN(sb, partition) +
- (sizeof(struct spaceBitmapDesc) << 3) +
- (sb->s_blocksize * 8) - 1) / (sb->s_blocksize * 8);
- block = first_block + (sizeof(struct spaceBitmapDesc) << 3);
- block_group = block >> (sb->s_blocksize_bits + 3);
- group_start = block_group ? 0 : sizeof(struct spaceBitmapDesc);
+ do {
+ nr_groups = udf_compute_nr_groups(sb, partition);
+ block = first_block + (sizeof(struct spaceBitmapDesc) << 3);
+ block_group = block >> (sb->s_blocksize_bits + 3);
+ group_start = block_group ? 0 : sizeof(struct spaceBitmapDesc);
- bitmap_nr = load_block_bitmap(sb, bitmap, block_group);
- if (bitmap_nr < 0)
- goto out;
- bh = bitmap->s_block_bitmap[bitmap_nr];
+ bitmap_nr = load_block_bitmap(sb, bitmap, block_group);
+ if (bitmap_nr < 0)
+ goto out;
+ bh = bitmap->s_block_bitmap[bitmap_nr];
- bit = block % (sb->s_blocksize << 3);
+ bit = block % (sb->s_blocksize << 3);
- while (bit < (sb->s_blocksize << 3) && block_count > 0) {
- if (!udf_test_bit(bit, bh->b_data)) {
- goto out;
- } else if (DQUOT_PREALLOC_BLOCK(inode, 1)) {
- goto out;
- } else if (!udf_clear_bit(bit, bh->b_data)) {
- udf_debug("bit already cleared for block %d\n", bit);
- DQUOT_FREE_BLOCK(inode, 1);
- goto out;
+ while (bit < (sb->s_blocksize << 3) && block_count > 0) {
+ if (!udf_test_bit(bit, bh->b_data))
+ goto out;
+ else if (DQUOT_PREALLOC_BLOCK(inode, 1))
+ goto out;
+ else if (!udf_clear_bit(bit, bh->b_data)) {
+ udf_debug("bit already cleared for block %d\n", bit);
+ DQUOT_FREE_BLOCK(inode, 1);
+ goto out;
+ }
+ block_count--;
+ alloc_count++;
+ bit++;
+ block++;
}
- block_count--;
- alloc_count++;
- bit++;
- block++;
- }
- mark_buffer_dirty(bh);
- if (block_count > 0)
- goto repeat;
+ mark_buffer_dirty(bh);
+ } while (block_count > 0);
+
out:
- if (UDF_SB_LVIDBH(sb)) {
- UDF_SB_LVID(sb)->freeSpaceTable[partition] =
- cpu_to_le32(le32_to_cpu(UDF_SB_LVID(sb)->freeSpaceTable[partition]) - alloc_count);
- mark_buffer_dirty(UDF_SB_LVIDBH(sb));
- }
+ if (udf_add_free_space(sbi, partition, -alloc_count))
+ mark_buffer_dirty(sbi->s_lvid_bh);
sb->s_dirt = 1;
mutex_unlock(&sbi->s_alloc_mutex);
return alloc_count;
mutex_lock(&sbi->s_alloc_mutex);
repeat:
- if (goal < 0 || goal >= UDF_SB_PARTLEN(sb, partition))
+ if (goal < 0 || goal >= sbi->s_partmaps[partition].s_partition_len)
goal = 0;
nr_groups = bitmap->s_nr_groups;
if (bit < end_goal)
goto got_block;
- ptr = memscan((char *)bh->b_data + (bit >> 3), 0xFF, sb->s_blocksize - ((bit + 7) >> 3));
+ ptr = memscan((char *)bh->b_data + (bit >> 3), 0xFF,
+ sb->s_blocksize - ((bit + 7) >> 3));
newbit = (ptr - ((char *)bh->b_data)) << 3;
if (newbit < sb->s_blocksize << 3) {
bit = newbit;
goto search_back;
}
- newbit = udf_find_next_one_bit(bh->b_data, sb->s_blocksize << 3, bit);
+ newbit = udf_find_next_one_bit(bh->b_data,
+ sb->s_blocksize << 3, bit);
if (newbit < sb->s_blocksize << 3) {
bit = newbit;
goto got_block;
if (bit < sb->s_blocksize << 3)
goto search_back;
else
- bit = udf_find_next_one_bit(bh->b_data, sb->s_blocksize << 3, group_start << 3);
+ bit = udf_find_next_one_bit(bh->b_data, sb->s_blocksize << 3,
+ group_start << 3);
if (bit >= sb->s_blocksize << 3) {
mutex_unlock(&sbi->s_alloc_mutex);
return 0;
}
search_back:
- for (i = 0; i < 7 && bit > (group_start << 3) && udf_test_bit(bit - 1, bh->b_data); i++, bit--)
- ; /* empty loop */
+ i = 0;
+ while (i < 7 && bit > (group_start << 3) &&
+ udf_test_bit(bit - 1, bh->b_data)) {
+ ++i;
+ --bit;
+ }
got_block:
mark_buffer_dirty(bh);
- if (UDF_SB_LVIDBH(sb)) {
- UDF_SB_LVID(sb)->freeSpaceTable[partition] =
- cpu_to_le32(le32_to_cpu(UDF_SB_LVID(sb)->freeSpaceTable[partition]) - 1);
- mark_buffer_dirty(UDF_SB_LVIDBH(sb));
- }
+ if (udf_add_free_space(sbi, partition, -1))
+ mark_buffer_dirty(sbi->s_lvid_bh);
sb->s_dirt = 1;
mutex_unlock(&sbi->s_alloc_mutex);
*err = 0;
struct extent_position oepos, epos;
int8_t etype;
int i;
+ struct udf_inode_info *iinfo;
mutex_lock(&sbi->s_alloc_mutex);
if (bloc.logicalBlockNum < 0 ||
- (bloc.logicalBlockNum + count) > UDF_SB_PARTLEN(sb, bloc.partitionReferenceNum)) {
+ (bloc.logicalBlockNum + count) >
+ sbi->s_partmaps[bloc.partitionReferenceNum].s_partition_len) {
udf_debug("%d < %d || %d + %d > %d\n",
bloc.logicalBlockNum, 0, bloc.logicalBlockNum, count,
- UDF_SB_PARTLEN(sb, bloc.partitionReferenceNum));
+ sbi->s_partmaps[bloc.partitionReferenceNum].
+ s_partition_len);
goto error_return;
}
- /* We do this up front - There are some error conditions that could occure,
- but.. oh well */
+ iinfo = UDF_I(table);
+ /* We do this up front - There are some error conditions that
+ could occure, but.. oh well */
if (inode)
DQUOT_FREE_BLOCK(inode, count);
- if (UDF_SB_LVIDBH(sb)) {
- UDF_SB_LVID(sb)->freeSpaceTable[UDF_SB_PARTITION(sb)] =
- cpu_to_le32(le32_to_cpu(UDF_SB_LVID(sb)->freeSpaceTable[UDF_SB_PARTITION(sb)]) + count);
- mark_buffer_dirty(UDF_SB_LVIDBH(sb));
- }
+ if (udf_add_free_space(sbi, sbi->s_partition, count))
+ mark_buffer_dirty(sbi->s_lvid_bh);
start = bloc.logicalBlockNum + offset;
end = bloc.logicalBlockNum + offset + count - 1;
epos.offset = oepos.offset = sizeof(struct unallocSpaceEntry);
elen = 0;
- epos.block = oepos.block = UDF_I_LOCATION(table);
+ epos.block = oepos.block = iinfo->i_location;
epos.bh = oepos.bh = NULL;
while (count &&
(etype = udf_next_aext(table, &epos, &eloc, &elen, 1)) != -1) {
- if (((eloc.logicalBlockNum + (elen >> sb->s_blocksize_bits)) == start)) {
- if ((0x3FFFFFFF - elen) < (count << sb->s_blocksize_bits)) {
- count -= ((0x3FFFFFFF - elen) >> sb->s_blocksize_bits);
- start += ((0x3FFFFFFF - elen) >> sb->s_blocksize_bits);
- elen = (etype << 30) | (0x40000000 - sb->s_blocksize);
+ if (((eloc.logicalBlockNum +
+ (elen >> sb->s_blocksize_bits)) == start)) {
+ if ((0x3FFFFFFF - elen) <
+ (count << sb->s_blocksize_bits)) {
+ uint32_t tmp = ((0x3FFFFFFF - elen) >>
+ sb->s_blocksize_bits);
+ count -= tmp;
+ start += tmp;
+ elen = (etype << 30) |
+ (0x40000000 - sb->s_blocksize);
} else {
- elen = (etype << 30) | (elen + (count << sb->s_blocksize_bits));
+ elen = (etype << 30) |
+ (elen +
+ (count << sb->s_blocksize_bits));
start += count;
count = 0;
}
udf_write_aext(table, &oepos, eloc, elen, 1);
} else if (eloc.logicalBlockNum == (end + 1)) {
- if ((0x3FFFFFFF - elen) < (count << sb->s_blocksize_bits)) {
- count -= ((0x3FFFFFFF - elen) >> sb->s_blocksize_bits);
- end -= ((0x3FFFFFFF - elen) >> sb->s_blocksize_bits);
- eloc.logicalBlockNum -= ((0x3FFFFFFF - elen) >> sb->s_blocksize_bits);
- elen = (etype << 30) | (0x40000000 - sb->s_blocksize);
+ if ((0x3FFFFFFF - elen) <
+ (count << sb->s_blocksize_bits)) {
+ uint32_t tmp = ((0x3FFFFFFF - elen) >>
+ sb->s_blocksize_bits);
+ count -= tmp;
+ end -= tmp;
+ eloc.logicalBlockNum -= tmp;
+ elen = (etype << 30) |
+ (0x40000000 - sb->s_blocksize);
} else {
eloc.logicalBlockNum = start;
- elen = (etype << 30) | (elen + (count << sb->s_blocksize_bits));
+ elen = (etype << 30) |
+ (elen +
+ (count << sb->s_blocksize_bits));
end -= count;
count = 0;
}
if (count) {
/*
- * NOTE: we CANNOT use udf_add_aext here, as it can try to allocate
- * a new block, and since we hold the super block lock already
- * very bad things would happen :)
+ * NOTE: we CANNOT use udf_add_aext here, as it can try to
+ * allocate a new block, and since we hold the super block
+ * lock already very bad things would happen :)
*
* We copy the behavior of udf_add_aext, but instead of
* trying to allocate a new block close to the existing one,
elen = EXT_RECORDED_ALLOCATED |
(count << sb->s_blocksize_bits);
- if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_SHORT) {
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
adsize = sizeof(short_ad);
- } else if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_LONG) {
+ else if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
adsize = sizeof(long_ad);
- } else {
+ else {
brelse(oepos.bh);
brelse(epos.bh);
goto error_return;
eloc.logicalBlockNum++;
elen -= sb->s_blocksize;
- if (!(epos.bh = udf_tread(sb, udf_get_lb_pblock(sb, epos.block, 0)))) {
+ epos.bh = udf_tread(sb,
+ udf_get_lb_pblock(sb, epos.block, 0));
+ if (!epos.bh) {
brelse(oepos.bh);
goto error_return;
}
aed = (struct allocExtDesc *)(epos.bh->b_data);
- aed->previousAllocExtLocation = cpu_to_le32(oepos.block.logicalBlockNum);
+ aed->previousAllocExtLocation =
+ cpu_to_le32(oepos.block.logicalBlockNum);
if (epos.offset + adsize > sb->s_blocksize) {
loffset = epos.offset;
aed->lengthAllocDescs = cpu_to_le32(adsize);
- sptr = UDF_I_DATA(table) + epos.offset - adsize;
- dptr = epos.bh->b_data + sizeof(struct allocExtDesc);
+ sptr = iinfo->i_ext.i_data + epos.offset
+ - adsize;
+ dptr = epos.bh->b_data +
+ sizeof(struct allocExtDesc);
memcpy(dptr, sptr, adsize);
- epos.offset = sizeof(struct allocExtDesc) + adsize;
+ epos.offset = sizeof(struct allocExtDesc) +
+ adsize;
} else {
loffset = epos.offset + adsize;
aed->lengthAllocDescs = cpu_to_le32(0);
if (oepos.bh) {
sptr = oepos.bh->b_data + epos.offset;
- aed = (struct allocExtDesc *)oepos.bh->b_data;
+ aed = (struct allocExtDesc *)
+ oepos.bh->b_data;
aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) + adsize);
+ cpu_to_le32(le32_to_cpu(
+ aed->lengthAllocDescs) +
+ adsize);
} else {
- sptr = UDF_I_DATA(table) + epos.offset;
- UDF_I_LENALLOC(table) += adsize;
+ sptr = iinfo->i_ext.i_data +
+ epos.offset;
+ iinfo->i_lenAlloc += adsize;
mark_inode_dirty(table);
}
epos.offset = sizeof(struct allocExtDesc);
}
- if (UDF_SB_UDFREV(sb) >= 0x0200)
- udf_new_tag(epos.bh->b_data, TAG_IDENT_AED, 3, 1,
- epos.block.logicalBlockNum, sizeof(tag));
+ if (sbi->s_udfrev >= 0x0200)
+ udf_new_tag(epos.bh->b_data, TAG_IDENT_AED,
+ 3, 1, epos.block.logicalBlockNum,
+ sizeof(tag));
else
- udf_new_tag(epos.bh->b_data, TAG_IDENT_AED, 2, 1,
- epos.block.logicalBlockNum, sizeof(tag));
-
- switch (UDF_I_ALLOCTYPE(table)) {
- case ICBTAG_FLAG_AD_SHORT:
- sad = (short_ad *)sptr;
- sad->extLength = cpu_to_le32(
- EXT_NEXT_EXTENT_ALLOCDECS |
- sb->s_blocksize);
- sad->extPosition = cpu_to_le32(epos.block.logicalBlockNum);
- break;
- case ICBTAG_FLAG_AD_LONG:
- lad = (long_ad *)sptr;
- lad->extLength = cpu_to_le32(
- EXT_NEXT_EXTENT_ALLOCDECS |
- sb->s_blocksize);
- lad->extLocation = cpu_to_lelb(epos.block);
- break;
+ udf_new_tag(epos.bh->b_data, TAG_IDENT_AED,
+ 2, 1, epos.block.logicalBlockNum,
+ sizeof(tag));
+
+ switch (iinfo->i_alloc_type) {
+ case ICBTAG_FLAG_AD_SHORT:
+ sad = (short_ad *)sptr;
+ sad->extLength = cpu_to_le32(
+ EXT_NEXT_EXTENT_ALLOCDECS |
+ sb->s_blocksize);
+ sad->extPosition =
+ cpu_to_le32(epos.block.logicalBlockNum);
+ break;
+ case ICBTAG_FLAG_AD_LONG:
+ lad = (long_ad *)sptr;
+ lad->extLength = cpu_to_le32(
+ EXT_NEXT_EXTENT_ALLOCDECS |
+ sb->s_blocksize);
+ lad->extLocation =
+ cpu_to_lelb(epos.block);
+ break;
}
if (oepos.bh) {
udf_update_tag(oepos.bh->b_data, loffset);
}
}
- if (elen) { /* It's possible that stealing the block emptied the extent */
+ /* It's possible that stealing the block emptied the extent */
+ if (elen) {
udf_write_aext(table, &epos, eloc, elen, 1);
if (!epos.bh) {
- UDF_I_LENALLOC(table) += adsize;
+ iinfo->i_lenAlloc += adsize;
mark_inode_dirty(table);
} else {
aed = (struct allocExtDesc *)epos.bh->b_data;
aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) + adsize);
+ cpu_to_le32(le32_to_cpu(
+ aed->lengthAllocDescs) + adsize);
udf_update_tag(epos.bh->b_data, epos.offset);
mark_buffer_dirty(epos.bh);
}
kernel_lb_addr eloc;
struct extent_position epos;
int8_t etype = -1;
+ struct udf_inode_info *iinfo;
- if (first_block < 0 || first_block >= UDF_SB_PARTLEN(sb, partition))
+ if (first_block < 0 ||
+ first_block >= sbi->s_partmaps[partition].s_partition_len)
return 0;
- if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_SHORT)
+ iinfo = UDF_I(table);
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
adsize = sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_LONG)
+ else if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
adsize = sizeof(long_ad);
else
return 0;
mutex_lock(&sbi->s_alloc_mutex);
epos.offset = sizeof(struct unallocSpaceEntry);
- epos.block = UDF_I_LOCATION(table);
+ epos.block = iinfo->i_location;
epos.bh = NULL;
eloc.logicalBlockNum = 0xFFFFFFFF;
epos.offset -= adsize;
alloc_count = (elen >> sb->s_blocksize_bits);
- if (inode && DQUOT_PREALLOC_BLOCK(inode, alloc_count > block_count ? block_count : alloc_count)) {
+ if (inode && DQUOT_PREALLOC_BLOCK(inode,
+ alloc_count > block_count ? block_count : alloc_count))
alloc_count = 0;
- } else if (alloc_count > block_count) {
+ else if (alloc_count > block_count) {
alloc_count = block_count;
eloc.logicalBlockNum += alloc_count;
elen -= (alloc_count << sb->s_blocksize_bits);
- udf_write_aext(table, &epos, eloc, (etype << 30) | elen, 1);
- } else {
- udf_delete_aext(table, epos, eloc, (etype << 30) | elen);
- }
+ udf_write_aext(table, &epos, eloc,
+ (etype << 30) | elen, 1);
+ } else
+ udf_delete_aext(table, epos, eloc,
+ (etype << 30) | elen);
} else {
alloc_count = 0;
}
brelse(epos.bh);
- if (alloc_count && UDF_SB_LVIDBH(sb)) {
- UDF_SB_LVID(sb)->freeSpaceTable[partition] =
- cpu_to_le32(le32_to_cpu(UDF_SB_LVID(sb)->freeSpaceTable[partition]) - alloc_count);
- mark_buffer_dirty(UDF_SB_LVIDBH(sb));
+ if (alloc_count && udf_add_free_space(sbi, partition, -alloc_count)) {
+ mark_buffer_dirty(sbi->s_lvid_bh);
sb->s_dirt = 1;
}
mutex_unlock(&sbi->s_alloc_mutex);
kernel_lb_addr eloc, uninitialized_var(goal_eloc);
struct extent_position epos, goal_epos;
int8_t etype;
+ struct udf_inode_info *iinfo = UDF_I(table);
*err = -ENOSPC;
- if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_SHORT)
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
adsize = sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_LONG)
+ else if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
adsize = sizeof(long_ad);
else
return newblock;
mutex_lock(&sbi->s_alloc_mutex);
- if (goal < 0 || goal >= UDF_SB_PARTLEN(sb, partition))
+ if (goal < 0 || goal >= sbi->s_partmaps[partition].s_partition_len)
goal = 0;
- /* We search for the closest matching block to goal. If we find a exact hit,
- we stop. Otherwise we keep going till we run out of extents.
- We store the buffer_head, bloc, and extoffset of the current closest
- match and use that when we are done.
+ /* We search for the closest matching block to goal. If we find
+ a exact hit, we stop. Otherwise we keep going till we run out
+ of extents. We store the buffer_head, bloc, and extoffset
+ of the current closest match and use that when we are done.
*/
epos.offset = sizeof(struct unallocSpaceEntry);
- epos.block = UDF_I_LOCATION(table);
+ epos.block = iinfo->i_location;
epos.bh = goal_epos.bh = NULL;
while (spread &&
(etype = udf_next_aext(table, &epos, &eloc, &elen, 1)) != -1) {
if (goal >= eloc.logicalBlockNum) {
- if (goal < eloc.logicalBlockNum + (elen >> sb->s_blocksize_bits))
+ if (goal < eloc.logicalBlockNum +
+ (elen >> sb->s_blocksize_bits))
nspread = 0;
else
nspread = goal - eloc.logicalBlockNum -
udf_delete_aext(table, goal_epos, goal_eloc, goal_elen);
brelse(goal_epos.bh);
- if (UDF_SB_LVIDBH(sb)) {
- UDF_SB_LVID(sb)->freeSpaceTable[partition] =
- cpu_to_le32(le32_to_cpu(UDF_SB_LVID(sb)->freeSpaceTable[partition]) - 1);
- mark_buffer_dirty(UDF_SB_LVIDBH(sb));
- }
+ if (udf_add_free_space(sbi, partition, -1))
+ mark_buffer_dirty(sbi->s_lvid_bh);
sb->s_dirt = 1;
mutex_unlock(&sbi->s_alloc_mutex);
uint32_t count)
{
uint16_t partition = bloc.partitionReferenceNum;
+ struct udf_part_map *map = &UDF_SB(sb)->s_partmaps[partition];
- if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_UNALLOC_BITMAP) {
+ if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_BITMAP) {
return udf_bitmap_free_blocks(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_uspace.s_bitmap,
+ map->s_uspace.s_bitmap,
bloc, offset, count);
- } else if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_UNALLOC_TABLE) {
+ } else if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_TABLE) {
return udf_table_free_blocks(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_uspace.s_table,
+ map->s_uspace.s_table,
bloc, offset, count);
- } else if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_FREED_BITMAP) {
+ } else if (map->s_partition_flags & UDF_PART_FLAG_FREED_BITMAP) {
return udf_bitmap_free_blocks(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_fspace.s_bitmap,
+ map->s_fspace.s_bitmap,
bloc, offset, count);
- } else if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_FREED_TABLE) {
+ } else if (map->s_partition_flags & UDF_PART_FLAG_FREED_TABLE) {
return udf_table_free_blocks(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_fspace.s_table,
+ map->s_fspace.s_table,
bloc, offset, count);
} else {
return;
uint16_t partition, uint32_t first_block,
uint32_t block_count)
{
- if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_UNALLOC_BITMAP) {
+ struct udf_part_map *map = &UDF_SB(sb)->s_partmaps[partition];
+
+ if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_BITMAP)
return udf_bitmap_prealloc_blocks(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_uspace.s_bitmap,
- partition, first_block, block_count);
- } else if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_UNALLOC_TABLE) {
+ map->s_uspace.s_bitmap,
+ partition, first_block,
+ block_count);
+ else if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_TABLE)
return udf_table_prealloc_blocks(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_uspace.s_table,
- partition, first_block, block_count);
- } else if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_FREED_BITMAP) {
+ map->s_uspace.s_table,
+ partition, first_block,
+ block_count);
+ else if (map->s_partition_flags & UDF_PART_FLAG_FREED_BITMAP)
return udf_bitmap_prealloc_blocks(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_fspace.s_bitmap,
- partition, first_block, block_count);
- } else if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_FREED_TABLE) {
+ map->s_fspace.s_bitmap,
+ partition, first_block,
+ block_count);
+ else if (map->s_partition_flags & UDF_PART_FLAG_FREED_TABLE)
return udf_table_prealloc_blocks(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_fspace.s_table,
- partition, first_block, block_count);
- } else {
+ map->s_fspace.s_table,
+ partition, first_block,
+ block_count);
+ else
return 0;
- }
}
inline int udf_new_block(struct super_block *sb,
struct inode *inode,
uint16_t partition, uint32_t goal, int *err)
{
- int ret;
+ struct udf_part_map *map = &UDF_SB(sb)->s_partmaps[partition];
- if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_UNALLOC_BITMAP) {
- ret = udf_bitmap_new_block(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_uspace.s_bitmap,
+ if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_BITMAP)
+ return udf_bitmap_new_block(sb, inode,
+ map->s_uspace.s_bitmap,
partition, goal, err);
- return ret;
- } else if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_UNALLOC_TABLE) {
+ else if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_TABLE)
return udf_table_new_block(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_uspace.s_table,
+ map->s_uspace.s_table,
partition, goal, err);
- } else if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_FREED_BITMAP) {
+ else if (map->s_partition_flags & UDF_PART_FLAG_FREED_BITMAP)
return udf_bitmap_new_block(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_fspace.s_bitmap,
+ map->s_fspace.s_bitmap,
partition, goal, err);
- } else if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_FREED_TABLE) {
+ else if (map->s_partition_flags & UDF_PART_FLAG_FREED_TABLE)
return udf_table_new_block(sb, inode,
- UDF_SB_PARTMAPS(sb)[partition].s_fspace.s_table,
+ map->s_fspace.s_table,
partition, goal, err);
- } else {
+ else {
*err = -EIO;
return 0;
}
* July 21, 1997 - Andrew E. Mileski
* Adapted from OSTA-UDF(tm) 1.50 standard.
*/
-uint16_t udf_crc(uint8_t * data, uint32_t size, uint16_t crc)
+uint16_t udf_crc(uint8_t *data, uint32_t size, uint16_t crc)
{
while (size--)
crc = crc_table[(crc >> 8 ^ *(data++)) & 0xffU] ^ (crc << 8);
#include "udf_i.h"
#include "udf_sb.h"
-/* Prototypes for file operations */
-static int udf_readdir(struct file *, void *, filldir_t);
-static int do_udf_readdir(struct inode *, struct file *, filldir_t, void *);
-
-/* readdir and lookup functions */
-
-const struct file_operations udf_dir_operations = {
- .read = generic_read_dir,
- .readdir = udf_readdir,
- .ioctl = udf_ioctl,
- .fsync = udf_fsync_file,
-};
-
-/*
- * udf_readdir
- *
- * PURPOSE
- * Read a directory entry.
- *
- * DESCRIPTION
- * Optional - sys_getdents() will return -ENOTDIR if this routine is not
- * available.
- *
- * Refer to sys_getdents() in fs/readdir.c
- * sys_getdents() -> .
- *
- * PRE-CONDITIONS
- * filp Pointer to directory file.
- * buf Pointer to directory entry buffer.
- * filldir Pointer to filldir function.
- *
- * POST-CONDITIONS
- * <return> >=0 on success.
- *
- * HISTORY
- * July 1, 1997 - Andrew E. Mileski
- * Written, tested, and released.
- */
-
-int udf_readdir(struct file *filp, void *dirent, filldir_t filldir)
-{
- struct inode *dir = filp->f_path.dentry->d_inode;
- int result;
-
- lock_kernel();
-
- if (filp->f_pos == 0) {
- if (filldir(dirent, ".", 1, filp->f_pos, dir->i_ino, DT_DIR) < 0) {
- unlock_kernel();
- return 0;
- }
- filp->f_pos++;
- }
-
- result = do_udf_readdir(dir, filp, filldir, dirent);
- unlock_kernel();
- return result;
-}
-
-static int
-do_udf_readdir(struct inode *dir, struct file *filp, filldir_t filldir,
- void *dirent)
+static int do_udf_readdir(struct inode *dir, struct file *filp,
+ filldir_t filldir, void *dirent)
{
struct udf_fileident_bh fibh;
struct fileIdentDesc *fi = NULL;
int i, num;
unsigned int dt_type;
struct extent_position epos = { NULL, 0, {0, 0} };
+ struct udf_inode_info *iinfo;
if (nf_pos >= size)
return 0;
nf_pos = (udf_ext0_offset(dir) >> 2);
fibh.soffset = fibh.eoffset = (nf_pos & ((dir->i_sb->s_blocksize - 1) >> 2)) << 2;
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB) {
+ iinfo = UDF_I(dir);
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
fibh.sbh = fibh.ebh = NULL;
} else if (inode_bmap(dir, nf_pos >> (dir->i_sb->s_blocksize_bits - 2),
&epos, &eloc, &elen, &offset) == (EXT_RECORDED_ALLOCATED >> 30)) {
block = udf_get_lb_pblock(dir->i_sb, eloc, offset);
if ((++offset << dir->i_sb->s_blocksize_bits) < elen) {
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_SHORT)
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
epos.offset -= sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_LONG)
+ else if (iinfo->i_alloc_type ==
+ ICBTAG_FLAG_AD_LONG)
epos.offset -= sizeof(long_ad);
} else {
offset = 0;
return 0;
}
+
+/*
+ * udf_readdir
+ *
+ * PURPOSE
+ * Read a directory entry.
+ *
+ * DESCRIPTION
+ * Optional - sys_getdents() will return -ENOTDIR if this routine is not
+ * available.
+ *
+ * Refer to sys_getdents() in fs/readdir.c
+ * sys_getdents() -> .
+ *
+ * PRE-CONDITIONS
+ * filp Pointer to directory file.
+ * buf Pointer to directory entry buffer.
+ * filldir Pointer to filldir function.
+ *
+ * POST-CONDITIONS
+ * <return> >=0 on success.
+ *
+ * HISTORY
+ * July 1, 1997 - Andrew E. Mileski
+ * Written, tested, and released.
+ */
+
+static int udf_readdir(struct file *filp, void *dirent, filldir_t filldir)
+{
+ struct inode *dir = filp->f_path.dentry->d_inode;
+ int result;
+
+ lock_kernel();
+
+ if (filp->f_pos == 0) {
+ if (filldir(dirent, ".", 1, filp->f_pos, dir->i_ino, DT_DIR) < 0) {
+ unlock_kernel();
+ return 0;
+ }
+ filp->f_pos++;
+ }
+
+ result = do_udf_readdir(dir, filp, filldir, dirent);
+ unlock_kernel();
+ return result;
+}
+
+/* readdir and lookup functions */
+const struct file_operations udf_dir_operations = {
+ .read = generic_read_dir,
+ .readdir = udf_readdir,
+ .ioctl = udf_ioctl,
+ .fsync = udf_fsync_file,
+};
#include <linux/buffer_head.h>
#if 0
-static uint8_t *udf_filead_read(struct inode *dir, uint8_t * tmpad,
+static uint8_t *udf_filead_read(struct inode *dir, uint8_t *tmpad,
uint8_t ad_size, kernel_lb_addr fe_loc,
int *pos, int *offset, struct buffer_head **bh,
int *error)
block = udf_get_lb_pblock(dir->i_sb, fe_loc, ++*pos);
if (!block)
return NULL;
- if (!(*bh = udf_tread(dir->i_sb, block)))
+ *bh = udf_tread(dir->i_sb, block);
+ if (!*bh)
return NULL;
} else if (*offset > dir->i_sb->s_blocksize) {
ad = tmpad;
block = udf_get_lb_pblock(dir->i_sb, fe_loc, ++*pos);
if (!block)
return NULL;
- if (!((*bh) = udf_tread(dir->i_sb, block)))
+ (*bh) = udf_tread(dir->i_sb, block);
+ if (!*bh)
return NULL;
- memcpy((uint8_t *)ad + remainder, (*bh)->b_data, ad_size - remainder);
+ memcpy((uint8_t *)ad + remainder, (*bh)->b_data,
+ ad_size - remainder);
*offset = ad_size - remainder;
}
}
#endif
-struct fileIdentDesc *udf_fileident_read(struct inode *dir, loff_t * nf_pos,
+struct fileIdentDesc *udf_fileident_read(struct inode *dir, loff_t *nf_pos,
struct udf_fileident_bh *fibh,
struct fileIdentDesc *cfi,
struct extent_position *epos,
- kernel_lb_addr * eloc, uint32_t * elen,
- sector_t * offset)
+ kernel_lb_addr *eloc, uint32_t *elen,
+ sector_t *offset)
{
struct fileIdentDesc *fi;
int i, num, block;
struct buffer_head *tmp, *bha[16];
+ struct udf_inode_info *iinfo = UDF_I(dir);
fibh->soffset = fibh->eoffset;
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB) {
- fi = udf_get_fileident(UDF_I_DATA(dir) -
- (UDF_I_EFE(dir) ?
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
+ fi = udf_get_fileident(iinfo->i_ext.i_data -
+ (iinfo->i_efe ?
sizeof(struct extendedFileEntry) :
sizeof(struct fileEntry)),
- dir->i_sb->s_blocksize, &(fibh->eoffset));
+ dir->i_sb->s_blocksize,
+ &(fibh->eoffset));
if (!fi)
return NULL;
- *nf_pos += ((fibh->eoffset - fibh->soffset) >> 2);
+ *nf_pos += fibh->eoffset - fibh->soffset;
memcpy((uint8_t *)cfi, (uint8_t *)fi,
sizeof(struct fileIdentDesc));
if (fibh->eoffset == dir->i_sb->s_blocksize) {
int lextoffset = epos->offset;
+ unsigned char blocksize_bits = dir->i_sb->s_blocksize_bits;
if (udf_next_aext(dir, epos, eloc, elen, 1) !=
(EXT_RECORDED_ALLOCATED >> 30))
(*offset)++;
- if ((*offset << dir->i_sb->s_blocksize_bits) >= *elen)
+ if ((*offset << blocksize_bits) >= *elen)
*offset = 0;
else
epos->offset = lextoffset;
brelse(fibh->sbh);
- if (!(fibh->sbh = fibh->ebh = udf_tread(dir->i_sb, block)))
+ fibh->sbh = fibh->ebh = udf_tread(dir->i_sb, block);
+ if (!fibh->sbh)
return NULL;
fibh->soffset = fibh->eoffset = 0;
- if (!(*offset & ((16 >> (dir->i_sb->s_blocksize_bits - 9)) - 1))) {
- i = 16 >> (dir->i_sb->s_blocksize_bits - 9);
- if (i + *offset > (*elen >> dir->i_sb->s_blocksize_bits))
- i = (*elen >> dir->i_sb->s_blocksize_bits)-*offset;
+ if (!(*offset & ((16 >> (blocksize_bits - 9)) - 1))) {
+ i = 16 >> (blocksize_bits - 9);
+ if (i + *offset > (*elen >> blocksize_bits))
+ i = (*elen >> blocksize_bits)-*offset;
for (num = 0; i > 0; i--) {
- block = udf_get_lb_pblock(dir->i_sb, *eloc, *offset + i);
+ block = udf_get_lb_pblock(dir->i_sb, *eloc,
+ *offset + i);
tmp = udf_tgetblk(dir->i_sb, block);
- if (tmp && !buffer_uptodate(tmp) && !buffer_locked(tmp))
+ if (tmp && !buffer_uptodate(tmp) &&
+ !buffer_locked(tmp))
bha[num++] = tmp;
else
brelse(tmp);
if (!fi)
return NULL;
- *nf_pos += ((fibh->eoffset - fibh->soffset) >> 2);
+ *nf_pos += fibh->eoffset - fibh->soffset;
if (fibh->eoffset <= dir->i_sb->s_blocksize) {
memcpy((uint8_t *)cfi, (uint8_t *)fi,
fibh->soffset -= dir->i_sb->s_blocksize;
fibh->eoffset -= dir->i_sb->s_blocksize;
- if (!(fibh->ebh = udf_tread(dir->i_sb, block)))
+ fibh->ebh = udf_tread(dir->i_sb, block);
+ if (!fibh->ebh)
return NULL;
if (sizeof(struct fileIdentDesc) > -fibh->soffset) {
int fi_len;
memcpy((uint8_t *)cfi, (uint8_t *)fi, -fibh->soffset);
- memcpy((uint8_t *)cfi - fibh->soffset, fibh->ebh->b_data,
+ memcpy((uint8_t *)cfi - fibh->soffset,
+ fibh->ebh->b_data,
sizeof(struct fileIdentDesc) + fibh->soffset);
- fi_len = (sizeof(struct fileIdentDesc) + cfi->lengthFileIdent +
+ fi_len = (sizeof(struct fileIdentDesc) +
+ cfi->lengthFileIdent +
le16_to_cpu(cfi->lengthOfImpUse) + 3) & ~3;
- *nf_pos += ((fi_len - (fibh->eoffset - fibh->soffset)) >> 2);
+ *nf_pos += fi_len - (fibh->eoffset - fibh->soffset);
fibh->eoffset = fibh->soffset + fi_len;
} else {
memcpy((uint8_t *)cfi, (uint8_t *)fi,
ptr = buffer;
- if ((*offset > 0) && (*offset < bufsize)) {
+ if ((*offset > 0) && (*offset < bufsize))
ptr += *offset;
- }
fi = (struct fileIdentDesc *)ptr;
- if (le16_to_cpu(fi->descTag.tagIdent) != TAG_IDENT_FID) {
+ if (fi->descTag.tagIdent != cpu_to_le16(TAG_IDENT_FID)) {
udf_debug("0x%x != TAG_IDENT_FID\n",
le16_to_cpu(fi->descTag.tagIdent));
udf_debug("offset: %u sizeof: %lu bufsize: %u\n",
bufsize);
return NULL;
}
- if ((*offset + sizeof(struct fileIdentDesc)) > bufsize) {
+ if ((*offset + sizeof(struct fileIdentDesc)) > bufsize)
lengthThisIdent = sizeof(struct fileIdentDesc);
- } else {
+ else
lengthThisIdent = sizeof(struct fileIdentDesc) +
fi->lengthFileIdent + le16_to_cpu(fi->lengthOfImpUse);
- }
/* we need to figure padding, too! */
padlen = lengthThisIdent % UDF_NAME_PAD;
fe = (struct fileEntry *)buffer;
- if (le16_to_cpu(fe->descTag.tagIdent) != TAG_IDENT_FE) {
+ if (fe->descTag.tagIdent != cpu_to_le16(TAG_IDENT_FE)) {
udf_debug("0x%x != TAG_IDENT_FE\n",
le16_to_cpu(fe->descTag.tagIdent));
return NULL;
}
- ptr = (uint8_t *)(fe->extendedAttr) + le32_to_cpu(fe->lengthExtendedAttr);
+ ptr = (uint8_t *)(fe->extendedAttr) +
+ le32_to_cpu(fe->lengthExtendedAttr);
- if ((*offset > 0) && (*offset < le32_to_cpu(fe->lengthAllocDescs))) {
+ if ((*offset > 0) && (*offset < le32_to_cpu(fe->lengthAllocDescs)))
ptr += *offset;
- }
ext = (extent_ad *)ptr;
}
#endif
-short_ad *udf_get_fileshortad(uint8_t *ptr, int maxoffset, int *offset,
+short_ad *udf_get_fileshortad(uint8_t *ptr, int maxoffset, uint32_t *offset,
int inc)
{
short_ad *sa;
return NULL;
}
- if ((*offset < 0) || ((*offset + sizeof(short_ad)) > maxoffset))
- return NULL;
- else if ((sa = (short_ad *)ptr)->extLength == 0)
+ if ((*offset + sizeof(short_ad)) > maxoffset)
return NULL;
+ else {
+ sa = (short_ad *)ptr;
+ if (sa->extLength == 0)
+ return NULL;
+ }
if (inc)
*offset += sizeof(short_ad);
return sa;
}
-long_ad *udf_get_filelongad(uint8_t *ptr, int maxoffset, int *offset, int inc)
+long_ad *udf_get_filelongad(uint8_t *ptr, int maxoffset, uint32_t *offset, int inc)
{
long_ad *la;
return NULL;
}
- if ((*offset < 0) || ((*offset + sizeof(long_ad)) > maxoffset))
- return NULL;
- else if ((la = (long_ad *)ptr)->extLength == 0)
+ if ((*offset + sizeof(long_ad)) > maxoffset)
return NULL;
+ else {
+ la = (long_ad *)ptr;
+ if (la->extLength == 0)
+ return NULL;
+ }
if (inc)
*offset += sizeof(long_ad);
{
struct inode *inode = page->mapping->host;
char *kaddr;
+ struct udf_inode_info *iinfo = UDF_I(inode);
BUG_ON(!PageLocked(page));
kaddr = kmap(page);
memset(kaddr, 0, PAGE_CACHE_SIZE);
- memcpy(kaddr, UDF_I_DATA(inode) + UDF_I_LENEATTR(inode), inode->i_size);
+ memcpy(kaddr, iinfo->i_ext.i_data + iinfo->i_lenEAttr, inode->i_size);
flush_dcache_page(page);
SetPageUptodate(page);
kunmap(page);
return 0;
}
-static int udf_adinicb_writepage(struct page *page, struct writeback_control *wbc)
+static int udf_adinicb_writepage(struct page *page,
+ struct writeback_control *wbc)
{
struct inode *inode = page->mapping->host;
char *kaddr;
+ struct udf_inode_info *iinfo = UDF_I(inode);
BUG_ON(!PageLocked(page));
kaddr = kmap(page);
- memcpy(UDF_I_DATA(inode) + UDF_I_LENEATTR(inode), kaddr, inode->i_size);
+ memcpy(iinfo->i_ext.i_data + iinfo->i_lenEAttr, kaddr, inode->i_size);
mark_inode_dirty(inode);
SetPageUptodate(page);
kunmap(page);
struct inode *inode = mapping->host;
unsigned offset = pos & (PAGE_CACHE_SIZE - 1);
char *kaddr;
+ struct udf_inode_info *iinfo = UDF_I(inode);
kaddr = kmap_atomic(page, KM_USER0);
- memcpy(UDF_I_DATA(inode) + UDF_I_LENEATTR(inode) + offset,
+ memcpy(iinfo->i_ext.i_data + iinfo->i_lenEAttr + offset,
kaddr + offset, copied);
kunmap_atomic(kaddr, KM_USER0);
struct inode *inode = file->f_path.dentry->d_inode;
int err, pos;
size_t count = iocb->ki_left;
+ struct udf_inode_info *iinfo = UDF_I(inode);
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB) {
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
if (file->f_flags & O_APPEND)
pos = inode->i_size;
else
pos = ppos;
- if (inode->i_sb->s_blocksize < (udf_file_entry_alloc_offset(inode) +
+ if (inode->i_sb->s_blocksize <
+ (udf_file_entry_alloc_offset(inode) +
pos + count)) {
udf_expand_file_adinicb(inode, pos + count, &err);
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB) {
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
udf_debug("udf_expand_adinicb: err=%d\n", err);
return err;
}
} else {
if (pos + count > inode->i_size)
- UDF_I_LENALLOC(inode) = pos + count;
+ iinfo->i_lenAlloc = pos + count;
else
- UDF_I_LENALLOC(inode) = inode->i_size;
+ iinfo->i_lenAlloc = inode->i_size;
}
}
switch (cmd) {
case UDF_GETVOLIDENT:
- return copy_to_user((char __user *)arg,
- UDF_SB_VOLIDENT(inode->i_sb), 32) ? -EFAULT : 0;
+ if (copy_to_user((char __user *)arg,
+ UDF_SB(inode->i_sb)->s_volume_ident, 32))
+ return -EFAULT;
+ else
+ return 0;
case UDF_RELOCATE_BLOCKS:
if (!capable(CAP_SYS_ADMIN))
return -EACCES;
if (get_user(old_block, (long __user *)arg))
return -EFAULT;
- if ((result = udf_relocate_blocks(inode->i_sb,
- old_block, &new_block)) == 0)
+ result = udf_relocate_blocks(inode->i_sb,
+ old_block, &new_block);
+ if (result == 0)
result = put_user(new_block, (long __user *)arg);
return result;
case UDF_GETEASIZE:
- result = put_user(UDF_I_LENEATTR(inode), (int __user *)arg);
+ result = put_user(UDF_I(inode)->i_lenEAttr, (int __user *)arg);
break;
case UDF_GETEABLOCK:
- result = copy_to_user((char __user *)arg, UDF_I_DATA(inode),
- UDF_I_LENEATTR(inode)) ? -EFAULT : 0;
+ result = copy_to_user((char __user *)arg,
+ UDF_I(inode)->i_ext.i_data,
+ UDF_I(inode)->i_lenEAttr) ? -EFAULT : 0;
break;
}
clear_inode(inode);
mutex_lock(&sbi->s_alloc_mutex);
- if (sbi->s_lvidbh) {
+ if (sbi->s_lvid_bh) {
+ struct logicalVolIntegrityDescImpUse *lvidiu =
+ udf_sb_lvidiu(sbi);
if (S_ISDIR(inode->i_mode))
- UDF_SB_LVIDIU(sb)->numDirs =
- cpu_to_le32(le32_to_cpu(UDF_SB_LVIDIU(sb)->numDirs) - 1);
+ lvidiu->numDirs =
+ cpu_to_le32(le32_to_cpu(lvidiu->numDirs) - 1);
else
- UDF_SB_LVIDIU(sb)->numFiles =
- cpu_to_le32(le32_to_cpu(UDF_SB_LVIDIU(sb)->numFiles) - 1);
+ lvidiu->numFiles =
+ cpu_to_le32(le32_to_cpu(lvidiu->numFiles) - 1);
- mark_buffer_dirty(sbi->s_lvidbh);
+ mark_buffer_dirty(sbi->s_lvid_bh);
}
mutex_unlock(&sbi->s_alloc_mutex);
- udf_free_blocks(sb, NULL, UDF_I_LOCATION(inode), 0, 1);
+ udf_free_blocks(sb, NULL, UDF_I(inode)->i_location, 0, 1);
}
struct inode *udf_new_inode(struct inode *dir, int mode, int *err)
struct udf_sb_info *sbi = UDF_SB(sb);
struct inode *inode;
int block;
- uint32_t start = UDF_I_LOCATION(dir).logicalBlockNum;
+ uint32_t start = UDF_I(dir)->i_location.logicalBlockNum;
+ struct udf_inode_info *iinfo;
+ struct udf_inode_info *dinfo = UDF_I(dir);
inode = new_inode(sb);
}
*err = -ENOSPC;
- UDF_I_UNIQUE(inode) = 0;
- UDF_I_LENEXTENTS(inode) = 0;
- UDF_I_NEXT_ALLOC_BLOCK(inode) = 0;
- UDF_I_NEXT_ALLOC_GOAL(inode) = 0;
- UDF_I_STRAT4096(inode) = 0;
+ iinfo = UDF_I(inode);
+ iinfo->i_unique = 0;
+ iinfo->i_lenExtents = 0;
+ iinfo->i_next_alloc_block = 0;
+ iinfo->i_next_alloc_goal = 0;
+ iinfo->i_strat4096 = 0;
- block = udf_new_block(dir->i_sb, NULL, UDF_I_LOCATION(dir).partitionReferenceNum,
+ block = udf_new_block(dir->i_sb, NULL,
+ dinfo->i_location.partitionReferenceNum,
start, err);
if (*err) {
iput(inode);
}
mutex_lock(&sbi->s_alloc_mutex);
- if (UDF_SB_LVIDBH(sb)) {
+ if (sbi->s_lvid_bh) {
+ struct logicalVolIntegrityDesc *lvid =
+ (struct logicalVolIntegrityDesc *)
+ sbi->s_lvid_bh->b_data;
+ struct logicalVolIntegrityDescImpUse *lvidiu =
+ udf_sb_lvidiu(sbi);
struct logicalVolHeaderDesc *lvhd;
uint64_t uniqueID;
- lvhd = (struct logicalVolHeaderDesc *)(UDF_SB_LVID(sb)->logicalVolContentsUse);
+ lvhd = (struct logicalVolHeaderDesc *)
+ (lvid->logicalVolContentsUse);
if (S_ISDIR(mode))
- UDF_SB_LVIDIU(sb)->numDirs =
- cpu_to_le32(le32_to_cpu(UDF_SB_LVIDIU(sb)->numDirs) + 1);
+ lvidiu->numDirs =
+ cpu_to_le32(le32_to_cpu(lvidiu->numDirs) + 1);
else
- UDF_SB_LVIDIU(sb)->numFiles =
- cpu_to_le32(le32_to_cpu(UDF_SB_LVIDIU(sb)->numFiles) + 1);
- UDF_I_UNIQUE(inode) = uniqueID = le64_to_cpu(lvhd->uniqueID);
+ lvidiu->numFiles =
+ cpu_to_le32(le32_to_cpu(lvidiu->numFiles) + 1);
+ iinfo->i_unique = uniqueID = le64_to_cpu(lvhd->uniqueID);
if (!(++uniqueID & 0x00000000FFFFFFFFUL))
uniqueID += 16;
lvhd->uniqueID = cpu_to_le64(uniqueID);
- mark_buffer_dirty(UDF_SB_LVIDBH(sb));
+ mark_buffer_dirty(sbi->s_lvid_bh);
}
inode->i_mode = mode;
inode->i_uid = current->fsuid;
inode->i_gid = current->fsgid;
}
- UDF_I_LOCATION(inode).logicalBlockNum = block;
- UDF_I_LOCATION(inode).partitionReferenceNum = UDF_I_LOCATION(dir).partitionReferenceNum;
- inode->i_ino = udf_get_lb_pblock(sb, UDF_I_LOCATION(inode), 0);
+ iinfo->i_location.logicalBlockNum = block;
+ iinfo->i_location.partitionReferenceNum =
+ dinfo->i_location.partitionReferenceNum;
+ inode->i_ino = udf_get_lb_pblock(sb, iinfo->i_location, 0);
inode->i_blocks = 0;
- UDF_I_LENEATTR(inode) = 0;
- UDF_I_LENALLOC(inode) = 0;
- UDF_I_USE(inode) = 0;
+ iinfo->i_lenEAttr = 0;
+ iinfo->i_lenAlloc = 0;
+ iinfo->i_use = 0;
if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_EXTENDED_FE)) {
- UDF_I_EFE(inode) = 1;
- UDF_UPDATE_UDFREV(inode->i_sb, UDF_VERS_USE_EXTENDED_FE);
- UDF_I_DATA(inode) = kzalloc(inode->i_sb->s_blocksize - sizeof(struct extendedFileEntry), GFP_KERNEL);
+ iinfo->i_efe = 1;
+ if (UDF_VERS_USE_EXTENDED_FE > sbi->s_udfrev)
+ sbi->s_udfrev = UDF_VERS_USE_EXTENDED_FE;
+ iinfo->i_ext.i_data = kzalloc(inode->i_sb->s_blocksize -
+ sizeof(struct extendedFileEntry),
+ GFP_KERNEL);
} else {
- UDF_I_EFE(inode) = 0;
- UDF_I_DATA(inode) = kzalloc(inode->i_sb->s_blocksize - sizeof(struct fileEntry), GFP_KERNEL);
+ iinfo->i_efe = 0;
+ iinfo->i_ext.i_data = kzalloc(inode->i_sb->s_blocksize -
+ sizeof(struct fileEntry),
+ GFP_KERNEL);
}
- if (!UDF_I_DATA(inode)) {
+ if (!iinfo->i_ext.i_data) {
iput(inode);
*err = -ENOMEM;
mutex_unlock(&sbi->s_alloc_mutex);
return NULL;
}
if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_AD_IN_ICB))
- UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_IN_ICB;
+ iinfo->i_alloc_type = ICBTAG_FLAG_AD_IN_ICB;
else if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_SHORT_AD))
- UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_SHORT;
+ iinfo->i_alloc_type = ICBTAG_FLAG_AD_SHORT;
else
- UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_LONG;
+ iinfo->i_alloc_type = ICBTAG_FLAG_AD_LONG;
inode->i_mtime = inode->i_atime = inode->i_ctime =
- UDF_I_CRTIME(inode) = current_fs_time(inode->i_sb);
+ iinfo->i_crtime = current_fs_time(inode->i_sb);
insert_inode_hash(inode);
mark_inode_dirty(inode);
mutex_unlock(&sbi->s_alloc_mutex);
* 10/04/98 dgb Added rudimentary directory functions
* 10/07/98 Fully working udf_block_map! It works!
* 11/25/98 bmap altered to better support extents
- * 12/06/98 blf partition support in udf_iget, udf_block_map and udf_read_inode
+ * 12/06/98 blf partition support in udf_iget, udf_block_map
+ * and udf_read_inode
* 12/12/98 rewrote udf_block_map to handle next extents and descs across
* block boundaries (which is not actually allowed)
* 12/20/98 added support for strategy 4096
static void udf_fill_inode(struct inode *, struct buffer_head *);
static int udf_alloc_i_data(struct inode *inode, size_t size);
static struct buffer_head *inode_getblk(struct inode *, sector_t, int *,
- long *, int *);
+ sector_t *, int *);
static int8_t udf_insert_aext(struct inode *, struct extent_position,
kernel_lb_addr, uint32_t);
static void udf_split_extents(struct inode *, int *, int, int,
*/
void udf_clear_inode(struct inode *inode)
{
+ struct udf_inode_info *iinfo;
if (!(inode->i_sb->s_flags & MS_RDONLY)) {
lock_kernel();
/* Discard preallocation for directories, symlinks, etc. */
udf_discard_prealloc(inode);
udf_truncate_tail_extent(inode);
unlock_kernel();
- write_inode_now(inode, 1);
+ write_inode_now(inode, 0);
}
- kfree(UDF_I_DATA(inode));
- UDF_I_DATA(inode) = NULL;
+ iinfo = UDF_I(inode);
+ kfree(iinfo->i_ext.i_data);
+ iinfo->i_ext.i_data = NULL;
}
static int udf_writepage(struct page *page, struct writeback_control *wbc)
{
struct page *page;
char *kaddr;
+ struct udf_inode_info *iinfo = UDF_I(inode);
struct writeback_control udf_wbc = {
.sync_mode = WB_SYNC_NONE,
.nr_to_write = 1,
/* from now on we have normal address_space methods */
inode->i_data.a_ops = &udf_aops;
- if (!UDF_I_LENALLOC(inode)) {
+ if (!iinfo->i_lenAlloc) {
if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_SHORT_AD))
- UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_SHORT;
+ iinfo->i_alloc_type = ICBTAG_FLAG_AD_SHORT;
else
- UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_LONG;
+ iinfo->i_alloc_type = ICBTAG_FLAG_AD_LONG;
mark_inode_dirty(inode);
return;
}
if (!PageUptodate(page)) {
kaddr = kmap(page);
- memset(kaddr + UDF_I_LENALLOC(inode), 0x00,
- PAGE_CACHE_SIZE - UDF_I_LENALLOC(inode));
- memcpy(kaddr, UDF_I_DATA(inode) + UDF_I_LENEATTR(inode),
- UDF_I_LENALLOC(inode));
+ memset(kaddr + iinfo->i_lenAlloc, 0x00,
+ PAGE_CACHE_SIZE - iinfo->i_lenAlloc);
+ memcpy(kaddr, iinfo->i_ext.i_data + iinfo->i_lenEAttr,
+ iinfo->i_lenAlloc);
flush_dcache_page(page);
SetPageUptodate(page);
kunmap(page);
}
- memset(UDF_I_DATA(inode) + UDF_I_LENEATTR(inode), 0x00,
- UDF_I_LENALLOC(inode));
- UDF_I_LENALLOC(inode) = 0;
+ memset(iinfo->i_ext.i_data + iinfo->i_lenEAttr, 0x00,
+ iinfo->i_lenAlloc);
+ iinfo->i_lenAlloc = 0;
if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_SHORT_AD))
- UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_SHORT;
+ iinfo->i_alloc_type = ICBTAG_FLAG_AD_SHORT;
else
- UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_LONG;
+ iinfo->i_alloc_type = ICBTAG_FLAG_AD_LONG;
inode->i_data.a_ops->writepage(page, &udf_wbc);
page_cache_release(page);
struct extent_position epos;
struct udf_fileident_bh sfibh, dfibh;
- loff_t f_pos = udf_ext0_offset(inode) >> 2;
- int size = (udf_ext0_offset(inode) + inode->i_size) >> 2;
+ loff_t f_pos = udf_ext0_offset(inode);
+ int size = udf_ext0_offset(inode) + inode->i_size;
struct fileIdentDesc cfi, *sfi, *dfi;
+ struct udf_inode_info *iinfo = UDF_I(inode);
if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_SHORT_AD))
alloctype = ICBTAG_FLAG_AD_SHORT;
alloctype = ICBTAG_FLAG_AD_LONG;
if (!inode->i_size) {
- UDF_I_ALLOCTYPE(inode) = alloctype;
+ iinfo->i_alloc_type = alloctype;
mark_inode_dirty(inode);
return NULL;
}
/* alloc block, and copy data to it */
*block = udf_new_block(inode->i_sb, inode,
- UDF_I_LOCATION(inode).partitionReferenceNum,
- UDF_I_LOCATION(inode).logicalBlockNum, err);
+ iinfo->i_location.partitionReferenceNum,
+ iinfo->i_location.logicalBlockNum, err);
if (!(*block))
return NULL;
newblock = udf_get_pblock(inode->i_sb, *block,
- UDF_I_LOCATION(inode).partitionReferenceNum, 0);
+ iinfo->i_location.partitionReferenceNum,
+ 0);
if (!newblock)
return NULL;
dbh = udf_tgetblk(inode->i_sb, newblock);
unlock_buffer(dbh);
mark_buffer_dirty_inode(dbh, inode);
- sfibh.soffset = sfibh.eoffset = (f_pos & ((inode->i_sb->s_blocksize - 1) >> 2)) << 2;
+ sfibh.soffset = sfibh.eoffset =
+ f_pos & (inode->i_sb->s_blocksize - 1);
sfibh.sbh = sfibh.ebh = NULL;
dfibh.soffset = dfibh.eoffset = 0;
dfibh.sbh = dfibh.ebh = dbh;
- while ((f_pos < size)) {
- UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_IN_ICB;
- sfi = udf_fileident_read(inode, &f_pos, &sfibh, &cfi, NULL, NULL, NULL, NULL);
+ while (f_pos < size) {
+ iinfo->i_alloc_type = ICBTAG_FLAG_AD_IN_ICB;
+ sfi = udf_fileident_read(inode, &f_pos, &sfibh, &cfi, NULL,
+ NULL, NULL, NULL);
if (!sfi) {
brelse(dbh);
return NULL;
}
- UDF_I_ALLOCTYPE(inode) = alloctype;
+ iinfo->i_alloc_type = alloctype;
sfi->descTag.tagLocation = cpu_to_le32(*block);
dfibh.soffset = dfibh.eoffset;
dfibh.eoffset += (sfibh.eoffset - sfibh.soffset);
dfi = (struct fileIdentDesc *)(dbh->b_data + dfibh.soffset);
if (udf_write_fi(inode, sfi, dfi, &dfibh, sfi->impUse,
- sfi->fileIdent + le16_to_cpu(sfi->lengthOfImpUse))) {
- UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_IN_ICB;
+ sfi->fileIdent +
+ le16_to_cpu(sfi->lengthOfImpUse))) {
+ iinfo->i_alloc_type = ICBTAG_FLAG_AD_IN_ICB;
brelse(dbh);
return NULL;
}
}
mark_buffer_dirty_inode(dbh, inode);
- memset(UDF_I_DATA(inode) + UDF_I_LENEATTR(inode), 0, UDF_I_LENALLOC(inode));
- UDF_I_LENALLOC(inode) = 0;
+ memset(iinfo->i_ext.i_data + iinfo->i_lenEAttr, 0,
+ iinfo->i_lenAlloc);
+ iinfo->i_lenAlloc = 0;
eloc.logicalBlockNum = *block;
- eloc.partitionReferenceNum = UDF_I_LOCATION(inode).partitionReferenceNum;
- elen = inode->i_size;
- UDF_I_LENEXTENTS(inode) = elen;
+ eloc.partitionReferenceNum =
+ iinfo->i_location.partitionReferenceNum;
+ elen = inode->i_sb->s_blocksize;
+ iinfo->i_lenExtents = elen;
epos.bh = NULL;
- epos.block = UDF_I_LOCATION(inode);
+ epos.block = iinfo->i_location;
epos.offset = udf_file_entry_alloc_offset(inode);
udf_add_aext(inode, &epos, eloc, elen, 0);
/* UniqueID stuff */
{
int err, new;
struct buffer_head *bh;
- unsigned long phys;
+ sector_t phys = 0;
+ struct udf_inode_info *iinfo;
if (!create) {
phys = udf_block_map(inode, block);
if (block < 0)
goto abort_negative;
- if (block == UDF_I_NEXT_ALLOC_BLOCK(inode) + 1) {
- UDF_I_NEXT_ALLOC_BLOCK(inode)++;
- UDF_I_NEXT_ALLOC_GOAL(inode)++;
+ iinfo = UDF_I(inode);
+ if (block == iinfo->i_next_alloc_block + 1) {
+ iinfo->i_next_alloc_block++;
+ iinfo->i_next_alloc_goal++;
}
err = 0;
/* Extend the file by 'blocks' blocks, return the number of extents added */
int udf_extend_file(struct inode *inode, struct extent_position *last_pos,
- kernel_long_ad * last_ext, sector_t blocks)
+ kernel_long_ad *last_ext, sector_t blocks)
{
sector_t add;
int count = 0, fake = !(last_ext->extLength & UDF_EXTENT_LENGTH_MASK);
struct super_block *sb = inode->i_sb;
kernel_lb_addr prealloc_loc = {};
int prealloc_len = 0;
+ struct udf_inode_info *iinfo;
/* The previous extent is fake and we should not extend by anything
* - there's nothing to do... */
if (!blocks && fake)
return 0;
+ iinfo = UDF_I(inode);
/* Round the last extent up to a multiple of block size */
if (last_ext->extLength & (sb->s_blocksize - 1)) {
last_ext->extLength =
(last_ext->extLength & UDF_EXTENT_FLAG_MASK) |
(((last_ext->extLength & UDF_EXTENT_LENGTH_MASK) +
sb->s_blocksize - 1) & ~(sb->s_blocksize - 1));
- UDF_I_LENEXTENTS(inode) =
- (UDF_I_LENEXTENTS(inode) + sb->s_blocksize - 1) &
+ iinfo->i_lenExtents =
+ (iinfo->i_lenExtents + sb->s_blocksize - 1) &
~(sb->s_blocksize - 1);
}
/* Last extent are just preallocated blocks? */
- if ((last_ext->extLength & UDF_EXTENT_FLAG_MASK) == EXT_NOT_RECORDED_ALLOCATED) {
+ if ((last_ext->extLength & UDF_EXTENT_FLAG_MASK) ==
+ EXT_NOT_RECORDED_ALLOCATED) {
/* Save the extent so that we can reattach it to the end */
prealloc_loc = last_ext->extLocation;
prealloc_len = last_ext->extLength;
last_ext->extLength = EXT_NOT_RECORDED_NOT_ALLOCATED |
(last_ext->extLength & UDF_EXTENT_LENGTH_MASK);
last_ext->extLocation.logicalBlockNum = 0;
- last_ext->extLocation.partitionReferenceNum = 0;
+ last_ext->extLocation.partitionReferenceNum = 0;
}
/* Can we merge with the previous extent? */
- if ((last_ext->extLength & UDF_EXTENT_FLAG_MASK) == EXT_NOT_RECORDED_NOT_ALLOCATED) {
- add = ((1 << 30) - sb->s_blocksize - (last_ext->extLength &
- UDF_EXTENT_LENGTH_MASK)) >> sb->s_blocksize_bits;
+ if ((last_ext->extLength & UDF_EXTENT_FLAG_MASK) ==
+ EXT_NOT_RECORDED_NOT_ALLOCATED) {
+ add = ((1 << 30) - sb->s_blocksize -
+ (last_ext->extLength & UDF_EXTENT_LENGTH_MASK)) >>
+ sb->s_blocksize_bits;
if (add > blocks)
add = blocks;
blocks -= add;
udf_add_aext(inode, last_pos, last_ext->extLocation,
last_ext->extLength, 1);
count++;
- } else {
- udf_write_aext(inode, last_pos, last_ext->extLocation, last_ext->extLength, 1);
- }
+ } else
+ udf_write_aext(inode, last_pos, last_ext->extLocation,
+ last_ext->extLength, 1);
/* Managed to do everything necessary? */
if (!blocks)
/* All further extents will be NOT_RECORDED_NOT_ALLOCATED */
last_ext->extLocation.logicalBlockNum = 0;
- last_ext->extLocation.partitionReferenceNum = 0;
+ last_ext->extLocation.partitionReferenceNum = 0;
add = (1 << (30-sb->s_blocksize_bits)) - 1;
- last_ext->extLength = EXT_NOT_RECORDED_NOT_ALLOCATED | (add << sb->s_blocksize_bits);
+ last_ext->extLength = EXT_NOT_RECORDED_NOT_ALLOCATED |
+ (add << sb->s_blocksize_bits);
/* Create enough extents to cover the whole hole */
while (blocks > add) {
out:
/* Do we have some preallocated blocks saved? */
if (prealloc_len) {
- if (udf_add_aext(inode, last_pos, prealloc_loc, prealloc_len, 1) == -1)
+ if (udf_add_aext(inode, last_pos, prealloc_loc,
+ prealloc_len, 1) == -1)
return -1;
last_ext->extLocation = prealloc_loc;
last_ext->extLength = prealloc_len;
}
/* last_pos should point to the last written extent... */
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
last_pos->offset -= sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
+ else if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
last_pos->offset -= sizeof(long_ad);
else
return -1;
}
static struct buffer_head *inode_getblk(struct inode *inode, sector_t block,
- int *err, long *phys, int *new)
+ int *err, sector_t *phys, int *new)
{
static sector_t last_block;
struct buffer_head *result = NULL;
uint32_t newblocknum, newblock;
sector_t offset = 0;
int8_t etype;
- int goal = 0, pgoal = UDF_I_LOCATION(inode).logicalBlockNum;
+ struct udf_inode_info *iinfo = UDF_I(inode);
+ int goal = 0, pgoal = iinfo->i_location.logicalBlockNum;
int lastblock = 0;
prev_epos.offset = udf_file_entry_alloc_offset(inode);
- prev_epos.block = UDF_I_LOCATION(inode);
+ prev_epos.block = iinfo->i_location;
prev_epos.bh = NULL;
cur_epos = next_epos = prev_epos;
b_off = (loff_t)block << inode->i_sb->s_blocksize_bits;
prev_epos.offset = cur_epos.offset;
cur_epos.offset = next_epos.offset;
- if ((etype = udf_next_aext(inode, &next_epos, &eloc, &elen, 1)) == -1)
+ etype = udf_next_aext(inode, &next_epos, &eloc, &elen, 1);
+ if (etype == -1)
break;
c = !c;
startnum = 1;
} else {
/* Create a fake extent when there's not one */
- memset(&laarr[0].extLocation, 0x00, sizeof(kernel_lb_addr));
+ memset(&laarr[0].extLocation, 0x00,
+ sizeof(kernel_lb_addr));
laarr[0].extLength = EXT_NOT_RECORDED_NOT_ALLOCATED;
- /* Will udf_extend_file() create real extent from a fake one? */
+ /* Will udf_extend_file() create real extent from
+ a fake one? */
startnum = (offset > 0);
}
/* Create extents for the hole between EOF and offset */
offset = 0;
count += ret;
/* We are not covered by a preallocated extent? */
- if ((laarr[0].extLength & UDF_EXTENT_FLAG_MASK) != EXT_NOT_RECORDED_ALLOCATED) {
+ if ((laarr[0].extLength & UDF_EXTENT_FLAG_MASK) !=
+ EXT_NOT_RECORDED_ALLOCATED) {
/* Is there any real extent? - otherwise we overwrite
* the fake one... */
if (count)
c = !c;
laarr[c].extLength = EXT_NOT_RECORDED_NOT_ALLOCATED |
inode->i_sb->s_blocksize;
- memset(&laarr[c].extLocation, 0x00, sizeof(kernel_lb_addr));
+ memset(&laarr[c].extLocation, 0x00,
+ sizeof(kernel_lb_addr));
count++;
endnum++;
}
} else {
endnum = startnum = ((count > 2) ? 2 : count);
- /* if the current extent is in position 0, swap it with the previous */
+ /* if the current extent is in position 0,
+ swap it with the previous */
if (!c && count != 1) {
laarr[2] = laarr[0];
laarr[0] = laarr[1];
c = 1;
}
- /* if the current block is located in an extent, read the next extent */
- if ((etype = udf_next_aext(inode, &next_epos, &eloc, &elen, 0)) != -1) {
+ /* if the current block is located in an extent,
+ read the next extent */
+ etype = udf_next_aext(inode, &next_epos, &eloc, &elen, 0);
+ if (etype != -1) {
laarr[c + 1].extLength = (etype << 30) | elen;
laarr[c + 1].extLocation = eloc;
count++;
startnum++;
endnum++;
- } else {
+ } else
lastblock = 1;
- }
}
/* if the current extent is not recorded but allocated, get the
* block in the extent corresponding to the requested block */
- if ((laarr[c].extLength >> 30) == (EXT_NOT_RECORDED_ALLOCATED >> 30)) {
+ if ((laarr[c].extLength >> 30) == (EXT_NOT_RECORDED_ALLOCATED >> 30))
newblocknum = laarr[c].extLocation.logicalBlockNum + offset;
- } else { /* otherwise, allocate a new block */
- if (UDF_I_NEXT_ALLOC_BLOCK(inode) == block)
- goal = UDF_I_NEXT_ALLOC_GOAL(inode);
+ else { /* otherwise, allocate a new block */
+ if (iinfo->i_next_alloc_block == block)
+ goal = iinfo->i_next_alloc_goal;
if (!goal) {
- if (!(goal = pgoal))
- goal = UDF_I_LOCATION(inode).logicalBlockNum + 1;
+ if (!(goal = pgoal)) /* XXX: what was intended here? */
+ goal = iinfo->i_location.logicalBlockNum + 1;
}
- if (!(newblocknum = udf_new_block(inode->i_sb, inode,
- UDF_I_LOCATION(inode).partitionReferenceNum,
- goal, err))) {
+ newblocknum = udf_new_block(inode->i_sb, inode,
+ iinfo->i_location.partitionReferenceNum,
+ goal, err);
+ if (!newblocknum) {
brelse(prev_epos.bh);
*err = -ENOSPC;
return NULL;
}
- UDF_I_LENEXTENTS(inode) += inode->i_sb->s_blocksize;
+ iinfo->i_lenExtents += inode->i_sb->s_blocksize;
}
- /* if the extent the requsted block is located in contains multiple blocks,
- * split the extent into at most three extents. blocks prior to requested
- * block, requested block, and blocks after requested block */
+ /* if the extent the requsted block is located in contains multiple
+ * blocks, split the extent into at most three extents. blocks prior
+ * to requested block, requested block, and blocks after requested
+ * block */
udf_split_extents(inode, &c, offset, newblocknum, laarr, &endnum);
#ifdef UDF_PREALLOCATE
brelse(prev_epos.bh);
- if (!(newblock = udf_get_pblock(inode->i_sb, newblocknum,
- UDF_I_LOCATION(inode).partitionReferenceNum, 0))) {
+ newblock = udf_get_pblock(inode->i_sb, newblocknum,
+ iinfo->i_location.partitionReferenceNum, 0);
+ if (!newblock)
return NULL;
- }
*phys = newblock;
*err = 0;
*new = 1;
- UDF_I_NEXT_ALLOC_BLOCK(inode) = block;
- UDF_I_NEXT_ALLOC_GOAL(inode) = newblocknum;
+ iinfo->i_next_alloc_block = block;
+ iinfo->i_next_alloc_goal = newblocknum;
inode->i_ctime = current_fs_time(inode->i_sb);
if (IS_SYNC(inode))
kernel_long_ad laarr[EXTENT_MERGE_SIZE],
int *endnum)
{
+ unsigned long blocksize = inode->i_sb->s_blocksize;
+ unsigned char blocksize_bits = inode->i_sb->s_blocksize_bits;
+
if ((laarr[*c].extLength >> 30) == (EXT_NOT_RECORDED_ALLOCATED >> 30) ||
- (laarr[*c].extLength >> 30) == (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30)) {
+ (laarr[*c].extLength >> 30) ==
+ (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30)) {
int curr = *c;
int blen = ((laarr[curr].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) >> inode->i_sb->s_blocksize_bits;
+ blocksize - 1) >> blocksize_bits;
int8_t etype = (laarr[curr].extLength >> 30);
- if (blen == 1) {
+ if (blen == 1)
;
- } else if (!offset || blen == offset + 1) {
+ else if (!offset || blen == offset + 1) {
laarr[curr + 2] = laarr[curr + 1];
laarr[curr + 1] = laarr[curr];
} else {
if (offset) {
if (etype == (EXT_NOT_RECORDED_ALLOCATED >> 30)) {
- udf_free_blocks(inode->i_sb, inode, laarr[curr].extLocation, 0, offset);
- laarr[curr].extLength = EXT_NOT_RECORDED_NOT_ALLOCATED |
- (offset << inode->i_sb->s_blocksize_bits);
+ udf_free_blocks(inode->i_sb, inode,
+ laarr[curr].extLocation,
+ 0, offset);
+ laarr[curr].extLength =
+ EXT_NOT_RECORDED_NOT_ALLOCATED |
+ (offset << blocksize_bits);
laarr[curr].extLocation.logicalBlockNum = 0;
- laarr[curr].extLocation.partitionReferenceNum = 0;
- } else {
+ laarr[curr].extLocation.
+ partitionReferenceNum = 0;
+ } else
laarr[curr].extLength = (etype << 30) |
- (offset << inode->i_sb->s_blocksize_bits);
- }
+ (offset << blocksize_bits);
curr++;
(*c)++;
(*endnum)++;
laarr[curr].extLocation.logicalBlockNum = newblocknum;
if (etype == (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30))
laarr[curr].extLocation.partitionReferenceNum =
- UDF_I_LOCATION(inode).partitionReferenceNum;
+ UDF_I(inode)->i_location.partitionReferenceNum;
laarr[curr].extLength = EXT_RECORDED_ALLOCATED |
- inode->i_sb->s_blocksize;
+ blocksize;
curr++;
if (blen != offset + 1) {
if (etype == (EXT_NOT_RECORDED_ALLOCATED >> 30))
- laarr[curr].extLocation.logicalBlockNum += (offset + 1);
+ laarr[curr].extLocation.logicalBlockNum +=
+ offset + 1;
laarr[curr].extLength = (etype << 30) |
- ((blen - (offset + 1)) << inode->i_sb->s_blocksize_bits);
+ ((blen - (offset + 1)) << blocksize_bits);
curr++;
(*endnum)++;
}
else
start = c;
} else {
- if ((laarr[c + 1].extLength >> 30) == (EXT_NOT_RECORDED_ALLOCATED >> 30)) {
+ if ((laarr[c + 1].extLength >> 30) ==
+ (EXT_NOT_RECORDED_ALLOCATED >> 30)) {
start = c + 1;
- length = currlength = (((laarr[c + 1].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) >> inode->i_sb->s_blocksize_bits);
- } else {
+ length = currlength =
+ (((laarr[c + 1].extLength &
+ UDF_EXTENT_LENGTH_MASK) +
+ inode->i_sb->s_blocksize - 1) >>
+ inode->i_sb->s_blocksize_bits);
+ } else
start = c;
- }
}
for (i = start + 1; i <= *endnum; i++) {
if (i == *endnum) {
if (lastblock)
length += UDF_DEFAULT_PREALLOC_BLOCKS;
- } else if ((laarr[i].extLength >> 30) == (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30)) {
- length += (((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) >> inode->i_sb->s_blocksize_bits);
- } else {
+ } else if ((laarr[i].extLength >> 30) ==
+ (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30)) {
+ length += (((laarr[i].extLength &
+ UDF_EXTENT_LENGTH_MASK) +
+ inode->i_sb->s_blocksize - 1) >>
+ inode->i_sb->s_blocksize_bits);
+ } else
break;
- }
}
if (length) {
int next = laarr[start].extLocation.logicalBlockNum +
(((laarr[start].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) >> inode->i_sb->s_blocksize_bits);
+ inode->i_sb->s_blocksize - 1) >>
+ inode->i_sb->s_blocksize_bits);
int numalloc = udf_prealloc_blocks(inode->i_sb, inode,
- laarr[start].extLocation.partitionReferenceNum,
- next, (UDF_DEFAULT_PREALLOC_BLOCKS > length ? length :
- UDF_DEFAULT_PREALLOC_BLOCKS) - currlength);
+ laarr[start].extLocation.partitionReferenceNum,
+ next, (UDF_DEFAULT_PREALLOC_BLOCKS > length ?
+ length : UDF_DEFAULT_PREALLOC_BLOCKS) -
+ currlength);
if (numalloc) {
- if (start == (c + 1)) {
+ if (start == (c + 1))
laarr[start].extLength +=
- (numalloc << inode->i_sb->s_blocksize_bits);
- } else {
+ (numalloc <<
+ inode->i_sb->s_blocksize_bits);
+ else {
memmove(&laarr[c + 2], &laarr[c + 1],
sizeof(long_ad) * (*endnum - (c + 1)));
(*endnum)++;
laarr[c + 1].extLocation.logicalBlockNum = next;
laarr[c + 1].extLocation.partitionReferenceNum =
- laarr[c].extLocation.partitionReferenceNum;
- laarr[c + 1].extLength = EXT_NOT_RECORDED_ALLOCATED |
- (numalloc << inode->i_sb->s_blocksize_bits);
+ laarr[c].extLocation.
+ partitionReferenceNum;
+ laarr[c + 1].extLength =
+ EXT_NOT_RECORDED_ALLOCATED |
+ (numalloc <<
+ inode->i_sb->s_blocksize_bits);
start = c + 1;
}
for (i = start + 1; numalloc && i < *endnum; i++) {
- int elen = ((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) >> inode->i_sb->s_blocksize_bits;
+ int elen = ((laarr[i].extLength &
+ UDF_EXTENT_LENGTH_MASK) +
+ inode->i_sb->s_blocksize - 1) >>
+ inode->i_sb->s_blocksize_bits;
if (elen > numalloc) {
laarr[i].extLength -=
- (numalloc << inode->i_sb->s_blocksize_bits);
+ (numalloc <<
+ inode->i_sb->s_blocksize_bits);
numalloc = 0;
} else {
numalloc -= elen;
if (*endnum > (i + 1))
- memmove(&laarr[i], &laarr[i + 1],
- sizeof(long_ad) * (*endnum - (i + 1)));
+ memmove(&laarr[i],
+ &laarr[i + 1],
+ sizeof(long_ad) *
+ (*endnum - (i + 1)));
i--;
(*endnum)--;
}
}
- UDF_I_LENEXTENTS(inode) += numalloc << inode->i_sb->s_blocksize_bits;
+ UDF_I(inode)->i_lenExtents +=
+ numalloc << inode->i_sb->s_blocksize_bits;
}
}
}
int *endnum)
{
int i;
+ unsigned long blocksize = inode->i_sb->s_blocksize;
+ unsigned char blocksize_bits = inode->i_sb->s_blocksize_bits;
for (i = 0; i < (*endnum - 1); i++) {
- if ((laarr[i].extLength >> 30) == (laarr[i + 1].extLength >> 30)) {
- if (((laarr[i].extLength >> 30) == (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30)) ||
- ((laarr[i + 1].extLocation.logicalBlockNum - laarr[i].extLocation.logicalBlockNum) ==
- (((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) >> inode->i_sb->s_blocksize_bits))) {
- if (((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
- (laarr[i + 1].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) & ~UDF_EXTENT_LENGTH_MASK) {
- laarr[i + 1].extLength = (laarr[i + 1].extLength -
- (laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
- UDF_EXTENT_LENGTH_MASK) & ~(inode->i_sb->s_blocksize - 1);
- laarr[i].extLength = (laarr[i].extLength & UDF_EXTENT_FLAG_MASK) +
- (UDF_EXTENT_LENGTH_MASK + 1) - inode->i_sb->s_blocksize;
- laarr[i + 1].extLocation.logicalBlockNum =
- laarr[i].extLocation.logicalBlockNum +
- ((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) >>
- inode->i_sb->s_blocksize_bits);
- } else {
- laarr[i].extLength = laarr[i + 1].extLength +
- (((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) & ~(inode->i_sb->s_blocksize - 1));
- if (*endnum > (i + 2))
- memmove(&laarr[i + 1], &laarr[i + 2],
- sizeof(long_ad) * (*endnum - (i + 2)));
- i--;
- (*endnum)--;
- }
+ kernel_long_ad *li /*l[i]*/ = &laarr[i];
+ kernel_long_ad *lip1 /*l[i plus 1]*/ = &laarr[i + 1];
+
+ if (((li->extLength >> 30) == (lip1->extLength >> 30)) &&
+ (((li->extLength >> 30) ==
+ (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30)) ||
+ ((lip1->extLocation.logicalBlockNum -
+ li->extLocation.logicalBlockNum) ==
+ (((li->extLength & UDF_EXTENT_LENGTH_MASK) +
+ blocksize - 1) >> blocksize_bits)))) {
+
+ if (((li->extLength & UDF_EXTENT_LENGTH_MASK) +
+ (lip1->extLength & UDF_EXTENT_LENGTH_MASK) +
+ blocksize - 1) & ~UDF_EXTENT_LENGTH_MASK) {
+ lip1->extLength = (lip1->extLength -
+ (li->extLength &
+ UDF_EXTENT_LENGTH_MASK) +
+ UDF_EXTENT_LENGTH_MASK) &
+ ~(blocksize - 1);
+ li->extLength = (li->extLength &
+ UDF_EXTENT_FLAG_MASK) +
+ (UDF_EXTENT_LENGTH_MASK + 1) -
+ blocksize;
+ lip1->extLocation.logicalBlockNum =
+ li->extLocation.logicalBlockNum +
+ ((li->extLength &
+ UDF_EXTENT_LENGTH_MASK) >>
+ blocksize_bits);
+ } else {
+ li->extLength = lip1->extLength +
+ (((li->extLength &
+ UDF_EXTENT_LENGTH_MASK) +
+ blocksize - 1) & ~(blocksize - 1));
+ if (*endnum > (i + 2))
+ memmove(&laarr[i + 1], &laarr[i + 2],
+ sizeof(long_ad) *
+ (*endnum - (i + 2)));
+ i--;
+ (*endnum)--;
}
- } else if (((laarr[i].extLength >> 30) == (EXT_NOT_RECORDED_ALLOCATED >> 30)) &&
- ((laarr[i + 1].extLength >> 30) == (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30))) {
- udf_free_blocks(inode->i_sb, inode, laarr[i].extLocation, 0,
- ((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) >> inode->i_sb->s_blocksize_bits);
- laarr[i].extLocation.logicalBlockNum = 0;
- laarr[i].extLocation.partitionReferenceNum = 0;
-
- if (((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
- (laarr[i + 1].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) & ~UDF_EXTENT_LENGTH_MASK) {
- laarr[i + 1].extLength = (laarr[i + 1].extLength -
- (laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
- UDF_EXTENT_LENGTH_MASK) & ~(inode->i_sb->s_blocksize - 1);
- laarr[i].extLength = (laarr[i].extLength & UDF_EXTENT_FLAG_MASK) +
- (UDF_EXTENT_LENGTH_MASK + 1) - inode->i_sb->s_blocksize;
+ } else if (((li->extLength >> 30) ==
+ (EXT_NOT_RECORDED_ALLOCATED >> 30)) &&
+ ((lip1->extLength >> 30) ==
+ (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30))) {
+ udf_free_blocks(inode->i_sb, inode, li->extLocation, 0,
+ ((li->extLength &
+ UDF_EXTENT_LENGTH_MASK) +
+ blocksize - 1) >> blocksize_bits);
+ li->extLocation.logicalBlockNum = 0;
+ li->extLocation.partitionReferenceNum = 0;
+
+ if (((li->extLength & UDF_EXTENT_LENGTH_MASK) +
+ (lip1->extLength & UDF_EXTENT_LENGTH_MASK) +
+ blocksize - 1) & ~UDF_EXTENT_LENGTH_MASK) {
+ lip1->extLength = (lip1->extLength -
+ (li->extLength &
+ UDF_EXTENT_LENGTH_MASK) +
+ UDF_EXTENT_LENGTH_MASK) &
+ ~(blocksize - 1);
+ li->extLength = (li->extLength &
+ UDF_EXTENT_FLAG_MASK) +
+ (UDF_EXTENT_LENGTH_MASK + 1) -
+ blocksize;
} else {
- laarr[i].extLength = laarr[i + 1].extLength +
- (((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) & ~(inode->i_sb->s_blocksize - 1));
+ li->extLength = lip1->extLength +
+ (((li->extLength &
+ UDF_EXTENT_LENGTH_MASK) +
+ blocksize - 1) & ~(blocksize - 1));
if (*endnum > (i + 2))
memmove(&laarr[i + 1], &laarr[i + 2],
- sizeof(long_ad) * (*endnum - (i + 2)));
+ sizeof(long_ad) *
+ (*endnum - (i + 2)));
i--;
(*endnum)--;
}
- } else if ((laarr[i].extLength >> 30) == (EXT_NOT_RECORDED_ALLOCATED >> 30)) {
- udf_free_blocks(inode->i_sb, inode, laarr[i].extLocation, 0,
- ((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
- inode->i_sb->s_blocksize - 1) >> inode->i_sb->s_blocksize_bits);
- laarr[i].extLocation.logicalBlockNum = 0;
- laarr[i].extLocation.partitionReferenceNum = 0;
- laarr[i].extLength = (laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) |
- EXT_NOT_RECORDED_NOT_ALLOCATED;
+ } else if ((li->extLength >> 30) ==
+ (EXT_NOT_RECORDED_ALLOCATED >> 30)) {
+ udf_free_blocks(inode->i_sb, inode,
+ li->extLocation, 0,
+ ((li->extLength &
+ UDF_EXTENT_LENGTH_MASK) +
+ blocksize - 1) >> blocksize_bits);
+ li->extLocation.logicalBlockNum = 0;
+ li->extLocation.partitionReferenceNum = 0;
+ li->extLength = (li->extLength &
+ UDF_EXTENT_LENGTH_MASK) |
+ EXT_NOT_RECORDED_NOT_ALLOCATED;
}
}
}
{
int offset;
int err;
+ struct udf_inode_info *iinfo;
if (!(S_ISREG(inode->i_mode) || S_ISDIR(inode->i_mode) ||
S_ISLNK(inode->i_mode)))
return;
lock_kernel();
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB) {
- if (inode->i_sb->s_blocksize < (udf_file_entry_alloc_offset(inode) +
- inode->i_size)) {
+ iinfo = UDF_I(inode);
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
+ if (inode->i_sb->s_blocksize <
+ (udf_file_entry_alloc_offset(inode) +
+ inode->i_size)) {
udf_expand_file_adinicb(inode, inode->i_size, &err);
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB) {
- inode->i_size = UDF_I_LENALLOC(inode);
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
+ inode->i_size = iinfo->i_lenAlloc;
unlock_kernel();
return;
- } else {
+ } else
udf_truncate_extents(inode);
- }
} else {
offset = inode->i_size & (inode->i_sb->s_blocksize - 1);
- memset(UDF_I_DATA(inode) + UDF_I_LENEATTR(inode) + offset, 0x00,
- inode->i_sb->s_blocksize - offset - udf_file_entry_alloc_offset(inode));
- UDF_I_LENALLOC(inode) = inode->i_size;
+ memset(iinfo->i_ext.i_data + iinfo->i_lenEAttr + offset,
+ 0x00, inode->i_sb->s_blocksize -
+ offset - udf_file_entry_alloc_offset(inode));
+ iinfo->i_lenAlloc = inode->i_size;
}
} else {
- block_truncate_page(inode->i_mapping, inode->i_size, udf_get_block);
+ block_truncate_page(inode->i_mapping, inode->i_size,
+ udf_get_block);
udf_truncate_extents(inode);
}
struct buffer_head *bh = NULL;
struct fileEntry *fe;
uint16_t ident;
+ struct udf_inode_info *iinfo = UDF_I(inode);
/*
* Set defaults, but the inode is still incomplete!
* i_nlink = 1
* i_op = NULL;
*/
- bh = udf_read_ptagged(inode->i_sb, UDF_I_LOCATION(inode), 0, &ident);
+ bh = udf_read_ptagged(inode->i_sb, iinfo->i_location, 0, &ident);
if (!bh) {
printk(KERN_ERR "udf: udf_read_inode(ino %ld) failed !bh\n",
inode->i_ino);
if (ident != TAG_IDENT_FE && ident != TAG_IDENT_EFE &&
ident != TAG_IDENT_USE) {
- printk(KERN_ERR "udf: udf_read_inode(ino %ld) failed ident=%d\n",
- inode->i_ino, ident);
+ printk(KERN_ERR "udf: udf_read_inode(ino %ld) "
+ "failed ident=%d\n", inode->i_ino, ident);
brelse(bh);
make_bad_inode(inode);
return;
fe = (struct fileEntry *)bh->b_data;
- if (le16_to_cpu(fe->icbTag.strategyType) == 4096) {
+ if (fe->icbTag.strategyType == cpu_to_le16(4096)) {
struct buffer_head *ibh = NULL, *nbh = NULL;
struct indirectEntry *ie;
- ibh = udf_read_ptagged(inode->i_sb, UDF_I_LOCATION(inode), 1, &ident);
+ ibh = udf_read_ptagged(inode->i_sb, iinfo->i_location, 1,
+ &ident);
if (ident == TAG_IDENT_IE) {
if (ibh) {
kernel_lb_addr loc;
loc = lelb_to_cpu(ie->indirectICB.extLocation);
if (ie->indirectICB.extLength &&
- (nbh = udf_read_ptagged(inode->i_sb, loc, 0, &ident))) {
+ (nbh = udf_read_ptagged(inode->i_sb, loc, 0,
+ &ident))) {
if (ident == TAG_IDENT_FE ||
ident == TAG_IDENT_EFE) {
- memcpy(&UDF_I_LOCATION(inode), &loc,
+ memcpy(&iinfo->i_location,
+ &loc,
sizeof(kernel_lb_addr));
brelse(bh);
brelse(ibh);
} else {
brelse(ibh);
}
- } else if (le16_to_cpu(fe->icbTag.strategyType) != 4) {
+ } else if (fe->icbTag.strategyType != cpu_to_le16(4)) {
printk(KERN_ERR "udf: unsupported strategy type: %d\n",
le16_to_cpu(fe->icbTag.strategyType));
brelse(bh);
time_t convtime;
long convtime_usec;
int offset;
+ struct udf_sb_info *sbi = UDF_SB(inode->i_sb);
+ struct udf_inode_info *iinfo = UDF_I(inode);
fe = (struct fileEntry *)bh->b_data;
efe = (struct extendedFileEntry *)bh->b_data;
- if (le16_to_cpu(fe->icbTag.strategyType) == 4)
- UDF_I_STRAT4096(inode) = 0;
- else /* if (le16_to_cpu(fe->icbTag.strategyType) == 4096) */
- UDF_I_STRAT4096(inode) = 1;
-
- UDF_I_ALLOCTYPE(inode) = le16_to_cpu(fe->icbTag.flags) & ICBTAG_FLAG_AD_MASK;
- UDF_I_UNIQUE(inode) = 0;
- UDF_I_LENEATTR(inode) = 0;
- UDF_I_LENEXTENTS(inode) = 0;
- UDF_I_LENALLOC(inode) = 0;
- UDF_I_NEXT_ALLOC_BLOCK(inode) = 0;
- UDF_I_NEXT_ALLOC_GOAL(inode) = 0;
- if (le16_to_cpu(fe->descTag.tagIdent) == TAG_IDENT_EFE) {
- UDF_I_EFE(inode) = 1;
- UDF_I_USE(inode) = 0;
- if (udf_alloc_i_data(inode, inode->i_sb->s_blocksize - sizeof(struct extendedFileEntry))) {
+ if (fe->icbTag.strategyType == cpu_to_le16(4))
+ iinfo->i_strat4096 = 0;
+ else /* if (fe->icbTag.strategyType == cpu_to_le16(4096)) */
+ iinfo->i_strat4096 = 1;
+
+ iinfo->i_alloc_type = le16_to_cpu(fe->icbTag.flags) &
+ ICBTAG_FLAG_AD_MASK;
+ iinfo->i_unique = 0;
+ iinfo->i_lenEAttr = 0;
+ iinfo->i_lenExtents = 0;
+ iinfo->i_lenAlloc = 0;
+ iinfo->i_next_alloc_block = 0;
+ iinfo->i_next_alloc_goal = 0;
+ if (fe->descTag.tagIdent == cpu_to_le16(TAG_IDENT_EFE)) {
+ iinfo->i_efe = 1;
+ iinfo->i_use = 0;
+ if (udf_alloc_i_data(inode, inode->i_sb->s_blocksize -
+ sizeof(struct extendedFileEntry))) {
make_bad_inode(inode);
return;
}
- memcpy(UDF_I_DATA(inode), bh->b_data + sizeof(struct extendedFileEntry),
- inode->i_sb->s_blocksize - sizeof(struct extendedFileEntry));
- } else if (le16_to_cpu(fe->descTag.tagIdent) == TAG_IDENT_FE) {
- UDF_I_EFE(inode) = 0;
- UDF_I_USE(inode) = 0;
- if (udf_alloc_i_data(inode, inode->i_sb->s_blocksize - sizeof(struct fileEntry))) {
+ memcpy(iinfo->i_ext.i_data,
+ bh->b_data + sizeof(struct extendedFileEntry),
+ inode->i_sb->s_blocksize -
+ sizeof(struct extendedFileEntry));
+ } else if (fe->descTag.tagIdent == cpu_to_le16(TAG_IDENT_FE)) {
+ iinfo->i_efe = 0;
+ iinfo->i_use = 0;
+ if (udf_alloc_i_data(inode, inode->i_sb->s_blocksize -
+ sizeof(struct fileEntry))) {
make_bad_inode(inode);
return;
}
- memcpy(UDF_I_DATA(inode), bh->b_data + sizeof(struct fileEntry),
+ memcpy(iinfo->i_ext.i_data,
+ bh->b_data + sizeof(struct fileEntry),
inode->i_sb->s_blocksize - sizeof(struct fileEntry));
- } else if (le16_to_cpu(fe->descTag.tagIdent) == TAG_IDENT_USE) {
- UDF_I_EFE(inode) = 0;
- UDF_I_USE(inode) = 1;
- UDF_I_LENALLOC(inode) =
- le32_to_cpu(((struct unallocSpaceEntry *)bh->b_data)->lengthAllocDescs);
- if (udf_alloc_i_data(inode, inode->i_sb->s_blocksize - sizeof(struct unallocSpaceEntry))) {
+ } else if (fe->descTag.tagIdent == cpu_to_le16(TAG_IDENT_USE)) {
+ iinfo->i_efe = 0;
+ iinfo->i_use = 1;
+ iinfo->i_lenAlloc = le32_to_cpu(
+ ((struct unallocSpaceEntry *)bh->b_data)->
+ lengthAllocDescs);
+ if (udf_alloc_i_data(inode, inode->i_sb->s_blocksize -
+ sizeof(struct unallocSpaceEntry))) {
make_bad_inode(inode);
return;
}
- memcpy(UDF_I_DATA(inode), bh->b_data + sizeof(struct unallocSpaceEntry),
- inode->i_sb->s_blocksize - sizeof(struct unallocSpaceEntry));
+ memcpy(iinfo->i_ext.i_data,
+ bh->b_data + sizeof(struct unallocSpaceEntry),
+ inode->i_sb->s_blocksize -
+ sizeof(struct unallocSpaceEntry));
return;
}
inode->i_nlink = 1;
inode->i_size = le64_to_cpu(fe->informationLength);
- UDF_I_LENEXTENTS(inode) = inode->i_size;
+ iinfo->i_lenExtents = inode->i_size;
inode->i_mode = udf_convert_permissions(fe);
inode->i_mode &= ~UDF_SB(inode->i_sb)->s_umask;
- if (UDF_I_EFE(inode) == 0) {
+ if (iinfo->i_efe == 0) {
inode->i_blocks = le64_to_cpu(fe->logicalBlocksRecorded) <<
(inode->i_sb->s_blocksize_bits - 9);
inode->i_atime.tv_sec = convtime;
inode->i_atime.tv_nsec = convtime_usec * 1000;
} else {
- inode->i_atime = UDF_SB_RECORDTIME(inode->i_sb);
+ inode->i_atime = sbi->s_record_time;
}
if (udf_stamp_to_time(&convtime, &convtime_usec,
inode->i_mtime.tv_sec = convtime;
inode->i_mtime.tv_nsec = convtime_usec * 1000;
} else {
- inode->i_mtime = UDF_SB_RECORDTIME(inode->i_sb);
+ inode->i_mtime = sbi->s_record_time;
}
if (udf_stamp_to_time(&convtime, &convtime_usec,
inode->i_ctime.tv_sec = convtime;
inode->i_ctime.tv_nsec = convtime_usec * 1000;
} else {
- inode->i_ctime = UDF_SB_RECORDTIME(inode->i_sb);
+ inode->i_ctime = sbi->s_record_time;
}
- UDF_I_UNIQUE(inode) = le64_to_cpu(fe->uniqueID);
- UDF_I_LENEATTR(inode) = le32_to_cpu(fe->lengthExtendedAttr);
- UDF_I_LENALLOC(inode) = le32_to_cpu(fe->lengthAllocDescs);
- offset = sizeof(struct fileEntry) + UDF_I_LENEATTR(inode);
+ iinfo->i_unique = le64_to_cpu(fe->uniqueID);
+ iinfo->i_lenEAttr = le32_to_cpu(fe->lengthExtendedAttr);
+ iinfo->i_lenAlloc = le32_to_cpu(fe->lengthAllocDescs);
+ offset = sizeof(struct fileEntry) + iinfo->i_lenEAttr;
} else {
inode->i_blocks = le64_to_cpu(efe->logicalBlocksRecorded) <<
(inode->i_sb->s_blocksize_bits - 9);
inode->i_atime.tv_sec = convtime;
inode->i_atime.tv_nsec = convtime_usec * 1000;
} else {
- inode->i_atime = UDF_SB_RECORDTIME(inode->i_sb);
+ inode->i_atime = sbi->s_record_time;
}
if (udf_stamp_to_time(&convtime, &convtime_usec,
inode->i_mtime.tv_sec = convtime;
inode->i_mtime.tv_nsec = convtime_usec * 1000;
} else {
- inode->i_mtime = UDF_SB_RECORDTIME(inode->i_sb);
+ inode->i_mtime = sbi->s_record_time;
}
if (udf_stamp_to_time(&convtime, &convtime_usec,
lets_to_cpu(efe->createTime))) {
- UDF_I_CRTIME(inode).tv_sec = convtime;
- UDF_I_CRTIME(inode).tv_nsec = convtime_usec * 1000;
+ iinfo->i_crtime.tv_sec = convtime;
+ iinfo->i_crtime.tv_nsec = convtime_usec * 1000;
} else {
- UDF_I_CRTIME(inode) = UDF_SB_RECORDTIME(inode->i_sb);
+ iinfo->i_crtime = sbi->s_record_time;
}
if (udf_stamp_to_time(&convtime, &convtime_usec,
inode->i_ctime.tv_sec = convtime;
inode->i_ctime.tv_nsec = convtime_usec * 1000;
} else {
- inode->i_ctime = UDF_SB_RECORDTIME(inode->i_sb);
+ inode->i_ctime = sbi->s_record_time;
}
- UDF_I_UNIQUE(inode) = le64_to_cpu(efe->uniqueID);
- UDF_I_LENEATTR(inode) = le32_to_cpu(efe->lengthExtendedAttr);
- UDF_I_LENALLOC(inode) = le32_to_cpu(efe->lengthAllocDescs);
- offset = sizeof(struct extendedFileEntry) + UDF_I_LENEATTR(inode);
+ iinfo->i_unique = le64_to_cpu(efe->uniqueID);
+ iinfo->i_lenEAttr = le32_to_cpu(efe->lengthExtendedAttr);
+ iinfo->i_lenAlloc = le32_to_cpu(efe->lengthAllocDescs);
+ offset = sizeof(struct extendedFileEntry) +
+ iinfo->i_lenEAttr;
}
switch (fe->icbTag.fileType) {
case ICBTAG_FILE_TYPE_REALTIME:
case ICBTAG_FILE_TYPE_REGULAR:
case ICBTAG_FILE_TYPE_UNDEF:
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
inode->i_data.a_ops = &udf_adinicb_aops;
else
inode->i_data.a_ops = &udf_aops;
inode->i_mode = S_IFLNK | S_IRWXUGO;
break;
default:
- printk(KERN_ERR "udf: udf_fill_inode(ino %ld) failed unknown file type=%d\n",
- inode->i_ino, fe->icbTag.fileType);
+ printk(KERN_ERR "udf: udf_fill_inode(ino %ld) failed unknown "
+ "file type=%d\n", inode->i_ino,
+ fe->icbTag.fileType);
make_bad_inode(inode);
return;
}
if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode)) {
- struct deviceSpec *dsea = (struct deviceSpec *)udf_get_extendedattr(inode, 12, 1);
+ struct deviceSpec *dsea =
+ (struct deviceSpec *)udf_get_extendedattr(inode, 12, 1);
if (dsea) {
init_special_inode(inode, inode->i_mode,
- MKDEV(le32_to_cpu(dsea->majorDeviceIdent),
- le32_to_cpu(dsea->minorDeviceIdent)));
+ MKDEV(le32_to_cpu(dsea->majorDeviceIdent),
+ le32_to_cpu(dsea->minorDeviceIdent)));
/* Developer ID ??? */
- } else {
+ } else
make_bad_inode(inode);
- }
}
}
static int udf_alloc_i_data(struct inode *inode, size_t size)
{
- UDF_I_DATA(inode) = kmalloc(size, GFP_KERNEL);
+ struct udf_inode_info *iinfo = UDF_I(inode);
+ iinfo->i_ext.i_data = kmalloc(size, GFP_KERNEL);
- if (!UDF_I_DATA(inode)) {
- printk(KERN_ERR "udf:udf_alloc_i_data (ino %ld) no free memory\n",
- inode->i_ino);
+ if (!iinfo->i_ext.i_data) {
+ printk(KERN_ERR "udf:udf_alloc_i_data (ino %ld) "
+ "no free memory\n", inode->i_ino);
return -ENOMEM;
}
permissions = le32_to_cpu(fe->permissions);
flags = le16_to_cpu(fe->icbTag.flags);
- mode = (( permissions ) & S_IRWXO) |
- (( permissions >> 2 ) & S_IRWXG) |
- (( permissions >> 4 ) & S_IRWXU) |
- (( flags & ICBTAG_FLAG_SETUID) ? S_ISUID : 0) |
- (( flags & ICBTAG_FLAG_SETGID) ? S_ISGID : 0) |
- (( flags & ICBTAG_FLAG_STICKY) ? S_ISVTX : 0);
+ mode = ((permissions) & S_IRWXO) |
+ ((permissions >> 2) & S_IRWXG) |
+ ((permissions >> 4) & S_IRWXU) |
+ ((flags & ICBTAG_FLAG_SETUID) ? S_ISUID : 0) |
+ ((flags & ICBTAG_FLAG_SETGID) ? S_ISGID : 0) |
+ ((flags & ICBTAG_FLAG_STICKY) ? S_ISVTX : 0);
return mode;
}
uint32_t udfperms;
uint16_t icbflags;
uint16_t crclen;
- int i;
kernel_timestamp cpu_time;
int err = 0;
+ struct udf_sb_info *sbi = UDF_SB(inode->i_sb);
+ unsigned char blocksize_bits = inode->i_sb->s_blocksize_bits;
+ struct udf_inode_info *iinfo = UDF_I(inode);
- bh = udf_tread(inode->i_sb, udf_get_lb_pblock(inode->i_sb, UDF_I_LOCATION(inode), 0));
+ bh = udf_tread(inode->i_sb,
+ udf_get_lb_pblock(inode->i_sb,
+ iinfo->i_location, 0));
if (!bh) {
udf_debug("bread failure\n");
return -EIO;
fe = (struct fileEntry *)bh->b_data;
efe = (struct extendedFileEntry *)bh->b_data;
- if (le16_to_cpu(fe->descTag.tagIdent) == TAG_IDENT_USE) {
+ if (fe->descTag.tagIdent == cpu_to_le16(TAG_IDENT_USE)) {
struct unallocSpaceEntry *use =
(struct unallocSpaceEntry *)bh->b_data;
- use->lengthAllocDescs = cpu_to_le32(UDF_I_LENALLOC(inode));
- memcpy(bh->b_data + sizeof(struct unallocSpaceEntry), UDF_I_DATA(inode),
- inode->i_sb->s_blocksize - sizeof(struct unallocSpaceEntry));
- crclen = sizeof(struct unallocSpaceEntry) + UDF_I_LENALLOC(inode) - sizeof(tag);
- use->descTag.tagLocation = cpu_to_le32(UDF_I_LOCATION(inode).logicalBlockNum);
+ use->lengthAllocDescs = cpu_to_le32(iinfo->i_lenAlloc);
+ memcpy(bh->b_data + sizeof(struct unallocSpaceEntry),
+ iinfo->i_ext.i_data, inode->i_sb->s_blocksize -
+ sizeof(struct unallocSpaceEntry));
+ crclen = sizeof(struct unallocSpaceEntry) +
+ iinfo->i_lenAlloc - sizeof(tag);
+ use->descTag.tagLocation = cpu_to_le32(
+ iinfo->i_location.
+ logicalBlockNum);
use->descTag.descCRCLength = cpu_to_le16(crclen);
- use->descTag.descCRC = cpu_to_le16(udf_crc((char *)use + sizeof(tag), crclen, 0));
-
- use->descTag.tagChecksum = 0;
- for (i = 0; i < 16; i++) {
- if (i != 4)
- use->descTag.tagChecksum += ((uint8_t *)&(use->descTag))[i];
- }
+ use->descTag.descCRC = cpu_to_le16(udf_crc((char *)use +
+ sizeof(tag), crclen,
+ 0));
+ use->descTag.tagChecksum = udf_tag_checksum(&use->descTag);
mark_buffer_dirty(bh);
brelse(bh);
else
fe->gid = cpu_to_le32(inode->i_gid);
- udfperms = ((inode->i_mode & S_IRWXO) ) |
- ((inode->i_mode & S_IRWXG) << 2) |
- ((inode->i_mode & S_IRWXU) << 4);
+ udfperms = ((inode->i_mode & S_IRWXO)) |
+ ((inode->i_mode & S_IRWXG) << 2) |
+ ((inode->i_mode & S_IRWXU) << 4);
- udfperms |= (le32_to_cpu(fe->permissions) &
- (FE_PERM_O_DELETE | FE_PERM_O_CHATTR |
- FE_PERM_G_DELETE | FE_PERM_G_CHATTR |
- FE_PERM_U_DELETE | FE_PERM_U_CHATTR));
+ udfperms |= (le32_to_cpu(fe->permissions) &
+ (FE_PERM_O_DELETE | FE_PERM_O_CHATTR |
+ FE_PERM_G_DELETE | FE_PERM_G_CHATTR |
+ FE_PERM_U_DELETE | FE_PERM_U_CHATTR));
fe->permissions = cpu_to_le32(udfperms);
if (S_ISDIR(inode->i_mode))
sizeof(regid), 12, 0x3);
dsea->attrType = cpu_to_le32(12);
dsea->attrSubtype = 1;
- dsea->attrLength = cpu_to_le32(sizeof(struct deviceSpec) +
- sizeof(regid));
+ dsea->attrLength = cpu_to_le32(
+ sizeof(struct deviceSpec) +
+ sizeof(regid));
dsea->impUseLength = cpu_to_le32(sizeof(regid));
}
eid = (regid *)dsea->impUse;
dsea->minorDeviceIdent = cpu_to_le32(iminor(inode));
}
- if (UDF_I_EFE(inode) == 0) {
- memcpy(bh->b_data + sizeof(struct fileEntry), UDF_I_DATA(inode),
+ if (iinfo->i_efe == 0) {
+ memcpy(bh->b_data + sizeof(struct fileEntry),
+ iinfo->i_ext.i_data,
inode->i_sb->s_blocksize - sizeof(struct fileEntry));
fe->logicalBlocksRecorded = cpu_to_le64(
- (inode->i_blocks + (1 << (inode->i_sb->s_blocksize_bits - 9)) - 1) >>
- (inode->i_sb->s_blocksize_bits - 9));
+ (inode->i_blocks + (1 << (blocksize_bits - 9)) - 1) >>
+ (blocksize_bits - 9));
if (udf_time_to_stamp(&cpu_time, inode->i_atime))
fe->accessTime = cpu_to_lets(cpu_time);
strcpy(fe->impIdent.ident, UDF_ID_DEVELOPER);
fe->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
fe->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
- fe->uniqueID = cpu_to_le64(UDF_I_UNIQUE(inode));
- fe->lengthExtendedAttr = cpu_to_le32(UDF_I_LENEATTR(inode));
- fe->lengthAllocDescs = cpu_to_le32(UDF_I_LENALLOC(inode));
+ fe->uniqueID = cpu_to_le64(iinfo->i_unique);
+ fe->lengthExtendedAttr = cpu_to_le32(iinfo->i_lenEAttr);
+ fe->lengthAllocDescs = cpu_to_le32(iinfo->i_lenAlloc);
fe->descTag.tagIdent = cpu_to_le16(TAG_IDENT_FE);
crclen = sizeof(struct fileEntry);
} else {
- memcpy(bh->b_data + sizeof(struct extendedFileEntry), UDF_I_DATA(inode),
- inode->i_sb->s_blocksize - sizeof(struct extendedFileEntry));
+ memcpy(bh->b_data + sizeof(struct extendedFileEntry),
+ iinfo->i_ext.i_data,
+ inode->i_sb->s_blocksize -
+ sizeof(struct extendedFileEntry));
efe->objectSize = cpu_to_le64(inode->i_size);
efe->logicalBlocksRecorded = cpu_to_le64(
- (inode->i_blocks + (1 << (inode->i_sb->s_blocksize_bits - 9)) - 1) >>
- (inode->i_sb->s_blocksize_bits - 9));
+ (inode->i_blocks + (1 << (blocksize_bits - 9)) - 1) >>
+ (blocksize_bits - 9));
- if (UDF_I_CRTIME(inode).tv_sec > inode->i_atime.tv_sec ||
- (UDF_I_CRTIME(inode).tv_sec == inode->i_atime.tv_sec &&
- UDF_I_CRTIME(inode).tv_nsec > inode->i_atime.tv_nsec)) {
- UDF_I_CRTIME(inode) = inode->i_atime;
- }
- if (UDF_I_CRTIME(inode).tv_sec > inode->i_mtime.tv_sec ||
- (UDF_I_CRTIME(inode).tv_sec == inode->i_mtime.tv_sec &&
- UDF_I_CRTIME(inode).tv_nsec > inode->i_mtime.tv_nsec)) {
- UDF_I_CRTIME(inode) = inode->i_mtime;
- }
- if (UDF_I_CRTIME(inode).tv_sec > inode->i_ctime.tv_sec ||
- (UDF_I_CRTIME(inode).tv_sec == inode->i_ctime.tv_sec &&
- UDF_I_CRTIME(inode).tv_nsec > inode->i_ctime.tv_nsec)) {
- UDF_I_CRTIME(inode) = inode->i_ctime;
- }
+ if (iinfo->i_crtime.tv_sec > inode->i_atime.tv_sec ||
+ (iinfo->i_crtime.tv_sec == inode->i_atime.tv_sec &&
+ iinfo->i_crtime.tv_nsec > inode->i_atime.tv_nsec))
+ iinfo->i_crtime = inode->i_atime;
+
+ if (iinfo->i_crtime.tv_sec > inode->i_mtime.tv_sec ||
+ (iinfo->i_crtime.tv_sec == inode->i_mtime.tv_sec &&
+ iinfo->i_crtime.tv_nsec > inode->i_mtime.tv_nsec))
+ iinfo->i_crtime = inode->i_mtime;
+
+ if (iinfo->i_crtime.tv_sec > inode->i_ctime.tv_sec ||
+ (iinfo->i_crtime.tv_sec == inode->i_ctime.tv_sec &&
+ iinfo->i_crtime.tv_nsec > inode->i_ctime.tv_nsec))
+ iinfo->i_crtime = inode->i_ctime;
if (udf_time_to_stamp(&cpu_time, inode->i_atime))
efe->accessTime = cpu_to_lets(cpu_time);
if (udf_time_to_stamp(&cpu_time, inode->i_mtime))
efe->modificationTime = cpu_to_lets(cpu_time);
- if (udf_time_to_stamp(&cpu_time, UDF_I_CRTIME(inode)))
+ if (udf_time_to_stamp(&cpu_time, iinfo->i_crtime))
efe->createTime = cpu_to_lets(cpu_time);
if (udf_time_to_stamp(&cpu_time, inode->i_ctime))
efe->attrTime = cpu_to_lets(cpu_time);
strcpy(efe->impIdent.ident, UDF_ID_DEVELOPER);
efe->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
efe->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
- efe->uniqueID = cpu_to_le64(UDF_I_UNIQUE(inode));
- efe->lengthExtendedAttr = cpu_to_le32(UDF_I_LENEATTR(inode));
- efe->lengthAllocDescs = cpu_to_le32(UDF_I_LENALLOC(inode));
+ efe->uniqueID = cpu_to_le64(iinfo->i_unique);
+ efe->lengthExtendedAttr = cpu_to_le32(iinfo->i_lenEAttr);
+ efe->lengthAllocDescs = cpu_to_le32(iinfo->i_lenAlloc);
efe->descTag.tagIdent = cpu_to_le16(TAG_IDENT_EFE);
crclen = sizeof(struct extendedFileEntry);
}
- if (UDF_I_STRAT4096(inode)) {
+ if (iinfo->i_strat4096) {
fe->icbTag.strategyType = cpu_to_le16(4096);
fe->icbTag.strategyParameter = cpu_to_le16(1);
fe->icbTag.numEntries = cpu_to_le16(2);
else if (S_ISSOCK(inode->i_mode))
fe->icbTag.fileType = ICBTAG_FILE_TYPE_SOCKET;
- icbflags = UDF_I_ALLOCTYPE(inode) |
+ icbflags = iinfo->i_alloc_type |
((inode->i_mode & S_ISUID) ? ICBTAG_FLAG_SETUID : 0) |
((inode->i_mode & S_ISGID) ? ICBTAG_FLAG_SETGID : 0) |
((inode->i_mode & S_ISVTX) ? ICBTAG_FLAG_STICKY : 0) |
ICBTAG_FLAG_SETGID | ICBTAG_FLAG_STICKY));
fe->icbTag.flags = cpu_to_le16(icbflags);
- if (UDF_SB_UDFREV(inode->i_sb) >= 0x0200)
+ if (sbi->s_udfrev >= 0x0200)
fe->descTag.descVersion = cpu_to_le16(3);
else
fe->descTag.descVersion = cpu_to_le16(2);
- fe->descTag.tagSerialNum = cpu_to_le16(UDF_SB_SERIALNUM(inode->i_sb));
- fe->descTag.tagLocation = cpu_to_le32(UDF_I_LOCATION(inode).logicalBlockNum);
- crclen += UDF_I_LENEATTR(inode) + UDF_I_LENALLOC(inode) - sizeof(tag);
+ fe->descTag.tagSerialNum = cpu_to_le16(sbi->s_serial_number);
+ fe->descTag.tagLocation = cpu_to_le32(
+ iinfo->i_location.logicalBlockNum);
+ crclen += iinfo->i_lenEAttr + iinfo->i_lenAlloc -
+ sizeof(tag);
fe->descTag.descCRCLength = cpu_to_le16(crclen);
- fe->descTag.descCRC = cpu_to_le16(udf_crc((char *)fe + sizeof(tag), crclen, 0));
-
- fe->descTag.tagChecksum = 0;
- for (i = 0; i < 16; i++) {
- if (i != 4)
- fe->descTag.tagChecksum += ((uint8_t *)&(fe->descTag))[i];
- }
+ fe->descTag.descCRC = cpu_to_le16(udf_crc((char *)fe + sizeof(tag),
+ crclen, 0));
+ fe->descTag.tagChecksum = udf_tag_checksum(&fe->descTag);
/* write the data blocks */
mark_buffer_dirty(bh);
if (do_sync) {
sync_dirty_buffer(bh);
if (buffer_req(bh) && !buffer_uptodate(bh)) {
- printk("IO error syncing udf inode [%s:%08lx]\n",
- inode->i_sb->s_id, inode->i_ino);
+ printk(KERN_WARNING "IO error syncing udf inode "
+ "[%s:%08lx]\n", inode->i_sb->s_id,
+ inode->i_ino);
err = -EIO;
}
}
return NULL;
if (inode->i_state & I_NEW) {
- memcpy(&UDF_I_LOCATION(inode), &ino, sizeof(kernel_lb_addr));
+ memcpy(&UDF_I(inode)->i_location, &ino, sizeof(kernel_lb_addr));
__udf_read_inode(inode);
unlock_new_inode(inode);
}
if (is_bad_inode(inode))
goto out_iput;
- if (ino.logicalBlockNum >= UDF_SB_PARTLEN(sb, ino.partitionReferenceNum)) {
+ if (ino.logicalBlockNum >= UDF_SB(sb)->
+ s_partmaps[ino.partitionReferenceNum].s_partition_len) {
udf_debug("block=%d, partition=%d out of range\n",
ino.logicalBlockNum, ino.partitionReferenceNum);
make_bad_inode(inode);
return NULL;
}
-int8_t udf_add_aext(struct inode * inode, struct extent_position * epos,
+int8_t udf_add_aext(struct inode *inode, struct extent_position *epos,
kernel_lb_addr eloc, uint32_t elen, int inc)
{
int adsize;
struct allocExtDesc *aed;
int8_t etype;
uint8_t *ptr;
+ struct udf_inode_info *iinfo = UDF_I(inode);
if (!epos->bh)
- ptr = UDF_I_DATA(inode) + epos->offset - udf_file_entry_alloc_offset(inode) + UDF_I_LENEATTR(inode);
+ ptr = iinfo->i_ext.i_data + epos->offset -
+ udf_file_entry_alloc_offset(inode) +
+ iinfo->i_lenEAttr;
else
ptr = epos->bh->b_data + epos->offset;
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
adsize = sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
+ else if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
adsize = sizeof(long_ad);
else
return -1;
int err, loffset;
kernel_lb_addr obloc = epos->block;
- if (!(epos->block.logicalBlockNum = udf_new_block(inode->i_sb, NULL,
- obloc.partitionReferenceNum,
- obloc.logicalBlockNum, &err))) {
+ epos->block.logicalBlockNum = udf_new_block(inode->i_sb, NULL,
+ obloc.partitionReferenceNum,
+ obloc.logicalBlockNum, &err);
+ if (!epos->block.logicalBlockNum)
return -1;
- }
- if (!(nbh = udf_tgetblk(inode->i_sb, udf_get_lb_pblock(inode->i_sb,
- epos->block, 0)))) {
+ nbh = udf_tgetblk(inode->i_sb, udf_get_lb_pblock(inode->i_sb,
+ epos->block,
+ 0));
+ if (!nbh)
return -1;
- }
lock_buffer(nbh);
memset(nbh->b_data, 0x00, inode->i_sb->s_blocksize);
set_buffer_uptodate(nbh);
aed = (struct allocExtDesc *)(nbh->b_data);
if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT))
- aed->previousAllocExtLocation = cpu_to_le32(obloc.logicalBlockNum);
+ aed->previousAllocExtLocation =
+ cpu_to_le32(obloc.logicalBlockNum);
if (epos->offset + adsize > inode->i_sb->s_blocksize) {
loffset = epos->offset;
aed->lengthAllocDescs = cpu_to_le32(adsize);
if (epos->bh) {
aed = (struct allocExtDesc *)epos->bh->b_data;
aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) + adsize);
+ cpu_to_le32(le32_to_cpu(
+ aed->lengthAllocDescs) + adsize);
} else {
- UDF_I_LENALLOC(inode) += adsize;
+ iinfo->i_lenAlloc += adsize;
mark_inode_dirty(inode);
}
}
- if (UDF_SB_UDFREV(inode->i_sb) >= 0x0200)
+ if (UDF_SB(inode->i_sb)->s_udfrev >= 0x0200)
udf_new_tag(nbh->b_data, TAG_IDENT_AED, 3, 1,
epos->block.logicalBlockNum, sizeof(tag));
else
udf_new_tag(nbh->b_data, TAG_IDENT_AED, 2, 1,
epos->block.logicalBlockNum, sizeof(tag));
- switch (UDF_I_ALLOCTYPE(inode)) {
+ switch (iinfo->i_alloc_type) {
case ICBTAG_FLAG_AD_SHORT:
sad = (short_ad *)sptr;
sad->extLength = cpu_to_le32(EXT_NEXT_EXTENT_ALLOCDECS |
inode->i_sb->s_blocksize);
- sad->extPosition = cpu_to_le32(epos->block.logicalBlockNum);
+ sad->extPosition =
+ cpu_to_le32(epos->block.logicalBlockNum);
break;
case ICBTAG_FLAG_AD_LONG:
lad = (long_ad *)sptr;
}
if (epos->bh) {
if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) ||
- UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
+ UDF_SB(inode->i_sb)->s_udfrev >= 0x0201)
udf_update_tag(epos->bh->b_data, loffset);
else
- udf_update_tag(epos->bh->b_data, sizeof(struct allocExtDesc));
+ udf_update_tag(epos->bh->b_data,
+ sizeof(struct allocExtDesc));
mark_buffer_dirty_inode(epos->bh, inode);
brelse(epos->bh);
} else {
etype = udf_write_aext(inode, epos, eloc, elen, inc);
if (!epos->bh) {
- UDF_I_LENALLOC(inode) += adsize;
+ iinfo->i_lenAlloc += adsize;
mark_inode_dirty(inode);
} else {
aed = (struct allocExtDesc *)epos->bh->b_data;
aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) + adsize);
- if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) || UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
- udf_update_tag(epos->bh->b_data, epos->offset + (inc ? 0 : adsize));
+ cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) +
+ adsize);
+ if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) ||
+ UDF_SB(inode->i_sb)->s_udfrev >= 0x0201)
+ udf_update_tag(epos->bh->b_data,
+ epos->offset + (inc ? 0 : adsize));
else
- udf_update_tag(epos->bh->b_data, sizeof(struct allocExtDesc));
+ udf_update_tag(epos->bh->b_data,
+ sizeof(struct allocExtDesc));
mark_buffer_dirty_inode(epos->bh, inode);
}
return etype;
}
-int8_t udf_write_aext(struct inode * inode, struct extent_position * epos,
+int8_t udf_write_aext(struct inode *inode, struct extent_position *epos,
kernel_lb_addr eloc, uint32_t elen, int inc)
{
int adsize;
uint8_t *ptr;
short_ad *sad;
long_ad *lad;
+ struct udf_inode_info *iinfo = UDF_I(inode);
if (!epos->bh)
- ptr = UDF_I_DATA(inode) + epos->offset - udf_file_entry_alloc_offset(inode) + UDF_I_LENEATTR(inode);
+ ptr = iinfo->i_ext.i_data + epos->offset -
+ udf_file_entry_alloc_offset(inode) +
+ iinfo->i_lenEAttr;
else
ptr = epos->bh->b_data + epos->offset;
- switch (UDF_I_ALLOCTYPE(inode)) {
+ switch (iinfo->i_alloc_type) {
case ICBTAG_FLAG_AD_SHORT:
sad = (short_ad *)ptr;
sad->extLength = cpu_to_le32(elen);
if (epos->bh) {
if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) ||
- UDF_SB_UDFREV(inode->i_sb) >= 0x0201) {
- struct allocExtDesc *aed = (struct allocExtDesc *)epos->bh->b_data;
+ UDF_SB(inode->i_sb)->s_udfrev >= 0x0201) {
+ struct allocExtDesc *aed =
+ (struct allocExtDesc *)epos->bh->b_data;
udf_update_tag(epos->bh->b_data,
- le32_to_cpu(aed->lengthAllocDescs) + sizeof(struct allocExtDesc));
+ le32_to_cpu(aed->lengthAllocDescs) +
+ sizeof(struct allocExtDesc));
}
mark_buffer_dirty_inode(epos->bh, inode);
} else {
return (elen >> 30);
}
-int8_t udf_next_aext(struct inode * inode, struct extent_position * epos,
- kernel_lb_addr * eloc, uint32_t * elen, int inc)
+int8_t udf_next_aext(struct inode *inode, struct extent_position *epos,
+ kernel_lb_addr *eloc, uint32_t *elen, int inc)
{
int8_t etype;
while ((etype = udf_current_aext(inode, epos, eloc, elen, inc)) ==
(EXT_NEXT_EXTENT_ALLOCDECS >> 30)) {
+ int block;
epos->block = *eloc;
epos->offset = sizeof(struct allocExtDesc);
brelse(epos->bh);
- if (!(epos->bh = udf_tread(inode->i_sb, udf_get_lb_pblock(inode->i_sb, epos->block, 0)))) {
- udf_debug("reading block %d failed!\n",
- udf_get_lb_pblock(inode->i_sb, epos->block, 0));
+ block = udf_get_lb_pblock(inode->i_sb, epos->block, 0);
+ epos->bh = udf_tread(inode->i_sb, block);
+ if (!epos->bh) {
+ udf_debug("reading block %d failed!\n", block);
return -1;
}
}
return etype;
}
-int8_t udf_current_aext(struct inode * inode, struct extent_position * epos,
- kernel_lb_addr * eloc, uint32_t * elen, int inc)
+int8_t udf_current_aext(struct inode *inode, struct extent_position *epos,
+ kernel_lb_addr *eloc, uint32_t *elen, int inc)
{
int alen;
int8_t etype;
uint8_t *ptr;
short_ad *sad;
long_ad *lad;
-
+ struct udf_inode_info *iinfo = UDF_I(inode);
if (!epos->bh) {
if (!epos->offset)
epos->offset = udf_file_entry_alloc_offset(inode);
- ptr = UDF_I_DATA(inode) + epos->offset - udf_file_entry_alloc_offset(inode) + UDF_I_LENEATTR(inode);
- alen = udf_file_entry_alloc_offset(inode) + UDF_I_LENALLOC(inode);
+ ptr = iinfo->i_ext.i_data + epos->offset -
+ udf_file_entry_alloc_offset(inode) +
+ iinfo->i_lenEAttr;
+ alen = udf_file_entry_alloc_offset(inode) +
+ iinfo->i_lenAlloc;
} else {
if (!epos->offset)
epos->offset = sizeof(struct allocExtDesc);
ptr = epos->bh->b_data + epos->offset;
alen = sizeof(struct allocExtDesc) +
- le32_to_cpu(((struct allocExtDesc *)epos->bh->b_data)->lengthAllocDescs);
+ le32_to_cpu(((struct allocExtDesc *)epos->bh->b_data)->
+ lengthAllocDescs);
}
- switch (UDF_I_ALLOCTYPE(inode)) {
+ switch (iinfo->i_alloc_type) {
case ICBTAG_FLAG_AD_SHORT:
- if (!(sad = udf_get_fileshortad(ptr, alen, &epos->offset, inc)))
+ sad = udf_get_fileshortad(ptr, alen, &epos->offset, inc);
+ if (!sad)
return -1;
etype = le32_to_cpu(sad->extLength) >> 30;
eloc->logicalBlockNum = le32_to_cpu(sad->extPosition);
- eloc->partitionReferenceNum = UDF_I_LOCATION(inode).partitionReferenceNum;
+ eloc->partitionReferenceNum =
+ iinfo->i_location.partitionReferenceNum;
*elen = le32_to_cpu(sad->extLength) & UDF_EXTENT_LENGTH_MASK;
break;
case ICBTAG_FLAG_AD_LONG:
- if (!(lad = udf_get_filelongad(ptr, alen, &epos->offset, inc)))
+ lad = udf_get_filelongad(ptr, alen, &epos->offset, inc);
+ if (!lad)
return -1;
etype = le32_to_cpu(lad->extLength) >> 30;
*eloc = lelb_to_cpu(lad->extLocation);
*elen = le32_to_cpu(lad->extLength) & UDF_EXTENT_LENGTH_MASK;
break;
default:
- udf_debug("alloc_type = %d unsupported\n", UDF_I_ALLOCTYPE(inode));
+ udf_debug("alloc_type = %d unsupported\n",
+ iinfo->i_alloc_type);
return -1;
}
return (nelen >> 30);
}
-int8_t udf_delete_aext(struct inode * inode, struct extent_position epos,
+int8_t udf_delete_aext(struct inode *inode, struct extent_position epos,
kernel_lb_addr eloc, uint32_t elen)
{
struct extent_position oepos;
int adsize;
int8_t etype;
struct allocExtDesc *aed;
+ struct udf_inode_info *iinfo;
if (epos.bh) {
get_bh(epos.bh);
get_bh(epos.bh);
}
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
+ iinfo = UDF_I(inode);
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
adsize = sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
+ else if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
adsize = sizeof(long_ad);
else
adsize = 0;
udf_write_aext(inode, &oepos, eloc, elen, 1);
udf_write_aext(inode, &oepos, eloc, elen, 1);
if (!oepos.bh) {
- UDF_I_LENALLOC(inode) -= (adsize * 2);
+ iinfo->i_lenAlloc -= (adsize * 2);
mark_inode_dirty(inode);
} else {
aed = (struct allocExtDesc *)oepos.bh->b_data;
aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) - (2 * adsize));
+ cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) -
+ (2 * adsize));
if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) ||
- UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
- udf_update_tag(oepos.bh->b_data, oepos.offset - (2 * adsize));
+ UDF_SB(inode->i_sb)->s_udfrev >= 0x0201)
+ udf_update_tag(oepos.bh->b_data,
+ oepos.offset - (2 * adsize));
else
- udf_update_tag(oepos.bh->b_data, sizeof(struct allocExtDesc));
+ udf_update_tag(oepos.bh->b_data,
+ sizeof(struct allocExtDesc));
mark_buffer_dirty_inode(oepos.bh, inode);
}
} else {
udf_write_aext(inode, &oepos, eloc, elen, 1);
if (!oepos.bh) {
- UDF_I_LENALLOC(inode) -= adsize;
+ iinfo->i_lenAlloc -= adsize;
mark_inode_dirty(inode);
} else {
aed = (struct allocExtDesc *)oepos.bh->b_data;
aed->lengthAllocDescs =
- cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) - adsize);
+ cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) -
+ adsize);
if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) ||
- UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
- udf_update_tag(oepos.bh->b_data, epos.offset - adsize);
+ UDF_SB(inode->i_sb)->s_udfrev >= 0x0201)
+ udf_update_tag(oepos.bh->b_data,
+ epos.offset - adsize);
else
- udf_update_tag(oepos.bh->b_data, sizeof(struct allocExtDesc));
+ udf_update_tag(oepos.bh->b_data,
+ sizeof(struct allocExtDesc));
mark_buffer_dirty_inode(oepos.bh, inode);
}
}
return (elen >> 30);
}
-int8_t inode_bmap(struct inode * inode, sector_t block,
- struct extent_position * pos, kernel_lb_addr * eloc,
- uint32_t * elen, sector_t * offset)
+int8_t inode_bmap(struct inode *inode, sector_t block,
+ struct extent_position *pos, kernel_lb_addr *eloc,
+ uint32_t *elen, sector_t *offset)
{
+ unsigned char blocksize_bits = inode->i_sb->s_blocksize_bits;
loff_t lbcount = 0, bcount =
- (loff_t) block << inode->i_sb->s_blocksize_bits;
+ (loff_t) block << blocksize_bits;
int8_t etype;
+ struct udf_inode_info *iinfo;
if (block < 0) {
printk(KERN_ERR "udf: inode_bmap: block < 0\n");
return -1;
}
+ iinfo = UDF_I(inode);
pos->offset = 0;
- pos->block = UDF_I_LOCATION(inode);
+ pos->block = iinfo->i_location;
pos->bh = NULL;
*elen = 0;
do {
- if ((etype = udf_next_aext(inode, pos, eloc, elen, 1)) == -1) {
- *offset = (bcount - lbcount) >> inode->i_sb->s_blocksize_bits;
- UDF_I_LENEXTENTS(inode) = lbcount;
+ etype = udf_next_aext(inode, pos, eloc, elen, 1);
+ if (etype == -1) {
+ *offset = (bcount - lbcount) >> blocksize_bits;
+ iinfo->i_lenExtents = lbcount;
return -1;
}
lbcount += *elen;
} while (lbcount <= bcount);
- *offset = (bcount + *elen - lbcount) >> inode->i_sb->s_blocksize_bits;
+ *offset = (bcount + *elen - lbcount) >> blocksize_bits;
return etype;
}
lock_kernel();
- if (inode_bmap(inode, block, &epos, &eloc, &elen, &offset) == (EXT_RECORDED_ALLOCATED >> 30))
+ if (inode_bmap(inode, block, &epos, &eloc, &elen, &offset) ==
+ (EXT_RECORDED_ALLOCATED >> 30))
ret = udf_get_lb_pblock(inode->i_sb, eloc, offset);
else
ret = 0;
uint8_t *ea = NULL, *ad = NULL;
int offset;
uint16_t crclen;
- int i;
+ struct udf_inode_info *iinfo = UDF_I(inode);
- ea = UDF_I_DATA(inode);
- if (UDF_I_LENEATTR(inode)) {
- ad = UDF_I_DATA(inode) + UDF_I_LENEATTR(inode);
+ ea = iinfo->i_ext.i_data;
+ if (iinfo->i_lenEAttr) {
+ ad = iinfo->i_ext.i_data + iinfo->i_lenEAttr;
} else {
ad = ea;
size += sizeof(struct extendedAttrHeaderDesc);
}
offset = inode->i_sb->s_blocksize - udf_file_entry_alloc_offset(inode) -
- UDF_I_LENALLOC(inode);
+ iinfo->i_lenAlloc;
/* TODO - Check for FreeEASpace */
struct extendedAttrHeaderDesc *eahd;
eahd = (struct extendedAttrHeaderDesc *)ea;
- if (UDF_I_LENALLOC(inode)) {
- memmove(&ad[size], ad, UDF_I_LENALLOC(inode));
- }
+ if (iinfo->i_lenAlloc)
+ memmove(&ad[size], ad, iinfo->i_lenAlloc);
- if (UDF_I_LENEATTR(inode)) {
+ if (iinfo->i_lenEAttr) {
/* check checksum/crc */
- if (le16_to_cpu(eahd->descTag.tagIdent) != TAG_IDENT_EAHD ||
- le32_to_cpu(eahd->descTag.tagLocation) != UDF_I_LOCATION(inode).logicalBlockNum) {
+ if (eahd->descTag.tagIdent !=
+ cpu_to_le16(TAG_IDENT_EAHD) ||
+ le32_to_cpu(eahd->descTag.tagLocation) !=
+ iinfo->i_location.logicalBlockNum)
return NULL;
- }
} else {
+ struct udf_sb_info *sbi = UDF_SB(inode->i_sb);
+
size -= sizeof(struct extendedAttrHeaderDesc);
- UDF_I_LENEATTR(inode) += sizeof(struct extendedAttrHeaderDesc);
+ iinfo->i_lenEAttr +=
+ sizeof(struct extendedAttrHeaderDesc);
eahd->descTag.tagIdent = cpu_to_le16(TAG_IDENT_EAHD);
- if (UDF_SB_UDFREV(inode->i_sb) >= 0x0200)
+ if (sbi->s_udfrev >= 0x0200)
eahd->descTag.descVersion = cpu_to_le16(3);
else
eahd->descTag.descVersion = cpu_to_le16(2);
- eahd->descTag.tagSerialNum = cpu_to_le16(UDF_SB_SERIALNUM(inode->i_sb));
- eahd->descTag.tagLocation = cpu_to_le32(UDF_I_LOCATION(inode).logicalBlockNum);
+ eahd->descTag.tagSerialNum =
+ cpu_to_le16(sbi->s_serial_number);
+ eahd->descTag.tagLocation = cpu_to_le32(
+ iinfo->i_location.logicalBlockNum);
eahd->impAttrLocation = cpu_to_le32(0xFFFFFFFF);
eahd->appAttrLocation = cpu_to_le32(0xFFFFFFFF);
}
- offset = UDF_I_LENEATTR(inode);
+ offset = iinfo->i_lenEAttr;
if (type < 2048) {
- if (le32_to_cpu(eahd->appAttrLocation) < UDF_I_LENEATTR(inode)) {
- uint32_t aal = le32_to_cpu(eahd->appAttrLocation);
+ if (le32_to_cpu(eahd->appAttrLocation) <
+ iinfo->i_lenEAttr) {
+ uint32_t aal =
+ le32_to_cpu(eahd->appAttrLocation);
memmove(&ea[offset - aal + size],
&ea[aal], offset - aal);
offset -= aal;
- eahd->appAttrLocation = cpu_to_le32(aal + size);
+ eahd->appAttrLocation =
+ cpu_to_le32(aal + size);
}
- if (le32_to_cpu(eahd->impAttrLocation) < UDF_I_LENEATTR(inode)) {
- uint32_t ial = le32_to_cpu(eahd->impAttrLocation);
+ if (le32_to_cpu(eahd->impAttrLocation) <
+ iinfo->i_lenEAttr) {
+ uint32_t ial =
+ le32_to_cpu(eahd->impAttrLocation);
memmove(&ea[offset - ial + size],
&ea[ial], offset - ial);
offset -= ial;
- eahd->impAttrLocation = cpu_to_le32(ial + size);
+ eahd->impAttrLocation =
+ cpu_to_le32(ial + size);
}
} else if (type < 65536) {
- if (le32_to_cpu(eahd->appAttrLocation) < UDF_I_LENEATTR(inode)) {
- uint32_t aal = le32_to_cpu(eahd->appAttrLocation);
+ if (le32_to_cpu(eahd->appAttrLocation) <
+ iinfo->i_lenEAttr) {
+ uint32_t aal =
+ le32_to_cpu(eahd->appAttrLocation);
memmove(&ea[offset - aal + size],
&ea[aal], offset - aal);
offset -= aal;
- eahd->appAttrLocation = cpu_to_le32(aal + size);
+ eahd->appAttrLocation =
+ cpu_to_le32(aal + size);
}
}
/* rewrite CRC + checksum of eahd */
crclen = sizeof(struct extendedAttrHeaderDesc) - sizeof(tag);
eahd->descTag.descCRCLength = cpu_to_le16(crclen);
eahd->descTag.descCRC = cpu_to_le16(udf_crc((char *)eahd +
- sizeof(tag), crclen, 0));
- eahd->descTag.tagChecksum = 0;
- for (i = 0; i < 16; i++)
- if (i != 4)
- eahd->descTag.tagChecksum += ((uint8_t *)&(eahd->descTag))[i];
- UDF_I_LENEATTR(inode) += size;
+ sizeof(tag), crclen, 0));
+ eahd->descTag.tagChecksum = udf_tag_checksum(&eahd->descTag);
+ iinfo->i_lenEAttr += size;
return (struct genericFormat *)&ea[offset];
}
- if (loc & 0x02) {
- }
+ if (loc & 0x02)
+ ;
return NULL;
}
struct genericFormat *gaf;
uint8_t *ea = NULL;
uint32_t offset;
+ struct udf_inode_info *iinfo = UDF_I(inode);
- ea = UDF_I_DATA(inode);
+ ea = iinfo->i_ext.i_data;
- if (UDF_I_LENEATTR(inode)) {
+ if (iinfo->i_lenEAttr) {
struct extendedAttrHeaderDesc *eahd;
eahd = (struct extendedAttrHeaderDesc *)ea;
/* check checksum/crc */
- if (le16_to_cpu(eahd->descTag.tagIdent) != TAG_IDENT_EAHD ||
- le32_to_cpu(eahd->descTag.tagLocation) != UDF_I_LOCATION(inode).logicalBlockNum) {
+ if (eahd->descTag.tagIdent !=
+ cpu_to_le16(TAG_IDENT_EAHD) ||
+ le32_to_cpu(eahd->descTag.tagLocation) !=
+ iinfo->i_location.logicalBlockNum)
return NULL;
- }
if (type < 2048)
offset = sizeof(struct extendedAttrHeaderDesc);
else
offset = le32_to_cpu(eahd->appAttrLocation);
- while (offset < UDF_I_LENEATTR(inode)) {
+ while (offset < iinfo->i_lenEAttr) {
gaf = (struct genericFormat *)&ea[offset];
- if (le32_to_cpu(gaf->attrType) == type && gaf->attrSubtype == subtype)
+ if (le32_to_cpu(gaf->attrType) == type &&
+ gaf->attrSubtype == subtype)
return gaf;
else
offset += le32_to_cpu(gaf->attrLength);
* Written, tested, and released.
*/
struct buffer_head *udf_read_tagged(struct super_block *sb, uint32_t block,
- uint32_t location, uint16_t * ident)
+ uint32_t location, uint16_t *ident)
{
tag *tag_p;
struct buffer_head *bh = NULL;
- register uint8_t checksum;
- register int i;
+ struct udf_sb_info *sbi = UDF_SB(sb);
/* Read the block */
if (block == 0xFFFFFFFF)
return NULL;
- bh = udf_tread(sb, block + UDF_SB_SESSION(sb));
+ bh = udf_tread(sb, block + sbi->s_session);
if (!bh) {
udf_debug("block=%d, location=%d: read failed\n",
- block + UDF_SB_SESSION(sb), location);
+ block + sbi->s_session, location);
return NULL;
}
if (location != le32_to_cpu(tag_p->tagLocation)) {
udf_debug("location mismatch block %u, tag %u != %u\n",
- block + UDF_SB_SESSION(sb), le32_to_cpu(tag_p->tagLocation), location);
+ block + sbi->s_session,
+ le32_to_cpu(tag_p->tagLocation), location);
goto error_out;
}
/* Verify the tag checksum */
- checksum = 0U;
- for (i = 0; i < 4; i++)
- checksum += (uint8_t)(bh->b_data[i]);
- for (i = 5; i < 16; i++)
- checksum += (uint8_t)(bh->b_data[i]);
- if (checksum != tag_p->tagChecksum) {
+ if (udf_tag_checksum(tag_p) != tag_p->tagChecksum) {
printk(KERN_ERR "udf: tag checksum failed block %d\n", block);
goto error_out;
}
/* Verify the tag version */
- if (le16_to_cpu(tag_p->descVersion) != 0x0002U &&
- le16_to_cpu(tag_p->descVersion) != 0x0003U) {
+ if (tag_p->descVersion != cpu_to_le16(0x0002U) &&
+ tag_p->descVersion != cpu_to_le16(0x0003U)) {
udf_debug("tag version 0x%04x != 0x0002 || 0x0003 block %d\n",
le16_to_cpu(tag_p->descVersion), block);
goto error_out;
/* Verify the descriptor CRC */
if (le16_to_cpu(tag_p->descCRCLength) + sizeof(tag) > sb->s_blocksize ||
le16_to_cpu(tag_p->descCRC) == udf_crc(bh->b_data + sizeof(tag),
- le16_to_cpu(tag_p->descCRCLength), 0)) {
+ le16_to_cpu(tag_p->descCRCLength), 0))
return bh;
- }
+
udf_debug("Crc failure block %d: crc = %d, crclen = %d\n",
- block + UDF_SB_SESSION(sb), le16_to_cpu(tag_p->descCRC),
+ block + sbi->s_session, le16_to_cpu(tag_p->descCRC),
le16_to_cpu(tag_p->descCRCLength));
error_out:
}
struct buffer_head *udf_read_ptagged(struct super_block *sb, kernel_lb_addr loc,
- uint32_t offset, uint16_t * ident)
+ uint32_t offset, uint16_t *ident)
{
return udf_read_tagged(sb, udf_get_lb_pblock(sb, loc, offset),
loc.logicalBlockNum + offset, ident);
void udf_update_tag(char *data, int length)
{
tag *tptr = (tag *)data;
- int i;
-
length -= sizeof(tag);
- tptr->tagChecksum = 0;
tptr->descCRCLength = cpu_to_le16(length);
tptr->descCRC = cpu_to_le16(udf_crc(data + sizeof(tag), length, 0));
-
- for (i = 0; i < 16; i++)
- if (i != 4)
- tptr->tagChecksum += (uint8_t)(data[i]);
+ tptr->tagChecksum = udf_tag_checksum(tptr);
}
void udf_new_tag(char *data, uint16_t ident, uint16_t version, uint16_t snum,
tptr->tagLocation = cpu_to_le32(loc);
udf_update_tag(data, length);
}
+
+u8 udf_tag_checksum(const tag *t)
+{
+ u8 *data = (u8 *)t;
+ u8 checksum = 0;
+ int i;
+ for (i = 0; i < sizeof(tag); ++i)
+ if (i != 4) /* position of checksum */
+ checksum += data[i];
+ return checksum;
+}
int udf_write_fi(struct inode *inode, struct fileIdentDesc *cfi,
struct fileIdentDesc *sfi, struct udf_fileident_bh *fibh,
- uint8_t * impuse, uint8_t * fileident)
+ uint8_t *impuse, uint8_t *fileident)
{
uint16_t crclen = fibh->eoffset - fibh->soffset - sizeof(tag);
uint16_t crc;
- uint8_t checksum = 0;
- int i;
int offset;
uint16_t liu = le16_to_cpu(cfi->lengthOfImpUse);
uint8_t lfi = cfi->lengthFileIdent;
sizeof(struct fileIdentDesc);
int adinicb = 0;
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
+ if (UDF_I(inode)->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
adinicb = 1;
offset = fibh->soffset + sizeof(struct fileIdentDesc);
memcpy(fibh->ebh->b_data + offset, impuse, liu);
} else {
memcpy((uint8_t *)sfi->impUse, impuse, -offset);
- memcpy(fibh->ebh->b_data, impuse - offset, liu + offset);
+ memcpy(fibh->ebh->b_data, impuse - offset,
+ liu + offset);
}
}
} else if (offset >= 0) {
memcpy(fibh->ebh->b_data + offset, fileident, lfi);
} else {
- memcpy((uint8_t *)sfi->fileIdent + liu, fileident, -offset);
- memcpy(fibh->ebh->b_data, fileident - offset, lfi + offset);
+ memcpy((uint8_t *)sfi->fileIdent + liu, fileident,
+ -offset);
+ memcpy(fibh->ebh->b_data, fileident - offset,
+ lfi + offset);
}
}
if (fibh->sbh == fibh->ebh) {
crc = udf_crc((uint8_t *)sfi->impUse,
- crclen + sizeof(tag) - sizeof(struct fileIdentDesc), crc);
+ crclen + sizeof(tag) -
+ sizeof(struct fileIdentDesc), crc);
} else if (sizeof(struct fileIdentDesc) >= -fibh->soffset) {
- crc = udf_crc(fibh->ebh->b_data + sizeof(struct fileIdentDesc) + fibh->soffset,
- crclen + sizeof(tag) - sizeof(struct fileIdentDesc), crc);
+ crc = udf_crc(fibh->ebh->b_data +
+ sizeof(struct fileIdentDesc) +
+ fibh->soffset,
+ crclen + sizeof(tag) -
+ sizeof(struct fileIdentDesc),
+ crc);
} else {
crc = udf_crc((uint8_t *)sfi->impUse,
- -fibh->soffset - sizeof(struct fileIdentDesc), crc);
+ -fibh->soffset - sizeof(struct fileIdentDesc),
+ crc);
crc = udf_crc(fibh->ebh->b_data, fibh->eoffset, crc);
}
cfi->descTag.descCRC = cpu_to_le16(crc);
cfi->descTag.descCRCLength = cpu_to_le16(crclen);
+ cfi->descTag.tagChecksum = udf_tag_checksum(&cfi->descTag);
- for (i = 0; i < 16; i++) {
- if (i != 4)
- checksum += ((uint8_t *)&cfi->descTag)[i];
- }
-
- cfi->descTag.tagChecksum = checksum;
if (adinicb || (sizeof(struct fileIdentDesc) <= -fibh->soffset)) {
- memcpy((uint8_t *)sfi, (uint8_t *)cfi, sizeof(struct fileIdentDesc));
+ memcpy((uint8_t *)sfi, (uint8_t *)cfi,
+ sizeof(struct fileIdentDesc));
} else {
memcpy((uint8_t *)sfi, (uint8_t *)cfi, -fibh->soffset);
memcpy(fibh->ebh->b_data, (uint8_t *)cfi - fibh->soffset,
uint32_t elen;
sector_t offset;
struct extent_position epos = {};
+ struct udf_inode_info *dinfo = UDF_I(dir);
- size = (udf_ext0_offset(dir) + dir->i_size) >> 2;
- f_pos = (udf_ext0_offset(dir) >> 2);
+ size = udf_ext0_offset(dir) + dir->i_size;
+ f_pos = udf_ext0_offset(dir);
- fibh->soffset = fibh->eoffset = (f_pos & ((dir->i_sb->s_blocksize - 1) >> 2)) << 2;
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB) {
+ fibh->soffset = fibh->eoffset = f_pos & (dir->i_sb->s_blocksize - 1);
+ if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
fibh->sbh = fibh->ebh = NULL;
- } else if (inode_bmap(dir, f_pos >> (dir->i_sb->s_blocksize_bits - 2),
- &epos, &eloc, &elen, &offset) == (EXT_RECORDED_ALLOCATED >> 30)) {
+ else if (inode_bmap(dir, f_pos >> dir->i_sb->s_blocksize_bits,
+ &epos, &eloc, &elen, &offset) ==
+ (EXT_RECORDED_ALLOCATED >> 30)) {
block = udf_get_lb_pblock(dir->i_sb, eloc, offset);
if ((++offset << dir->i_sb->s_blocksize_bits) < elen) {
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_SHORT)
+ if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
epos.offset -= sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_LONG)
+ else if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
epos.offset -= sizeof(long_ad);
- } else {
+ } else
offset = 0;
- }
- if (!(fibh->sbh = fibh->ebh = udf_tread(dir->i_sb, block))) {
+ fibh->sbh = fibh->ebh = udf_tread(dir->i_sb, block);
+ if (!fibh->sbh) {
brelse(epos.bh);
return NULL;
}
return NULL;
}
- while ((f_pos < size)) {
+ while (f_pos < size) {
fi = udf_fileident_read(dir, &f_pos, fibh, cfi, &epos, &eloc,
&elen, &offset);
if (!fi) {
} else {
int poffset; /* Unpaded ending offset */
- poffset = fibh->soffset + sizeof(struct fileIdentDesc) + liu + lfi;
+ poffset = fibh->soffset + sizeof(struct fileIdentDesc) +
+ liu + lfi;
- if (poffset >= lfi) {
- nameptr = (uint8_t *)(fibh->ebh->b_data + poffset - lfi);
- } else {
+ if (poffset >= lfi)
+ nameptr = (uint8_t *)(fibh->ebh->b_data +
+ poffset - lfi);
+ else {
nameptr = fname;
- memcpy(nameptr, fi->fileIdent + liu, lfi - poffset);
- memcpy(nameptr + lfi - poffset, fibh->ebh->b_data, poffset);
+ memcpy(nameptr, fi->fileIdent + liu,
+ lfi - poffset);
+ memcpy(nameptr + lfi - poffset,
+ fibh->ebh->b_data, poffset);
}
}
if (!lfi)
continue;
- if ((flen = udf_get_filename(dir->i_sb, nameptr, fname, lfi))) {
- if (udf_match(flen, fname, dentry->d_name.len, dentry->d_name.name)) {
- brelse(epos.bh);
- return fi;
- }
+ flen = udf_get_filename(dir->i_sb, nameptr, fname, lfi);
+ if (flen && udf_match(flen, fname, dentry->d_name.len,
+ dentry->d_name.name)) {
+ brelse(epos.bh);
+ return fi;
}
}
if (!strncmp(dentry->d_name.name, ".B=", 3)) {
kernel_lb_addr lb = {
.logicalBlockNum = 0,
- .partitionReferenceNum = simple_strtoul(dentry->d_name.name + 3,
- NULL, 0),
+ .partitionReferenceNum =
+ simple_strtoul(dentry->d_name.name + 3,
+ NULL, 0),
};
inode = udf_iget(dir->i_sb, lb);
if (!inode) {
unlock_kernel();
return ERR_PTR(-EACCES);
}
- }
- else
+ } else
#endif /* UDF_RECOVERY */
if (udf_find_entry(dir, dentry, &fibh, &cfi)) {
struct udf_fileident_bh *fibh,
struct fileIdentDesc *cfi, int *err)
{
- struct super_block *sb;
+ struct super_block *sb = dir->i_sb;
struct fileIdentDesc *fi = NULL;
char name[UDF_NAME_LEN], fname[UDF_NAME_LEN];
int namelen;
loff_t f_pos;
int flen;
char *nameptr;
- loff_t size = (udf_ext0_offset(dir) + dir->i_size) >> 2;
+ loff_t size = udf_ext0_offset(dir) + dir->i_size;
int nfidlen;
uint8_t lfi;
uint16_t liu;
uint32_t elen;
sector_t offset;
struct extent_position epos = {};
-
- sb = dir->i_sb;
+ struct udf_inode_info *dinfo;
if (dentry) {
if (!dentry->d_name.len) {
*err = -EINVAL;
return NULL;
}
- if (!(namelen = udf_put_filename(sb, dentry->d_name.name, name,
- dentry->d_name.len))) {
+ namelen = udf_put_filename(sb, dentry->d_name.name, name,
+ dentry->d_name.len);
+ if (!namelen) {
*err = -ENAMETOOLONG;
return NULL;
}
nfidlen = (sizeof(struct fileIdentDesc) + namelen + 3) & ~3;
- f_pos = (udf_ext0_offset(dir) >> 2);
+ f_pos = udf_ext0_offset(dir);
- fibh->soffset = fibh->eoffset = (f_pos & ((dir->i_sb->s_blocksize - 1) >> 2)) << 2;
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB) {
+ fibh->soffset = fibh->eoffset = f_pos & (dir->i_sb->s_blocksize - 1);
+ dinfo = UDF_I(dir);
+ if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
fibh->sbh = fibh->ebh = NULL;
- } else if (inode_bmap(dir, f_pos >> (dir->i_sb->s_blocksize_bits - 2),
- &epos, &eloc, &elen, &offset) == (EXT_RECORDED_ALLOCATED >> 30)) {
+ else if (inode_bmap(dir, f_pos >> dir->i_sb->s_blocksize_bits,
+ &epos, &eloc, &elen, &offset) ==
+ (EXT_RECORDED_ALLOCATED >> 30)) {
block = udf_get_lb_pblock(dir->i_sb, eloc, offset);
if ((++offset << dir->i_sb->s_blocksize_bits) < elen) {
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_SHORT)
+ if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
epos.offset -= sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_LONG)
+ else if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
epos.offset -= sizeof(long_ad);
- } else {
+ } else
offset = 0;
- }
- if (!(fibh->sbh = fibh->ebh = udf_tread(dir->i_sb, block))) {
+ fibh->sbh = fibh->ebh = udf_tread(dir->i_sb, block);
+ if (!fibh->sbh) {
brelse(epos.bh);
*err = -EIO;
return NULL;
}
- block = UDF_I_LOCATION(dir).logicalBlockNum;
-
+ block = dinfo->i_location.logicalBlockNum;
} else {
- block = udf_get_lb_pblock(dir->i_sb, UDF_I_LOCATION(dir), 0);
+ block = udf_get_lb_pblock(dir->i_sb, dinfo->i_location, 0);
fibh->sbh = fibh->ebh = NULL;
fibh->soffset = fibh->eoffset = sb->s_blocksize;
goto add;
}
- while ((f_pos < size)) {
+ while (f_pos < size) {
fi = udf_fileident_read(dir, &f_pos, fibh, cfi, &epos, &eloc,
&elen, &offset);
liu = le16_to_cpu(cfi->lengthOfImpUse);
lfi = cfi->lengthFileIdent;
- if (fibh->sbh == fibh->ebh) {
+ if (fibh->sbh == fibh->ebh)
nameptr = fi->fileIdent + liu;
- } else {
+ else {
int poffset; /* Unpaded ending offset */
- poffset = fibh->soffset + sizeof(struct fileIdentDesc) + liu + lfi;
+ poffset = fibh->soffset + sizeof(struct fileIdentDesc) +
+ liu + lfi;
- if (poffset >= lfi) {
- nameptr = (char *)(fibh->ebh->b_data + poffset - lfi);
- } else {
+ if (poffset >= lfi)
+ nameptr = (char *)(fibh->ebh->b_data +
+ poffset - lfi);
+ else {
nameptr = fname;
- memcpy(nameptr, fi->fileIdent + liu, lfi - poffset);
- memcpy(nameptr + lfi - poffset, fibh->ebh->b_data, poffset);
+ memcpy(nameptr, fi->fileIdent + liu,
+ lfi - poffset);
+ memcpy(nameptr + lfi - poffset,
+ fibh->ebh->b_data, poffset);
}
}
if ((cfi->fileCharacteristics & FID_FILE_CHAR_DELETED) != 0) {
- if (((sizeof(struct fileIdentDesc) + liu + lfi + 3) & ~3) == nfidlen) {
+ if (((sizeof(struct fileIdentDesc) +
+ liu + lfi + 3) & ~3) == nfidlen) {
brelse(epos.bh);
cfi->descTag.tagSerialNum = cpu_to_le16(1);
cfi->fileVersionNum = cpu_to_le16(1);
cfi->fileCharacteristics = 0;
cfi->lengthFileIdent = namelen;
cfi->lengthOfImpUse = cpu_to_le16(0);
- if (!udf_write_fi(dir, cfi, fi, fibh, NULL, name)) {
+ if (!udf_write_fi(dir, cfi, fi, fibh, NULL,
+ name))
return fi;
- } else {
+ else {
*err = -EIO;
return NULL;
}
if (!lfi || !dentry)
continue;
- if ((flen = udf_get_filename(dir->i_sb, nameptr, fname, lfi)) &&
- udf_match(flen, fname, dentry->d_name.len, dentry->d_name.name)) {
+ flen = udf_get_filename(dir->i_sb, nameptr, fname, lfi);
+ if (flen && udf_match(flen, fname, dentry->d_name.len,
+ dentry->d_name.name)) {
if (fibh->sbh != fibh->ebh)
brelse(fibh->ebh);
brelse(fibh->sbh);
}
add:
+ if (dinfo->i_alloc_type != ICBTAG_FLAG_AD_IN_ICB) {
+ elen = (elen + sb->s_blocksize - 1) & ~(sb->s_blocksize - 1);
+ if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
+ epos.offset -= sizeof(short_ad);
+ else if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
+ epos.offset -= sizeof(long_ad);
+ udf_write_aext(dir, &epos, eloc, elen, 1);
+ }
f_pos += nfidlen;
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB &&
+ if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB &&
sb->s_blocksize - fibh->eoffset < nfidlen) {
brelse(epos.bh);
epos.bh = NULL;
fibh->soffset -= udf_ext0_offset(dir);
fibh->eoffset -= udf_ext0_offset(dir);
- f_pos -= (udf_ext0_offset(dir) >> 2);
+ f_pos -= udf_ext0_offset(dir);
if (fibh->sbh != fibh->ebh)
brelse(fibh->ebh);
brelse(fibh->sbh);
- if (!(fibh->sbh = fibh->ebh = udf_expand_dir_adinicb(dir, &block, err)))
+ fibh->sbh = fibh->ebh =
+ udf_expand_dir_adinicb(dir, &block, err);
+ if (!fibh->sbh)
return NULL;
- epos.block = UDF_I_LOCATION(dir);
- eloc.logicalBlockNum = block;
- eloc.partitionReferenceNum = UDF_I_LOCATION(dir).partitionReferenceNum;
- elen = dir->i_sb->s_blocksize;
+ epos.block = dinfo->i_location;
epos.offset = udf_file_entry_alloc_offset(dir);
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_SHORT)
- epos.offset += sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_LONG)
- epos.offset += sizeof(long_ad);
+ /* Load extent udf_expand_dir_adinicb() has created */
+ udf_current_aext(dir, &epos, &eloc, &elen, 1);
}
if (sb->s_blocksize - fibh->eoffset >= nfidlen) {
fibh->sbh = fibh->ebh;
}
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB) {
- block = UDF_I_LOCATION(dir).logicalBlockNum;
- fi = (struct fileIdentDesc *)(UDF_I_DATA(dir) + fibh->soffset -
- udf_ext0_offset(dir) +
- UDF_I_LENEATTR(dir));
+ if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
+ block = dinfo->i_location.logicalBlockNum;
+ fi = (struct fileIdentDesc *)
+ (dinfo->i_ext.i_data +
+ fibh->soffset -
+ udf_ext0_offset(dir) +
+ dinfo->i_lenEAttr);
} else {
- block = eloc.logicalBlockNum + ((elen - 1) >>
- dir->i_sb->s_blocksize_bits);
- fi = (struct fileIdentDesc *)(fibh->sbh->b_data + fibh->soffset);
+ block = eloc.logicalBlockNum +
+ ((elen - 1) >>
+ dir->i_sb->s_blocksize_bits);
+ fi = (struct fileIdentDesc *)
+ (fibh->sbh->b_data + fibh->soffset);
}
} else {
fibh->soffset = fibh->eoffset - sb->s_blocksize;
block = eloc.logicalBlockNum + ((elen - 1) >>
dir->i_sb->s_blocksize_bits);
- fibh->ebh = udf_bread(dir, f_pos >> (dir->i_sb->s_blocksize_bits - 2), 1, err);
+ fibh->ebh = udf_bread(dir,
+ f_pos >> dir->i_sb->s_blocksize_bits, 1, err);
if (!fibh->ebh) {
brelse(epos.bh);
brelse(fibh->sbh);
(EXT_RECORDED_ALLOCATED >> 30)) {
block = eloc.logicalBlockNum + ((elen - 1) >>
dir->i_sb->s_blocksize_bits);
- } else {
+ } else
block++;
- }
brelse(fibh->sbh);
fibh->sbh = fibh->ebh;
fi = (struct fileIdentDesc *)(fibh->sbh->b_data);
} else {
fi = (struct fileIdentDesc *)
- (fibh->sbh->b_data + sb->s_blocksize + fibh->soffset);
+ (fibh->sbh->b_data + sb->s_blocksize +
+ fibh->soffset);
}
}
memset(cfi, 0, sizeof(struct fileIdentDesc));
- if (UDF_SB_UDFREV(sb) >= 0x0200)
- udf_new_tag((char *)cfi, TAG_IDENT_FID, 3, 1, block, sizeof(tag));
+ if (UDF_SB(sb)->s_udfrev >= 0x0200)
+ udf_new_tag((char *)cfi, TAG_IDENT_FID, 3, 1, block,
+ sizeof(tag));
else
- udf_new_tag((char *)cfi, TAG_IDENT_FID, 2, 1, block, sizeof(tag));
+ udf_new_tag((char *)cfi, TAG_IDENT_FID, 2, 1, block,
+ sizeof(tag));
cfi->fileVersionNum = cpu_to_le16(1);
cfi->lengthFileIdent = namelen;
cfi->lengthOfImpUse = cpu_to_le16(0);
if (!udf_write_fi(dir, cfi, fi, fibh, NULL, name)) {
brelse(epos.bh);
dir->i_size += nfidlen;
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB)
- UDF_I_LENALLOC(dir) += nfidlen;
+ if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
+ dinfo->i_lenAlloc += nfidlen;
mark_inode_dirty(dir);
return fi;
} else {
struct inode *inode;
struct fileIdentDesc cfi, *fi;
int err;
+ struct udf_inode_info *iinfo;
lock_kernel();
inode = udf_new_inode(dir, mode, &err);
return err;
}
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
+ iinfo = UDF_I(inode);
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
inode->i_data.a_ops = &udf_adinicb_aops;
else
inode->i_data.a_ops = &udf_aops;
inode->i_mode = mode;
mark_inode_dirty(inode);
- if (!(fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err))) {
+ fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err);
+ if (!fi) {
inode->i_nlink--;
mark_inode_dirty(inode);
iput(inode);
return err;
}
cfi.icb.extLength = cpu_to_le32(inode->i_sb->s_blocksize);
- cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(inode));
+ cfi.icb.extLocation = cpu_to_lelb(iinfo->i_location);
*(__le32 *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
- cpu_to_le32(UDF_I_UNIQUE(inode) & 0x00000000FFFFFFFFUL);
+ cpu_to_le32(iinfo->i_unique & 0x00000000FFFFFFFFUL);
udf_write_fi(dir, &cfi, fi, &fibh, NULL, NULL);
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB) {
+ if (UDF_I(dir)->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
mark_inode_dirty(dir);
- }
if (fibh.sbh != fibh.ebh)
brelse(fibh.ebh);
brelse(fibh.sbh);
struct udf_fileident_bh fibh;
struct fileIdentDesc cfi, *fi;
int err;
+ struct udf_inode_info *iinfo;
if (!old_valid_dev(rdev))
return -EINVAL;
if (!inode)
goto out;
+ iinfo = UDF_I(inode);
inode->i_uid = current->fsuid;
init_special_inode(inode, mode, rdev);
- if (!(fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err))) {
+ fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err);
+ if (!fi) {
inode->i_nlink--;
mark_inode_dirty(inode);
iput(inode);
return err;
}
cfi.icb.extLength = cpu_to_le32(inode->i_sb->s_blocksize);
- cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(inode));
+ cfi.icb.extLocation = cpu_to_lelb(iinfo->i_location);
*(__le32 *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
- cpu_to_le32(UDF_I_UNIQUE(inode) & 0x00000000FFFFFFFFUL);
+ cpu_to_le32(iinfo->i_unique & 0x00000000FFFFFFFFUL);
udf_write_fi(dir, &cfi, fi, &fibh, NULL, NULL);
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB) {
+ if (UDF_I(dir)->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
mark_inode_dirty(dir);
- }
mark_inode_dirty(inode);
if (fibh.sbh != fibh.ebh)
struct udf_fileident_bh fibh;
struct fileIdentDesc cfi, *fi;
int err;
+ struct udf_inode_info *dinfo = UDF_I(dir);
+ struct udf_inode_info *iinfo;
lock_kernel();
err = -EMLINK;
if (!inode)
goto out;
+ iinfo = UDF_I(inode);
inode->i_op = &udf_dir_inode_operations;
inode->i_fop = &udf_dir_operations;
- if (!(fi = udf_add_entry(inode, NULL, &fibh, &cfi, &err))) {
+ fi = udf_add_entry(inode, NULL, &fibh, &cfi, &err);
+ if (!fi) {
inode->i_nlink--;
mark_inode_dirty(inode);
iput(inode);
}
inode->i_nlink = 2;
cfi.icb.extLength = cpu_to_le32(inode->i_sb->s_blocksize);
- cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(dir));
+ cfi.icb.extLocation = cpu_to_lelb(dinfo->i_location);
*(__le32 *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
- cpu_to_le32(UDF_I_UNIQUE(dir) & 0x00000000FFFFFFFFUL);
- cfi.fileCharacteristics = FID_FILE_CHAR_DIRECTORY | FID_FILE_CHAR_PARENT;
+ cpu_to_le32(dinfo->i_unique & 0x00000000FFFFFFFFUL);
+ cfi.fileCharacteristics =
+ FID_FILE_CHAR_DIRECTORY | FID_FILE_CHAR_PARENT;
udf_write_fi(inode, &cfi, fi, &fibh, NULL, NULL);
brelse(fibh.sbh);
inode->i_mode = S_IFDIR | mode;
inode->i_mode |= S_ISGID;
mark_inode_dirty(inode);
- if (!(fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err))) {
+ fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err);
+ if (!fi) {
inode->i_nlink = 0;
mark_inode_dirty(inode);
iput(inode);
goto out;
}
cfi.icb.extLength = cpu_to_le32(inode->i_sb->s_blocksize);
- cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(inode));
+ cfi.icb.extLocation = cpu_to_lelb(iinfo->i_location);
*(__le32 *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
- cpu_to_le32(UDF_I_UNIQUE(inode) & 0x00000000FFFFFFFFUL);
+ cpu_to_le32(iinfo->i_unique & 0x00000000FFFFFFFFUL);
cfi.fileCharacteristics |= FID_FILE_CHAR_DIRECTORY;
udf_write_fi(dir, &cfi, fi, &fibh, NULL, NULL);
inc_nlink(dir);
struct fileIdentDesc *fi, cfi;
struct udf_fileident_bh fibh;
loff_t f_pos;
- loff_t size = (udf_ext0_offset(dir) + dir->i_size) >> 2;
+ loff_t size = udf_ext0_offset(dir) + dir->i_size;
int block;
kernel_lb_addr eloc;
uint32_t elen;
sector_t offset;
struct extent_position epos = {};
+ struct udf_inode_info *dinfo = UDF_I(dir);
- f_pos = (udf_ext0_offset(dir) >> 2);
+ f_pos = udf_ext0_offset(dir);
+ fibh.soffset = fibh.eoffset = f_pos & (dir->i_sb->s_blocksize - 1);
- fibh.soffset = fibh.eoffset = (f_pos & ((dir->i_sb->s_blocksize - 1) >> 2)) << 2;
-
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB) {
+ if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
fibh.sbh = fibh.ebh = NULL;
- } else if (inode_bmap(dir, f_pos >> (dir->i_sb->s_blocksize_bits - 2),
- &epos, &eloc, &elen, &offset) == (EXT_RECORDED_ALLOCATED >> 30)) {
+ else if (inode_bmap(dir, f_pos >> dir->i_sb->s_blocksize_bits,
+ &epos, &eloc, &elen, &offset) ==
+ (EXT_RECORDED_ALLOCATED >> 30)) {
block = udf_get_lb_pblock(dir->i_sb, eloc, offset);
if ((++offset << dir->i_sb->s_blocksize_bits) < elen) {
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_SHORT)
+ if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
epos.offset -= sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_LONG)
+ else if (dinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
epos.offset -= sizeof(long_ad);
- } else {
+ } else
offset = 0;
- }
- if (!(fibh.sbh = fibh.ebh = udf_tread(dir->i_sb, block))) {
+ fibh.sbh = fibh.ebh = udf_tread(dir->i_sb, block);
+ if (!fibh.sbh) {
brelse(epos.bh);
return 0;
}
return 0;
}
- while ((f_pos < size)) {
+ while (f_pos < size) {
fi = udf_fileident_read(dir, &f_pos, &fibh, &cfi, &epos, &eloc,
&elen, &offset);
if (!fi) {
clear_nlink(inode);
inode->i_size = 0;
inode_dec_link_count(dir);
- inode->i_ctime = dir->i_ctime = dir->i_mtime = current_fs_time(dir->i_sb);
+ inode->i_ctime = dir->i_ctime = dir->i_mtime =
+ current_fs_time(dir->i_sb);
mark_inode_dirty(dir);
end_rmdir:
int block;
char name[UDF_NAME_LEN];
int namelen;
+ struct buffer_head *bh;
+ struct udf_inode_info *iinfo;
lock_kernel();
- if (!(inode = udf_new_inode(dir, S_IFLNK, &err)))
+ inode = udf_new_inode(dir, S_IFLNK, &err);
+ if (!inode)
goto out;
+ iinfo = UDF_I(inode);
inode->i_mode = S_IFLNK | S_IRWXUGO;
inode->i_data.a_ops = &udf_symlink_aops;
inode->i_op = &page_symlink_inode_operations;
- if (UDF_I_ALLOCTYPE(inode) != ICBTAG_FLAG_AD_IN_ICB) {
+ if (iinfo->i_alloc_type != ICBTAG_FLAG_AD_IN_ICB) {
kernel_lb_addr eloc;
uint32_t elen;
block = udf_new_block(inode->i_sb, inode,
- UDF_I_LOCATION(inode).partitionReferenceNum,
- UDF_I_LOCATION(inode).logicalBlockNum, &err);
+ iinfo->i_location.partitionReferenceNum,
+ iinfo->i_location.logicalBlockNum, &err);
if (!block)
goto out_no_entry;
- epos.block = UDF_I_LOCATION(inode);
+ epos.block = iinfo->i_location;
epos.offset = udf_file_entry_alloc_offset(inode);
epos.bh = NULL;
eloc.logicalBlockNum = block;
- eloc.partitionReferenceNum = UDF_I_LOCATION(inode).partitionReferenceNum;
+ eloc.partitionReferenceNum =
+ iinfo->i_location.partitionReferenceNum;
elen = inode->i_sb->s_blocksize;
- UDF_I_LENEXTENTS(inode) = elen;
+ iinfo->i_lenExtents = elen;
udf_add_aext(inode, &epos, eloc, elen, 0);
brelse(epos.bh);
block = udf_get_pblock(inode->i_sb, block,
- UDF_I_LOCATION(inode).partitionReferenceNum, 0);
+ iinfo->i_location.partitionReferenceNum,
+ 0);
epos.bh = udf_tread(inode->i_sb, block);
lock_buffer(epos.bh);
memset(epos.bh->b_data, 0x00, inode->i_sb->s_blocksize);
unlock_buffer(epos.bh);
mark_buffer_dirty_inode(epos.bh, inode);
ea = epos.bh->b_data + udf_ext0_offset(inode);
- } else {
- ea = UDF_I_DATA(inode) + UDF_I_LENEATTR(inode);
- }
+ } else
+ ea = iinfo->i_ext.i_data + iinfo->i_lenEAttr;
eoffset = inode->i_sb->s_blocksize - udf_ext0_offset(inode);
pc = (struct pathComponent *)ea;
if (compstart[0] == '.') {
if ((symname - compstart) == 1)
pc->componentType = 4;
- else if ((symname - compstart) == 2 && compstart[1] == '.')
+ else if ((symname - compstart) == 2 &&
+ compstart[1] == '.')
pc->componentType = 3;
}
if (!namelen)
goto out_no_entry;
- if (elen + sizeof(struct pathComponent) + namelen > eoffset)
+ if (elen + sizeof(struct pathComponent) + namelen >
+ eoffset)
goto out_no_entry;
else
pc->lengthComponentIdent = namelen;
brelse(epos.bh);
inode->i_size = elen;
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
- UDF_I_LENALLOC(inode) = inode->i_size;
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
+ iinfo->i_lenAlloc = inode->i_size;
mark_inode_dirty(inode);
- if (!(fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err)))
+ fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err);
+ if (!fi)
goto out_no_entry;
cfi.icb.extLength = cpu_to_le32(inode->i_sb->s_blocksize);
- cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(inode));
- if (UDF_SB_LVIDBH(inode->i_sb)) {
+ cfi.icb.extLocation = cpu_to_lelb(iinfo->i_location);
+ bh = UDF_SB(inode->i_sb)->s_lvid_bh;
+ if (bh) {
+ struct logicalVolIntegrityDesc *lvid =
+ (struct logicalVolIntegrityDesc *)bh->b_data;
struct logicalVolHeaderDesc *lvhd;
uint64_t uniqueID;
- lvhd = (struct logicalVolHeaderDesc *)(UDF_SB_LVID(inode->i_sb)->logicalVolContentsUse);
+ lvhd = (struct logicalVolHeaderDesc *)
+ lvid->logicalVolContentsUse;
uniqueID = le64_to_cpu(lvhd->uniqueID);
*(__le32 *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
cpu_to_le32(uniqueID & 0x00000000FFFFFFFFUL);
if (!(++uniqueID & 0x00000000FFFFFFFFUL))
uniqueID += 16;
lvhd->uniqueID = cpu_to_le64(uniqueID);
- mark_buffer_dirty(UDF_SB_LVIDBH(inode->i_sb));
+ mark_buffer_dirty(bh);
}
udf_write_fi(dir, &cfi, fi, &fibh, NULL, NULL);
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB) {
+ if (UDF_I(dir)->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
mark_inode_dirty(dir);
- }
if (fibh.sbh != fibh.ebh)
brelse(fibh.ebh);
brelse(fibh.sbh);
struct udf_fileident_bh fibh;
struct fileIdentDesc cfi, *fi;
int err;
+ struct buffer_head *bh;
lock_kernel();
if (inode->i_nlink >= (256 << sizeof(inode->i_nlink)) - 1) {
return -EMLINK;
}
- if (!(fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err))) {
+ fi = udf_add_entry(dir, dentry, &fibh, &cfi, &err);
+ if (!fi) {
unlock_kernel();
return err;
}
cfi.icb.extLength = cpu_to_le32(inode->i_sb->s_blocksize);
- cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(inode));
- if (UDF_SB_LVIDBH(inode->i_sb)) {
+ cfi.icb.extLocation = cpu_to_lelb(UDF_I(inode)->i_location);
+ bh = UDF_SB(inode->i_sb)->s_lvid_bh;
+ if (bh) {
+ struct logicalVolIntegrityDesc *lvid =
+ (struct logicalVolIntegrityDesc *)bh->b_data;
struct logicalVolHeaderDesc *lvhd;
uint64_t uniqueID;
- lvhd = (struct logicalVolHeaderDesc *)(UDF_SB_LVID(inode->i_sb)->logicalVolContentsUse);
+ lvhd = (struct logicalVolHeaderDesc *)
+ (lvid->logicalVolContentsUse);
uniqueID = le64_to_cpu(lvhd->uniqueID);
*(__le32 *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
cpu_to_le32(uniqueID & 0x00000000FFFFFFFFUL);
if (!(++uniqueID & 0x00000000FFFFFFFFUL))
uniqueID += 16;
lvhd->uniqueID = cpu_to_le64(uniqueID);
- mark_buffer_dirty(UDF_SB_LVIDBH(inode->i_sb));
+ mark_buffer_dirty(bh);
}
udf_write_fi(dir, &cfi, fi, &fibh, NULL, NULL);
- if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB) {
+ if (UDF_I(dir)->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
mark_inode_dirty(dir);
- }
if (fibh.sbh != fibh.ebh)
brelse(fibh.ebh);
struct inode *old_inode = old_dentry->d_inode;
struct inode *new_inode = new_dentry->d_inode;
struct udf_fileident_bh ofibh, nfibh;
- struct fileIdentDesc *ofi = NULL, *nfi = NULL, *dir_fi = NULL, ocfi, ncfi;
+ struct fileIdentDesc *ofi = NULL, *nfi = NULL, *dir_fi = NULL;
+ struct fileIdentDesc ocfi, ncfi;
struct buffer_head *dir_bh = NULL;
int retval = -ENOENT;
kernel_lb_addr tloc;
+ struct udf_inode_info *old_iinfo = UDF_I(old_inode);
lock_kernel();
- if ((ofi = udf_find_entry(old_dir, old_dentry, &ofibh, &ocfi))) {
+ ofi = udf_find_entry(old_dir, old_dentry, &ofibh, &ocfi);
+ if (ofi) {
if (ofibh.sbh != ofibh.ebh)
brelse(ofibh.ebh);
brelse(ofibh.sbh);
}
}
if (S_ISDIR(old_inode->i_mode)) {
- uint32_t offset = udf_ext0_offset(old_inode);
+ int offset = udf_ext0_offset(old_inode);
if (new_inode) {
retval = -ENOTEMPTY;
goto end_rename;
}
retval = -EIO;
- if (UDF_I_ALLOCTYPE(old_inode) == ICBTAG_FLAG_AD_IN_ICB) {
- dir_fi = udf_get_fileident(UDF_I_DATA(old_inode) -
- (UDF_I_EFE(old_inode) ?
- sizeof(struct extendedFileEntry) :
- sizeof(struct fileEntry)),
- old_inode->i_sb->s_blocksize, &offset);
+ if (old_iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
+ dir_fi = udf_get_fileident(
+ old_iinfo->i_ext.i_data -
+ (old_iinfo->i_efe ?
+ sizeof(struct extendedFileEntry) :
+ sizeof(struct fileEntry)),
+ old_inode->i_sb->s_blocksize, &offset);
} else {
dir_bh = udf_bread(old_inode, 0, 0, &retval);
if (!dir_bh)
goto end_rename;
- dir_fi = udf_get_fileident(dir_bh->b_data, old_inode->i_sb->s_blocksize, &offset);
+ dir_fi = udf_get_fileident(dir_bh->b_data,
+ old_inode->i_sb->s_blocksize, &offset);
}
if (!dir_fi)
goto end_rename;
tloc = lelb_to_cpu(dir_fi->icb.extLocation);
- if (udf_get_lb_pblock(old_inode->i_sb, tloc, 0) != old_dir->i_ino)
+ if (udf_get_lb_pblock(old_inode->i_sb, tloc, 0) !=
+ old_dir->i_ino)
goto end_rename;
retval = -EMLINK;
- if (!new_inode && new_dir->i_nlink >= (256 << sizeof(new_dir->i_nlink)) - 1)
+ if (!new_inode &&
+ new_dir->i_nlink >=
+ (256 << sizeof(new_dir->i_nlink)) - 1)
goto end_rename;
}
if (!nfi) {
- nfi = udf_add_entry(new_dir, new_dentry, &nfibh, &ncfi, &retval);
+ nfi = udf_add_entry(new_dir, new_dentry, &nfibh, &ncfi,
+ &retval);
if (!nfi)
goto end_rename;
}
mark_inode_dirty(old_dir);
if (dir_fi) {
- dir_fi->icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(new_dir));
- udf_update_tag((char *)dir_fi, (sizeof(struct fileIdentDesc) +
- le16_to_cpu(dir_fi->lengthOfImpUse) + 3) & ~3);
- if (UDF_I_ALLOCTYPE(old_inode) == ICBTAG_FLAG_AD_IN_ICB) {
+ dir_fi->icb.extLocation = cpu_to_lelb(UDF_I(new_dir)->i_location);
+ udf_update_tag((char *)dir_fi,
+ (sizeof(struct fileIdentDesc) +
+ le16_to_cpu(dir_fi->lengthOfImpUse) + 3) & ~3);
+ if (old_iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB)
mark_inode_dirty(old_inode);
- } else {
+ else
mark_buffer_dirty_inode(dir_bh, old_inode);
- }
+
inode_dec_link_count(old_dir);
- if (new_inode) {
+ if (new_inode)
inode_dec_link_count(new_inode);
- } else {
+ else {
inc_nlink(new_dir);
mark_inode_dirty(new_dir);
}
inline uint32_t udf_get_pblock(struct super_block *sb, uint32_t block,
uint16_t partition, uint32_t offset)
{
- if (partition >= UDF_SB_NUMPARTS(sb)) {
- udf_debug("block=%d, partition=%d, offset=%d: invalid partition\n",
- block, partition, offset);
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct udf_part_map *map;
+ if (partition >= sbi->s_partitions) {
+ udf_debug("block=%d, partition=%d, offset=%d: "
+ "invalid partition\n", block, partition, offset);
return 0xFFFFFFFF;
}
- if (UDF_SB_PARTFUNC(sb, partition))
- return UDF_SB_PARTFUNC(sb, partition)(sb, block, partition, offset);
+ map = &sbi->s_partmaps[partition];
+ if (map->s_partition_func)
+ return map->s_partition_func(sb, block, partition, offset);
else
- return UDF_SB_PARTROOT(sb, partition) + block + offset;
+ return map->s_partition_root + block + offset;
}
uint32_t udf_get_pblock_virt15(struct super_block *sb, uint32_t block,
uint32_t newblock;
uint32_t index;
uint32_t loc;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct udf_part_map *map;
+ struct udf_virtual_data *vdata;
+ struct udf_inode_info *iinfo;
- index = (sb->s_blocksize - UDF_SB_TYPEVIRT(sb,partition).s_start_offset) / sizeof(uint32_t);
+ map = &sbi->s_partmaps[partition];
+ vdata = &map->s_type_specific.s_virtual;
+ index = (sb->s_blocksize - vdata->s_start_offset) / sizeof(uint32_t);
- if (block > UDF_SB_TYPEVIRT(sb,partition).s_num_entries) {
- udf_debug("Trying to access block beyond end of VAT (%d max %d)\n",
- block, UDF_SB_TYPEVIRT(sb,partition).s_num_entries);
+ if (block > vdata->s_num_entries) {
+ udf_debug("Trying to access block beyond end of VAT "
+ "(%d max %d)\n", block, vdata->s_num_entries);
return 0xFFFFFFFF;
}
index = block % (sb->s_blocksize / sizeof(uint32_t));
} else {
newblock = 0;
- index = UDF_SB_TYPEVIRT(sb,partition).s_start_offset / sizeof(uint32_t) + block;
+ index = vdata->s_start_offset / sizeof(uint32_t) + block;
}
- loc = udf_block_map(UDF_SB_VAT(sb), newblock);
+ loc = udf_block_map(sbi->s_vat_inode, newblock);
- if (!(bh = sb_bread(sb, loc))) {
+ bh = sb_bread(sb, loc);
+ if (!bh) {
udf_debug("get_pblock(UDF_VIRTUAL_MAP:%p,%d,%d) VAT: %d[%d]\n",
sb, block, partition, loc, index);
return 0xFFFFFFFF;
brelse(bh);
- if (UDF_I_LOCATION(UDF_SB_VAT(sb)).partitionReferenceNum == partition) {
+ iinfo = UDF_I(sbi->s_vat_inode);
+ if (iinfo->i_location.partitionReferenceNum == partition) {
udf_debug("recursive call to udf_get_pblock!\n");
return 0xFFFFFFFF;
}
return udf_get_pblock(sb, loc,
- UDF_I_LOCATION(UDF_SB_VAT(sb)).partitionReferenceNum,
+ iinfo->i_location.partitionReferenceNum,
offset);
}
-inline uint32_t udf_get_pblock_virt20(struct super_block * sb, uint32_t block,
+inline uint32_t udf_get_pblock_virt20(struct super_block *sb, uint32_t block,
uint16_t partition, uint32_t offset)
{
return udf_get_pblock_virt15(sb, block, partition, offset);
}
-uint32_t udf_get_pblock_spar15(struct super_block * sb, uint32_t block,
+uint32_t udf_get_pblock_spar15(struct super_block *sb, uint32_t block,
uint16_t partition, uint32_t offset)
{
int i;
struct sparingTable *st = NULL;
- uint32_t packet = (block + offset) & ~(UDF_SB_TYPESPAR(sb,partition).s_packet_len - 1);
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct udf_part_map *map;
+ uint32_t packet;
+ struct udf_sparing_data *sdata;
+
+ map = &sbi->s_partmaps[partition];
+ sdata = &map->s_type_specific.s_sparing;
+ packet = (block + offset) & ~(sdata->s_packet_len - 1);
for (i = 0; i < 4; i++) {
- if (UDF_SB_TYPESPAR(sb,partition).s_spar_map[i] != NULL) {
- st = (struct sparingTable *)UDF_SB_TYPESPAR(sb,partition).s_spar_map[i]->b_data;
+ if (sdata->s_spar_map[i] != NULL) {
+ st = (struct sparingTable *)
+ sdata->s_spar_map[i]->b_data;
break;
}
}
if (st) {
for (i = 0; i < le16_to_cpu(st->reallocationTableLen); i++) {
- if (le32_to_cpu(st->mapEntry[i].origLocation) >= 0xFFFFFFF0) {
+ struct sparingEntry *entry = &st->mapEntry[i];
+ u32 origLoc = le32_to_cpu(entry->origLocation);
+ if (origLoc >= 0xFFFFFFF0)
break;
- } else if (le32_to_cpu(st->mapEntry[i].origLocation) == packet) {
- return le32_to_cpu(st->mapEntry[i].mappedLocation) +
- ((block + offset) & (UDF_SB_TYPESPAR(sb,partition).s_packet_len - 1));
- } else if (le32_to_cpu(st->mapEntry[i].origLocation) > packet) {
+ else if (origLoc == packet)
+ return le32_to_cpu(entry->mappedLocation) +
+ ((block + offset) &
+ (sdata->s_packet_len - 1));
+ else if (origLoc > packet)
break;
- }
}
}
- return UDF_SB_PARTROOT(sb,partition) + block + offset;
+ return map->s_partition_root + block + offset;
}
int udf_relocate_blocks(struct super_block *sb, long old_block, long *new_block)
struct sparingEntry mapEntry;
uint32_t packet;
int i, j, k, l;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ u16 reallocationTableLen;
+ struct buffer_head *bh;
- for (i = 0; i < UDF_SB_NUMPARTS(sb); i++) {
- if (old_block > UDF_SB_PARTROOT(sb,i) &&
- old_block < UDF_SB_PARTROOT(sb,i) + UDF_SB_PARTLEN(sb,i)) {
- sdata = &UDF_SB_TYPESPAR(sb,i);
- packet = (old_block - UDF_SB_PARTROOT(sb,i)) & ~(sdata->s_packet_len - 1);
+ for (i = 0; i < sbi->s_partitions; i++) {
+ struct udf_part_map *map = &sbi->s_partmaps[i];
+ if (old_block > map->s_partition_root &&
+ old_block < map->s_partition_root + map->s_partition_len) {
+ sdata = &map->s_type_specific.s_sparing;
+ packet = (old_block - map->s_partition_root) &
+ ~(sdata->s_packet_len - 1);
- for (j = 0; j < 4; j++) {
- if (UDF_SB_TYPESPAR(sb,i).s_spar_map[j] != NULL) {
- st = (struct sparingTable *)sdata->s_spar_map[j]->b_data;
+ for (j = 0; j < 4; j++)
+ if (sdata->s_spar_map[j] != NULL) {
+ st = (struct sparingTable *)
+ sdata->s_spar_map[j]->b_data;
break;
}
- }
if (!st)
return 1;
- for (k = 0; k < le16_to_cpu(st->reallocationTableLen); k++) {
- if (le32_to_cpu(st->mapEntry[k].origLocation) == 0xFFFFFFFF) {
+ reallocationTableLen =
+ le16_to_cpu(st->reallocationTableLen);
+ for (k = 0; k < reallocationTableLen; k++) {
+ struct sparingEntry *entry = &st->mapEntry[k];
+ u32 origLoc = le32_to_cpu(entry->origLocation);
+
+ if (origLoc == 0xFFFFFFFF) {
for (; j < 4; j++) {
- if (sdata->s_spar_map[j]) {
- st = (struct sparingTable *)sdata->s_spar_map[j]->b_data;
- st->mapEntry[k].origLocation = cpu_to_le32(packet);
- udf_update_tag((char *)st, sizeof(struct sparingTable) + le16_to_cpu(st->reallocationTableLen) * sizeof(struct sparingEntry));
- mark_buffer_dirty(sdata->s_spar_map[j]);
- }
+ int len;
+ bh = sdata->s_spar_map[j];
+ if (!bh)
+ continue;
+
+ st = (struct sparingTable *)
+ bh->b_data;
+ entry->origLocation =
+ cpu_to_le32(packet);
+ len =
+ sizeof(struct sparingTable) +
+ reallocationTableLen *
+ sizeof(struct sparingEntry);
+ udf_update_tag((char *)st, len);
+ mark_buffer_dirty(bh);
}
- *new_block = le32_to_cpu(st->mapEntry[k].mappedLocation) +
- ((old_block - UDF_SB_PARTROOT(sb,i)) & (sdata->s_packet_len - 1));
+ *new_block = le32_to_cpu(
+ entry->mappedLocation) +
+ ((old_block -
+ map->s_partition_root) &
+ (sdata->s_packet_len - 1));
return 0;
- } else if (le32_to_cpu(st->mapEntry[k].origLocation) == packet) {
- *new_block = le32_to_cpu(st->mapEntry[k].mappedLocation) +
- ((old_block - UDF_SB_PARTROOT(sb,i)) & (sdata->s_packet_len - 1));
+ } else if (origLoc == packet) {
+ *new_block = le32_to_cpu(
+ entry->mappedLocation) +
+ ((old_block -
+ map->s_partition_root) &
+ (sdata->s_packet_len - 1));
return 0;
- } else if (le32_to_cpu(st->mapEntry[k].origLocation) > packet) {
+ } else if (origLoc > packet)
break;
- }
}
- for (l = k; l < le16_to_cpu(st->reallocationTableLen); l++) {
- if (le32_to_cpu(st->mapEntry[l].origLocation) == 0xFFFFFFFF) {
- for (; j < 4; j++) {
- if (sdata->s_spar_map[j]) {
- st = (struct sparingTable *)sdata->s_spar_map[j]->b_data;
- mapEntry = st->mapEntry[l];
- mapEntry.origLocation = cpu_to_le32(packet);
- memmove(&st->mapEntry[k + 1], &st->mapEntry[k], (l - k) * sizeof(struct sparingEntry));
- st->mapEntry[k] = mapEntry;
- udf_update_tag((char *)st, sizeof(struct sparingTable) + le16_to_cpu(st->reallocationTableLen) * sizeof(struct sparingEntry));
- mark_buffer_dirty(sdata->s_spar_map[j]);
- }
- }
- *new_block = le32_to_cpu(st->mapEntry[k].mappedLocation) +
- ((old_block - UDF_SB_PARTROOT(sb,i)) & (sdata->s_packet_len - 1));
- return 0;
+ for (l = k; l < reallocationTableLen; l++) {
+ struct sparingEntry *entry = &st->mapEntry[l];
+ u32 origLoc = le32_to_cpu(entry->origLocation);
+
+ if (origLoc != 0xFFFFFFFF)
+ continue;
+
+ for (; j < 4; j++) {
+ bh = sdata->s_spar_map[j];
+ if (!bh)
+ continue;
+
+ st = (struct sparingTable *)bh->b_data;
+ mapEntry = st->mapEntry[l];
+ mapEntry.origLocation =
+ cpu_to_le32(packet);
+ memmove(&st->mapEntry[k + 1],
+ &st->mapEntry[k],
+ (l - k) *
+ sizeof(struct sparingEntry));
+ st->mapEntry[k] = mapEntry;
+ udf_update_tag((char *)st,
+ sizeof(struct sparingTable) +
+ reallocationTableLen *
+ sizeof(struct sparingEntry));
+ mark_buffer_dirty(bh);
}
+ *new_block =
+ le32_to_cpu(
+ st->mapEntry[k].mappedLocation) +
+ ((old_block - map->s_partition_root) &
+ (sdata->s_packet_len - 1));
+ return 0;
}
return 1;
} /* if old_block */
}
- if (i == UDF_SB_NUMPARTS(sb)) {
+ if (i == sbi->s_partitions) {
/* outside of partitions */
/* for now, fail =) */
return 1;
* 10/17/98 added freespace count for "df"
* 11/11/98 gr added novrs option
* 11/26/98 dgb added fileset,anchor mount options
- * 12/06/98 blf really hosed things royally. vat/sparing support. sequenced vol descs
- * rewrote option handling based on isofs
+ * 12/06/98 blf really hosed things royally. vat/sparing support. sequenced
+ * vol descs. rewrote option handling based on isofs
* 12/20/98 find the free space bitmap (if it exists)
*/
#include <linux/buffer_head.h>
#include <linux/vfs.h>
#include <linux/vmalloc.h>
+#include <linux/errno.h>
+#include <linux/mount.h>
+#include <linux/seq_file.h>
#include <asm/byteorder.h>
#include <linux/udf_fs.h>
#define VDS_POS_TERMINATING_DESC 6
#define VDS_POS_LENGTH 7
+#define UDF_DEFAULT_BLOCKSIZE 2048
+
static char error_buf[1024];
/* These are the "meat" - everything else is stuffing */
static void udf_close_lvid(struct super_block *);
static unsigned int udf_count_free(struct super_block *);
static int udf_statfs(struct dentry *, struct kstatfs *);
+static int udf_show_options(struct seq_file *, struct vfsmount *);
+
+struct logicalVolIntegrityDescImpUse *udf_sb_lvidiu(struct udf_sb_info *sbi)
+{
+ struct logicalVolIntegrityDesc *lvid =
+ (struct logicalVolIntegrityDesc *)sbi->s_lvid_bh->b_data;
+ __u32 number_of_partitions = le32_to_cpu(lvid->numOfPartitions);
+ __u32 offset = number_of_partitions * 2 *
+ sizeof(uint32_t)/sizeof(uint8_t);
+ return (struct logicalVolIntegrityDescImpUse *)&(lvid->impUse[offset]);
+}
/* UDF filesystem type */
static int udf_get_sb(struct file_system_type *fs_type,
static struct inode *udf_alloc_inode(struct super_block *sb)
{
struct udf_inode_info *ei;
- ei = (struct udf_inode_info *)kmem_cache_alloc(udf_inode_cachep, GFP_KERNEL);
+ ei = kmem_cache_alloc(udf_inode_cachep, GFP_KERNEL);
if (!ei)
return NULL;
.write_super = udf_write_super,
.statfs = udf_statfs,
.remount_fs = udf_remount_fs,
+ .show_options = udf_show_options,
};
struct udf_options {
module_init(init_udf_fs)
module_exit(exit_udf_fs)
+static int udf_sb_alloc_partition_maps(struct super_block *sb, u32 count)
+{
+ struct udf_sb_info *sbi = UDF_SB(sb);
+
+ sbi->s_partmaps = kcalloc(count, sizeof(struct udf_part_map),
+ GFP_KERNEL);
+ if (!sbi->s_partmaps) {
+ udf_error(sb, __FUNCTION__,
+ "Unable to allocate space for %d partition maps",
+ count);
+ sbi->s_partitions = 0;
+ return -ENOMEM;
+ }
+
+ sbi->s_partitions = count;
+ return 0;
+}
+
+static int udf_show_options(struct seq_file *seq, struct vfsmount *mnt)
+{
+ struct super_block *sb = mnt->mnt_sb;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+
+ if (!UDF_QUERY_FLAG(sb, UDF_FLAG_STRICT))
+ seq_puts(seq, ",nostrict");
+ if (sb->s_blocksize != UDF_DEFAULT_BLOCKSIZE)
+ seq_printf(seq, ",bs=%lu", sb->s_blocksize);
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_UNHIDE))
+ seq_puts(seq, ",unhide");
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_UNDELETE))
+ seq_puts(seq, ",undelete");
+ if (!UDF_QUERY_FLAG(sb, UDF_FLAG_USE_AD_IN_ICB))
+ seq_puts(seq, ",noadinicb");
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_USE_SHORT_AD))
+ seq_puts(seq, ",shortad");
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_UID_FORGET))
+ seq_puts(seq, ",uid=forget");
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_UID_IGNORE))
+ seq_puts(seq, ",uid=ignore");
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_GID_FORGET))
+ seq_puts(seq, ",gid=forget");
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_GID_IGNORE))
+ seq_puts(seq, ",gid=ignore");
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_UID_SET))
+ seq_printf(seq, ",uid=%u", sbi->s_uid);
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_GID_SET))
+ seq_printf(seq, ",gid=%u", sbi->s_gid);
+ if (sbi->s_umask != 0)
+ seq_printf(seq, ",umask=%o", sbi->s_umask);
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_SESSION_SET))
+ seq_printf(seq, ",session=%u", sbi->s_session);
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_LASTBLOCK_SET))
+ seq_printf(seq, ",lastblock=%u", sbi->s_last_block);
+ /*
+ * s_anchor[2] could be zeroed out in case there is no anchor
+ * in the specified block, but then the "anchor=N" option
+ * originally given by the user wasn't effective, so it's OK
+ * if we don't show it.
+ */
+ if (sbi->s_anchor[2] != 0)
+ seq_printf(seq, ",anchor=%u", sbi->s_anchor[2]);
+ /*
+ * volume, partition, fileset and rootdir seem to be ignored
+ * currently
+ */
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_UTF8))
+ seq_puts(seq, ",utf8");
+ if (UDF_QUERY_FLAG(sb, UDF_FLAG_NLS_MAP) && sbi->s_nls_map)
+ seq_printf(seq, ",iocharset=%s", sbi->s_nls_map->charset);
+
+ return 0;
+}
+
/*
* udf_parse_options
*
{Opt_err, NULL}
};
-static int udf_parse_options(char *options, struct udf_options *uopt)
+static int udf_parse_options(char *options, struct udf_options *uopt,
+ bool remount)
{
char *p;
int option;
uopt->novrs = 0;
- uopt->blocksize = 2048;
+ uopt->blocksize = UDF_DEFAULT_BLOCKSIZE;
uopt->partition = 0xFFFF;
uopt->session = 0xFFFFFFFF;
uopt->lastblock = 0;
if (match_int(args, &option))
return 0;
uopt->session = option;
+ if (!remount)
+ uopt->flags |= (1 << UDF_FLAG_SESSION_SET);
break;
case Opt_lastblock:
if (match_int(args, &option))
return 0;
uopt->lastblock = option;
+ if (!remount)
+ uopt->flags |= (1 << UDF_FLAG_LASTBLOCK_SET);
break;
case Opt_anchor:
if (match_int(args, &option))
return 1;
}
-void udf_write_super(struct super_block *sb)
+static void udf_write_super(struct super_block *sb)
{
lock_kernel();
static int udf_remount_fs(struct super_block *sb, int *flags, char *options)
{
struct udf_options uopt;
+ struct udf_sb_info *sbi = UDF_SB(sb);
- uopt.flags = UDF_SB(sb)->s_flags;
- uopt.uid = UDF_SB(sb)->s_uid;
- uopt.gid = UDF_SB(sb)->s_gid;
- uopt.umask = UDF_SB(sb)->s_umask;
+ uopt.flags = sbi->s_flags;
+ uopt.uid = sbi->s_uid;
+ uopt.gid = sbi->s_gid;
+ uopt.umask = sbi->s_umask;
- if (!udf_parse_options(options, &uopt))
+ if (!udf_parse_options(options, &uopt, true))
return -EINVAL;
- UDF_SB(sb)->s_flags = uopt.flags;
- UDF_SB(sb)->s_uid = uopt.uid;
- UDF_SB(sb)->s_gid = uopt.gid;
- UDF_SB(sb)->s_umask = uopt.umask;
+ sbi->s_flags = uopt.flags;
+ sbi->s_uid = uopt.uid;
+ sbi->s_gid = uopt.gid;
+ sbi->s_umask = uopt.umask;
- if (UDF_SB_LVIDBH(sb)) {
- int write_rev = le16_to_cpu(UDF_SB_LVIDIU(sb)->minUDFWriteRev);
+ if (sbi->s_lvid_bh) {
+ int write_rev = le16_to_cpu(udf_sb_lvidiu(sbi)->minUDFWriteRev);
if (write_rev > UDF_MAX_WRITE_VERSION)
*flags |= MS_RDONLY;
}
int iso9660 = 0;
int nsr02 = 0;
int nsr03 = 0;
+ struct udf_sb_info *sbi;
/* Block size must be a multiple of 512 */
if (sb->s_blocksize & 511)
return 0;
+ sbi = UDF_SB(sb);
if (sb->s_blocksize < sizeof(struct volStructDesc))
sectorsize = sizeof(struct volStructDesc);
else
sectorsize = sb->s_blocksize;
- sector += (UDF_SB_SESSION(sb) << sb->s_blocksize_bits);
+ sector += (sbi->s_session << sb->s_blocksize_bits);
udf_debug("Starting at sector %u (%ld byte sectors)\n",
(sector >> sb->s_blocksize_bits), sb->s_blocksize);
/* Look for ISO descriptors */
vsd = (struct volStructDesc *)(bh->b_data +
- (sector & (sb->s_blocksize - 1)));
+ (sector & (sb->s_blocksize - 1)));
if (vsd->stdIdent[0] == 0) {
brelse(bh);
break;
- } else if (!strncmp(vsd->stdIdent, VSD_STD_ID_CD001, VSD_STD_ID_LEN)) {
+ } else if (!strncmp(vsd->stdIdent, VSD_STD_ID_CD001,
+ VSD_STD_ID_LEN)) {
iso9660 = sector;
switch (vsd->structType) {
case 0:
udf_debug("ISO9660 Boot Record found\n");
break;
case 1:
- udf_debug
- ("ISO9660 Primary Volume Descriptor found\n");
+ udf_debug("ISO9660 Primary Volume Descriptor "
+ "found\n");
break;
case 2:
- udf_debug
- ("ISO9660 Supplementary Volume Descriptor found\n");
+ udf_debug("ISO9660 Supplementary Volume "
+ "Descriptor found\n");
break;
case 3:
- udf_debug
- ("ISO9660 Volume Partition Descriptor found\n");
+ udf_debug("ISO9660 Volume Partition Descriptor "
+ "found\n");
break;
case 255:
- udf_debug
- ("ISO9660 Volume Descriptor Set Terminator found\n");
+ udf_debug("ISO9660 Volume Descriptor Set "
+ "Terminator found\n");
break;
default:
udf_debug("ISO9660 VRS (%u) found\n",
vsd->structType);
break;
}
- } else if (!strncmp(vsd->stdIdent, VSD_STD_ID_BEA01, VSD_STD_ID_LEN)) {
- } else if (!strncmp(vsd->stdIdent, VSD_STD_ID_TEA01, VSD_STD_ID_LEN)) {
+ } else if (!strncmp(vsd->stdIdent, VSD_STD_ID_BEA01,
+ VSD_STD_ID_LEN))
+ ; /* nothing */
+ else if (!strncmp(vsd->stdIdent, VSD_STD_ID_TEA01,
+ VSD_STD_ID_LEN)) {
brelse(bh);
break;
- } else if (!strncmp(vsd->stdIdent, VSD_STD_ID_NSR02, VSD_STD_ID_LEN)) {
+ } else if (!strncmp(vsd->stdIdent, VSD_STD_ID_NSR02,
+ VSD_STD_ID_LEN))
nsr02 = sector;
- } else if (!strncmp(vsd->stdIdent, VSD_STD_ID_NSR03, VSD_STD_ID_LEN)) {
+ else if (!strncmp(vsd->stdIdent, VSD_STD_ID_NSR03,
+ VSD_STD_ID_LEN))
nsr03 = sector;
- }
brelse(bh);
}
return nsr03;
else if (nsr02)
return nsr02;
- else if (sector - (UDF_SB_SESSION(sb) << sb->s_blocksize_bits) == 32768)
+ else if (sector - (sbi->s_session << sb->s_blocksize_bits) == 32768)
return -1;
else
return 0;
*/
static void udf_find_anchor(struct super_block *sb)
{
- int lastblock = UDF_SB_LASTBLOCK(sb);
+ int lastblock;
struct buffer_head *bh = NULL;
uint16_t ident;
uint32_t location;
int i;
+ struct udf_sb_info *sbi;
+
+ sbi = UDF_SB(sb);
+ lastblock = sbi->s_last_block;
if (lastblock) {
int varlastblock = udf_variable_to_fixed(lastblock);
* however, if the disc isn't closed, it could be 512 */
for (i = 0; !lastblock && i < ARRAY_SIZE(last); i++) {
- if (last[i] < 0 || !(bh = sb_bread(sb, last[i]))) {
- ident = location = 0;
- } else {
- ident = le16_to_cpu(((tag *)bh->b_data)->tagIdent);
- location = le32_to_cpu(((tag *)bh->b_data)->tagLocation);
- brelse(bh);
+ ident = location = 0;
+ if (last[i] >= 0) {
+ bh = sb_bread(sb, last[i]);
+ if (bh) {
+ tag *t = (tag *)bh->b_data;
+ ident = le16_to_cpu(t->tagIdent);
+ location = le32_to_cpu(t->tagLocation);
+ brelse(bh);
+ }
}
if (ident == TAG_IDENT_AVDP) {
- if (location == last[i] - UDF_SB_SESSION(sb)) {
- lastblock = UDF_SB_ANCHOR(sb)[0] = last[i] - UDF_SB_SESSION(sb);
- UDF_SB_ANCHOR(sb)[1] = last[i] - 256 - UDF_SB_SESSION(sb);
- } else if (location == udf_variable_to_fixed(last[i]) - UDF_SB_SESSION(sb)) {
+ if (location == last[i] - sbi->s_session) {
+ lastblock = last[i] - sbi->s_session;
+ sbi->s_anchor[0] = lastblock;
+ sbi->s_anchor[1] = lastblock - 256;
+ } else if (location ==
+ udf_variable_to_fixed(last[i]) -
+ sbi->s_session) {
UDF_SET_FLAG(sb, UDF_FLAG_VARCONV);
- lastblock = UDF_SB_ANCHOR(sb)[0] = udf_variable_to_fixed(last[i]) - UDF_SB_SESSION(sb);
- UDF_SB_ANCHOR(sb)[1] = lastblock - 256 - UDF_SB_SESSION(sb);
+ lastblock =
+ udf_variable_to_fixed(last[i]) -
+ sbi->s_session;
+ sbi->s_anchor[0] = lastblock;
+ sbi->s_anchor[1] = lastblock - 256 -
+ sbi->s_session;
} else {
- udf_debug("Anchor found at block %d, location mismatch %d.\n",
+ udf_debug("Anchor found at block %d, "
+ "location mismatch %d.\n",
last[i], location);
}
- } else if (ident == TAG_IDENT_FE || ident == TAG_IDENT_EFE) {
+ } else if (ident == TAG_IDENT_FE ||
+ ident == TAG_IDENT_EFE) {
lastblock = last[i];
- UDF_SB_ANCHOR(sb)[3] = 512;
+ sbi->s_anchor[3] = 512;
} else {
- if (last[i] < 256 || !(bh = sb_bread(sb, last[i] - 256))) {
- ident = location = 0;
- } else {
- ident = le16_to_cpu(((tag *)bh->b_data)->tagIdent);
- location = le32_to_cpu(((tag *)bh->b_data)->tagLocation);
- brelse(bh);
+ ident = location = 0;
+ if (last[i] >= 256) {
+ bh = sb_bread(sb, last[i] - 256);
+ if (bh) {
+ tag *t = (tag *)bh->b_data;
+ ident = le16_to_cpu(
+ t->tagIdent);
+ location = le32_to_cpu(
+ t->tagLocation);
+ brelse(bh);
+ }
}
if (ident == TAG_IDENT_AVDP &&
- location == last[i] - 256 - UDF_SB_SESSION(sb)) {
+ location == last[i] - 256 -
+ sbi->s_session) {
lastblock = last[i];
- UDF_SB_ANCHOR(sb)[1] = last[i] - 256;
+ sbi->s_anchor[1] = last[i] - 256;
} else {
- if (last[i] < 312 + UDF_SB_SESSION(sb) ||
- !(bh = sb_bread(sb, last[i] - 312 - UDF_SB_SESSION(sb)))) {
- ident = location = 0;
- } else {
- ident = le16_to_cpu(((tag *)bh->b_data)->tagIdent);
- location = le32_to_cpu(((tag *)bh->b_data)->tagLocation);
- brelse(bh);
+ ident = location = 0;
+ if (last[i] >= 312 + sbi->s_session) {
+ bh = sb_bread(sb,
+ last[i] - 312 -
+ sbi->s_session);
+ if (bh) {
+ tag *t = (tag *)
+ bh->b_data;
+ ident = le16_to_cpu(
+ t->tagIdent);
+ location = le32_to_cpu(
+ t->tagLocation);
+ brelse(bh);
+ }
}
if (ident == TAG_IDENT_AVDP &&
location == udf_variable_to_fixed(last[i]) - 256) {
- UDF_SET_FLAG(sb, UDF_FLAG_VARCONV);
+ UDF_SET_FLAG(sb,
+ UDF_FLAG_VARCONV);
lastblock = udf_variable_to_fixed(last[i]);
- UDF_SB_ANCHOR(sb)[1] = lastblock - 256;
+ sbi->s_anchor[1] = lastblock - 256;
}
}
}
}
if (!lastblock) {
- /* We havn't found the lastblock. check 312 */
- if ((bh = sb_bread(sb, 312 + UDF_SB_SESSION(sb)))) {
- ident = le16_to_cpu(((tag *)bh->b_data)->tagIdent);
- location = le32_to_cpu(((tag *)bh->b_data)->tagLocation);
+ /* We haven't found the lastblock. check 312 */
+ bh = sb_bread(sb, 312 + sbi->s_session);
+ if (bh) {
+ tag *t = (tag *)bh->b_data;
+ ident = le16_to_cpu(t->tagIdent);
+ location = le32_to_cpu(t->tagLocation);
brelse(bh);
if (ident == TAG_IDENT_AVDP && location == 256)
}
}
- for (i = 0; i < ARRAY_SIZE(UDF_SB_ANCHOR(sb)); i++) {
- if (UDF_SB_ANCHOR(sb)[i]) {
- if (!(bh = udf_read_tagged(sb, UDF_SB_ANCHOR(sb)[i],
- UDF_SB_ANCHOR(sb)[i], &ident))) {
- UDF_SB_ANCHOR(sb)[i] = 0;
- } else {
+ for (i = 0; i < ARRAY_SIZE(sbi->s_anchor); i++) {
+ if (sbi->s_anchor[i]) {
+ bh = udf_read_tagged(sb, sbi->s_anchor[i],
+ sbi->s_anchor[i], &ident);
+ if (!bh)
+ sbi->s_anchor[i] = 0;
+ else {
brelse(bh);
if ((ident != TAG_IDENT_AVDP) &&
- (i || (ident != TAG_IDENT_FE && ident != TAG_IDENT_EFE))) {
- UDF_SB_ANCHOR(sb)[i] = 0;
- }
+ (i || (ident != TAG_IDENT_FE &&
+ ident != TAG_IDENT_EFE)))
+ sbi->s_anchor[i] = 0;
}
}
}
- UDF_SB_LASTBLOCK(sb) = lastblock;
+ sbi->s_last_block = lastblock;
}
-static int udf_find_fileset(struct super_block *sb, kernel_lb_addr *fileset, kernel_lb_addr *root)
+static int udf_find_fileset(struct super_block *sb,
+ kernel_lb_addr *fileset,
+ kernel_lb_addr *root)
{
struct buffer_head *bh = NULL;
long lastblock;
uint16_t ident;
+ struct udf_sb_info *sbi;
if (fileset->logicalBlockNum != 0xFFFFFFFF ||
fileset->partitionReferenceNum != 0xFFFF) {
}
- if (!bh) { /* Search backwards through the partitions */
+ sbi = UDF_SB(sb);
+ if (!bh) {
+ /* Search backwards through the partitions */
kernel_lb_addr newfileset;
/* --> cvg: FIXME - is it reasonable? */
return 1;
- for (newfileset.partitionReferenceNum = UDF_SB_NUMPARTS(sb) - 1;
+ for (newfileset.partitionReferenceNum = sbi->s_partitions - 1;
(newfileset.partitionReferenceNum != 0xFFFF &&
fileset->logicalBlockNum == 0xFFFFFFFF &&
fileset->partitionReferenceNum == 0xFFFF);
newfileset.partitionReferenceNum--) {
- lastblock = UDF_SB_PARTLEN(sb, newfileset.partitionReferenceNum);
+ lastblock = sbi->s_partmaps
+ [newfileset.partitionReferenceNum]
+ .s_partition_len;
newfileset.logicalBlockNum = 0;
do {
- bh = udf_read_ptagged(sb, newfileset, 0, &ident);
+ bh = udf_read_ptagged(sb, newfileset, 0,
+ &ident);
if (!bh) {
newfileset.logicalBlockNum++;
continue;
case TAG_IDENT_SBD:
{
struct spaceBitmapDesc *sp;
- sp = (struct spaceBitmapDesc *)bh->b_data;
+ sp = (struct spaceBitmapDesc *)
+ bh->b_data;
newfileset.logicalBlockNum += 1 +
((le32_to_cpu(sp->numOfBytes) +
- sizeof(struct spaceBitmapDesc) - 1)
- >> sb->s_blocksize_bits);
+ sizeof(struct spaceBitmapDesc)
+ - 1) >> sb->s_blocksize_bits);
brelse(bh);
break;
}
fileset->logicalBlockNum,
fileset->partitionReferenceNum);
- UDF_SB_PARTITION(sb) = fileset->partitionReferenceNum;
+ sbi->s_partition = fileset->partitionReferenceNum;
udf_load_fileset(sb, bh, root);
brelse(bh);
return 0;
lets_to_cpu(pvoldesc->recordingDateAndTime))) {
kernel_timestamp ts;
ts = lets_to_cpu(pvoldesc->recordingDateAndTime);
- udf_debug("recording time %ld/%ld, %04u/%02u/%02u %02u:%02u (%x)\n",
+ udf_debug("recording time %ld/%ld, %04u/%02u/%02u"
+ " %02u:%02u (%x)\n",
recording, recording_usec,
ts.year, ts.month, ts.day, ts.hour,
ts.minute, ts.typeAndTimezone);
- UDF_SB_RECORDTIME(sb).tv_sec = recording;
- UDF_SB_RECORDTIME(sb).tv_nsec = recording_usec * 1000;
+ UDF_SB(sb)->s_record_time.tv_sec = recording;
+ UDF_SB(sb)->s_record_time.tv_nsec = recording_usec * 1000;
}
- if (!udf_build_ustr(&instr, pvoldesc->volIdent, 32)) {
+ if (!udf_build_ustr(&instr, pvoldesc->volIdent, 32))
if (udf_CS0toUTF8(&outstr, &instr)) {
- strncpy(UDF_SB_VOLIDENT(sb), outstr.u_name,
+ strncpy(UDF_SB(sb)->s_volume_ident, outstr.u_name,
outstr.u_len > 31 ? 31 : outstr.u_len);
- udf_debug("volIdent[] = '%s'\n", UDF_SB_VOLIDENT(sb));
+ udf_debug("volIdent[] = '%s'\n",
+ UDF_SB(sb)->s_volume_ident);
}
- }
- if (!udf_build_ustr(&instr, pvoldesc->volSetIdent, 128)) {
+ if (!udf_build_ustr(&instr, pvoldesc->volSetIdent, 128))
if (udf_CS0toUTF8(&outstr, &instr))
udf_debug("volSetIdent[] = '%s'\n", outstr.u_name);
- }
}
static void udf_load_fileset(struct super_block *sb, struct buffer_head *bh,
*root = lelb_to_cpu(fset->rootDirectoryICB.extLocation);
- UDF_SB_SERIALNUM(sb) = le16_to_cpu(fset->descTag.tagSerialNum);
+ UDF_SB(sb)->s_serial_number = le16_to_cpu(fset->descTag.tagSerialNum);
udf_debug("Rootdir at block=%d, partition=%d\n",
root->logicalBlockNum, root->partitionReferenceNum);
}
+int udf_compute_nr_groups(struct super_block *sb, u32 partition)
+{
+ struct udf_part_map *map = &UDF_SB(sb)->s_partmaps[partition];
+ return (map->s_partition_len +
+ (sizeof(struct spaceBitmapDesc) << 3) +
+ (sb->s_blocksize * 8) - 1) /
+ (sb->s_blocksize * 8);
+}
+
+static struct udf_bitmap *udf_sb_alloc_bitmap(struct super_block *sb, u32 index)
+{
+ struct udf_bitmap *bitmap;
+ int nr_groups;
+ int size;
+
+ nr_groups = udf_compute_nr_groups(sb, index);
+ size = sizeof(struct udf_bitmap) +
+ (sizeof(struct buffer_head *) * nr_groups);
+
+ if (size <= PAGE_SIZE)
+ bitmap = kmalloc(size, GFP_KERNEL);
+ else
+ bitmap = vmalloc(size); /* TODO: get rid of vmalloc */
+
+ if (bitmap == NULL) {
+ udf_error(sb, __FUNCTION__,
+ "Unable to allocate space for bitmap "
+ "and %d buffer_head pointers", nr_groups);
+ return NULL;
+ }
+
+ memset(bitmap, 0x00, size);
+ bitmap->s_block_bitmap = (struct buffer_head **)(bitmap + 1);
+ bitmap->s_nr_groups = nr_groups;
+ return bitmap;
+}
+
static int udf_load_partdesc(struct super_block *sb, struct buffer_head *bh)
{
struct partitionDesc *p;
int i;
+ struct udf_part_map *map;
+ struct udf_sb_info *sbi;
p = (struct partitionDesc *)bh->b_data;
+ sbi = UDF_SB(sb);
- for (i = 0; i < UDF_SB_NUMPARTS(sb); i++) {
+ for (i = 0; i < sbi->s_partitions; i++) {
+ map = &sbi->s_partmaps[i];
udf_debug("Searching map: (%d == %d)\n",
- UDF_SB_PARTMAPS(sb)[i].s_partition_num, le16_to_cpu(p->partitionNumber));
- if (UDF_SB_PARTMAPS(sb)[i].s_partition_num == le16_to_cpu(p->partitionNumber)) {
- UDF_SB_PARTLEN(sb,i) = le32_to_cpu(p->partitionLength); /* blocks */
- UDF_SB_PARTROOT(sb,i) = le32_to_cpu(p->partitionStartingLocation);
- if (le32_to_cpu(p->accessType) == PD_ACCESS_TYPE_READ_ONLY)
- UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_READ_ONLY;
- if (le32_to_cpu(p->accessType) == PD_ACCESS_TYPE_WRITE_ONCE)
- UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_WRITE_ONCE;
- if (le32_to_cpu(p->accessType) == PD_ACCESS_TYPE_REWRITABLE)
- UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_REWRITABLE;
- if (le32_to_cpu(p->accessType) == PD_ACCESS_TYPE_OVERWRITABLE)
- UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_OVERWRITABLE;
-
- if (!strcmp(p->partitionContents.ident, PD_PARTITION_CONTENTS_NSR02) ||
- !strcmp(p->partitionContents.ident, PD_PARTITION_CONTENTS_NSR03)) {
+ map->s_partition_num,
+ le16_to_cpu(p->partitionNumber));
+ if (map->s_partition_num ==
+ le16_to_cpu(p->partitionNumber)) {
+ map->s_partition_len =
+ le32_to_cpu(p->partitionLength); /* blocks */
+ map->s_partition_root =
+ le32_to_cpu(p->partitionStartingLocation);
+ if (p->accessType ==
+ cpu_to_le32(PD_ACCESS_TYPE_READ_ONLY))
+ map->s_partition_flags |=
+ UDF_PART_FLAG_READ_ONLY;
+ if (p->accessType ==
+ cpu_to_le32(PD_ACCESS_TYPE_WRITE_ONCE))
+ map->s_partition_flags |=
+ UDF_PART_FLAG_WRITE_ONCE;
+ if (p->accessType ==
+ cpu_to_le32(PD_ACCESS_TYPE_REWRITABLE))
+ map->s_partition_flags |=
+ UDF_PART_FLAG_REWRITABLE;
+ if (p->accessType ==
+ cpu_to_le32(PD_ACCESS_TYPE_OVERWRITABLE))
+ map->s_partition_flags |=
+ UDF_PART_FLAG_OVERWRITABLE;
+
+ if (!strcmp(p->partitionContents.ident,
+ PD_PARTITION_CONTENTS_NSR02) ||
+ !strcmp(p->partitionContents.ident,
+ PD_PARTITION_CONTENTS_NSR03)) {
struct partitionHeaderDesc *phd;
- phd = (struct partitionHeaderDesc *)(p->partitionContentsUse);
+ phd = (struct partitionHeaderDesc *)
+ (p->partitionContentsUse);
if (phd->unallocSpaceTable.extLength) {
kernel_lb_addr loc = {
.logicalBlockNum = le32_to_cpu(phd->unallocSpaceTable.extPosition),
.partitionReferenceNum = i,
};
- UDF_SB_PARTMAPS(sb)[i].s_uspace.s_table =
+ map->s_uspace.s_table =
udf_iget(sb, loc);
- if (!UDF_SB_PARTMAPS(sb)[i].s_uspace.s_table) {
+ if (!map->s_uspace.s_table) {
udf_debug("cannot load unallocSpaceTable (part %d)\n", i);
return 1;
}
- UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_UNALLOC_TABLE;
+ map->s_partition_flags |=
+ UDF_PART_FLAG_UNALLOC_TABLE;
udf_debug("unallocSpaceTable (part %d) @ %ld\n",
- i, UDF_SB_PARTMAPS(sb)[i].s_uspace.s_table->i_ino);
+ i, map->s_uspace.s_table->i_ino);
}
if (phd->unallocSpaceBitmap.extLength) {
- UDF_SB_ALLOC_BITMAP(sb, i, s_uspace);
- if (UDF_SB_PARTMAPS(sb)[i].s_uspace.s_bitmap != NULL) {
- UDF_SB_PARTMAPS(sb)[i].s_uspace.s_bitmap->s_extLength =
+ struct udf_bitmap *bitmap =
+ udf_sb_alloc_bitmap(sb, i);
+ map->s_uspace.s_bitmap = bitmap;
+ if (bitmap != NULL) {
+ bitmap->s_extLength =
le32_to_cpu(phd->unallocSpaceBitmap.extLength);
- UDF_SB_PARTMAPS(sb)[i].s_uspace.s_bitmap->s_extPosition =
+ bitmap->s_extPosition =
le32_to_cpu(phd->unallocSpaceBitmap.extPosition);
- UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_UNALLOC_BITMAP;
+ map->s_partition_flags |= UDF_PART_FLAG_UNALLOC_BITMAP;
udf_debug("unallocSpaceBitmap (part %d) @ %d\n",
- i, UDF_SB_PARTMAPS(sb)[i].s_uspace.s_bitmap->s_extPosition);
+ i, bitmap->s_extPosition);
}
}
if (phd->partitionIntegrityTable.extLength)
.partitionReferenceNum = i,
};
- UDF_SB_PARTMAPS(sb)[i].s_fspace.s_table =
+ map->s_fspace.s_table =
udf_iget(sb, loc);
- if (!UDF_SB_PARTMAPS(sb)[i].s_fspace.s_table) {
+ if (!map->s_fspace.s_table) {
udf_debug("cannot load freedSpaceTable (part %d)\n", i);
return 1;
}
- UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_FREED_TABLE;
+ map->s_partition_flags |=
+ UDF_PART_FLAG_FREED_TABLE;
udf_debug("freedSpaceTable (part %d) @ %ld\n",
- i, UDF_SB_PARTMAPS(sb)[i].s_fspace.s_table->i_ino);
+ i, map->s_fspace.s_table->i_ino);
}
if (phd->freedSpaceBitmap.extLength) {
- UDF_SB_ALLOC_BITMAP(sb, i, s_fspace);
- if (UDF_SB_PARTMAPS(sb)[i].s_fspace.s_bitmap != NULL) {
- UDF_SB_PARTMAPS(sb)[i].s_fspace.s_bitmap->s_extLength =
+ struct udf_bitmap *bitmap =
+ udf_sb_alloc_bitmap(sb, i);
+ map->s_fspace.s_bitmap = bitmap;
+ if (bitmap != NULL) {
+ bitmap->s_extLength =
le32_to_cpu(phd->freedSpaceBitmap.extLength);
- UDF_SB_PARTMAPS(sb)[i].s_fspace.s_bitmap->s_extPosition =
+ bitmap->s_extPosition =
le32_to_cpu(phd->freedSpaceBitmap.extPosition);
- UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_FREED_BITMAP;
+ map->s_partition_flags |= UDF_PART_FLAG_FREED_BITMAP;
udf_debug("freedSpaceBitmap (part %d) @ %d\n",
- i, UDF_SB_PARTMAPS(sb)[i].s_fspace.s_bitmap->s_extPosition);
+ i, bitmap->s_extPosition);
}
}
}
break;
}
}
- if (i == UDF_SB_NUMPARTS(sb)) {
+ if (i == sbi->s_partitions)
udf_debug("Partition (%d) not found in partition map\n",
le16_to_cpu(p->partitionNumber));
- } else {
- udf_debug("Partition (%d:%d type %x) starts at physical %d, block length %d\n",
- le16_to_cpu(p->partitionNumber), i, UDF_SB_PARTTYPE(sb,i),
- UDF_SB_PARTROOT(sb,i), UDF_SB_PARTLEN(sb,i));
- }
+ else
+ udf_debug("Partition (%d:%d type %x) starts at physical %d, "
+ "block length %d\n",
+ le16_to_cpu(p->partitionNumber), i,
+ map->s_partition_type,
+ map->s_partition_root,
+ map->s_partition_len);
return 0;
}
struct logicalVolDesc *lvd;
int i, j, offset;
uint8_t type;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct genericPartitionMap *gpm;
lvd = (struct logicalVolDesc *)bh->b_data;
- UDF_SB_ALLOC_PARTMAPS(sb, le32_to_cpu(lvd->numPartitionMaps));
+ i = udf_sb_alloc_partition_maps(sb, le32_to_cpu(lvd->numPartitionMaps));
+ if (i != 0)
+ return i;
for (i = 0, offset = 0;
- i < UDF_SB_NUMPARTS(sb) && offset < le32_to_cpu(lvd->mapTableLength);
- i++, offset += ((struct genericPartitionMap *)&(lvd->partitionMaps[offset]))->partitionMapLength) {
- type = ((struct genericPartitionMap *)&(lvd->partitionMaps[offset]))->partitionMapType;
+ i < sbi->s_partitions && offset < le32_to_cpu(lvd->mapTableLength);
+ i++, offset += gpm->partitionMapLength) {
+ struct udf_part_map *map = &sbi->s_partmaps[i];
+ gpm = (struct genericPartitionMap *)
+ &(lvd->partitionMaps[offset]);
+ type = gpm->partitionMapType;
if (type == 1) {
- struct genericPartitionMap1 *gpm1 = (struct genericPartitionMap1 *)&(lvd->partitionMaps[offset]);
- UDF_SB_PARTTYPE(sb,i) = UDF_TYPE1_MAP15;
- UDF_SB_PARTVSN(sb,i) = le16_to_cpu(gpm1->volSeqNum);
- UDF_SB_PARTNUM(sb,i) = le16_to_cpu(gpm1->partitionNum);
- UDF_SB_PARTFUNC(sb,i) = NULL;
+ struct genericPartitionMap1 *gpm1 =
+ (struct genericPartitionMap1 *)gpm;
+ map->s_partition_type = UDF_TYPE1_MAP15;
+ map->s_volumeseqnum = le16_to_cpu(gpm1->volSeqNum);
+ map->s_partition_num = le16_to_cpu(gpm1->partitionNum);
+ map->s_partition_func = NULL;
} else if (type == 2) {
- struct udfPartitionMap2 *upm2 = (struct udfPartitionMap2 *)&(lvd->partitionMaps[offset]);
- if (!strncmp(upm2->partIdent.ident, UDF_ID_VIRTUAL, strlen(UDF_ID_VIRTUAL))) {
- if (le16_to_cpu(((__le16 *)upm2->partIdent.identSuffix)[0]) == 0x0150) {
- UDF_SB_PARTTYPE(sb,i) = UDF_VIRTUAL_MAP15;
- UDF_SB_PARTFUNC(sb,i) = udf_get_pblock_virt15;
- } else if (le16_to_cpu(((__le16 *)upm2->partIdent.identSuffix)[0]) == 0x0200) {
- UDF_SB_PARTTYPE(sb,i) = UDF_VIRTUAL_MAP20;
- UDF_SB_PARTFUNC(sb,i) = udf_get_pblock_virt20;
+ struct udfPartitionMap2 *upm2 =
+ (struct udfPartitionMap2 *)gpm;
+ if (!strncmp(upm2->partIdent.ident, UDF_ID_VIRTUAL,
+ strlen(UDF_ID_VIRTUAL))) {
+ u16 suf =
+ le16_to_cpu(((__le16 *)upm2->partIdent.
+ identSuffix)[0]);
+ if (suf == 0x0150) {
+ map->s_partition_type =
+ UDF_VIRTUAL_MAP15;
+ map->s_partition_func =
+ udf_get_pblock_virt15;
+ } else if (suf == 0x0200) {
+ map->s_partition_type =
+ UDF_VIRTUAL_MAP20;
+ map->s_partition_func =
+ udf_get_pblock_virt20;
}
- } else if (!strncmp(upm2->partIdent.ident, UDF_ID_SPARABLE, strlen(UDF_ID_SPARABLE))) {
+ } else if (!strncmp(upm2->partIdent.ident,
+ UDF_ID_SPARABLE,
+ strlen(UDF_ID_SPARABLE))) {
uint32_t loc;
uint16_t ident;
struct sparingTable *st;
- struct sparablePartitionMap *spm = (struct sparablePartitionMap *)&(lvd->partitionMaps[offset]);
+ struct sparablePartitionMap *spm =
+ (struct sparablePartitionMap *)gpm;
- UDF_SB_PARTTYPE(sb,i) = UDF_SPARABLE_MAP15;
- UDF_SB_TYPESPAR(sb,i).s_packet_len = le16_to_cpu(spm->packetLength);
+ map->s_partition_type = UDF_SPARABLE_MAP15;
+ map->s_type_specific.s_sparing.s_packet_len =
+ le16_to_cpu(spm->packetLength);
for (j = 0; j < spm->numSparingTables; j++) {
- loc = le32_to_cpu(spm->locSparingTable[j]);
- UDF_SB_TYPESPAR(sb,i).s_spar_map[j] =
- udf_read_tagged(sb, loc, loc, &ident);
- if (UDF_SB_TYPESPAR(sb,i).s_spar_map[j] != NULL) {
- st = (struct sparingTable *)UDF_SB_TYPESPAR(sb,i).s_spar_map[j]->b_data;
- if (ident != 0 ||
- strncmp(st->sparingIdent.ident, UDF_ID_SPARING, strlen(UDF_ID_SPARING))) {
- brelse(UDF_SB_TYPESPAR(sb,i).s_spar_map[j]);
- UDF_SB_TYPESPAR(sb,i).s_spar_map[j] = NULL;
+ struct buffer_head *bh2;
+
+ loc = le32_to_cpu(
+ spm->locSparingTable[j]);
+ bh2 = udf_read_tagged(sb, loc, loc,
+ &ident);
+ map->s_type_specific.s_sparing.
+ s_spar_map[j] = bh2;
+
+ if (bh2 != NULL) {
+ st = (struct sparingTable *)
+ bh2->b_data;
+ if (ident != 0 || strncmp(
+ st->sparingIdent.ident,
+ UDF_ID_SPARING,
+ strlen(UDF_ID_SPARING))) {
+ brelse(bh2);
+ map->s_type_specific.
+ s_sparing.
+ s_spar_map[j] =
+ NULL;
}
}
}
- UDF_SB_PARTFUNC(sb,i) = udf_get_pblock_spar15;
+ map->s_partition_func = udf_get_pblock_spar15;
} else {
- udf_debug("Unknown ident: %s\n", upm2->partIdent.ident);
+ udf_debug("Unknown ident: %s\n",
+ upm2->partIdent.ident);
continue;
}
- UDF_SB_PARTVSN(sb,i) = le16_to_cpu(upm2->volSeqNum);
- UDF_SB_PARTNUM(sb,i) = le16_to_cpu(upm2->partitionNum);
+ map->s_volumeseqnum = le16_to_cpu(upm2->volSeqNum);
+ map->s_partition_num = le16_to_cpu(upm2->partitionNum);
}
udf_debug("Partition (%d:%d) type %d on volume %d\n",
- i, UDF_SB_PARTNUM(sb,i), type, UDF_SB_PARTVSN(sb,i));
+ i, map->s_partition_num, type,
+ map->s_volumeseqnum);
}
if (fileset) {
long_ad *la = (long_ad *)&(lvd->logicalVolContentsUse[0]);
*fileset = lelb_to_cpu(la->extLocation);
- udf_debug("FileSet found in LogicalVolDesc at block=%d, partition=%d\n",
- fileset->logicalBlockNum,
+ udf_debug("FileSet found in LogicalVolDesc at block=%d, "
+ "partition=%d\n", fileset->logicalBlockNum,
fileset->partitionReferenceNum);
}
if (lvd->integritySeqExt.extLength)
{
struct buffer_head *bh = NULL;
uint16_t ident;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct logicalVolIntegrityDesc *lvid;
while (loc.extLength > 0 &&
(bh = udf_read_tagged(sb, loc.extLocation,
loc.extLocation, &ident)) &&
ident == TAG_IDENT_LVID) {
- UDF_SB_LVIDBH(sb) = bh;
+ sbi->s_lvid_bh = bh;
+ lvid = (struct logicalVolIntegrityDesc *)bh->b_data;
- if (UDF_SB_LVID(sb)->nextIntegrityExt.extLength)
- udf_load_logicalvolint(sb, leea_to_cpu(UDF_SB_LVID(sb)->nextIntegrityExt));
+ if (lvid->nextIntegrityExt.extLength)
+ udf_load_logicalvolint(sb,
+ leea_to_cpu(lvid->nextIntegrityExt));
- if (UDF_SB_LVIDBH(sb) != bh)
+ if (sbi->s_lvid_bh != bh)
brelse(bh);
loc.extLength -= sb->s_blocksize;
loc.extLocation++;
}
- if (UDF_SB_LVIDBH(sb) != bh)
+ if (sbi->s_lvid_bh != bh)
brelse(bh);
}
* July 1, 1997 - Andrew E. Mileski
* Written, tested, and released.
*/
-static int udf_process_sequence(struct super_block *sb, long block, long lastblock,
- kernel_lb_addr *fileset)
+static int udf_process_sequence(struct super_block *sb, long block,
+ long lastblock, kernel_lb_addr *fileset)
{
struct buffer_head *bh = NULL;
struct udf_vds_record vds[VDS_POS_LENGTH];
+ struct udf_vds_record *curr;
struct generic_desc *gd;
struct volDescPtr *vdp;
int done = 0;
vdsn = le32_to_cpu(gd->volDescSeqNum);
switch (ident) {
case TAG_IDENT_PVD: /* ISO 13346 3/10.1 */
- if (vdsn >= vds[VDS_POS_PRIMARY_VOL_DESC].volDescSeqNum) {
- vds[VDS_POS_PRIMARY_VOL_DESC].volDescSeqNum = vdsn;
- vds[VDS_POS_PRIMARY_VOL_DESC].block = block;
+ curr = &vds[VDS_POS_PRIMARY_VOL_DESC];
+ if (vdsn >= curr->volDescSeqNum) {
+ curr->volDescSeqNum = vdsn;
+ curr->block = block;
}
break;
case TAG_IDENT_VDP: /* ISO 13346 3/10.3 */
- if (vdsn >= vds[VDS_POS_VOL_DESC_PTR].volDescSeqNum) {
- vds[VDS_POS_VOL_DESC_PTR].volDescSeqNum = vdsn;
- vds[VDS_POS_VOL_DESC_PTR].block = block;
+ curr = &vds[VDS_POS_VOL_DESC_PTR];
+ if (vdsn >= curr->volDescSeqNum) {
+ curr->volDescSeqNum = vdsn;
+ curr->block = block;
vdp = (struct volDescPtr *)bh->b_data;
- next_s = le32_to_cpu(vdp->nextVolDescSeqExt.extLocation);
- next_e = le32_to_cpu(vdp->nextVolDescSeqExt.extLength);
+ next_s = le32_to_cpu(
+ vdp->nextVolDescSeqExt.extLocation);
+ next_e = le32_to_cpu(
+ vdp->nextVolDescSeqExt.extLength);
next_e = next_e >> sb->s_blocksize_bits;
next_e += next_s;
}
break;
case TAG_IDENT_IUVD: /* ISO 13346 3/10.4 */
- if (vdsn >= vds[VDS_POS_IMP_USE_VOL_DESC].volDescSeqNum) {
- vds[VDS_POS_IMP_USE_VOL_DESC].volDescSeqNum = vdsn;
- vds[VDS_POS_IMP_USE_VOL_DESC].block = block;
+ curr = &vds[VDS_POS_IMP_USE_VOL_DESC];
+ if (vdsn >= curr->volDescSeqNum) {
+ curr->volDescSeqNum = vdsn;
+ curr->block = block;
}
break;
case TAG_IDENT_PD: /* ISO 13346 3/10.5 */
- if (!vds[VDS_POS_PARTITION_DESC].block)
- vds[VDS_POS_PARTITION_DESC].block = block;
+ curr = &vds[VDS_POS_PARTITION_DESC];
+ if (!curr->block)
+ curr->block = block;
break;
case TAG_IDENT_LVD: /* ISO 13346 3/10.6 */
- if (vdsn >= vds[VDS_POS_LOGICAL_VOL_DESC].volDescSeqNum) {
- vds[VDS_POS_LOGICAL_VOL_DESC].volDescSeqNum = vdsn;
- vds[VDS_POS_LOGICAL_VOL_DESC].block = block;
+ curr = &vds[VDS_POS_LOGICAL_VOL_DESC];
+ if (vdsn >= curr->volDescSeqNum) {
+ curr->volDescSeqNum = vdsn;
+ curr->block = block;
}
break;
case TAG_IDENT_USD: /* ISO 13346 3/10.8 */
- if (vdsn >= vds[VDS_POS_UNALLOC_SPACE_DESC].volDescSeqNum) {
- vds[VDS_POS_UNALLOC_SPACE_DESC].volDescSeqNum = vdsn;
- vds[VDS_POS_UNALLOC_SPACE_DESC].block = block;
+ curr = &vds[VDS_POS_UNALLOC_SPACE_DESC];
+ if (vdsn >= curr->volDescSeqNum) {
+ curr->volDescSeqNum = vdsn;
+ curr->block = block;
}
break;
case TAG_IDENT_TD: /* ISO 13346 3/10.9 */
block = next_s;
lastblock = next_e;
next_s = next_e = 0;
- } else {
+ } else
done = 1;
- }
break;
}
brelse(bh);
}
for (i = 0; i < VDS_POS_LENGTH; i++) {
if (vds[i].block) {
- bh = udf_read_tagged(sb, vds[i].block, vds[i].block, &ident);
+ bh = udf_read_tagged(sb, vds[i].block, vds[i].block,
+ &ident);
if (i == VDS_POS_PRIMARY_VOL_DESC) {
udf_load_pvoldesc(sb, bh);
} else if (i == VDS_POS_LOGICAL_VOL_DESC) {
- udf_load_logicalvol(sb, bh, fileset);
+ if (udf_load_logicalvol(sb, bh, fileset)) {
+ brelse(bh);
+ return 1;
+ }
} else if (i == VDS_POS_PARTITION_DESC) {
struct buffer_head *bh2 = NULL;
if (udf_load_partdesc(sb, bh)) {
brelse(bh);
return 1;
}
- for (j = vds[i].block + 1; j < vds[VDS_POS_TERMINATING_DESC].block; j++) {
+ for (j = vds[i].block + 1;
+ j < vds[VDS_POS_TERMINATING_DESC].block;
+ j++) {
bh2 = udf_read_tagged(sb, j, j, &ident);
gd = (struct generic_desc *)bh2->b_data;
if (ident == TAG_IDENT_PD)
- if (udf_load_partdesc(sb, bh2)) {
+ if (udf_load_partdesc(sb,
+ bh2)) {
brelse(bh);
brelse(bh2);
return 1;
}
/* Check that it is NSR02 compliant */
/* Process any "CD-ROM Volume Descriptor Set" (ECMA 167 2/8.3.1) */
- else if ((block = udf_vrs(sb, silent)) == -1) {
- udf_debug("Failed to read byte 32768. Assuming open disc. "
- "Skipping validity check\n");
- if (!UDF_SB_LASTBLOCK(sb))
- UDF_SB_LASTBLOCK(sb) = udf_get_last_block(sb);
- return 0;
- } else {
- return !block;
+ else {
+ block = udf_vrs(sb, silent);
+ if (block == -1) {
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ udf_debug("Failed to read byte 32768. Assuming open "
+ "disc. Skipping validity check\n");
+ if (!sbi->s_last_block)
+ sbi->s_last_block = udf_get_last_block(sb);
+ return 0;
+ } else
+ return !block;
}
}
struct buffer_head *bh;
long main_s, main_e, reserve_s, reserve_e;
int i, j;
+ struct udf_sb_info *sbi;
if (!sb)
return 1;
+ sbi = UDF_SB(sb);
- for (i = 0; i < ARRAY_SIZE(UDF_SB_ANCHOR(sb)); i++) {
- if (UDF_SB_ANCHOR(sb)[i] &&
- (bh = udf_read_tagged(sb, UDF_SB_ANCHOR(sb)[i],
- UDF_SB_ANCHOR(sb)[i], &ident))) {
- anchor = (struct anchorVolDescPtr *)bh->b_data;
+ for (i = 0; i < ARRAY_SIZE(sbi->s_anchor); i++) {
+ if (!sbi->s_anchor[i])
+ continue;
+ bh = udf_read_tagged(sb, sbi->s_anchor[i], sbi->s_anchor[i],
+ &ident);
+ if (!bh)
+ continue;
- /* Locate the main sequence */
- main_s = le32_to_cpu(anchor->mainVolDescSeqExt.extLocation);
- main_e = le32_to_cpu(anchor->mainVolDescSeqExt.extLength );
- main_e = main_e >> sb->s_blocksize_bits;
- main_e += main_s;
+ anchor = (struct anchorVolDescPtr *)bh->b_data;
- /* Locate the reserve sequence */
- reserve_s = le32_to_cpu(anchor->reserveVolDescSeqExt.extLocation);
- reserve_e = le32_to_cpu(anchor->reserveVolDescSeqExt.extLength);
- reserve_e = reserve_e >> sb->s_blocksize_bits;
- reserve_e += reserve_s;
+ /* Locate the main sequence */
+ main_s = le32_to_cpu(anchor->mainVolDescSeqExt.extLocation);
+ main_e = le32_to_cpu(anchor->mainVolDescSeqExt.extLength);
+ main_e = main_e >> sb->s_blocksize_bits;
+ main_e += main_s;
- brelse(bh);
+ /* Locate the reserve sequence */
+ reserve_s = le32_to_cpu(
+ anchor->reserveVolDescSeqExt.extLocation);
+ reserve_e = le32_to_cpu(
+ anchor->reserveVolDescSeqExt.extLength);
+ reserve_e = reserve_e >> sb->s_blocksize_bits;
+ reserve_e += reserve_s;
- /* Process the main & reserve sequences */
- /* responsible for finding the PartitionDesc(s) */
- if (!(udf_process_sequence(sb, main_s, main_e, fileset) &&
- udf_process_sequence(sb, reserve_s, reserve_e, fileset))) {
- break;
- }
- }
+ brelse(bh);
+
+ /* Process the main & reserve sequences */
+ /* responsible for finding the PartitionDesc(s) */
+ if (!(udf_process_sequence(sb, main_s, main_e,
+ fileset) &&
+ udf_process_sequence(sb, reserve_s, reserve_e,
+ fileset)))
+ break;
}
- if (i == ARRAY_SIZE(UDF_SB_ANCHOR(sb))) {
+ if (i == ARRAY_SIZE(sbi->s_anchor)) {
udf_debug("No Anchor block found\n");
return 1;
- } else
- udf_debug("Using anchor in block %d\n", UDF_SB_ANCHOR(sb)[i]);
+ }
+ udf_debug("Using anchor in block %d\n", sbi->s_anchor[i]);
- for (i = 0; i < UDF_SB_NUMPARTS(sb); i++) {
+ for (i = 0; i < sbi->s_partitions; i++) {
kernel_lb_addr uninitialized_var(ino);
- switch (UDF_SB_PARTTYPE(sb, i)) {
+ struct udf_part_map *map = &sbi->s_partmaps[i];
+ switch (map->s_partition_type) {
case UDF_VIRTUAL_MAP15:
case UDF_VIRTUAL_MAP20:
- if (!UDF_SB_LASTBLOCK(sb)) {
- UDF_SB_LASTBLOCK(sb) = udf_get_last_block(sb);
+ if (!sbi->s_last_block) {
+ sbi->s_last_block = udf_get_last_block(sb);
udf_find_anchor(sb);
}
- if (!UDF_SB_LASTBLOCK(sb)) {
+ if (!sbi->s_last_block) {
udf_debug("Unable to determine Lastblock (For "
"Virtual Partition)\n");
return 1;
}
- for (j = 0; j < UDF_SB_NUMPARTS(sb); j++) {
+ for (j = 0; j < sbi->s_partitions; j++) {
+ struct udf_part_map *map2 = &sbi->s_partmaps[j];
if (j != i &&
- UDF_SB_PARTVSN(sb, i) == UDF_SB_PARTVSN(sb, j) &&
- UDF_SB_PARTNUM(sb, i) == UDF_SB_PARTNUM(sb, j)) {
+ map->s_volumeseqnum ==
+ map2->s_volumeseqnum &&
+ map->s_partition_num ==
+ map2->s_partition_num) {
ino.partitionReferenceNum = j;
- ino.logicalBlockNum = UDF_SB_LASTBLOCK(sb) - UDF_SB_PARTROOT(sb, j);
+ ino.logicalBlockNum =
+ sbi->s_last_block -
+ map2->s_partition_root;
break;
}
}
- if (j == UDF_SB_NUMPARTS(sb))
+ if (j == sbi->s_partitions)
return 1;
- if (!(UDF_SB_VAT(sb) = udf_iget(sb, ino)))
+ sbi->s_vat_inode = udf_iget(sb, ino);
+ if (!sbi->s_vat_inode)
return 1;
- if (UDF_SB_PARTTYPE(sb, i) == UDF_VIRTUAL_MAP15) {
- UDF_SB_TYPEVIRT(sb, i).s_start_offset =
- udf_ext0_offset(UDF_SB_VAT(sb));
- UDF_SB_TYPEVIRT(sb, i).s_num_entries =
- (UDF_SB_VAT(sb)->i_size - 36) >> 2;
- } else if (UDF_SB_PARTTYPE(sb, i) == UDF_VIRTUAL_MAP20) {
- struct buffer_head *bh = NULL;
+ if (map->s_partition_type == UDF_VIRTUAL_MAP15) {
+ map->s_type_specific.s_virtual.s_start_offset =
+ udf_ext0_offset(sbi->s_vat_inode);
+ map->s_type_specific.s_virtual.s_num_entries =
+ (sbi->s_vat_inode->i_size - 36) >> 2;
+ } else if (map->s_partition_type == UDF_VIRTUAL_MAP20) {
uint32_t pos;
+ struct virtualAllocationTable20 *vat20;
- pos = udf_block_map(UDF_SB_VAT(sb), 0);
+ pos = udf_block_map(sbi->s_vat_inode, 0);
bh = sb_bread(sb, pos);
if (!bh)
return 1;
- UDF_SB_TYPEVIRT(sb, i).s_start_offset =
- le16_to_cpu(((struct virtualAllocationTable20 *)bh->b_data +
- udf_ext0_offset(UDF_SB_VAT(sb)))->lengthHeader) +
- udf_ext0_offset(UDF_SB_VAT(sb));
- UDF_SB_TYPEVIRT(sb, i).s_num_entries = (UDF_SB_VAT(sb)->i_size -
- UDF_SB_TYPEVIRT(sb, i).s_start_offset) >> 2;
+ vat20 = (struct virtualAllocationTable20 *)
+ bh->b_data +
+ udf_ext0_offset(sbi->s_vat_inode);
+ map->s_type_specific.s_virtual.s_start_offset =
+ le16_to_cpu(vat20->lengthHeader) +
+ udf_ext0_offset(sbi->s_vat_inode);
+ map->s_type_specific.s_virtual.s_num_entries =
+ (sbi->s_vat_inode->i_size -
+ map->s_type_specific.s_virtual.
+ s_start_offset) >> 2;
brelse(bh);
}
- UDF_SB_PARTROOT(sb, i) = udf_get_pblock(sb, 0, i, 0);
- UDF_SB_PARTLEN(sb, i) = UDF_SB_PARTLEN(sb, ino.partitionReferenceNum);
+ map->s_partition_root = udf_get_pblock(sb, 0, i, 0);
+ map->s_partition_len =
+ sbi->s_partmaps[ino.partitionReferenceNum].
+ s_partition_len;
}
}
return 0;
static void udf_open_lvid(struct super_block *sb)
{
- if (UDF_SB_LVIDBH(sb)) {
- int i;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct buffer_head *bh = sbi->s_lvid_bh;
+ if (bh) {
kernel_timestamp cpu_time;
+ struct logicalVolIntegrityDesc *lvid =
+ (struct logicalVolIntegrityDesc *)bh->b_data;
+ struct logicalVolIntegrityDescImpUse *lvidiu =
+ udf_sb_lvidiu(sbi);
- UDF_SB_LVIDIU(sb)->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
- UDF_SB_LVIDIU(sb)->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
+ lvidiu->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
+ lvidiu->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
if (udf_time_to_stamp(&cpu_time, CURRENT_TIME))
- UDF_SB_LVID(sb)->recordingDateAndTime = cpu_to_lets(cpu_time);
- UDF_SB_LVID(sb)->integrityType = LVID_INTEGRITY_TYPE_OPEN;
-
- UDF_SB_LVID(sb)->descTag.descCRC = cpu_to_le16(udf_crc((char *)UDF_SB_LVID(sb) + sizeof(tag),
- le16_to_cpu(UDF_SB_LVID(sb)->descTag.descCRCLength), 0));
+ lvid->recordingDateAndTime = cpu_to_lets(cpu_time);
+ lvid->integrityType = LVID_INTEGRITY_TYPE_OPEN;
- UDF_SB_LVID(sb)->descTag.tagChecksum = 0;
- for (i = 0; i < 16; i++)
- if (i != 4)
- UDF_SB_LVID(sb)->descTag.tagChecksum +=
- ((uint8_t *) &(UDF_SB_LVID(sb)->descTag))[i];
+ lvid->descTag.descCRC = cpu_to_le16(
+ udf_crc((char *)lvid + sizeof(tag),
+ le16_to_cpu(lvid->descTag.descCRCLength),
+ 0));
- mark_buffer_dirty(UDF_SB_LVIDBH(sb));
+ lvid->descTag.tagChecksum = udf_tag_checksum(&lvid->descTag);
+ mark_buffer_dirty(bh);
}
}
static void udf_close_lvid(struct super_block *sb)
{
kernel_timestamp cpu_time;
- int i;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct buffer_head *bh = sbi->s_lvid_bh;
+ struct logicalVolIntegrityDesc *lvid;
+
+ if (!bh)
+ return;
+
+ lvid = (struct logicalVolIntegrityDesc *)bh->b_data;
- if (UDF_SB_LVIDBH(sb) &&
- UDF_SB_LVID(sb)->integrityType == LVID_INTEGRITY_TYPE_OPEN) {
- UDF_SB_LVIDIU(sb)->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
- UDF_SB_LVIDIU(sb)->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
+ if (lvid->integrityType == LVID_INTEGRITY_TYPE_OPEN) {
+ struct logicalVolIntegrityDescImpUse *lvidiu =
+ udf_sb_lvidiu(sbi);
+ lvidiu->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
+ lvidiu->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
if (udf_time_to_stamp(&cpu_time, CURRENT_TIME))
- UDF_SB_LVID(sb)->recordingDateAndTime = cpu_to_lets(cpu_time);
- if (UDF_MAX_WRITE_VERSION > le16_to_cpu(UDF_SB_LVIDIU(sb)->maxUDFWriteRev))
- UDF_SB_LVIDIU(sb)->maxUDFWriteRev = cpu_to_le16(UDF_MAX_WRITE_VERSION);
- if (UDF_SB_UDFREV(sb) > le16_to_cpu(UDF_SB_LVIDIU(sb)->minUDFReadRev))
- UDF_SB_LVIDIU(sb)->minUDFReadRev = cpu_to_le16(UDF_SB_UDFREV(sb));
- if (UDF_SB_UDFREV(sb) > le16_to_cpu(UDF_SB_LVIDIU(sb)->minUDFWriteRev))
- UDF_SB_LVIDIU(sb)->minUDFWriteRev = cpu_to_le16(UDF_SB_UDFREV(sb));
- UDF_SB_LVID(sb)->integrityType = cpu_to_le32(LVID_INTEGRITY_TYPE_CLOSE);
-
- UDF_SB_LVID(sb)->descTag.descCRC =
- cpu_to_le16(udf_crc((char *)UDF_SB_LVID(sb) + sizeof(tag),
- le16_to_cpu(UDF_SB_LVID(sb)->descTag.descCRCLength), 0));
-
- UDF_SB_LVID(sb)->descTag.tagChecksum = 0;
- for (i = 0; i < 16; i++)
- if (i != 4)
- UDF_SB_LVID(sb)->descTag.tagChecksum +=
- ((uint8_t *)&(UDF_SB_LVID(sb)->descTag))[i];
-
- mark_buffer_dirty(UDF_SB_LVIDBH(sb));
+ lvid->recordingDateAndTime = cpu_to_lets(cpu_time);
+ if (UDF_MAX_WRITE_VERSION > le16_to_cpu(lvidiu->maxUDFWriteRev))
+ lvidiu->maxUDFWriteRev =
+ cpu_to_le16(UDF_MAX_WRITE_VERSION);
+ if (sbi->s_udfrev > le16_to_cpu(lvidiu->minUDFReadRev))
+ lvidiu->minUDFReadRev = cpu_to_le16(sbi->s_udfrev);
+ if (sbi->s_udfrev > le16_to_cpu(lvidiu->minUDFWriteRev))
+ lvidiu->minUDFWriteRev = cpu_to_le16(sbi->s_udfrev);
+ lvid->integrityType = cpu_to_le32(LVID_INTEGRITY_TYPE_CLOSE);
+
+ lvid->descTag.descCRC = cpu_to_le16(
+ udf_crc((char *)lvid + sizeof(tag),
+ le16_to_cpu(lvid->descTag.descCRCLength),
+ 0));
+
+ lvid->descTag.tagChecksum = udf_tag_checksum(&lvid->descTag);
+ mark_buffer_dirty(bh);
}
}
+static void udf_sb_free_bitmap(struct udf_bitmap *bitmap)
+{
+ int i;
+ int nr_groups = bitmap->s_nr_groups;
+ int size = sizeof(struct udf_bitmap) + (sizeof(struct buffer_head *) *
+ nr_groups);
+
+ for (i = 0; i < nr_groups; i++)
+ if (bitmap->s_block_bitmap[i])
+ brelse(bitmap->s_block_bitmap[i]);
+
+ if (size <= PAGE_SIZE)
+ kfree(bitmap);
+ else
+ vfree(bitmap);
+}
+
/*
* udf_read_super
*
uopt.gid = -1;
uopt.umask = 0;
- sbi = kmalloc(sizeof(struct udf_sb_info), GFP_KERNEL);
+ sbi = kzalloc(sizeof(struct udf_sb_info), GFP_KERNEL);
if (!sbi)
return -ENOMEM;
sb->s_fs_info = sbi;
- memset(UDF_SB(sb), 0x00, sizeof(struct udf_sb_info));
mutex_init(&sbi->s_alloc_mutex);
- if (!udf_parse_options((char *)options, &uopt))
+ if (!udf_parse_options((char *)options, &uopt, false))
goto error_out;
if (uopt.flags & (1 << UDF_FLAG_UTF8) &&
fileset.logicalBlockNum = 0xFFFFFFFF;
fileset.partitionReferenceNum = 0xFFFF;
- UDF_SB(sb)->s_flags = uopt.flags;
- UDF_SB(sb)->s_uid = uopt.uid;
- UDF_SB(sb)->s_gid = uopt.gid;
- UDF_SB(sb)->s_umask = uopt.umask;
- UDF_SB(sb)->s_nls_map = uopt.nls_map;
+ sbi->s_flags = uopt.flags;
+ sbi->s_uid = uopt.uid;
+ sbi->s_gid = uopt.gid;
+ sbi->s_umask = uopt.umask;
+ sbi->s_nls_map = uopt.nls_map;
/* Set the block size for all transfers */
if (!udf_set_blocksize(sb, uopt.blocksize))
goto error_out;
if (uopt.session == 0xFFFFFFFF)
- UDF_SB_SESSION(sb) = udf_get_last_session(sb);
+ sbi->s_session = udf_get_last_session(sb);
else
- UDF_SB_SESSION(sb) = uopt.session;
+ sbi->s_session = uopt.session;
- udf_debug("Multi-session=%d\n", UDF_SB_SESSION(sb));
+ udf_debug("Multi-session=%d\n", sbi->s_session);
- UDF_SB_LASTBLOCK(sb) = uopt.lastblock;
- UDF_SB_ANCHOR(sb)[0] = UDF_SB_ANCHOR(sb)[1] = 0;
- UDF_SB_ANCHOR(sb)[2] = uopt.anchor;
- UDF_SB_ANCHOR(sb)[3] = 256;
+ sbi->s_last_block = uopt.lastblock;
+ sbi->s_anchor[0] = sbi->s_anchor[1] = 0;
+ sbi->s_anchor[2] = uopt.anchor;
+ sbi->s_anchor[3] = 256;
- if (udf_check_valid(sb, uopt.novrs, silent)) { /* read volume recognition sequences */
- printk("UDF-fs: No VRS found\n");
+ if (udf_check_valid(sb, uopt.novrs, silent)) {
+ /* read volume recognition sequences */
+ printk(KERN_WARNING "UDF-fs: No VRS found\n");
goto error_out;
}
sb->s_time_gran = 1000;
if (udf_load_partition(sb, &fileset)) {
- printk("UDF-fs: No partition found (1)\n");
+ printk(KERN_WARNING "UDF-fs: No partition found (1)\n");
goto error_out;
}
- udf_debug("Lastblock=%d\n", UDF_SB_LASTBLOCK(sb));
+ udf_debug("Lastblock=%d\n", sbi->s_last_block);
- if (UDF_SB_LVIDBH(sb)) {
- uint16_t minUDFReadRev = le16_to_cpu(UDF_SB_LVIDIU(sb)->minUDFReadRev);
- uint16_t minUDFWriteRev = le16_to_cpu(UDF_SB_LVIDIU(sb)->minUDFWriteRev);
- /* uint16_t maxUDFWriteRev = le16_to_cpu(UDF_SB_LVIDIU(sb)->maxUDFWriteRev); */
+ if (sbi->s_lvid_bh) {
+ struct logicalVolIntegrityDescImpUse *lvidiu =
+ udf_sb_lvidiu(sbi);
+ uint16_t minUDFReadRev = le16_to_cpu(lvidiu->minUDFReadRev);
+ uint16_t minUDFWriteRev = le16_to_cpu(lvidiu->minUDFWriteRev);
+ /* uint16_t maxUDFWriteRev =
+ le16_to_cpu(lvidiu->maxUDFWriteRev); */
if (minUDFReadRev > UDF_MAX_READ_VERSION) {
- printk("UDF-fs: minUDFReadRev=%x (max is %x)\n",
- le16_to_cpu(UDF_SB_LVIDIU(sb)->minUDFReadRev),
+ printk(KERN_ERR "UDF-fs: minUDFReadRev=%x "
+ "(max is %x)\n",
+ le16_to_cpu(lvidiu->minUDFReadRev),
UDF_MAX_READ_VERSION);
goto error_out;
- } else if (minUDFWriteRev > UDF_MAX_WRITE_VERSION) {
+ } else if (minUDFWriteRev > UDF_MAX_WRITE_VERSION)
sb->s_flags |= MS_RDONLY;
- }
- UDF_SB_UDFREV(sb) = minUDFWriteRev;
+ sbi->s_udfrev = minUDFWriteRev;
if (minUDFReadRev >= UDF_VERS_USE_EXTENDED_FE)
UDF_SET_FLAG(sb, UDF_FLAG_USE_EXTENDED_FE);
UDF_SET_FLAG(sb, UDF_FLAG_USE_STREAMS);
}
- if (!UDF_SB_NUMPARTS(sb)) {
- printk("UDF-fs: No partition found (2)\n");
+ if (!sbi->s_partitions) {
+ printk(KERN_WARNING "UDF-fs: No partition found (2)\n");
goto error_out;
}
- if (UDF_SB_PARTFLAGS(sb, UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_READ_ONLY) {
- printk("UDF-fs: Partition marked readonly; forcing readonly mount\n");
+ if (sbi->s_partmaps[sbi->s_partition].s_partition_flags &
+ UDF_PART_FLAG_READ_ONLY) {
+ printk(KERN_NOTICE "UDF-fs: Partition marked readonly; "
+ "forcing readonly mount\n");
sb->s_flags |= MS_RDONLY;
}
if (udf_find_fileset(sb, &fileset, &rootdir)) {
- printk("UDF-fs: No fileset found\n");
+ printk(KERN_WARNING "UDF-fs: No fileset found\n");
goto error_out;
}
if (!silent) {
kernel_timestamp ts;
- udf_time_to_stamp(&ts, UDF_SB_RECORDTIME(sb));
- udf_info("UDF %s (%s) Mounting volume '%s', "
+ udf_time_to_stamp(&ts, sbi->s_record_time);
+ udf_info("UDF: Mounting volume '%s', "
"timestamp %04u/%02u/%02u %02u:%02u (%x)\n",
- UDFFS_VERSION, UDFFS_DATE,
- UDF_SB_VOLIDENT(sb), ts.year, ts.month, ts.day, ts.hour, ts.minute,
- ts.typeAndTimezone);
+ sbi->s_volume_ident, ts.year, ts.month, ts.day,
+ ts.hour, ts.minute, ts.typeAndTimezone);
}
if (!(sb->s_flags & MS_RDONLY))
udf_open_lvid(sb);
/* perhaps it's not extensible enough, but for now ... */
inode = udf_iget(sb, rootdir);
if (!inode) {
- printk("UDF-fs: Error in udf_iget, block=%d, partition=%d\n",
+ printk(KERN_ERR "UDF-fs: Error in udf_iget, block=%d, "
+ "partition=%d\n",
rootdir.logicalBlockNum, rootdir.partitionReferenceNum);
goto error_out;
}
/* Allocate a dentry for the root inode */
sb->s_root = d_alloc_root(inode);
if (!sb->s_root) {
- printk("UDF-fs: Couldn't allocate root dentry\n");
+ printk(KERN_ERR "UDF-fs: Couldn't allocate root dentry\n");
iput(inode);
goto error_out;
}
return 0;
error_out:
- if (UDF_SB_VAT(sb))
- iput(UDF_SB_VAT(sb));
- if (UDF_SB_NUMPARTS(sb)) {
- if (UDF_SB_PARTFLAGS(sb, UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_UNALLOC_TABLE)
- iput(UDF_SB_PARTMAPS(sb)[UDF_SB_PARTITION(sb)].s_uspace.s_table);
- if (UDF_SB_PARTFLAGS(sb, UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_FREED_TABLE)
- iput(UDF_SB_PARTMAPS(sb)[UDF_SB_PARTITION(sb)].s_fspace.s_table);
- if (UDF_SB_PARTFLAGS(sb, UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_UNALLOC_BITMAP)
- UDF_SB_FREE_BITMAP(sb,UDF_SB_PARTITION(sb), s_uspace);
- if (UDF_SB_PARTFLAGS(sb, UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_FREED_BITMAP)
- UDF_SB_FREE_BITMAP(sb,UDF_SB_PARTITION(sb), s_fspace);
- if (UDF_SB_PARTTYPE(sb, UDF_SB_PARTITION(sb)) == UDF_SPARABLE_MAP15) {
+ if (sbi->s_vat_inode)
+ iput(sbi->s_vat_inode);
+ if (sbi->s_partitions) {
+ struct udf_part_map *map = &sbi->s_partmaps[sbi->s_partition];
+ if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_TABLE)
+ iput(map->s_uspace.s_table);
+ if (map->s_partition_flags & UDF_PART_FLAG_FREED_TABLE)
+ iput(map->s_fspace.s_table);
+ if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_BITMAP)
+ udf_sb_free_bitmap(map->s_uspace.s_bitmap);
+ if (map->s_partition_flags & UDF_PART_FLAG_FREED_BITMAP)
+ udf_sb_free_bitmap(map->s_fspace.s_bitmap);
+ if (map->s_partition_type == UDF_SPARABLE_MAP15)
for (i = 0; i < 4; i++)
- brelse(UDF_SB_TYPESPAR(sb, UDF_SB_PARTITION(sb)).s_spar_map[i]);
- }
+ brelse(map->s_type_specific.s_sparing.
+ s_spar_map[i]);
}
#ifdef CONFIG_UDF_NLS
if (UDF_QUERY_FLAG(sb, UDF_FLAG_NLS_MAP))
- unload_nls(UDF_SB(sb)->s_nls_map);
+ unload_nls(sbi->s_nls_map);
#endif
if (!(sb->s_flags & MS_RDONLY))
udf_close_lvid(sb);
- brelse(UDF_SB_LVIDBH(sb));
- UDF_SB_FREE(sb);
+ brelse(sbi->s_lvid_bh);
+
+ kfree(sbi->s_partmaps);
kfree(sbi);
sb->s_fs_info = NULL;
va_start(args, fmt);
vsnprintf(error_buf, sizeof(error_buf), fmt, args);
va_end(args);
- printk (KERN_CRIT "UDF-fs error (device %s): %s: %s\n",
+ printk(KERN_CRIT "UDF-fs error (device %s): %s: %s\n",
sb->s_id, function, error_buf);
}
static void udf_put_super(struct super_block *sb)
{
int i;
+ struct udf_sb_info *sbi;
- if (UDF_SB_VAT(sb))
- iput(UDF_SB_VAT(sb));
- if (UDF_SB_NUMPARTS(sb)) {
- if (UDF_SB_PARTFLAGS(sb, UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_UNALLOC_TABLE)
- iput(UDF_SB_PARTMAPS(sb)[UDF_SB_PARTITION(sb)].s_uspace.s_table);
- if (UDF_SB_PARTFLAGS(sb, UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_FREED_TABLE)
- iput(UDF_SB_PARTMAPS(sb)[UDF_SB_PARTITION(sb)].s_fspace.s_table);
- if (UDF_SB_PARTFLAGS(sb, UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_UNALLOC_BITMAP)
- UDF_SB_FREE_BITMAP(sb,UDF_SB_PARTITION(sb), s_uspace);
- if (UDF_SB_PARTFLAGS(sb, UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_FREED_BITMAP)
- UDF_SB_FREE_BITMAP(sb,UDF_SB_PARTITION(sb), s_fspace);
- if (UDF_SB_PARTTYPE(sb, UDF_SB_PARTITION(sb)) == UDF_SPARABLE_MAP15) {
+ sbi = UDF_SB(sb);
+ if (sbi->s_vat_inode)
+ iput(sbi->s_vat_inode);
+ if (sbi->s_partitions) {
+ struct udf_part_map *map = &sbi->s_partmaps[sbi->s_partition];
+ if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_TABLE)
+ iput(map->s_uspace.s_table);
+ if (map->s_partition_flags & UDF_PART_FLAG_FREED_TABLE)
+ iput(map->s_fspace.s_table);
+ if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_BITMAP)
+ udf_sb_free_bitmap(map->s_uspace.s_bitmap);
+ if (map->s_partition_flags & UDF_PART_FLAG_FREED_BITMAP)
+ udf_sb_free_bitmap(map->s_fspace.s_bitmap);
+ if (map->s_partition_type == UDF_SPARABLE_MAP15)
for (i = 0; i < 4; i++)
- brelse(UDF_SB_TYPESPAR(sb, UDF_SB_PARTITION(sb)).s_spar_map[i]);
- }
+ brelse(map->s_type_specific.s_sparing.
+ s_spar_map[i]);
}
#ifdef CONFIG_UDF_NLS
if (UDF_QUERY_FLAG(sb, UDF_FLAG_NLS_MAP))
- unload_nls(UDF_SB(sb)->s_nls_map);
+ unload_nls(sbi->s_nls_map);
#endif
if (!(sb->s_flags & MS_RDONLY))
udf_close_lvid(sb);
- brelse(UDF_SB_LVIDBH(sb));
- UDF_SB_FREE(sb);
+ brelse(sbi->s_lvid_bh);
+ kfree(sbi->s_partmaps);
kfree(sb->s_fs_info);
sb->s_fs_info = NULL;
}
static int udf_statfs(struct dentry *dentry, struct kstatfs *buf)
{
struct super_block *sb = dentry->d_sb;
+ struct udf_sb_info *sbi = UDF_SB(sb);
+ struct logicalVolIntegrityDescImpUse *lvidiu;
+
+ if (sbi->s_lvid_bh != NULL)
+ lvidiu = udf_sb_lvidiu(sbi);
+ else
+ lvidiu = NULL;
buf->f_type = UDF_SUPER_MAGIC;
buf->f_bsize = sb->s_blocksize;
- buf->f_blocks = UDF_SB_PARTLEN(sb, UDF_SB_PARTITION(sb));
+ buf->f_blocks = sbi->s_partmaps[sbi->s_partition].s_partition_len;
buf->f_bfree = udf_count_free(sb);
buf->f_bavail = buf->f_bfree;
- buf->f_files = (UDF_SB_LVIDBH(sb) ?
- (le32_to_cpu(UDF_SB_LVIDIU(sb)->numFiles) +
- le32_to_cpu(UDF_SB_LVIDIU(sb)->numDirs)) : 0) + buf->f_bfree;
+ buf->f_files = (lvidiu != NULL ? (le32_to_cpu(lvidiu->numFiles) +
+ le32_to_cpu(lvidiu->numDirs)) : 0)
+ + buf->f_bfree;
buf->f_ffree = buf->f_bfree;
/* __kernel_fsid_t f_fsid */
buf->f_namelen = UDF_NAME_LEN - 2;
0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4
};
-static unsigned int udf_count_free_bitmap(struct super_block *sb, struct udf_bitmap *bitmap)
+static unsigned int udf_count_free_bitmap(struct super_block *sb,
+ struct udf_bitmap *bitmap)
{
struct buffer_head *bh = NULL;
unsigned int accum = 0;
lock_kernel();
loc.logicalBlockNum = bitmap->s_extPosition;
- loc.partitionReferenceNum = UDF_SB_PARTITION(sb);
+ loc.partitionReferenceNum = UDF_SB(sb)->s_partition;
bh = udf_read_ptagged(sb, loc, 0, &ident);
if (!bh) {
return accum;
}
-static unsigned int udf_count_free_table(struct super_block *sb, struct inode *table)
+static unsigned int udf_count_free_table(struct super_block *sb,
+ struct inode *table)
{
unsigned int accum = 0;
uint32_t elen;
lock_kernel();
- epos.block = UDF_I_LOCATION(table);
+ epos.block = UDF_I(table)->i_location;
epos.offset = sizeof(struct unallocSpaceEntry);
epos.bh = NULL;
- while ((etype = udf_next_aext(table, &epos, &eloc, &elen, 1)) != -1) {
+ while ((etype = udf_next_aext(table, &epos, &eloc, &elen, 1)) != -1)
accum += (elen >> table->i_sb->s_blocksize_bits);
- }
+
brelse(epos.bh);
unlock_kernel();
static unsigned int udf_count_free(struct super_block *sb)
{
unsigned int accum = 0;
-
- if (UDF_SB_LVIDBH(sb)) {
- if (le32_to_cpu(UDF_SB_LVID(sb)->numOfPartitions) > UDF_SB_PARTITION(sb)) {
- accum = le32_to_cpu(UDF_SB_LVID(sb)->freeSpaceTable[UDF_SB_PARTITION(sb)]);
+ struct udf_sb_info *sbi;
+ struct udf_part_map *map;
+
+ sbi = UDF_SB(sb);
+ if (sbi->s_lvid_bh) {
+ struct logicalVolIntegrityDesc *lvid =
+ (struct logicalVolIntegrityDesc *)
+ sbi->s_lvid_bh->b_data;
+ if (le32_to_cpu(lvid->numOfPartitions) > sbi->s_partition) {
+ accum = le32_to_cpu(
+ lvid->freeSpaceTable[sbi->s_partition]);
if (accum == 0xFFFFFFFF)
accum = 0;
}
if (accum)
return accum;
- if (UDF_SB_PARTFLAGS(sb,UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_UNALLOC_BITMAP) {
+ map = &sbi->s_partmaps[sbi->s_partition];
+ if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_BITMAP) {
accum += udf_count_free_bitmap(sb,
- UDF_SB_PARTMAPS(sb)[UDF_SB_PARTITION(sb)].s_uspace.s_bitmap);
+ map->s_uspace.s_bitmap);
}
- if (UDF_SB_PARTFLAGS(sb,UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_FREED_BITMAP) {
+ if (map->s_partition_flags & UDF_PART_FLAG_FREED_BITMAP) {
accum += udf_count_free_bitmap(sb,
- UDF_SB_PARTMAPS(sb)[UDF_SB_PARTITION(sb)].s_fspace.s_bitmap);
+ map->s_fspace.s_bitmap);
}
if (accum)
return accum;
- if (UDF_SB_PARTFLAGS(sb,UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_UNALLOC_TABLE) {
+ if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_TABLE) {
accum += udf_count_free_table(sb,
- UDF_SB_PARTMAPS(sb)[UDF_SB_PARTITION(sb)].s_uspace.s_table);
+ map->s_uspace.s_table);
}
- if (UDF_SB_PARTFLAGS(sb,UDF_SB_PARTITION(sb)) & UDF_PART_FLAG_FREED_TABLE) {
+ if (map->s_partition_flags & UDF_PART_FLAG_FREED_TABLE) {
accum += udf_count_free_table(sb,
- UDF_SB_PARTMAPS(sb)[UDF_SB_PARTITION(sb)].s_fspace.s_table);
+ map->s_fspace.s_table);
}
return accum;
#include <linux/buffer_head.h>
#include "udf_i.h"
-static void udf_pc_to_char(struct super_block *sb, char *from, int fromlen, char *to)
+static void udf_pc_to_char(struct super_block *sb, char *from, int fromlen,
+ char *to)
{
struct pathComponent *pc;
int elen = 0;
char *symlink;
int err = -EIO;
char *p = kmap(page);
+ struct udf_inode_info *iinfo;
lock_kernel();
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB) {
- symlink = UDF_I_DATA(inode) + UDF_I_LENEATTR(inode);
+ iinfo = UDF_I(inode);
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB) {
+ symlink = iinfo->i_ext.i_data + iinfo->i_lenEAttr;
} else {
bh = sb_bread(inode->i_sb, udf_block_map(inode, 0));
uint64_t lbcount = 0;
int8_t etype = -1, netype;
int adsize;
+ struct udf_inode_info *iinfo = UDF_I(inode);
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB ||
- inode->i_size == UDF_I_LENEXTENTS(inode))
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB ||
+ inode->i_size == iinfo->i_lenExtents)
return;
/* Are we going to delete the file anyway? */
if (inode->i_nlink == 0)
return;
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
adsize = sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
+ else if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
adsize = sizeof(long_ad);
else
BUG();
}
/* This inode entry is in-memory only and thus we don't have to mark
* the inode dirty */
- UDF_I_LENEXTENTS(inode) = inode->i_size;
+ iinfo->i_lenExtents = inode->i_size;
brelse(epos.bh);
}
uint64_t lbcount = 0;
int8_t etype = -1, netype;
int adsize;
+ struct udf_inode_info *iinfo = UDF_I(inode);
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB ||
- inode->i_size == UDF_I_LENEXTENTS(inode))
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB ||
+ inode->i_size == iinfo->i_lenExtents)
return;
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
adsize = sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
+ else if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
adsize = sizeof(long_ad);
else
adsize = 0;
- epos.block = UDF_I_LOCATION(inode);
+ epos.block = iinfo->i_location;
/* Find the last extent in the file */
while ((netype = udf_next_aext(inode, &epos, &eloc, &elen, 1)) != -1) {
lbcount -= elen;
extent_trunc(inode, &epos, eloc, etype, elen, 0);
if (!epos.bh) {
- UDF_I_LENALLOC(inode) =
- epos.offset - udf_file_entry_alloc_offset(inode);
+ iinfo->i_lenAlloc =
+ epos.offset -
+ udf_file_entry_alloc_offset(inode);
mark_inode_dirty(inode);
} else {
struct allocExtDesc *aed =
cpu_to_le32(epos.offset -
sizeof(struct allocExtDesc));
if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) ||
- UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
+ UDF_SB(inode->i_sb)->s_udfrev >= 0x0201)
udf_update_tag(epos.bh->b_data, epos.offset);
else
udf_update_tag(epos.bh->b_data,
}
/* This inode entry is in-memory only and thus we don't have to mark
* the inode dirty */
- UDF_I_LENEXTENTS(inode) = lbcount;
+ iinfo->i_lenExtents = lbcount;
brelse(epos.bh);
}
uint32_t elen, nelen = 0, indirect_ext_len = 0, lenalloc;
int8_t etype;
struct super_block *sb = inode->i_sb;
+ struct udf_sb_info *sbi = UDF_SB(sb);
sector_t first_block = inode->i_size >> sb->s_blocksize_bits, offset;
loff_t byte_offset;
int adsize;
+ struct udf_inode_info *iinfo = UDF_I(inode);
- if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
+ if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_SHORT)
adsize = sizeof(short_ad);
- else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
+ else if (iinfo->i_alloc_type == ICBTAG_FLAG_AD_LONG)
adsize = sizeof(long_ad);
else
BUG();
else
lenalloc -= sizeof(struct allocExtDesc);
- while ((etype = udf_current_aext(inode, &epos, &eloc, &elen, 0)) != -1) {
+ while ((etype = udf_current_aext(inode, &epos, &eloc,
+ &elen, 0)) != -1) {
if (etype == (EXT_NEXT_EXTENT_ALLOCDECS >> 30)) {
udf_write_aext(inode, &epos, neloc, nelen, 0);
if (indirect_ext_len) {
0, indirect_ext_len);
} else {
if (!epos.bh) {
- UDF_I_LENALLOC(inode) = lenalloc;
+ iinfo->i_lenAlloc =
+ lenalloc;
mark_inode_dirty(inode);
} else {
struct allocExtDesc *aed =
- (struct allocExtDesc *)(epos.bh->b_data);
+ (struct allocExtDesc *)
+ (epos.bh->b_data);
+ int len =
+ sizeof(struct allocExtDesc);
+
aed->lengthAllocDescs =
cpu_to_le32(lenalloc);
- if (!UDF_QUERY_FLAG(sb, UDF_FLAG_STRICT) ||
- UDF_SB_UDFREV(sb) >= 0x0201)
- udf_update_tag(epos.bh->b_data,
- lenalloc +
- sizeof(struct allocExtDesc));
- else
- udf_update_tag(epos.bh->b_data,
- sizeof(struct allocExtDesc));
- mark_buffer_dirty_inode(epos.bh, inode);
+ if (!UDF_QUERY_FLAG(sb,
+ UDF_FLAG_STRICT) ||
+ sbi->s_udfrev >= 0x0201)
+ len += lenalloc;
+
+ udf_update_tag(epos.bh->b_data,
+ len);
+ mark_buffer_dirty_inode(
+ epos.bh, inode);
}
}
brelse(epos.bh);
epos.offset = sizeof(struct allocExtDesc);
epos.block = eloc;
- epos.bh = udf_tread(sb, udf_get_lb_pblock(sb, eloc, 0));
+ epos.bh = udf_tread(sb,
+ udf_get_lb_pblock(sb, eloc, 0));
if (elen)
- indirect_ext_len = (elen + sb->s_blocksize -1) >>
+ indirect_ext_len =
+ (elen + sb->s_blocksize - 1) >>
sb->s_blocksize_bits;
else
indirect_ext_len = 1;
} else {
- extent_trunc(inode, &epos, eloc, etype, elen, 0);
+ extent_trunc(inode, &epos, eloc, etype,
+ elen, 0);
epos.offset += adsize;
}
}
indirect_ext_len);
} else {
if (!epos.bh) {
- UDF_I_LENALLOC(inode) = lenalloc;
+ iinfo->i_lenAlloc = lenalloc;
mark_inode_dirty(inode);
} else {
struct allocExtDesc *aed =
(struct allocExtDesc *)(epos.bh->b_data);
aed->lengthAllocDescs = cpu_to_le32(lenalloc);
if (!UDF_QUERY_FLAG(sb, UDF_FLAG_STRICT) ||
- UDF_SB_UDFREV(sb) >= 0x0201)
+ sbi->s_udfrev >= 0x0201)
udf_update_tag(epos.bh->b_data,
- lenalloc + sizeof(struct allocExtDesc));
+ lenalloc +
+ sizeof(struct allocExtDesc));
else
udf_update_tag(epos.bh->b_data,
- sizeof(struct allocExtDesc));
+ sizeof(struct allocExtDesc));
mark_buffer_dirty_inode(epos.bh, inode);
}
}
* extending the file by 'offset' blocks.
*/
if ((!epos.bh &&
- epos.offset == udf_file_entry_alloc_offset(inode)) ||
- (epos.bh && epos.offset == sizeof(struct allocExtDesc))) {
+ epos.offset ==
+ udf_file_entry_alloc_offset(inode)) ||
+ (epos.bh && epos.offset ==
+ sizeof(struct allocExtDesc))) {
/* File has no extents at all or has empty last
* indirect extent! Create a fake extent... */
extent.extLocation.logicalBlockNum = 0;
extent.extLocation.partitionReferenceNum = 0;
- extent.extLength = EXT_NOT_RECORDED_NOT_ALLOCATED;
+ extent.extLength =
+ EXT_NOT_RECORDED_NOT_ALLOCATED;
} else {
epos.offset -= adsize;
etype = udf_next_aext(inode, &epos,
extent.extLength |= etype << 30;
}
udf_extend_file(inode, &epos, &extent,
- offset + ((inode->i_size & (sb->s_blocksize - 1)) != 0));
+ offset +
+ ((inode->i_size &
+ (sb->s_blocksize - 1)) != 0));
}
}
- UDF_I_LENEXTENTS(inode) = inode->i_size;
+ iinfo->i_lenExtents = inode->i_size;
brelse(epos.bh);
}
return list_entry(inode, struct udf_inode_info, vfs_inode);
}
-#define UDF_I_LOCATION(X) ( UDF_I(X)->i_location )
-#define UDF_I_LENEATTR(X) ( UDF_I(X)->i_lenEAttr )
-#define UDF_I_LENALLOC(X) ( UDF_I(X)->i_lenAlloc )
-#define UDF_I_LENEXTENTS(X) ( UDF_I(X)->i_lenExtents )
-#define UDF_I_UNIQUE(X) ( UDF_I(X)->i_unique )
-#define UDF_I_ALLOCTYPE(X) ( UDF_I(X)->i_alloc_type )
-#define UDF_I_EFE(X) ( UDF_I(X)->i_efe )
-#define UDF_I_USE(X) ( UDF_I(X)->i_use )
-#define UDF_I_STRAT4096(X) ( UDF_I(X)->i_strat4096 )
-#define UDF_I_NEXT_ALLOC_BLOCK(X) ( UDF_I(X)->i_next_alloc_block )
-#define UDF_I_NEXT_ALLOC_GOAL(X) ( UDF_I(X)->i_next_alloc_goal )
-#define UDF_I_CRTIME(X) ( UDF_I(X)->i_crtime )
-#define UDF_I_SAD(X) ( UDF_I(X)->i_ext.i_sad )
-#define UDF_I_LAD(X) ( UDF_I(X)->i_ext.i_lad )
-#define UDF_I_DATA(X) ( UDF_I(X)->i_ext.i_data )
-
#endif /* !defined(_LINUX_UDF_I_H) */
#define UDF_FLAG_GID_IGNORE 14
#define UDF_FLAG_UID_SET 15
#define UDF_FLAG_GID_SET 16
+#define UDF_FLAG_SESSION_SET 17
+#define UDF_FLAG_LASTBLOCK_SET 18
#define UDF_PART_FLAG_UNALLOC_BITMAP 0x0001
#define UDF_PART_FLAG_UNALLOC_TABLE 0x0002
return sb->s_fs_info;
}
-#define UDF_SB_FREE(X)\
-{\
- if (UDF_SB(X)) {\
- kfree(UDF_SB_PARTMAPS(X));\
- UDF_SB_PARTMAPS(X) = NULL;\
- }\
-}
-
-#define UDF_SB_ALLOC_PARTMAPS(X,Y)\
-{\
- UDF_SB_PARTMAPS(X) = kmalloc(sizeof(struct udf_part_map) * Y, GFP_KERNEL);\
- if (UDF_SB_PARTMAPS(X) != NULL) {\
- UDF_SB_NUMPARTS(X) = Y;\
- memset(UDF_SB_PARTMAPS(X), 0x00, sizeof(struct udf_part_map) * Y);\
- } else {\
- UDF_SB_NUMPARTS(X) = 0;\
- udf_error(X, __FUNCTION__, "Unable to allocate space for %d partition maps", Y);\
- }\
-}
-
-#define UDF_SB_ALLOC_BITMAP(X,Y,Z)\
-{\
- int nr_groups = ((UDF_SB_PARTLEN((X),(Y)) + (sizeof(struct spaceBitmapDesc) << 3) +\
- ((X)->s_blocksize * 8) - 1) / ((X)->s_blocksize * 8));\
- int size = sizeof(struct udf_bitmap) + (sizeof(struct buffer_head *) * nr_groups);\
- if (size <= PAGE_SIZE)\
- UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap = kmalloc(size, GFP_KERNEL);\
- else\
- UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap = vmalloc(size);\
- if (UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap != NULL) {\
- memset(UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap, 0x00, size);\
- UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap->s_block_bitmap =\
- (struct buffer_head **)(UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap + 1);\
- UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap->s_nr_groups = nr_groups;\
- } else {\
- udf_error(X, __FUNCTION__, "Unable to allocate space for bitmap and %d buffer_head pointers", nr_groups);\
- }\
-}
+struct logicalVolIntegrityDescImpUse *udf_sb_lvidiu(struct udf_sb_info *sbi);
-#define UDF_SB_FREE_BITMAP(X,Y,Z)\
-{\
- int i;\
- int nr_groups = UDF_SB_BITMAP_NR_GROUPS(X,Y,Z);\
- int size = sizeof(struct udf_bitmap) + (sizeof(struct buffer_head *) * nr_groups);\
- for (i = 0; i < nr_groups; i++) {\
- if (UDF_SB_BITMAP(X,Y,Z,i))\
- brelse(UDF_SB_BITMAP(X,Y,Z,i));\
- }\
- if (size <= PAGE_SIZE)\
- kfree(UDF_SB_PARTMAPS(X)[Y].Z.s_bitmap);\
- else\
- vfree(UDF_SB_PARTMAPS(X)[Y].Z.s_bitmap);\
-}
+int udf_compute_nr_groups(struct super_block *sb, u32 partition);
#define UDF_QUERY_FLAG(X,Y) ( UDF_SB(X)->s_flags & ( 1 << (Y) ) )
#define UDF_SET_FLAG(X,Y) ( UDF_SB(X)->s_flags |= ( 1 << (Y) ) )
#define UDF_CLEAR_FLAG(X,Y) ( UDF_SB(X)->s_flags &= ~( 1 << (Y) ) )
-#define UDF_UPDATE_UDFREV(X,Y) ( ((Y) > UDF_SB_UDFREV(X)) ? UDF_SB_UDFREV(X) = (Y) : UDF_SB_UDFREV(X) )
-
-#define UDF_SB_PARTMAPS(X) ( UDF_SB(X)->s_partmaps )
-#define UDF_SB_PARTTYPE(X,Y) ( UDF_SB_PARTMAPS(X)[(Y)].s_partition_type )
-#define UDF_SB_PARTROOT(X,Y) ( UDF_SB_PARTMAPS(X)[(Y)].s_partition_root )
-#define UDF_SB_PARTLEN(X,Y) ( UDF_SB_PARTMAPS(X)[(Y)].s_partition_len )
-#define UDF_SB_PARTVSN(X,Y) ( UDF_SB_PARTMAPS(X)[(Y)].s_volumeseqnum )
-#define UDF_SB_PARTNUM(X,Y) ( UDF_SB_PARTMAPS(X)[(Y)].s_partition_num )
-#define UDF_SB_TYPESPAR(X,Y) ( UDF_SB_PARTMAPS(X)[(Y)].s_type_specific.s_sparing )
-#define UDF_SB_TYPEVIRT(X,Y) ( UDF_SB_PARTMAPS(X)[(Y)].s_type_specific.s_virtual )
-#define UDF_SB_PARTFUNC(X,Y) ( UDF_SB_PARTMAPS(X)[(Y)].s_partition_func )
-#define UDF_SB_PARTFLAGS(X,Y) ( UDF_SB_PARTMAPS(X)[(Y)].s_partition_flags )
-#define UDF_SB_BITMAP(X,Y,Z,I) ( UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap->s_block_bitmap[I] )
-#define UDF_SB_BITMAP_NR_GROUPS(X,Y,Z) ( UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap->s_nr_groups )
-
-#define UDF_SB_VOLIDENT(X) ( UDF_SB(X)->s_volident )
-#define UDF_SB_NUMPARTS(X) ( UDF_SB(X)->s_partitions )
-#define UDF_SB_PARTITION(X) ( UDF_SB(X)->s_partition )
-#define UDF_SB_SESSION(X) ( UDF_SB(X)->s_session )
-#define UDF_SB_ANCHOR(X) ( UDF_SB(X)->s_anchor )
-#define UDF_SB_LASTBLOCK(X) ( UDF_SB(X)->s_lastblock )
-#define UDF_SB_LVIDBH(X) ( UDF_SB(X)->s_lvidbh )
-#define UDF_SB_LVID(X) ( (struct logicalVolIntegrityDesc *)UDF_SB_LVIDBH(X)->b_data )
-#define UDF_SB_LVIDIU(X) ( (struct logicalVolIntegrityDescImpUse *)&(UDF_SB_LVID(X)->impUse[le32_to_cpu(UDF_SB_LVID(X)->numOfPartitions) * 2 * sizeof(uint32_t)/sizeof(uint8_t)]) )
-
-#define UDF_SB_UMASK(X) ( UDF_SB(X)->s_umask )
-#define UDF_SB_GID(X) ( UDF_SB(X)->s_gid )
-#define UDF_SB_UID(X) ( UDF_SB(X)->s_uid )
-#define UDF_SB_RECORDTIME(X) ( UDF_SB(X)->s_recordtime )
-#define UDF_SB_SERIALNUM(X) ( UDF_SB(X)->s_serialnum )
-#define UDF_SB_UDFREV(X) ( UDF_SB(X)->s_udfrev )
-#define UDF_SB_FLAGS(X) ( UDF_SB(X)->s_flags )
-#define UDF_SB_VAT(X) ( UDF_SB(X)->s_vat )
-
#endif /* __LINUX_UDF_SB_H */
#define UDF_PATH_LEN 1023
#define udf_file_entry_alloc_offset(inode)\
- (UDF_I_USE(inode) ?\
+ (UDF_I(inode)->i_use ?\
sizeof(struct unallocSpaceEntry) :\
- ((UDF_I_EFE(inode) ?\
+ ((UDF_I(inode)->i_efe ?\
sizeof(struct extendedFileEntry) :\
- sizeof(struct fileEntry)) + UDF_I_LENEATTR(inode)))
+ sizeof(struct fileEntry)) + UDF_I(inode)->i_lenEAttr))
#define udf_ext0_offset(inode)\
- (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB ?\
+ (UDF_I(inode)->i_alloc_type == ICBTAG_FLAG_AD_IN_ICB ?\
udf_file_entry_alloc_offset(inode) : 0)
#define udf_get_lb_pblock(sb,loc,offset) udf_get_pblock((sb), (loc).logicalBlockNum, (loc).partitionReferenceNum, (offset))
+/* computes tag checksum */
+u8 udf_tag_checksum(const tag *t);
+
struct dentry;
struct inode;
struct task_struct;
sector_t *);
extern struct fileIdentDesc *udf_get_fileident(void *buffer, int bufsize,
int *offset);
-extern long_ad *udf_get_filelongad(uint8_t *, int, int *, int);
-extern short_ad *udf_get_fileshortad(uint8_t *, int, int *, int);
+extern long_ad *udf_get_filelongad(uint8_t *, int, uint32_t *, int);
+extern short_ad *udf_get_fileshortad(uint8_t *, int, uint32_t *, int);
/* crc.c */
extern uint16_t udf_crc(uint8_t *, uint32_t, uint16_t);
Boston, MA 02111-1307, USA. */
/*
- * dgb 10/02/98: ripped this from glibc source to help convert timestamps to unix time
- * 10/04/98: added new table-based lookup after seeing how ugly the gnu code is
+ * dgb 10/02/98: ripped this from glibc source to help convert timestamps
+ * to unix time
+ * 10/04/98: added new table-based lookup after seeing how ugly
+ * the gnu code is
* blf 09/27/99: ripped out all the old code and inserted new table from
* John Brockmeyer (without leap second corrections)
* rewrote udf_stamp_to_time and fixed timezone accounting in
#define MAX_YEAR_SECONDS 69
#define SPD 0x15180 /*3600*24 */
-#define SPY(y,l,s) (SPD * (365*y+l)+s)
-
-static time_t year_seconds[MAX_YEAR_SECONDS]= {
-/*1970*/ SPY( 0, 0,0), SPY( 1, 0,0), SPY( 2, 0,0), SPY( 3, 1,0),
-/*1974*/ SPY( 4, 1,0), SPY( 5, 1,0), SPY( 6, 1,0), SPY( 7, 2,0),
-/*1978*/ SPY( 8, 2,0), SPY( 9, 2,0), SPY(10, 2,0), SPY(11, 3,0),
-/*1982*/ SPY(12, 3,0), SPY(13, 3,0), SPY(14, 3,0), SPY(15, 4,0),
-/*1986*/ SPY(16, 4,0), SPY(17, 4,0), SPY(18, 4,0), SPY(19, 5,0),
-/*1990*/ SPY(20, 5,0), SPY(21, 5,0), SPY(22, 5,0), SPY(23, 6,0),
-/*1994*/ SPY(24, 6,0), SPY(25, 6,0), SPY(26, 6,0), SPY(27, 7,0),
-/*1998*/ SPY(28, 7,0), SPY(29, 7,0), SPY(30, 7,0), SPY(31, 8,0),
-/*2002*/ SPY(32, 8,0), SPY(33, 8,0), SPY(34, 8,0), SPY(35, 9,0),
-/*2006*/ SPY(36, 9,0), SPY(37, 9,0), SPY(38, 9,0), SPY(39,10,0),
-/*2010*/ SPY(40,10,0), SPY(41,10,0), SPY(42,10,0), SPY(43,11,0),
-/*2014*/ SPY(44,11,0), SPY(45,11,0), SPY(46,11,0), SPY(47,12,0),
-/*2018*/ SPY(48,12,0), SPY(49,12,0), SPY(50,12,0), SPY(51,13,0),
-/*2022*/ SPY(52,13,0), SPY(53,13,0), SPY(54,13,0), SPY(55,14,0),
-/*2026*/ SPY(56,14,0), SPY(57,14,0), SPY(58,14,0), SPY(59,15,0),
-/*2030*/ SPY(60,15,0), SPY(61,15,0), SPY(62,15,0), SPY(63,16,0),
-/*2034*/ SPY(64,16,0), SPY(65,16,0), SPY(66,16,0), SPY(67,17,0),
-/*2038*/ SPY(68,17,0)
+#define SPY(y, l, s) (SPD * (365 * y + l) + s)
+
+static time_t year_seconds[MAX_YEAR_SECONDS] = {
+/*1970*/ SPY(0, 0, 0), SPY(1, 0, 0), SPY(2, 0, 0), SPY(3, 1, 0),
+/*1974*/ SPY(4, 1, 0), SPY(5, 1, 0), SPY(6, 1, 0), SPY(7, 2, 0),
+/*1978*/ SPY(8, 2, 0), SPY(9, 2, 0), SPY(10, 2, 0), SPY(11, 3, 0),
+/*1982*/ SPY(12, 3, 0), SPY(13, 3, 0), SPY(14, 3, 0), SPY(15, 4, 0),
+/*1986*/ SPY(16, 4, 0), SPY(17, 4, 0), SPY(18, 4, 0), SPY(19, 5, 0),
+/*1990*/ SPY(20, 5, 0), SPY(21, 5, 0), SPY(22, 5, 0), SPY(23, 6, 0),
+/*1994*/ SPY(24, 6, 0), SPY(25, 6, 0), SPY(26, 6, 0), SPY(27, 7, 0),
+/*1998*/ SPY(28, 7, 0), SPY(29, 7, 0), SPY(30, 7, 0), SPY(31, 8, 0),
+/*2002*/ SPY(32, 8, 0), SPY(33, 8, 0), SPY(34, 8, 0), SPY(35, 9, 0),
+/*2006*/ SPY(36, 9, 0), SPY(37, 9, 0), SPY(38, 9, 0), SPY(39, 10, 0),
+/*2010*/ SPY(40, 10, 0), SPY(41, 10, 0), SPY(42, 10, 0), SPY(43, 11, 0),
+/*2014*/ SPY(44, 11, 0), SPY(45, 11, 0), SPY(46, 11, 0), SPY(47, 12, 0),
+/*2018*/ SPY(48, 12, 0), SPY(49, 12, 0), SPY(50, 12, 0), SPY(51, 13, 0),
+/*2022*/ SPY(52, 13, 0), SPY(53, 13, 0), SPY(54, 13, 0), SPY(55, 14, 0),
+/*2026*/ SPY(56, 14, 0), SPY(57, 14, 0), SPY(58, 14, 0), SPY(59, 15, 0),
+/*2030*/ SPY(60, 15, 0), SPY(61, 15, 0), SPY(62, 15, 0), SPY(63, 16, 0),
+/*2034*/ SPY(64, 16, 0), SPY(65, 16, 0), SPY(66, 16, 0), SPY(67, 17, 0),
+/*2038*/ SPY(68, 17, 0)
};
extern struct timezone sys_tz;
return dest;
}
-kernel_timestamp *udf_time_to_stamp(kernel_timestamp * dest, struct timespec ts)
+kernel_timestamp *udf_time_to_stamp(kernel_timestamp *dest, struct timespec ts)
{
long int days, rem, y;
const unsigned short int *ip;
dest->second = rem % 60;
y = 1970;
-#define DIV(a,b) ((a) / (b) - ((a) % (b) < 0))
+#define DIV(a, b) ((a) / (b) - ((a) % (b) < 0))
#define LEAPS_THRU_END_OF(y) (DIV (y, 4) - DIV (y, 100) + DIV (y, 400))
while (days < 0 || days >= (__isleap(y) ? 366 : 365)) {
/* Adjust DAYS and Y to match the guessed year. */
days -= ((yg - y) * 365
- + LEAPS_THRU_END_OF (yg - 1)
- - LEAPS_THRU_END_OF (y - 1));
+ + LEAPS_THRU_END_OF(yg - 1)
+ - LEAPS_THRU_END_OF(y - 1));
y = yg;
}
dest->year = y;
dest->day = days + 1;
dest->centiseconds = ts.tv_nsec / 10000000;
- dest->hundredsOfMicroseconds = (ts.tv_nsec / 1000 - dest->centiseconds * 10000) / 100;
+ dest->hundredsOfMicroseconds = (ts.tv_nsec / 1000 -
+ dest->centiseconds * 10000) / 100;
dest->microseconds = (ts.tv_nsec / 1000 - dest->centiseconds * 10000 -
dest->hundredsOfMicroseconds * 100);
return dest;
if (c < 0x80U) {
utf_o->u_name[utf_o->u_len++] = (uint8_t)c;
} else if (c < 0x800U) {
- utf_o->u_name[utf_o->u_len++] = (uint8_t)(0xc0 | (c >> 6));
- utf_o->u_name[utf_o->u_len++] = (uint8_t)(0x80 | (c & 0x3f));
+ utf_o->u_name[utf_o->u_len++] =
+ (uint8_t)(0xc0 | (c >> 6));
+ utf_o->u_name[utf_o->u_len++] =
+ (uint8_t)(0x80 | (c & 0x3f));
} else {
- utf_o->u_name[utf_o->u_len++] = (uint8_t)(0xe0 | (c >> 12));
- utf_o->u_name[utf_o->u_len++] = (uint8_t)(0x80 | ((c >> 6) & 0x3f));
- utf_o->u_name[utf_o->u_len++] = (uint8_t)(0x80 | (c & 0x3f));
+ utf_o->u_name[utf_o->u_len++] =
+ (uint8_t)(0xe0 | (c >> 12));
+ utf_o->u_name[utf_o->u_len++] =
+ (uint8_t)(0x80 |
+ ((c >> 6) & 0x3f));
+ utf_o->u_name[utf_o->u_len++] =
+ (uint8_t)(0x80 | (c & 0x3f));
}
}
utf_o->u_cmpID = 8;
goto error_out;
}
- if (max_val == 0xffffU) {
+ if (max_val == 0xffffU)
ocu[++u_len] = (uint8_t)(utf_char >> 8);
- }
ocu[++u_len] = (uint8_t)(utf_char & 0xffU);
}
struct ustr filename, unifilename;
int len;
- if (udf_build_ustr_exact(&unifilename, sname, flen)) {
+ if (udf_build_ustr_exact(&unifilename, sname, flen))
return 0;
- }
if (UDF_QUERY_FLAG(sb, UDF_FLAG_UTF8)) {
if (!udf_CS0toUTF8(&filename, &unifilename)) {
- udf_debug("Failed in udf_get_filename: sname = %s\n", sname);
+ udf_debug("Failed in udf_get_filename: sname = %s\n",
+ sname);
return 0;
}
} else if (UDF_QUERY_FLAG(sb, UDF_FLAG_NLS_MAP)) {
- if (!udf_CS0toNLS(UDF_SB(sb)->s_nls_map, &filename, &unifilename)) {
- udf_debug("Failed in udf_get_filename: sname = %s\n", sname);
+ if (!udf_CS0toNLS(UDF_SB(sb)->s_nls_map, &filename,
+ &unifilename)) {
+ udf_debug("Failed in udf_get_filename: sname = %s\n",
+ sname);
return 0;
}
- } else {
+ } else
return 0;
- }
len = udf_translate_to_linux(dname, filename.u_name, filename.u_len,
unifilename.u_name, unifilename.u_len);
- if (len) {
+ if (len)
return len;
- }
return 0;
}
struct ustr unifilename;
int namelen;
- if (!(udf_char_to_ustr(&unifilename, sname, flen))) {
+ if (!udf_char_to_ustr(&unifilename, sname, flen))
return 0;
- }
if (UDF_QUERY_FLAG(sb, UDF_FLAG_UTF8)) {
namelen = udf_UTF8toCS0(dname, &unifilename, UDF_NAME_LEN);
- if (!namelen) {
+ if (!namelen)
return 0;
- }
} else if (UDF_QUERY_FLAG(sb, UDF_FLAG_NLS_MAP)) {
- namelen = udf_NLStoCS0(UDF_SB(sb)->s_nls_map, dname, &unifilename, UDF_NAME_LEN);
- if (!namelen) {
+ namelen = udf_NLStoCS0(UDF_SB(sb)->s_nls_map, dname,
+ &unifilename, UDF_NAME_LEN);
+ if (!namelen)
return 0;
- }
- } else {
+ } else
return 0;
- }
return namelen;
}
#define CRC_MARK '#'
#define EXT_SIZE 5
-static int udf_translate_to_linux(uint8_t *newName, uint8_t *udfName, int udfLen,
- uint8_t *fidName, int fidNameLen)
+static int udf_translate_to_linux(uint8_t *newName, uint8_t *udfName,
+ int udfLen, uint8_t *fidName,
+ int fidNameLen)
{
int index, newIndex = 0, needsCRC = 0;
int extIndex = 0, newExtIndex = 0, hasExt = 0;
if (curr == '/' || curr == 0) {
needsCRC = 1;
curr = ILLEGAL_CHAR_MARK;
- while (index + 1 < udfLen && (udfName[index + 1] == '/' ||
- udfName[index + 1] == 0))
+ while (index + 1 < udfLen &&
+ (udfName[index + 1] == '/' ||
+ udfName[index + 1] == 0))
index++;
- } if (curr == EXT_MARK && (udfLen - index - 1) <= EXT_SIZE) {
- if (udfLen == index + 1) {
+ }
+ if (curr == EXT_MARK &&
+ (udfLen - index - 1) <= EXT_SIZE) {
+ if (udfLen == index + 1)
hasExt = 0;
- } else {
+ else {
hasExt = 1;
extIndex = index;
newExtIndex = newIndex;
if (hasExt) {
int maxFilenameLen;
- for(index = 0; index < EXT_SIZE && extIndex + index + 1 < udfLen; index++) {
+ for (index = 0;
+ index < EXT_SIZE && extIndex + index + 1 < udfLen;
+ index++) {
curr = udfName[extIndex + index + 1];
if (curr == '/' || curr == 0) {
needsCRC = 1;
curr = ILLEGAL_CHAR_MARK;
- while(extIndex + index + 2 < udfLen &&
- (index + 1 < EXT_SIZE
- && (udfName[extIndex + index + 2] == '/' ||
- udfName[extIndex + index + 2] == 0)))
+ while (extIndex + index + 2 < udfLen &&
+ (index + 1 < EXT_SIZE &&
+ (udfName[extIndex + index + 2] == '/' ||
+ udfName[extIndex + index + 2] == 0)))
index++;
}
ext[localExtIndex++] = curr;
newIndex = maxFilenameLen;
else
newIndex = newExtIndex;
- } else if (newIndex > 250) {
+ } else if (newIndex > 250)
newIndex = 250;
- }
newName[newIndex++] = CRC_MARK;
valueCRC = udf_crc(fidName, fidNameLen, 0);
newName[newIndex++] = hexChar[(valueCRC & 0xf000) >> 12];
*/
#include <linux/fs.h>
-#include <linux/ufs_fs.h>
#include <linux/stat.h>
#include <linux/time.h>
#include <linux/string.h>
#include <linux/bitops.h>
#include <asm/byteorder.h>
+#include "ufs_fs.h"
#include "ufs.h"
#include "swab.h"
#include "util.h"
*/
#include <linux/fs.h>
-#include <linux/ufs_fs.h>
#include <linux/time.h>
#include <linux/stat.h>
#include <linux/string.h>
#include <asm/byteorder.h>
+#include "ufs_fs.h"
#include "ufs.h"
#include "swab.h"
#include "util.h"
#include <linux/time.h>
#include <linux/fs.h>
-#include <linux/ufs_fs.h>
#include <linux/swap.h>
+#include "ufs_fs.h"
#include "ufs.h"
#include "swab.h"
#include "util.h"
*/
#include <linux/fs.h>
-#include <linux/ufs_fs.h>
#include <linux/buffer_head.h> /* for sync_mapping_buffers() */
+#include "ufs_fs.h"
#include "ufs.h"
*/
#include <linux/fs.h>
-#include <linux/ufs_fs.h>
#include <linux/time.h>
#include <linux/stat.h>
#include <linux/string.h>
#include <linux/bitops.h>
#include <asm/byteorder.h>
+#include "ufs_fs.h"
#include "ufs.h"
#include "swab.h"
#include "util.h"
#include <linux/errno.h>
#include <linux/fs.h>
-#include <linux/ufs_fs.h>
#include <linux/time.h>
#include <linux/stat.h>
#include <linux/string.h>
#include <linux/smp_lock.h>
#include <linux/buffer_head.h>
+#include "ufs_fs.h"
#include "ufs.h"
#include "swab.h"
#include "util.h"
#include <linux/time.h>
#include <linux/fs.h>
-#include <linux/ufs_fs.h>
#include <linux/smp_lock.h>
+
+#include "ufs_fs.h"
#include "ufs.h"
#include "util.h"
#include <linux/errno.h>
#include <linux/fs.h>
-#include <linux/ufs_fs.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/stat.h>
#include <linux/mount.h>
#include <linux/seq_file.h>
+#include "ufs_fs.h"
#include "ufs.h"
#include "swab.h"
#include "util.h"
printk(KERN_INFO" cs_nffree(Num of free frags): %llu\n",
(unsigned long long)
fs64_to_cpu(sb, usb3->fs_un1.fs_u2.cs_nffree));
+ printk(KERN_INFO" fs_maxsymlinklen: %u\n",
+ fs32_to_cpu(sb, usb3->fs_un2.fs_44.fs_maxsymlinklen));
} else {
printk(" sblkno: %u\n", fs32_to_cpu(sb, usb1->fs_sblkno));
printk(" cblkno: %u\n", fs32_to_cpu(sb, usb1->fs_cblkno));
uspi->s_bpf = uspi->s_fsize << 3;
uspi->s_bpfshift = uspi->s_fshift + 3;
uspi->s_bpfmask = uspi->s_bpf - 1;
- if ((sbi->s_mount_opt & UFS_MOUNT_UFSTYPE) ==
- UFS_MOUNT_UFSTYPE_44BSD)
+ if ((sbi->s_mount_opt & UFS_MOUNT_UFSTYPE) == UFS_MOUNT_UFSTYPE_44BSD ||
+ (sbi->s_mount_opt & UFS_MOUNT_UFSTYPE) == UFS_MOUNT_UFSTYPE_UFS2)
uspi->s_maxsymlinklen =
fs32_to_cpu(sb, usb3->fs_un2.fs_44.fs_maxsymlinklen);
#include <linux/fs.h>
#include <linux/namei.h>
-#include <linux/ufs_fs.h>
+
+#include "ufs_fs.h"
#include "ufs.h"
#include <linux/errno.h>
#include <linux/fs.h>
-#include <linux/ufs_fs.h>
#include <linux/fcntl.h>
#include <linux/time.h>
#include <linux/stat.h>
#include <linux/blkdev.h>
#include <linux/sched.h>
+#include "ufs_fs.h"
#include "ufs.h"
#include "swab.h"
#include "util.h"
#include <linux/stat.h>
#include <linux/fs.h>
-#ifndef __KERNEL__
-typedef __u64 __fs64;
-typedef __u32 __fs32;
-typedef __u16 __fs16;
-#else
#include <asm/div64.h>
typedef __u64 __bitwise __fs64;
typedef __u32 __bitwise __fs32;
typedef __u16 __bitwise __fs16;
-#endif
#define UFS_BBLOCK 0
#define UFS_BBSIZE 8192
*/
#define UFS_MINFREE 5
#define UFS_DEFAULTOPT UFS_OPTTIME
-
+
/*
* Turn file system block numbers into disk block addresses.
* This maps file system blocks to device size blocks.
__u32 c_clustersumoff;/* (u_int32) counts of avail clusters */
__u32 c_clusteroff; /* (u_int8) free cluster map */
__u32 c_nclusterblks; /* number of clusters this cg */
-};
+};
struct ufs_sb_private_info {
#include <linux/string.h>
#include <linux/slab.h>
-#include <linux/ufs_fs.h>
#include <linux/buffer_head.h>
+#include "ufs_fs.h"
#include "ufs.h"
#include "swab.h"
#include "util.h"
--- /dev/null
+/* a.out coredump register dumper
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_A_OUT_CORE_H
+#define _ASM_A_OUT_CORE_H
+
+#ifdef __KERNEL__
+
+#include <linux/user.h>
+
+/*
+ * Fill in the user structure for an ECOFF core dump.
+ */
+static inline void aout_dump_thread(struct pt_regs *pt, struct user *dump)
+{
+ /* switch stack follows right below pt_regs: */
+ struct switch_stack * sw = ((struct switch_stack *) pt) - 1;
+
+ dump->magic = CMAGIC;
+ dump->start_code = current->mm->start_code;
+ dump->start_data = current->mm->start_data;
+ dump->start_stack = rdusp() & ~(PAGE_SIZE - 1);
+ dump->u_tsize = ((current->mm->end_code - dump->start_code)
+ >> PAGE_SHIFT);
+ dump->u_dsize = ((current->mm->brk + PAGE_SIZE-1 - dump->start_data)
+ >> PAGE_SHIFT);
+ dump->u_ssize = (current->mm->start_stack - dump->start_stack
+ + PAGE_SIZE-1) >> PAGE_SHIFT;
+
+ /*
+ * We store the registers in an order/format that is
+ * compatible with DEC Unix/OSF/1 as this makes life easier
+ * for gdb.
+ */
+ dump->regs[EF_V0] = pt->r0;
+ dump->regs[EF_T0] = pt->r1;
+ dump->regs[EF_T1] = pt->r2;
+ dump->regs[EF_T2] = pt->r3;
+ dump->regs[EF_T3] = pt->r4;
+ dump->regs[EF_T4] = pt->r5;
+ dump->regs[EF_T5] = pt->r6;
+ dump->regs[EF_T6] = pt->r7;
+ dump->regs[EF_T7] = pt->r8;
+ dump->regs[EF_S0] = sw->r9;
+ dump->regs[EF_S1] = sw->r10;
+ dump->regs[EF_S2] = sw->r11;
+ dump->regs[EF_S3] = sw->r12;
+ dump->regs[EF_S4] = sw->r13;
+ dump->regs[EF_S5] = sw->r14;
+ dump->regs[EF_S6] = sw->r15;
+ dump->regs[EF_A3] = pt->r19;
+ dump->regs[EF_A4] = pt->r20;
+ dump->regs[EF_A5] = pt->r21;
+ dump->regs[EF_T8] = pt->r22;
+ dump->regs[EF_T9] = pt->r23;
+ dump->regs[EF_T10] = pt->r24;
+ dump->regs[EF_T11] = pt->r25;
+ dump->regs[EF_RA] = pt->r26;
+ dump->regs[EF_T12] = pt->r27;
+ dump->regs[EF_AT] = pt->r28;
+ dump->regs[EF_SP] = rdusp();
+ dump->regs[EF_PS] = pt->ps;
+ dump->regs[EF_PC] = pt->pc;
+ dump->regs[EF_GP] = pt->gp;
+ dump->regs[EF_A0] = pt->r16;
+ dump->regs[EF_A1] = pt->r17;
+ dump->regs[EF_A2] = pt->r18;
+ memcpy((char *)dump->regs + EF_SIZE, sw->fp, 32 * 8);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_A_OUT_CORE_H */
set_personality (((BFPM->sh_bang || EX.ah.entry < 0x100000000L \
? ADDR_LIMIT_32BIT : 0) | PER_OSF4))
-#define STACK_TOP \
- (current->personality & ADDR_LIMIT_32BIT ? 0x80000000 : 0x00120000000UL)
-
-#define STACK_TOP_MAX 0x00120000000UL
-
-#endif
-
+#endif /* __KERNEL__ */
#endif /* __A_OUT_GNU_H__ */
#endif /* STRICT_MM_TYPECHECKS */
+typedef struct page *pgtable_t;
+
#ifdef USE_48_BIT_KSEG
#define PAGE_OFFSET 0xffff800000000000UL
#else
hardware ignores reprogramming. We also need userland buy-in to the
change in HZ, since this is visible in the wait4 resources etc. */
-
-#ifndef HZ
-# ifndef CONFIG_ALPHA_RAWHIDE
-# define HZ 1024
-# else
-# define HZ 1200
-# endif
-#endif
-
+#define HZ CONFIG_HZ
#define USER_HZ HZ
#define EXEC_PAGESIZE 8192
*/
static inline void
-pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte)
+pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t pte)
{
pmd_set(pmd, (pte_t *)(page_to_pa(pte) + PAGE_OFFSET));
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
static inline void
pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte)
free_page((unsigned long)pte);
}
-static inline struct page *
-pte_alloc_one(struct mm_struct *mm, unsigned long addr)
+static inline pgtable_t
+pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
- pte_t *pte = pte_alloc_one_kernel(mm, addr);
- if (pte)
- return virt_to_page(pte);
- return NULL;
+ pte_t *pte = pte_alloc_one_kernel(mm, address);
+ struct page *page;
+
+ if (!pte)
+ return NULL;
+ page = virt_to_page(pte);
+ pgtable_page_ctor(page);
+ return page;
}
static inline void
-pte_free(struct mm_struct *mm, struct page *page)
+pte_free(struct mm_struct *mm, pgtable_t page)
{
+ pgtable_page_dtor(page);
__free_page(page);
}
*/
#define TASK_SIZE (0x40000000000UL)
+#define STACK_TOP \
+ (current->personality & ADDR_LIMIT_32BIT ? 0x80000000 : 0x00120000000UL)
+
+#define STACK_TOP_MAX 0x00120000000UL
+
/* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
--- /dev/null
+/* a.out coredump register dumper
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_A_OUT_CORE_H
+#define _ASM_A_OUT_CORE_H
+
+#ifdef __KERNEL__
+
+#include <linux/user.h>
+#include <linux/elfcore.h>
+
+/*
+ * fill in the user structure for an a.out core dump
+ */
+static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
+{
+ struct task_struct *tsk = current;
+
+ dump->magic = CMAGIC;
+ dump->start_code = tsk->mm->start_code;
+ dump->start_stack = regs->ARM_sp & ~(PAGE_SIZE - 1);
+
+ dump->u_tsize = (tsk->mm->end_code - tsk->mm->start_code) >> PAGE_SHIFT;
+ dump->u_dsize = (tsk->mm->brk - tsk->mm->start_data + PAGE_SIZE - 1) >> PAGE_SHIFT;
+ dump->u_ssize = 0;
+
+ dump->u_debugreg[0] = tsk->thread.debug.bp[0].address;
+ dump->u_debugreg[1] = tsk->thread.debug.bp[1].address;
+ dump->u_debugreg[2] = tsk->thread.debug.bp[0].insn.arm;
+ dump->u_debugreg[3] = tsk->thread.debug.bp[1].insn.arm;
+ dump->u_debugreg[4] = tsk->thread.debug.nsaved;
+
+ if (dump->start_stack < 0x04000000)
+ dump->u_ssize = (0x04000000 - dump->start_stack) >> PAGE_SHIFT;
+
+ dump->regs = *regs;
+ dump->u_fpvalid = dump_fpu (regs, &dump->u_fp);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_A_OUT_CORE_H */
#define M_ARM 103
-#ifdef __KERNEL__
-#define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \
- TASK_SIZE : TASK_SIZE_26)
-#define STACK_TOP_MAX TASK_SIZE
-#endif
-
#ifndef LIBRARY_START_TEXT
#define LIBRARY_START_TEXT (0x00c00000)
#endif
* published by the Free Software Foundation.
*/
+#include <asm/arch/orion.h>
+
.macro addruart,rx
- mov \rx, #0xf1000000
- orr \rx, \rx, #0x00012000
+ mrc p15, 0, \rx, c1, c0
+ tst \rx, #1 @ MMU enabled?
+ ldreq \rx, =ORION_REGS_PHYS_BASE
+ ldrne \rx, =ORION_REGS_VIRT_BASE
+ orr \rx, \rx, #0x00012000
.endm
#define UART_SHIFT 2
*
* Low-level IRQ helper macros for Orion platforms
*
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
- *
*/
#ifndef __ASM_ARCH_HARDWARE_H__
#include "orion.h"
-#define PCI_MEMORY_VADDR ORION_PCI_SYS_MEM_BASE
-#define PCI_IO_VADDR ORION_PCI_SYS_IO_BASE
+#define pcibios_assign_all_busses() 1
-#define pcibios_assign_all_busses() 1
+#define PCIBIOS_MIN_IO 0x00001000
+#define PCIBIOS_MIN_MEM 0x01000000
+#define PCIMEM_BASE ORION_PCIE_MEM_PHYS_BASE
-#define PCIBIOS_MIN_IO 0x1000
-#define PCIBIOS_MIN_MEM 0x01000000
-#define PCIMEM_BASE PCI_MEMORY_VADDR /* mem base for VGA */
-#endif /* _ASM_ARCH_HARDWARE_H */
+#endif
#ifndef __ASM_ARCH_ORION_H__
#define __ASM_ARCH_ORION_H__
-/*******************************************************************************
+/*****************************************************************************
* Orion Address Map
- * Use the same mapping (1:1 virtual:physical) of internal registers and
- * PCI system (PCI+PCIE) for all machines.
- * Each machine defines the rest of its mapping (e.g. device bus flashes)
- ******************************************************************************/
-#define ORION_REGS_BASE 0xf1000000
+ *
+ * virt phys size
+ * fdd00000 f1000000 1M on-chip peripheral registers
+ * fde00000 f2000000 1M PCIe I/O space
+ * fdf00000 f2100000 1M PCI I/O space
+ * fe000000 f0000000 16M PCIe WA space (Orion-NAS only)
+ ****************************************************************************/
+#define ORION_REGS_PHYS_BASE 0xf1000000
+#define ORION_REGS_VIRT_BASE 0xfdd00000
#define ORION_REGS_SIZE SZ_1M
-#define ORION_PCI_SYS_MEM_BASE 0xe0000000
-#define ORION_PCIE_MEM_BASE ORION_PCI_SYS_MEM_BASE
-#define ORION_PCIE_MEM_SIZE SZ_128M
-#define ORION_PCI_MEM_BASE (ORION_PCIE_MEM_BASE + ORION_PCIE_MEM_SIZE)
-#define ORION_PCI_MEM_SIZE SZ_128M
-
-#define ORION_PCI_SYS_IO_BASE 0xf2000000
-#define ORION_PCIE_IO_BASE ORION_PCI_SYS_IO_BASE
+#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
+#define ORION_PCIE_IO_VIRT_BASE 0xfde00000
+#define ORION_PCIE_IO_BUS_BASE 0x00000000
#define ORION_PCIE_IO_SIZE SZ_1M
-#define ORION_PCIE_IO_REMAP (ORION_PCIE_IO_BASE - ORION_PCI_SYS_IO_BASE)
-#define ORION_PCI_IO_BASE (ORION_PCIE_IO_BASE + ORION_PCIE_IO_SIZE)
+
+#define ORION_PCI_IO_PHYS_BASE 0xf2100000
+#define ORION_PCI_IO_VIRT_BASE 0xfdf00000
+#define ORION_PCI_IO_BUS_BASE 0x00100000
#define ORION_PCI_IO_SIZE SZ_1M
-#define ORION_PCI_IO_REMAP (ORION_PCI_IO_BASE - ORION_PCI_SYS_IO_BASE)
+
/* Relevant only for Orion-NAS */
-#define ORION_PCIE_WA_BASE 0xf0000000
+#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
+#define ORION_PCIE_WA_VIRT_BASE 0xfe000000
#define ORION_PCIE_WA_SIZE SZ_16M
+#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000
+#define ORION_PCIE_MEM_SIZE SZ_128M
+
+#define ORION_PCI_MEM_PHYS_BASE 0xe8000000
+#define ORION_PCI_MEM_SIZE SZ_128M
+
/*******************************************************************************
* Supported Devices & Revisions
******************************************************************************/
/*******************************************************************************
* Orion Registers Map
******************************************************************************/
-#define ORION_DDR_REG_BASE (ORION_REGS_BASE | 0x00000)
-#define ORION_DEV_BUS_REG_BASE (ORION_REGS_BASE | 0x10000)
-#define ORION_BRIDGE_REG_BASE (ORION_REGS_BASE | 0x20000)
-#define ORION_PCI_REG_BASE (ORION_REGS_BASE | 0x30000)
-#define ORION_PCIE_REG_BASE (ORION_REGS_BASE | 0x40000)
-#define ORION_USB0_REG_BASE (ORION_REGS_BASE | 0x50000)
-#define ORION_ETH_REG_BASE (ORION_REGS_BASE | 0x70000)
-#define ORION_SATA_REG_BASE (ORION_REGS_BASE | 0x80000)
-#define ORION_USB1_REG_BASE (ORION_REGS_BASE | 0xa0000)
-
-#define ORION_DDR_REG(x) (ORION_DDR_REG_BASE | (x))
-#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_REG_BASE | (x))
-#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_REG_BASE | (x))
-#define ORION_PCI_REG(x) (ORION_PCI_REG_BASE | (x))
-#define ORION_PCIE_REG(x) (ORION_PCIE_REG_BASE | (x))
-#define ORION_USB0_REG(x) (ORION_USB0_REG_BASE | (x))
-#define ORION_USB1_REG(x) (ORION_USB1_REG_BASE | (x))
-#define ORION_ETH_REG(x) (ORION_ETH_REG_BASE | (x))
-#define ORION_SATA_REG(x) (ORION_SATA_REG_BASE | (x))
+#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000)
+#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x))
+
+#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000)
+#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000)
+#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x))
+#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000)
+#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000)
+#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000)
+#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100)
+#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100)
+
+#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
+#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
+
+#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
+#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
+
+#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000)
+#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x))
+
+#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000)
+#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000)
+#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x))
+
+#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000)
+#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000)
+#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x))
+
+#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000)
+#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000)
+#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x))
+
+#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000)
+#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000)
+#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x))
/*******************************************************************************
* Device Bus Registers
#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
-#define I2C_BASE ORION_DEV_BUS_REG(0x1000)
-#define UART0_BASE ORION_DEV_BUS_REG(0x2000)
-#define UART1_BASE ORION_DEV_BUS_REG(0x2100)
#define GPIO_MAX 32
/***************************************************************************
#include <asm/arch/orion.h>
-#define MV_UART_LSR ((volatile unsigned char *)(UART0_BASE + 0x14))
-#define MV_UART_THR ((volatile unsigned char *)(UART0_BASE + 0x0))
+#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
+#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
#define LSR_THRE 0x20
{
}
-static void orion_early_putstr(const char *ptr)
-{
- char c;
- while ((c = *ptr++) != '\0') {
- if (c == '\n')
- putc('\r');
- putc(c);
- }
-}
-
/*
* nothing to do
*/
* include/asm-arm/arch-orion/vmalloc.h
*/
-#define VMALLOC_END 0xf0000000
+#define VMALLOC_END 0xfd800000
* reattempted until it succeeds.
*/
static inline void
-__mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *))
+__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
{
int __ex_flag, __res;
}
static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *))
+__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
{
int __ex_flag, __res;
* better generated assembly.
*/
static inline void
-__mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *))
+__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
{
int __ex_flag, __res, __orig;
#endif /* STRICT_MM_TYPECHECKS */
+typedef struct page *pgtable_t;
+
#endif /* CONFIG_MMU */
#include <asm/memory.h>
return pte;
}
-static inline struct page *
+static inline pgtable_t
pte_alloc_one(struct mm_struct *mm, unsigned long addr)
{
struct page *pte;
if (pte) {
void *page = page_address(pte);
clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE);
+ pgtable_page_ctor(pte);
}
return pte;
}
}
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
+ pgtable_page_dtor(pte);
__free_page(pte);
}
}
static inline void
-pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
+pmd_populate(struct mm_struct *mm, pmd_t *pmdp, pgtable_t ptep)
{
__pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE);
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
#endif /* CONFIG_MMU */
#endif
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
#undef __FD_SET
#define __FD_SET(fd, fdsetp) \
#include <asm/ptrace.h>
#include <asm/types.h>
+#ifdef __KERNEL__
+#define STACK_TOP ((current->personality == PER_LINUX_32BIT) ? \
+ TASK_SIZE : TASK_SIZE_26)
+#define STACK_TOP_MAX TASK_SIZE
+#endif
+
union debug_insn {
u32 arm;
u16 thumb;
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-#ifdef __KERNEL__
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-
-#endif
-
#endif /* __ASM_AVR32_A_OUT_H */
at32_add_device_ide(unsigned int id, unsigned int extint,
struct ide_platform_data *data);
+/* mask says which PWM channels to mux */
+struct platform_device *at32_add_device_pwm(u32 mask);
+
/* depending on what's hooked up, not all SSC pins will be used */
#define ATMEL_SSC_TK 0x01
#define ATMEL_SSC_TF 0x02
typedef struct { unsigned long pte; } pte_t;
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct page *pgtable_t;
#define pte_val(x) ((x).pte)
#define pgd_val(x) ((x).pgd)
set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
- struct page *pte)
+ pgtable_t pte)
{
set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte)));
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
/*
* Allocate and free page tables
struct page *pte;
pte = alloc_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
-
+ if (!pte)
+ return NULL;
+ pgtable_page_ctor(pte);
return pte;
}
free_page((unsigned long)pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
+ pgtable_page_dtor(pte);
__free_page(pte);
}
-#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
+#define __pte_free_tlb(tlb,pte) \
+do { \
+ pgtable_page_dtor(pte); \
+ tlb_remove_page((tlb), pte); \
+} while (0)
#define check_pgt_cache() do { } while(0)
#endif
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
#if defined(__KERNEL__)
#define TASK_SIZE 0x80000000
+#ifdef __KERNEL__
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
+#endif
+
#ifndef __ASSEMBLY__
static inline void *current_text_addr(void)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-#ifdef __KERNEL__
-
-#define STACK_TOP TASK_SIZE
-
-#endif
-
#endif /* __BFIN_A_OUT_H__ */
extern void evt14_softirq(void);
extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type);
+extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
extern asmlinkage void finish_atomic_sections (struct pt_regs *regs);
extern char fixed_code_start;
extern unsigned long table_start, table_end;
+extern unsigned long bfin_sic_iwr[];
extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
extern struct file_operations dpmc_fops;
extern char _start;
/************************************************************
-*
-* Copyright (C) 2004, Analog Devices. All Rights Reserved
+
+* Copyright (C) 2006-2008, Analog Devices. All Rights Reserved
*
* FILE bfin5xx_spi.h
* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
#define SPI_BAUD_OFF 0x14
#define SPI_SHAW_OFF 0x18
-#define CMD_SPI_OUT_ENABLE 1
-#define CMD_SPI_SET_BAUDRATE 2
-#define CMD_SPI_SET_POLAR 3
-#define CMD_SPI_SET_PHASE 4
-#define CMD_SPI_SET_MASTER 5
-#define CMD_SPI_SET_SENDOPT 6
-#define CMD_SPI_SET_RECVOPT 7
-#define CMD_SPI_SET_ORDER 8
-#define CMD_SPI_SET_LENGTH16 9
-#define CMD_SPI_GET_STAT 11
-#define CMD_SPI_GET_CFG 12
-#define CMD_SPI_SET_CSAVAIL 13
-#define CMD_SPI_SET_CSHIGH 14 /* CS unavail */
-#define CMD_SPI_SET_CSLOW 15 /* CS avail */
-#define CMD_SPI_MISO_ENABLE 16
-#define CMD_SPI_SET_CSENABLE 17
-#define CMD_SPI_SET_CSDISABLE 18
-
-#define CMD_SPI_SET_TRIGGER_MODE 19
-#define CMD_SPI_SET_TRIGGER_SENSE 20
-#define CMD_SPI_SET_TRIGGER_EDGE 21
-#define CMD_SPI_SET_TRIGGER_LEVEL 22
-
-#define CMD_SPI_SET_TIME_SPS 23
-#define CMD_SPI_SET_TIME_SAMPLES 24
-#define CMD_SPI_GET_SYSTEMCLOCK 25
-
-#define CMD_SPI_SET_WRITECONTINUOUS 26
-#define CMD_SPI_SET_SKFS 27
-
-#define CMD_SPI_GET_ALLCONFIG 32 /* For debug */
-
-#define SPI_DEFAULT_BARD 0x0100
-
-#define SPI0_IRQ_NUM IRQ_SPI
-#define SPI_ERR_TRIG -1
#define BIT_CTL_ENABLE 0x4000
#define BIT_CTL_OPENDRAIN 0x2000
#define CFG_SPI_CS6VALUE 6
#define CFG_SPI_CS7VALUE 7
+#define CMD_SPI_SET_BAUDRATE 2
+#define CMD_SPI_GET_SYSTEMCLOCK 25
+#define CMD_SPI_SET_WRITECONTINUOUS 26
+
/* device.platform_data for SSP controller devices */
struct bfin5xx_spi_master {
u16 num_chipselect;
void change_baud(int baud);
void fullon_mode(void);
void active_mode(void);
-void sleep_mode(u32 sic_iwr);
-void deep_sleep(u32 sic_iwr);
-void hibernate_mode(u32 sic_iwr);
-void sleep_deeper(u32 sic_iwr);
+void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
+void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
+void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
+void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
void program_wdog_timer(unsigned long);
void unmask_wdog_wakeup_evt(void);
void clear_wdog_wakeup_evt(void);
#endif
#ifdef CONFIG_PM
+unsigned int bfin_pm_setup(void);
+void bfin_pm_restore(void);
+
+#ifndef CONFIG_BF54x
#define PM_WAKE_RISING 0x1
#define PM_WAKE_FALLING 0x2
#define PM_WAKE_HIGH 0x4
#define PM_WAKE_LOW 0x8
#define PM_WAKE_BOTH_EDGES (PM_WAKE_RISING | PM_WAKE_FALLING)
+#define PM_WAKE_IGNORE 0xF0
int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
void gpio_pm_wakeup_free(unsigned gpio);
-unsigned int gpio_pm_setup(void);
-void gpio_pm_restore(void);
struct gpio_port_s {
unsigned short data;
unsigned short fer;
unsigned short reserved;
};
+#endif /*CONFIG_BF54x*/
#endif /*CONFIG_PM*/
/***********************************************************
#include "defBF544.h"
#endif
+#ifdef CONFIG_BF547
+#include "defBF547.h"
+#endif
+
#ifdef CONFIG_BF548
#include "defBF548.h"
#endif
#ifdef CONFIG_BF542
#include "cdefBF542.h"
#endif
-
#ifdef CONFIG_BF544
#include "cdefBF544.h"
#endif
+#ifdef CONFIG_BF547
+#include "cdefBF547.h"
+#endif
#ifdef CONFIG_BF548
#include "cdefBF548.h"
#endif
--- /dev/null
+/*
+ * File: include/asm-blackfin/mach-bf548/cdefBF547.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF548_H
+#define _CDEF_BF548_H
+
+/* include all Core registers and bit definitions */
+#include "defBF548.h"
+
+/* include core sbfin_read_()ecific register pointer definitions */
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
+
+/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
+#include "cdefBF54x_base.h"
+
+/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
+
+/* Timer Registers */
+
+#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
+#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
+#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
+#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
+#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
+#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
+#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
+#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
+#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
+#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
+#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
+#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
+
+/* Timer Groubfin_read_() of 3 */
+
+#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
+#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
+#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
+#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
+#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
+#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
+
+/* SPORT0 Registers */
+
+#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
+#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
+#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
+#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
+#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
+#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
+#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
+#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
+#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
+#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
+#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
+#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
+#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
+#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
+#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
+#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
+#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
+#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
+#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
+#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
+#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
+#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
+
+/* EPPI0 Registers */
+
+#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
+#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
+#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
+#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
+#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
+#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
+#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
+#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
+#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
+#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
+#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
+#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
+#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
+#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
+#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
+#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
+#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
+#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
+#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
+#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
+#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
+#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
+#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
+#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
+#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
+#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
+#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
+#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
+
+/* UART2 Registers */
+
+#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
+#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
+#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
+#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
+#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
+#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
+#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
+#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
+#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
+#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
+#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
+#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
+#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
+#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
+#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
+#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
+#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
+#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
+#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
+#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
+#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
+#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
+#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
+#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
+#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
+#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
+#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
+#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
+#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
+#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
+#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
+#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
+#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
+#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
+#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
+#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
+#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
+#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
+#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
+#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
+#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
+#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
+#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
+#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
+#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
+#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
+#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
+#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
+#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
+#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
+#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
+#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
+#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
+
+/* SPI2 Registers */
+
+#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
+#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
+#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
+#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
+#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
+#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
+#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
+#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
+#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
+#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
+#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
+#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
+#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
+#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
+
+/* ATAPI Registers */
+
+#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
+#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
+#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
+#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
+#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
+#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
+#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
+#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
+#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
+#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
+#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
+#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
+#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
+#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
+#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
+#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
+#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
+#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
+#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
+#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
+#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
+#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
+#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
+#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
+#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
+#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
+#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
+#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
+#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
+#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
+#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
+#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
+#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
+#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
+#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
+#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
+#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
+#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
+#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
+#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
+#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
+#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
+#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
+#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
+#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
+#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
+#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
+#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
+#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
+#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
+
+/* SDH Registers */
+
+#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
+#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
+#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
+#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
+#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
+#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
+#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
+#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
+#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
+#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
+#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
+#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
+#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
+#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
+#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
+#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
+#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
+#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
+#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
+#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
+#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
+#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
+#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
+#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
+#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
+#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
+#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
+#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
+#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
+#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
+#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
+#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
+#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
+#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
+#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
+#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
+#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
+#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
+#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
+#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
+#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
+#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
+#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
+#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
+#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
+#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
+#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
+#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
+#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
+#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
+#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
+#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
+#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
+#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
+#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
+#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
+#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
+#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
+#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
+#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
+#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
+#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
+
+/* HOST Port Registers */
+
+#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
+#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
+#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
+#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
+#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
+#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
+
+/* USB Control Registers */
+
+#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
+#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
+#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
+#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
+#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
+#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
+#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
+#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
+#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
+#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
+#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
+#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
+#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
+#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
+#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
+#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
+#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
+#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
+#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
+#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
+#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
+#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
+#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
+#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
+#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
+#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
+
+/* USB Packet Control Registers */
+
+#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
+#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
+#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
+#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
+#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
+#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
+#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
+#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
+#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
+#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
+#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
+#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
+#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
+#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
+#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
+#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
+#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
+#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
+#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
+#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
+#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
+#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
+#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
+#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
+#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
+#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
+
+/* USB Endbfin_read_()oint FIFO Registers */
+
+#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
+#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
+#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
+#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
+#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
+#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
+#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
+#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
+#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
+#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
+#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
+#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
+#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
+#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
+#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
+#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
+
+/* USB OTG Control Registers */
+
+#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
+#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
+#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
+#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
+#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
+#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
+
+/* USB Phy Control Registers */
+
+#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
+#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
+#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
+#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
+#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
+#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
+#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
+#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
+#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
+#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
+#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
+#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
+#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
+#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
+#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
+#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
+#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
+#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
+#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
+
+/* USB Endbfin_read_()oint 0 Control Registers */
+
+#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
+#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
+#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
+#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
+#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
+#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
+#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
+#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
+#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
+#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
+#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
+#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
+#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
+#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
+#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
+#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
+#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 1 Control Registers */
+
+#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
+#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
+#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
+#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
+#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
+#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
+#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
+#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
+#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
+#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
+#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
+#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
+#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
+#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
+#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
+#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
+#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
+#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
+#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 2 Control Registers */
+
+#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
+#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
+#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
+#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
+#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
+#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
+#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
+#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
+#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
+#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
+#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
+#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
+#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
+#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
+#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
+#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
+#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
+#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
+#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 3 Control Registers */
+
+#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
+#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
+#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
+#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
+#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
+#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
+#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
+#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
+#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
+#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
+#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
+#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
+#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
+#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
+#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
+#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
+#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
+#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
+#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 4 Control Registers */
+
+#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
+#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
+#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
+#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
+#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
+#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
+#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
+#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
+#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
+#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
+#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
+#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
+#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
+#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
+#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
+#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
+#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
+#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
+#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 5 Control Registers */
+
+#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
+#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
+#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
+#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
+#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
+#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
+#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
+#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
+#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
+#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
+#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
+#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
+#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
+#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
+#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
+#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
+#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
+#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
+#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 6 Control Registers */
+
+#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
+#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
+#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
+#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
+#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
+#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
+#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
+#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
+#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
+#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
+#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
+#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
+#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
+#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
+#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
+#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
+#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
+#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
+#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
+
+/* USB Endbfin_read_()oint 7 Control Registers */
+
+#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
+#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
+#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
+#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
+#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
+#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
+#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
+#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
+#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
+#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
+#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
+#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
+#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
+#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
+#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
+#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
+#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
+#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
+#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
+#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
+#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
+#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
+#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
+
+/* USB Channel 0 Config Registers */
+
+#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
+#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
+#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
+#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
+#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
+#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
+#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
+#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
+#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
+#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
+
+/* USB Channel 1 Config Registers */
+
+#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
+#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
+#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
+#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
+#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
+#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
+#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
+#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
+#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
+#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
+
+/* USB Channel 2 Config Registers */
+
+#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
+#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
+#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
+#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
+#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
+#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
+#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
+#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
+#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
+#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
+
+/* USB Channel 3 Config Registers */
+
+#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
+#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
+#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
+#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
+#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
+#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
+#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
+#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
+#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
+#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
+
+/* USB Channel 4 Config Registers */
+
+#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
+#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
+#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
+#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
+#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
+#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
+#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
+#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
+#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
+#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
+
+/* USB Channel 5 Config Registers */
+
+#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
+#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
+#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
+#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
+#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
+#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
+#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
+#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
+#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
+#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
+
+/* USB Channel 6 Config Registers */
+
+#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
+#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
+#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
+#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
+#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
+#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
+#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
+#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
+#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
+#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
+
+/* USB Channel 7 Config Registers */
+
+#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
+#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
+#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
+#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
+#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
+#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
+#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
+#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
+#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
+#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
+
+/* Keybfin_read_()ad Registers */
+
+#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
+#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
+#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
+#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
+#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
+#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
+#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
+#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
+#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
+#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
+#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
+#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
+
+/* Pixel Combfin_read_()ositor (PIXC) Registers */
+
+#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
+#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
+#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
+#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
+#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
+#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
+#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
+#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
+#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
+#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
+#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
+#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
+#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
+#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
+#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
+#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
+#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
+#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
+#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
+#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
+#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
+#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
+#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
+#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
+#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
+#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
+#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
+#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
+#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
+#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
+#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
+#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
+#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
+#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
+#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
+#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
+#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
+#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
+
+/* Handshake MDMA 0 Registers */
+
+#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
+#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
+#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
+#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
+#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
+#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
+#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
+
+/* Handshake MDMA 1 Registers */
+
+#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
+#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
+#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
+#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
+#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
+#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
+#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
+
+#endif /* _CDEF_BF548_H */
--- /dev/null
+/*
+ * File: include/asm-blackfin/mach-bf548/defBF547.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF548_H
+#define _DEF_BF548_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/mach-common/def_LPBlackfin.h>
+
+/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
+
+/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
+#include "defBF54x_base.h"
+
+/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
+
+/* Timer Registers */
+
+#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
+#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
+#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
+#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
+#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
+#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
+#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
+#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
+#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
+#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
+#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
+#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
+
+/* Timer Group of 3 Registers */
+
+#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
+#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
+#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
+
+/* SPORT0 Registers */
+
+#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
+#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
+#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
+#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
+#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
+#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
+#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
+#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
+#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
+#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
+#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
+#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
+#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
+#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
+#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
+#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
+#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
+#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
+#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
+
+/* EPPI0 Registers */
+
+#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
+#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
+#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
+#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
+#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
+#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
+#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
+#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
+#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
+#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
+#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
+#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
+#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
+#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
+
+/* UART2 Registers */
+
+#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
+#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
+#define UART2_GCTL 0xffc02108 /* Global Control Register */
+#define UART2_LCR 0xffc0210c /* Line Control Register */
+#define UART2_MCR 0xffc02110 /* Modem Control Register */
+#define UART2_LSR 0xffc02114 /* Line Status Register */
+#define UART2_MSR 0xffc02118 /* Modem Status Register */
+#define UART2_SCR 0xffc0211c /* Scratch Register */
+#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
+#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
+#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
+
+/* Two Wire Interface Registers (TWI1) */
+
+#define TWI1_REGBASE 0xffc02200
+#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
+#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
+#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
+#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
+#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
+#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
+#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
+#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
+#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
+#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
+#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
+#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
+#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
+#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
+#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
+#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
+
+/* SPI2 Registers */
+
+#define SPI2_REGBASE 0xffc02400
+#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
+#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
+#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
+#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
+#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
+#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
+#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
+
+/* ATAPI Registers */
+
+#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
+#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
+#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
+#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
+#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
+#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
+#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
+#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
+#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
+#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
+#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
+#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
+#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
+#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
+#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
+#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
+#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
+#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
+#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
+#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
+#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
+#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
+#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
+#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
+
+/* SDH Registers */
+
+#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
+#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
+#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
+#define SDH_COMMAND 0xffc0390c /* SDH Command */
+#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
+#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
+#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
+#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
+#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
+#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
+#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
+#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
+#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
+#define SDH_STATUS 0xffc03934 /* SDH Status */
+#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
+#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
+#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
+#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
+#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
+#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
+#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
+#define SDH_CFG 0xffc039c8 /* SDH Configuration */
+#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
+#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
+#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
+#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
+#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
+#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
+#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
+#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
+#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
+
+/* HOST Port Registers */
+
+#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
+#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
+#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
+
+/* USB Control Registers */
+
+#define USB_FADDR 0xffc03c00 /* Function address register */
+#define USB_POWER 0xffc03c04 /* Power management register */
+#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
+#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
+#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
+#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
+#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
+#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
+#define USB_FRAME 0xffc03c20 /* USB frame number */
+#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
+#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
+#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
+#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
+
+/* USB Packet Control Registers */
+
+#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
+#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
+#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
+#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
+#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
+#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
+#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
+#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
+#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
+#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* USB Endpoint FIFO Registers */
+
+#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
+#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
+#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
+#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
+#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
+#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
+#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
+#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
+
+/* USB OTG Control Registers */
+
+#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
+#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
+#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
+
+/* USB Phy Control Registers */
+
+#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
+#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
+#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
+#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
+#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
+
+/* (APHY_CNTRL is for ADI usage only) */
+
+#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
+
+/* (APHY_CALIB is for ADI usage only) */
+
+#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
+#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
+
+/* (PHY_TEST is for ADI usage only) */
+
+#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
+#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
+#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
+
+/* USB Endpoint 0 Control Registers */
+
+#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
+#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
+#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
+#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
+#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
+#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
+#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
+#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+
+/* USB Endpoint 1 Control Registers */
+
+#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
+#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
+#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
+#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
+#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
+#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
+#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
+#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
+#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+
+/* USB Endpoint 2 Control Registers */
+
+#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
+#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
+#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
+#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
+#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
+#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
+#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
+#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
+#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+
+/* USB Endpoint 3 Control Registers */
+
+#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
+#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
+#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
+#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
+#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
+#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
+#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
+#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
+#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+
+/* USB Endpoint 4 Control Registers */
+
+#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
+#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
+#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
+#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
+#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
+#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
+#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
+#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
+#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+
+/* USB Endpoint 5 Control Registers */
+
+#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
+#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
+#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
+#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
+#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
+#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
+#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
+#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
+#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+
+/* USB Endpoint 6 Control Registers */
+
+#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
+#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
+#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
+#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
+#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
+#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
+#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
+#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
+#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+
+/* USB Endpoint 7 Control Registers */
+
+#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
+#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
+#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
+#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
+#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
+#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
+#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
+#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
+#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
+
+/* USB Channel 0 Config Registers */
+
+#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
+#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
+#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
+#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
+
+/* USB Channel 1 Config Registers */
+
+#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
+#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
+#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
+#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
+
+/* USB Channel 2 Config Registers */
+
+#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
+#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
+#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
+#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
+
+/* USB Channel 3 Config Registers */
+
+#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
+#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
+#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
+#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
+
+/* USB Channel 4 Config Registers */
+
+#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
+#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
+#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
+#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
+
+/* USB Channel 5 Config Registers */
+
+#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
+#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
+#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
+#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
+
+/* USB Channel 6 Config Registers */
+
+#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
+#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
+#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
+#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
+
+/* USB Channel 7 Config Registers */
+
+#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
+#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
+#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
+#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
+
+/* Keypad Registers */
+
+#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
+#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
+#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
+#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
+#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
+#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
+
+/* Pixel Compositor (PIXC) Registers */
+
+#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
+#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
+#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
+#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
+#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
+#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
+#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
+#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
+#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
+#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
+#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
+#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
+#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
+#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
+#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
+#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
+#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
+#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
+#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
+
+/* Handshake MDMA 0 Registers */
+
+#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
+#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
+#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
+#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
+#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
+#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
+#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
+
+/* Handshake MDMA 1 Registers */
+
+#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
+#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
+#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
+#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
+#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
+#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
+#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
+
+
+/* ********************************************************** */
+/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
+/* and MULTI BIT READ MACROS */
+/* ********************************************************** */
+
+/* Bit masks for PIXC_CTL */
+
+#define PIXC_EN 0x1 /* Pixel Compositor Enable */
+#define OVR_A_EN 0x2 /* Overlay A Enable */
+#define OVR_B_EN 0x4 /* Overlay B Enable */
+#define IMG_FORM 0x8 /* Image Data Format */
+#define OVR_FORM 0x10 /* Overlay Data Format */
+#define OUT_FORM 0x20 /* Output Data Format */
+#define UDS_MOD 0x40 /* Resampling Mode */
+#define TC_EN 0x80 /* Transparent Color Enable */
+#define IMG_STAT 0x300 /* Image FIFO Status */
+#define OVR_STAT 0xc00 /* Overlay FIFO Status */
+#define WM_LVL 0x3000 /* FIFO Watermark Level */
+
+/* Bit masks for PIXC_AHSTART */
+
+#define A_HSTART 0xfff /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_AHEND */
+
+#define A_HEND 0xfff /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_AVSTART */
+
+#define A_VSTART 0x3ff /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_AVEND */
+
+#define A_VEND 0x3ff /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_ATRANSP */
+
+#define A_TRANSP 0xf /* Transparency Value */
+
+/* Bit masks for PIXC_BHSTART */
+
+#define B_HSTART 0xfff /* Horizontal Start Coordinates */
+
+/* Bit masks for PIXC_BHEND */
+
+#define B_HEND 0xfff /* Horizontal End Coordinates */
+
+/* Bit masks for PIXC_BVSTART */
+
+#define B_VSTART 0x3ff /* Vertical Start Coordinates */
+
+/* Bit masks for PIXC_BVEND */
+
+#define B_VEND 0x3ff /* Vertical End Coordinates */
+
+/* Bit masks for PIXC_BTRANSP */
+
+#define B_TRANSP 0xf /* Transparency Value */
+
+/* Bit masks for PIXC_INTRSTAT */
+
+#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
+#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
+#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
+#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
+
+/* Bit masks for PIXC_RYCON */
+
+#define A11 0x3ff /* A11 in the Coefficient Matrix */
+#define A12 0xffc00 /* A12 in the Coefficient Matrix */
+#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
+#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
+
+/* Bit masks for PIXC_GUCON */
+
+#define A21 0x3ff /* A21 in the Coefficient Matrix */
+#define A22 0xffc00 /* A22 in the Coefficient Matrix */
+#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
+#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
+
+/* Bit masks for PIXC_BVCON */
+
+#define A31 0x3ff /* A31 in the Coefficient Matrix */
+#define A32 0xffc00 /* A32 in the Coefficient Matrix */
+#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
+#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
+
+/* Bit masks for PIXC_CCBIAS */
+
+#define A14 0x3ff /* A14 in the Bias Vector */
+#define A24 0xffc00 /* A24 in the Bias Vector */
+#define A34 0x3ff00000 /* A34 in the Bias Vector */
+
+/* Bit masks for PIXC_TC */
+
+#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
+#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
+#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
+
+/* Bit masks for HOST_CONTROL */
+
+#define HOST_EN 0x1 /* Host Enable */
+#define HOST_END 0x2 /* Host Endianess */
+#define DATA_SIZE 0x4 /* Data Size */
+#define HOST_RST 0x8 /* Host Reset */
+#define HRDY_OVR 0x20 /* Host Ready Override */
+#define INT_MODE 0x40 /* Interrupt Mode */
+#define BT_EN 0x80 /* Bus Timeout Enable */
+#define EHW 0x100 /* Enable Host Write */
+#define EHR 0x200 /* Enable Host Read */
+#define BDR 0x400 /* Burst DMA Requests */
+
+/* Bit masks for HOST_STATUS */
+
+#define DMA_READY 0x1 /* DMA Ready */
+#define FIFOFULL 0x2 /* FIFO Full */
+#define FIFOEMPTY 0x4 /* FIFO Empty */
+#define DMA_COMPLETE 0x8 /* DMA Complete */
+#define HSHK 0x10 /* Host Handshake */
+#define HSTIMEOUT 0x20 /* Host Timeout */
+#define HIRQ 0x40 /* Host Interrupt Request */
+#define ALLOW_CNFG 0x80 /* Allow New Configuration */
+#define DMA_DIR 0x100 /* DMA Direction */
+#define BTE 0x200 /* Bus Timeout Enabled */
+
+/* Bit masks for HOST_TIMEOUT */
+
+#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
+
+/* Bit masks for KPAD_CTL */
+
+#define KPAD_EN 0x1 /* Keypad Enable */
+#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
+#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
+#define KPAD_COLEN 0xe000 /* Column Enable Width */
+
+/* Bit masks for KPAD_PRESCALE */
+
+#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
+
+/* Bit masks for KPAD_MSEL */
+
+#define DBON_SCALE 0xff /* Debounce Scale Value */
+#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
+
+/* Bit masks for KPAD_ROWCOL */
+
+#define KPAD_ROW 0xff /* Rows Pressed */
+#define KPAD_COL 0xff00 /* Columns Pressed */
+
+/* Bit masks for KPAD_STAT */
+
+#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
+#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
+#define KPAD_PRESSED 0x8 /* Key press current status */
+
+/* Bit masks for KPAD_SOFTEVAL */
+
+#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
+
+/* Bit masks for SDH_COMMAND */
+
+#define CMD_IDX 0x3f /* Command Index */
+#define CMD_RSP 0x40 /* Response */
+#define CMD_L_RSP 0x80 /* Long Response */
+#define CMD_INT_E 0x100 /* Command Interrupt */
+#define CMD_PEND_E 0x200 /* Command Pending */
+#define CMD_E 0x400 /* Command Enable */
+
+/* Bit masks for SDH_PWR_CTL */
+
+#define PWR_ON 0x3 /* Power On */
+#if 0
+#define TBD 0x3c /* TBD */
+#endif
+#define SD_CMD_OD 0x40 /* Open Drain Output */
+#define ROD_CTL 0x80 /* Rod Control */
+
+/* Bit masks for SDH_CLK_CTL */
+
+#define CLKDIV 0xff /* MC_CLK Divisor */
+#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
+#define PWR_SV_E 0x200 /* Power Save Enable */
+#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
+#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
+
+/* Bit masks for SDH_RESP_CMD */
+
+#define RESP_CMD 0x3f /* Response Command */
+
+/* Bit masks for SDH_DATA_CTL */
+
+#define DTX_E 0x1 /* Data Transfer Enable */
+#define DTX_DIR 0x2 /* Data Transfer Direction */
+#define DTX_MODE 0x4 /* Data Transfer Mode */
+#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
+#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
+
+/* Bit masks for SDH_STATUS */
+
+#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
+#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
+#define CMD_TIME_OUT 0x4 /* CMD Time Out */
+#define DAT_TIME_OUT 0x8 /* Data Time Out */
+#define TX_UNDERRUN 0x10 /* Transmit Underrun */
+#define RX_OVERRUN 0x20 /* Receive Overrun */
+#define CMD_RESP_END 0x40 /* CMD Response End */
+#define CMD_SENT 0x80 /* CMD Sent */
+#define DAT_END 0x100 /* Data End */
+#define START_BIT_ERR 0x200 /* Start Bit Error */
+#define DAT_BLK_END 0x400 /* Data Block End */
+#define CMD_ACT 0x800 /* CMD Active */
+#define TX_ACT 0x1000 /* Transmit Active */
+#define RX_ACT 0x2000 /* Receive Active */
+#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
+#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
+#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
+#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
+#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
+#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
+#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
+#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
+
+/* Bit masks for SDH_STATUS_CLR */
+
+#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
+#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
+#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
+#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
+#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
+#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
+#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
+#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
+#define DAT_END_STAT 0x100 /* Data End Status */
+#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
+#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
+
+/* Bit masks for SDH_MASK0 */
+
+#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
+#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
+#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
+#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
+#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
+#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
+#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
+#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
+#define DAT_END_MASK 0x100 /* Data End Mask */
+#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
+#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
+#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
+#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
+#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
+#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
+#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
+#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
+#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
+#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
+#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
+#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
+#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
+
+/* Bit masks for SDH_FIFO_CNT */
+
+#define FIFO_COUNT 0x7fff /* FIFO Count */
+
+/* Bit masks for SDH_E_STATUS */
+
+#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
+#define SD_CARD_DET 0x10 /* SD Card Detect */
+
+/* Bit masks for SDH_E_MASK */
+
+#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
+#define SCD_MSK 0x40 /* Mask Card Detect */
+
+/* Bit masks for SDH_CFG */
+
+#define CLKS_EN 0x1 /* Clocks Enable */
+#define SD4E 0x4 /* SDIO 4-Bit Enable */
+#define MWE 0x8 /* Moving Window Enable */
+#define SD_RST 0x10 /* SDMMC Reset */
+#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
+#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
+#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
+
+/* Bit masks for SDH_RD_WAIT_EN */
+
+#define RWR 0x1 /* Read Wait Request */
+
+/* Bit masks for ATAPI_CONTROL */
+
+#define PIO_START 0x1 /* Start PIO/Reg Op */
+#define MULTI_START 0x2 /* Start Multi-DMA Op */
+#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
+#define XFER_DIR 0x8 /* Transfer Direction */
+#define IORDY_EN 0x10 /* IORDY Enable */
+#define FIFO_FLUSH 0x20 /* Flush FIFOs */
+#define SOFT_RST 0x40 /* Soft Reset */
+#define DEV_RST 0x80 /* Device Reset */
+#define TFRCNT_RST 0x100 /* Trans Count Reset */
+#define END_ON_TERM 0x200 /* End/Terminate Select */
+#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
+#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
+
+/* Bit masks for ATAPI_STATUS */
+
+#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
+#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
+#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
+#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
+
+/* Bit masks for ATAPI_DEV_ADDR */
+
+#define DEV_ADDR 0x1f /* Device Address */
+
+/* Bit masks for ATAPI_INT_MASK */
+
+#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
+#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
+#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
+#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
+#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
+#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
+#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
+#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
+#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
+
+/* Bit masks for ATAPI_INT_STATUS */
+
+#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
+#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
+#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
+#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
+#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
+#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
+#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
+#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
+#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
+
+/* Bit masks for ATAPI_LINE_STATUS */
+
+#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
+#define ATAPI_DASP 0x2 /* Device dasp to host line status */
+#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
+#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
+#define ATAPI_ADDR 0x70 /* ATAPI address line status */
+#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
+#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
+#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
+#define ATAPI_DIORN 0x400 /* ATAPI read line status */
+#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_SM_STATE */
+
+#define PIO_CSTATE 0xf /* PIO mode state machine current state */
+#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
+#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
+#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
+
+/* Bit masks for ATAPI_TERMINATE */
+
+#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
+
+/* Bit masks for ATAPI_REG_TIM_0 */
+
+#define T2_REG 0xff /* End of cycle time for register access transfers */
+#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
+
+/* Bit masks for ATAPI_PIO_TIM_0 */
+
+#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
+#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
+#define T4_REG 0xf000 /* DIOW data hold */
+
+/* Bit masks for ATAPI_PIO_TIM_1 */
+
+#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
+
+/* Bit masks for ATAPI_MULTI_TIM_0 */
+
+#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
+#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
+
+/* Bit masks for ATAPI_MULTI_TIM_1 */
+
+#define TKW 0xff /* Selects DIOW negated pulsewidth */
+#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
+
+/* Bit masks for ATAPI_MULTI_TIM_2 */
+
+#define TH 0xff /* Selects DIOW data hold */
+#define TEOC 0xff00 /* Selects end of cycle for DMA */
+
+/* Bit masks for ATAPI_ULTRA_TIM_0 */
+
+#define TACK 0xff /* Selects setup and hold times for TACK */
+#define TENV 0xff00 /* Selects envelope time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_1 */
+
+#define TDVS 0xff /* Selects data valid setup time */
+#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_2 */
+
+#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
+#define TMLI 0xff00 /* Selects interlock time */
+
+/* Bit masks for ATAPI_ULTRA_TIM_3 */
+
+#define TZAH 0xff /* Selects minimum delay required for output */
+#define READY_PAUSE 0xff00 /* Selects ready to pause */
+
+/* Bit masks for TIMER_ENABLE1 */
+
+#define TIMEN8 0x1 /* Timer 8 Enable */
+#define TIMEN9 0x2 /* Timer 9 Enable */
+#define TIMEN10 0x4 /* Timer 10 Enable */
+
+/* Bit masks for TIMER_DISABLE1 */
+
+#define TIMDIS8 0x1 /* Timer 8 Disable */
+#define TIMDIS9 0x2 /* Timer 9 Disable */
+#define TIMDIS10 0x4 /* Timer 10 Disable */
+
+/* Bit masks for TIMER_STATUS1 */
+
+#define TIMIL8 0x1 /* Timer 8 Interrupt */
+#define TIMIL9 0x2 /* Timer 9 Interrupt */
+#define TIMIL10 0x4 /* Timer 10 Interrupt */
+#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
+#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
+#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
+#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
+#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
+#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
+
+/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
+
+/* Bit masks for USB_FADDR */
+
+#define FUNCTION_ADDRESS 0x7f /* Function address */
+
+/* Bit masks for USB_POWER */
+
+#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
+#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
+#define RESUME_MODE 0x4 /* DMA Mode */
+#define RESET 0x8 /* Reset indicator */
+#define HS_MODE 0x10 /* High Speed mode indicator */
+#define HS_ENABLE 0x20 /* high Speed Enable */
+#define SOFT_CONN 0x40 /* Soft connect */
+#define ISO_UPDATE 0x80 /* Isochronous update */
+
+/* Bit masks for USB_INTRTX */
+
+#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
+#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
+#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
+#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
+#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
+#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
+#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
+#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
+
+/* Bit masks for USB_INTRRX */
+
+#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
+#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
+#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
+#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
+#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
+#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
+#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
+
+/* Bit masks for USB_INTRTXE */
+
+#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
+#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
+#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
+#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
+#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
+#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
+#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
+#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
+
+/* Bit masks for USB_INTRRXE */
+
+#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
+#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
+#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
+#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
+#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
+#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
+#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
+
+/* Bit masks for USB_INTRUSB */
+
+#define SUSPEND_B 0x1 /* Suspend indicator */
+#define RESUME_B 0x2 /* Resume indicator */
+#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
+#define SOF_B 0x8 /* Start of frame */
+#define CONN_B 0x10 /* Connection indicator */
+#define DISCON_B 0x20 /* Disconnect indicator */
+#define SESSION_REQ_B 0x40 /* Session Request */
+#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
+
+/* Bit masks for USB_INTRUSBE */
+
+#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
+#define RESUME_BE 0x2 /* Resume indicator int enable */
+#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
+#define SOF_BE 0x8 /* Start of frame int enable */
+#define CONN_BE 0x10 /* Connection indicator int enable */
+#define DISCON_BE 0x20 /* Disconnect indicator int enable */
+#define SESSION_REQ_BE 0x40 /* Session Request int enable */
+#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
+
+/* Bit masks for USB_FRAME */
+
+#define FRAME_NUMBER 0x7ff /* Frame number */
+
+/* Bit masks for USB_INDEX */
+
+#define SELECTED_ENDPOINT 0xf /* selected endpoint */
+
+/* Bit masks for USB_GLOBAL_CTL */
+
+#define GLOBAL_ENA 0x1 /* enables USB module */
+#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
+#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
+#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
+#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
+#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
+#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
+#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
+#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
+#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
+#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
+#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
+#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
+#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
+#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
+
+/* Bit masks for USB_OTG_DEV_CTL */
+
+#define SESSION 0x1 /* session indicator */
+#define HOST_REQ 0x2 /* Host negotiation request */
+#define HOST_MODE 0x4 /* indicates USBDRC is a host */
+#define VBUS0 0x8 /* Vbus level indicator[0] */
+#define VBUS1 0x10 /* Vbus level indicator[1] */
+#define LSDEV 0x20 /* Low-speed indicator */
+#define FSDEV 0x40 /* Full or High-speed indicator */
+#define B_DEVICE 0x80 /* A' or 'B' device indicator */
+
+/* Bit masks for USB_OTG_VBUS_IRQ */
+
+#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
+#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
+#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
+#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
+#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
+#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
+
+/* Bit masks for USB_OTG_VBUS_MASK */
+
+#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
+#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
+#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
+#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
+#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
+#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
+
+/* Bit masks for USB_CSR0 */
+
+#define RXPKTRDY 0x1 /* data packet receive indicator */
+#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
+#define STALL_SENT 0x4 /* STALL handshake sent */
+#define DATAEND 0x8 /* Data end indicator */
+#define SETUPEND 0x10 /* Setup end */
+#define SENDSTALL 0x20 /* Send STALL handshake */
+#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
+#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
+#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
+#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
+#define SETUPPKT_H 0x8 /* send Setup token host mode */
+#define ERROR_H 0x10 /* timeout error indicator host mode */
+#define REQPKT_H 0x20 /* Request an IN transaction host mode */
+#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
+#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
+
+/* Bit masks for USB_COUNT0 */
+
+#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
+
+/* Bit masks for USB_NAKLIMIT0 */
+
+#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
+
+/* Bit masks for USB_TX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_RX_MAX_PACKET */
+
+#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
+
+/* Bit masks for USB_TXCSR */
+
+#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
+#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
+#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
+#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
+#define STALL_SEND_T 0x10 /* issue a Stall handshake */
+#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
+#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
+#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
+#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
+#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
+#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
+#define ISO_T 0x4000 /* enable Isochronous transfers */
+#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
+#define ERROR_TH 0x4 /* error condition host mode */
+#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
+#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
+
+/* Bit masks for USB_TXCOUNT */
+
+#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
+
+/* Bit masks for USB_RXCSR */
+
+#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
+#define FIFO_FULL_R 0x2 /* FIFO not empty */
+#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
+#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
+#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
+#define STALL_SEND_R 0x20 /* issue a Stall handshake */
+#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
+#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
+#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
+#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
+#define DISNYET_R 0x1000 /* disable Nyet handshakes */
+#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
+#define ISO_R 0x4000 /* enable Isochronous transfers */
+#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
+#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
+#define REQPKT_RH 0x20 /* request an IN transaction host mode */
+#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
+#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
+#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
+#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
+
+/* Bit masks for USB_RXCOUNT */
+
+#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
+
+/* Bit masks for USB_TXTYPE */
+
+#define TARGET_EP_NO_T 0xf /* EP number */
+#define PROTOCOL_T 0xc /* transfer type */
+
+/* Bit masks for USB_TXINTERVAL */
+
+#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
+
+/* Bit masks for USB_RXTYPE */
+
+#define TARGET_EP_NO_R 0xf /* EP number */
+#define PROTOCOL_R 0xc /* transfer type */
+
+/* Bit masks for USB_RXINTERVAL */
+
+#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
+
+/* Bit masks for USB_DMA_INTERRUPT */
+
+#define DMA0_INT 0x1 /* DMA0 pending interrupt */
+#define DMA1_INT 0x2 /* DMA1 pending interrupt */
+#define DMA2_INT 0x4 /* DMA2 pending interrupt */
+#define DMA3_INT 0x8 /* DMA3 pending interrupt */
+#define DMA4_INT 0x10 /* DMA4 pending interrupt */
+#define DMA5_INT 0x20 /* DMA5 pending interrupt */
+#define DMA6_INT 0x40 /* DMA6 pending interrupt */
+#define DMA7_INT 0x80 /* DMA7 pending interrupt */
+
+/* Bit masks for USB_DMAxCONTROL */
+
+#define DMA_ENA 0x1 /* DMA enable */
+#define DIRECTION 0x2 /* direction of DMA transfer */
+#define MODE 0x4 /* DMA Bus error */
+#define INT_ENA 0x8 /* Interrupt enable */
+#define EPNUM 0xf0 /* EP number */
+#define BUSERROR 0x100 /* DMA Bus error */
+
+/* Bit masks for USB_DMAxADDRHIGH */
+
+#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxADDRLOW */
+
+#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTHIGH */
+
+#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for USB_DMAxCOUNTLOW */
+
+#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
+
+/* Bit masks for HMDMAx_CONTROL */
+
+#define HMDMAEN 0x1 /* Handshake MDMA Enable */
+#define REP 0x2 /* Handshake MDMA Request Polarity */
+#define UTE 0x8 /* Urgency Threshold Enable */
+#define OIE 0x10 /* Overflow Interrupt Enable */
+#define BDIE 0x20 /* Block Done Interrupt Enable */
+#define MBDI 0x40 /* Mask Block Done Interrupt */
+#define DRQ 0x300 /* Handshake MDMA Request Type */
+#define RBC 0x1000 /* Force Reload of BCOUNT */
+#define PS 0x2000 /* Pin Status */
+#define OI 0x4000 /* Overflow Interrupt Generated */
+#define BDI 0x8000 /* Block Done Interrupt Generated */
+
+/* ******************************************* */
+/* MULTI BIT MACRO ENUMERATIONS */
+/* ******************************************* */
+
+
+#endif /* _DEF_BF548_H */
#define DMA_READY 0x1 /* DMA Ready */
#define FIFOFULL 0x2 /* FIFO Full */
#define FIFOEMPTY 0x4 /* FIFO Empty */
-#define COMPLETE 0x8 /* DMA Complete */
+#define DMA_COMPLETE 0x8 /* DMA Complete */
#define HSHK 0x10 /* Host Handshake */
-#define TIMEOUT 0x20 /* Host Timeout */
+#define HSTIMEOUT 0x20 /* Host Timeout */
#define HIRQ 0x40 /* Host Interrupt Request */
#define ALLOW_CNFG 0x80 /* Allow New Configuration */
#define DMA_DIR 0x100 /* DMA Direction */
#define CH_PIXC_OVERLAY 16
#define CH_PIXC_OUTPUT 17
#define CH_SPORT2_RX 18
+#define CH_UART2_RX 18
#define CH_SPORT2_TX 19
+#define CH_UART2_TX 19
#define CH_SPORT3_RX 20
+#define CH_UART3_RX 20
#define CH_SPORT3_TX 21
+#define CH_UART3_TX 21
#define CH_SDH 22
#define CH_NFC 22
#define CH_SPI2 23
#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
+#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
+#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
+#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
+#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
/* IAR4 BIT FILEDS */
#define IRQ_CAN0_ERR_POS 0
#define IRQ_SPORT2_RX_POS 4
+#define IRQ_UART2_RX_POS 4
#define IRQ_SPORT2_TX_POS 8
+#define IRQ_UART2_TX_POS 8
#define IRQ_SPORT3_RX_POS 12
+#define IRQ_UART3_RX_POS 12
#define IRQ_SPORT3_TX_POS 16
+#define IRQ_UART3_TX_POS 16
#define IRQ_EPPI1_POS 20
#define IRQ_EPPI2_POS 24
#define IRQ_SPI1_POS 28
#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
+
+#define SIC_IAR0 SICA_IAR0
+#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
+#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
+#define bfin_write_SIC_IWR0 bfin_write_SICA_IWR0
+#define bfin_write_SIC_IWR1 bfin_write_SICA_IWR1
+
+#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
+#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
+#define bfin_read_SIC_IWR0 bfin_read_SICA_IWR0
+#define bfin_read_SIC_IWR1 bfin_read_SICA_IWR1
+#define bfin_read_SIC_ISR0 bfin_read_SICA_ISR0
+#define bfin_read_SIC_ISR1 bfin_read_SICA_ISR1
+
+#define bfin_read_SIC_IMASK(x) bfin_read32(SICA_IMASK0 + (x << 2))
+#define bfin_write_SIC_IMASK(x, val) bfin_write32((SICA_IMASK0 + (x << 2)), val)
+#define bfin_read_SIC_ISR(x) bfin_read32(SICA_ISR0 + (x << 2))
+#define bfin_write_SIC_ISR(x, val) bfin_write32((SICA_ISR0 + (x << 2)), val)
+
+
#endif /* _MACH_BLACKFIN_H_ */
#endif
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
#undef __FD_SET
#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
#undef __FD_ZERO
#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif
extern unsigned long memory_end;
#define TASK_SIZE (memory_end)
+#ifdef __KERNEL__
+#define STACK_TOP TASK_SIZE
+#endif
+
#define TASK_UNMAPPED_BASE 0
struct thread_struct {
/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-/* line disciplines */
-#define N_TTY 0
-#define N_SLIP 1
-#define N_MOUSE 2
-#define N_PPP 3
-#define N_STRIP 4
-#define N_AX25 5
-#define N_X25 6 /* X.25 async */
-#define N_6PACK 7
-#define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */
-#define N_R3964 9 /* Reserved for Simatic R3964 module */
-#define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */
-#define N_IRDA 11 /* Linux IR - http://irda.sourceforge.net/ */
-#define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */
-#define N_HDLC 13 /* synchronous HDLC */
-#define N_SYNC_PPP 14 /* synchronous PPP */
-#define N_HCI 15 /* Bluetooth HCI UART */
-
#ifdef __KERNEL__
/* intr=^C quit=^\ erase=del kill=^U
#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-#define TRACE_BUFFER_START(preg, dreg) trace_buffer_start(preg, dreg)
-#define TRACE_BUFFER_STOP(preg, dreg) trace_buffer_stop(preg, dreg)
-
#define trace_buffer_stop(preg, dreg) \
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
dreg = 0x1; \
[preg] = dreg;
-#define trace_buffer_start(preg, dreg) \
- preg.L = LO(TBUFCTL); \
- preg.H = HI(TBUFCTL); \
- dreg = BFIN_TRACE_ON; \
- [preg] = dreg;
-
#define trace_buffer_init(preg, dreg) \
preg.L = LO(TBUFCTL); \
preg.H = HI(TBUFCTL); \
dreg = BFIN_TRACE_INIT; \
[preg] = dreg;
+#define trace_buffer_save(preg, dreg) \
+ preg.L = LO(TBUFCTL); \
+ preg.H = HI(TBUFCTL); \
+ dreg = [preg]; \
+ [sp++] = dreg; \
+ dreg = 0x1; \
+ [preg] = dreg;
+
+#define trace_buffer_restore(preg, dreg) \
+ preg.L = LO(TBUFCTL); \
+ preg.H = HI(TBUFCTL); \
+ dreg = [sp--]; \
+ [preg] = dreg;
+
#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
#define trace_buffer_stop(preg, dreg)
-#define trace_buffer_start(preg, dreg)
#define trace_buffer_init(preg, dreg)
+#define trace_buffer_save(preg, dreg)
+#define trace_buffer_restore(preg, dreg)
#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
-# define DEBUG_START_HWTRACE(preg, dreg) trace_buffer_start(preg, dreg)
-# define DEBUG_STOP_HWTRACE(preg, dreg) trace_buffer_stop(preg, dreg)
-
+# define DEBUG_HWTRACE_SAVE(preg, dreg) trace_buffer_save(preg, dreg)
+# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg)
#else
-# define DEBUG_START_HWTRACE(preg, dreg)
-# define DEBUG_STOP_HWTRACE(preg, dreg)
+# define DEBUG_HWTRACE_SAVE(preg, dreg)
+# define DEBUG_HWTRACE_RESTORE(preg, dreg)
#endif
#endif /* __ASSEMBLY__ */
include include/asm-generic/Kbuild.asm
-header-y += arch-v10/ arch-v32/
+header-$(CONFIG_ETRAX_ARCH_V10) += arch-v10/
+header-$(CONFIG_ETRAX_ARCH_V32) += arch-v32/
+header-y += ethernet.h
+header-y += rtc.h
+header-y += sync_serial.h
+
+unifdef-y += etraxgpio.h
unifdef-y += rs485.h
* wants to know about a.out even if there is no interpreter available...
*/
-/* grabbed from the intel stuff */
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-
-
struct exec
{
unsigned long a_info; /* Use macros N_MAGIC, etc for access */
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-
#endif
header-y += ptrace.h
header-y += user.h
+header-y += svinto.h
+header-y += sv_addr_ag.h
+header-y += sv_addr.agh
--- /dev/null
+#ifndef __ASM_CRISv10_ARCH_BUG_H
+#define __ASM_CRISv10_ARCH_BUG_H
+
+#include <linux/stringify.h>
+
+#ifdef CONFIG_BUG
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+/* The BUG() macro is used for marking obviously incorrect code paths.
+ * It will cause a message with the file name and line number to be printed,
+ * and then cause an oops. The message is actually printed by handle_BUG()
+ * in arch/cris/kernel/traps.c, and the reason we use this method of storing
+ * the file name and line number is that we do not want to affect the registers
+ * by calling printk() before causing the oops.
+ */
+
+#define BUG_PREFIX 0x0D7F
+#define BUG_MAGIC 0x00001234
+
+struct bug_frame {
+ unsigned short prefix;
+ unsigned int magic;
+ unsigned short clear;
+ unsigned short movu;
+ unsigned short line;
+ unsigned short jump;
+ unsigned char *filename;
+};
+
+#if 0
+/* Unfortunately this version of the macro does not work due to a problem
+ * with the compiler (aka a bug) when compiling with -O2, which sometimes
+ * erroneously causes the second input to be stored in a register...
+ */
+#define BUG() \
+ __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
+ "movu.w %0,$r0\n\t" \
+ "jump %1\n\t" \
+ : : "i" (__LINE__), "i" (__FILE__))
+#else
+/* This version will have to do for now, until the compiler is fixed.
+ * The drawbacks of this version are that the file name will appear multiple
+ * times in the .rodata section, and that __LINE__ and __FILE__ can probably
+ * not be used like this with newer versions of gcc.
+ */
+#define BUG() \
+ __asm__ __volatile__ ("clear.d [" __stringify(BUG_MAGIC) "]\n\t"\
+ "movu.w " __stringify(__LINE__) ",$r0\n\t"\
+ "jump 0f\n\t" \
+ ".section .rodata\n" \
+ "0:\t.string \"" __FILE__ "\"\n\t" \
+ ".previous")
+#endif
+
+#else
+
+/* This just causes an oops. */
+#define BUG() (*(int *)0 = 0)
+
+#endif
+
+#define HAVE_ARCH_BUG
+#endif
+
+#include <asm-generic/bug.h>
+
+#endif
extern volatile unsigned long *port_csp0_addr;
extern volatile unsigned long *port_csp4_addr;
-/* macro for setting regs through a shadow -
+/* macro for setting regs through a shadow -
* r = register name (like R_PORT_PA_DATA)
* s = shadow name (like port_pa_data_shadow)
* b = bit number
#undef CONFIG_ETRAX_PA_LEDS
#undef CONFIG_ETRAX_PB_LEDS
#undef CONFIG_ETRAX_CSP0_LEDS
-#define LED_NETWORK_SET_G(x)
-#define LED_NETWORK_SET_R(x)
-#define LED_ACTIVE_SET_G(x)
-#define LED_ACTIVE_SET_R(x)
-#define LED_DISK_WRITE(x)
-#define LED_DISK_READ(x)
+#define CRIS_LED_NETWORK_SET_G(x)
+#define CRIS_LED_NETWORK_SET_R(x)
+#define CRIS_LED_ACTIVE_SET_G(x)
+#define CRIS_LED_ACTIVE_SET_R(x)
+#define CRIS_LED_DISK_WRITE(x)
+#define CRIS_LED_DISK_READ(x)
#endif
#if !defined(CONFIG_ETRAX_CSP0_LEDS)
-#define LED_BIT_SET(x)
-#define LED_BIT_CLR(x)
+#define CRIS_LED_BIT_SET(x)
+#define CRIS_LED_BIT_CLR(x)
#endif
-#define LED_OFF 0x00
-#define LED_GREEN 0x01
-#define LED_RED 0x02
-#define LED_ORANGE (LED_GREEN | LED_RED)
+#define CRIS_LED_OFF 0x00
+#define CRIS_LED_GREEN 0x01
+#define CRIS_LED_RED 0x02
+#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
-#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R
-#define LED_NETWORK_SET(x) \
+#if defined(CONFIG_ETRAX_NO_LEDS)
+#define CRIS_LED_NETWORK_SET(x)
+#else
+#if CONFIG_ETRAX_LED1G == CONFIG_ETRAX_LED1R
+#define CRIS_LED_NETWORK_SET(x) \
do { \
- LED_NETWORK_SET_G((x) & LED_GREEN); \
+ CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
} while (0)
#else
-#define LED_NETWORK_SET(x) \
+#define CRIS_LED_NETWORK_SET(x) \
do { \
- LED_NETWORK_SET_G((x) & LED_GREEN); \
- LED_NETWORK_SET_R((x) & LED_RED); \
+ CRIS_LED_NETWORK_SET_G((x) & CRIS_LED_GREEN); \
+ CRIS_LED_NETWORK_SET_R((x) & CRIS_LED_RED); \
} while (0)
#endif
-#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R
-#define LED_ACTIVE_SET(x) \
+#if CONFIG_ETRAX_LED2G == CONFIG_ETRAX_LED2R
+#define CRIS_LED_ACTIVE_SET(x) \
do { \
- LED_ACTIVE_SET_G((x) & LED_GREEN); \
+ CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
} while (0)
#else
-#define LED_ACTIVE_SET(x) \
+#define CRIS_LED_ACTIVE_SET(x) \
do { \
- LED_ACTIVE_SET_G((x) & LED_GREEN); \
- LED_ACTIVE_SET_R((x) & LED_RED); \
+ CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
+ CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \
} while (0)
#endif
+#endif
#ifdef CONFIG_ETRAX_PA_LEDS
-#define LED_NETWORK_SET_G(x) \
+#define CRIS_LED_NETWORK_SET_G(x) \
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define LED_NETWORK_SET_R(x) \
+#define CRIS_LED_NETWORK_SET_R(x) \
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define LED_ACTIVE_SET_G(x) \
+#define CRIS_LED_ACTIVE_SET_G(x) \
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define LED_ACTIVE_SET_R(x) \
+#define CRIS_LED_ACTIVE_SET_R(x) \
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define LED_DISK_WRITE(x) \
+#define CRIS_LED_DISK_WRITE(x) \
do{\
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
}while(0)
-#define LED_DISK_READ(x) \
- REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, CONFIG_ETRAX_LED3G, !(x))
+#define CRIS_LED_DISK_READ(x) \
+ REG_SHADOW_SET(R_PORT_PA_DATA, port_pa_data_shadow, \
+ CONFIG_ETRAX_LED3G, !(x))
#endif
#ifdef CONFIG_ETRAX_PB_LEDS
-#define LED_NETWORK_SET_G(x) \
+#define CRIS_LED_NETWORK_SET_G(x) \
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define LED_NETWORK_SET_R(x) \
+#define CRIS_LED_NETWORK_SET_R(x) \
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define LED_ACTIVE_SET_G(x) \
+#define CRIS_LED_ACTIVE_SET_G(x) \
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define LED_ACTIVE_SET_R(x) \
+#define CRIS_LED_ACTIVE_SET_R(x) \
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define LED_DISK_WRITE(x) \
+#define CRIS_LED_DISK_WRITE(x) \
do{\
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x));\
REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3R, !(x));\
}while(0)
-#define LED_DISK_READ(x) \
- REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, CONFIG_ETRAX_LED3G, !(x))
+#define CRIS_LED_DISK_READ(x) \
+ REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, \
+ CONFIG_ETRAX_LED3G, !(x))
#endif
#ifdef CONFIG_ETRAX_CSP0_LEDS
(1 << CONFIG_ETRAX_LED10Y ) |(1 << CONFIG_ETRAX_LED11Y )|\
(1 << CONFIG_ETRAX_LED12R ))
-#define LED_NETWORK_SET_G(x) \
+#define CRIS_LED_NETWORK_SET_G(x) \
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1G, !(x))
-#define LED_NETWORK_SET_R(x) \
+#define CRIS_LED_NETWORK_SET_R(x) \
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED1R, !(x))
-#define LED_ACTIVE_SET_G(x) \
+#define CRIS_LED_ACTIVE_SET_G(x) \
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2G, !(x))
-#define LED_ACTIVE_SET_R(x) \
+#define CRIS_LED_ACTIVE_SET_R(x) \
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED2R, !(x))
-#define LED_DISK_WRITE(x) \
+#define CRIS_LED_DISK_WRITE(x) \
do{\
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x));\
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3R, !(x));\
}while(0)
-#define LED_DISK_READ(x) \
+#define CRIS_LED_DISK_READ(x) \
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, CONFIG_ETRAX_LED3G, !(x))
-#define LED_BIT_SET(x)\
+#define CRIS_LED_BIT_SET(x)\
do{\
if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 1);\
}while(0)
-#define LED_BIT_CLR(x)\
+#define CRIS_LED_BIT_CLR(x)\
do{\
if((( 1 << x) & CONFIGURABLE_LEDS) != 0)\
REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, x, 0);\
#endif
/* macros to convert between really physical and virtual addresses
- * by stripping a selected bit, we can convert between KSEG_x and 0x40000000 where
- * the DRAM really resides
+ * by stripping a selected bit, we can convert between KSEG_x and
+ * 0x40000000 where the DRAM really resides
*/
#ifdef CONFIG_CRIS_LOW_MAP
header-y += ptrace.h
header-y += user.h
+header-y += cryptocop.h
#ifndef __ASM_CRIS_ARCH_ATOMIC__
#define __ASM_CRIS_ARCH_ATOMIC__
-#include <asm/system.h>
+#include <linux/spinlock_types.h>
extern void cris_spin_unlock(void *l, int val);
extern void cris_spin_lock(void *l);
#define cris_atomic_save(addr, flags) \
local_irq_save(flags); \
- cris_spin_lock((void*)&cris_atomic_locks[HASH_ADDR(addr)].lock);
+ cris_spin_lock((void *)&cris_atomic_locks[HASH_ADDR(addr)].raw_lock.slock);
#define cris_atomic_restore(addr, flags) \
{ \
spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \
__asm__ volatile ("move.d %1,%0" \
- : "=m" (lock->lock) \
- : "r" (1) \
- : "memory"); \
+ : "=m" (lock->raw_lock.slock) \
+ : "r" (1) \
+ : "memory"); \
local_irq_restore(flags); \
}
--- /dev/null
+#ifndef __ASM_CRISv32_ARCH_BUG_H
+#define __ASM_CRISv32_ARCH_BUG_H
+
+#include <linux/stringify.h>
+
+#ifdef CONFIG_BUG
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+/*
+ * The penalty for the in-band code path will be the size of break 14.
+ * All other stuff is done out-of-band with exception handlers.
+ */
+#define BUG() \
+ __asm__ __volatile__ ("0: break 14\n\t" \
+ ".section .fixup,\"ax\"\n" \
+ "1:\n\t" \
+ "move.d %0, $r10\n\t" \
+ "move.d %1, $r11\n\t" \
+ "jump do_BUG\n\t" \
+ "nop\n\t" \
+ ".previous\n\t" \
+ ".section __ex_table,\"a\"\n\t" \
+ ".dword 0b, 1b\n\t" \
+ ".previous\n\t" \
+ : : "ri" (__FILE__), "i" (__LINE__))
+#else
+#define BUG() __asm__ __volatile__ ("break 14\n\t")
+#endif
+
+#define HAVE_ARCH_BUG
+#endif
+
+#include <asm-generic/bug.h>
+#endif
#ifndef _ASM_CRIS_ARCH_CACHE_H
#define _ASM_CRIS_ARCH_CACHE_H
+#include <asm/arch/hwregs/dma.h>
+
/* A cache-line is 32 bytes. */
#define L1_CACHE_BYTES 32
#define L1_CACHE_SHIFT 5
+void flush_dma_list(dma_descr_data *descr);
+void flush_dma_descr(dma_descr_data *descr, int flush_buf);
+
+#define flush_dma_context(c) \
+ flush_dma_list(phys_to_virt((c)->saved_data));
+
+void cris_flush_cache_range(void *buf, unsigned long len);
+void cris_flush_cache(void);
+
#endif /* _ASM_CRIS_ARCH_CACHE_H */
#ifndef _ASM_CRIS_ARCH_DELAY_H
#define _ASM_CRIS_ARCH_DELAY_H
+extern void cris_delay10ns(u32 n10ns);
+#define udelay(u) cris_delay10ns((u)*100)
+#define ndelay(n) cris_delay10ns(((n)+9)/10)
+
+/*
+ * Not used anymore for udelay or ndelay. Referenced by
+ * e.g. init/calibrate.c. All other references are likely bugs;
+ * should be replaced by mdelay, udelay or ndelay.
+ */
+
static inline void
__delay(int loops)
{
-# $Id: Makefile,v 1.8 2004/01/07 21:16:18 johana Exp $
# Makefile to generate or copy the latest register definitions
# and related datastructures and helpermacros.
# The offical place for these files is at:
-/* $Id: dma.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
- *
+/*
* DMA C definitions and help macros
*
*/
// give stream command
#define DMA_WR_CMD( inst, cmd_par ) \
- do { reg_dma_rw_stream_cmd r = {0}; \
- do { r = REG_RD( dma, inst, rw_stream_cmd ); } while( r.busy ); \
- r.cmd = (cmd_par); \
- REG_WR( dma, inst, rw_stream_cmd, r ); \
- } while( 0 )
+ do { reg_dma_rw_stream_cmd __x = {0}; \
+ do { __x = REG_RD(dma, inst, rw_stream_cmd); } while (__x.busy); \
+ __x.cmd = (cmd_par); \
+ REG_WR(dma, inst, rw_stream_cmd, __x); \
+ } while (0)
// load: g,c,d:burst
#define DMA_START_GROUP( inst, group_descr ) \
/*
* This file is autogenerated from
- * file: ../../inst/eth/rtl/eth_regs.r
- * id: eth_regs.r,v 1.11 2005/02/09 10:48:38 kriskn Exp
- * last modfied: Mon Apr 11 16:07:03 2005
+ * file: eth.r
+ * id: eth_regs.r,v 1.16 2005/05/20 15:41:22 perz Exp
+ * last modfied: Mon Jan 9 06:06:41 2006
*
- * by /n/asic/design/tools/rdesc/src/rdes2c --outfile eth_defs.h ../../inst/eth/rtl/eth_regs.r
- * id: $Id: eth_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ * by /n/asic/design/tools/rdesc/rdes2c eth.r
+ * id: $Id: eth_defs.h,v 1.7 2006/01/26 13:45:30 karljope Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
/* Register rw_ga_lo, scope eth, type rw */
typedef struct {
- unsigned int table : 32;
+ unsigned int tbl : 32;
} reg_eth_rw_ga_lo;
#define REG_RD_ADDR_eth_rw_ga_lo 16
#define REG_WR_ADDR_eth_rw_ga_lo 16
/* Register rw_ga_hi, scope eth, type rw */
typedef struct {
- unsigned int table : 32;
+ unsigned int tbl : 32;
} reg_eth_rw_ga_hi;
#define REG_RD_ADDR_eth_rw_ga_hi 20
#define REG_WR_ADDR_eth_rw_ga_hi 20
/* Register rw_gen_ctrl, scope eth, type rw */
typedef struct {
- unsigned int en : 1;
- unsigned int phy : 2;
- unsigned int protocol : 1;
- unsigned int loopback : 1;
- unsigned int flow_ctrl_dis : 1;
- unsigned int dummy1 : 26;
+ unsigned int en : 1;
+ unsigned int phy : 2;
+ unsigned int protocol : 1;
+ unsigned int loopback : 1;
+ unsigned int flow_ctrl : 1;
+ unsigned int gtxclk_out : 1;
+ unsigned int phyrst_n : 1;
+ unsigned int dummy1 : 24;
} reg_eth_rw_gen_ctrl;
#define REG_RD_ADDR_eth_rw_gen_ctrl 24
#define REG_WR_ADDR_eth_rw_gen_ctrl 24
unsigned int oversize : 1;
unsigned int bad_crc : 1;
unsigned int duplex : 1;
- unsigned int max_size : 1;
- unsigned int dummy1 : 23;
+ unsigned int max_size : 16;
+ unsigned int dummy1 : 8;
} reg_eth_rw_rec_ctrl;
#define REG_RD_ADDR_eth_rw_rec_ctrl 28
#define REG_WR_ADDR_eth_rw_rec_ctrl 28
/* Register rw_tr_ctrl, scope eth, type rw */
typedef struct {
- unsigned int crc : 1;
- unsigned int pad : 1;
- unsigned int retry : 1;
- unsigned int ignore_col : 1;
- unsigned int cancel : 1;
- unsigned int hsh_delay : 1;
- unsigned int ignore_crs : 1;
- unsigned int dummy1 : 25;
+ unsigned int crc : 1;
+ unsigned int pad : 1;
+ unsigned int retry : 1;
+ unsigned int ignore_col : 1;
+ unsigned int cancel : 1;
+ unsigned int hsh_delay : 1;
+ unsigned int ignore_crs : 1;
+ unsigned int carrier_ext : 1;
+ unsigned int dummy1 : 24;
} reg_eth_rw_tr_ctrl;
#define REG_RD_ADDR_eth_rw_tr_ctrl 32
#define REG_WR_ADDR_eth_rw_tr_ctrl 32
/* Register rw_mgm_ctrl, scope eth, type rw */
typedef struct {
- unsigned int mdio : 1;
- unsigned int mdoe : 1;
- unsigned int mdc : 1;
- unsigned int phyclk : 1;
- unsigned int txdata : 4;
- unsigned int txen : 1;
- unsigned int dummy1 : 23;
+ unsigned int mdio : 1;
+ unsigned int mdoe : 1;
+ unsigned int mdc : 1;
+ unsigned int dummy1 : 29;
} reg_eth_rw_mgm_ctrl;
#define REG_RD_ADDR_eth_rw_mgm_ctrl 40
#define REG_WR_ADDR_eth_rw_mgm_ctrl 40
unsigned int mdio : 1;
unsigned int exc_col : 1;
unsigned int urun : 1;
- unsigned int phyclk : 1;
- unsigned int txdata : 4;
- unsigned int txen : 1;
- unsigned int col : 1;
- unsigned int crs : 1;
- unsigned int txclk : 1;
- unsigned int rxdata : 4;
- unsigned int rxer : 1;
- unsigned int rxdv : 1;
- unsigned int rxclk : 1;
- unsigned int dummy1 : 13;
+ unsigned int clk_125 : 1;
+ unsigned int dummy1 : 28;
} reg_eth_r_stat;
#define REG_RD_ADDR_eth_r_stat 44
/* Register rw_intr_mask, scope eth, type rw */
typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int excessive_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
+ unsigned int crc : 1;
+ unsigned int align : 1;
+ unsigned int oversize : 1;
+ unsigned int congestion : 1;
+ unsigned int single_col : 1;
+ unsigned int mult_col : 1;
+ unsigned int late_col : 1;
+ unsigned int deferred : 1;
+ unsigned int carrier_loss : 1;
+ unsigned int sqe_test_err : 1;
+ unsigned int orun : 1;
+ unsigned int urun : 1;
+ unsigned int exc_col : 1;
+ unsigned int mdio : 1;
+ unsigned int dummy1 : 18;
} reg_eth_rw_intr_mask;
#define REG_RD_ADDR_eth_rw_intr_mask 76
#define REG_WR_ADDR_eth_rw_intr_mask 76
/* Register rw_ack_intr, scope eth, type rw */
typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int excessive_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
+ unsigned int crc : 1;
+ unsigned int align : 1;
+ unsigned int oversize : 1;
+ unsigned int congestion : 1;
+ unsigned int single_col : 1;
+ unsigned int mult_col : 1;
+ unsigned int late_col : 1;
+ unsigned int deferred : 1;
+ unsigned int carrier_loss : 1;
+ unsigned int sqe_test_err : 1;
+ unsigned int orun : 1;
+ unsigned int urun : 1;
+ unsigned int exc_col : 1;
+ unsigned int mdio : 1;
+ unsigned int dummy1 : 18;
} reg_eth_rw_ack_intr;
#define REG_RD_ADDR_eth_rw_ack_intr 80
#define REG_WR_ADDR_eth_rw_ack_intr 80
/* Register r_intr, scope eth, type r */
typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int excessive_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
+ unsigned int crc : 1;
+ unsigned int align : 1;
+ unsigned int oversize : 1;
+ unsigned int congestion : 1;
+ unsigned int single_col : 1;
+ unsigned int mult_col : 1;
+ unsigned int late_col : 1;
+ unsigned int deferred : 1;
+ unsigned int carrier_loss : 1;
+ unsigned int sqe_test_err : 1;
+ unsigned int orun : 1;
+ unsigned int urun : 1;
+ unsigned int exc_col : 1;
+ unsigned int mdio : 1;
+ unsigned int dummy1 : 18;
} reg_eth_r_intr;
#define REG_RD_ADDR_eth_r_intr 84
/* Register r_masked_intr, scope eth, type r */
typedef struct {
- unsigned int crc : 1;
- unsigned int align : 1;
- unsigned int oversize : 1;
- unsigned int congestion : 1;
- unsigned int single_col : 1;
- unsigned int mult_col : 1;
- unsigned int late_col : 1;
- unsigned int deferred : 1;
- unsigned int carrier_loss : 1;
- unsigned int sqe_test_err : 1;
- unsigned int orun : 1;
- unsigned int urun : 1;
- unsigned int excessive_col : 1;
- unsigned int mdio : 1;
- unsigned int dummy1 : 18;
+ unsigned int crc : 1;
+ unsigned int align : 1;
+ unsigned int oversize : 1;
+ unsigned int congestion : 1;
+ unsigned int single_col : 1;
+ unsigned int mult_col : 1;
+ unsigned int late_col : 1;
+ unsigned int deferred : 1;
+ unsigned int carrier_loss : 1;
+ unsigned int sqe_test_err : 1;
+ unsigned int orun : 1;
+ unsigned int urun : 1;
+ unsigned int exc_col : 1;
+ unsigned int mdio : 1;
+ unsigned int dummy1 : 18;
} reg_eth_r_masked_intr;
#define REG_RD_ADDR_eth_r_masked_intr 88
regk_eth_discard = 0x00000000,
regk_eth_ether = 0x00000000,
regk_eth_full = 0x00000001,
+ regk_eth_gmii = 0x00000003,
+ regk_eth_gtxclk = 0x00000001,
regk_eth_half = 0x00000000,
regk_eth_hsh = 0x00000001,
regk_eth_mii = 0x00000001,
+ regk_eth_mii_arec = 0x00000002,
regk_eth_mii_clk = 0x00000000,
- regk_eth_mii_rec = 0x00000002,
regk_eth_no = 0x00000000,
+ regk_eth_phyrst = 0x00000000,
regk_eth_rec = 0x00000001,
regk_eth_rw_ga_hi_default = 0x00000000,
regk_eth_rw_ga_lo_default = 0x00000000,
regk_eth_rw_ma1_lo_default = 0x00000000,
regk_eth_rw_mgm_ctrl_default = 0x00000000,
regk_eth_rw_test_ctrl_default = 0x00000000,
- regk_eth_size1518 = 0x00000000,
- regk_eth_size1522 = 0x00000001,
+ regk_eth_size1518 = 0x000005ee,
+ regk_eth_size1522 = 0x000005f2,
regk_eth_yes = 0x00000001
};
#endif /* __eth_defs_h */
-/* $Id: reg_rdwr.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
- *
+/*
* Read/write register macros used by *_defs.h
*/
#ifndef reg_rdwr_h
#define reg_rdwr_h
+#ifndef REG_READ
+#define REG_READ(type, addr) (*((volatile type *) (addr)))
+#endif
-#define REG_READ(type, addr) *((volatile type *) (addr))
-
+#ifndef REG_WRITE
#define REG_WRITE(type, addr, val) \
do { *((volatile type *) (addr)) = (val); } while(0)
+#endif
#endif
#ifndef _ASM_ARCH_CRIS_IO_H
#define _ASM_ARCH_CRIS_IO_H
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/gio_defs.h>
+#include <linux/spinlock.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/gio_defs.h>
enum crisv32_io_dir
{
struct crisv32_ioport
{
- unsigned long* oe;
- unsigned long* data;
- unsigned long* data_in;
+ volatile unsigned long *oe;
+ volatile unsigned long *data;
+ volatile unsigned long *data_in;
unsigned int pin_count;
+ spinlock_t lock;
};
struct crisv32_iopin
extern struct crisv32_iopin crisv32_led3_green;
extern struct crisv32_iopin crisv32_led3_red;
-static inline void crisv32_io_set(struct crisv32_iopin* iopin,
- int val)
+extern struct crisv32_iopin crisv32_led_net0_green;
+extern struct crisv32_iopin crisv32_led_net0_red;
+extern struct crisv32_iopin crisv32_led_net1_green;
+extern struct crisv32_iopin crisv32_led_net1_red;
+
+static inline void crisv32_io_set(struct crisv32_iopin *iopin, int val)
{
+ long flags;
+ spin_lock_irqsave(&iopin->port->lock, flags);
+
if (val)
*iopin->port->data |= iopin->bit;
else
*iopin->port->data &= ~iopin->bit;
+
+ spin_unlock_irqrestore(&iopin->port->lock, flags);
}
static inline void crisv32_io_set_dir(struct crisv32_iopin* iopin,
enum crisv32_io_dir dir)
{
+ long flags;
+ spin_lock_irqsave(&iopin->port->lock, flags);
+
if (dir == crisv32_io_dir_in)
*iopin->port->oe &= ~iopin->bit;
else
*iopin->port->oe |= iopin->bit;
+
+ spin_unlock_irqrestore(&iopin->port->lock, flags);
}
static inline int crisv32_io_rd(struct crisv32_iopin* iopin)
int crisv32_io_get(struct crisv32_iopin* iopin,
unsigned int port, unsigned int pin);
int crisv32_io_get_name(struct crisv32_iopin* iopin,
- char* name);
+ const char *name);
-#define LED_OFF 0x00
-#define LED_GREEN 0x01
-#define LED_RED 0x02
-#define LED_ORANGE (LED_GREEN | LED_RED)
+#define CRIS_LED_OFF 0x00
+#define CRIS_LED_GREEN 0x01
+#define CRIS_LED_RED 0x02
+#define CRIS_LED_ORANGE (CRIS_LED_GREEN | CRIS_LED_RED)
-#define LED_NETWORK_SET(x) \
- do { \
- LED_NETWORK_SET_G((x) & LED_GREEN); \
- LED_NETWORK_SET_R((x) & LED_RED); \
+#if (defined(CONFIG_ETRAX_NBR_LED_GRP_ONE) || defined(CONFIG_ETRAX_NBR_LED_GRP_TWO))
+#define CRIS_LED_NETWORK_GRP0_SET(x) \
+ do { \
+ CRIS_LED_NETWORK_GRP0_SET_G((x) & CRIS_LED_GREEN); \
+ CRIS_LED_NETWORK_GRP0_SET_R((x) & CRIS_LED_RED); \
} while (0)
-#define LED_ACTIVE_SET(x) \
+#else
+#define CRIS_LED_NETWORK_GRP0_SET(x) while (0) {}
+#endif
+
+#define CRIS_LED_NETWORK_GRP0_SET_G(x) \
+ crisv32_io_set(&crisv32_led_net0_green, !(x));
+
+#define CRIS_LED_NETWORK_GRP0_SET_R(x) \
+ crisv32_io_set(&crisv32_led_net0_red, !(x));
+
+#if defined(CONFIG_ETRAX_NBR_LED_GRP_TWO)
+#define CRIS_LED_NETWORK_GRP1_SET(x) \
+ do { \
+ CRIS_LED_NETWORK_GRP1_SET_G((x) & CRIS_LED_GREEN); \
+ CRIS_LED_NETWORK_GRP1_SET_R((x) & CRIS_LED_RED); \
+ } while (0)
+#else
+#define CRIS_LED_NETWORK_GRP1_SET(x) while (0) {}
+#endif
+
+#define CRIS_LED_NETWORK_GRP1_SET_G(x) \
+ crisv32_io_set(&crisv32_led_net1_green, !(x));
+
+#define CRIS_LED_NETWORK_GRP1_SET_R(x) \
+ crisv32_io_set(&crisv32_led_net1_red, !(x));
+
+#define CRIS_LED_ACTIVE_SET(x) \
do { \
- LED_ACTIVE_SET_G((x) & LED_GREEN); \
- LED_ACTIVE_SET_R((x) & LED_RED); \
+ CRIS_LED_ACTIVE_SET_G((x) & CRIS_LED_GREEN); \
+ CRIS_LED_ACTIVE_SET_R((x) & CRIS_LED_RED); \
} while (0)
-#define LED_NETWORK_SET_G(x) \
- crisv32_io_set(&crisv32_led1_green, !(x));
-#define LED_NETWORK_SET_R(x) \
- crisv32_io_set(&crisv32_led1_red, !(x));
-#define LED_ACTIVE_SET_G(x) \
+#define CRIS_LED_ACTIVE_SET_G(x) \
crisv32_io_set(&crisv32_led2_green, !(x));
-#define LED_ACTIVE_SET_R(x) \
+#define CRIS_LED_ACTIVE_SET_R(x) \
crisv32_io_set(&crisv32_led2_red, !(x));
-#define LED_DISK_WRITE(x) \
+#define CRIS_LED_DISK_WRITE(x) \
do{\
crisv32_io_set(&crisv32_led3_green, !(x)); \
crisv32_io_set(&crisv32_led3_red, !(x)); \
}while(0)
-#define LED_DISK_READ(x) \
+#define CRIS_LED_DISK_READ(x) \
crisv32_io_set(&crisv32_led3_green, !(x));
#endif
#ifndef _ASM_ARCH_IRQ_H
#define _ASM_ARCH_IRQ_H
-#include "hwregs/intr_vect.h"
+#include <hwregs/intr_vect.h>
/* Number of non-cpu interrupts. */
-#define NR_IRQS 0x50 /* Exceptions + IRQs */
-#define NR_REAL_IRQS 0x20 /* IRQs */
+#define NR_IRQS NBR_INTR_VECT /* Exceptions + IRQs */
#define FIRST_IRQ 0x31 /* Exception number for first IRQ */
+#define NR_REAL_IRQS (NBR_INTR_VECT - FIRST_IRQ) /* IRQs */
+#if NR_REAL_IRQS > 32
+#define MACH_IRQS 64
+#else
+#define MACH_IRQS 32
+#endif
#ifndef __ASSEMBLY__
/* Global IRQ vector. */
* which will acknowledge the interrupt, is run. The actual blocking is made
* by crisv32_do_IRQ.
*/
-#define BUILD_IRQ(nr, mask) \
+#define BUILD_IRQ(nr) \
void IRQ_NAME(nr); \
__asm__ ( \
".text\n\t" \
SAVE_ALL \
KGDB_FIXUP \
"move.d "#nr",$r10\n\t" \
- "move.d $sp,$r12\n\t" \
+ "move.d $sp, $r12\n\t" \
"jsr crisv32_do_IRQ\n\t" \
"moveq 1, $r11\n\t" \
"jump ret_from_intr\n\t" \
+++ /dev/null
-#ifndef _ASM_JULIETTE_H
-#define _ASM_JULIETTE_H
-
-/* juliette _IOC_TYPE, bits 8 to 15 in ioctl cmd */
-
-#define JULIOCTYPE 42
-
-/* supported ioctl _IOC_NR's */
-
-#define JULSTARTDMA 0x1 /* start a picture asynchronously */
-
-/* set parameters */
-
-#define SETDEFAULT 0x2 /* CCD/VIDEO/SS1M */
-#define SETPARAMETERS 0x3 /* CCD/VIDEO */
-#define SETSIZE 0x4 /* CCD/VIDEO/SS1M */
-#define SETCOMPRESSION 0x5 /* CCD/VIDEO/SS1M */
-#define SETCOLORLEVEL 0x6 /* CCD/VIDEO */
-#define SETBRIGHTNESS 0x7 /* CCD */
-#define SETROTATION 0x8 /* CCD */
-#define SETTEXT 0x9 /* CCD/VIDEO/SS1M */
-#define SETCLOCK 0xa /* CCD/VIDEO/SS1M */
-#define SETDATE 0xb /* CCD/VIDEO/SS1M */
-#define SETTIMEFORMAT 0xc /* CCD/VIDEO/SS1M */
-#define SETDATEFORMAT 0xd /* VIDEO */
-#define SETTEXTALIGNMENT 0xe /* VIDEO */
-#define SETFPS 0xf /* CCD/VIDEO/SS1M */
-#define SETVGA 0xff /* VIDEO */
-#define SETCOMMENT 0xfe /* CCD/VIDEO */
-
-/* get parameters */
-
-#define GETDRIVERTYPE 0x10 /* CCD/VIDEO/SS1M */
-#define GETNBROFCAMERAS 0x11 /* CCD/VIDEO/SS1M */
-#define GETPARAMETERS 0x12 /* CCD/VIDEO/SS1M */
-#define GETBUFFERSIZE 0x13 /* CCD/VIDEO/SS1M */
-#define GETVIDEOTYPE 0x14 /* VIDEO/SS1M */
-#define GETVIDEOSIGNAL 0x15 /* VIDEO */
-#define GETMODULATION 0x16 /* VIDEO */
-#define GETDCYVALUES 0xa0 /* CCD /SS1M */
-#define GETDCYWIDTH 0xa1 /* CCD /SS1M */
-#define GETDCYHEIGHT 0xa2 /* CCD /SS1M */
-#define GETSIZE 0xa3 /* CCD/VIDEO */
-#define GETCOMPRESSION 0xa4 /* CCD/VIDEO */
-
-/* detect and get parameters */
-
-#define DETECTMODULATION 0x17 /* VIDEO */
-#define DETECTVIDEOTYPE 0x18 /* VIDEO */
-#define DETECTVIDEOSIGNAL 0x19 /* VIDEO */
-
-/* configure default parameters */
-
-#define CONFIGUREDEFAULT 0x20 /* CCD/VIDEO/SS1M */
-#define DEFSIZE 0x21 /* CCD/VIDEO/SS1M */
-#define DEFCOMPRESSION 0x22 /* CCD/VIDEO/SS1M */
-#define DEFCOLORLEVEL 0x23 /* CCD/VIDEO */
-#define DEFBRIGHTNESS 0x24 /* CCD */
-#define DEFROTATION 0x25 /* CCD */
-#define DEFWHITEBALANCE 0x26 /* CCD */
-#define DEFEXPOSURE 0x27 /* CCD */
-#define DEFAUTOEXPWINDOW 0x28 /* CCD */
-#define DEFTEXT 0x29 /* CCD/VIDEO/SS1M */
-#define DEFCLOCK 0x2a /* CCD/VIDEO/SS1M */
-#define DEFDATE 0x2b /* CCD/VIDEO/SS1M */
-#define DEFTIMEFORMAT 0x2c /* CCD/VIDEO/SS1M */
-#define DEFDATEFORMAT 0x2d /* VIDEO */
-#define DEFTEXTALIGNMENT 0x2e /* VIDEO */
-#define DEFFPS 0x2f /* CCD/VIDEO/SS1M */
-#define DEFTEXTSTRING 0x30 /* CCD/VIDEO/SS1M */
-#define DEFHEADERINFO 0x31 /* CCD/VIDEO/SS1M */
-#define DEFWEXAR 0x32 /* CCD */
-#define DEFLINEDELAY 0x33 /* CCD */
-#define DEFDISABLEDVIDEO 0x34 /* VIDEO */
-#define DEFVIDEOTYPE 0x35 /* VIDEO */
-#define DEFMODULATION 0x36 /* VIDEO */
-#define DEFXOFFSET 0x37 /* VIDEO */
-#define DEFYOFFSET 0x38 /* VIDEO */
-#define DEFYCMODE 0x39 /* VIDEO */
-#define DEFVCRMODE 0x3a /* VIDEO */
-#define DEFSTOREDCYVALUES 0x3b /* CCD/VIDEO/SS1M */
-#define DEFWCDS 0x3c /* CCD */
-#define DEFVGA 0x3d /* VIDEO */
-#define DEFCOMMENT 0x3e /* CCD/VIDEO */
-#define DEFCOMMENTSIZE 0x3f /* CCD/VIDEO */
-#define DEFCOMMENTTEXT 0x50 /* CCD/VIDEO */
-#define DEFSTOREDCYTEXT 0x51 /* VIDEO */
-
-
-#define JULABORTDMA 0x70 /* Abort current DMA transfer */
-
-/* juliette general i/o port */
-
-#define JIO_READBITS 0x40 /* read and return current port bits */
-#define JIO_SETBITS 0x41 /* set bits marked by 1 in the argument */
-#define JIO_CLRBITS 0x42 /* clr bits marked by 1 in the argument */
-#define JIO_READDIR 0x43 /* read direction, 0=input 1=output */
-#define JIO_SETINPUT 0x44 /* set direction, 0=unchanged 1=input
- returns current dir */
-#define JIO_SETOUTPUT 0x45 /* set direction, 0=unchanged 1=output
- returns current dir */
-
-/**** YumYum internal adresses ****/
-
-/* Juliette buffer addresses */
-
-#define BUFFER1_VIDEO 0x1100
-#define BUFFER2_VIDEO 0x2800
-#define ACDC_BUFF_VIDEO 0x0aaa
-#define BUFFER1 0x1700
-#define BUFFER2 0x2b01
-#define ACDC_BUFFER 0x1200
-#define BUFFER1_SS1M 0x1100
-#define BUFFER2_SS1M 0x2800
-#define ACDC_BUFF_SS1M 0x0900
-
-/* Juliette parameter memory addresses */
-
-#define PA_BUFFER_CNT 0x3f09 /* CCD/VIDEO */
-#define PA_CCD_BUFFER 0x3f10 /* CCD */
-#define PA_VIDEO_BUFFER 0x3f10 /* VIDEO */
-#define PA_DCT_BUFFER 0x3f11 /* CCD/VIDEO */
-#define PA_TEMP 0x3f12 /* CCD/VIDEO */
-#define PA_VIDEOLINE_RD 0x3f13 /* VIDEO */
-#define PA_VIDEOLINE_WR 0x3f14 /* VIDEO */
-#define PA_VI_HDELAY0 0x3f15 /* VIDEO */
-#define PA_VI_VDELAY0 0x3f16 /* VIDEO */
-#define PA_VI_HDELAY1 0x3f17 /* VIDEO */
-#define PA_VI_VDELAY1 0x3f18 /* VIDEO */
-#define PA_VI_HDELAY2 0x3f19 /* VIDEO */
-#define PA_VI_VDELAY2 0x3f1a /* VIDEO */
-#define PA_VI_HDELAY3 0x3f1b /* VIDEO */
-#define PA_VI_VDELAY3 0x3f1c /* VIDEO */
-#define PA_VI_CTRL 0x3f20 /* VIDEO */
-#define PA_JPEG_CTRL 0x3f22 /* CCD/VIDEO */
-#define PA_BUFFER_SIZE 0x3f24 /* CCD/VIDEO */
-#define PA_PAL_NTSC 0x3f25 /* VIDEO */
-#define PA_MACROBLOCKS 0x3f26 /* CCD/VIDEO */
-#define PA_COLOR 0x3f27 /* VIDEO */
-#define PA_MEMCH1CNT2 0x3f28 /* CCD/VIDEO */
-#define PA_MEMCH1CNT3 0x3f29 /* VIDEO */
-#define PA_MEMCH1STR2 0x3f2a /* CCD/VIDEO */
-#define PA_MEMCH1STR3 0x3f2b /* VIDEO */
-#define PA_BUFFERS 0x3f2c /* CCD/VIDEO */
-#define PA_PROGRAM 0x3f2d /* CCD/VIDEO */
-#define PA_ROTATION 0x3f2e /* CCD */
-#define PA_PC 0x3f30 /* CCD/VIDEO */
-#define PA_PC2 0x3f31 /* VIDEO */
-#define PA_ODD_LINE 0x3f32 /* VIDEO */
-#define PA_EXP_DELAY 0x3f34 /* CCD */
-#define PA_MACROBLOCK_CNT 0x3f35 /* CCD/VIDEO */
-#define PA_DRAM_PTR1_L 0x3f36 /* CCD/VIDEO */
-#define PA_CLPOB_CNT 0x3f37 /* CCD */
-#define PA_DRAM_PTR1_H 0x3f38 /* CCD/VIDEO */
-#define PA_DRAM_PTR2_L 0x3f3a /* VIDEO */
-#define PA_DRAM_PTR2_H 0x3f3c /* VIDEO */
-#define PA_CCD_LINE_CNT 0x3f3f /* CCD */
-#define PA_VIDEO_LINE_CNT 0x3f3f /* VIDEO */
-#define PA_TEXT 0x3f41 /* CCD/VIDEO */
-#define PA_CAMERA_CHANGED 0x3f42 /* VIDEO */
-#define PA_TEXTALIGNMENT 0x3f43 /* VIDEO */
-#define PA_DISABLED 0x3f44 /* VIDEO */
-#define PA_MACROBLOCKTEXT 0x3f45 /* VIDEO */
-#define PA_VGA 0x3f46 /* VIDEO */
-#define PA_ZERO 0x3ffe /* VIDEO */
-#define PA_NULL 0x3fff /* CCD/VIDEO */
-
-typedef enum {
- jpeg = 0,
- dummy = 1
-} request_type;
-
-typedef enum {
- hugesize = 0,
- fullsize = 1,
- halfsize = 2,
- fieldsize = 3
-} size_type;
-
-typedef enum {
- min = 0,
- low = 1,
- medium = 2,
- high = 3,
- very_high = 4,
- very_low = 5,
- q1 = 6,
- q2 = 7,
- q3 = 8,
- q4 = 9,
- q5 = 10,
- q6 = 11
-} compr_type;
-
-typedef enum {
- deg_0 = 0,
- deg_180 = 1,
- deg_90 = 2,
- deg_270 = 3
-} rotation_type;
-
-typedef enum {
- auto_white = 0,
- hold = 1,
- fixed_outdoor = 2,
- fixed_indoor = 3,
- fixed_fluor = 4
-} white_balance_type;
-
-typedef enum {
- auto_exp = 0,
- fixed_exp = 1
-} exposure_type;
-
-typedef enum {
- no_window = 0,
- center = 1,
- top = 2,
- lower = 3,
- left = 4,
- right = 5,
- spot = 6,
- cw = 7
-} exp_window_type;
-
-typedef enum {
- h_24 = 0,
- h_12 = 1,
- h_24P = 2
-} hour_type;
-
-typedef enum {
- standard = 0,
- YYYY_MM_DD = 1,
- Www_Mmm_DD_YYYY = 2,
- Www_DD_MM_YYYY = 3
-} date_type;
-
-typedef enum {
- left_align = 0,
- center_align = 1,
- right_align = 2
-} alignment_type;
-
-typedef enum {
- off = 0,
- on = 1,
- no = 0,
- yes = 1
-} enable_type;
-
-typedef enum {
- disabled = 0,
- enabled = 1,
- extended = 2
-} comment_type;
-
-typedef enum {
- pal = 0,
- ntsc = 1
-} video_type;
-
-typedef enum {
- pal_bghi_ntsc_m = 0,
- ntsc_4_43_50hz_pal_4_43_60hz = 1,
- pal_n_ntsc_4_43_60hz = 2,
- ntsc_n_pal_m = 3,
- secam_pal_4_43_60hz = 4
-} modulation_type;
-
-typedef enum {
- cam0 = 0,
- cam1 = 1,
- cam2 = 2,
- cam3 = 3,
- quad = 32
-} camera_type;
-
-typedef enum {
- video_driver = 0,
- ccd_driver = 1
-} driver_type;
-
-struct jul_param {
- request_type req_type;
- size_type size;
- compr_type compression;
- rotation_type rotation;
- int color_level;
- int brightness;
- white_balance_type white_balance;
- exposure_type exposure;
- exp_window_type auto_exp_window;
- hour_type time_format;
- date_type date_format;
- alignment_type text_alignment;
- enable_type text;
- enable_type clock;
- enable_type date;
- enable_type fps;
- enable_type vga;
- enable_type comment;
-};
-
-struct video_param {
- enable_type disabled;
- modulation_type modulation;
- video_type video;
- enable_type signal;
- enable_type vcr;
- int xoffset;
- int yoffset;
-};
-
-/* The juliette_request structure is used during the JULSTARTDMA asynchronous
- * picture-taking ioctl call as an argument to specify a buffer which will get
- * the final picture.
- */
-
-struct juliette_request {
- char *buf; /* Pointer to the buffer to hold picture data */
- unsigned int buflen; /* Length of the above buffer */
- unsigned int size; /* Resulting length, 0 if the picture is not ready */
-};
-
-#endif
--- /dev/null
+#ifndef _ASM_CRIS_ARCH_ARBITER_H
+#define _ASM_CRIS_ARCH_ARBITER_H
+
+#define EXT_REGION 0
+#define INT_REGION 1
+
+typedef void (watch_callback)(void);
+
+enum {
+ arbiter_all_dmas = 0x7fe,
+ arbiter_cpu = 0x1800,
+ arbiter_all_clients = 0x7fff
+};
+
+enum {
+ arbiter_bar_all_clients = 0x1ff
+};
+
+enum {
+ arbiter_all_read = 0x55,
+ arbiter_all_write = 0xaa,
+ arbiter_all_accesses = 0xff
+};
+
+#define MARB_CLIENTS(foo_cli, bar_cli) (((bar_cli) << 16) | (foo_cli))
+
+int crisv32_arbiter_allocate_bandwidth(int client, int region,
+ unsigned long bandwidth);
+int crisv32_arbiter_watch(unsigned long start, unsigned long size,
+ unsigned long clients, unsigned long accesses,
+ watch_callback * cb);
+int crisv32_arbiter_unwatch(int id);
+
+#endif
--- /dev/null
+#ifndef _ASM_ARCH_CRIS_DMA_H
+#define _ASM_ARCH_CRIS_DMA_H
+
+/* Defines for using and allocating dma channels. */
+
+#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */
+
+enum dma_owner {
+ dma_eth,
+ dma_ser0,
+ dma_ser1,
+ dma_ser2,
+ dma_ser3,
+ dma_ser4,
+ dma_iop,
+ dma_sser,
+ dma_strp,
+ dma_h264,
+ dma_jpeg
+};
+
+int crisv32_request_dma(unsigned int dmanr, const char *device_id,
+ unsigned options, unsigned bandwidth, enum dma_owner owner);
+void crisv32_free_dma(unsigned int dmanr);
+
+/* Masks used by crisv32_request_dma options: */
+#define DMA_VERBOSE_ON_ERROR 1
+#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
+#define DMA_INT_MEM 4
+
+#endif /* _ASM_ARCH_CRIS_DMA_H */
--- /dev/null
+#ifndef __clkgen_defs_asm_h
+#define __clkgen_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: clkgen.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile clkgen_defs_asm.h clkgen.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register r_bootsel, scope clkgen, type r */
+#define reg_clkgen_r_bootsel___boot_mode___lsb 0
+#define reg_clkgen_r_bootsel___boot_mode___width 5
+#define reg_clkgen_r_bootsel___intern_main_clk___lsb 5
+#define reg_clkgen_r_bootsel___intern_main_clk___width 1
+#define reg_clkgen_r_bootsel___intern_main_clk___bit 5
+#define reg_clkgen_r_bootsel___extern_usb2_clk___lsb 6
+#define reg_clkgen_r_bootsel___extern_usb2_clk___width 1
+#define reg_clkgen_r_bootsel___extern_usb2_clk___bit 6
+#define reg_clkgen_r_bootsel_offset 0
+
+/* Register rw_clk_ctrl, scope clkgen, type rw */
+#define reg_clkgen_rw_clk_ctrl___pll___lsb 0
+#define reg_clkgen_rw_clk_ctrl___pll___width 1
+#define reg_clkgen_rw_clk_ctrl___pll___bit 0
+#define reg_clkgen_rw_clk_ctrl___cpu___lsb 1
+#define reg_clkgen_rw_clk_ctrl___cpu___width 1
+#define reg_clkgen_rw_clk_ctrl___cpu___bit 1
+#define reg_clkgen_rw_clk_ctrl___iop_usb___lsb 2
+#define reg_clkgen_rw_clk_ctrl___iop_usb___width 1
+#define reg_clkgen_rw_clk_ctrl___iop_usb___bit 2
+#define reg_clkgen_rw_clk_ctrl___vin___lsb 3
+#define reg_clkgen_rw_clk_ctrl___vin___width 1
+#define reg_clkgen_rw_clk_ctrl___vin___bit 3
+#define reg_clkgen_rw_clk_ctrl___sclr___lsb 4
+#define reg_clkgen_rw_clk_ctrl___sclr___width 1
+#define reg_clkgen_rw_clk_ctrl___sclr___bit 4
+#define reg_clkgen_rw_clk_ctrl___h264___lsb 5
+#define reg_clkgen_rw_clk_ctrl___h264___width 1
+#define reg_clkgen_rw_clk_ctrl___h264___bit 5
+#define reg_clkgen_rw_clk_ctrl___ddr2___lsb 6
+#define reg_clkgen_rw_clk_ctrl___ddr2___width 1
+#define reg_clkgen_rw_clk_ctrl___ddr2___bit 6
+#define reg_clkgen_rw_clk_ctrl___vout_hist___lsb 7
+#define reg_clkgen_rw_clk_ctrl___vout_hist___width 1
+#define reg_clkgen_rw_clk_ctrl___vout_hist___bit 7
+#define reg_clkgen_rw_clk_ctrl___eth___lsb 8
+#define reg_clkgen_rw_clk_ctrl___eth___width 1
+#define reg_clkgen_rw_clk_ctrl___eth___bit 8
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___lsb 9
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___width 1
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_200___bit 9
+#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___lsb 10
+#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___width 1
+#define reg_clkgen_rw_clk_ctrl___dma0_1_eth___bit 10
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___lsb 11
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___width 1
+#define reg_clkgen_rw_clk_ctrl___ccd_tg_100___bit 11
+#define reg_clkgen_rw_clk_ctrl___jpeg___lsb 12
+#define reg_clkgen_rw_clk_ctrl___jpeg___width 1
+#define reg_clkgen_rw_clk_ctrl___jpeg___bit 12
+#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___lsb 13
+#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___width 1
+#define reg_clkgen_rw_clk_ctrl___sser_ser_dma6_7___bit 13
+#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___lsb 14
+#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___width 1
+#define reg_clkgen_rw_clk_ctrl___strdma0_2_video___bit 14
+#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___lsb 15
+#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___width 1
+#define reg_clkgen_rw_clk_ctrl___dma2_3_strcop___bit 15
+#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___lsb 16
+#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___width 1
+#define reg_clkgen_rw_clk_ctrl___dma4_5_iop___bit 16
+#define reg_clkgen_rw_clk_ctrl___dma9_11___lsb 17
+#define reg_clkgen_rw_clk_ctrl___dma9_11___width 1
+#define reg_clkgen_rw_clk_ctrl___dma9_11___bit 17
+#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___lsb 18
+#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___width 1
+#define reg_clkgen_rw_clk_ctrl___memarb_bar_ddr___bit 18
+#define reg_clkgen_rw_clk_ctrl___sclr_h264___lsb 19
+#define reg_clkgen_rw_clk_ctrl___sclr_h264___width 1
+#define reg_clkgen_rw_clk_ctrl___sclr_h264___bit 19
+#define reg_clkgen_rw_clk_ctrl_offset 4
+
+
+/* Constants */
+#define regk_clkgen_eth1000_rx 0x0000000c
+#define regk_clkgen_eth1000_tx 0x0000000e
+#define regk_clkgen_eth100_rx 0x0000001d
+#define regk_clkgen_eth100_rx_half 0x0000001c
+#define regk_clkgen_eth100_tx 0x0000001f
+#define regk_clkgen_eth100_tx_half 0x0000001e
+#define regk_clkgen_nand_3_2 0x00000000
+#define regk_clkgen_nand_3_2_0x30 0x00000002
+#define regk_clkgen_nand_3_2_0x30_pll 0x00000012
+#define regk_clkgen_nand_3_2_pll 0x00000010
+#define regk_clkgen_nand_3_3 0x00000001
+#define regk_clkgen_nand_3_3_0x30 0x00000003
+#define regk_clkgen_nand_3_3_0x30_pll 0x00000013
+#define regk_clkgen_nand_3_3_pll 0x00000011
+#define regk_clkgen_nand_4_2 0x00000004
+#define regk_clkgen_nand_4_2_0x30 0x00000006
+#define regk_clkgen_nand_4_2_0x30_pll 0x00000016
+#define regk_clkgen_nand_4_2_pll 0x00000014
+#define regk_clkgen_nand_4_3 0x00000005
+#define regk_clkgen_nand_4_3_0x30 0x00000007
+#define regk_clkgen_nand_4_3_0x30_pll 0x00000017
+#define regk_clkgen_nand_4_3_pll 0x00000015
+#define regk_clkgen_nand_5_2 0x00000008
+#define regk_clkgen_nand_5_2_0x30 0x0000000a
+#define regk_clkgen_nand_5_2_0x30_pll 0x0000001a
+#define regk_clkgen_nand_5_2_pll 0x00000018
+#define regk_clkgen_nand_5_3 0x00000009
+#define regk_clkgen_nand_5_3_0x30 0x0000000b
+#define regk_clkgen_nand_5_3_0x30_pll 0x0000001b
+#define regk_clkgen_nand_5_3_pll 0x00000019
+#define regk_clkgen_no 0x00000000
+#define regk_clkgen_rw_clk_ctrl_default 0x00000002
+#define regk_clkgen_ser 0x0000000d
+#define regk_clkgen_ser_pll 0x0000000f
+#define regk_clkgen_yes 0x00000001
+#endif /* __clkgen_defs_asm_h */
--- /dev/null
+#ifndef __ddr2_defs_asm_h
+#define __ddr2_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: ddr2.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile ddr2_defs_asm.h ddr2.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_cfg, scope ddr2, type rw */
+#define reg_ddr2_rw_cfg___col_width___lsb 0
+#define reg_ddr2_rw_cfg___col_width___width 4
+#define reg_ddr2_rw_cfg___nr_banks___lsb 4
+#define reg_ddr2_rw_cfg___nr_banks___width 1
+#define reg_ddr2_rw_cfg___nr_banks___bit 4
+#define reg_ddr2_rw_cfg___bw___lsb 5
+#define reg_ddr2_rw_cfg___bw___width 1
+#define reg_ddr2_rw_cfg___bw___bit 5
+#define reg_ddr2_rw_cfg___nr_ref___lsb 6
+#define reg_ddr2_rw_cfg___nr_ref___width 4
+#define reg_ddr2_rw_cfg___ref_interval___lsb 10
+#define reg_ddr2_rw_cfg___ref_interval___width 11
+#define reg_ddr2_rw_cfg___odt_ctrl___lsb 21
+#define reg_ddr2_rw_cfg___odt_ctrl___width 2
+#define reg_ddr2_rw_cfg___odt_mem___lsb 23
+#define reg_ddr2_rw_cfg___odt_mem___width 1
+#define reg_ddr2_rw_cfg___odt_mem___bit 23
+#define reg_ddr2_rw_cfg___imp_strength___lsb 24
+#define reg_ddr2_rw_cfg___imp_strength___width 1
+#define reg_ddr2_rw_cfg___imp_strength___bit 24
+#define reg_ddr2_rw_cfg___auto_imp_cal___lsb 25
+#define reg_ddr2_rw_cfg___auto_imp_cal___width 1
+#define reg_ddr2_rw_cfg___auto_imp_cal___bit 25
+#define reg_ddr2_rw_cfg___imp_cal_override___lsb 26
+#define reg_ddr2_rw_cfg___imp_cal_override___width 1
+#define reg_ddr2_rw_cfg___imp_cal_override___bit 26
+#define reg_ddr2_rw_cfg___dll_override___lsb 27
+#define reg_ddr2_rw_cfg___dll_override___width 1
+#define reg_ddr2_rw_cfg___dll_override___bit 27
+#define reg_ddr2_rw_cfg_offset 0
+
+/* Register rw_timing, scope ddr2, type rw */
+#define reg_ddr2_rw_timing___wr___lsb 0
+#define reg_ddr2_rw_timing___wr___width 3
+#define reg_ddr2_rw_timing___rcd___lsb 3
+#define reg_ddr2_rw_timing___rcd___width 3
+#define reg_ddr2_rw_timing___rp___lsb 6
+#define reg_ddr2_rw_timing___rp___width 3
+#define reg_ddr2_rw_timing___ras___lsb 9
+#define reg_ddr2_rw_timing___ras___width 4
+#define reg_ddr2_rw_timing___rfc___lsb 13
+#define reg_ddr2_rw_timing___rfc___width 7
+#define reg_ddr2_rw_timing___rc___lsb 20
+#define reg_ddr2_rw_timing___rc___width 5
+#define reg_ddr2_rw_timing___rtp___lsb 25
+#define reg_ddr2_rw_timing___rtp___width 2
+#define reg_ddr2_rw_timing___rtw___lsb 27
+#define reg_ddr2_rw_timing___rtw___width 3
+#define reg_ddr2_rw_timing___wtr___lsb 30
+#define reg_ddr2_rw_timing___wtr___width 2
+#define reg_ddr2_rw_timing_offset 4
+
+/* Register rw_latency, scope ddr2, type rw */
+#define reg_ddr2_rw_latency___cas___lsb 0
+#define reg_ddr2_rw_latency___cas___width 3
+#define reg_ddr2_rw_latency___additive___lsb 3
+#define reg_ddr2_rw_latency___additive___width 3
+#define reg_ddr2_rw_latency_offset 8
+
+/* Register rw_phy_cfg, scope ddr2, type rw */
+#define reg_ddr2_rw_phy_cfg___en___lsb 0
+#define reg_ddr2_rw_phy_cfg___en___width 1
+#define reg_ddr2_rw_phy_cfg___en___bit 0
+#define reg_ddr2_rw_phy_cfg_offset 12
+
+/* Register rw_phy_ctrl, scope ddr2, type rw */
+#define reg_ddr2_rw_phy_ctrl___rst___lsb 0
+#define reg_ddr2_rw_phy_ctrl___rst___width 1
+#define reg_ddr2_rw_phy_ctrl___rst___bit 0
+#define reg_ddr2_rw_phy_ctrl___cal_rst___lsb 1
+#define reg_ddr2_rw_phy_ctrl___cal_rst___width 1
+#define reg_ddr2_rw_phy_ctrl___cal_rst___bit 1
+#define reg_ddr2_rw_phy_ctrl___cal_start___lsb 2
+#define reg_ddr2_rw_phy_ctrl___cal_start___width 1
+#define reg_ddr2_rw_phy_ctrl___cal_start___bit 2
+#define reg_ddr2_rw_phy_ctrl_offset 16
+
+/* Register rw_ctrl, scope ddr2, type rw */
+#define reg_ddr2_rw_ctrl___mrs_data___lsb 0
+#define reg_ddr2_rw_ctrl___mrs_data___width 16
+#define reg_ddr2_rw_ctrl___cmd___lsb 16
+#define reg_ddr2_rw_ctrl___cmd___width 8
+#define reg_ddr2_rw_ctrl_offset 20
+
+/* Register rw_pwr_down, scope ddr2, type rw */
+#define reg_ddr2_rw_pwr_down___self_ref___lsb 0
+#define reg_ddr2_rw_pwr_down___self_ref___width 2
+#define reg_ddr2_rw_pwr_down___phy_en___lsb 2
+#define reg_ddr2_rw_pwr_down___phy_en___width 1
+#define reg_ddr2_rw_pwr_down___phy_en___bit 2
+#define reg_ddr2_rw_pwr_down_offset 24
+
+/* Register r_stat, scope ddr2, type r */
+#define reg_ddr2_r_stat___dll_lock___lsb 0
+#define reg_ddr2_r_stat___dll_lock___width 1
+#define reg_ddr2_r_stat___dll_lock___bit 0
+#define reg_ddr2_r_stat___dll_delay_code___lsb 1
+#define reg_ddr2_r_stat___dll_delay_code___width 7
+#define reg_ddr2_r_stat___imp_cal_done___lsb 8
+#define reg_ddr2_r_stat___imp_cal_done___width 1
+#define reg_ddr2_r_stat___imp_cal_done___bit 8
+#define reg_ddr2_r_stat___imp_cal_fault___lsb 9
+#define reg_ddr2_r_stat___imp_cal_fault___width 1
+#define reg_ddr2_r_stat___imp_cal_fault___bit 9
+#define reg_ddr2_r_stat___cal_imp_pu___lsb 10
+#define reg_ddr2_r_stat___cal_imp_pu___width 4
+#define reg_ddr2_r_stat___cal_imp_pd___lsb 14
+#define reg_ddr2_r_stat___cal_imp_pd___width 4
+#define reg_ddr2_r_stat_offset 28
+
+/* Register rw_imp_ctrl, scope ddr2, type rw */
+#define reg_ddr2_rw_imp_ctrl___imp_pu___lsb 0
+#define reg_ddr2_rw_imp_ctrl___imp_pu___width 4
+#define reg_ddr2_rw_imp_ctrl___imp_pd___lsb 4
+#define reg_ddr2_rw_imp_ctrl___imp_pd___width 4
+#define reg_ddr2_rw_imp_ctrl_offset 32
+
+#define STRIDE_ddr2_rw_dll_ctrl 4
+/* Register rw_dll_ctrl, scope ddr2, type rw */
+#define reg_ddr2_rw_dll_ctrl___mode___lsb 0
+#define reg_ddr2_rw_dll_ctrl___mode___width 1
+#define reg_ddr2_rw_dll_ctrl___mode___bit 0
+#define reg_ddr2_rw_dll_ctrl___clk_delay___lsb 1
+#define reg_ddr2_rw_dll_ctrl___clk_delay___width 7
+#define reg_ddr2_rw_dll_ctrl_offset 36
+
+#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
+/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
+#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___lsb 0
+#define reg_ddr2_rw_dqs_dll_ctrl___dqs90_delay___width 7
+#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___lsb 7
+#define reg_ddr2_rw_dqs_dll_ctrl___dqs180_delay___width 7
+#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___lsb 14
+#define reg_ddr2_rw_dqs_dll_ctrl___dqs270_delay___width 7
+#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___lsb 21
+#define reg_ddr2_rw_dqs_dll_ctrl___dqs360_delay___width 7
+#define reg_ddr2_rw_dqs_dll_ctrl_offset 52
+
+
+/* Constants */
+#define regk_ddr2_al0 0x00000000
+#define regk_ddr2_al1 0x00000008
+#define regk_ddr2_al2 0x00000010
+#define regk_ddr2_al3 0x00000018
+#define regk_ddr2_al4 0x00000020
+#define regk_ddr2_auto 0x00000003
+#define regk_ddr2_bank4 0x00000000
+#define regk_ddr2_bank8 0x00000001
+#define regk_ddr2_bl4 0x00000002
+#define regk_ddr2_bl8 0x00000003
+#define regk_ddr2_bt_il 0x00000008
+#define regk_ddr2_bt_seq 0x00000000
+#define regk_ddr2_bw16 0x00000001
+#define regk_ddr2_bw32 0x00000000
+#define regk_ddr2_cas2 0x00000020
+#define regk_ddr2_cas3 0x00000030
+#define regk_ddr2_cas4 0x00000040
+#define regk_ddr2_cas5 0x00000050
+#define regk_ddr2_deselect 0x000000c0
+#define regk_ddr2_dic_weak 0x00000002
+#define regk_ddr2_direct 0x00000001
+#define regk_ddr2_dis 0x00000000
+#define regk_ddr2_dll_dis 0x00000001
+#define regk_ddr2_dll_en 0x00000000
+#define regk_ddr2_dll_rst 0x00000100
+#define regk_ddr2_emrs 0x00000081
+#define regk_ddr2_emrs2 0x00000082
+#define regk_ddr2_emrs3 0x00000083
+#define regk_ddr2_full 0x00000001
+#define regk_ddr2_hi_ref_rate 0x00000080
+#define regk_ddr2_mrs 0x00000080
+#define regk_ddr2_no 0x00000000
+#define regk_ddr2_nop 0x000000b8
+#define regk_ddr2_ocd_adj 0x00000200
+#define regk_ddr2_ocd_default 0x00000380
+#define regk_ddr2_ocd_drive0 0x00000100
+#define regk_ddr2_ocd_drive1 0x00000080
+#define regk_ddr2_ocd_exit 0x00000000
+#define regk_ddr2_odt_dis 0x00000000
+#define regk_ddr2_offs 0x00000000
+#define regk_ddr2_pre 0x00000090
+#define regk_ddr2_pre_all 0x00000400
+#define regk_ddr2_pwr_down_fast 0x00000000
+#define regk_ddr2_pwr_down_slow 0x00001000
+#define regk_ddr2_ref 0x00000088
+#define regk_ddr2_rtt150 0x00000040
+#define regk_ddr2_rtt50 0x00000044
+#define regk_ddr2_rtt75 0x00000004
+#define regk_ddr2_rw_cfg_default 0x00186000
+#define regk_ddr2_rw_dll_ctrl_default 0x00000000
+#define regk_ddr2_rw_dll_ctrl_size 0x00000004
+#define regk_ddr2_rw_dqs_dll_ctrl_default 0x00000000
+#define regk_ddr2_rw_dqs_dll_ctrl_size 0x00000004
+#define regk_ddr2_rw_latency_default 0x00000000
+#define regk_ddr2_rw_phy_cfg_default 0x00000000
+#define regk_ddr2_rw_pwr_down_default 0x00000000
+#define regk_ddr2_rw_timing_default 0x00000000
+#define regk_ddr2_s1Gb 0x0000001a
+#define regk_ddr2_s256Mb 0x0000000f
+#define regk_ddr2_s2Gb 0x00000027
+#define regk_ddr2_s4Gb 0x00000042
+#define regk_ddr2_s512Mb 0x00000015
+#define regk_ddr2_temp0_85 0x00000618
+#define regk_ddr2_temp85_95 0x0000030c
+#define regk_ddr2_term150 0x00000002
+#define regk_ddr2_term50 0x00000003
+#define regk_ddr2_term75 0x00000001
+#define regk_ddr2_test 0x00000080
+#define regk_ddr2_weak 0x00000000
+#define regk_ddr2_wr2 0x00000200
+#define regk_ddr2_wr3 0x00000400
+#define regk_ddr2_yes 0x00000001
+#endif /* __ddr2_defs_asm_h */
--- /dev/null
+#ifndef __gio_defs_asm_h
+#define __gio_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: gio.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile gio_defs_asm.h gio.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register r_pa_din, scope gio, type r */
+#define reg_gio_r_pa_din___data___lsb 0
+#define reg_gio_r_pa_din___data___width 32
+#define reg_gio_r_pa_din_offset 0
+
+/* Register rw_pa_dout, scope gio, type rw */
+#define reg_gio_rw_pa_dout___data___lsb 0
+#define reg_gio_rw_pa_dout___data___width 32
+#define reg_gio_rw_pa_dout_offset 4
+
+/* Register rw_pa_oe, scope gio, type rw */
+#define reg_gio_rw_pa_oe___oe___lsb 0
+#define reg_gio_rw_pa_oe___oe___width 32
+#define reg_gio_rw_pa_oe_offset 8
+
+/* Register rw_pa_byte0_dout, scope gio, type rw */
+#define reg_gio_rw_pa_byte0_dout___data___lsb 0
+#define reg_gio_rw_pa_byte0_dout___data___width 8
+#define reg_gio_rw_pa_byte0_dout_offset 12
+
+/* Register rw_pa_byte0_oe, scope gio, type rw */
+#define reg_gio_rw_pa_byte0_oe___oe___lsb 0
+#define reg_gio_rw_pa_byte0_oe___oe___width 8
+#define reg_gio_rw_pa_byte0_oe_offset 16
+
+/* Register rw_pa_byte1_dout, scope gio, type rw */
+#define reg_gio_rw_pa_byte1_dout___data___lsb 0
+#define reg_gio_rw_pa_byte1_dout___data___width 8
+#define reg_gio_rw_pa_byte1_dout_offset 20
+
+/* Register rw_pa_byte1_oe, scope gio, type rw */
+#define reg_gio_rw_pa_byte1_oe___oe___lsb 0
+#define reg_gio_rw_pa_byte1_oe___oe___width 8
+#define reg_gio_rw_pa_byte1_oe_offset 24
+
+/* Register rw_pa_byte2_dout, scope gio, type rw */
+#define reg_gio_rw_pa_byte2_dout___data___lsb 0
+#define reg_gio_rw_pa_byte2_dout___data___width 8
+#define reg_gio_rw_pa_byte2_dout_offset 28
+
+/* Register rw_pa_byte2_oe, scope gio, type rw */
+#define reg_gio_rw_pa_byte2_oe___oe___lsb 0
+#define reg_gio_rw_pa_byte2_oe___oe___width 8
+#define reg_gio_rw_pa_byte2_oe_offset 32
+
+/* Register rw_pa_byte3_dout, scope gio, type rw */
+#define reg_gio_rw_pa_byte3_dout___data___lsb 0
+#define reg_gio_rw_pa_byte3_dout___data___width 8
+#define reg_gio_rw_pa_byte3_dout_offset 36
+
+/* Register rw_pa_byte3_oe, scope gio, type rw */
+#define reg_gio_rw_pa_byte3_oe___oe___lsb 0
+#define reg_gio_rw_pa_byte3_oe___oe___width 8
+#define reg_gio_rw_pa_byte3_oe_offset 40
+
+/* Register r_pb_din, scope gio, type r */
+#define reg_gio_r_pb_din___data___lsb 0
+#define reg_gio_r_pb_din___data___width 32
+#define reg_gio_r_pb_din_offset 44
+
+/* Register rw_pb_dout, scope gio, type rw */
+#define reg_gio_rw_pb_dout___data___lsb 0
+#define reg_gio_rw_pb_dout___data___width 32
+#define reg_gio_rw_pb_dout_offset 48
+
+/* Register rw_pb_oe, scope gio, type rw */
+#define reg_gio_rw_pb_oe___oe___lsb 0
+#define reg_gio_rw_pb_oe___oe___width 32
+#define reg_gio_rw_pb_oe_offset 52
+
+/* Register rw_pb_byte0_dout, scope gio, type rw */
+#define reg_gio_rw_pb_byte0_dout___data___lsb 0
+#define reg_gio_rw_pb_byte0_dout___data___width 8
+#define reg_gio_rw_pb_byte0_dout_offset 56
+
+/* Register rw_pb_byte0_oe, scope gio, type rw */
+#define reg_gio_rw_pb_byte0_oe___oe___lsb 0
+#define reg_gio_rw_pb_byte0_oe___oe___width 8
+#define reg_gio_rw_pb_byte0_oe_offset 60
+
+/* Register rw_pb_byte1_dout, scope gio, type rw */
+#define reg_gio_rw_pb_byte1_dout___data___lsb 0
+#define reg_gio_rw_pb_byte1_dout___data___width 8
+#define reg_gio_rw_pb_byte1_dout_offset 64
+
+/* Register rw_pb_byte1_oe, scope gio, type rw */
+#define reg_gio_rw_pb_byte1_oe___oe___lsb 0
+#define reg_gio_rw_pb_byte1_oe___oe___width 8
+#define reg_gio_rw_pb_byte1_oe_offset 68
+
+/* Register rw_pb_byte2_dout, scope gio, type rw */
+#define reg_gio_rw_pb_byte2_dout___data___lsb 0
+#define reg_gio_rw_pb_byte2_dout___data___width 8
+#define reg_gio_rw_pb_byte2_dout_offset 72
+
+/* Register rw_pb_byte2_oe, scope gio, type rw */
+#define reg_gio_rw_pb_byte2_oe___oe___lsb 0
+#define reg_gio_rw_pb_byte2_oe___oe___width 8
+#define reg_gio_rw_pb_byte2_oe_offset 76
+
+/* Register rw_pb_byte3_dout, scope gio, type rw */
+#define reg_gio_rw_pb_byte3_dout___data___lsb 0
+#define reg_gio_rw_pb_byte3_dout___data___width 8
+#define reg_gio_rw_pb_byte3_dout_offset 80
+
+/* Register rw_pb_byte3_oe, scope gio, type rw */
+#define reg_gio_rw_pb_byte3_oe___oe___lsb 0
+#define reg_gio_rw_pb_byte3_oe___oe___width 8
+#define reg_gio_rw_pb_byte3_oe_offset 84
+
+/* Register r_pc_din, scope gio, type r */
+#define reg_gio_r_pc_din___data___lsb 0
+#define reg_gio_r_pc_din___data___width 16
+#define reg_gio_r_pc_din_offset 88
+
+/* Register rw_pc_dout, scope gio, type rw */
+#define reg_gio_rw_pc_dout___data___lsb 0
+#define reg_gio_rw_pc_dout___data___width 16
+#define reg_gio_rw_pc_dout_offset 92
+
+/* Register rw_pc_oe, scope gio, type rw */
+#define reg_gio_rw_pc_oe___oe___lsb 0
+#define reg_gio_rw_pc_oe___oe___width 16
+#define reg_gio_rw_pc_oe_offset 96
+
+/* Register rw_pc_byte0_dout, scope gio, type rw */
+#define reg_gio_rw_pc_byte0_dout___data___lsb 0
+#define reg_gio_rw_pc_byte0_dout___data___width 8
+#define reg_gio_rw_pc_byte0_dout_offset 100
+
+/* Register rw_pc_byte0_oe, scope gio, type rw */
+#define reg_gio_rw_pc_byte0_oe___oe___lsb 0
+#define reg_gio_rw_pc_byte0_oe___oe___width 8
+#define reg_gio_rw_pc_byte0_oe_offset 104
+
+/* Register rw_pc_byte1_dout, scope gio, type rw */
+#define reg_gio_rw_pc_byte1_dout___data___lsb 0
+#define reg_gio_rw_pc_byte1_dout___data___width 8
+#define reg_gio_rw_pc_byte1_dout_offset 108
+
+/* Register rw_pc_byte1_oe, scope gio, type rw */
+#define reg_gio_rw_pc_byte1_oe___oe___lsb 0
+#define reg_gio_rw_pc_byte1_oe___oe___width 8
+#define reg_gio_rw_pc_byte1_oe_offset 112
+
+/* Register r_pd_din, scope gio, type r */
+#define reg_gio_r_pd_din___data___lsb 0
+#define reg_gio_r_pd_din___data___width 32
+#define reg_gio_r_pd_din_offset 116
+
+/* Register rw_intr_cfg, scope gio, type rw */
+#define reg_gio_rw_intr_cfg___intr0___lsb 0
+#define reg_gio_rw_intr_cfg___intr0___width 3
+#define reg_gio_rw_intr_cfg___intr1___lsb 3
+#define reg_gio_rw_intr_cfg___intr1___width 3
+#define reg_gio_rw_intr_cfg___intr2___lsb 6
+#define reg_gio_rw_intr_cfg___intr2___width 3
+#define reg_gio_rw_intr_cfg___intr3___lsb 9
+#define reg_gio_rw_intr_cfg___intr3___width 3
+#define reg_gio_rw_intr_cfg___intr4___lsb 12
+#define reg_gio_rw_intr_cfg___intr4___width 3
+#define reg_gio_rw_intr_cfg___intr5___lsb 15
+#define reg_gio_rw_intr_cfg___intr5___width 3
+#define reg_gio_rw_intr_cfg___intr6___lsb 18
+#define reg_gio_rw_intr_cfg___intr6___width 3
+#define reg_gio_rw_intr_cfg___intr7___lsb 21
+#define reg_gio_rw_intr_cfg___intr7___width 3
+#define reg_gio_rw_intr_cfg_offset 120
+
+/* Register rw_intr_pins, scope gio, type rw */
+#define reg_gio_rw_intr_pins___intr0___lsb 0
+#define reg_gio_rw_intr_pins___intr0___width 4
+#define reg_gio_rw_intr_pins___intr1___lsb 4
+#define reg_gio_rw_intr_pins___intr1___width 4
+#define reg_gio_rw_intr_pins___intr2___lsb 8
+#define reg_gio_rw_intr_pins___intr2___width 4
+#define reg_gio_rw_intr_pins___intr3___lsb 12
+#define reg_gio_rw_intr_pins___intr3___width 4
+#define reg_gio_rw_intr_pins___intr4___lsb 16
+#define reg_gio_rw_intr_pins___intr4___width 4
+#define reg_gio_rw_intr_pins___intr5___lsb 20
+#define reg_gio_rw_intr_pins___intr5___width 4
+#define reg_gio_rw_intr_pins___intr6___lsb 24
+#define reg_gio_rw_intr_pins___intr6___width 4
+#define reg_gio_rw_intr_pins___intr7___lsb 28
+#define reg_gio_rw_intr_pins___intr7___width 4
+#define reg_gio_rw_intr_pins_offset 124
+
+/* Register rw_intr_mask, scope gio, type rw */
+#define reg_gio_rw_intr_mask___intr0___lsb 0
+#define reg_gio_rw_intr_mask___intr0___width 1
+#define reg_gio_rw_intr_mask___intr0___bit 0
+#define reg_gio_rw_intr_mask___intr1___lsb 1
+#define reg_gio_rw_intr_mask___intr1___width 1
+#define reg_gio_rw_intr_mask___intr1___bit 1
+#define reg_gio_rw_intr_mask___intr2___lsb 2
+#define reg_gio_rw_intr_mask___intr2___width 1
+#define reg_gio_rw_intr_mask___intr2___bit 2
+#define reg_gio_rw_intr_mask___intr3___lsb 3
+#define reg_gio_rw_intr_mask___intr3___width 1
+#define reg_gio_rw_intr_mask___intr3___bit 3
+#define reg_gio_rw_intr_mask___intr4___lsb 4
+#define reg_gio_rw_intr_mask___intr4___width 1
+#define reg_gio_rw_intr_mask___intr4___bit 4
+#define reg_gio_rw_intr_mask___intr5___lsb 5
+#define reg_gio_rw_intr_mask___intr5___width 1
+#define reg_gio_rw_intr_mask___intr5___bit 5
+#define reg_gio_rw_intr_mask___intr6___lsb 6
+#define reg_gio_rw_intr_mask___intr6___width 1
+#define reg_gio_rw_intr_mask___intr6___bit 6
+#define reg_gio_rw_intr_mask___intr7___lsb 7
+#define reg_gio_rw_intr_mask___intr7___width 1
+#define reg_gio_rw_intr_mask___intr7___bit 7
+#define reg_gio_rw_intr_mask___i2c0_done___lsb 8
+#define reg_gio_rw_intr_mask___i2c0_done___width 1
+#define reg_gio_rw_intr_mask___i2c0_done___bit 8
+#define reg_gio_rw_intr_mask___i2c1_done___lsb 9
+#define reg_gio_rw_intr_mask___i2c1_done___width 1
+#define reg_gio_rw_intr_mask___i2c1_done___bit 9
+#define reg_gio_rw_intr_mask_offset 128
+
+/* Register rw_ack_intr, scope gio, type rw */
+#define reg_gio_rw_ack_intr___intr0___lsb 0
+#define reg_gio_rw_ack_intr___intr0___width 1
+#define reg_gio_rw_ack_intr___intr0___bit 0
+#define reg_gio_rw_ack_intr___intr1___lsb 1
+#define reg_gio_rw_ack_intr___intr1___width 1
+#define reg_gio_rw_ack_intr___intr1___bit 1
+#define reg_gio_rw_ack_intr___intr2___lsb 2
+#define reg_gio_rw_ack_intr___intr2___width 1
+#define reg_gio_rw_ack_intr___intr2___bit 2
+#define reg_gio_rw_ack_intr___intr3___lsb 3
+#define reg_gio_rw_ack_intr___intr3___width 1
+#define reg_gio_rw_ack_intr___intr3___bit 3
+#define reg_gio_rw_ack_intr___intr4___lsb 4
+#define reg_gio_rw_ack_intr___intr4___width 1
+#define reg_gio_rw_ack_intr___intr4___bit 4
+#define reg_gio_rw_ack_intr___intr5___lsb 5
+#define reg_gio_rw_ack_intr___intr5___width 1
+#define reg_gio_rw_ack_intr___intr5___bit 5
+#define reg_gio_rw_ack_intr___intr6___lsb 6
+#define reg_gio_rw_ack_intr___intr6___width 1
+#define reg_gio_rw_ack_intr___intr6___bit 6
+#define reg_gio_rw_ack_intr___intr7___lsb 7
+#define reg_gio_rw_ack_intr___intr7___width 1
+#define reg_gio_rw_ack_intr___intr7___bit 7
+#define reg_gio_rw_ack_intr___i2c0_done___lsb 8
+#define reg_gio_rw_ack_intr___i2c0_done___width 1
+#define reg_gio_rw_ack_intr___i2c0_done___bit 8
+#define reg_gio_rw_ack_intr___i2c1_done___lsb 9
+#define reg_gio_rw_ack_intr___i2c1_done___width 1
+#define reg_gio_rw_ack_intr___i2c1_done___bit 9
+#define reg_gio_rw_ack_intr_offset 132
+
+/* Register r_intr, scope gio, type r */
+#define reg_gio_r_intr___intr0___lsb 0
+#define reg_gio_r_intr___intr0___width 1
+#define reg_gio_r_intr___intr0___bit 0
+#define reg_gio_r_intr___intr1___lsb 1
+#define reg_gio_r_intr___intr1___width 1
+#define reg_gio_r_intr___intr1___bit 1
+#define reg_gio_r_intr___intr2___lsb 2
+#define reg_gio_r_intr___intr2___width 1
+#define reg_gio_r_intr___intr2___bit 2
+#define reg_gio_r_intr___intr3___lsb 3
+#define reg_gio_r_intr___intr3___width 1
+#define reg_gio_r_intr___intr3___bit 3
+#define reg_gio_r_intr___intr4___lsb 4
+#define reg_gio_r_intr___intr4___width 1
+#define reg_gio_r_intr___intr4___bit 4
+#define reg_gio_r_intr___intr5___lsb 5
+#define reg_gio_r_intr___intr5___width 1
+#define reg_gio_r_intr___intr5___bit 5
+#define reg_gio_r_intr___intr6___lsb 6
+#define reg_gio_r_intr___intr6___width 1
+#define reg_gio_r_intr___intr6___bit 6
+#define reg_gio_r_intr___intr7___lsb 7
+#define reg_gio_r_intr___intr7___width 1
+#define reg_gio_r_intr___intr7___bit 7
+#define reg_gio_r_intr___i2c0_done___lsb 8
+#define reg_gio_r_intr___i2c0_done___width 1
+#define reg_gio_r_intr___i2c0_done___bit 8
+#define reg_gio_r_intr___i2c1_done___lsb 9
+#define reg_gio_r_intr___i2c1_done___width 1
+#define reg_gio_r_intr___i2c1_done___bit 9
+#define reg_gio_r_intr_offset 136
+
+/* Register r_masked_intr, scope gio, type r */
+#define reg_gio_r_masked_intr___intr0___lsb 0
+#define reg_gio_r_masked_intr___intr0___width 1
+#define reg_gio_r_masked_intr___intr0___bit 0
+#define reg_gio_r_masked_intr___intr1___lsb 1
+#define reg_gio_r_masked_intr___intr1___width 1
+#define reg_gio_r_masked_intr___intr1___bit 1
+#define reg_gio_r_masked_intr___intr2___lsb 2
+#define reg_gio_r_masked_intr___intr2___width 1
+#define reg_gio_r_masked_intr___intr2___bit 2
+#define reg_gio_r_masked_intr___intr3___lsb 3
+#define reg_gio_r_masked_intr___intr3___width 1
+#define reg_gio_r_masked_intr___intr3___bit 3
+#define reg_gio_r_masked_intr___intr4___lsb 4
+#define reg_gio_r_masked_intr___intr4___width 1
+#define reg_gio_r_masked_intr___intr4___bit 4
+#define reg_gio_r_masked_intr___intr5___lsb 5
+#define reg_gio_r_masked_intr___intr5___width 1
+#define reg_gio_r_masked_intr___intr5___bit 5
+#define reg_gio_r_masked_intr___intr6___lsb 6
+#define reg_gio_r_masked_intr___intr6___width 1
+#define reg_gio_r_masked_intr___intr6___bit 6
+#define reg_gio_r_masked_intr___intr7___lsb 7
+#define reg_gio_r_masked_intr___intr7___width 1
+#define reg_gio_r_masked_intr___intr7___bit 7
+#define reg_gio_r_masked_intr___i2c0_done___lsb 8
+#define reg_gio_r_masked_intr___i2c0_done___width 1
+#define reg_gio_r_masked_intr___i2c0_done___bit 8
+#define reg_gio_r_masked_intr___i2c1_done___lsb 9
+#define reg_gio_r_masked_intr___i2c1_done___width 1
+#define reg_gio_r_masked_intr___i2c1_done___bit 9
+#define reg_gio_r_masked_intr_offset 140
+
+/* Register rw_i2c0_start, scope gio, type rw */
+#define reg_gio_rw_i2c0_start___run___lsb 0
+#define reg_gio_rw_i2c0_start___run___width 1
+#define reg_gio_rw_i2c0_start___run___bit 0
+#define reg_gio_rw_i2c0_start_offset 144
+
+/* Register rw_i2c0_cfg, scope gio, type rw */
+#define reg_gio_rw_i2c0_cfg___en___lsb 0
+#define reg_gio_rw_i2c0_cfg___en___width 1
+#define reg_gio_rw_i2c0_cfg___en___bit 0
+#define reg_gio_rw_i2c0_cfg___bit_order___lsb 1
+#define reg_gio_rw_i2c0_cfg___bit_order___width 1
+#define reg_gio_rw_i2c0_cfg___bit_order___bit 1
+#define reg_gio_rw_i2c0_cfg___scl_io___lsb 2
+#define reg_gio_rw_i2c0_cfg___scl_io___width 1
+#define reg_gio_rw_i2c0_cfg___scl_io___bit 2
+#define reg_gio_rw_i2c0_cfg___scl_inv___lsb 3
+#define reg_gio_rw_i2c0_cfg___scl_inv___width 1
+#define reg_gio_rw_i2c0_cfg___scl_inv___bit 3
+#define reg_gio_rw_i2c0_cfg___sda_io___lsb 4
+#define reg_gio_rw_i2c0_cfg___sda_io___width 1
+#define reg_gio_rw_i2c0_cfg___sda_io___bit 4
+#define reg_gio_rw_i2c0_cfg___sda_idle___lsb 5
+#define reg_gio_rw_i2c0_cfg___sda_idle___width 1
+#define reg_gio_rw_i2c0_cfg___sda_idle___bit 5
+#define reg_gio_rw_i2c0_cfg_offset 148
+
+/* Register rw_i2c0_ctrl, scope gio, type rw */
+#define reg_gio_rw_i2c0_ctrl___trf_bits___lsb 0
+#define reg_gio_rw_i2c0_ctrl___trf_bits___width 6
+#define reg_gio_rw_i2c0_ctrl___switch_dir___lsb 6
+#define reg_gio_rw_i2c0_ctrl___switch_dir___width 6
+#define reg_gio_rw_i2c0_ctrl___extra_start___lsb 12
+#define reg_gio_rw_i2c0_ctrl___extra_start___width 3
+#define reg_gio_rw_i2c0_ctrl___early_end___lsb 15
+#define reg_gio_rw_i2c0_ctrl___early_end___width 1
+#define reg_gio_rw_i2c0_ctrl___early_end___bit 15
+#define reg_gio_rw_i2c0_ctrl___start_stop___lsb 16
+#define reg_gio_rw_i2c0_ctrl___start_stop___width 1
+#define reg_gio_rw_i2c0_ctrl___start_stop___bit 16
+#define reg_gio_rw_i2c0_ctrl___ack_dir0___lsb 17
+#define reg_gio_rw_i2c0_ctrl___ack_dir0___width 1
+#define reg_gio_rw_i2c0_ctrl___ack_dir0___bit 17
+#define reg_gio_rw_i2c0_ctrl___ack_dir1___lsb 18
+#define reg_gio_rw_i2c0_ctrl___ack_dir1___width 1
+#define reg_gio_rw_i2c0_ctrl___ack_dir1___bit 18
+#define reg_gio_rw_i2c0_ctrl___ack_dir2___lsb 19
+#define reg_gio_rw_i2c0_ctrl___ack_dir2___width 1
+#define reg_gio_rw_i2c0_ctrl___ack_dir2___bit 19
+#define reg_gio_rw_i2c0_ctrl___ack_dir3___lsb 20
+#define reg_gio_rw_i2c0_ctrl___ack_dir3___width 1
+#define reg_gio_rw_i2c0_ctrl___ack_dir3___bit 20
+#define reg_gio_rw_i2c0_ctrl___ack_dir4___lsb 21
+#define reg_gio_rw_i2c0_ctrl___ack_dir4___width 1
+#define reg_gio_rw_i2c0_ctrl___ack_dir4___bit 21
+#define reg_gio_rw_i2c0_ctrl___ack_dir5___lsb 22
+#define reg_gio_rw_i2c0_ctrl___ack_dir5___width 1
+#define reg_gio_rw_i2c0_ctrl___ack_dir5___bit 22
+#define reg_gio_rw_i2c0_ctrl___ack_bit___lsb 23
+#define reg_gio_rw_i2c0_ctrl___ack_bit___width 1
+#define reg_gio_rw_i2c0_ctrl___ack_bit___bit 23
+#define reg_gio_rw_i2c0_ctrl___start_bit___lsb 24
+#define reg_gio_rw_i2c0_ctrl___start_bit___width 1
+#define reg_gio_rw_i2c0_ctrl___start_bit___bit 24
+#define reg_gio_rw_i2c0_ctrl___freq___lsb 25
+#define reg_gio_rw_i2c0_ctrl___freq___width 2
+#define reg_gio_rw_i2c0_ctrl_offset 152
+
+/* Register rw_i2c0_data, scope gio, type rw */
+#define reg_gio_rw_i2c0_data___data0___lsb 0
+#define reg_gio_rw_i2c0_data___data0___width 8
+#define reg_gio_rw_i2c0_data___data1___lsb 8
+#define reg_gio_rw_i2c0_data___data1___width 8
+#define reg_gio_rw_i2c0_data___data2___lsb 16
+#define reg_gio_rw_i2c0_data___data2___width 8
+#define reg_gio_rw_i2c0_data___data3___lsb 24
+#define reg_gio_rw_i2c0_data___data3___width 8
+#define reg_gio_rw_i2c0_data_offset 156
+
+/* Register rw_i2c0_data2, scope gio, type rw */
+#define reg_gio_rw_i2c0_data2___data4___lsb 0
+#define reg_gio_rw_i2c0_data2___data4___width 8
+#define reg_gio_rw_i2c0_data2___data5___lsb 8
+#define reg_gio_rw_i2c0_data2___data5___width 8
+#define reg_gio_rw_i2c0_data2___start_val___lsb 16
+#define reg_gio_rw_i2c0_data2___start_val___width 6
+#define reg_gio_rw_i2c0_data2___ack_val___lsb 22
+#define reg_gio_rw_i2c0_data2___ack_val___width 6
+#define reg_gio_rw_i2c0_data2_offset 160
+
+/* Register rw_i2c1_start, scope gio, type rw */
+#define reg_gio_rw_i2c1_start___run___lsb 0
+#define reg_gio_rw_i2c1_start___run___width 1
+#define reg_gio_rw_i2c1_start___run___bit 0
+#define reg_gio_rw_i2c1_start_offset 164
+
+/* Register rw_i2c1_cfg, scope gio, type rw */
+#define reg_gio_rw_i2c1_cfg___en___lsb 0
+#define reg_gio_rw_i2c1_cfg___en___width 1
+#define reg_gio_rw_i2c1_cfg___en___bit 0
+#define reg_gio_rw_i2c1_cfg___bit_order___lsb 1
+#define reg_gio_rw_i2c1_cfg___bit_order___width 1
+#define reg_gio_rw_i2c1_cfg___bit_order___bit 1
+#define reg_gio_rw_i2c1_cfg___scl_io___lsb 2
+#define reg_gio_rw_i2c1_cfg___scl_io___width 1
+#define reg_gio_rw_i2c1_cfg___scl_io___bit 2
+#define reg_gio_rw_i2c1_cfg___scl_inv___lsb 3
+#define reg_gio_rw_i2c1_cfg___scl_inv___width 1
+#define reg_gio_rw_i2c1_cfg___scl_inv___bit 3
+#define reg_gio_rw_i2c1_cfg___sda0_io___lsb 4
+#define reg_gio_rw_i2c1_cfg___sda0_io___width 1
+#define reg_gio_rw_i2c1_cfg___sda0_io___bit 4
+#define reg_gio_rw_i2c1_cfg___sda0_idle___lsb 5
+#define reg_gio_rw_i2c1_cfg___sda0_idle___width 1
+#define reg_gio_rw_i2c1_cfg___sda0_idle___bit 5
+#define reg_gio_rw_i2c1_cfg___sda1_io___lsb 6
+#define reg_gio_rw_i2c1_cfg___sda1_io___width 1
+#define reg_gio_rw_i2c1_cfg___sda1_io___bit 6
+#define reg_gio_rw_i2c1_cfg___sda1_idle___lsb 7
+#define reg_gio_rw_i2c1_cfg___sda1_idle___width 1
+#define reg_gio_rw_i2c1_cfg___sda1_idle___bit 7
+#define reg_gio_rw_i2c1_cfg___sda2_io___lsb 8
+#define reg_gio_rw_i2c1_cfg___sda2_io___width 1
+#define reg_gio_rw_i2c1_cfg___sda2_io___bit 8
+#define reg_gio_rw_i2c1_cfg___sda2_idle___lsb 9
+#define reg_gio_rw_i2c1_cfg___sda2_idle___width 1
+#define reg_gio_rw_i2c1_cfg___sda2_idle___bit 9
+#define reg_gio_rw_i2c1_cfg___sda3_io___lsb 10
+#define reg_gio_rw_i2c1_cfg___sda3_io___width 1
+#define reg_gio_rw_i2c1_cfg___sda3_io___bit 10
+#define reg_gio_rw_i2c1_cfg___sda3_idle___lsb 11
+#define reg_gio_rw_i2c1_cfg___sda3_idle___width 1
+#define reg_gio_rw_i2c1_cfg___sda3_idle___bit 11
+#define reg_gio_rw_i2c1_cfg___sda_sel___lsb 12
+#define reg_gio_rw_i2c1_cfg___sda_sel___width 2
+#define reg_gio_rw_i2c1_cfg___sen_idle___lsb 14
+#define reg_gio_rw_i2c1_cfg___sen_idle___width 1
+#define reg_gio_rw_i2c1_cfg___sen_idle___bit 14
+#define reg_gio_rw_i2c1_cfg___sen_inv___lsb 15
+#define reg_gio_rw_i2c1_cfg___sen_inv___width 1
+#define reg_gio_rw_i2c1_cfg___sen_inv___bit 15
+#define reg_gio_rw_i2c1_cfg___sen_sel___lsb 16
+#define reg_gio_rw_i2c1_cfg___sen_sel___width 2
+#define reg_gio_rw_i2c1_cfg_offset 168
+
+/* Register rw_i2c1_ctrl, scope gio, type rw */
+#define reg_gio_rw_i2c1_ctrl___trf_bits___lsb 0
+#define reg_gio_rw_i2c1_ctrl___trf_bits___width 6
+#define reg_gio_rw_i2c1_ctrl___switch_dir___lsb 6
+#define reg_gio_rw_i2c1_ctrl___switch_dir___width 6
+#define reg_gio_rw_i2c1_ctrl___extra_start___lsb 12
+#define reg_gio_rw_i2c1_ctrl___extra_start___width 3
+#define reg_gio_rw_i2c1_ctrl___early_end___lsb 15
+#define reg_gio_rw_i2c1_ctrl___early_end___width 1
+#define reg_gio_rw_i2c1_ctrl___early_end___bit 15
+#define reg_gio_rw_i2c1_ctrl___start_stop___lsb 16
+#define reg_gio_rw_i2c1_ctrl___start_stop___width 1
+#define reg_gio_rw_i2c1_ctrl___start_stop___bit 16
+#define reg_gio_rw_i2c1_ctrl___ack_dir0___lsb 17
+#define reg_gio_rw_i2c1_ctrl___ack_dir0___width 1
+#define reg_gio_rw_i2c1_ctrl___ack_dir0___bit 17
+#define reg_gio_rw_i2c1_ctrl___ack_dir1___lsb 18
+#define reg_gio_rw_i2c1_ctrl___ack_dir1___width 1
+#define reg_gio_rw_i2c1_ctrl___ack_dir1___bit 18
+#define reg_gio_rw_i2c1_ctrl___ack_dir2___lsb 19
+#define reg_gio_rw_i2c1_ctrl___ack_dir2___width 1
+#define reg_gio_rw_i2c1_ctrl___ack_dir2___bit 19
+#define reg_gio_rw_i2c1_ctrl___ack_dir3___lsb 20
+#define reg_gio_rw_i2c1_ctrl___ack_dir3___width 1
+#define reg_gio_rw_i2c1_ctrl___ack_dir3___bit 20
+#define reg_gio_rw_i2c1_ctrl___ack_dir4___lsb 21
+#define reg_gio_rw_i2c1_ctrl___ack_dir4___width 1
+#define reg_gio_rw_i2c1_ctrl___ack_dir4___bit 21
+#define reg_gio_rw_i2c1_ctrl___ack_dir5___lsb 22
+#define reg_gio_rw_i2c1_ctrl___ack_dir5___width 1
+#define reg_gio_rw_i2c1_ctrl___ack_dir5___bit 22
+#define reg_gio_rw_i2c1_ctrl___ack_bit___lsb 23
+#define reg_gio_rw_i2c1_ctrl___ack_bit___width 1
+#define reg_gio_rw_i2c1_ctrl___ack_bit___bit 23
+#define reg_gio_rw_i2c1_ctrl___start_bit___lsb 24
+#define reg_gio_rw_i2c1_ctrl___start_bit___width 1
+#define reg_gio_rw_i2c1_ctrl___start_bit___bit 24
+#define reg_gio_rw_i2c1_ctrl___freq___lsb 25
+#define reg_gio_rw_i2c1_ctrl___freq___width 2
+#define reg_gio_rw_i2c1_ctrl_offset 172
+
+/* Register rw_i2c1_data, scope gio, type rw */
+#define reg_gio_rw_i2c1_data___data0___lsb 0
+#define reg_gio_rw_i2c1_data___data0___width 8
+#define reg_gio_rw_i2c1_data___data1___lsb 8
+#define reg_gio_rw_i2c1_data___data1___width 8
+#define reg_gio_rw_i2c1_data___data2___lsb 16
+#define reg_gio_rw_i2c1_data___data2___width 8
+#define reg_gio_rw_i2c1_data___data3___lsb 24
+#define reg_gio_rw_i2c1_data___data3___width 8
+#define reg_gio_rw_i2c1_data_offset 176
+
+/* Register rw_i2c1_data2, scope gio, type rw */
+#define reg_gio_rw_i2c1_data2___data4___lsb 0
+#define reg_gio_rw_i2c1_data2___data4___width 8
+#define reg_gio_rw_i2c1_data2___data5___lsb 8
+#define reg_gio_rw_i2c1_data2___data5___width 8
+#define reg_gio_rw_i2c1_data2___start_val___lsb 16
+#define reg_gio_rw_i2c1_data2___start_val___width 6
+#define reg_gio_rw_i2c1_data2___ack_val___lsb 22
+#define reg_gio_rw_i2c1_data2___ack_val___width 6
+#define reg_gio_rw_i2c1_data2_offset 180
+
+/* Register r_ppwm_stat, scope gio, type r */
+#define reg_gio_r_ppwm_stat___freq___lsb 0
+#define reg_gio_r_ppwm_stat___freq___width 2
+#define reg_gio_r_ppwm_stat_offset 184
+
+/* Register rw_ppwm_data, scope gio, type rw */
+#define reg_gio_rw_ppwm_data___data___lsb 0
+#define reg_gio_rw_ppwm_data___data___width 8
+#define reg_gio_rw_ppwm_data_offset 188
+
+/* Register rw_pwm0_ctrl, scope gio, type rw */
+#define reg_gio_rw_pwm0_ctrl___mode___lsb 0
+#define reg_gio_rw_pwm0_ctrl___mode___width 2
+#define reg_gio_rw_pwm0_ctrl___ccd_override___lsb 2
+#define reg_gio_rw_pwm0_ctrl___ccd_override___width 1
+#define reg_gio_rw_pwm0_ctrl___ccd_override___bit 2
+#define reg_gio_rw_pwm0_ctrl___ccd_val___lsb 3
+#define reg_gio_rw_pwm0_ctrl___ccd_val___width 1
+#define reg_gio_rw_pwm0_ctrl___ccd_val___bit 3
+#define reg_gio_rw_pwm0_ctrl_offset 192
+
+/* Register rw_pwm0_var, scope gio, type rw */
+#define reg_gio_rw_pwm0_var___lo___lsb 0
+#define reg_gio_rw_pwm0_var___lo___width 13
+#define reg_gio_rw_pwm0_var___hi___lsb 13
+#define reg_gio_rw_pwm0_var___hi___width 13
+#define reg_gio_rw_pwm0_var_offset 196
+
+/* Register rw_pwm0_data, scope gio, type rw */
+#define reg_gio_rw_pwm0_data___data___lsb 0
+#define reg_gio_rw_pwm0_data___data___width 8
+#define reg_gio_rw_pwm0_data_offset 200
+
+/* Register rw_pwm1_ctrl, scope gio, type rw */
+#define reg_gio_rw_pwm1_ctrl___mode___lsb 0
+#define reg_gio_rw_pwm1_ctrl___mode___width 2
+#define reg_gio_rw_pwm1_ctrl___ccd_override___lsb 2
+#define reg_gio_rw_pwm1_ctrl___ccd_override___width 1
+#define reg_gio_rw_pwm1_ctrl___ccd_override___bit 2
+#define reg_gio_rw_pwm1_ctrl___ccd_val___lsb 3
+#define reg_gio_rw_pwm1_ctrl___ccd_val___width 1
+#define reg_gio_rw_pwm1_ctrl___ccd_val___bit 3
+#define reg_gio_rw_pwm1_ctrl_offset 204
+
+/* Register rw_pwm1_var, scope gio, type rw */
+#define reg_gio_rw_pwm1_var___lo___lsb 0
+#define reg_gio_rw_pwm1_var___lo___width 13
+#define reg_gio_rw_pwm1_var___hi___lsb 13
+#define reg_gio_rw_pwm1_var___hi___width 13
+#define reg_gio_rw_pwm1_var_offset 208
+
+/* Register rw_pwm1_data, scope gio, type rw */
+#define reg_gio_rw_pwm1_data___data___lsb 0
+#define reg_gio_rw_pwm1_data___data___width 8
+#define reg_gio_rw_pwm1_data_offset 212
+
+/* Register rw_pwm2_ctrl, scope gio, type rw */
+#define reg_gio_rw_pwm2_ctrl___mode___lsb 0
+#define reg_gio_rw_pwm2_ctrl___mode___width 2
+#define reg_gio_rw_pwm2_ctrl___ccd_override___lsb 2
+#define reg_gio_rw_pwm2_ctrl___ccd_override___width 1
+#define reg_gio_rw_pwm2_ctrl___ccd_override___bit 2
+#define reg_gio_rw_pwm2_ctrl___ccd_val___lsb 3
+#define reg_gio_rw_pwm2_ctrl___ccd_val___width 1
+#define reg_gio_rw_pwm2_ctrl___ccd_val___bit 3
+#define reg_gio_rw_pwm2_ctrl_offset 216
+
+/* Register rw_pwm2_var, scope gio, type rw */
+#define reg_gio_rw_pwm2_var___lo___lsb 0
+#define reg_gio_rw_pwm2_var___lo___width 13
+#define reg_gio_rw_pwm2_var___hi___lsb 13
+#define reg_gio_rw_pwm2_var___hi___width 13
+#define reg_gio_rw_pwm2_var_offset 220
+
+/* Register rw_pwm2_data, scope gio, type rw */
+#define reg_gio_rw_pwm2_data___data___lsb 0
+#define reg_gio_rw_pwm2_data___data___width 8
+#define reg_gio_rw_pwm2_data_offset 224
+
+/* Register rw_pwm_in_cfg, scope gio, type rw */
+#define reg_gio_rw_pwm_in_cfg___pin___lsb 0
+#define reg_gio_rw_pwm_in_cfg___pin___width 3
+#define reg_gio_rw_pwm_in_cfg_offset 228
+
+/* Register r_pwm_in_lo, scope gio, type r */
+#define reg_gio_r_pwm_in_lo___data___lsb 0
+#define reg_gio_r_pwm_in_lo___data___width 32
+#define reg_gio_r_pwm_in_lo_offset 232
+
+/* Register r_pwm_in_hi, scope gio, type r */
+#define reg_gio_r_pwm_in_hi___data___lsb 0
+#define reg_gio_r_pwm_in_hi___data___width 32
+#define reg_gio_r_pwm_in_hi_offset 236
+
+/* Register r_pwm_in_cnt, scope gio, type r */
+#define reg_gio_r_pwm_in_cnt___data___lsb 0
+#define reg_gio_r_pwm_in_cnt___data___width 32
+#define reg_gio_r_pwm_in_cnt_offset 240
+
+
+/* Constants */
+#define regk_gio_anyedge 0x00000007
+#define regk_gio_f100k 0x00000000
+#define regk_gio_f1562 0x00000000
+#define regk_gio_f195 0x00000003
+#define regk_gio_f1m 0x00000002
+#define regk_gio_f390 0x00000002
+#define regk_gio_f400k 0x00000001
+#define regk_gio_f5m 0x00000003
+#define regk_gio_f781 0x00000001
+#define regk_gio_hi 0x00000001
+#define regk_gio_in 0x00000000
+#define regk_gio_intr_pa0 0x00000000
+#define regk_gio_intr_pa1 0x00000000
+#define regk_gio_intr_pa10 0x00000001
+#define regk_gio_intr_pa11 0x00000001
+#define regk_gio_intr_pa12 0x00000001
+#define regk_gio_intr_pa13 0x00000001
+#define regk_gio_intr_pa14 0x00000001
+#define regk_gio_intr_pa15 0x00000001
+#define regk_gio_intr_pa16 0x00000002
+#define regk_gio_intr_pa17 0x00000002
+#define regk_gio_intr_pa18 0x00000002
+#define regk_gio_intr_pa19 0x00000002
+#define regk_gio_intr_pa2 0x00000000
+#define regk_gio_intr_pa20 0x00000002
+#define regk_gio_intr_pa21 0x00000002
+#define regk_gio_intr_pa22 0x00000002
+#define regk_gio_intr_pa23 0x00000002
+#define regk_gio_intr_pa24 0x00000003
+#define regk_gio_intr_pa25 0x00000003
+#define regk_gio_intr_pa26 0x00000003
+#define regk_gio_intr_pa27 0x00000003
+#define regk_gio_intr_pa28 0x00000003
+#define regk_gio_intr_pa29 0x00000003
+#define regk_gio_intr_pa3 0x00000000
+#define regk_gio_intr_pa30 0x00000003
+#define regk_gio_intr_pa31 0x00000003
+#define regk_gio_intr_pa4 0x00000000
+#define regk_gio_intr_pa5 0x00000000
+#define regk_gio_intr_pa6 0x00000000
+#define regk_gio_intr_pa7 0x00000000
+#define regk_gio_intr_pa8 0x00000001
+#define regk_gio_intr_pa9 0x00000001
+#define regk_gio_intr_pb0 0x00000004
+#define regk_gio_intr_pb1 0x00000004
+#define regk_gio_intr_pb10 0x00000005
+#define regk_gio_intr_pb11 0x00000005
+#define regk_gio_intr_pb12 0x00000005
+#define regk_gio_intr_pb13 0x00000005
+#define regk_gio_intr_pb14 0x00000005
+#define regk_gio_intr_pb15 0x00000005
+#define regk_gio_intr_pb16 0x00000006
+#define regk_gio_intr_pb17 0x00000006
+#define regk_gio_intr_pb18 0x00000006
+#define regk_gio_intr_pb19 0x00000006
+#define regk_gio_intr_pb2 0x00000004
+#define regk_gio_intr_pb20 0x00000006
+#define regk_gio_intr_pb21 0x00000006
+#define regk_gio_intr_pb22 0x00000006
+#define regk_gio_intr_pb23 0x00000006
+#define regk_gio_intr_pb24 0x00000007
+#define regk_gio_intr_pb25 0x00000007
+#define regk_gio_intr_pb26 0x00000007
+#define regk_gio_intr_pb27 0x00000007
+#define regk_gio_intr_pb28 0x00000007
+#define regk_gio_intr_pb29 0x00000007
+#define regk_gio_intr_pb3 0x00000004
+#define regk_gio_intr_pb30 0x00000007
+#define regk_gio_intr_pb31 0x00000007
+#define regk_gio_intr_pb4 0x00000004
+#define regk_gio_intr_pb5 0x00000004
+#define regk_gio_intr_pb6 0x00000004
+#define regk_gio_intr_pb7 0x00000004
+#define regk_gio_intr_pb8 0x00000005
+#define regk_gio_intr_pb9 0x00000005
+#define regk_gio_intr_pc0 0x00000008
+#define regk_gio_intr_pc1 0x00000008
+#define regk_gio_intr_pc10 0x00000009
+#define regk_gio_intr_pc11 0x00000009
+#define regk_gio_intr_pc12 0x00000009
+#define regk_gio_intr_pc13 0x00000009
+#define regk_gio_intr_pc14 0x00000009
+#define regk_gio_intr_pc15 0x00000009
+#define regk_gio_intr_pc2 0x00000008
+#define regk_gio_intr_pc3 0x00000008
+#define regk_gio_intr_pc4 0x00000008
+#define regk_gio_intr_pc5 0x00000008
+#define regk_gio_intr_pc6 0x00000008
+#define regk_gio_intr_pc7 0x00000008
+#define regk_gio_intr_pc8 0x00000009
+#define regk_gio_intr_pc9 0x00000009
+#define regk_gio_intr_pd0 0x0000000c
+#define regk_gio_intr_pd1 0x0000000c
+#define regk_gio_intr_pd10 0x0000000d
+#define regk_gio_intr_pd11 0x0000000d
+#define regk_gio_intr_pd12 0x0000000d
+#define regk_gio_intr_pd13 0x0000000d
+#define regk_gio_intr_pd14 0x0000000d
+#define regk_gio_intr_pd15 0x0000000d
+#define regk_gio_intr_pd16 0x0000000e
+#define regk_gio_intr_pd17 0x0000000e
+#define regk_gio_intr_pd18 0x0000000e
+#define regk_gio_intr_pd19 0x0000000e
+#define regk_gio_intr_pd2 0x0000000c
+#define regk_gio_intr_pd20 0x0000000e
+#define regk_gio_intr_pd21 0x0000000e
+#define regk_gio_intr_pd22 0x0000000e
+#define regk_gio_intr_pd23 0x0000000e
+#define regk_gio_intr_pd24 0x0000000f
+#define regk_gio_intr_pd25 0x0000000f
+#define regk_gio_intr_pd26 0x0000000f
+#define regk_gio_intr_pd27 0x0000000f
+#define regk_gio_intr_pd28 0x0000000f
+#define regk_gio_intr_pd29 0x0000000f
+#define regk_gio_intr_pd3 0x0000000c
+#define regk_gio_intr_pd30 0x0000000f
+#define regk_gio_intr_pd31 0x0000000f
+#define regk_gio_intr_pd4 0x0000000c
+#define regk_gio_intr_pd5 0x0000000c
+#define regk_gio_intr_pd6 0x0000000c
+#define regk_gio_intr_pd7 0x0000000c
+#define regk_gio_intr_pd8 0x0000000d
+#define regk_gio_intr_pd9 0x0000000d
+#define regk_gio_lo 0x00000002
+#define regk_gio_lsb 0x00000000
+#define regk_gio_msb 0x00000001
+#define regk_gio_negedge 0x00000006
+#define regk_gio_no 0x00000000
+#define regk_gio_no_switch 0x0000003f
+#define regk_gio_none 0x00000007
+#define regk_gio_off 0x00000000
+#define regk_gio_opendrain 0x00000000
+#define regk_gio_out 0x00000001
+#define regk_gio_posedge 0x00000005
+#define regk_gio_pwm_hfp 0x00000002
+#define regk_gio_pwm_pa0 0x00000001
+#define regk_gio_pwm_pa19 0x00000004
+#define regk_gio_pwm_pa6 0x00000002
+#define regk_gio_pwm_pa7 0x00000003
+#define regk_gio_pwm_pb26 0x00000005
+#define regk_gio_pwm_pd23 0x00000006
+#define regk_gio_pwm_pd31 0x00000007
+#define regk_gio_pwm_std 0x00000001
+#define regk_gio_pwm_var 0x00000003
+#define regk_gio_rw_i2c0_cfg_default 0x00000020
+#define regk_gio_rw_i2c0_ctrl_default 0x00010000
+#define regk_gio_rw_i2c0_start_default 0x00000000
+#define regk_gio_rw_i2c1_cfg_default 0x00000aa0
+#define regk_gio_rw_i2c1_ctrl_default 0x00010000
+#define regk_gio_rw_i2c1_start_default 0x00000000
+#define regk_gio_rw_intr_cfg_default 0x00000000
+#define regk_gio_rw_intr_mask_default 0x00000000
+#define regk_gio_rw_pa_oe_default 0x00000000
+#define regk_gio_rw_pb_oe_default 0x00000000
+#define regk_gio_rw_pc_oe_default 0x00000000
+#define regk_gio_rw_ppwm_data_default 0x00000000
+#define regk_gio_rw_pwm0_ctrl_default 0x00000000
+#define regk_gio_rw_pwm1_ctrl_default 0x00000000
+#define regk_gio_rw_pwm2_ctrl_default 0x00000000
+#define regk_gio_rw_pwm_in_cfg_default 0x00000000
+#define regk_gio_sda0 0x00000000
+#define regk_gio_sda1 0x00000001
+#define regk_gio_sda2 0x00000002
+#define regk_gio_sda3 0x00000003
+#define regk_gio_sen 0x00000000
+#define regk_gio_set 0x00000003
+#define regk_gio_yes 0x00000001
+#endif /* __gio_defs_asm_h */
--- /dev/null
+#ifndef __pinmux_defs_asm_h
+#define __pinmux_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: pinmux.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pinmux_defs_asm.h pinmux.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_hwprot, scope pinmux, type rw */
+#define reg_pinmux_rw_hwprot___eth___lsb 0
+#define reg_pinmux_rw_hwprot___eth___width 1
+#define reg_pinmux_rw_hwprot___eth___bit 0
+#define reg_pinmux_rw_hwprot___eth_mdio___lsb 1
+#define reg_pinmux_rw_hwprot___eth_mdio___width 1
+#define reg_pinmux_rw_hwprot___eth_mdio___bit 1
+#define reg_pinmux_rw_hwprot___geth___lsb 2
+#define reg_pinmux_rw_hwprot___geth___width 1
+#define reg_pinmux_rw_hwprot___geth___bit 2
+#define reg_pinmux_rw_hwprot___tg___lsb 3
+#define reg_pinmux_rw_hwprot___tg___width 1
+#define reg_pinmux_rw_hwprot___tg___bit 3
+#define reg_pinmux_rw_hwprot___tg_clk___lsb 4
+#define reg_pinmux_rw_hwprot___tg_clk___width 1
+#define reg_pinmux_rw_hwprot___tg_clk___bit 4
+#define reg_pinmux_rw_hwprot___vout___lsb 5
+#define reg_pinmux_rw_hwprot___vout___width 1
+#define reg_pinmux_rw_hwprot___vout___bit 5
+#define reg_pinmux_rw_hwprot___vout_sync___lsb 6
+#define reg_pinmux_rw_hwprot___vout_sync___width 1
+#define reg_pinmux_rw_hwprot___vout_sync___bit 6
+#define reg_pinmux_rw_hwprot___ser1___lsb 7
+#define reg_pinmux_rw_hwprot___ser1___width 1
+#define reg_pinmux_rw_hwprot___ser1___bit 7
+#define reg_pinmux_rw_hwprot___ser2___lsb 8
+#define reg_pinmux_rw_hwprot___ser2___width 1
+#define reg_pinmux_rw_hwprot___ser2___bit 8
+#define reg_pinmux_rw_hwprot___ser3___lsb 9
+#define reg_pinmux_rw_hwprot___ser3___width 1
+#define reg_pinmux_rw_hwprot___ser3___bit 9
+#define reg_pinmux_rw_hwprot___ser4___lsb 10
+#define reg_pinmux_rw_hwprot___ser4___width 1
+#define reg_pinmux_rw_hwprot___ser4___bit 10
+#define reg_pinmux_rw_hwprot___sser___lsb 11
+#define reg_pinmux_rw_hwprot___sser___width 1
+#define reg_pinmux_rw_hwprot___sser___bit 11
+#define reg_pinmux_rw_hwprot___pwm0___lsb 12
+#define reg_pinmux_rw_hwprot___pwm0___width 1
+#define reg_pinmux_rw_hwprot___pwm0___bit 12
+#define reg_pinmux_rw_hwprot___pwm1___lsb 13
+#define reg_pinmux_rw_hwprot___pwm1___width 1
+#define reg_pinmux_rw_hwprot___pwm1___bit 13
+#define reg_pinmux_rw_hwprot___pwm2___lsb 14
+#define reg_pinmux_rw_hwprot___pwm2___width 1
+#define reg_pinmux_rw_hwprot___pwm2___bit 14
+#define reg_pinmux_rw_hwprot___timer0___lsb 15
+#define reg_pinmux_rw_hwprot___timer0___width 1
+#define reg_pinmux_rw_hwprot___timer0___bit 15
+#define reg_pinmux_rw_hwprot___timer1___lsb 16
+#define reg_pinmux_rw_hwprot___timer1___width 1
+#define reg_pinmux_rw_hwprot___timer1___bit 16
+#define reg_pinmux_rw_hwprot___pio___lsb 17
+#define reg_pinmux_rw_hwprot___pio___width 1
+#define reg_pinmux_rw_hwprot___pio___bit 17
+#define reg_pinmux_rw_hwprot___i2c0___lsb 18
+#define reg_pinmux_rw_hwprot___i2c0___width 1
+#define reg_pinmux_rw_hwprot___i2c0___bit 18
+#define reg_pinmux_rw_hwprot___i2c1___lsb 19
+#define reg_pinmux_rw_hwprot___i2c1___width 1
+#define reg_pinmux_rw_hwprot___i2c1___bit 19
+#define reg_pinmux_rw_hwprot___i2c1_sda1___lsb 20
+#define reg_pinmux_rw_hwprot___i2c1_sda1___width 1
+#define reg_pinmux_rw_hwprot___i2c1_sda1___bit 20
+#define reg_pinmux_rw_hwprot___i2c1_sda2___lsb 21
+#define reg_pinmux_rw_hwprot___i2c1_sda2___width 1
+#define reg_pinmux_rw_hwprot___i2c1_sda2___bit 21
+#define reg_pinmux_rw_hwprot___i2c1_sda3___lsb 22
+#define reg_pinmux_rw_hwprot___i2c1_sda3___width 1
+#define reg_pinmux_rw_hwprot___i2c1_sda3___bit 22
+#define reg_pinmux_rw_hwprot___i2c1_sen___lsb 23
+#define reg_pinmux_rw_hwprot___i2c1_sen___width 1
+#define reg_pinmux_rw_hwprot___i2c1_sen___bit 23
+#define reg_pinmux_rw_hwprot_offset 0
+
+/* Register rw_gio_pa, scope pinmux, type rw */
+#define reg_pinmux_rw_gio_pa___pa0___lsb 0
+#define reg_pinmux_rw_gio_pa___pa0___width 1
+#define reg_pinmux_rw_gio_pa___pa0___bit 0
+#define reg_pinmux_rw_gio_pa___pa1___lsb 1
+#define reg_pinmux_rw_gio_pa___pa1___width 1
+#define reg_pinmux_rw_gio_pa___pa1___bit 1
+#define reg_pinmux_rw_gio_pa___pa2___lsb 2
+#define reg_pinmux_rw_gio_pa___pa2___width 1
+#define reg_pinmux_rw_gio_pa___pa2___bit 2
+#define reg_pinmux_rw_gio_pa___pa3___lsb 3
+#define reg_pinmux_rw_gio_pa___pa3___width 1
+#define reg_pinmux_rw_gio_pa___pa3___bit 3
+#define reg_pinmux_rw_gio_pa___pa4___lsb 4
+#define reg_pinmux_rw_gio_pa___pa4___width 1
+#define reg_pinmux_rw_gio_pa___pa4___bit 4
+#define reg_pinmux_rw_gio_pa___pa5___lsb 5
+#define reg_pinmux_rw_gio_pa___pa5___width 1
+#define reg_pinmux_rw_gio_pa___pa5___bit 5
+#define reg_pinmux_rw_gio_pa___pa6___lsb 6
+#define reg_pinmux_rw_gio_pa___pa6___width 1
+#define reg_pinmux_rw_gio_pa___pa6___bit 6
+#define reg_pinmux_rw_gio_pa___pa7___lsb 7
+#define reg_pinmux_rw_gio_pa___pa7___width 1
+#define reg_pinmux_rw_gio_pa___pa7___bit 7
+#define reg_pinmux_rw_gio_pa___pa8___lsb 8
+#define reg_pinmux_rw_gio_pa___pa8___width 1
+#define reg_pinmux_rw_gio_pa___pa8___bit 8
+#define reg_pinmux_rw_gio_pa___pa9___lsb 9
+#define reg_pinmux_rw_gio_pa___pa9___width 1
+#define reg_pinmux_rw_gio_pa___pa9___bit 9
+#define reg_pinmux_rw_gio_pa___pa10___lsb 10
+#define reg_pinmux_rw_gio_pa___pa10___width 1
+#define reg_pinmux_rw_gio_pa___pa10___bit 10
+#define reg_pinmux_rw_gio_pa___pa11___lsb 11
+#define reg_pinmux_rw_gio_pa___pa11___width 1
+#define reg_pinmux_rw_gio_pa___pa11___bit 11
+#define reg_pinmux_rw_gio_pa___pa12___lsb 12
+#define reg_pinmux_rw_gio_pa___pa12___width 1
+#define reg_pinmux_rw_gio_pa___pa12___bit 12
+#define reg_pinmux_rw_gio_pa___pa13___lsb 13
+#define reg_pinmux_rw_gio_pa___pa13___width 1
+#define reg_pinmux_rw_gio_pa___pa13___bit 13
+#define reg_pinmux_rw_gio_pa___pa14___lsb 14
+#define reg_pinmux_rw_gio_pa___pa14___width 1
+#define reg_pinmux_rw_gio_pa___pa14___bit 14
+#define reg_pinmux_rw_gio_pa___pa15___lsb 15
+#define reg_pinmux_rw_gio_pa___pa15___width 1
+#define reg_pinmux_rw_gio_pa___pa15___bit 15
+#define reg_pinmux_rw_gio_pa___pa16___lsb 16
+#define reg_pinmux_rw_gio_pa___pa16___width 1
+#define reg_pinmux_rw_gio_pa___pa16___bit 16
+#define reg_pinmux_rw_gio_pa___pa17___lsb 17
+#define reg_pinmux_rw_gio_pa___pa17___width 1
+#define reg_pinmux_rw_gio_pa___pa17___bit 17
+#define reg_pinmux_rw_gio_pa___pa18___lsb 18
+#define reg_pinmux_rw_gio_pa___pa18___width 1
+#define reg_pinmux_rw_gio_pa___pa18___bit 18
+#define reg_pinmux_rw_gio_pa___pa19___lsb 19
+#define reg_pinmux_rw_gio_pa___pa19___width 1
+#define reg_pinmux_rw_gio_pa___pa19___bit 19
+#define reg_pinmux_rw_gio_pa___pa20___lsb 20
+#define reg_pinmux_rw_gio_pa___pa20___width 1
+#define reg_pinmux_rw_gio_pa___pa20___bit 20
+#define reg_pinmux_rw_gio_pa___pa21___lsb 21
+#define reg_pinmux_rw_gio_pa___pa21___width 1
+#define reg_pinmux_rw_gio_pa___pa21___bit 21
+#define reg_pinmux_rw_gio_pa___pa22___lsb 22
+#define reg_pinmux_rw_gio_pa___pa22___width 1
+#define reg_pinmux_rw_gio_pa___pa22___bit 22
+#define reg_pinmux_rw_gio_pa___pa23___lsb 23
+#define reg_pinmux_rw_gio_pa___pa23___width 1
+#define reg_pinmux_rw_gio_pa___pa23___bit 23
+#define reg_pinmux_rw_gio_pa___pa24___lsb 24
+#define reg_pinmux_rw_gio_pa___pa24___width 1
+#define reg_pinmux_rw_gio_pa___pa24___bit 24
+#define reg_pinmux_rw_gio_pa___pa25___lsb 25
+#define reg_pinmux_rw_gio_pa___pa25___width 1
+#define reg_pinmux_rw_gio_pa___pa25___bit 25
+#define reg_pinmux_rw_gio_pa___pa26___lsb 26
+#define reg_pinmux_rw_gio_pa___pa26___width 1
+#define reg_pinmux_rw_gio_pa___pa26___bit 26
+#define reg_pinmux_rw_gio_pa___pa27___lsb 27
+#define reg_pinmux_rw_gio_pa___pa27___width 1
+#define reg_pinmux_rw_gio_pa___pa27___bit 27
+#define reg_pinmux_rw_gio_pa___pa28___lsb 28
+#define reg_pinmux_rw_gio_pa___pa28___width 1
+#define reg_pinmux_rw_gio_pa___pa28___bit 28
+#define reg_pinmux_rw_gio_pa___pa29___lsb 29
+#define reg_pinmux_rw_gio_pa___pa29___width 1
+#define reg_pinmux_rw_gio_pa___pa29___bit 29
+#define reg_pinmux_rw_gio_pa___pa30___lsb 30
+#define reg_pinmux_rw_gio_pa___pa30___width 1
+#define reg_pinmux_rw_gio_pa___pa30___bit 30
+#define reg_pinmux_rw_gio_pa___pa31___lsb 31
+#define reg_pinmux_rw_gio_pa___pa31___width 1
+#define reg_pinmux_rw_gio_pa___pa31___bit 31
+#define reg_pinmux_rw_gio_pa_offset 4
+
+/* Register rw_gio_pb, scope pinmux, type rw */
+#define reg_pinmux_rw_gio_pb___pb0___lsb 0
+#define reg_pinmux_rw_gio_pb___pb0___width 1
+#define reg_pinmux_rw_gio_pb___pb0___bit 0
+#define reg_pinmux_rw_gio_pb___pb1___lsb 1
+#define reg_pinmux_rw_gio_pb___pb1___width 1
+#define reg_pinmux_rw_gio_pb___pb1___bit 1
+#define reg_pinmux_rw_gio_pb___pb2___lsb 2
+#define reg_pinmux_rw_gio_pb___pb2___width 1
+#define reg_pinmux_rw_gio_pb___pb2___bit 2
+#define reg_pinmux_rw_gio_pb___pb3___lsb 3
+#define reg_pinmux_rw_gio_pb___pb3___width 1
+#define reg_pinmux_rw_gio_pb___pb3___bit 3
+#define reg_pinmux_rw_gio_pb___pb4___lsb 4
+#define reg_pinmux_rw_gio_pb___pb4___width 1
+#define reg_pinmux_rw_gio_pb___pb4___bit 4
+#define reg_pinmux_rw_gio_pb___pb5___lsb 5
+#define reg_pinmux_rw_gio_pb___pb5___width 1
+#define reg_pinmux_rw_gio_pb___pb5___bit 5
+#define reg_pinmux_rw_gio_pb___pb6___lsb 6
+#define reg_pinmux_rw_gio_pb___pb6___width 1
+#define reg_pinmux_rw_gio_pb___pb6___bit 6
+#define reg_pinmux_rw_gio_pb___pb7___lsb 7
+#define reg_pinmux_rw_gio_pb___pb7___width 1
+#define reg_pinmux_rw_gio_pb___pb7___bit 7
+#define reg_pinmux_rw_gio_pb___pb8___lsb 8
+#define reg_pinmux_rw_gio_pb___pb8___width 1
+#define reg_pinmux_rw_gio_pb___pb8___bit 8
+#define reg_pinmux_rw_gio_pb___pb9___lsb 9
+#define reg_pinmux_rw_gio_pb___pb9___width 1
+#define reg_pinmux_rw_gio_pb___pb9___bit 9
+#define reg_pinmux_rw_gio_pb___pb10___lsb 10
+#define reg_pinmux_rw_gio_pb___pb10___width 1
+#define reg_pinmux_rw_gio_pb___pb10___bit 10
+#define reg_pinmux_rw_gio_pb___pb11___lsb 11
+#define reg_pinmux_rw_gio_pb___pb11___width 1
+#define reg_pinmux_rw_gio_pb___pb11___bit 11
+#define reg_pinmux_rw_gio_pb___pb12___lsb 12
+#define reg_pinmux_rw_gio_pb___pb12___width 1
+#define reg_pinmux_rw_gio_pb___pb12___bit 12
+#define reg_pinmux_rw_gio_pb___pb13___lsb 13
+#define reg_pinmux_rw_gio_pb___pb13___width 1
+#define reg_pinmux_rw_gio_pb___pb13___bit 13
+#define reg_pinmux_rw_gio_pb___pb14___lsb 14
+#define reg_pinmux_rw_gio_pb___pb14___width 1
+#define reg_pinmux_rw_gio_pb___pb14___bit 14
+#define reg_pinmux_rw_gio_pb___pb15___lsb 15
+#define reg_pinmux_rw_gio_pb___pb15___width 1
+#define reg_pinmux_rw_gio_pb___pb15___bit 15
+#define reg_pinmux_rw_gio_pb___pb16___lsb 16
+#define reg_pinmux_rw_gio_pb___pb16___width 1
+#define reg_pinmux_rw_gio_pb___pb16___bit 16
+#define reg_pinmux_rw_gio_pb___pb17___lsb 17
+#define reg_pinmux_rw_gio_pb___pb17___width 1
+#define reg_pinmux_rw_gio_pb___pb17___bit 17
+#define reg_pinmux_rw_gio_pb___pb18___lsb 18
+#define reg_pinmux_rw_gio_pb___pb18___width 1
+#define reg_pinmux_rw_gio_pb___pb18___bit 18
+#define reg_pinmux_rw_gio_pb___pb19___lsb 19
+#define reg_pinmux_rw_gio_pb___pb19___width 1
+#define reg_pinmux_rw_gio_pb___pb19___bit 19
+#define reg_pinmux_rw_gio_pb___pb20___lsb 20
+#define reg_pinmux_rw_gio_pb___pb20___width 1
+#define reg_pinmux_rw_gio_pb___pb20___bit 20
+#define reg_pinmux_rw_gio_pb___pb21___lsb 21
+#define reg_pinmux_rw_gio_pb___pb21___width 1
+#define reg_pinmux_rw_gio_pb___pb21___bit 21
+#define reg_pinmux_rw_gio_pb___pb22___lsb 22
+#define reg_pinmux_rw_gio_pb___pb22___width 1
+#define reg_pinmux_rw_gio_pb___pb22___bit 22
+#define reg_pinmux_rw_gio_pb___pb23___lsb 23
+#define reg_pinmux_rw_gio_pb___pb23___width 1
+#define reg_pinmux_rw_gio_pb___pb23___bit 23
+#define reg_pinmux_rw_gio_pb___pb24___lsb 24
+#define reg_pinmux_rw_gio_pb___pb24___width 1
+#define reg_pinmux_rw_gio_pb___pb24___bit 24
+#define reg_pinmux_rw_gio_pb___pb25___lsb 25
+#define reg_pinmux_rw_gio_pb___pb25___width 1
+#define reg_pinmux_rw_gio_pb___pb25___bit 25
+#define reg_pinmux_rw_gio_pb___pb26___lsb 26
+#define reg_pinmux_rw_gio_pb___pb26___width 1
+#define reg_pinmux_rw_gio_pb___pb26___bit 26
+#define reg_pinmux_rw_gio_pb___pb27___lsb 27
+#define reg_pinmux_rw_gio_pb___pb27___width 1
+#define reg_pinmux_rw_gio_pb___pb27___bit 27
+#define reg_pinmux_rw_gio_pb___pb28___lsb 28
+#define reg_pinmux_rw_gio_pb___pb28___width 1
+#define reg_pinmux_rw_gio_pb___pb28___bit 28
+#define reg_pinmux_rw_gio_pb___pb29___lsb 29
+#define reg_pinmux_rw_gio_pb___pb29___width 1
+#define reg_pinmux_rw_gio_pb___pb29___bit 29
+#define reg_pinmux_rw_gio_pb___pb30___lsb 30
+#define reg_pinmux_rw_gio_pb___pb30___width 1
+#define reg_pinmux_rw_gio_pb___pb30___bit 30
+#define reg_pinmux_rw_gio_pb___pb31___lsb 31
+#define reg_pinmux_rw_gio_pb___pb31___width 1
+#define reg_pinmux_rw_gio_pb___pb31___bit 31
+#define reg_pinmux_rw_gio_pb_offset 8
+
+/* Register rw_gio_pc, scope pinmux, type rw */
+#define reg_pinmux_rw_gio_pc___pc0___lsb 0
+#define reg_pinmux_rw_gio_pc___pc0___width 1
+#define reg_pinmux_rw_gio_pc___pc0___bit 0
+#define reg_pinmux_rw_gio_pc___pc1___lsb 1
+#define reg_pinmux_rw_gio_pc___pc1___width 1
+#define reg_pinmux_rw_gio_pc___pc1___bit 1
+#define reg_pinmux_rw_gio_pc___pc2___lsb 2
+#define reg_pinmux_rw_gio_pc___pc2___width 1
+#define reg_pinmux_rw_gio_pc___pc2___bit 2
+#define reg_pinmux_rw_gio_pc___pc3___lsb 3
+#define reg_pinmux_rw_gio_pc___pc3___width 1
+#define reg_pinmux_rw_gio_pc___pc3___bit 3
+#define reg_pinmux_rw_gio_pc___pc4___lsb 4
+#define reg_pinmux_rw_gio_pc___pc4___width 1
+#define reg_pinmux_rw_gio_pc___pc4___bit 4
+#define reg_pinmux_rw_gio_pc___pc5___lsb 5
+#define reg_pinmux_rw_gio_pc___pc5___width 1
+#define reg_pinmux_rw_gio_pc___pc5___bit 5
+#define reg_pinmux_rw_gio_pc___pc6___lsb 6
+#define reg_pinmux_rw_gio_pc___pc6___width 1
+#define reg_pinmux_rw_gio_pc___pc6___bit 6
+#define reg_pinmux_rw_gio_pc___pc7___lsb 7
+#define reg_pinmux_rw_gio_pc___pc7___width 1
+#define reg_pinmux_rw_gio_pc___pc7___bit 7
+#define reg_pinmux_rw_gio_pc___pc8___lsb 8
+#define reg_pinmux_rw_gio_pc___pc8___width 1
+#define reg_pinmux_rw_gio_pc___pc8___bit 8
+#define reg_pinmux_rw_gio_pc___pc9___lsb 9
+#define reg_pinmux_rw_gio_pc___pc9___width 1
+#define reg_pinmux_rw_gio_pc___pc9___bit 9
+#define reg_pinmux_rw_gio_pc___pc10___lsb 10
+#define reg_pinmux_rw_gio_pc___pc10___width 1
+#define reg_pinmux_rw_gio_pc___pc10___bit 10
+#define reg_pinmux_rw_gio_pc___pc11___lsb 11
+#define reg_pinmux_rw_gio_pc___pc11___width 1
+#define reg_pinmux_rw_gio_pc___pc11___bit 11
+#define reg_pinmux_rw_gio_pc___pc12___lsb 12
+#define reg_pinmux_rw_gio_pc___pc12___width 1
+#define reg_pinmux_rw_gio_pc___pc12___bit 12
+#define reg_pinmux_rw_gio_pc___pc13___lsb 13
+#define reg_pinmux_rw_gio_pc___pc13___width 1
+#define reg_pinmux_rw_gio_pc___pc13___bit 13
+#define reg_pinmux_rw_gio_pc___pc14___lsb 14
+#define reg_pinmux_rw_gio_pc___pc14___width 1
+#define reg_pinmux_rw_gio_pc___pc14___bit 14
+#define reg_pinmux_rw_gio_pc___pc15___lsb 15
+#define reg_pinmux_rw_gio_pc___pc15___width 1
+#define reg_pinmux_rw_gio_pc___pc15___bit 15
+#define reg_pinmux_rw_gio_pc_offset 12
+
+/* Register rw_iop_pa, scope pinmux, type rw */
+#define reg_pinmux_rw_iop_pa___pa0___lsb 0
+#define reg_pinmux_rw_iop_pa___pa0___width 1
+#define reg_pinmux_rw_iop_pa___pa0___bit 0
+#define reg_pinmux_rw_iop_pa___pa1___lsb 1
+#define reg_pinmux_rw_iop_pa___pa1___width 1
+#define reg_pinmux_rw_iop_pa___pa1___bit 1
+#define reg_pinmux_rw_iop_pa___pa2___lsb 2
+#define reg_pinmux_rw_iop_pa___pa2___width 1
+#define reg_pinmux_rw_iop_pa___pa2___bit 2
+#define reg_pinmux_rw_iop_pa___pa3___lsb 3
+#define reg_pinmux_rw_iop_pa___pa3___width 1
+#define reg_pinmux_rw_iop_pa___pa3___bit 3
+#define reg_pinmux_rw_iop_pa___pa4___lsb 4
+#define reg_pinmux_rw_iop_pa___pa4___width 1
+#define reg_pinmux_rw_iop_pa___pa4___bit 4
+#define reg_pinmux_rw_iop_pa___pa5___lsb 5
+#define reg_pinmux_rw_iop_pa___pa5___width 1
+#define reg_pinmux_rw_iop_pa___pa5___bit 5
+#define reg_pinmux_rw_iop_pa___pa6___lsb 6
+#define reg_pinmux_rw_iop_pa___pa6___width 1
+#define reg_pinmux_rw_iop_pa___pa6___bit 6
+#define reg_pinmux_rw_iop_pa___pa7___lsb 7
+#define reg_pinmux_rw_iop_pa___pa7___width 1
+#define reg_pinmux_rw_iop_pa___pa7___bit 7
+#define reg_pinmux_rw_iop_pa___pa8___lsb 8
+#define reg_pinmux_rw_iop_pa___pa8___width 1
+#define reg_pinmux_rw_iop_pa___pa8___bit 8
+#define reg_pinmux_rw_iop_pa___pa9___lsb 9
+#define reg_pinmux_rw_iop_pa___pa9___width 1
+#define reg_pinmux_rw_iop_pa___pa9___bit 9
+#define reg_pinmux_rw_iop_pa___pa10___lsb 10
+#define reg_pinmux_rw_iop_pa___pa10___width 1
+#define reg_pinmux_rw_iop_pa___pa10___bit 10
+#define reg_pinmux_rw_iop_pa___pa11___lsb 11
+#define reg_pinmux_rw_iop_pa___pa11___width 1
+#define reg_pinmux_rw_iop_pa___pa11___bit 11
+#define reg_pinmux_rw_iop_pa___pa12___lsb 12
+#define reg_pinmux_rw_iop_pa___pa12___width 1
+#define reg_pinmux_rw_iop_pa___pa12___bit 12
+#define reg_pinmux_rw_iop_pa___pa13___lsb 13
+#define reg_pinmux_rw_iop_pa___pa13___width 1
+#define reg_pinmux_rw_iop_pa___pa13___bit 13
+#define reg_pinmux_rw_iop_pa___pa14___lsb 14
+#define reg_pinmux_rw_iop_pa___pa14___width 1
+#define reg_pinmux_rw_iop_pa___pa14___bit 14
+#define reg_pinmux_rw_iop_pa___pa15___lsb 15
+#define reg_pinmux_rw_iop_pa___pa15___width 1
+#define reg_pinmux_rw_iop_pa___pa15___bit 15
+#define reg_pinmux_rw_iop_pa___pa16___lsb 16
+#define reg_pinmux_rw_iop_pa___pa16___width 1
+#define reg_pinmux_rw_iop_pa___pa16___bit 16
+#define reg_pinmux_rw_iop_pa___pa17___lsb 17
+#define reg_pinmux_rw_iop_pa___pa17___width 1
+#define reg_pinmux_rw_iop_pa___pa17___bit 17
+#define reg_pinmux_rw_iop_pa___pa18___lsb 18
+#define reg_pinmux_rw_iop_pa___pa18___width 1
+#define reg_pinmux_rw_iop_pa___pa18___bit 18
+#define reg_pinmux_rw_iop_pa___pa19___lsb 19
+#define reg_pinmux_rw_iop_pa___pa19___width 1
+#define reg_pinmux_rw_iop_pa___pa19___bit 19
+#define reg_pinmux_rw_iop_pa___pa20___lsb 20
+#define reg_pinmux_rw_iop_pa___pa20___width 1
+#define reg_pinmux_rw_iop_pa___pa20___bit 20
+#define reg_pinmux_rw_iop_pa___pa21___lsb 21
+#define reg_pinmux_rw_iop_pa___pa21___width 1
+#define reg_pinmux_rw_iop_pa___pa21___bit 21
+#define reg_pinmux_rw_iop_pa___pa22___lsb 22
+#define reg_pinmux_rw_iop_pa___pa22___width 1
+#define reg_pinmux_rw_iop_pa___pa22___bit 22
+#define reg_pinmux_rw_iop_pa___pa23___lsb 23
+#define reg_pinmux_rw_iop_pa___pa23___width 1
+#define reg_pinmux_rw_iop_pa___pa23___bit 23
+#define reg_pinmux_rw_iop_pa___pa24___lsb 24
+#define reg_pinmux_rw_iop_pa___pa24___width 1
+#define reg_pinmux_rw_iop_pa___pa24___bit 24
+#define reg_pinmux_rw_iop_pa___pa25___lsb 25
+#define reg_pinmux_rw_iop_pa___pa25___width 1
+#define reg_pinmux_rw_iop_pa___pa25___bit 25
+#define reg_pinmux_rw_iop_pa___pa26___lsb 26
+#define reg_pinmux_rw_iop_pa___pa26___width 1
+#define reg_pinmux_rw_iop_pa___pa26___bit 26
+#define reg_pinmux_rw_iop_pa___pa27___lsb 27
+#define reg_pinmux_rw_iop_pa___pa27___width 1
+#define reg_pinmux_rw_iop_pa___pa27___bit 27
+#define reg_pinmux_rw_iop_pa___pa28___lsb 28
+#define reg_pinmux_rw_iop_pa___pa28___width 1
+#define reg_pinmux_rw_iop_pa___pa28___bit 28
+#define reg_pinmux_rw_iop_pa___pa29___lsb 29
+#define reg_pinmux_rw_iop_pa___pa29___width 1
+#define reg_pinmux_rw_iop_pa___pa29___bit 29
+#define reg_pinmux_rw_iop_pa___pa30___lsb 30
+#define reg_pinmux_rw_iop_pa___pa30___width 1
+#define reg_pinmux_rw_iop_pa___pa30___bit 30
+#define reg_pinmux_rw_iop_pa___pa31___lsb 31
+#define reg_pinmux_rw_iop_pa___pa31___width 1
+#define reg_pinmux_rw_iop_pa___pa31___bit 31
+#define reg_pinmux_rw_iop_pa_offset 16
+
+/* Register rw_iop_pb, scope pinmux, type rw */
+#define reg_pinmux_rw_iop_pb___pb0___lsb 0
+#define reg_pinmux_rw_iop_pb___pb0___width 1
+#define reg_pinmux_rw_iop_pb___pb0___bit 0
+#define reg_pinmux_rw_iop_pb___pb1___lsb 1
+#define reg_pinmux_rw_iop_pb___pb1___width 1
+#define reg_pinmux_rw_iop_pb___pb1___bit 1
+#define reg_pinmux_rw_iop_pb___pb2___lsb 2
+#define reg_pinmux_rw_iop_pb___pb2___width 1
+#define reg_pinmux_rw_iop_pb___pb2___bit 2
+#define reg_pinmux_rw_iop_pb___pb3___lsb 3
+#define reg_pinmux_rw_iop_pb___pb3___width 1
+#define reg_pinmux_rw_iop_pb___pb3___bit 3
+#define reg_pinmux_rw_iop_pb___pb4___lsb 4
+#define reg_pinmux_rw_iop_pb___pb4___width 1
+#define reg_pinmux_rw_iop_pb___pb4___bit 4
+#define reg_pinmux_rw_iop_pb___pb5___lsb 5
+#define reg_pinmux_rw_iop_pb___pb5___width 1
+#define reg_pinmux_rw_iop_pb___pb5___bit 5
+#define reg_pinmux_rw_iop_pb___pb6___lsb 6
+#define reg_pinmux_rw_iop_pb___pb6___width 1
+#define reg_pinmux_rw_iop_pb___pb6___bit 6
+#define reg_pinmux_rw_iop_pb___pb7___lsb 7
+#define reg_pinmux_rw_iop_pb___pb7___width 1
+#define reg_pinmux_rw_iop_pb___pb7___bit 7
+#define reg_pinmux_rw_iop_pb_offset 20
+
+/* Register rw_iop_pio, scope pinmux, type rw */
+#define reg_pinmux_rw_iop_pio___d0___lsb 0
+#define reg_pinmux_rw_iop_pio___d0___width 1
+#define reg_pinmux_rw_iop_pio___d0___bit 0
+#define reg_pinmux_rw_iop_pio___d1___lsb 1
+#define reg_pinmux_rw_iop_pio___d1___width 1
+#define reg_pinmux_rw_iop_pio___d1___bit 1
+#define reg_pinmux_rw_iop_pio___d2___lsb 2
+#define reg_pinmux_rw_iop_pio___d2___width 1
+#define reg_pinmux_rw_iop_pio___d2___bit 2
+#define reg_pinmux_rw_iop_pio___d3___lsb 3
+#define reg_pinmux_rw_iop_pio___d3___width 1
+#define reg_pinmux_rw_iop_pio___d3___bit 3
+#define reg_pinmux_rw_iop_pio___d4___lsb 4
+#define reg_pinmux_rw_iop_pio___d4___width 1
+#define reg_pinmux_rw_iop_pio___d4___bit 4
+#define reg_pinmux_rw_iop_pio___d5___lsb 5
+#define reg_pinmux_rw_iop_pio___d5___width 1
+#define reg_pinmux_rw_iop_pio___d5___bit 5
+#define reg_pinmux_rw_iop_pio___d6___lsb 6
+#define reg_pinmux_rw_iop_pio___d6___width 1
+#define reg_pinmux_rw_iop_pio___d6___bit 6
+#define reg_pinmux_rw_iop_pio___d7___lsb 7
+#define reg_pinmux_rw_iop_pio___d7___width 1
+#define reg_pinmux_rw_iop_pio___d7___bit 7
+#define reg_pinmux_rw_iop_pio___rd_n___lsb 8
+#define reg_pinmux_rw_iop_pio___rd_n___width 1
+#define reg_pinmux_rw_iop_pio___rd_n___bit 8
+#define reg_pinmux_rw_iop_pio___wr_n___lsb 9
+#define reg_pinmux_rw_iop_pio___wr_n___width 1
+#define reg_pinmux_rw_iop_pio___wr_n___bit 9
+#define reg_pinmux_rw_iop_pio___a0___lsb 10
+#define reg_pinmux_rw_iop_pio___a0___width 1
+#define reg_pinmux_rw_iop_pio___a0___bit 10
+#define reg_pinmux_rw_iop_pio___a1___lsb 11
+#define reg_pinmux_rw_iop_pio___a1___width 1
+#define reg_pinmux_rw_iop_pio___a1___bit 11
+#define reg_pinmux_rw_iop_pio___ce0_n___lsb 12
+#define reg_pinmux_rw_iop_pio___ce0_n___width 1
+#define reg_pinmux_rw_iop_pio___ce0_n___bit 12
+#define reg_pinmux_rw_iop_pio___ce1_n___lsb 13
+#define reg_pinmux_rw_iop_pio___ce1_n___width 1
+#define reg_pinmux_rw_iop_pio___ce1_n___bit 13
+#define reg_pinmux_rw_iop_pio___ce2_n___lsb 14
+#define reg_pinmux_rw_iop_pio___ce2_n___width 1
+#define reg_pinmux_rw_iop_pio___ce2_n___bit 14
+#define reg_pinmux_rw_iop_pio___rdy___lsb 15
+#define reg_pinmux_rw_iop_pio___rdy___width 1
+#define reg_pinmux_rw_iop_pio___rdy___bit 15
+#define reg_pinmux_rw_iop_pio_offset 24
+
+/* Register rw_iop_usb, scope pinmux, type rw */
+#define reg_pinmux_rw_iop_usb___usb0___lsb 0
+#define reg_pinmux_rw_iop_usb___usb0___width 1
+#define reg_pinmux_rw_iop_usb___usb0___bit 0
+#define reg_pinmux_rw_iop_usb_offset 28
+
+
+/* Constants */
+#define regk_pinmux_no 0x00000000
+#define regk_pinmux_rw_gio_pa_default 0x00000000
+#define regk_pinmux_rw_gio_pb_default 0x00000000
+#define regk_pinmux_rw_gio_pc_default 0x00000000
+#define regk_pinmux_rw_hwprot_default 0x00000000
+#define regk_pinmux_rw_iop_pa_default 0x00000000
+#define regk_pinmux_rw_iop_pb_default 0x00000000
+#define regk_pinmux_rw_iop_pio_default 0x00000000
+#define regk_pinmux_rw_iop_usb_default 0x00000001
+#define regk_pinmux_yes 0x00000001
+#endif /* __pinmux_defs_asm_h */
--- /dev/null
+#ifndef __pio_defs_asm_h
+#define __pio_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: pio.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile pio_defs_asm.h pio.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_data, scope pio, type rw */
+#define reg_pio_rw_data_offset 64
+
+/* Register rw_io_access0, scope pio, type rw */
+#define reg_pio_rw_io_access0___data___lsb 0
+#define reg_pio_rw_io_access0___data___width 8
+#define reg_pio_rw_io_access0_offset 0
+
+/* Register rw_io_access1, scope pio, type rw */
+#define reg_pio_rw_io_access1___data___lsb 0
+#define reg_pio_rw_io_access1___data___width 8
+#define reg_pio_rw_io_access1_offset 4
+
+/* Register rw_io_access2, scope pio, type rw */
+#define reg_pio_rw_io_access2___data___lsb 0
+#define reg_pio_rw_io_access2___data___width 8
+#define reg_pio_rw_io_access2_offset 8
+
+/* Register rw_io_access3, scope pio, type rw */
+#define reg_pio_rw_io_access3___data___lsb 0
+#define reg_pio_rw_io_access3___data___width 8
+#define reg_pio_rw_io_access3_offset 12
+
+/* Register rw_io_access4, scope pio, type rw */
+#define reg_pio_rw_io_access4___data___lsb 0
+#define reg_pio_rw_io_access4___data___width 8
+#define reg_pio_rw_io_access4_offset 16
+
+/* Register rw_io_access5, scope pio, type rw */
+#define reg_pio_rw_io_access5___data___lsb 0
+#define reg_pio_rw_io_access5___data___width 8
+#define reg_pio_rw_io_access5_offset 20
+
+/* Register rw_io_access6, scope pio, type rw */
+#define reg_pio_rw_io_access6___data___lsb 0
+#define reg_pio_rw_io_access6___data___width 8
+#define reg_pio_rw_io_access6_offset 24
+
+/* Register rw_io_access7, scope pio, type rw */
+#define reg_pio_rw_io_access7___data___lsb 0
+#define reg_pio_rw_io_access7___data___width 8
+#define reg_pio_rw_io_access7_offset 28
+
+/* Register rw_io_access8, scope pio, type rw */
+#define reg_pio_rw_io_access8___data___lsb 0
+#define reg_pio_rw_io_access8___data___width 8
+#define reg_pio_rw_io_access8_offset 32
+
+/* Register rw_io_access9, scope pio, type rw */
+#define reg_pio_rw_io_access9___data___lsb 0
+#define reg_pio_rw_io_access9___data___width 8
+#define reg_pio_rw_io_access9_offset 36
+
+/* Register rw_io_access10, scope pio, type rw */
+#define reg_pio_rw_io_access10___data___lsb 0
+#define reg_pio_rw_io_access10___data___width 8
+#define reg_pio_rw_io_access10_offset 40
+
+/* Register rw_io_access11, scope pio, type rw */
+#define reg_pio_rw_io_access11___data___lsb 0
+#define reg_pio_rw_io_access11___data___width 8
+#define reg_pio_rw_io_access11_offset 44
+
+/* Register rw_io_access12, scope pio, type rw */
+#define reg_pio_rw_io_access12___data___lsb 0
+#define reg_pio_rw_io_access12___data___width 8
+#define reg_pio_rw_io_access12_offset 48
+
+/* Register rw_io_access13, scope pio, type rw */
+#define reg_pio_rw_io_access13___data___lsb 0
+#define reg_pio_rw_io_access13___data___width 8
+#define reg_pio_rw_io_access13_offset 52
+
+/* Register rw_io_access14, scope pio, type rw */
+#define reg_pio_rw_io_access14___data___lsb 0
+#define reg_pio_rw_io_access14___data___width 8
+#define reg_pio_rw_io_access14_offset 56
+
+/* Register rw_io_access15, scope pio, type rw */
+#define reg_pio_rw_io_access15___data___lsb 0
+#define reg_pio_rw_io_access15___data___width 8
+#define reg_pio_rw_io_access15_offset 60
+
+/* Register rw_ce0_cfg, scope pio, type rw */
+#define reg_pio_rw_ce0_cfg___lw___lsb 0
+#define reg_pio_rw_ce0_cfg___lw___width 6
+#define reg_pio_rw_ce0_cfg___ew___lsb 6
+#define reg_pio_rw_ce0_cfg___ew___width 3
+#define reg_pio_rw_ce0_cfg___zw___lsb 9
+#define reg_pio_rw_ce0_cfg___zw___width 3
+#define reg_pio_rw_ce0_cfg___aw___lsb 12
+#define reg_pio_rw_ce0_cfg___aw___width 2
+#define reg_pio_rw_ce0_cfg___mode___lsb 14
+#define reg_pio_rw_ce0_cfg___mode___width 2
+#define reg_pio_rw_ce0_cfg_offset 68
+
+/* Register rw_ce1_cfg, scope pio, type rw */
+#define reg_pio_rw_ce1_cfg___lw___lsb 0
+#define reg_pio_rw_ce1_cfg___lw___width 6
+#define reg_pio_rw_ce1_cfg___ew___lsb 6
+#define reg_pio_rw_ce1_cfg___ew___width 3
+#define reg_pio_rw_ce1_cfg___zw___lsb 9
+#define reg_pio_rw_ce1_cfg___zw___width 3
+#define reg_pio_rw_ce1_cfg___aw___lsb 12
+#define reg_pio_rw_ce1_cfg___aw___width 2
+#define reg_pio_rw_ce1_cfg___mode___lsb 14
+#define reg_pio_rw_ce1_cfg___mode___width 2
+#define reg_pio_rw_ce1_cfg_offset 72
+
+/* Register rw_ce2_cfg, scope pio, type rw */
+#define reg_pio_rw_ce2_cfg___lw___lsb 0
+#define reg_pio_rw_ce2_cfg___lw___width 6
+#define reg_pio_rw_ce2_cfg___ew___lsb 6
+#define reg_pio_rw_ce2_cfg___ew___width 3
+#define reg_pio_rw_ce2_cfg___zw___lsb 9
+#define reg_pio_rw_ce2_cfg___zw___width 3
+#define reg_pio_rw_ce2_cfg___aw___lsb 12
+#define reg_pio_rw_ce2_cfg___aw___width 2
+#define reg_pio_rw_ce2_cfg___mode___lsb 14
+#define reg_pio_rw_ce2_cfg___mode___width 2
+#define reg_pio_rw_ce2_cfg_offset 76
+
+/* Register rw_dout, scope pio, type rw */
+#define reg_pio_rw_dout___data___lsb 0
+#define reg_pio_rw_dout___data___width 8
+#define reg_pio_rw_dout___rd_n___lsb 8
+#define reg_pio_rw_dout___rd_n___width 1
+#define reg_pio_rw_dout___rd_n___bit 8
+#define reg_pio_rw_dout___wr_n___lsb 9
+#define reg_pio_rw_dout___wr_n___width 1
+#define reg_pio_rw_dout___wr_n___bit 9
+#define reg_pio_rw_dout___a0___lsb 10
+#define reg_pio_rw_dout___a0___width 1
+#define reg_pio_rw_dout___a0___bit 10
+#define reg_pio_rw_dout___a1___lsb 11
+#define reg_pio_rw_dout___a1___width 1
+#define reg_pio_rw_dout___a1___bit 11
+#define reg_pio_rw_dout___ce0_n___lsb 12
+#define reg_pio_rw_dout___ce0_n___width 1
+#define reg_pio_rw_dout___ce0_n___bit 12
+#define reg_pio_rw_dout___ce1_n___lsb 13
+#define reg_pio_rw_dout___ce1_n___width 1
+#define reg_pio_rw_dout___ce1_n___bit 13
+#define reg_pio_rw_dout___ce2_n___lsb 14
+#define reg_pio_rw_dout___ce2_n___width 1
+#define reg_pio_rw_dout___ce2_n___bit 14
+#define reg_pio_rw_dout___rdy___lsb 15
+#define reg_pio_rw_dout___rdy___width 1
+#define reg_pio_rw_dout___rdy___bit 15
+#define reg_pio_rw_dout_offset 80
+
+/* Register rw_oe, scope pio, type rw */
+#define reg_pio_rw_oe___data___lsb 0
+#define reg_pio_rw_oe___data___width 8
+#define reg_pio_rw_oe___rd_n___lsb 8
+#define reg_pio_rw_oe___rd_n___width 1
+#define reg_pio_rw_oe___rd_n___bit 8
+#define reg_pio_rw_oe___wr_n___lsb 9
+#define reg_pio_rw_oe___wr_n___width 1
+#define reg_pio_rw_oe___wr_n___bit 9
+#define reg_pio_rw_oe___a0___lsb 10
+#define reg_pio_rw_oe___a0___width 1
+#define reg_pio_rw_oe___a0___bit 10
+#define reg_pio_rw_oe___a1___lsb 11
+#define reg_pio_rw_oe___a1___width 1
+#define reg_pio_rw_oe___a1___bit 11
+#define reg_pio_rw_oe___ce0_n___lsb 12
+#define reg_pio_rw_oe___ce0_n___width 1
+#define reg_pio_rw_oe___ce0_n___bit 12
+#define reg_pio_rw_oe___ce1_n___lsb 13
+#define reg_pio_rw_oe___ce1_n___width 1
+#define reg_pio_rw_oe___ce1_n___bit 13
+#define reg_pio_rw_oe___ce2_n___lsb 14
+#define reg_pio_rw_oe___ce2_n___width 1
+#define reg_pio_rw_oe___ce2_n___bit 14
+#define reg_pio_rw_oe___rdy___lsb 15
+#define reg_pio_rw_oe___rdy___width 1
+#define reg_pio_rw_oe___rdy___bit 15
+#define reg_pio_rw_oe_offset 84
+
+/* Register rw_man_ctrl, scope pio, type rw */
+#define reg_pio_rw_man_ctrl___data___lsb 0
+#define reg_pio_rw_man_ctrl___data___width 8
+#define reg_pio_rw_man_ctrl___rd_n___lsb 8
+#define reg_pio_rw_man_ctrl___rd_n___width 1
+#define reg_pio_rw_man_ctrl___rd_n___bit 8
+#define reg_pio_rw_man_ctrl___wr_n___lsb 9
+#define reg_pio_rw_man_ctrl___wr_n___width 1
+#define reg_pio_rw_man_ctrl___wr_n___bit 9
+#define reg_pio_rw_man_ctrl___a0___lsb 10
+#define reg_pio_rw_man_ctrl___a0___width 1
+#define reg_pio_rw_man_ctrl___a0___bit 10
+#define reg_pio_rw_man_ctrl___a1___lsb 11
+#define reg_pio_rw_man_ctrl___a1___width 1
+#define reg_pio_rw_man_ctrl___a1___bit 11
+#define reg_pio_rw_man_ctrl___ce0_n___lsb 12
+#define reg_pio_rw_man_ctrl___ce0_n___width 1
+#define reg_pio_rw_man_ctrl___ce0_n___bit 12
+#define reg_pio_rw_man_ctrl___ce1_n___lsb 13
+#define reg_pio_rw_man_ctrl___ce1_n___width 1
+#define reg_pio_rw_man_ctrl___ce1_n___bit 13
+#define reg_pio_rw_man_ctrl___ce2_n___lsb 14
+#define reg_pio_rw_man_ctrl___ce2_n___width 1
+#define reg_pio_rw_man_ctrl___ce2_n___bit 14
+#define reg_pio_rw_man_ctrl___rdy___lsb 15
+#define reg_pio_rw_man_ctrl___rdy___width 1
+#define reg_pio_rw_man_ctrl___rdy___bit 15
+#define reg_pio_rw_man_ctrl_offset 88
+
+/* Register r_din, scope pio, type r */
+#define reg_pio_r_din___data___lsb 0
+#define reg_pio_r_din___data___width 8
+#define reg_pio_r_din___rd_n___lsb 8
+#define reg_pio_r_din___rd_n___width 1
+#define reg_pio_r_din___rd_n___bit 8
+#define reg_pio_r_din___wr_n___lsb 9
+#define reg_pio_r_din___wr_n___width 1
+#define reg_pio_r_din___wr_n___bit 9
+#define reg_pio_r_din___a0___lsb 10
+#define reg_pio_r_din___a0___width 1
+#define reg_pio_r_din___a0___bit 10
+#define reg_pio_r_din___a1___lsb 11
+#define reg_pio_r_din___a1___width 1
+#define reg_pio_r_din___a1___bit 11
+#define reg_pio_r_din___ce0_n___lsb 12
+#define reg_pio_r_din___ce0_n___width 1
+#define reg_pio_r_din___ce0_n___bit 12
+#define reg_pio_r_din___ce1_n___lsb 13
+#define reg_pio_r_din___ce1_n___width 1
+#define reg_pio_r_din___ce1_n___bit 13
+#define reg_pio_r_din___ce2_n___lsb 14
+#define reg_pio_r_din___ce2_n___width 1
+#define reg_pio_r_din___ce2_n___bit 14
+#define reg_pio_r_din___rdy___lsb 15
+#define reg_pio_r_din___rdy___width 1
+#define reg_pio_r_din___rdy___bit 15
+#define reg_pio_r_din_offset 92
+
+/* Register r_stat, scope pio, type r */
+#define reg_pio_r_stat___busy___lsb 0
+#define reg_pio_r_stat___busy___width 1
+#define reg_pio_r_stat___busy___bit 0
+#define reg_pio_r_stat_offset 96
+
+/* Register rw_intr_mask, scope pio, type rw */
+#define reg_pio_rw_intr_mask___rdy___lsb 0
+#define reg_pio_rw_intr_mask___rdy___width 1
+#define reg_pio_rw_intr_mask___rdy___bit 0
+#define reg_pio_rw_intr_mask_offset 100
+
+/* Register rw_ack_intr, scope pio, type rw */
+#define reg_pio_rw_ack_intr___rdy___lsb 0
+#define reg_pio_rw_ack_intr___rdy___width 1
+#define reg_pio_rw_ack_intr___rdy___bit 0
+#define reg_pio_rw_ack_intr_offset 104
+
+/* Register r_intr, scope pio, type r */
+#define reg_pio_r_intr___rdy___lsb 0
+#define reg_pio_r_intr___rdy___width 1
+#define reg_pio_r_intr___rdy___bit 0
+#define reg_pio_r_intr_offset 108
+
+/* Register r_masked_intr, scope pio, type r */
+#define reg_pio_r_masked_intr___rdy___lsb 0
+#define reg_pio_r_masked_intr___rdy___width 1
+#define reg_pio_r_masked_intr___rdy___bit 0
+#define reg_pio_r_masked_intr_offset 112
+
+
+/* Constants */
+#define regk_pio_a2 0x00000003
+#define regk_pio_no 0x00000000
+#define regk_pio_normal 0x00000000
+#define regk_pio_rd 0x00000001
+#define regk_pio_rw_ce0_cfg_default 0x00000000
+#define regk_pio_rw_ce1_cfg_default 0x00000000
+#define regk_pio_rw_ce2_cfg_default 0x00000000
+#define regk_pio_rw_intr_mask_default 0x00000000
+#define regk_pio_rw_man_ctrl_default 0x00000000
+#define regk_pio_rw_oe_default 0x00000000
+#define regk_pio_wr 0x00000002
+#define regk_pio_wr_ce2 0x00000003
+#define regk_pio_yes 0x00000001
+#define regk_pio_yes_all 0x000000ff
+#endif /* __pio_defs_asm_h */
--- /dev/null
+#ifndef __reg_map_asm_h
+#define __reg_map_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: reg.rmap
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map_asm.h reg.rmap
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+#define regi_ccd 0xb0000000
+#define regi_ccd_top 0xb0000000
+#define regi_ccd_dp 0xb0000400
+#define regi_ccd_stat 0xb0000800
+#define regi_ccd_tg 0xb0001000
+#define regi_cfg 0xb0002000
+#define regi_clkgen 0xb0004000
+#define regi_ddr2_ctrl 0xb0006000
+#define regi_dma0 0xb0008000
+#define regi_dma1 0xb000a000
+#define regi_dma11 0xb000c000
+#define regi_dma2 0xb000e000
+#define regi_dma3 0xb0010000
+#define regi_dma4 0xb0012000
+#define regi_dma5 0xb0014000
+#define regi_dma6 0xb0016000
+#define regi_dma7 0xb0018000
+#define regi_dma9 0xb001a000
+#define regi_eth 0xb001c000
+#define regi_gio 0xb0020000
+#define regi_h264 0xb0022000
+#define regi_hist 0xb0026000
+#define regi_iop 0xb0028000
+#define regi_iop_version 0xb0028000
+#define regi_iop_fifo_in_extra 0xb0028040
+#define regi_iop_fifo_out_extra 0xb0028080
+#define regi_iop_trigger_grp0 0xb00280c0
+#define regi_iop_trigger_grp1 0xb0028100
+#define regi_iop_trigger_grp2 0xb0028140
+#define regi_iop_trigger_grp3 0xb0028180
+#define regi_iop_trigger_grp4 0xb00281c0
+#define regi_iop_trigger_grp5 0xb0028200
+#define regi_iop_trigger_grp6 0xb0028240
+#define regi_iop_trigger_grp7 0xb0028280
+#define regi_iop_crc_par 0xb0028300
+#define regi_iop_dmc_in 0xb0028380
+#define regi_iop_dmc_out 0xb0028400
+#define regi_iop_fifo_in 0xb0028480
+#define regi_iop_fifo_out 0xb0028500
+#define regi_iop_scrc_in 0xb0028580
+#define regi_iop_scrc_out 0xb0028600
+#define regi_iop_timer_grp0 0xb0028680
+#define regi_iop_timer_grp1 0xb0028700
+#define regi_iop_sap_in 0xb0028800
+#define regi_iop_sap_out 0xb0028900
+#define regi_iop_spu 0xb0028a00
+#define regi_iop_sw_cfg 0xb0028b00
+#define regi_iop_sw_cpu 0xb0028c00
+#define regi_iop_sw_mpu 0xb0028d00
+#define regi_iop_sw_spu 0xb0028e00
+#define regi_iop_mpu 0xb0029000
+#define regi_irq 0xb002a000
+#define regi_jpeg 0xb002c000
+#define regi_l2cache 0xb0030000
+#define regi_marb_bar 0xb0032000
+#define regi_marb_bar_bp0 0xb0032140
+#define regi_marb_bar_bp1 0xb0032180
+#define regi_marb_bar_bp2 0xb00321c0
+#define regi_marb_bar_bp3 0xb0032200
+#define regi_marb_foo 0xb0034000
+#define regi_marb_foo_bp0 0xb0034280
+#define regi_marb_foo_bp1 0xb00342c0
+#define regi_marb_foo_bp2 0xb0034300
+#define regi_marb_foo_bp3 0xb0034340
+#define regi_pinmux 0xb0038000
+#define regi_pio 0xb0036000
+#define regi_sclr 0xb003a000
+#define regi_sclr_fifo 0xb003c000
+#define regi_ser0 0xb003e000
+#define regi_ser1 0xb0040000
+#define regi_ser2 0xb0042000
+#define regi_ser3 0xb0044000
+#define regi_ser4 0xb0046000
+#define regi_sser 0xb0048000
+#define regi_strcop 0xb004a000
+#define regi_strdma0 0xb004e000
+#define regi_strdma1 0xb0050000
+#define regi_strdma2 0xb0052000
+#define regi_strdma3 0xb0054000
+#define regi_strdma5 0xb0056000
+#define regi_strmux 0xb004c000
+#define regi_timer0 0xb0058000
+#define regi_timer1 0xb005a000
+#define regi_trace 0xb005c000
+#define regi_vin 0xb005e000
+#define regi_vout 0xb0060000
+#endif /* __reg_map_asm_h */
--- /dev/null
+#ifndef __timer_defs_asm_h
+#define __timer_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: timer.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile timer_defs_asm.h timer.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_tmr0_div, scope timer, type rw */
+#define reg_timer_rw_tmr0_div_offset 0
+
+/* Register r_tmr0_data, scope timer, type r */
+#define reg_timer_r_tmr0_data_offset 4
+
+/* Register rw_tmr0_ctrl, scope timer, type rw */
+#define reg_timer_rw_tmr0_ctrl___op___lsb 0
+#define reg_timer_rw_tmr0_ctrl___op___width 2
+#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
+#define reg_timer_rw_tmr0_ctrl___freq___width 3
+#define reg_timer_rw_tmr0_ctrl_offset 8
+
+/* Register rw_tmr1_div, scope timer, type rw */
+#define reg_timer_rw_tmr1_div_offset 16
+
+/* Register r_tmr1_data, scope timer, type r */
+#define reg_timer_r_tmr1_data_offset 20
+
+/* Register rw_tmr1_ctrl, scope timer, type rw */
+#define reg_timer_rw_tmr1_ctrl___op___lsb 0
+#define reg_timer_rw_tmr1_ctrl___op___width 2
+#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
+#define reg_timer_rw_tmr1_ctrl___freq___width 3
+#define reg_timer_rw_tmr1_ctrl_offset 24
+
+/* Register rs_cnt_data, scope timer, type rs */
+#define reg_timer_rs_cnt_data___tmr___lsb 0
+#define reg_timer_rs_cnt_data___tmr___width 24
+#define reg_timer_rs_cnt_data___cnt___lsb 24
+#define reg_timer_rs_cnt_data___cnt___width 8
+#define reg_timer_rs_cnt_data_offset 32
+
+/* Register r_cnt_data, scope timer, type r */
+#define reg_timer_r_cnt_data___tmr___lsb 0
+#define reg_timer_r_cnt_data___tmr___width 24
+#define reg_timer_r_cnt_data___cnt___lsb 24
+#define reg_timer_r_cnt_data___cnt___width 8
+#define reg_timer_r_cnt_data_offset 36
+
+/* Register rw_cnt_cfg, scope timer, type rw */
+#define reg_timer_rw_cnt_cfg___clk___lsb 0
+#define reg_timer_rw_cnt_cfg___clk___width 2
+#define reg_timer_rw_cnt_cfg_offset 40
+
+/* Register rw_trig, scope timer, type rw */
+#define reg_timer_rw_trig_offset 48
+
+/* Register rw_trig_cfg, scope timer, type rw */
+#define reg_timer_rw_trig_cfg___tmr___lsb 0
+#define reg_timer_rw_trig_cfg___tmr___width 2
+#define reg_timer_rw_trig_cfg_offset 52
+
+/* Register r_time, scope timer, type r */
+#define reg_timer_r_time_offset 56
+
+/* Register rw_out, scope timer, type rw */
+#define reg_timer_rw_out___tmr___lsb 0
+#define reg_timer_rw_out___tmr___width 2
+#define reg_timer_rw_out_offset 60
+
+/* Register rw_wd_ctrl, scope timer, type rw */
+#define reg_timer_rw_wd_ctrl___cnt___lsb 0
+#define reg_timer_rw_wd_ctrl___cnt___width 8
+#define reg_timer_rw_wd_ctrl___cmd___lsb 8
+#define reg_timer_rw_wd_ctrl___cmd___width 1
+#define reg_timer_rw_wd_ctrl___cmd___bit 8
+#define reg_timer_rw_wd_ctrl___key___lsb 9
+#define reg_timer_rw_wd_ctrl___key___width 7
+#define reg_timer_rw_wd_ctrl_offset 64
+
+/* Register r_wd_stat, scope timer, type r */
+#define reg_timer_r_wd_stat___cnt___lsb 0
+#define reg_timer_r_wd_stat___cnt___width 8
+#define reg_timer_r_wd_stat___cmd___lsb 8
+#define reg_timer_r_wd_stat___cmd___width 1
+#define reg_timer_r_wd_stat___cmd___bit 8
+#define reg_timer_r_wd_stat_offset 68
+
+/* Register rw_intr_mask, scope timer, type rw */
+#define reg_timer_rw_intr_mask___tmr0___lsb 0
+#define reg_timer_rw_intr_mask___tmr0___width 1
+#define reg_timer_rw_intr_mask___tmr0___bit 0
+#define reg_timer_rw_intr_mask___tmr1___lsb 1
+#define reg_timer_rw_intr_mask___tmr1___width 1
+#define reg_timer_rw_intr_mask___tmr1___bit 1
+#define reg_timer_rw_intr_mask___cnt___lsb 2
+#define reg_timer_rw_intr_mask___cnt___width 1
+#define reg_timer_rw_intr_mask___cnt___bit 2
+#define reg_timer_rw_intr_mask___trig___lsb 3
+#define reg_timer_rw_intr_mask___trig___width 1
+#define reg_timer_rw_intr_mask___trig___bit 3
+#define reg_timer_rw_intr_mask_offset 72
+
+/* Register rw_ack_intr, scope timer, type rw */
+#define reg_timer_rw_ack_intr___tmr0___lsb 0
+#define reg_timer_rw_ack_intr___tmr0___width 1
+#define reg_timer_rw_ack_intr___tmr0___bit 0
+#define reg_timer_rw_ack_intr___tmr1___lsb 1
+#define reg_timer_rw_ack_intr___tmr1___width 1
+#define reg_timer_rw_ack_intr___tmr1___bit 1
+#define reg_timer_rw_ack_intr___cnt___lsb 2
+#define reg_timer_rw_ack_intr___cnt___width 1
+#define reg_timer_rw_ack_intr___cnt___bit 2
+#define reg_timer_rw_ack_intr___trig___lsb 3
+#define reg_timer_rw_ack_intr___trig___width 1
+#define reg_timer_rw_ack_intr___trig___bit 3
+#define reg_timer_rw_ack_intr_offset 76
+
+/* Register r_intr, scope timer, type r */
+#define reg_timer_r_intr___tmr0___lsb 0
+#define reg_timer_r_intr___tmr0___width 1
+#define reg_timer_r_intr___tmr0___bit 0
+#define reg_timer_r_intr___tmr1___lsb 1
+#define reg_timer_r_intr___tmr1___width 1
+#define reg_timer_r_intr___tmr1___bit 1
+#define reg_timer_r_intr___cnt___lsb 2
+#define reg_timer_r_intr___cnt___width 1
+#define reg_timer_r_intr___cnt___bit 2
+#define reg_timer_r_intr___trig___lsb 3
+#define reg_timer_r_intr___trig___width 1
+#define reg_timer_r_intr___trig___bit 3
+#define reg_timer_r_intr_offset 80
+
+/* Register r_masked_intr, scope timer, type r */
+#define reg_timer_r_masked_intr___tmr0___lsb 0
+#define reg_timer_r_masked_intr___tmr0___width 1
+#define reg_timer_r_masked_intr___tmr0___bit 0
+#define reg_timer_r_masked_intr___tmr1___lsb 1
+#define reg_timer_r_masked_intr___tmr1___width 1
+#define reg_timer_r_masked_intr___tmr1___bit 1
+#define reg_timer_r_masked_intr___cnt___lsb 2
+#define reg_timer_r_masked_intr___cnt___width 1
+#define reg_timer_r_masked_intr___cnt___bit 2
+#define reg_timer_r_masked_intr___trig___lsb 3
+#define reg_timer_r_masked_intr___trig___width 1
+#define reg_timer_r_masked_intr___trig___bit 3
+#define reg_timer_r_masked_intr_offset 84
+
+/* Register rw_test, scope timer, type rw */
+#define reg_timer_rw_test___dis___lsb 0
+#define reg_timer_rw_test___dis___width 1
+#define reg_timer_rw_test___dis___bit 0
+#define reg_timer_rw_test___en___lsb 1
+#define reg_timer_rw_test___en___width 1
+#define reg_timer_rw_test___en___bit 1
+#define reg_timer_rw_test_offset 88
+
+
+/* Constants */
+#define regk_timer_ext 0x00000001
+#define regk_timer_f100 0x00000007
+#define regk_timer_f29_493 0x00000004
+#define regk_timer_f32 0x00000005
+#define regk_timer_f32_768 0x00000006
+#define regk_timer_f90 0x00000003
+#define regk_timer_hold 0x00000001
+#define regk_timer_ld 0x00000000
+#define regk_timer_no 0x00000000
+#define regk_timer_off 0x00000000
+#define regk_timer_run 0x00000002
+#define regk_timer_rw_cnt_cfg_default 0x00000000
+#define regk_timer_rw_intr_mask_default 0x00000000
+#define regk_timer_rw_out_default 0x00000000
+#define regk_timer_rw_test_default 0x00000000
+#define regk_timer_rw_tmr0_ctrl_default 0x00000000
+#define regk_timer_rw_tmr1_ctrl_default 0x00000000
+#define regk_timer_rw_trig_cfg_default 0x00000000
+#define regk_timer_start 0x00000001
+#define regk_timer_stop 0x00000000
+#define regk_timer_time 0x00000001
+#define regk_timer_tmr0 0x00000002
+#define regk_timer_tmr1 0x00000003
+#define regk_timer_vclk 0x00000002
+#define regk_timer_yes 0x00000001
+#endif /* __timer_defs_asm_h */
--- /dev/null
+#ifndef __clkgen_defs_h
+#define __clkgen_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: clkgen.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile clkgen_defs.h clkgen.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope clkgen */
+
+/* Register r_bootsel, scope clkgen, type r */
+typedef struct {
+ unsigned int boot_mode : 5;
+ unsigned int intern_main_clk : 1;
+ unsigned int extern_usb2_clk : 1;
+ unsigned int dummy1 : 25;
+} reg_clkgen_r_bootsel;
+#define REG_RD_ADDR_clkgen_r_bootsel 0
+
+/* Register rw_clk_ctrl, scope clkgen, type rw */
+typedef struct {
+ unsigned int pll : 1;
+ unsigned int cpu : 1;
+ unsigned int iop_usb : 1;
+ unsigned int vin : 1;
+ unsigned int sclr : 1;
+ unsigned int h264 : 1;
+ unsigned int ddr2 : 1;
+ unsigned int vout_hist : 1;
+ unsigned int eth : 1;
+ unsigned int ccd_tg_200 : 1;
+ unsigned int dma0_1_eth : 1;
+ unsigned int ccd_tg_100 : 1;
+ unsigned int jpeg : 1;
+ unsigned int sser_ser_dma6_7 : 1;
+ unsigned int strdma0_2_video : 1;
+ unsigned int dma2_3_strcop : 1;
+ unsigned int dma4_5_iop : 1;
+ unsigned int dma9_11 : 1;
+ unsigned int memarb_bar_ddr : 1;
+ unsigned int sclr_h264 : 1;
+ unsigned int dummy1 : 12;
+} reg_clkgen_rw_clk_ctrl;
+#define REG_RD_ADDR_clkgen_rw_clk_ctrl 4
+#define REG_WR_ADDR_clkgen_rw_clk_ctrl 4
+
+
+/* Constants */
+enum {
+ regk_clkgen_eth1000_rx = 0x0000000c,
+ regk_clkgen_eth1000_tx = 0x0000000e,
+ regk_clkgen_eth100_rx = 0x0000001d,
+ regk_clkgen_eth100_rx_half = 0x0000001c,
+ regk_clkgen_eth100_tx = 0x0000001f,
+ regk_clkgen_eth100_tx_half = 0x0000001e,
+ regk_clkgen_nand_3_2 = 0x00000000,
+ regk_clkgen_nand_3_2_0x30 = 0x00000002,
+ regk_clkgen_nand_3_2_0x30_pll = 0x00000012,
+ regk_clkgen_nand_3_2_pll = 0x00000010,
+ regk_clkgen_nand_3_3 = 0x00000001,
+ regk_clkgen_nand_3_3_0x30 = 0x00000003,
+ regk_clkgen_nand_3_3_0x30_pll = 0x00000013,
+ regk_clkgen_nand_3_3_pll = 0x00000011,
+ regk_clkgen_nand_4_2 = 0x00000004,
+ regk_clkgen_nand_4_2_0x30 = 0x00000006,
+ regk_clkgen_nand_4_2_0x30_pll = 0x00000016,
+ regk_clkgen_nand_4_2_pll = 0x00000014,
+ regk_clkgen_nand_4_3 = 0x00000005,
+ regk_clkgen_nand_4_3_0x30 = 0x00000007,
+ regk_clkgen_nand_4_3_0x30_pll = 0x00000017,
+ regk_clkgen_nand_4_3_pll = 0x00000015,
+ regk_clkgen_nand_5_2 = 0x00000008,
+ regk_clkgen_nand_5_2_0x30 = 0x0000000a,
+ regk_clkgen_nand_5_2_0x30_pll = 0x0000001a,
+ regk_clkgen_nand_5_2_pll = 0x00000018,
+ regk_clkgen_nand_5_3 = 0x00000009,
+ regk_clkgen_nand_5_3_0x30 = 0x0000000b,
+ regk_clkgen_nand_5_3_0x30_pll = 0x0000001b,
+ regk_clkgen_nand_5_3_pll = 0x00000019,
+ regk_clkgen_no = 0x00000000,
+ regk_clkgen_rw_clk_ctrl_default = 0x00000002,
+ regk_clkgen_ser = 0x0000000d,
+ regk_clkgen_ser_pll = 0x0000000f,
+ regk_clkgen_yes = 0x00000001
+};
+#endif /* __clkgen_defs_h */
--- /dev/null
+#ifndef __ddr2_defs_h
+#define __ddr2_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: ddr2.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile ddr2_defs.h ddr2.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope ddr2 */
+
+/* Register rw_cfg, scope ddr2, type rw */
+typedef struct {
+ unsigned int col_width : 4;
+ unsigned int nr_banks : 1;
+ unsigned int bw : 1;
+ unsigned int nr_ref : 4;
+ unsigned int ref_interval : 11;
+ unsigned int odt_ctrl : 2;
+ unsigned int odt_mem : 1;
+ unsigned int imp_strength : 1;
+ unsigned int auto_imp_cal : 1;
+ unsigned int imp_cal_override : 1;
+ unsigned int dll_override : 1;
+ unsigned int dummy1 : 4;
+} reg_ddr2_rw_cfg;
+#define REG_RD_ADDR_ddr2_rw_cfg 0
+#define REG_WR_ADDR_ddr2_rw_cfg 0
+
+/* Register rw_timing, scope ddr2, type rw */
+typedef struct {
+ unsigned int wr : 3;
+ unsigned int rcd : 3;
+ unsigned int rp : 3;
+ unsigned int ras : 4;
+ unsigned int rfc : 7;
+ unsigned int rc : 5;
+ unsigned int rtp : 2;
+ unsigned int rtw : 3;
+ unsigned int wtr : 2;
+} reg_ddr2_rw_timing;
+#define REG_RD_ADDR_ddr2_rw_timing 4
+#define REG_WR_ADDR_ddr2_rw_timing 4
+
+/* Register rw_latency, scope ddr2, type rw */
+typedef struct {
+ unsigned int cas : 3;
+ unsigned int additive : 3;
+ unsigned int dummy1 : 26;
+} reg_ddr2_rw_latency;
+#define REG_RD_ADDR_ddr2_rw_latency 8
+#define REG_WR_ADDR_ddr2_rw_latency 8
+
+/* Register rw_phy_cfg, scope ddr2, type rw */
+typedef struct {
+ unsigned int en : 1;
+ unsigned int dummy1 : 31;
+} reg_ddr2_rw_phy_cfg;
+#define REG_RD_ADDR_ddr2_rw_phy_cfg 12
+#define REG_WR_ADDR_ddr2_rw_phy_cfg 12
+
+/* Register rw_phy_ctrl, scope ddr2, type rw */
+typedef struct {
+ unsigned int rst : 1;
+ unsigned int cal_rst : 1;
+ unsigned int cal_start : 1;
+ unsigned int dummy1 : 29;
+} reg_ddr2_rw_phy_ctrl;
+#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16
+#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16
+
+/* Register rw_ctrl, scope ddr2, type rw */
+typedef struct {
+ unsigned int mrs_data : 16;
+ unsigned int cmd : 8;
+ unsigned int dummy1 : 8;
+} reg_ddr2_rw_ctrl;
+#define REG_RD_ADDR_ddr2_rw_ctrl 20
+#define REG_WR_ADDR_ddr2_rw_ctrl 20
+
+/* Register rw_pwr_down, scope ddr2, type rw */
+typedef struct {
+ unsigned int self_ref : 2;
+ unsigned int phy_en : 1;
+ unsigned int dummy1 : 29;
+} reg_ddr2_rw_pwr_down;
+#define REG_RD_ADDR_ddr2_rw_pwr_down 24
+#define REG_WR_ADDR_ddr2_rw_pwr_down 24
+
+/* Register r_stat, scope ddr2, type r */
+typedef struct {
+ unsigned int dll_lock : 1;
+ unsigned int dll_delay_code : 7;
+ unsigned int imp_cal_done : 1;
+ unsigned int imp_cal_fault : 1;
+ unsigned int cal_imp_pu : 4;
+ unsigned int cal_imp_pd : 4;
+ unsigned int dummy1 : 14;
+} reg_ddr2_r_stat;
+#define REG_RD_ADDR_ddr2_r_stat 28
+
+/* Register rw_imp_ctrl, scope ddr2, type rw */
+typedef struct {
+ unsigned int imp_pu : 4;
+ unsigned int imp_pd : 4;
+ unsigned int dummy1 : 24;
+} reg_ddr2_rw_imp_ctrl;
+#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32
+#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32
+
+#define STRIDE_ddr2_rw_dll_ctrl 4
+/* Register rw_dll_ctrl, scope ddr2, type rw */
+typedef struct {
+ unsigned int mode : 1;
+ unsigned int clk_delay : 7;
+ unsigned int dummy1 : 24;
+} reg_ddr2_rw_dll_ctrl;
+#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36
+#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36
+
+#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
+/* Register rw_dqs_dll_ctrl, scope ddr2, type rw */
+typedef struct {
+ unsigned int dqs90_delay : 7;
+ unsigned int dqs180_delay : 7;
+ unsigned int dqs270_delay : 7;
+ unsigned int dqs360_delay : 7;
+ unsigned int dummy1 : 4;
+} reg_ddr2_rw_dqs_dll_ctrl;
+#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52
+#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52
+
+
+/* Constants */
+enum {
+ regk_ddr2_al0 = 0x00000000,
+ regk_ddr2_al1 = 0x00000008,
+ regk_ddr2_al2 = 0x00000010,
+ regk_ddr2_al3 = 0x00000018,
+ regk_ddr2_al4 = 0x00000020,
+ regk_ddr2_auto = 0x00000003,
+ regk_ddr2_bank4 = 0x00000000,
+ regk_ddr2_bank8 = 0x00000001,
+ regk_ddr2_bl4 = 0x00000002,
+ regk_ddr2_bl8 = 0x00000003,
+ regk_ddr2_bt_il = 0x00000008,
+ regk_ddr2_bt_seq = 0x00000000,
+ regk_ddr2_bw16 = 0x00000001,
+ regk_ddr2_bw32 = 0x00000000,
+ regk_ddr2_cas2 = 0x00000020,
+ regk_ddr2_cas3 = 0x00000030,
+ regk_ddr2_cas4 = 0x00000040,
+ regk_ddr2_cas5 = 0x00000050,
+ regk_ddr2_deselect = 0x000000c0,
+ regk_ddr2_dic_weak = 0x00000002,
+ regk_ddr2_direct = 0x00000001,
+ regk_ddr2_dis = 0x00000000,
+ regk_ddr2_dll_dis = 0x00000001,
+ regk_ddr2_dll_en = 0x00000000,
+ regk_ddr2_dll_rst = 0x00000100,
+ regk_ddr2_emrs = 0x00000081,
+ regk_ddr2_emrs2 = 0x00000082,
+ regk_ddr2_emrs3 = 0x00000083,
+ regk_ddr2_full = 0x00000001,
+ regk_ddr2_hi_ref_rate = 0x00000080,
+ regk_ddr2_mrs = 0x00000080,
+ regk_ddr2_no = 0x00000000,
+ regk_ddr2_nop = 0x000000b8,
+ regk_ddr2_ocd_adj = 0x00000200,
+ regk_ddr2_ocd_default = 0x00000380,
+ regk_ddr2_ocd_drive0 = 0x00000100,
+ regk_ddr2_ocd_drive1 = 0x00000080,
+ regk_ddr2_ocd_exit = 0x00000000,
+ regk_ddr2_odt_dis = 0x00000000,
+ regk_ddr2_offs = 0x00000000,
+ regk_ddr2_pre = 0x00000090,
+ regk_ddr2_pre_all = 0x00000400,
+ regk_ddr2_pwr_down_fast = 0x00000000,
+ regk_ddr2_pwr_down_slow = 0x00001000,
+ regk_ddr2_ref = 0x00000088,
+ regk_ddr2_rtt150 = 0x00000040,
+ regk_ddr2_rtt50 = 0x00000044,
+ regk_ddr2_rtt75 = 0x00000004,
+ regk_ddr2_rw_cfg_default = 0x00186000,
+ regk_ddr2_rw_dll_ctrl_default = 0x00000000,
+ regk_ddr2_rw_dll_ctrl_size = 0x00000004,
+ regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000,
+ regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004,
+ regk_ddr2_rw_latency_default = 0x00000000,
+ regk_ddr2_rw_phy_cfg_default = 0x00000000,
+ regk_ddr2_rw_pwr_down_default = 0x00000000,
+ regk_ddr2_rw_timing_default = 0x00000000,
+ regk_ddr2_s1Gb = 0x0000001a,
+ regk_ddr2_s256Mb = 0x0000000f,
+ regk_ddr2_s2Gb = 0x00000027,
+ regk_ddr2_s4Gb = 0x00000042,
+ regk_ddr2_s512Mb = 0x00000015,
+ regk_ddr2_temp0_85 = 0x00000618,
+ regk_ddr2_temp85_95 = 0x0000030c,
+ regk_ddr2_term150 = 0x00000002,
+ regk_ddr2_term50 = 0x00000003,
+ regk_ddr2_term75 = 0x00000001,
+ regk_ddr2_test = 0x00000080,
+ regk_ddr2_weak = 0x00000000,
+ regk_ddr2_wr2 = 0x00000200,
+ regk_ddr2_wr3 = 0x00000400,
+ regk_ddr2_yes = 0x00000001
+};
+#endif /* __ddr2_defs_h */
--- /dev/null
+#ifndef __gio_defs_h
+#define __gio_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: gio.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile gio_defs.h gio.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope gio */
+
+/* Register r_pa_din, scope gio, type r */
+typedef struct {
+ unsigned int data : 32;
+} reg_gio_r_pa_din;
+#define REG_RD_ADDR_gio_r_pa_din 0
+
+/* Register rw_pa_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 32;
+} reg_gio_rw_pa_dout;
+#define REG_RD_ADDR_gio_rw_pa_dout 4
+#define REG_WR_ADDR_gio_rw_pa_dout 4
+
+/* Register rw_pa_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 32;
+} reg_gio_rw_pa_oe;
+#define REG_RD_ADDR_gio_rw_pa_oe 8
+#define REG_WR_ADDR_gio_rw_pa_oe 8
+
+/* Register rw_pa_byte0_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pa_byte0_dout;
+#define REG_RD_ADDR_gio_rw_pa_byte0_dout 12
+#define REG_WR_ADDR_gio_rw_pa_byte0_dout 12
+
+/* Register rw_pa_byte0_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pa_byte0_oe;
+#define REG_RD_ADDR_gio_rw_pa_byte0_oe 16
+#define REG_WR_ADDR_gio_rw_pa_byte0_oe 16
+
+/* Register rw_pa_byte1_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pa_byte1_dout;
+#define REG_RD_ADDR_gio_rw_pa_byte1_dout 20
+#define REG_WR_ADDR_gio_rw_pa_byte1_dout 20
+
+/* Register rw_pa_byte1_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pa_byte1_oe;
+#define REG_RD_ADDR_gio_rw_pa_byte1_oe 24
+#define REG_WR_ADDR_gio_rw_pa_byte1_oe 24
+
+/* Register rw_pa_byte2_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pa_byte2_dout;
+#define REG_RD_ADDR_gio_rw_pa_byte2_dout 28
+#define REG_WR_ADDR_gio_rw_pa_byte2_dout 28
+
+/* Register rw_pa_byte2_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pa_byte2_oe;
+#define REG_RD_ADDR_gio_rw_pa_byte2_oe 32
+#define REG_WR_ADDR_gio_rw_pa_byte2_oe 32
+
+/* Register rw_pa_byte3_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pa_byte3_dout;
+#define REG_RD_ADDR_gio_rw_pa_byte3_dout 36
+#define REG_WR_ADDR_gio_rw_pa_byte3_dout 36
+
+/* Register rw_pa_byte3_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pa_byte3_oe;
+#define REG_RD_ADDR_gio_rw_pa_byte3_oe 40
+#define REG_WR_ADDR_gio_rw_pa_byte3_oe 40
+
+/* Register r_pb_din, scope gio, type r */
+typedef struct {
+ unsigned int data : 32;
+} reg_gio_r_pb_din;
+#define REG_RD_ADDR_gio_r_pb_din 44
+
+/* Register rw_pb_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 32;
+} reg_gio_rw_pb_dout;
+#define REG_RD_ADDR_gio_rw_pb_dout 48
+#define REG_WR_ADDR_gio_rw_pb_dout 48
+
+/* Register rw_pb_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 32;
+} reg_gio_rw_pb_oe;
+#define REG_RD_ADDR_gio_rw_pb_oe 52
+#define REG_WR_ADDR_gio_rw_pb_oe 52
+
+/* Register rw_pb_byte0_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pb_byte0_dout;
+#define REG_RD_ADDR_gio_rw_pb_byte0_dout 56
+#define REG_WR_ADDR_gio_rw_pb_byte0_dout 56
+
+/* Register rw_pb_byte0_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pb_byte0_oe;
+#define REG_RD_ADDR_gio_rw_pb_byte0_oe 60
+#define REG_WR_ADDR_gio_rw_pb_byte0_oe 60
+
+/* Register rw_pb_byte1_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pb_byte1_dout;
+#define REG_RD_ADDR_gio_rw_pb_byte1_dout 64
+#define REG_WR_ADDR_gio_rw_pb_byte1_dout 64
+
+/* Register rw_pb_byte1_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pb_byte1_oe;
+#define REG_RD_ADDR_gio_rw_pb_byte1_oe 68
+#define REG_WR_ADDR_gio_rw_pb_byte1_oe 68
+
+/* Register rw_pb_byte2_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pb_byte2_dout;
+#define REG_RD_ADDR_gio_rw_pb_byte2_dout 72
+#define REG_WR_ADDR_gio_rw_pb_byte2_dout 72
+
+/* Register rw_pb_byte2_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pb_byte2_oe;
+#define REG_RD_ADDR_gio_rw_pb_byte2_oe 76
+#define REG_WR_ADDR_gio_rw_pb_byte2_oe 76
+
+/* Register rw_pb_byte3_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pb_byte3_dout;
+#define REG_RD_ADDR_gio_rw_pb_byte3_dout 80
+#define REG_WR_ADDR_gio_rw_pb_byte3_dout 80
+
+/* Register rw_pb_byte3_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pb_byte3_oe;
+#define REG_RD_ADDR_gio_rw_pb_byte3_oe 84
+#define REG_WR_ADDR_gio_rw_pb_byte3_oe 84
+
+/* Register r_pc_din, scope gio, type r */
+typedef struct {
+ unsigned int data : 16;
+ unsigned int dummy1 : 16;
+} reg_gio_r_pc_din;
+#define REG_RD_ADDR_gio_r_pc_din 88
+
+/* Register rw_pc_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 16;
+ unsigned int dummy1 : 16;
+} reg_gio_rw_pc_dout;
+#define REG_RD_ADDR_gio_rw_pc_dout 92
+#define REG_WR_ADDR_gio_rw_pc_dout 92
+
+/* Register rw_pc_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 16;
+ unsigned int dummy1 : 16;
+} reg_gio_rw_pc_oe;
+#define REG_RD_ADDR_gio_rw_pc_oe 96
+#define REG_WR_ADDR_gio_rw_pc_oe 96
+
+/* Register rw_pc_byte0_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pc_byte0_dout;
+#define REG_RD_ADDR_gio_rw_pc_byte0_dout 100
+#define REG_WR_ADDR_gio_rw_pc_byte0_dout 100
+
+/* Register rw_pc_byte0_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pc_byte0_oe;
+#define REG_RD_ADDR_gio_rw_pc_byte0_oe 104
+#define REG_WR_ADDR_gio_rw_pc_byte0_oe 104
+
+/* Register rw_pc_byte1_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pc_byte1_dout;
+#define REG_RD_ADDR_gio_rw_pc_byte1_dout 108
+#define REG_WR_ADDR_gio_rw_pc_byte1_dout 108
+
+/* Register rw_pc_byte1_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pc_byte1_oe;
+#define REG_RD_ADDR_gio_rw_pc_byte1_oe 112
+#define REG_WR_ADDR_gio_rw_pc_byte1_oe 112
+
+/* Register r_pd_din, scope gio, type r */
+typedef struct {
+ unsigned int data : 32;
+} reg_gio_r_pd_din;
+#define REG_RD_ADDR_gio_r_pd_din 116
+
+/* Register rw_intr_cfg, scope gio, type rw */
+typedef struct {
+ unsigned int intr0 : 3;
+ unsigned int intr1 : 3;
+ unsigned int intr2 : 3;
+ unsigned int intr3 : 3;
+ unsigned int intr4 : 3;
+ unsigned int intr5 : 3;
+ unsigned int intr6 : 3;
+ unsigned int intr7 : 3;
+ unsigned int dummy1 : 8;
+} reg_gio_rw_intr_cfg;
+#define REG_RD_ADDR_gio_rw_intr_cfg 120
+#define REG_WR_ADDR_gio_rw_intr_cfg 120
+
+/* Register rw_intr_pins, scope gio, type rw */
+typedef struct {
+ unsigned int intr0 : 4;
+ unsigned int intr1 : 4;
+ unsigned int intr2 : 4;
+ unsigned int intr3 : 4;
+ unsigned int intr4 : 4;
+ unsigned int intr5 : 4;
+ unsigned int intr6 : 4;
+ unsigned int intr7 : 4;
+} reg_gio_rw_intr_pins;
+#define REG_RD_ADDR_gio_rw_intr_pins 124
+#define REG_WR_ADDR_gio_rw_intr_pins 124
+
+/* Register rw_intr_mask, scope gio, type rw */
+typedef struct {
+ unsigned int intr0 : 1;
+ unsigned int intr1 : 1;
+ unsigned int intr2 : 1;
+ unsigned int intr3 : 1;
+ unsigned int intr4 : 1;
+ unsigned int intr5 : 1;
+ unsigned int intr6 : 1;
+ unsigned int intr7 : 1;
+ unsigned int i2c0_done : 1;
+ unsigned int i2c1_done : 1;
+ unsigned int dummy1 : 22;
+} reg_gio_rw_intr_mask;
+#define REG_RD_ADDR_gio_rw_intr_mask 128
+#define REG_WR_ADDR_gio_rw_intr_mask 128
+
+/* Register rw_ack_intr, scope gio, type rw */
+typedef struct {
+ unsigned int intr0 : 1;
+ unsigned int intr1 : 1;
+ unsigned int intr2 : 1;
+ unsigned int intr3 : 1;
+ unsigned int intr4 : 1;
+ unsigned int intr5 : 1;
+ unsigned int intr6 : 1;
+ unsigned int intr7 : 1;
+ unsigned int i2c0_done : 1;
+ unsigned int i2c1_done : 1;
+ unsigned int dummy1 : 22;
+} reg_gio_rw_ack_intr;
+#define REG_RD_ADDR_gio_rw_ack_intr 132
+#define REG_WR_ADDR_gio_rw_ack_intr 132
+
+/* Register r_intr, scope gio, type r */
+typedef struct {
+ unsigned int intr0 : 1;
+ unsigned int intr1 : 1;
+ unsigned int intr2 : 1;
+ unsigned int intr3 : 1;
+ unsigned int intr4 : 1;
+ unsigned int intr5 : 1;
+ unsigned int intr6 : 1;
+ unsigned int intr7 : 1;
+ unsigned int i2c0_done : 1;
+ unsigned int i2c1_done : 1;
+ unsigned int dummy1 : 22;
+} reg_gio_r_intr;
+#define REG_RD_ADDR_gio_r_intr 136
+
+/* Register r_masked_intr, scope gio, type r */
+typedef struct {
+ unsigned int intr0 : 1;
+ unsigned int intr1 : 1;
+ unsigned int intr2 : 1;
+ unsigned int intr3 : 1;
+ unsigned int intr4 : 1;
+ unsigned int intr5 : 1;
+ unsigned int intr6 : 1;
+ unsigned int intr7 : 1;
+ unsigned int i2c0_done : 1;
+ unsigned int i2c1_done : 1;
+ unsigned int dummy1 : 22;
+} reg_gio_r_masked_intr;
+#define REG_RD_ADDR_gio_r_masked_intr 140
+
+/* Register rw_i2c0_start, scope gio, type rw */
+typedef struct {
+ unsigned int run : 1;
+ unsigned int dummy1 : 31;
+} reg_gio_rw_i2c0_start;
+#define REG_RD_ADDR_gio_rw_i2c0_start 144
+#define REG_WR_ADDR_gio_rw_i2c0_start 144
+
+/* Register rw_i2c0_cfg, scope gio, type rw */
+typedef struct {
+ unsigned int en : 1;
+ unsigned int bit_order : 1;
+ unsigned int scl_io : 1;
+ unsigned int scl_inv : 1;
+ unsigned int sda_io : 1;
+ unsigned int sda_idle : 1;
+ unsigned int dummy1 : 26;
+} reg_gio_rw_i2c0_cfg;
+#define REG_RD_ADDR_gio_rw_i2c0_cfg 148
+#define REG_WR_ADDR_gio_rw_i2c0_cfg 148
+
+/* Register rw_i2c0_ctrl, scope gio, type rw */
+typedef struct {
+ unsigned int trf_bits : 6;
+ unsigned int switch_dir : 6;
+ unsigned int extra_start : 3;
+ unsigned int early_end : 1;
+ unsigned int start_stop : 1;
+ unsigned int ack_dir0 : 1;
+ unsigned int ack_dir1 : 1;
+ unsigned int ack_dir2 : 1;
+ unsigned int ack_dir3 : 1;
+ unsigned int ack_dir4 : 1;
+ unsigned int ack_dir5 : 1;
+ unsigned int ack_bit : 1;
+ unsigned int start_bit : 1;
+ unsigned int freq : 2;
+ unsigned int dummy1 : 5;
+} reg_gio_rw_i2c0_ctrl;
+#define REG_RD_ADDR_gio_rw_i2c0_ctrl 152
+#define REG_WR_ADDR_gio_rw_i2c0_ctrl 152
+
+/* Register rw_i2c0_data, scope gio, type rw */
+typedef struct {
+ unsigned int data0 : 8;
+ unsigned int data1 : 8;
+ unsigned int data2 : 8;
+ unsigned int data3 : 8;
+} reg_gio_rw_i2c0_data;
+#define REG_RD_ADDR_gio_rw_i2c0_data 156
+#define REG_WR_ADDR_gio_rw_i2c0_data 156
+
+/* Register rw_i2c0_data2, scope gio, type rw */
+typedef struct {
+ unsigned int data4 : 8;
+ unsigned int data5 : 8;
+ unsigned int start_val : 6;
+ unsigned int ack_val : 6;
+ unsigned int dummy1 : 4;
+} reg_gio_rw_i2c0_data2;
+#define REG_RD_ADDR_gio_rw_i2c0_data2 160
+#define REG_WR_ADDR_gio_rw_i2c0_data2 160
+
+/* Register rw_i2c1_start, scope gio, type rw */
+typedef struct {
+ unsigned int run : 1;
+ unsigned int dummy1 : 31;
+} reg_gio_rw_i2c1_start;
+#define REG_RD_ADDR_gio_rw_i2c1_start 164
+#define REG_WR_ADDR_gio_rw_i2c1_start 164
+
+/* Register rw_i2c1_cfg, scope gio, type rw */
+typedef struct {
+ unsigned int en : 1;
+ unsigned int bit_order : 1;
+ unsigned int scl_io : 1;
+ unsigned int scl_inv : 1;
+ unsigned int sda0_io : 1;
+ unsigned int sda0_idle : 1;
+ unsigned int sda1_io : 1;
+ unsigned int sda1_idle : 1;
+ unsigned int sda2_io : 1;
+ unsigned int sda2_idle : 1;
+ unsigned int sda3_io : 1;
+ unsigned int sda3_idle : 1;
+ unsigned int sda_sel : 2;
+ unsigned int sen_idle : 1;
+ unsigned int sen_inv : 1;
+ unsigned int sen_sel : 2;
+ unsigned int dummy1 : 14;
+} reg_gio_rw_i2c1_cfg;
+#define REG_RD_ADDR_gio_rw_i2c1_cfg 168
+#define REG_WR_ADDR_gio_rw_i2c1_cfg 168
+
+/* Register rw_i2c1_ctrl, scope gio, type rw */
+typedef struct {
+ unsigned int trf_bits : 6;
+ unsigned int switch_dir : 6;
+ unsigned int extra_start : 3;
+ unsigned int early_end : 1;
+ unsigned int start_stop : 1;
+ unsigned int ack_dir0 : 1;
+ unsigned int ack_dir1 : 1;
+ unsigned int ack_dir2 : 1;
+ unsigned int ack_dir3 : 1;
+ unsigned int ack_dir4 : 1;
+ unsigned int ack_dir5 : 1;
+ unsigned int ack_bit : 1;
+ unsigned int start_bit : 1;
+ unsigned int freq : 2;
+ unsigned int dummy1 : 5;
+} reg_gio_rw_i2c1_ctrl;
+#define REG_RD_ADDR_gio_rw_i2c1_ctrl 172
+#define REG_WR_ADDR_gio_rw_i2c1_ctrl 172
+
+/* Register rw_i2c1_data, scope gio, type rw */
+typedef struct {
+ unsigned int data0 : 8;
+ unsigned int data1 : 8;
+ unsigned int data2 : 8;
+ unsigned int data3 : 8;
+} reg_gio_rw_i2c1_data;
+#define REG_RD_ADDR_gio_rw_i2c1_data 176
+#define REG_WR_ADDR_gio_rw_i2c1_data 176
+
+/* Register rw_i2c1_data2, scope gio, type rw */
+typedef struct {
+ unsigned int data4 : 8;
+ unsigned int data5 : 8;
+ unsigned int start_val : 6;
+ unsigned int ack_val : 6;
+ unsigned int dummy1 : 4;
+} reg_gio_rw_i2c1_data2;
+#define REG_RD_ADDR_gio_rw_i2c1_data2 180
+#define REG_WR_ADDR_gio_rw_i2c1_data2 180
+
+/* Register r_ppwm_stat, scope gio, type r */
+typedef struct {
+ unsigned int freq : 2;
+ unsigned int dummy1 : 30;
+} reg_gio_r_ppwm_stat;
+#define REG_RD_ADDR_gio_r_ppwm_stat 184
+
+/* Register rw_ppwm_data, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_ppwm_data;
+#define REG_RD_ADDR_gio_rw_ppwm_data 188
+#define REG_WR_ADDR_gio_rw_ppwm_data 188
+
+/* Register rw_pwm0_ctrl, scope gio, type rw */
+typedef struct {
+ unsigned int mode : 2;
+ unsigned int ccd_override : 1;
+ unsigned int ccd_val : 1;
+ unsigned int dummy1 : 28;
+} reg_gio_rw_pwm0_ctrl;
+#define REG_RD_ADDR_gio_rw_pwm0_ctrl 192
+#define REG_WR_ADDR_gio_rw_pwm0_ctrl 192
+
+/* Register rw_pwm0_var, scope gio, type rw */
+typedef struct {
+ unsigned int lo : 13;
+ unsigned int hi : 13;
+ unsigned int dummy1 : 6;
+} reg_gio_rw_pwm0_var;
+#define REG_RD_ADDR_gio_rw_pwm0_var 196
+#define REG_WR_ADDR_gio_rw_pwm0_var 196
+
+/* Register rw_pwm0_data, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pwm0_data;
+#define REG_RD_ADDR_gio_rw_pwm0_data 200
+#define REG_WR_ADDR_gio_rw_pwm0_data 200
+
+/* Register rw_pwm1_ctrl, scope gio, type rw */
+typedef struct {
+ unsigned int mode : 2;
+ unsigned int ccd_override : 1;
+ unsigned int ccd_val : 1;
+ unsigned int dummy1 : 28;
+} reg_gio_rw_pwm1_ctrl;
+#define REG_RD_ADDR_gio_rw_pwm1_ctrl 204
+#define REG_WR_ADDR_gio_rw_pwm1_ctrl 204
+
+/* Register rw_pwm1_var, scope gio, type rw */
+typedef struct {
+ unsigned int lo : 13;
+ unsigned int hi : 13;
+ unsigned int dummy1 : 6;
+} reg_gio_rw_pwm1_var;
+#define REG_RD_ADDR_gio_rw_pwm1_var 208
+#define REG_WR_ADDR_gio_rw_pwm1_var 208
+
+/* Register rw_pwm1_data, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pwm1_data;
+#define REG_RD_ADDR_gio_rw_pwm1_data 212
+#define REG_WR_ADDR_gio_rw_pwm1_data 212
+
+/* Register rw_pwm2_ctrl, scope gio, type rw */
+typedef struct {
+ unsigned int mode : 2;
+ unsigned int ccd_override : 1;
+ unsigned int ccd_val : 1;
+ unsigned int dummy1 : 28;
+} reg_gio_rw_pwm2_ctrl;
+#define REG_RD_ADDR_gio_rw_pwm2_ctrl 216
+#define REG_WR_ADDR_gio_rw_pwm2_ctrl 216
+
+/* Register rw_pwm2_var, scope gio, type rw */
+typedef struct {
+ unsigned int lo : 13;
+ unsigned int hi : 13;
+ unsigned int dummy1 : 6;
+} reg_gio_rw_pwm2_var;
+#define REG_RD_ADDR_gio_rw_pwm2_var 220
+#define REG_WR_ADDR_gio_rw_pwm2_var 220
+
+/* Register rw_pwm2_data, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pwm2_data;
+#define REG_RD_ADDR_gio_rw_pwm2_data 224
+#define REG_WR_ADDR_gio_rw_pwm2_data 224
+
+/* Register rw_pwm_in_cfg, scope gio, type rw */
+typedef struct {
+ unsigned int pin : 3;
+ unsigned int dummy1 : 29;
+} reg_gio_rw_pwm_in_cfg;
+#define REG_RD_ADDR_gio_rw_pwm_in_cfg 228
+#define REG_WR_ADDR_gio_rw_pwm_in_cfg 228
+
+/* Register r_pwm_in_lo, scope gio, type r */
+typedef struct {
+ unsigned int data : 32;
+} reg_gio_r_pwm_in_lo;
+#define REG_RD_ADDR_gio_r_pwm_in_lo 232
+
+/* Register r_pwm_in_hi, scope gio, type r */
+typedef struct {
+ unsigned int data : 32;
+} reg_gio_r_pwm_in_hi;
+#define REG_RD_ADDR_gio_r_pwm_in_hi 236
+
+/* Register r_pwm_in_cnt, scope gio, type r */
+typedef struct {
+ unsigned int data : 32;
+} reg_gio_r_pwm_in_cnt;
+#define REG_RD_ADDR_gio_r_pwm_in_cnt 240
+
+
+/* Constants */
+enum {
+ regk_gio_anyedge = 0x00000007,
+ regk_gio_f100k = 0x00000000,
+ regk_gio_f1562 = 0x00000000,
+ regk_gio_f195 = 0x00000003,
+ regk_gio_f1m = 0x00000002,
+ regk_gio_f390 = 0x00000002,
+ regk_gio_f400k = 0x00000001,
+ regk_gio_f5m = 0x00000003,
+ regk_gio_f781 = 0x00000001,
+ regk_gio_hi = 0x00000001,
+ regk_gio_in = 0x00000000,
+ regk_gio_intr_pa0 = 0x00000000,
+ regk_gio_intr_pa1 = 0x00000000,
+ regk_gio_intr_pa10 = 0x00000001,
+ regk_gio_intr_pa11 = 0x00000001,
+ regk_gio_intr_pa12 = 0x00000001,
+ regk_gio_intr_pa13 = 0x00000001,
+ regk_gio_intr_pa14 = 0x00000001,
+ regk_gio_intr_pa15 = 0x00000001,
+ regk_gio_intr_pa16 = 0x00000002,
+ regk_gio_intr_pa17 = 0x00000002,
+ regk_gio_intr_pa18 = 0x00000002,
+ regk_gio_intr_pa19 = 0x00000002,
+ regk_gio_intr_pa2 = 0x00000000,
+ regk_gio_intr_pa20 = 0x00000002,
+ regk_gio_intr_pa21 = 0x00000002,
+ regk_gio_intr_pa22 = 0x00000002,
+ regk_gio_intr_pa23 = 0x00000002,
+ regk_gio_intr_pa24 = 0x00000003,
+ regk_gio_intr_pa25 = 0x00000003,
+ regk_gio_intr_pa26 = 0x00000003,
+ regk_gio_intr_pa27 = 0x00000003,
+ regk_gio_intr_pa28 = 0x00000003,
+ regk_gio_intr_pa29 = 0x00000003,
+ regk_gio_intr_pa3 = 0x00000000,
+ regk_gio_intr_pa30 = 0x00000003,
+ regk_gio_intr_pa31 = 0x00000003,
+ regk_gio_intr_pa4 = 0x00000000,
+ regk_gio_intr_pa5 = 0x00000000,
+ regk_gio_intr_pa6 = 0x00000000,
+ regk_gio_intr_pa7 = 0x00000000,
+ regk_gio_intr_pa8 = 0x00000001,
+ regk_gio_intr_pa9 = 0x00000001,
+ regk_gio_intr_pb0 = 0x00000004,
+ regk_gio_intr_pb1 = 0x00000004,
+ regk_gio_intr_pb10 = 0x00000005,
+ regk_gio_intr_pb11 = 0x00000005,
+ regk_gio_intr_pb12 = 0x00000005,
+ regk_gio_intr_pb13 = 0x00000005,
+ regk_gio_intr_pb14 = 0x00000005,
+ regk_gio_intr_pb15 = 0x00000005,
+ regk_gio_intr_pb16 = 0x00000006,
+ regk_gio_intr_pb17 = 0x00000006,
+ regk_gio_intr_pb18 = 0x00000006,
+ regk_gio_intr_pb19 = 0x00000006,
+ regk_gio_intr_pb2 = 0x00000004,
+ regk_gio_intr_pb20 = 0x00000006,
+ regk_gio_intr_pb21 = 0x00000006,
+ regk_gio_intr_pb22 = 0x00000006,
+ regk_gio_intr_pb23 = 0x00000006,
+ regk_gio_intr_pb24 = 0x00000007,
+ regk_gio_intr_pb25 = 0x00000007,
+ regk_gio_intr_pb26 = 0x00000007,
+ regk_gio_intr_pb27 = 0x00000007,
+ regk_gio_intr_pb28 = 0x00000007,
+ regk_gio_intr_pb29 = 0x00000007,
+ regk_gio_intr_pb3 = 0x00000004,
+ regk_gio_intr_pb30 = 0x00000007,
+ regk_gio_intr_pb31 = 0x00000007,
+ regk_gio_intr_pb4 = 0x00000004,
+ regk_gio_intr_pb5 = 0x00000004,
+ regk_gio_intr_pb6 = 0x00000004,
+ regk_gio_intr_pb7 = 0x00000004,
+ regk_gio_intr_pb8 = 0x00000005,
+ regk_gio_intr_pb9 = 0x00000005,
+ regk_gio_intr_pc0 = 0x00000008,
+ regk_gio_intr_pc1 = 0x00000008,
+ regk_gio_intr_pc10 = 0x00000009,
+ regk_gio_intr_pc11 = 0x00000009,
+ regk_gio_intr_pc12 = 0x00000009,
+ regk_gio_intr_pc13 = 0x00000009,
+ regk_gio_intr_pc14 = 0x00000009,
+ regk_gio_intr_pc15 = 0x00000009,
+ regk_gio_intr_pc2 = 0x00000008,
+ regk_gio_intr_pc3 = 0x00000008,
+ regk_gio_intr_pc4 = 0x00000008,
+ regk_gio_intr_pc5 = 0x00000008,
+ regk_gio_intr_pc6 = 0x00000008,
+ regk_gio_intr_pc7 = 0x00000008,
+ regk_gio_intr_pc8 = 0x00000009,
+ regk_gio_intr_pc9 = 0x00000009,
+ regk_gio_intr_pd0 = 0x0000000c,
+ regk_gio_intr_pd1 = 0x0000000c,
+ regk_gio_intr_pd10 = 0x0000000d,
+ regk_gio_intr_pd11 = 0x0000000d,
+ regk_gio_intr_pd12 = 0x0000000d,
+ regk_gio_intr_pd13 = 0x0000000d,
+ regk_gio_intr_pd14 = 0x0000000d,
+ regk_gio_intr_pd15 = 0x0000000d,
+ regk_gio_intr_pd16 = 0x0000000e,
+ regk_gio_intr_pd17 = 0x0000000e,
+ regk_gio_intr_pd18 = 0x0000000e,
+ regk_gio_intr_pd19 = 0x0000000e,
+ regk_gio_intr_pd2 = 0x0000000c,
+ regk_gio_intr_pd20 = 0x0000000e,
+ regk_gio_intr_pd21 = 0x0000000e,
+ regk_gio_intr_pd22 = 0x0000000e,
+ regk_gio_intr_pd23 = 0x0000000e,
+ regk_gio_intr_pd24 = 0x0000000f,
+ regk_gio_intr_pd25 = 0x0000000f,
+ regk_gio_intr_pd26 = 0x0000000f,
+ regk_gio_intr_pd27 = 0x0000000f,
+ regk_gio_intr_pd28 = 0x0000000f,
+ regk_gio_intr_pd29 = 0x0000000f,
+ regk_gio_intr_pd3 = 0x0000000c,
+ regk_gio_intr_pd30 = 0x0000000f,
+ regk_gio_intr_pd31 = 0x0000000f,
+ regk_gio_intr_pd4 = 0x0000000c,
+ regk_gio_intr_pd5 = 0x0000000c,
+ regk_gio_intr_pd6 = 0x0000000c,
+ regk_gio_intr_pd7 = 0x0000000c,
+ regk_gio_intr_pd8 = 0x0000000d,
+ regk_gio_intr_pd9 = 0x0000000d,
+ regk_gio_lo = 0x00000002,
+ regk_gio_lsb = 0x00000000,
+ regk_gio_msb = 0x00000001,
+ regk_gio_negedge = 0x00000006,
+ regk_gio_no = 0x00000000,
+ regk_gio_no_switch = 0x0000003f,
+ regk_gio_none = 0x00000007,
+ regk_gio_off = 0x00000000,
+ regk_gio_opendrain = 0x00000000,
+ regk_gio_out = 0x00000001,
+ regk_gio_posedge = 0x00000005,
+ regk_gio_pwm_hfp = 0x00000002,
+ regk_gio_pwm_pa0 = 0x00000001,
+ regk_gio_pwm_pa19 = 0x00000004,
+ regk_gio_pwm_pa6 = 0x00000002,
+ regk_gio_pwm_pa7 = 0x00000003,
+ regk_gio_pwm_pb26 = 0x00000005,
+ regk_gio_pwm_pd23 = 0x00000006,
+ regk_gio_pwm_pd31 = 0x00000007,
+ regk_gio_pwm_std = 0x00000001,
+ regk_gio_pwm_var = 0x00000003,
+ regk_gio_rw_i2c0_cfg_default = 0x00000020,
+ regk_gio_rw_i2c0_ctrl_default = 0x00010000,
+ regk_gio_rw_i2c0_start_default = 0x00000000,
+ regk_gio_rw_i2c1_cfg_default = 0x00000aa0,
+ regk_gio_rw_i2c1_ctrl_default = 0x00010000,
+ regk_gio_rw_i2c1_start_default = 0x00000000,
+ regk_gio_rw_intr_cfg_default = 0x00000000,
+ regk_gio_rw_intr_mask_default = 0x00000000,
+ regk_gio_rw_pa_oe_default = 0x00000000,
+ regk_gio_rw_pb_oe_default = 0x00000000,
+ regk_gio_rw_pc_oe_default = 0x00000000,
+ regk_gio_rw_ppwm_data_default = 0x00000000,
+ regk_gio_rw_pwm0_ctrl_default = 0x00000000,
+ regk_gio_rw_pwm1_ctrl_default = 0x00000000,
+ regk_gio_rw_pwm2_ctrl_default = 0x00000000,
+ regk_gio_rw_pwm_in_cfg_default = 0x00000000,
+ regk_gio_sda0 = 0x00000000,
+ regk_gio_sda1 = 0x00000001,
+ regk_gio_sda2 = 0x00000002,
+ regk_gio_sda3 = 0x00000003,
+ regk_gio_sen = 0x00000000,
+ regk_gio_set = 0x00000003,
+ regk_gio_yes = 0x00000001
+};
+#endif /* __gio_defs_h */
--- /dev/null
+/* Interrupt vector numbers autogenerated by ../../../tools/rdesc/bin/rdes2intr
+ from intr_vect.r */
+
+#ifndef _INTR_VECT_R
+#define _INTR_VECT_R
+#define TIMER0_INTR_VECT 0x31
+#define TIMER1_INTR_VECT 0x32
+#define DMA0_INTR_VECT 0x33
+#define DMA1_INTR_VECT 0x34
+#define DMA2_INTR_VECT 0x35
+#define DMA3_INTR_VECT 0x36
+#define DMA4_INTR_VECT 0x37
+#define DMA5_INTR_VECT 0x38
+#define DMA6_INTR_VECT 0x39
+#define DMA7_INTR_VECT 0x3a
+#define DMA9_INTR_VECT 0x3b
+#define DMA11_INTR_VECT 0x3c
+#define GIO_INTR_VECT 0x3d
+#define IOP0_INTR_VECT 0x3e
+#define IOP1_INTR_VECT 0x3f
+#define SER0_INTR_VECT 0x40
+#define SER1_INTR_VECT 0x41
+#define SER2_INTR_VECT 0x42
+#define SER3_INTR_VECT 0x43
+#define SER4_INTR_VECT 0x44
+#define SSER_INTR_VECT 0x45
+#define STRDMA0_INTR_VECT 0x46
+#define STRDMA1_INTR_VECT 0x47
+#define STRDMA2_INTR_VECT 0x48
+#define STRDMA3_INTR_VECT 0x49
+#define STRDMA5_INTR_VECT 0x4a
+#define VIN_INTR_VECT 0x4b
+#define VOUT_INTR_VECT 0x4c
+#define JPEG_INTR_VECT 0x4d
+#define H264_INTR_VECT 0x4e
+#define HISTO_INTR_VECT 0x4f
+#define CCD_INTR_VECT 0x50
+#define ETH_INTR_VECT 0x51
+#define MEMARB_BAR_INTR_VECT 0x52
+#define MEMARB_FOO_INTR_VECT 0x53
+#define PIO_INTR_VECT 0x54
+#define SCLR_INTR_VECT 0x55
+#define SCLR_FIFO_INTR_VECT 0x56
+#define IPI_INTR_VECT 0x57
+#define NBR_INTR_VECT 0x58
+#endif
--- /dev/null
+#ifndef __intr_vect_defs_h
+#define __intr_vect_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: intr_vect.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile intr_vect_defs.h intr_vect.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope intr_vect */
+
+
+#define STRIDE_intr_vect_rw_mask 4
+/* Register rw_mask0, scope intr_vect, type rw */
+typedef struct {
+ unsigned int timer0 : 1;
+ unsigned int timer1 : 1;
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma9 : 1;
+ unsigned int dma11 : 1;
+ unsigned int gio : 1;
+ unsigned int iop0 : 1;
+ unsigned int iop1 : 1;
+ unsigned int ser0 : 1;
+ unsigned int ser1 : 1;
+ unsigned int ser2 : 1;
+ unsigned int ser3 : 1;
+ unsigned int ser4 : 1;
+ unsigned int sser : 1;
+ unsigned int strdma0 : 1;
+ unsigned int strdma1 : 1;
+ unsigned int strdma2 : 1;
+ unsigned int strdma3 : 1;
+ unsigned int strdma5 : 1;
+ unsigned int vin : 1;
+ unsigned int vout : 1;
+ unsigned int jpeg : 1;
+ unsigned int h264 : 1;
+ unsigned int histo : 1;
+ unsigned int ccd : 1;
+} reg_intr_vect_rw_mask0;
+#define reg_intr_vect_rw_mask reg_intr_vect_rw_mask0
+#define REG_RD_ADDR_intr_vect_rw_mask 0
+#define REG_WR_ADDR_intr_vect_rw_mask 0
+#define REG_RD_ADDR_intr_vect_rw_mask0 0
+#define REG_WR_ADDR_intr_vect_rw_mask0 0
+
+#define STRIDE_intr_vect_r_vect 4
+/* Register r_vect0, scope intr_vect, type r */
+typedef struct {
+ unsigned int timer0 : 1;
+ unsigned int timer1 : 1;
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma9 : 1;
+ unsigned int dma11 : 1;
+ unsigned int gio : 1;
+ unsigned int iop0 : 1;
+ unsigned int iop1 : 1;
+ unsigned int ser0 : 1;
+ unsigned int ser1 : 1;
+ unsigned int ser2 : 1;
+ unsigned int ser3 : 1;
+ unsigned int ser4 : 1;
+ unsigned int sser : 1;
+ unsigned int strdma0 : 1;
+ unsigned int strdma1 : 1;
+ unsigned int strdma2 : 1;
+ unsigned int strdma3 : 1;
+ unsigned int strdma5 : 1;
+ unsigned int vin : 1;
+ unsigned int vout : 1;
+ unsigned int jpeg : 1;
+ unsigned int h264 : 1;
+ unsigned int histo : 1;
+ unsigned int ccd : 1;
+} reg_intr_vect_r_vect0;
+#define reg_intr_vect_r_vect reg_intr_vect_r_vect0
+#define REG_RD_ADDR_intr_vect_r_vect 8
+#define REG_RD_ADDR_intr_vect_r_vect0 8
+
+#define STRIDE_intr_vect_r_masked_vect 4
+/* Register r_masked_vect0, scope intr_vect, type r */
+typedef struct {
+ unsigned int timer0 : 1;
+ unsigned int timer1 : 1;
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma9 : 1;
+ unsigned int dma11 : 1;
+ unsigned int gio : 1;
+ unsigned int iop0 : 1;
+ unsigned int iop1 : 1;
+ unsigned int ser0 : 1;
+ unsigned int ser1 : 1;
+ unsigned int ser2 : 1;
+ unsigned int ser3 : 1;
+ unsigned int ser4 : 1;
+ unsigned int sser : 1;
+ unsigned int strdma0 : 1;
+ unsigned int strdma1 : 1;
+ unsigned int strdma2 : 1;
+ unsigned int strdma3 : 1;
+ unsigned int strdma5 : 1;
+ unsigned int vin : 1;
+ unsigned int vout : 1;
+ unsigned int jpeg : 1;
+ unsigned int h264 : 1;
+ unsigned int histo : 1;
+ unsigned int ccd : 1;
+} reg_intr_vect_r_masked_vect0;
+#define reg_intr_vect_r_masked_vect reg_intr_masked_vect_r_vect0
+#define REG_RD_ADDR_intr_vect_r_masked_vect0 16
+#define REG_RD_ADDR_intr_vect_r_masked_vect 16
+
+#define STRIDE_intr_vect_rw_xmask 4
+/* Register rw_xmask0, scope intr_vect, type rw */
+typedef struct {
+ unsigned int timer0 : 1;
+ unsigned int timer1 : 1;
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma9 : 1;
+ unsigned int dma11 : 1;
+ unsigned int gio : 1;
+ unsigned int iop0 : 1;
+ unsigned int iop1 : 1;
+ unsigned int ser0 : 1;
+ unsigned int ser1 : 1;
+ unsigned int ser2 : 1;
+ unsigned int ser3 : 1;
+ unsigned int ser4 : 1;
+ unsigned int sser : 1;
+ unsigned int strdma0 : 1;
+ unsigned int strdma1 : 1;
+ unsigned int strdma2 : 1;
+ unsigned int strdma3 : 1;
+ unsigned int strdma5 : 1;
+ unsigned int vin : 1;
+ unsigned int vout : 1;
+ unsigned int jpeg : 1;
+ unsigned int h264 : 1;
+ unsigned int histo : 1;
+ unsigned int ccd : 1;
+} reg_intr_vect_rw_xmask0;
+#define reg_intr_vect_rw_xmask reg_intr_vect_rw_xmask0
+#define REG_RD_ADDR_intr_vect_rw_xmask0 24
+#define REG_WR_ADDR_intr_vect_rw_xmask0 24
+#define REG_RD_ADDR_intr_vect_rw_xmask 24
+#define REG_WR_ADDR_intr_vect_rw_xmask 24
+
+/* Register rw_mask1, scope intr_vect, type rw */
+typedef struct {
+ unsigned int eth : 1;
+ unsigned int memarb_bar : 1;
+ unsigned int memarb_foo : 1;
+ unsigned int pio : 1;
+ unsigned int sclr : 1;
+ unsigned int sclr_fifo : 1;
+ unsigned int dummy1 : 26;
+} reg_intr_vect_rw_mask1;
+#define REG_RD_ADDR_intr_vect_rw_mask1 4
+#define REG_WR_ADDR_intr_vect_rw_mask1 4
+
+/* Register r_vect1, scope intr_vect, type r */
+typedef struct {
+ unsigned int eth : 1;
+ unsigned int memarb_bar : 1;
+ unsigned int memarb_foo : 1;
+ unsigned int pio : 1;
+ unsigned int sclr : 1;
+ unsigned int sclr_fifo : 1;
+ unsigned int dummy1 : 26;
+} reg_intr_vect_r_vect1;
+#define REG_RD_ADDR_intr_vect_r_vect1 12
+
+/* Register r_masked_vect1, scope intr_vect, type r */
+typedef struct {
+ unsigned int eth : 1;
+ unsigned int memarb_bar : 1;
+ unsigned int memarb_foo : 1;
+ unsigned int pio : 1;
+ unsigned int sclr : 1;
+ unsigned int sclr_fifo : 1;
+ unsigned int dummy1 : 26;
+} reg_intr_vect_r_masked_vect1;
+#define REG_RD_ADDR_intr_vect_r_masked_vect1 20
+
+/* Register rw_xmask1, scope intr_vect, type rw */
+typedef struct {
+ unsigned int eth : 1;
+ unsigned int memarb_bar : 1;
+ unsigned int memarb_foo : 1;
+ unsigned int pio : 1;
+ unsigned int sclr : 1;
+ unsigned int sclr_fifo : 1;
+ unsigned int dummy1 : 26;
+} reg_intr_vect_rw_xmask1;
+#define REG_RD_ADDR_intr_vect_rw_xmask1 28
+#define REG_WR_ADDR_intr_vect_rw_xmask1 28
+
+/* Register rw_xmask_ctrl, scope intr_vect, type rw */
+typedef struct {
+ unsigned int en : 1;
+ unsigned int dummy1 : 31;
+} reg_intr_vect_rw_xmask_ctrl;
+#define REG_RD_ADDR_intr_vect_rw_xmask_ctrl 32
+#define REG_WR_ADDR_intr_vect_rw_xmask_ctrl 32
+
+/* Register r_nmi, scope intr_vect, type r */
+typedef struct {
+ unsigned int watchdog0 : 1;
+ unsigned int watchdog1 : 1;
+ unsigned int dummy1 : 30;
+} reg_intr_vect_r_nmi;
+#define REG_RD_ADDR_intr_vect_r_nmi 64
+
+/* Register r_guru, scope intr_vect, type r */
+typedef struct {
+ unsigned int jtag : 1;
+ unsigned int dummy1 : 31;
+} reg_intr_vect_r_guru;
+#define REG_RD_ADDR_intr_vect_r_guru 68
+
+
+/* Register rw_ipi, scope intr_vect, type rw */
+typedef struct
+{
+ unsigned int vector;
+} reg_intr_vect_rw_ipi;
+#define REG_RD_ADDR_intr_vect_rw_ipi 72
+#define REG_WR_ADDR_intr_vect_rw_ipi 72
+
+/* Constants */
+enum {
+ regk_intr_vect_no = 0x00000000,
+ regk_intr_vect_rw_mask0_default = 0x00000000,
+ regk_intr_vect_rw_mask1_default = 0x00000000,
+ regk_intr_vect_rw_xmask0_default = 0x00000000,
+ regk_intr_vect_rw_xmask1_default = 0x00000000,
+ regk_intr_vect_rw_xmask_ctrl_default = 0x00000000,
+ regk_intr_vect_yes = 0x00000001
+};
+#endif /* __intr_vect_defs_h */
--- /dev/null
+/* Autogenerated Changes here will be lost!
+ * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg
+ */
+#define iop_version 0
+#define iop_fifo_in_extra 64
+#define iop_fifo_out_extra 128
+#define iop_trigger_grp0 192
+#define iop_trigger_grp1 256
+#define iop_trigger_grp2 320
+#define iop_trigger_grp3 384
+#define iop_trigger_grp4 448
+#define iop_trigger_grp5 512
+#define iop_trigger_grp6 576
+#define iop_trigger_grp7 640
+#define iop_crc_par 768
+#define iop_dmc_in 896
+#define iop_dmc_out 1024
+#define iop_fifo_in 1152
+#define iop_fifo_out 1280
+#define iop_scrc_in 1408
+#define iop_scrc_out 1536
+#define iop_timer_grp0 1664
+#define iop_timer_grp1 1792
+#define iop_sap_in 2048
+#define iop_sap_out 2304
+#define iop_spu 2560
+#define iop_sw_cfg 2816
+#define iop_sw_cpu 3072
+#define iop_sw_mpu 3328
+#define iop_sw_spu 3584
+#define iop_mpu 4096
--- /dev/null
+#ifndef __iop_sap_in_defs_asm_h
+#define __iop_sap_in_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sap_in.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+#define STRIDE_iop_sap_in_rw_bus_byte 4
+/* Register rw_bus_byte, scope iop_sap_in, type rw */
+#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0
+#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2
+#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2
+#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3
+#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5
+#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2
+#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7
+#define reg_iop_sap_in_rw_bus_byte___delay___width 2
+#define reg_iop_sap_in_rw_bus_byte_offset 0
+
+#define STRIDE_iop_sap_in_rw_gio 4
+/* Register rw_gio, scope iop_sap_in, type rw */
+#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
+#define reg_iop_sap_in_rw_gio___sync_sel___width 2
+#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
+#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
+#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
+#define reg_iop_sap_in_rw_gio___sync_edge___width 2
+#define reg_iop_sap_in_rw_gio___delay___lsb 7
+#define reg_iop_sap_in_rw_gio___delay___width 2
+#define reg_iop_sap_in_rw_gio___logic___lsb 9
+#define reg_iop_sap_in_rw_gio___logic___width 2
+#define reg_iop_sap_in_rw_gio_offset 16
+
+
+/* Constants */
+#define regk_iop_sap_in_and 0x00000002
+#define regk_iop_sap_in_ext_clk200 0x00000003
+#define regk_iop_sap_in_gio0 0x00000000
+#define regk_iop_sap_in_gio12 0x00000003
+#define regk_iop_sap_in_gio16 0x00000004
+#define regk_iop_sap_in_gio20 0x00000005
+#define regk_iop_sap_in_gio24 0x00000006
+#define regk_iop_sap_in_gio28 0x00000007
+#define regk_iop_sap_in_gio4 0x00000001
+#define regk_iop_sap_in_gio8 0x00000002
+#define regk_iop_sap_in_inv 0x00000001
+#define regk_iop_sap_in_neg 0x00000002
+#define regk_iop_sap_in_no 0x00000000
+#define regk_iop_sap_in_no_del_ext_clk200 0x00000002
+#define regk_iop_sap_in_none 0x00000000
+#define regk_iop_sap_in_one 0x00000001
+#define regk_iop_sap_in_or 0x00000003
+#define regk_iop_sap_in_pos 0x00000001
+#define regk_iop_sap_in_pos_neg 0x00000003
+#define regk_iop_sap_in_rw_bus_byte_default 0x00000000
+#define regk_iop_sap_in_rw_bus_byte_size 0x00000004
+#define regk_iop_sap_in_rw_gio_default 0x00000000
+#define regk_iop_sap_in_rw_gio_size 0x00000020
+#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000
+#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001
+#define regk_iop_sap_in_tmr_clk200 0x00000001
+#define regk_iop_sap_in_two 0x00000002
+#define regk_iop_sap_in_two_clk200 0x00000000
+#endif /* __iop_sap_in_defs_asm_h */
--- /dev/null
+#ifndef __iop_sap_out_defs_asm_h
+#define __iop_sap_out_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sap_out.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_gen_gated, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
+#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
+#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
+#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
+#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
+#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
+#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
+#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
+#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
+#define reg_iop_sap_out_rw_gen_gated_offset 0
+
+/* Register rw_bus, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2
+#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2
+#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2
+#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4
+#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1
+#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4
+#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5
+#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5
+#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6
+#define reg_iop_sap_out_rw_bus___byte0_delay___width 1
+#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6
+#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7
+#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2
+#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9
+#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2
+#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11
+#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1
+#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11
+#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12
+#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12
+#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13
+#define reg_iop_sap_out_rw_bus___byte1_delay___width 1
+#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13
+#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14
+#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2
+#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16
+#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2
+#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18
+#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1
+#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18
+#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19
+#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19
+#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20
+#define reg_iop_sap_out_rw_bus___byte2_delay___width 1
+#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20
+#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21
+#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2
+#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23
+#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2
+#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25
+#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1
+#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25
+#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26
+#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26
+#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27
+#define reg_iop_sap_out_rw_bus___byte3_delay___width 1
+#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27
+#define reg_iop_sap_out_rw_bus_offset 4
+
+/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9
+#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20
+#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2
+#define reg_iop_sap_out_rw_bus_lo_oe_offset 8
+
+/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9
+#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20
+#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2
+#define reg_iop_sap_out_rw_bus_hi_oe_offset 12
+
+#define STRIDE_iop_sap_out_rw_gio 4
+/* Register rw_gio, scope iop_sap_out, type rw */
+#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
+#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
+#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
+#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2
+#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5
+#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1
+#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5
+#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6
+#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
+#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6
+#define reg_iop_sap_out_rw_gio___out_delay___lsb 7
+#define reg_iop_sap_out_rw_gio___out_delay___width 1
+#define reg_iop_sap_out_rw_gio___out_delay___bit 7
+#define reg_iop_sap_out_rw_gio___out_logic___lsb 8
+#define reg_iop_sap_out_rw_gio___out_logic___width 2
+#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10
+#define reg_iop_sap_out_rw_gio___out_logic_src___width 2
+#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12
+#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
+#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15
+#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2
+#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
+#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1
+#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17
+#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18
+#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
+#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18
+#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19
+#define reg_iop_sap_out_rw_gio___oe_delay___width 1
+#define reg_iop_sap_out_rw_gio___oe_delay___bit 19
+#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
+#define reg_iop_sap_out_rw_gio___oe_logic___width 2
+#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22
+#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2
+#define reg_iop_sap_out_rw_gio_offset 16
+
+
+/* Constants */
+#define regk_iop_sap_out_always 0x00000001
+#define regk_iop_sap_out_and 0x00000002
+#define regk_iop_sap_out_clk0 0x00000000
+#define regk_iop_sap_out_clk1 0x00000001
+#define regk_iop_sap_out_clk12 0x00000004
+#define regk_iop_sap_out_clk200 0x00000000
+#define regk_iop_sap_out_ext 0x00000002
+#define regk_iop_sap_out_gated 0x00000003
+#define regk_iop_sap_out_gio0 0x00000000
+#define regk_iop_sap_out_gio1 0x00000000
+#define regk_iop_sap_out_gio16 0x00000002
+#define regk_iop_sap_out_gio17 0x00000002
+#define regk_iop_sap_out_gio24 0x00000003
+#define regk_iop_sap_out_gio25 0x00000003
+#define regk_iop_sap_out_gio8 0x00000001
+#define regk_iop_sap_out_gio9 0x00000001
+#define regk_iop_sap_out_gio_out10 0x00000005
+#define regk_iop_sap_out_gio_out18 0x00000006
+#define regk_iop_sap_out_gio_out2 0x00000004
+#define regk_iop_sap_out_gio_out26 0x00000007
+#define regk_iop_sap_out_inv 0x00000001
+#define regk_iop_sap_out_nand 0x00000003
+#define regk_iop_sap_out_no 0x00000000
+#define regk_iop_sap_out_none 0x00000000
+#define regk_iop_sap_out_one 0x00000001
+#define regk_iop_sap_out_rw_bus_default 0x00000000
+#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000
+#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000
+#define regk_iop_sap_out_rw_gen_gated_default 0x00000000
+#define regk_iop_sap_out_rw_gio_default 0x00000000
+#define regk_iop_sap_out_rw_gio_size 0x00000020
+#define regk_iop_sap_out_spu_gio6 0x00000002
+#define regk_iop_sap_out_spu_gio7 0x00000003
+#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000
+#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001
+#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002
+#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003
+#define regk_iop_sap_out_tmr200 0x00000001
+#define regk_iop_sap_out_yes 0x00000001
+#endif /* __iop_sap_out_defs_asm_h */
--- /dev/null
+#ifndef __iop_sw_cfg_defs_asm_h
+#define __iop_sw_cfg_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sw_cfg.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0
+
+/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4
+
+/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8
+
+/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12
+
+/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16
+
+/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20
+
+/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24
+
+/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28
+
+/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32
+
+/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36
+
+/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40
+
+/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1
+#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0
+#define reg_iop_sw_cfg_rw_spu_owner_offset 44
+
+/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48
+
+/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52
+
+/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56
+
+/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60
+
+/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64
+
+/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68
+
+/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72
+
+/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76
+
+/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80
+
+/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
+#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84
+
+/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0
+#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8
+#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8
+#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8
+#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16
+#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8
+#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24
+#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8
+#define reg_iop_sw_cfg_rw_bus_mask_offset 88
+
+/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1
+#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3
+#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92
+
+/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
+#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
+#define reg_iop_sw_cfg_rw_gio_mask_offset 96
+
+/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
+#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
+#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100
+
+/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0
+#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4
+#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6
+#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8
+#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10
+#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12
+#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14
+#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16
+#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18
+#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20
+#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
+#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22
+#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
+#define reg_iop_sw_cfg_rw_pinmapping_offset 104
+
+/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6
+#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2
+#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108
+
+/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15
+#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112
+
+/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15
+#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116
+
+/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15
+#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120
+
+/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15
+#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124
+
+/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15
+#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128
+
+/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15
+#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132
+
+/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15
+#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136
+
+/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15
+#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140
+
+/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0
+#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1
+#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0
+#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1
+#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1
+#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1
+#define reg_iop_sw_cfg_rw_spu_cfg_offset 144
+
+/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2
+#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148
+
+/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2
+#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152
+
+/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
+#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156
+
+/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0
+#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4
+#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4
+#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2
+#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6
+#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3
+#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9
+#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2
+#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11
+#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4
+#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160
+
+/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8
+#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3
+#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164
+
+
+/* Constants */
+#define regk_iop_sw_cfg_a 0x00000001
+#define regk_iop_sw_cfg_b 0x00000002
+#define regk_iop_sw_cfg_bus 0x00000000
+#define regk_iop_sw_cfg_bus_rot16 0x00000002
+#define regk_iop_sw_cfg_bus_rot24 0x00000003
+#define regk_iop_sw_cfg_bus_rot8 0x00000001
+#define regk_iop_sw_cfg_clk12 0x00000000
+#define regk_iop_sw_cfg_cpu 0x00000000
+#define regk_iop_sw_cfg_gated_clk0 0x0000000e
+#define regk_iop_sw_cfg_gated_clk1 0x0000000f
+#define regk_iop_sw_cfg_gio0 0x00000004
+#define regk_iop_sw_cfg_gio1 0x00000001
+#define regk_iop_sw_cfg_gio2 0x00000005
+#define regk_iop_sw_cfg_gio3 0x00000002
+#define regk_iop_sw_cfg_gio4 0x00000006
+#define regk_iop_sw_cfg_gio5 0x00000003
+#define regk_iop_sw_cfg_gio6 0x00000007
+#define regk_iop_sw_cfg_gio7 0x00000004
+#define regk_iop_sw_cfg_gio_in18 0x00000002
+#define regk_iop_sw_cfg_gio_in19 0x00000003
+#define regk_iop_sw_cfg_gio_in20 0x00000004
+#define regk_iop_sw_cfg_gio_in21 0x00000005
+#define regk_iop_sw_cfg_gio_in26 0x00000006
+#define regk_iop_sw_cfg_gio_in27 0x00000007
+#define regk_iop_sw_cfg_gio_in4 0x00000000
+#define regk_iop_sw_cfg_gio_in5 0x00000001
+#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001
+#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002
+#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003
+#define regk_iop_sw_cfg_mpu 0x00000001
+#define regk_iop_sw_cfg_none 0x00000000
+#define regk_iop_sw_cfg_pdp_out 0x00000001
+#define regk_iop_sw_cfg_pdp_out_hi 0x00000001
+#define regk_iop_sw_cfg_pdp_out_lo 0x00000000
+#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000
+#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000
+#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000
+#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555
+#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000
+#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000
+#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000
+#define regk_iop_sw_cfg_sdp_out 0x00000004
+#define regk_iop_sw_cfg_size16 0x00000002
+#define regk_iop_sw_cfg_size24 0x00000003
+#define regk_iop_sw_cfg_size32 0x00000004
+#define regk_iop_sw_cfg_size8 0x00000001
+#define regk_iop_sw_cfg_spu 0x00000002
+#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002
+#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002
+#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003
+#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003
+#define regk_iop_sw_cfg_spu_g0 0x00000007
+#define regk_iop_sw_cfg_spu_g1 0x00000007
+#define regk_iop_sw_cfg_spu_g2 0x00000007
+#define regk_iop_sw_cfg_spu_g3 0x00000007
+#define regk_iop_sw_cfg_spu_g4 0x00000007
+#define regk_iop_sw_cfg_spu_g5 0x00000007
+#define regk_iop_sw_cfg_spu_g6 0x00000007
+#define regk_iop_sw_cfg_spu_g7 0x00000007
+#define regk_iop_sw_cfg_spu_gio0 0x00000000
+#define regk_iop_sw_cfg_spu_gio1 0x00000001
+#define regk_iop_sw_cfg_spu_gio5 0x00000005
+#define regk_iop_sw_cfg_spu_gio6 0x00000006
+#define regk_iop_sw_cfg_spu_gio7 0x00000007
+#define regk_iop_sw_cfg_spu_gio_out0 0x00000008
+#define regk_iop_sw_cfg_spu_gio_out1 0x00000009
+#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a
+#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b
+#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c
+#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d
+#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e
+#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f
+#define regk_iop_sw_cfg_spu_gioout0 0x00000000
+#define regk_iop_sw_cfg_spu_gioout1 0x00000000
+#define regk_iop_sw_cfg_spu_gioout10 0x00000007
+#define regk_iop_sw_cfg_spu_gioout11 0x00000007
+#define regk_iop_sw_cfg_spu_gioout12 0x00000007
+#define regk_iop_sw_cfg_spu_gioout13 0x00000007
+#define regk_iop_sw_cfg_spu_gioout14 0x00000007
+#define regk_iop_sw_cfg_spu_gioout15 0x00000007
+#define regk_iop_sw_cfg_spu_gioout16 0x00000007
+#define regk_iop_sw_cfg_spu_gioout17 0x00000007
+#define regk_iop_sw_cfg_spu_gioout18 0x00000007
+#define regk_iop_sw_cfg_spu_gioout19 0x00000007
+#define regk_iop_sw_cfg_spu_gioout2 0x00000001
+#define regk_iop_sw_cfg_spu_gioout20 0x00000007
+#define regk_iop_sw_cfg_spu_gioout21 0x00000007
+#define regk_iop_sw_cfg_spu_gioout22 0x00000007
+#define regk_iop_sw_cfg_spu_gioout23 0x00000007
+#define regk_iop_sw_cfg_spu_gioout24 0x00000007
+#define regk_iop_sw_cfg_spu_gioout25 0x00000007
+#define regk_iop_sw_cfg_spu_gioout26 0x00000007
+#define regk_iop_sw_cfg_spu_gioout27 0x00000007
+#define regk_iop_sw_cfg_spu_gioout28 0x00000007
+#define regk_iop_sw_cfg_spu_gioout29 0x00000007
+#define regk_iop_sw_cfg_spu_gioout3 0x00000001
+#define regk_iop_sw_cfg_spu_gioout30 0x00000007
+#define regk_iop_sw_cfg_spu_gioout31 0x00000007
+#define regk_iop_sw_cfg_spu_gioout4 0x00000002
+#define regk_iop_sw_cfg_spu_gioout5 0x00000002
+#define regk_iop_sw_cfg_spu_gioout6 0x00000003
+#define regk_iop_sw_cfg_spu_gioout7 0x00000003
+#define regk_iop_sw_cfg_spu_gioout8 0x00000007
+#define regk_iop_sw_cfg_spu_gioout9 0x00000007
+#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001
+#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002
+#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003
+#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002
+#define regk_iop_sw_cfg_timer_grp0 0x00000000
+#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001
+#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005
+#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005
+#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005
+#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005
+#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002
+#define regk_iop_sw_cfg_timer_grp1 0x00000000
+#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001
+#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006
+#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006
+#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006
+#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006
+#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003
+#define regk_iop_sw_cfg_trig0_0 0x00000000
+#define regk_iop_sw_cfg_trig0_1 0x00000000
+#define regk_iop_sw_cfg_trig0_2 0x00000000
+#define regk_iop_sw_cfg_trig0_3 0x00000000
+#define regk_iop_sw_cfg_trig1_0 0x00000000
+#define regk_iop_sw_cfg_trig1_1 0x00000000
+#define regk_iop_sw_cfg_trig1_2 0x00000000
+#define regk_iop_sw_cfg_trig1_3 0x00000000
+#define regk_iop_sw_cfg_trig2_0 0x00000001
+#define regk_iop_sw_cfg_trig2_1 0x00000001
+#define regk_iop_sw_cfg_trig2_2 0x00000001
+#define regk_iop_sw_cfg_trig2_3 0x00000001
+#define regk_iop_sw_cfg_trig3_0 0x00000001
+#define regk_iop_sw_cfg_trig3_1 0x00000001
+#define regk_iop_sw_cfg_trig3_2 0x00000001
+#define regk_iop_sw_cfg_trig3_3 0x00000001
+#define regk_iop_sw_cfg_trig4_0 0x00000002
+#define regk_iop_sw_cfg_trig4_1 0x00000002
+#define regk_iop_sw_cfg_trig4_2 0x00000002
+#define regk_iop_sw_cfg_trig4_3 0x00000002
+#define regk_iop_sw_cfg_trig5_0 0x00000002
+#define regk_iop_sw_cfg_trig5_1 0x00000002
+#define regk_iop_sw_cfg_trig5_2 0x00000002
+#define regk_iop_sw_cfg_trig5_3 0x00000002
+#define regk_iop_sw_cfg_trig6_0 0x00000003
+#define regk_iop_sw_cfg_trig6_1 0x00000003
+#define regk_iop_sw_cfg_trig6_2 0x00000003
+#define regk_iop_sw_cfg_trig6_3 0x00000003
+#define regk_iop_sw_cfg_trig7_0 0x00000003
+#define regk_iop_sw_cfg_trig7_1 0x00000003
+#define regk_iop_sw_cfg_trig7_2 0x00000003
+#define regk_iop_sw_cfg_trig7_3 0x00000003
+#endif /* __iop_sw_cfg_defs_asm_h */
--- /dev/null
+#ifndef __iop_sw_cpu_defs_asm_h
+#define __iop_sw_cpu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sw_cpu.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register r_mpu_trace, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_mpu_trace_offset 0
+
+/* Register r_spu_trace, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_spu_trace_offset 4
+
+/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8
+
+/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
+#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
+#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
+#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
+#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
+#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
+#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1
+#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6
+#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12
+
+/* Register rw_mc_data, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
+#define reg_iop_sw_cpu_rw_mc_data___val___width 32
+#define reg_iop_sw_cpu_rw_mc_data_offset 16
+
+/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_mc_addr_offset 20
+
+/* Register rs_mc_data, scope iop_sw_cpu, type rs */
+#define reg_iop_sw_cpu_rs_mc_data_offset 24
+
+/* Register r_mc_data, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_mc_data_offset 28
+
+/* Register r_mc_stat, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
+#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
+#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1
+#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5
+#define reg_iop_sw_cpu_r_mc_stat_offset 32
+
+/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8
+#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8
+#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8
+#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16
+#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8
+#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24
+#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8
+#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36
+
+/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8
+#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8
+#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8
+#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16
+#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8
+#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24
+#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8
+#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40
+
+/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44
+
+/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48
+
+/* Register r_bus_in, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_bus_in_offset 52
+
+/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56
+
+/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
+#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
+#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68
+
+/* Register r_gio_in, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_gio_in_offset 72
+
+/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1
+#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31
+#define reg_iop_sw_cpu_rw_intr0_mask_offset 76
+
+/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1
+#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31
+#define reg_iop_sw_cpu_rw_ack_intr0_offset 80
+
+/* Register r_intr0, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
+#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
+#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
+#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
+#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
+#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
+#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
+#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
+#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
+#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
+#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
+#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
+#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
+#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
+#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
+#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
+#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
+#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
+#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
+#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
+#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
+#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
+#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
+#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
+#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
+#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
+#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
+#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
+#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
+#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
+#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
+#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
+#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
+#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16
+#define reg_iop_sw_cpu_r_intr0___spu_0___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16
+#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17
+#define reg_iop_sw_cpu_r_intr0___spu_1___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17
+#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18
+#define reg_iop_sw_cpu_r_intr0___spu_2___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18
+#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19
+#define reg_iop_sw_cpu_r_intr0___spu_3___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19
+#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20
+#define reg_iop_sw_cpu_r_intr0___spu_4___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20
+#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21
+#define reg_iop_sw_cpu_r_intr0___spu_5___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21
+#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22
+#define reg_iop_sw_cpu_r_intr0___spu_6___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22
+#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23
+#define reg_iop_sw_cpu_r_intr0___spu_7___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23
+#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24
+#define reg_iop_sw_cpu_r_intr0___spu_8___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24
+#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25
+#define reg_iop_sw_cpu_r_intr0___spu_9___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25
+#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26
+#define reg_iop_sw_cpu_r_intr0___spu_10___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26
+#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27
+#define reg_iop_sw_cpu_r_intr0___spu_11___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27
+#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28
+#define reg_iop_sw_cpu_r_intr0___spu_12___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28
+#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29
+#define reg_iop_sw_cpu_r_intr0___spu_13___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29
+#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30
+#define reg_iop_sw_cpu_r_intr0___spu_14___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30
+#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31
+#define reg_iop_sw_cpu_r_intr0___spu_15___width 1
+#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31
+#define reg_iop_sw_cpu_r_intr0_offset 84
+
+/* Register r_masked_intr0, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
+#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16
+#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16
+#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17
+#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17
+#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18
+#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18
+#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19
+#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19
+#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20
+#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20
+#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21
+#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21
+#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22
+#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22
+#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23
+#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23
+#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24
+#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24
+#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25
+#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25
+#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26
+#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26
+#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27
+#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27
+#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28
+#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28
+#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29
+#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29
+#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30
+#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30
+#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31
+#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1
+#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31
+#define reg_iop_sw_cpu_r_masked_intr0_offset 88
+
+/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
+#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16
+#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16
+#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17
+#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30
+#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30
+#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31
+#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1
+#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31
+#define reg_iop_sw_cpu_rw_intr1_mask_offset 92
+
+/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
+#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
+#define reg_iop_sw_cpu_rw_ack_intr1_offset 96
+
+/* Register r_intr1, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
+#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
+#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
+#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
+#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
+#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
+#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
+#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
+#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
+#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
+#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
+#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
+#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
+#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
+#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
+#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
+#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
+#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
+#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
+#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
+#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
+#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
+#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
+#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
+#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
+#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
+#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
+#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
+#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
+#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
+#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
+#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
+#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
+#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16
+#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1
+#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16
+#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17
+#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1
+#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17
+#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18
+#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1
+#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18
+#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19
+#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1
+#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19
+#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20
+#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1
+#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20
+#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21
+#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1
+#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21
+#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1
+#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1
+#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1
+#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1
+#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1
+#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1
+#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1
+#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1
+#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30
+#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1
+#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30
+#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31
+#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1
+#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31
+#define reg_iop_sw_cpu_r_intr1_offset 100
+
+/* Register r_masked_intr1, scope iop_sw_cpu, type r */
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
+#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16
+#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16
+#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17
+#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29
+#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30
+#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30
+#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31
+#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1
+#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31
+#define reg_iop_sw_cpu_r_masked_intr1_offset 104
+
+
+/* Constants */
+#define regk_iop_sw_cpu_copy 0x00000000
+#define regk_iop_sw_cpu_no 0x00000000
+#define regk_iop_sw_cpu_rd 0x00000002
+#define regk_iop_sw_cpu_reg_copy 0x00000001
+#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000
+#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000
+#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000
+#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000
+#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000
+#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000
+#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000
+#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000
+#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000
+#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000
+#define regk_iop_sw_cpu_wr 0x00000003
+#define regk_iop_sw_cpu_yes 0x00000001
+#endif /* __iop_sw_cpu_defs_asm_h */
--- /dev/null
+#ifndef __iop_sw_mpu_defs_asm_h
+#define __iop_sw_mpu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sw_mpu.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
+#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
+#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
+
+/* Register r_spu_trace, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_spu_trace_offset 4
+
+/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8
+
+/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
+#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
+#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
+#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
+#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
+#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
+#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1
+#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6
+#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12
+
+/* Register rw_mc_data, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
+#define reg_iop_sw_mpu_rw_mc_data___val___width 32
+#define reg_iop_sw_mpu_rw_mc_data_offset 16
+
+/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_mc_addr_offset 20
+
+/* Register rs_mc_data, scope iop_sw_mpu, type rs */
+#define reg_iop_sw_mpu_rs_mc_data_offset 24
+
+/* Register r_mc_data, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_mc_data_offset 28
+
+/* Register r_mc_stat, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
+#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
+#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1
+#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5
+#define reg_iop_sw_mpu_r_mc_stat_offset 32
+
+/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8
+#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8
+#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8
+#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16
+#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8
+#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24
+#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8
+#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36
+
+/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8
+#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8
+#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8
+#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16
+#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8
+#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24
+#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8
+#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40
+
+/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44
+
+/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48
+
+/* Register r_bus_in, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_bus_in_offset 52
+
+/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56
+
+/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
+#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
+#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68
+
+/* Register r_gio_in, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_gio_in_offset 72
+
+/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
+#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
+#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
+#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
+#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
+#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
+#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
+#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
+#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
+#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
+#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
+#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
+#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
+#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
+#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
+#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
+#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
+#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
+#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
+#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
+#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
+#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
+#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
+#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
+#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
+#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
+#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
+#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
+#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
+#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
+#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
+#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
+#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
+#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
+#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
+#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
+#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
+#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
+#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
+#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
+#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
+#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
+#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
+#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
+#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
+#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
+#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
+#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
+#define reg_iop_sw_mpu_rw_cpu_intr_offset 76
+
+/* Register r_cpu_intr, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
+#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
+#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
+#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
+#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
+#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
+#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
+#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
+#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
+#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
+#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
+#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
+#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
+#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
+#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
+#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
+#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
+#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
+#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
+#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
+#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
+#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
+#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
+#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
+#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
+#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
+#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
+#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
+#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
+#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
+#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
+#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
+#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
+#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
+#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
+#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
+#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
+#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
+#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
+#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
+#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
+#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
+#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
+#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
+#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
+#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
+#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
+#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
+#define reg_iop_sw_mpu_r_cpu_intr_offset 80
+
+/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1
+#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84
+
+/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12
+#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88
+
+/* Register r_intr_grp0, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1
+#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15
+#define reg_iop_sw_mpu_r_intr_grp0_offset 92
+
+/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96
+
+/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1
+#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100
+
+/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12
+#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104
+
+/* Register r_intr_grp1, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1
+#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15
+#define reg_iop_sw_mpu_r_intr_grp1_offset 108
+
+/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112
+
+/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1
+#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116
+
+/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12
+#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120
+
+/* Register r_intr_grp2, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1
+#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15
+#define reg_iop_sw_mpu_r_intr_grp2_offset 124
+
+/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128
+
+/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1
+#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15
+#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132
+
+/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1
+#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12
+#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136
+
+/* Register r_intr_grp3, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1
+#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15
+#define reg_iop_sw_mpu_r_intr_grp3_offset 140
+
+/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1
+#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15
+#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144
+
+
+/* Constants */
+#define regk_iop_sw_mpu_copy 0x00000000
+#define regk_iop_sw_mpu_cpu 0x00000000
+#define regk_iop_sw_mpu_mpu 0x00000001
+#define regk_iop_sw_mpu_no 0x00000000
+#define regk_iop_sw_mpu_nop 0x00000000
+#define regk_iop_sw_mpu_rd 0x00000002
+#define regk_iop_sw_mpu_reg_copy 0x00000001
+#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000
+#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000
+#define regk_iop_sw_mpu_set 0x00000001
+#define regk_iop_sw_mpu_spu 0x00000002
+#define regk_iop_sw_mpu_wr 0x00000003
+#define regk_iop_sw_mpu_yes 0x00000001
+#endif /* __iop_sw_mpu_defs_asm_h */
--- /dev/null
+#ifndef __iop_sw_spu_defs_asm_h
+#define __iop_sw_spu_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sw_spu.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register r_mpu_trace, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_mpu_trace_offset 0
+
+/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
+#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
+#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
+#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
+#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
+#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
+#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1
+#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6
+#define reg_iop_sw_spu_rw_mc_ctrl_offset 4
+
+/* Register rw_mc_data, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
+#define reg_iop_sw_spu_rw_mc_data___val___width 32
+#define reg_iop_sw_spu_rw_mc_data_offset 8
+
+/* Register rw_mc_addr, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mc_addr_offset 12
+
+/* Register rs_mc_data, scope iop_sw_spu, type rs */
+#define reg_iop_sw_spu_rs_mc_data_offset 16
+
+/* Register r_mc_data, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_mc_data_offset 20
+
+/* Register r_mc_stat, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
+#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
+#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
+#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
+#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2
+#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1
+#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2
+#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3
+#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3
+#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4
+#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
+#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1
+#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5
+#define reg_iop_sw_spu_r_mc_stat_offset 24
+
+/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8
+#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8
+#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16
+#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8
+#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24
+#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8
+#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28
+
+/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8
+#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8
+#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16
+#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8
+#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24
+#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8
+#define reg_iop_sw_spu_rw_bus_set_mask_offset 32
+
+/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3
+#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36
+
+/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1
+#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3
+#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40
+
+/* Register r_bus_in, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_bus_in_offset 44
+
+/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48
+
+/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_set_mask_offset 52
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60
+
+/* Register r_gio_in, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_gio_in_offset 64
+
+/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8
+#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8
+#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68
+
+/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0
+#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8
+#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8
+#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8
+#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72
+
+/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0
+#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8
+#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8
+#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8
+#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76
+
+/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0
+#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8
+#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8
+#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8
+#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80
+
+/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84
+
+/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88
+
+/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92
+
+/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96
+
+/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100
+
+/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104
+
+/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108
+
+/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
+#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112
+
+/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
+#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_rw_cpu_intr_offset 116
+
+/* Register r_cpu_intr, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
+#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_r_cpu_intr_offset 120
+
+/* Register r_hw_intr, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
+#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
+#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
+#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
+#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
+#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
+#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
+#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
+#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10
+#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10
+#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11
+#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11
+#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12
+#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12
+#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13
+#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1
+#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13
+#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14
+#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1
+#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14
+#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15
+#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1
+#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15
+#define reg_iop_sw_spu_r_hw_intr_offset 124
+
+/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
+#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
+#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_rw_mpu_intr_offset 128
+
+/* Register r_mpu_intr, scope iop_sw_spu, type r */
+#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
+#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
+#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
+#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
+#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
+#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
+#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
+#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
+#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
+#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
+#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
+#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
+#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
+#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
+#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
+#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
+#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
+#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
+#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
+#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
+#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
+#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
+#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
+#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
+#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
+#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
+#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
+#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
+#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
+#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
+#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
+#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
+#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
+#define reg_iop_sw_spu_r_mpu_intr_offset 132
+
+
+/* Constants */
+#define regk_iop_sw_spu_copy 0x00000000
+#define regk_iop_sw_spu_no 0x00000000
+#define regk_iop_sw_spu_nop 0x00000000
+#define regk_iop_sw_spu_rd 0x00000002
+#define regk_iop_sw_spu_reg_copy 0x00000001
+#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000
+#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000
+#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000
+#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000
+#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000
+#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000
+#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000
+#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000
+#define regk_iop_sw_spu_set 0x00000001
+#define regk_iop_sw_spu_wr 0x00000003
+#define regk_iop_sw_spu_yes 0x00000001
+#endif /* __iop_sw_spu_defs_asm_h */
--- /dev/null
+#ifndef __iop_version_defs_asm_h
+#define __iop_version_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_version.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register r_version, scope iop_version, type r */
+#define reg_iop_version_r_version___nr___lsb 0
+#define reg_iop_version_r_version___nr___width 8
+#define reg_iop_version_r_version_offset 0
+
+
+/* Constants */
+#define regk_iop_version_v2_0 0x00000002
+#endif /* __iop_version_defs_asm_h */
--- /dev/null
+/* Autogenerated Changes here will be lost!
+ * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg
+ */
+#define regi_iop_version (regi_iop + 0)
+#define regi_iop_fifo_in_extra (regi_iop + 64)
+#define regi_iop_fifo_out_extra (regi_iop + 128)
+#define regi_iop_trigger_grp0 (regi_iop + 192)
+#define regi_iop_trigger_grp1 (regi_iop + 256)
+#define regi_iop_trigger_grp2 (regi_iop + 320)
+#define regi_iop_trigger_grp3 (regi_iop + 384)
+#define regi_iop_trigger_grp4 (regi_iop + 448)
+#define regi_iop_trigger_grp5 (regi_iop + 512)
+#define regi_iop_trigger_grp6 (regi_iop + 576)
+#define regi_iop_trigger_grp7 (regi_iop + 640)
+#define regi_iop_crc_par (regi_iop + 768)
+#define regi_iop_dmc_in (regi_iop + 896)
+#define regi_iop_dmc_out (regi_iop + 1024)
+#define regi_iop_fifo_in (regi_iop + 1152)
+#define regi_iop_fifo_out (regi_iop + 1280)
+#define regi_iop_scrc_in (regi_iop + 1408)
+#define regi_iop_scrc_out (regi_iop + 1536)
+#define regi_iop_timer_grp0 (regi_iop + 1664)
+#define regi_iop_timer_grp1 (regi_iop + 1792)
+#define regi_iop_sap_in (regi_iop + 2048)
+#define regi_iop_sap_out (regi_iop + 2304)
+#define regi_iop_spu (regi_iop + 2560)
+#define regi_iop_sw_cfg (regi_iop + 2816)
+#define regi_iop_sw_cpu (regi_iop + 3072)
+#define regi_iop_sw_mpu (regi_iop + 3328)
+#define regi_iop_sw_spu (regi_iop + 3584)
+#define regi_iop_mpu (regi_iop + 4096)
--- /dev/null
+#ifndef __iop_sap_in_defs_h
+#define __iop_sap_in_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sap_in.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sap_in */
+
+#define STRIDE_iop_sap_in_rw_bus_byte 4
+/* Register rw_bus_byte, scope iop_sap_in, type rw */
+typedef struct {
+ unsigned int sync_sel : 2;
+ unsigned int sync_ext_src : 3;
+ unsigned int sync_edge : 2;
+ unsigned int delay : 2;
+ unsigned int dummy1 : 23;
+} reg_iop_sap_in_rw_bus_byte;
+#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0
+#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0
+
+#define STRIDE_iop_sap_in_rw_gio 4
+/* Register rw_gio, scope iop_sap_in, type rw */
+typedef struct {
+ unsigned int sync_sel : 2;
+ unsigned int sync_ext_src : 3;
+ unsigned int sync_edge : 2;
+ unsigned int delay : 2;
+ unsigned int logic : 2;
+ unsigned int dummy1 : 21;
+} reg_iop_sap_in_rw_gio;
+#define REG_RD_ADDR_iop_sap_in_rw_gio 16
+#define REG_WR_ADDR_iop_sap_in_rw_gio 16
+
+
+/* Constants */
+enum {
+ regk_iop_sap_in_and = 0x00000002,
+ regk_iop_sap_in_ext_clk200 = 0x00000003,
+ regk_iop_sap_in_gio0 = 0x00000000,
+ regk_iop_sap_in_gio12 = 0x00000003,
+ regk_iop_sap_in_gio16 = 0x00000004,
+ regk_iop_sap_in_gio20 = 0x00000005,
+ regk_iop_sap_in_gio24 = 0x00000006,
+ regk_iop_sap_in_gio28 = 0x00000007,
+ regk_iop_sap_in_gio4 = 0x00000001,
+ regk_iop_sap_in_gio8 = 0x00000002,
+ regk_iop_sap_in_inv = 0x00000001,
+ regk_iop_sap_in_neg = 0x00000002,
+ regk_iop_sap_in_no = 0x00000000,
+ regk_iop_sap_in_no_del_ext_clk200 = 0x00000002,
+ regk_iop_sap_in_none = 0x00000000,
+ regk_iop_sap_in_one = 0x00000001,
+ regk_iop_sap_in_or = 0x00000003,
+ regk_iop_sap_in_pos = 0x00000001,
+ regk_iop_sap_in_pos_neg = 0x00000003,
+ regk_iop_sap_in_rw_bus_byte_default = 0x00000000,
+ regk_iop_sap_in_rw_bus_byte_size = 0x00000004,
+ regk_iop_sap_in_rw_gio_default = 0x00000000,
+ regk_iop_sap_in_rw_gio_size = 0x00000020,
+ regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000,
+ regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001,
+ regk_iop_sap_in_tmr_clk200 = 0x00000001,
+ regk_iop_sap_in_two = 0x00000002,
+ regk_iop_sap_in_two_clk200 = 0x00000000
+};
+#endif /* __iop_sap_in_defs_h */
--- /dev/null
+#ifndef __iop_sap_out_defs_h
+#define __iop_sap_out_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sap_out.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sap_out */
+
+/* Register rw_gen_gated, scope iop_sap_out, type rw */
+typedef struct {
+ unsigned int clk0_src : 2;
+ unsigned int clk0_gate_src : 2;
+ unsigned int clk0_force_src : 3;
+ unsigned int clk1_src : 2;
+ unsigned int clk1_gate_src : 2;
+ unsigned int clk1_force_src : 3;
+ unsigned int dummy1 : 18;
+} reg_iop_sap_out_rw_gen_gated;
+#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0
+#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0
+
+/* Register rw_bus, scope iop_sap_out, type rw */
+typedef struct {
+ unsigned int byte0_clk_sel : 2;
+ unsigned int byte0_clk_ext : 2;
+ unsigned int byte0_gated_clk : 1;
+ unsigned int byte0_clk_inv : 1;
+ unsigned int byte0_delay : 1;
+ unsigned int byte1_clk_sel : 2;
+ unsigned int byte1_clk_ext : 2;
+ unsigned int byte1_gated_clk : 1;
+ unsigned int byte1_clk_inv : 1;
+ unsigned int byte1_delay : 1;
+ unsigned int byte2_clk_sel : 2;
+ unsigned int byte2_clk_ext : 2;
+ unsigned int byte2_gated_clk : 1;
+ unsigned int byte2_clk_inv : 1;
+ unsigned int byte2_delay : 1;
+ unsigned int byte3_clk_sel : 2;
+ unsigned int byte3_clk_ext : 2;
+ unsigned int byte3_gated_clk : 1;
+ unsigned int byte3_clk_inv : 1;
+ unsigned int byte3_delay : 1;
+ unsigned int dummy1 : 4;
+} reg_iop_sap_out_rw_bus;
+#define REG_RD_ADDR_iop_sap_out_rw_bus 4
+#define REG_WR_ADDR_iop_sap_out_rw_bus 4
+
+/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */
+typedef struct {
+ unsigned int byte0_clk_sel : 2;
+ unsigned int byte0_clk_ext : 2;
+ unsigned int byte0_gated_clk : 1;
+ unsigned int byte0_clk_inv : 1;
+ unsigned int byte0_delay : 1;
+ unsigned int byte0_logic : 2;
+ unsigned int byte0_logic_src : 2;
+ unsigned int byte1_clk_sel : 2;
+ unsigned int byte1_clk_ext : 2;
+ unsigned int byte1_gated_clk : 1;
+ unsigned int byte1_clk_inv : 1;
+ unsigned int byte1_delay : 1;
+ unsigned int byte1_logic : 2;
+ unsigned int byte1_logic_src : 2;
+ unsigned int dummy1 : 10;
+} reg_iop_sap_out_rw_bus_lo_oe;
+#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8
+#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8
+
+/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */
+typedef struct {
+ unsigned int byte2_clk_sel : 2;
+ unsigned int byte2_clk_ext : 2;
+ unsigned int byte2_gated_clk : 1;
+ unsigned int byte2_clk_inv : 1;
+ unsigned int byte2_delay : 1;
+ unsigned int byte2_logic : 2;
+ unsigned int byte2_logic_src : 2;
+ unsigned int byte3_clk_sel : 2;
+ unsigned int byte3_clk_ext : 2;
+ unsigned int byte3_gated_clk : 1;
+ unsigned int byte3_clk_inv : 1;
+ unsigned int byte3_delay : 1;
+ unsigned int byte3_logic : 2;
+ unsigned int byte3_logic_src : 2;
+ unsigned int dummy1 : 10;
+} reg_iop_sap_out_rw_bus_hi_oe;
+#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12
+#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12
+
+#define STRIDE_iop_sap_out_rw_gio 4
+/* Register rw_gio, scope iop_sap_out, type rw */
+typedef struct {
+ unsigned int out_clk_sel : 3;
+ unsigned int out_clk_ext : 2;
+ unsigned int out_gated_clk : 1;
+ unsigned int out_clk_inv : 1;
+ unsigned int out_delay : 1;
+ unsigned int out_logic : 2;
+ unsigned int out_logic_src : 2;
+ unsigned int oe_clk_sel : 3;
+ unsigned int oe_clk_ext : 2;
+ unsigned int oe_gated_clk : 1;
+ unsigned int oe_clk_inv : 1;
+ unsigned int oe_delay : 1;
+ unsigned int oe_logic : 2;
+ unsigned int oe_logic_src : 2;
+ unsigned int dummy1 : 8;
+} reg_iop_sap_out_rw_gio;
+#define REG_RD_ADDR_iop_sap_out_rw_gio 16
+#define REG_WR_ADDR_iop_sap_out_rw_gio 16
+
+
+/* Constants */
+enum {
+ regk_iop_sap_out_always = 0x00000001,
+ regk_iop_sap_out_and = 0x00000002,
+ regk_iop_sap_out_clk0 = 0x00000000,
+ regk_iop_sap_out_clk1 = 0x00000001,
+ regk_iop_sap_out_clk12 = 0x00000004,
+ regk_iop_sap_out_clk200 = 0x00000000,
+ regk_iop_sap_out_ext = 0x00000002,
+ regk_iop_sap_out_gated = 0x00000003,
+ regk_iop_sap_out_gio0 = 0x00000000,
+ regk_iop_sap_out_gio1 = 0x00000000,
+ regk_iop_sap_out_gio16 = 0x00000002,
+ regk_iop_sap_out_gio17 = 0x00000002,
+ regk_iop_sap_out_gio24 = 0x00000003,
+ regk_iop_sap_out_gio25 = 0x00000003,
+ regk_iop_sap_out_gio8 = 0x00000001,
+ regk_iop_sap_out_gio9 = 0x00000001,
+ regk_iop_sap_out_gio_out10 = 0x00000005,
+ regk_iop_sap_out_gio_out18 = 0x00000006,
+ regk_iop_sap_out_gio_out2 = 0x00000004,
+ regk_iop_sap_out_gio_out26 = 0x00000007,
+ regk_iop_sap_out_inv = 0x00000001,
+ regk_iop_sap_out_nand = 0x00000003,
+ regk_iop_sap_out_no = 0x00000000,
+ regk_iop_sap_out_none = 0x00000000,
+ regk_iop_sap_out_one = 0x00000001,
+ regk_iop_sap_out_rw_bus_default = 0x00000000,
+ regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000,
+ regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000,
+ regk_iop_sap_out_rw_gen_gated_default = 0x00000000,
+ regk_iop_sap_out_rw_gio_default = 0x00000000,
+ regk_iop_sap_out_rw_gio_size = 0x00000020,
+ regk_iop_sap_out_spu_gio6 = 0x00000002,
+ regk_iop_sap_out_spu_gio7 = 0x00000003,
+ regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000,
+ regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001,
+ regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002,
+ regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003,
+ regk_iop_sap_out_tmr200 = 0x00000001,
+ regk_iop_sap_out_yes = 0x00000001
+};
+#endif /* __iop_sap_out_defs_h */
--- /dev/null
+#ifndef __iop_sw_cfg_defs_h
+#define __iop_sw_cfg_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sw_cfg.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_cfg */
+
+/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_crc_par_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0
+#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0
+
+/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_dmc_in_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
+#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4
+
+/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_dmc_out_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
+#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8
+
+/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_in_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12
+
+/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_in_extra_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16
+
+/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_out_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20
+
+/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_fifo_out_extra_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
+#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24
+
+/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_sap_in_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28
+#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28
+
+/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_sap_out_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32
+#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32
+
+/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_scrc_in_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
+#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36
+
+/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_scrc_out_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
+#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40
+
+/* Register rw_spu_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 1;
+ unsigned int dummy1 : 31;
+} reg_iop_sw_cfg_rw_spu_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44
+#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44
+
+/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_timer_grp0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48
+
+/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_timer_grp1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52
+
+/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp0_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56
+
+/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp1_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60
+
+/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp2_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64
+
+/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp3_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68
+
+/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp4_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72
+
+/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp5_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76
+
+/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp6_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80
+
+/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_trigger_grp7_owner;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84
+
+/* Register rw_bus_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int byte0 : 8;
+ unsigned int byte1 : 8;
+ unsigned int byte2 : 8;
+ unsigned int byte3 : 8;
+} reg_iop_sw_cfg_rw_bus_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88
+
+/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int byte0 : 1;
+ unsigned int byte1 : 1;
+ unsigned int byte2 : 1;
+ unsigned int byte3 : 1;
+ unsigned int dummy1 : 28;
+} reg_iop_sw_cfg_rw_bus_oe_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92
+
+/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_cfg_rw_gio_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96
+
+/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_cfg_rw_gio_oe_mask;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100
+
+/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int bus_byte0 : 2;
+ unsigned int bus_byte1 : 2;
+ unsigned int bus_byte2 : 2;
+ unsigned int bus_byte3 : 2;
+ unsigned int gio3_0 : 2;
+ unsigned int gio7_4 : 2;
+ unsigned int gio11_8 : 2;
+ unsigned int gio15_12 : 2;
+ unsigned int gio19_16 : 2;
+ unsigned int gio23_20 : 2;
+ unsigned int gio27_24 : 2;
+ unsigned int gio31_28 : 2;
+ unsigned int dummy1 : 8;
+} reg_iop_sw_cfg_rw_pinmapping;
+#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104
+#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104
+
+/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int bus_lo : 2;
+ unsigned int bus_hi : 2;
+ unsigned int bus_lo_oe : 2;
+ unsigned int bus_hi_oe : 2;
+ unsigned int dummy1 : 24;
+} reg_iop_sw_cfg_rw_bus_out_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
+#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108
+
+/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int gio0 : 3;
+ unsigned int gio0_oe : 1;
+ unsigned int gio1 : 3;
+ unsigned int gio1_oe : 1;
+ unsigned int gio2 : 3;
+ unsigned int gio2_oe : 1;
+ unsigned int gio3 : 3;
+ unsigned int gio3_oe : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_cfg_rw_gio_out_grp0_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112
+
+/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int gio4 : 3;
+ unsigned int gio4_oe : 1;
+ unsigned int gio5 : 3;
+ unsigned int gio5_oe : 1;
+ unsigned int gio6 : 3;
+ unsigned int gio6_oe : 1;
+ unsigned int gio7 : 3;
+ unsigned int gio7_oe : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_cfg_rw_gio_out_grp1_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116
+
+/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int gio8 : 3;
+ unsigned int gio8_oe : 1;
+ unsigned int gio9 : 3;
+ unsigned int gio9_oe : 1;
+ unsigned int gio10 : 3;
+ unsigned int gio10_oe : 1;
+ unsigned int gio11 : 3;
+ unsigned int gio11_oe : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_cfg_rw_gio_out_grp2_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120
+
+/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int gio12 : 3;
+ unsigned int gio12_oe : 1;
+ unsigned int gio13 : 3;
+ unsigned int gio13_oe : 1;
+ unsigned int gio14 : 3;
+ unsigned int gio14_oe : 1;
+ unsigned int gio15 : 3;
+ unsigned int gio15_oe : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_cfg_rw_gio_out_grp3_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124
+
+/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int gio16 : 3;
+ unsigned int gio16_oe : 1;
+ unsigned int gio17 : 3;
+ unsigned int gio17_oe : 1;
+ unsigned int gio18 : 3;
+ unsigned int gio18_oe : 1;
+ unsigned int gio19 : 3;
+ unsigned int gio19_oe : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_cfg_rw_gio_out_grp4_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128
+
+/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int gio20 : 3;
+ unsigned int gio20_oe : 1;
+ unsigned int gio21 : 3;
+ unsigned int gio21_oe : 1;
+ unsigned int gio22 : 3;
+ unsigned int gio22_oe : 1;
+ unsigned int gio23 : 3;
+ unsigned int gio23_oe : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_cfg_rw_gio_out_grp5_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132
+
+/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int gio24 : 3;
+ unsigned int gio24_oe : 1;
+ unsigned int gio25 : 3;
+ unsigned int gio25_oe : 1;
+ unsigned int gio26 : 3;
+ unsigned int gio26_oe : 1;
+ unsigned int gio27 : 3;
+ unsigned int gio27_oe : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_cfg_rw_gio_out_grp6_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136
+
+/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int gio28 : 3;
+ unsigned int gio28_oe : 1;
+ unsigned int gio29 : 3;
+ unsigned int gio29_oe : 1;
+ unsigned int gio30 : 3;
+ unsigned int gio30_oe : 1;
+ unsigned int gio31 : 3;
+ unsigned int gio31_oe : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_cfg_rw_gio_out_grp7_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
+#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140
+
+/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int bus0_in : 1;
+ unsigned int bus1_in : 1;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_cfg_rw_spu_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144
+#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144
+
+/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int ext_clk : 3;
+ unsigned int tmr0_en : 2;
+ unsigned int tmr1_en : 2;
+ unsigned int tmr2_en : 2;
+ unsigned int tmr3_en : 2;
+ unsigned int tmr0_dis : 2;
+ unsigned int tmr1_dis : 2;
+ unsigned int tmr2_dis : 2;
+ unsigned int tmr3_dis : 2;
+ unsigned int dummy1 : 13;
+} reg_iop_sw_cfg_rw_timer_grp0_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148
+
+/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int ext_clk : 3;
+ unsigned int tmr0_en : 2;
+ unsigned int tmr1_en : 2;
+ unsigned int tmr2_en : 2;
+ unsigned int tmr3_en : 2;
+ unsigned int tmr0_dis : 2;
+ unsigned int tmr1_dis : 2;
+ unsigned int tmr2_dis : 2;
+ unsigned int tmr3_dis : 2;
+ unsigned int dummy1 : 13;
+} reg_iop_sw_cfg_rw_timer_grp1_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
+#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152
+
+/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int grp0_dis : 1;
+ unsigned int grp0_en : 1;
+ unsigned int grp1_dis : 1;
+ unsigned int grp1_en : 1;
+ unsigned int grp2_dis : 1;
+ unsigned int grp2_en : 1;
+ unsigned int grp3_dis : 1;
+ unsigned int grp3_en : 1;
+ unsigned int grp4_dis : 1;
+ unsigned int grp4_en : 1;
+ unsigned int grp5_dis : 1;
+ unsigned int grp5_en : 1;
+ unsigned int grp6_dis : 1;
+ unsigned int grp6_en : 1;
+ unsigned int grp7_dis : 1;
+ unsigned int grp7_en : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_cfg_rw_trigger_grps_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
+#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156
+
+/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int out_strb : 4;
+ unsigned int in_src : 2;
+ unsigned int in_size : 3;
+ unsigned int in_last : 2;
+ unsigned int in_strb : 4;
+ unsigned int dummy1 : 17;
+} reg_iop_sw_cfg_rw_pdp_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160
+#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160
+
+/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
+typedef struct {
+ unsigned int sdp_out_strb : 3;
+ unsigned int sdp_in_data : 3;
+ unsigned int sdp_in_last : 2;
+ unsigned int sdp_in_strb : 3;
+ unsigned int dummy1 : 21;
+} reg_iop_sw_cfg_rw_sdp_cfg;
+#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164
+#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164
+
+
+/* Constants */
+enum {
+ regk_iop_sw_cfg_a = 0x00000001,
+ regk_iop_sw_cfg_b = 0x00000002,
+ regk_iop_sw_cfg_bus = 0x00000000,
+ regk_iop_sw_cfg_bus_rot16 = 0x00000002,
+ regk_iop_sw_cfg_bus_rot24 = 0x00000003,
+ regk_iop_sw_cfg_bus_rot8 = 0x00000001,
+ regk_iop_sw_cfg_clk12 = 0x00000000,
+ regk_iop_sw_cfg_cpu = 0x00000000,
+ regk_iop_sw_cfg_gated_clk0 = 0x0000000e,
+ regk_iop_sw_cfg_gated_clk1 = 0x0000000f,
+ regk_iop_sw_cfg_gio0 = 0x00000004,
+ regk_iop_sw_cfg_gio1 = 0x00000001,
+ regk_iop_sw_cfg_gio2 = 0x00000005,
+ regk_iop_sw_cfg_gio3 = 0x00000002,
+ regk_iop_sw_cfg_gio4 = 0x00000006,
+ regk_iop_sw_cfg_gio5 = 0x00000003,
+ regk_iop_sw_cfg_gio6 = 0x00000007,
+ regk_iop_sw_cfg_gio7 = 0x00000004,
+ regk_iop_sw_cfg_gio_in18 = 0x00000002,
+ regk_iop_sw_cfg_gio_in19 = 0x00000003,
+ regk_iop_sw_cfg_gio_in20 = 0x00000004,
+ regk_iop_sw_cfg_gio_in21 = 0x00000005,
+ regk_iop_sw_cfg_gio_in26 = 0x00000006,
+ regk_iop_sw_cfg_gio_in27 = 0x00000007,
+ regk_iop_sw_cfg_gio_in4 = 0x00000000,
+ regk_iop_sw_cfg_gio_in5 = 0x00000001,
+ regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001,
+ regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002,
+ regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003,
+ regk_iop_sw_cfg_mpu = 0x00000001,
+ regk_iop_sw_cfg_none = 0x00000000,
+ regk_iop_sw_cfg_pdp_out = 0x00000001,
+ regk_iop_sw_cfg_pdp_out_hi = 0x00000001,
+ regk_iop_sw_cfg_pdp_out_lo = 0x00000000,
+ regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000,
+ regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000,
+ regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000,
+ regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000,
+ regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555,
+ regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000,
+ regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000,
+ regk_iop_sw_cfg_sdp_out = 0x00000004,
+ regk_iop_sw_cfg_size16 = 0x00000002,
+ regk_iop_sw_cfg_size24 = 0x00000003,
+ regk_iop_sw_cfg_size32 = 0x00000004,
+ regk_iop_sw_cfg_size8 = 0x00000001,
+ regk_iop_sw_cfg_spu = 0x00000002,
+ regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002,
+ regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002,
+ regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003,
+ regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003,
+ regk_iop_sw_cfg_spu_g0 = 0x00000007,
+ regk_iop_sw_cfg_spu_g1 = 0x00000007,
+ regk_iop_sw_cfg_spu_g2 = 0x00000007,
+ regk_iop_sw_cfg_spu_g3 = 0x00000007,
+ regk_iop_sw_cfg_spu_g4 = 0x00000007,
+ regk_iop_sw_cfg_spu_g5 = 0x00000007,
+ regk_iop_sw_cfg_spu_g6 = 0x00000007,
+ regk_iop_sw_cfg_spu_g7 = 0x00000007,
+ regk_iop_sw_cfg_spu_gio0 = 0x00000000,
+ regk_iop_sw_cfg_spu_gio1 = 0x00000001,
+ regk_iop_sw_cfg_spu_gio5 = 0x00000005,
+ regk_iop_sw_cfg_spu_gio6 = 0x00000006,
+ regk_iop_sw_cfg_spu_gio7 = 0x00000007,
+ regk_iop_sw_cfg_spu_gio_out0 = 0x00000008,
+ regk_iop_sw_cfg_spu_gio_out1 = 0x00000009,
+ regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a,
+ regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b,
+ regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c,
+ regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d,
+ regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e,
+ regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f,
+ regk_iop_sw_cfg_spu_gioout0 = 0x00000000,
+ regk_iop_sw_cfg_spu_gioout1 = 0x00000000,
+ regk_iop_sw_cfg_spu_gioout10 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout11 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout12 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout13 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout14 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout15 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout16 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout17 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout18 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout19 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout2 = 0x00000001,
+ regk_iop_sw_cfg_spu_gioout20 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout21 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout22 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout23 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout24 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout25 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout26 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout27 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout28 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout29 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout3 = 0x00000001,
+ regk_iop_sw_cfg_spu_gioout30 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout31 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout4 = 0x00000002,
+ regk_iop_sw_cfg_spu_gioout5 = 0x00000002,
+ regk_iop_sw_cfg_spu_gioout6 = 0x00000003,
+ regk_iop_sw_cfg_spu_gioout7 = 0x00000003,
+ regk_iop_sw_cfg_spu_gioout8 = 0x00000007,
+ regk_iop_sw_cfg_spu_gioout9 = 0x00000007,
+ regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001,
+ regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002,
+ regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003,
+ regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002,
+ regk_iop_sw_cfg_timer_grp0 = 0x00000000,
+ regk_iop_sw_cfg_timer_grp0_rot = 0x00000001,
+ regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005,
+ regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005,
+ regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005,
+ regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005,
+ regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002,
+ regk_iop_sw_cfg_timer_grp1 = 0x00000000,
+ regk_iop_sw_cfg_timer_grp1_rot = 0x00000001,
+ regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006,
+ regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006,
+ regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006,
+ regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006,
+ regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003,
+ regk_iop_sw_cfg_trig0_0 = 0x00000000,
+ regk_iop_sw_cfg_trig0_1 = 0x00000000,
+ regk_iop_sw_cfg_trig0_2 = 0x00000000,
+ regk_iop_sw_cfg_trig0_3 = 0x00000000,
+ regk_iop_sw_cfg_trig1_0 = 0x00000000,
+ regk_iop_sw_cfg_trig1_1 = 0x00000000,
+ regk_iop_sw_cfg_trig1_2 = 0x00000000,
+ regk_iop_sw_cfg_trig1_3 = 0x00000000,
+ regk_iop_sw_cfg_trig2_0 = 0x00000001,
+ regk_iop_sw_cfg_trig2_1 = 0x00000001,
+ regk_iop_sw_cfg_trig2_2 = 0x00000001,
+ regk_iop_sw_cfg_trig2_3 = 0x00000001,
+ regk_iop_sw_cfg_trig3_0 = 0x00000001,
+ regk_iop_sw_cfg_trig3_1 = 0x00000001,
+ regk_iop_sw_cfg_trig3_2 = 0x00000001,
+ regk_iop_sw_cfg_trig3_3 = 0x00000001,
+ regk_iop_sw_cfg_trig4_0 = 0x00000002,
+ regk_iop_sw_cfg_trig4_1 = 0x00000002,
+ regk_iop_sw_cfg_trig4_2 = 0x00000002,
+ regk_iop_sw_cfg_trig4_3 = 0x00000002,
+ regk_iop_sw_cfg_trig5_0 = 0x00000002,
+ regk_iop_sw_cfg_trig5_1 = 0x00000002,
+ regk_iop_sw_cfg_trig5_2 = 0x00000002,
+ regk_iop_sw_cfg_trig5_3 = 0x00000002,
+ regk_iop_sw_cfg_trig6_0 = 0x00000003,
+ regk_iop_sw_cfg_trig6_1 = 0x00000003,
+ regk_iop_sw_cfg_trig6_2 = 0x00000003,
+ regk_iop_sw_cfg_trig6_3 = 0x00000003,
+ regk_iop_sw_cfg_trig7_0 = 0x00000003,
+ regk_iop_sw_cfg_trig7_1 = 0x00000003,
+ regk_iop_sw_cfg_trig7_2 = 0x00000003,
+ regk_iop_sw_cfg_trig7_3 = 0x00000003
+};
+#endif /* __iop_sw_cfg_defs_h */
--- /dev/null
+#ifndef __iop_sw_cpu_defs_h
+#define __iop_sw_cpu_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sw_cpu.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_cpu */
+
+/* Register r_mpu_trace, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_mpu_trace;
+#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0
+
+/* Register r_spu_trace, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_spu_trace;
+#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4
+
+/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace;
+#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8
+
+/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int keep_owner : 1;
+ unsigned int cmd : 2;
+ unsigned int size : 3;
+ unsigned int wr_spu_mem : 1;
+ unsigned int dummy1 : 25;
+} reg_iop_sw_cpu_rw_mc_ctrl;
+#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12
+#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12
+
+/* Register rw_mc_data, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_cpu_rw_mc_data;
+#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16
+#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16
+
+/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
+typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
+#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20
+#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20
+
+/* Register rs_mc_data, scope iop_sw_cpu, type rs */
+typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
+#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24
+
+/* Register r_mc_data, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_mc_data;
+#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28
+
+/* Register r_mc_stat, scope iop_sw_cpu, type r */
+typedef struct {
+ unsigned int busy_cpu : 1;
+ unsigned int busy_mpu : 1;
+ unsigned int busy_spu : 1;
+ unsigned int owned_by_cpu : 1;
+ unsigned int owned_by_mpu : 1;
+ unsigned int owned_by_spu : 1;
+ unsigned int dummy1 : 26;
+} reg_iop_sw_cpu_r_mc_stat;
+#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32
+
+/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int byte0 : 8;
+ unsigned int byte1 : 8;
+ unsigned int byte2 : 8;
+ unsigned int byte3 : 8;
+} reg_iop_sw_cpu_rw_bus_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36
+
+/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int byte0 : 8;
+ unsigned int byte1 : 8;
+ unsigned int byte2 : 8;
+ unsigned int byte3 : 8;
+} reg_iop_sw_cpu_rw_bus_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40
+
+/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int byte0 : 1;
+ unsigned int byte1 : 1;
+ unsigned int byte2 : 1;
+ unsigned int byte3 : 1;
+ unsigned int dummy1 : 28;
+} reg_iop_sw_cpu_rw_bus_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44
+
+/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int byte0 : 1;
+ unsigned int byte1 : 1;
+ unsigned int byte2 : 1;
+ unsigned int byte3 : 1;
+ unsigned int dummy1 : 28;
+} reg_iop_sw_cpu_rw_bus_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
+#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48
+
+/* Register r_bus_in, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_bus_in;
+#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52
+
+/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56
+
+/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_cpu_rw_gio_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
+#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68
+
+/* Register r_gio_in, scope iop_sw_cpu, type r */
+typedef unsigned int reg_iop_sw_cpu_r_gio_in;
+#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72
+
+/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int mpu_0 : 1;
+ unsigned int mpu_1 : 1;
+ unsigned int mpu_2 : 1;
+ unsigned int mpu_3 : 1;
+ unsigned int mpu_4 : 1;
+ unsigned int mpu_5 : 1;
+ unsigned int mpu_6 : 1;
+ unsigned int mpu_7 : 1;
+ unsigned int mpu_8 : 1;
+ unsigned int mpu_9 : 1;
+ unsigned int mpu_10 : 1;
+ unsigned int mpu_11 : 1;
+ unsigned int mpu_12 : 1;
+ unsigned int mpu_13 : 1;
+ unsigned int mpu_14 : 1;
+ unsigned int mpu_15 : 1;
+ unsigned int spu_0 : 1;
+ unsigned int spu_1 : 1;
+ unsigned int spu_2 : 1;
+ unsigned int spu_3 : 1;
+ unsigned int spu_4 : 1;
+ unsigned int spu_5 : 1;
+ unsigned int spu_6 : 1;
+ unsigned int spu_7 : 1;
+ unsigned int spu_8 : 1;
+ unsigned int spu_9 : 1;
+ unsigned int spu_10 : 1;
+ unsigned int spu_11 : 1;
+ unsigned int spu_12 : 1;
+ unsigned int spu_13 : 1;
+ unsigned int spu_14 : 1;
+ unsigned int spu_15 : 1;
+} reg_iop_sw_cpu_rw_intr0_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76
+#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76
+
+/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int mpu_0 : 1;
+ unsigned int mpu_1 : 1;
+ unsigned int mpu_2 : 1;
+ unsigned int mpu_3 : 1;
+ unsigned int mpu_4 : 1;
+ unsigned int mpu_5 : 1;
+ unsigned int mpu_6 : 1;
+ unsigned int mpu_7 : 1;
+ unsigned int mpu_8 : 1;
+ unsigned int mpu_9 : 1;
+ unsigned int mpu_10 : 1;
+ unsigned int mpu_11 : 1;
+ unsigned int mpu_12 : 1;
+ unsigned int mpu_13 : 1;
+ unsigned int mpu_14 : 1;
+ unsigned int mpu_15 : 1;
+ unsigned int spu_0 : 1;
+ unsigned int spu_1 : 1;
+ unsigned int spu_2 : 1;
+ unsigned int spu_3 : 1;
+ unsigned int spu_4 : 1;
+ unsigned int spu_5 : 1;
+ unsigned int spu_6 : 1;
+ unsigned int spu_7 : 1;
+ unsigned int spu_8 : 1;
+ unsigned int spu_9 : 1;
+ unsigned int spu_10 : 1;
+ unsigned int spu_11 : 1;
+ unsigned int spu_12 : 1;
+ unsigned int spu_13 : 1;
+ unsigned int spu_14 : 1;
+ unsigned int spu_15 : 1;
+} reg_iop_sw_cpu_rw_ack_intr0;
+#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80
+#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80
+
+/* Register r_intr0, scope iop_sw_cpu, type r */
+typedef struct {
+ unsigned int mpu_0 : 1;
+ unsigned int mpu_1 : 1;
+ unsigned int mpu_2 : 1;
+ unsigned int mpu_3 : 1;
+ unsigned int mpu_4 : 1;
+ unsigned int mpu_5 : 1;
+ unsigned int mpu_6 : 1;
+ unsigned int mpu_7 : 1;
+ unsigned int mpu_8 : 1;
+ unsigned int mpu_9 : 1;
+ unsigned int mpu_10 : 1;
+ unsigned int mpu_11 : 1;
+ unsigned int mpu_12 : 1;
+ unsigned int mpu_13 : 1;
+ unsigned int mpu_14 : 1;
+ unsigned int mpu_15 : 1;
+ unsigned int spu_0 : 1;
+ unsigned int spu_1 : 1;
+ unsigned int spu_2 : 1;
+ unsigned int spu_3 : 1;
+ unsigned int spu_4 : 1;
+ unsigned int spu_5 : 1;
+ unsigned int spu_6 : 1;
+ unsigned int spu_7 : 1;
+ unsigned int spu_8 : 1;
+ unsigned int spu_9 : 1;
+ unsigned int spu_10 : 1;
+ unsigned int spu_11 : 1;
+ unsigned int spu_12 : 1;
+ unsigned int spu_13 : 1;
+ unsigned int spu_14 : 1;
+ unsigned int spu_15 : 1;
+} reg_iop_sw_cpu_r_intr0;
+#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84
+
+/* Register r_masked_intr0, scope iop_sw_cpu, type r */
+typedef struct {
+ unsigned int mpu_0 : 1;
+ unsigned int mpu_1 : 1;
+ unsigned int mpu_2 : 1;
+ unsigned int mpu_3 : 1;
+ unsigned int mpu_4 : 1;
+ unsigned int mpu_5 : 1;
+ unsigned int mpu_6 : 1;
+ unsigned int mpu_7 : 1;
+ unsigned int mpu_8 : 1;
+ unsigned int mpu_9 : 1;
+ unsigned int mpu_10 : 1;
+ unsigned int mpu_11 : 1;
+ unsigned int mpu_12 : 1;
+ unsigned int mpu_13 : 1;
+ unsigned int mpu_14 : 1;
+ unsigned int mpu_15 : 1;
+ unsigned int spu_0 : 1;
+ unsigned int spu_1 : 1;
+ unsigned int spu_2 : 1;
+ unsigned int spu_3 : 1;
+ unsigned int spu_4 : 1;
+ unsigned int spu_5 : 1;
+ unsigned int spu_6 : 1;
+ unsigned int spu_7 : 1;
+ unsigned int spu_8 : 1;
+ unsigned int spu_9 : 1;
+ unsigned int spu_10 : 1;
+ unsigned int spu_11 : 1;
+ unsigned int spu_12 : 1;
+ unsigned int spu_13 : 1;
+ unsigned int spu_14 : 1;
+ unsigned int spu_15 : 1;
+} reg_iop_sw_cpu_r_masked_intr0;
+#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88
+
+/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int mpu_16 : 1;
+ unsigned int mpu_17 : 1;
+ unsigned int mpu_18 : 1;
+ unsigned int mpu_19 : 1;
+ unsigned int mpu_20 : 1;
+ unsigned int mpu_21 : 1;
+ unsigned int mpu_22 : 1;
+ unsigned int mpu_23 : 1;
+ unsigned int mpu_24 : 1;
+ unsigned int mpu_25 : 1;
+ unsigned int mpu_26 : 1;
+ unsigned int mpu_27 : 1;
+ unsigned int mpu_28 : 1;
+ unsigned int mpu_29 : 1;
+ unsigned int mpu_30 : 1;
+ unsigned int mpu_31 : 1;
+ unsigned int dmc_in : 1;
+ unsigned int dmc_out : 1;
+ unsigned int fifo_in : 1;
+ unsigned int fifo_out : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int trigger_grp0 : 1;
+ unsigned int trigger_grp1 : 1;
+ unsigned int trigger_grp2 : 1;
+ unsigned int trigger_grp3 : 1;
+ unsigned int trigger_grp4 : 1;
+ unsigned int trigger_grp5 : 1;
+ unsigned int trigger_grp6 : 1;
+ unsigned int trigger_grp7 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int timer_grp1 : 1;
+} reg_iop_sw_cpu_rw_intr1_mask;
+#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92
+#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92
+
+/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
+typedef struct {
+ unsigned int mpu_16 : 1;
+ unsigned int mpu_17 : 1;
+ unsigned int mpu_18 : 1;
+ unsigned int mpu_19 : 1;
+ unsigned int mpu_20 : 1;
+ unsigned int mpu_21 : 1;
+ unsigned int mpu_22 : 1;
+ unsigned int mpu_23 : 1;
+ unsigned int mpu_24 : 1;
+ unsigned int mpu_25 : 1;
+ unsigned int mpu_26 : 1;
+ unsigned int mpu_27 : 1;
+ unsigned int mpu_28 : 1;
+ unsigned int mpu_29 : 1;
+ unsigned int mpu_30 : 1;
+ unsigned int mpu_31 : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_cpu_rw_ack_intr1;
+#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96
+#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96
+
+/* Register r_intr1, scope iop_sw_cpu, type r */
+typedef struct {
+ unsigned int mpu_16 : 1;
+ unsigned int mpu_17 : 1;
+ unsigned int mpu_18 : 1;
+ unsigned int mpu_19 : 1;
+ unsigned int mpu_20 : 1;
+ unsigned int mpu_21 : 1;
+ unsigned int mpu_22 : 1;
+ unsigned int mpu_23 : 1;
+ unsigned int mpu_24 : 1;
+ unsigned int mpu_25 : 1;
+ unsigned int mpu_26 : 1;
+ unsigned int mpu_27 : 1;
+ unsigned int mpu_28 : 1;
+ unsigned int mpu_29 : 1;
+ unsigned int mpu_30 : 1;
+ unsigned int mpu_31 : 1;
+ unsigned int dmc_in : 1;
+ unsigned int dmc_out : 1;
+ unsigned int fifo_in : 1;
+ unsigned int fifo_out : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int trigger_grp0 : 1;
+ unsigned int trigger_grp1 : 1;
+ unsigned int trigger_grp2 : 1;
+ unsigned int trigger_grp3 : 1;
+ unsigned int trigger_grp4 : 1;
+ unsigned int trigger_grp5 : 1;
+ unsigned int trigger_grp6 : 1;
+ unsigned int trigger_grp7 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int timer_grp1 : 1;
+} reg_iop_sw_cpu_r_intr1;
+#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100
+
+/* Register r_masked_intr1, scope iop_sw_cpu, type r */
+typedef struct {
+ unsigned int mpu_16 : 1;
+ unsigned int mpu_17 : 1;
+ unsigned int mpu_18 : 1;
+ unsigned int mpu_19 : 1;
+ unsigned int mpu_20 : 1;
+ unsigned int mpu_21 : 1;
+ unsigned int mpu_22 : 1;
+ unsigned int mpu_23 : 1;
+ unsigned int mpu_24 : 1;
+ unsigned int mpu_25 : 1;
+ unsigned int mpu_26 : 1;
+ unsigned int mpu_27 : 1;
+ unsigned int mpu_28 : 1;
+ unsigned int mpu_29 : 1;
+ unsigned int mpu_30 : 1;
+ unsigned int mpu_31 : 1;
+ unsigned int dmc_in : 1;
+ unsigned int dmc_out : 1;
+ unsigned int fifo_in : 1;
+ unsigned int fifo_out : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int trigger_grp0 : 1;
+ unsigned int trigger_grp1 : 1;
+ unsigned int trigger_grp2 : 1;
+ unsigned int trigger_grp3 : 1;
+ unsigned int trigger_grp4 : 1;
+ unsigned int trigger_grp5 : 1;
+ unsigned int trigger_grp6 : 1;
+ unsigned int trigger_grp7 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int timer_grp1 : 1;
+} reg_iop_sw_cpu_r_masked_intr1;
+#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104
+
+
+/* Constants */
+enum {
+ regk_iop_sw_cpu_copy = 0x00000000,
+ regk_iop_sw_cpu_no = 0x00000000,
+ regk_iop_sw_cpu_rd = 0x00000002,
+ regk_iop_sw_cpu_reg_copy = 0x00000001,
+ regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000,
+ regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000,
+ regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000,
+ regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000,
+ regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000,
+ regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
+ regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
+ regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,
+ regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000,
+ regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000,
+ regk_iop_sw_cpu_wr = 0x00000003,
+ regk_iop_sw_cpu_yes = 0x00000001
+};
+#endif /* __iop_sw_cpu_defs_h */
--- /dev/null
+#ifndef __iop_sw_mpu_defs_h
+#define __iop_sw_mpu_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sw_mpu.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_mpu */
+
+/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int cfg : 2;
+ unsigned int dummy1 : 30;
+} reg_iop_sw_mpu_rw_sw_cfg_owner;
+#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
+#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0
+
+/* Register r_spu_trace, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_spu_trace;
+#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4
+
+/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace;
+#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8
+
+/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int keep_owner : 1;
+ unsigned int cmd : 2;
+ unsigned int size : 3;
+ unsigned int wr_spu_mem : 1;
+ unsigned int dummy1 : 25;
+} reg_iop_sw_mpu_rw_mc_ctrl;
+#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12
+#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12
+
+/* Register rw_mc_data, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_mpu_rw_mc_data;
+#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16
+#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16
+
+/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
+typedef unsigned int reg_iop_sw_mpu_rw_mc_addr;
+#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20
+#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20
+
+/* Register rs_mc_data, scope iop_sw_mpu, type rs */
+typedef unsigned int reg_iop_sw_mpu_rs_mc_data;
+#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24
+
+/* Register r_mc_data, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_mc_data;
+#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28
+
+/* Register r_mc_stat, scope iop_sw_mpu, type r */
+typedef struct {
+ unsigned int busy_cpu : 1;
+ unsigned int busy_mpu : 1;
+ unsigned int busy_spu : 1;
+ unsigned int owned_by_cpu : 1;
+ unsigned int owned_by_mpu : 1;
+ unsigned int owned_by_spu : 1;
+ unsigned int dummy1 : 26;
+} reg_iop_sw_mpu_r_mc_stat;
+#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32
+
+/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int byte0 : 8;
+ unsigned int byte1 : 8;
+ unsigned int byte2 : 8;
+ unsigned int byte3 : 8;
+} reg_iop_sw_mpu_rw_bus_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36
+
+/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int byte0 : 8;
+ unsigned int byte1 : 8;
+ unsigned int byte2 : 8;
+ unsigned int byte3 : 8;
+} reg_iop_sw_mpu_rw_bus_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40
+
+/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int byte0 : 1;
+ unsigned int byte1 : 1;
+ unsigned int byte2 : 1;
+ unsigned int byte3 : 1;
+ unsigned int dummy1 : 28;
+} reg_iop_sw_mpu_rw_bus_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44
+
+/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int byte0 : 1;
+ unsigned int byte1 : 1;
+ unsigned int byte2 : 1;
+ unsigned int byte3 : 1;
+ unsigned int dummy1 : 28;
+} reg_iop_sw_mpu_rw_bus_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
+#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48
+
+/* Register r_bus_in, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_bus_in;
+#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52
+
+/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56
+
+/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_mpu_rw_gio_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
+#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68
+
+/* Register r_gio_in, scope iop_sw_mpu, type r */
+typedef unsigned int reg_iop_sw_mpu_r_gio_in;
+#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72
+
+/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int intr0 : 1;
+ unsigned int intr1 : 1;
+ unsigned int intr2 : 1;
+ unsigned int intr3 : 1;
+ unsigned int intr4 : 1;
+ unsigned int intr5 : 1;
+ unsigned int intr6 : 1;
+ unsigned int intr7 : 1;
+ unsigned int intr8 : 1;
+ unsigned int intr9 : 1;
+ unsigned int intr10 : 1;
+ unsigned int intr11 : 1;
+ unsigned int intr12 : 1;
+ unsigned int intr13 : 1;
+ unsigned int intr14 : 1;
+ unsigned int intr15 : 1;
+ unsigned int intr16 : 1;
+ unsigned int intr17 : 1;
+ unsigned int intr18 : 1;
+ unsigned int intr19 : 1;
+ unsigned int intr20 : 1;
+ unsigned int intr21 : 1;
+ unsigned int intr22 : 1;
+ unsigned int intr23 : 1;
+ unsigned int intr24 : 1;
+ unsigned int intr25 : 1;
+ unsigned int intr26 : 1;
+ unsigned int intr27 : 1;
+ unsigned int intr28 : 1;
+ unsigned int intr29 : 1;
+ unsigned int intr30 : 1;
+ unsigned int intr31 : 1;
+} reg_iop_sw_mpu_rw_cpu_intr;
+#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76
+#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76
+
+/* Register r_cpu_intr, scope iop_sw_mpu, type r */
+typedef struct {
+ unsigned int intr0 : 1;
+ unsigned int intr1 : 1;
+ unsigned int intr2 : 1;
+ unsigned int intr3 : 1;
+ unsigned int intr4 : 1;
+ unsigned int intr5 : 1;
+ unsigned int intr6 : 1;
+ unsigned int intr7 : 1;
+ unsigned int intr8 : 1;
+ unsigned int intr9 : 1;
+ unsigned int intr10 : 1;
+ unsigned int intr11 : 1;
+ unsigned int intr12 : 1;
+ unsigned int intr13 : 1;
+ unsigned int intr14 : 1;
+ unsigned int intr15 : 1;
+ unsigned int intr16 : 1;
+ unsigned int intr17 : 1;
+ unsigned int intr18 : 1;
+ unsigned int intr19 : 1;
+ unsigned int intr20 : 1;
+ unsigned int intr21 : 1;
+ unsigned int intr22 : 1;
+ unsigned int intr23 : 1;
+ unsigned int intr24 : 1;
+ unsigned int intr25 : 1;
+ unsigned int intr26 : 1;
+ unsigned int intr27 : 1;
+ unsigned int intr28 : 1;
+ unsigned int intr29 : 1;
+ unsigned int intr30 : 1;
+ unsigned int intr31 : 1;
+} reg_iop_sw_mpu_r_cpu_intr;
+#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80
+
+/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int spu_intr0 : 1;
+ unsigned int trigger_grp0 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr1 : 1;
+ unsigned int trigger_grp1 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int spu_intr2 : 1;
+ unsigned int trigger_grp2 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr3 : 1;
+ unsigned int trigger_grp3 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_rw_intr_grp0_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84
+
+/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int spu_intr0 : 1;
+ unsigned int dummy1 : 3;
+ unsigned int spu_intr1 : 1;
+ unsigned int dummy2 : 3;
+ unsigned int spu_intr2 : 1;
+ unsigned int dummy3 : 3;
+ unsigned int spu_intr3 : 1;
+ unsigned int dummy4 : 19;
+} reg_iop_sw_mpu_rw_ack_intr_grp0;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88
+
+/* Register r_intr_grp0, scope iop_sw_mpu, type r */
+typedef struct {
+ unsigned int spu_intr0 : 1;
+ unsigned int trigger_grp0 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr1 : 1;
+ unsigned int trigger_grp1 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int spu_intr2 : 1;
+ unsigned int trigger_grp2 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr3 : 1;
+ unsigned int trigger_grp3 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_r_intr_grp0;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92
+
+/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
+typedef struct {
+ unsigned int spu_intr0 : 1;
+ unsigned int trigger_grp0 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr1 : 1;
+ unsigned int trigger_grp1 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int spu_intr2 : 1;
+ unsigned int trigger_grp2 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr3 : 1;
+ unsigned int trigger_grp3 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_r_masked_intr_grp0;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96
+
+/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int spu_intr4 : 1;
+ unsigned int trigger_grp4 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr5 : 1;
+ unsigned int trigger_grp5 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int spu_intr6 : 1;
+ unsigned int trigger_grp6 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr7 : 1;
+ unsigned int trigger_grp7 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_rw_intr_grp1_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100
+
+/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int spu_intr4 : 1;
+ unsigned int dummy1 : 3;
+ unsigned int spu_intr5 : 1;
+ unsigned int dummy2 : 3;
+ unsigned int spu_intr6 : 1;
+ unsigned int dummy3 : 3;
+ unsigned int spu_intr7 : 1;
+ unsigned int dummy4 : 19;
+} reg_iop_sw_mpu_rw_ack_intr_grp1;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104
+
+/* Register r_intr_grp1, scope iop_sw_mpu, type r */
+typedef struct {
+ unsigned int spu_intr4 : 1;
+ unsigned int trigger_grp4 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr5 : 1;
+ unsigned int trigger_grp5 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int spu_intr6 : 1;
+ unsigned int trigger_grp6 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr7 : 1;
+ unsigned int trigger_grp7 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_r_intr_grp1;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108
+
+/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
+typedef struct {
+ unsigned int spu_intr4 : 1;
+ unsigned int trigger_grp4 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr5 : 1;
+ unsigned int trigger_grp5 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int spu_intr6 : 1;
+ unsigned int trigger_grp6 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr7 : 1;
+ unsigned int trigger_grp7 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_r_masked_intr_grp1;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112
+
+/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int spu_intr8 : 1;
+ unsigned int trigger_grp0 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr9 : 1;
+ unsigned int trigger_grp1 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int spu_intr10 : 1;
+ unsigned int trigger_grp2 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr11 : 1;
+ unsigned int trigger_grp3 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_rw_intr_grp2_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116
+
+/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int spu_intr8 : 1;
+ unsigned int dummy1 : 3;
+ unsigned int spu_intr9 : 1;
+ unsigned int dummy2 : 3;
+ unsigned int spu_intr10 : 1;
+ unsigned int dummy3 : 3;
+ unsigned int spu_intr11 : 1;
+ unsigned int dummy4 : 19;
+} reg_iop_sw_mpu_rw_ack_intr_grp2;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120
+
+/* Register r_intr_grp2, scope iop_sw_mpu, type r */
+typedef struct {
+ unsigned int spu_intr8 : 1;
+ unsigned int trigger_grp0 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr9 : 1;
+ unsigned int trigger_grp1 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int spu_intr10 : 1;
+ unsigned int trigger_grp2 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr11 : 1;
+ unsigned int trigger_grp3 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_r_intr_grp2;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124
+
+/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
+typedef struct {
+ unsigned int spu_intr8 : 1;
+ unsigned int trigger_grp0 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr9 : 1;
+ unsigned int trigger_grp1 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int spu_intr10 : 1;
+ unsigned int trigger_grp2 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr11 : 1;
+ unsigned int trigger_grp3 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_r_masked_intr_grp2;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128
+
+/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int spu_intr12 : 1;
+ unsigned int trigger_grp4 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr13 : 1;
+ unsigned int trigger_grp5 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int spu_intr14 : 1;
+ unsigned int trigger_grp6 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr15 : 1;
+ unsigned int trigger_grp7 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_rw_intr_grp3_mask;
+#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
+#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132
+
+/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
+typedef struct {
+ unsigned int spu_intr12 : 1;
+ unsigned int dummy1 : 3;
+ unsigned int spu_intr13 : 1;
+ unsigned int dummy2 : 3;
+ unsigned int spu_intr14 : 1;
+ unsigned int dummy3 : 3;
+ unsigned int spu_intr15 : 1;
+ unsigned int dummy4 : 19;
+} reg_iop_sw_mpu_rw_ack_intr_grp3;
+#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
+#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136
+
+/* Register r_intr_grp3, scope iop_sw_mpu, type r */
+typedef struct {
+ unsigned int spu_intr12 : 1;
+ unsigned int trigger_grp4 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr13 : 1;
+ unsigned int trigger_grp5 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int spu_intr14 : 1;
+ unsigned int trigger_grp6 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr15 : 1;
+ unsigned int trigger_grp7 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_r_intr_grp3;
+#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140
+
+/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
+typedef struct {
+ unsigned int spu_intr12 : 1;
+ unsigned int trigger_grp4 : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int spu_intr13 : 1;
+ unsigned int trigger_grp5 : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_in : 1;
+ unsigned int spu_intr14 : 1;
+ unsigned int trigger_grp6 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int spu_intr15 : 1;
+ unsigned int trigger_grp7 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_mpu_r_masked_intr_grp3;
+#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144
+
+
+/* Constants */
+enum {
+ regk_iop_sw_mpu_copy = 0x00000000,
+ regk_iop_sw_mpu_cpu = 0x00000000,
+ regk_iop_sw_mpu_mpu = 0x00000001,
+ regk_iop_sw_mpu_no = 0x00000000,
+ regk_iop_sw_mpu_nop = 0x00000000,
+ regk_iop_sw_mpu_rd = 0x00000002,
+ regk_iop_sw_mpu_reg_copy = 0x00000001,
+ regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000,
+ regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,
+ regk_iop_sw_mpu_set = 0x00000001,
+ regk_iop_sw_mpu_spu = 0x00000002,
+ regk_iop_sw_mpu_wr = 0x00000003,
+ regk_iop_sw_mpu_yes = 0x00000001
+};
+#endif /* __iop_sw_mpu_defs_h */
--- /dev/null
+#ifndef __iop_sw_spu_defs_h
+#define __iop_sw_spu_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_sw_spu.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_sw_spu */
+
+/* Register r_mpu_trace, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_mpu_trace;
+#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0
+
+/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int keep_owner : 1;
+ unsigned int cmd : 2;
+ unsigned int size : 3;
+ unsigned int wr_spu_mem : 1;
+ unsigned int dummy1 : 25;
+} reg_iop_sw_spu_rw_mc_ctrl;
+#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4
+#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4
+
+/* Register rw_mc_data, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_spu_rw_mc_data;
+#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8
+#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8
+
+/* Register rw_mc_addr, scope iop_sw_spu, type rw */
+typedef unsigned int reg_iop_sw_spu_rw_mc_addr;
+#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12
+#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12
+
+/* Register rs_mc_data, scope iop_sw_spu, type rs */
+typedef unsigned int reg_iop_sw_spu_rs_mc_data;
+#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16
+
+/* Register r_mc_data, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_mc_data;
+#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20
+
+/* Register r_mc_stat, scope iop_sw_spu, type r */
+typedef struct {
+ unsigned int busy_cpu : 1;
+ unsigned int busy_mpu : 1;
+ unsigned int busy_spu : 1;
+ unsigned int owned_by_cpu : 1;
+ unsigned int owned_by_mpu : 1;
+ unsigned int owned_by_spu : 1;
+ unsigned int dummy1 : 26;
+} reg_iop_sw_spu_r_mc_stat;
+#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24
+
+/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int byte0 : 8;
+ unsigned int byte1 : 8;
+ unsigned int byte2 : 8;
+ unsigned int byte3 : 8;
+} reg_iop_sw_spu_rw_bus_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28
+#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28
+
+/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int byte0 : 8;
+ unsigned int byte1 : 8;
+ unsigned int byte2 : 8;
+ unsigned int byte3 : 8;
+} reg_iop_sw_spu_rw_bus_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32
+#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32
+
+/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int byte0 : 1;
+ unsigned int byte1 : 1;
+ unsigned int byte2 : 1;
+ unsigned int byte3 : 1;
+ unsigned int dummy1 : 28;
+} reg_iop_sw_spu_rw_bus_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
+#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36
+
+/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int byte0 : 1;
+ unsigned int byte1 : 1;
+ unsigned int byte2 : 1;
+ unsigned int byte3 : 1;
+ unsigned int dummy1 : 28;
+} reg_iop_sw_spu_rw_bus_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
+#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40
+
+/* Register r_bus_in, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_bus_in;
+#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44
+
+/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48
+
+/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52
+
+/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_oe_clr_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56
+
+/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 32;
+} reg_iop_sw_spu_rw_gio_oe_set_mask;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60
+
+/* Register r_gio_in, scope iop_sw_spu, type r */
+typedef unsigned int reg_iop_sw_spu_r_gio_in;
+#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64
+
+/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int byte0 : 8;
+ unsigned int byte1 : 8;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus_clr_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
+#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68
+
+/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int byte2 : 8;
+ unsigned int byte3 : 8;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus_clr_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
+#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72
+
+/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int byte0 : 8;
+ unsigned int byte1 : 8;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus_set_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
+#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76
+
+/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int byte2 : 8;
+ unsigned int byte3 : 8;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_bus_set_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
+#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80
+
+/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 16;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_clr_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84
+
+/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 16;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_clr_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88
+
+/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 16;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_set_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92
+
+/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 16;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_set_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96
+
+/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 16;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100
+
+/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 16;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104
+
+/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 16;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_set_mask_lo;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108
+
+/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int val : 16;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_gio_oe_set_mask_hi;
+#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
+#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112
+
+/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int intr0 : 1;
+ unsigned int intr1 : 1;
+ unsigned int intr2 : 1;
+ unsigned int intr3 : 1;
+ unsigned int intr4 : 1;
+ unsigned int intr5 : 1;
+ unsigned int intr6 : 1;
+ unsigned int intr7 : 1;
+ unsigned int intr8 : 1;
+ unsigned int intr9 : 1;
+ unsigned int intr10 : 1;
+ unsigned int intr11 : 1;
+ unsigned int intr12 : 1;
+ unsigned int intr13 : 1;
+ unsigned int intr14 : 1;
+ unsigned int intr15 : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_cpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116
+#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116
+
+/* Register r_cpu_intr, scope iop_sw_spu, type r */
+typedef struct {
+ unsigned int intr0 : 1;
+ unsigned int intr1 : 1;
+ unsigned int intr2 : 1;
+ unsigned int intr3 : 1;
+ unsigned int intr4 : 1;
+ unsigned int intr5 : 1;
+ unsigned int intr6 : 1;
+ unsigned int intr7 : 1;
+ unsigned int intr8 : 1;
+ unsigned int intr9 : 1;
+ unsigned int intr10 : 1;
+ unsigned int intr11 : 1;
+ unsigned int intr12 : 1;
+ unsigned int intr13 : 1;
+ unsigned int intr14 : 1;
+ unsigned int intr15 : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_r_cpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120
+
+/* Register r_hw_intr, scope iop_sw_spu, type r */
+typedef struct {
+ unsigned int trigger_grp0 : 1;
+ unsigned int trigger_grp1 : 1;
+ unsigned int trigger_grp2 : 1;
+ unsigned int trigger_grp3 : 1;
+ unsigned int trigger_grp4 : 1;
+ unsigned int trigger_grp5 : 1;
+ unsigned int trigger_grp6 : 1;
+ unsigned int trigger_grp7 : 1;
+ unsigned int timer_grp0 : 1;
+ unsigned int timer_grp1 : 1;
+ unsigned int fifo_out : 1;
+ unsigned int fifo_out_extra : 1;
+ unsigned int fifo_in : 1;
+ unsigned int fifo_in_extra : 1;
+ unsigned int dmc_out : 1;
+ unsigned int dmc_in : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_r_hw_intr;
+#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124
+
+/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
+typedef struct {
+ unsigned int intr0 : 1;
+ unsigned int intr1 : 1;
+ unsigned int intr2 : 1;
+ unsigned int intr3 : 1;
+ unsigned int intr4 : 1;
+ unsigned int intr5 : 1;
+ unsigned int intr6 : 1;
+ unsigned int intr7 : 1;
+ unsigned int intr8 : 1;
+ unsigned int intr9 : 1;
+ unsigned int intr10 : 1;
+ unsigned int intr11 : 1;
+ unsigned int intr12 : 1;
+ unsigned int intr13 : 1;
+ unsigned int intr14 : 1;
+ unsigned int intr15 : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_rw_mpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128
+#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128
+
+/* Register r_mpu_intr, scope iop_sw_spu, type r */
+typedef struct {
+ unsigned int intr0 : 1;
+ unsigned int intr1 : 1;
+ unsigned int intr2 : 1;
+ unsigned int intr3 : 1;
+ unsigned int intr4 : 1;
+ unsigned int intr5 : 1;
+ unsigned int intr6 : 1;
+ unsigned int intr7 : 1;
+ unsigned int intr8 : 1;
+ unsigned int intr9 : 1;
+ unsigned int intr10 : 1;
+ unsigned int intr11 : 1;
+ unsigned int intr12 : 1;
+ unsigned int intr13 : 1;
+ unsigned int intr14 : 1;
+ unsigned int intr15 : 1;
+ unsigned int dummy1 : 16;
+} reg_iop_sw_spu_r_mpu_intr;
+#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132
+
+
+/* Constants */
+enum {
+ regk_iop_sw_spu_copy = 0x00000000,
+ regk_iop_sw_spu_no = 0x00000000,
+ regk_iop_sw_spu_nop = 0x00000000,
+ regk_iop_sw_spu_rd = 0x00000002,
+ regk_iop_sw_spu_reg_copy = 0x00000001,
+ regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000,
+ regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000,
+ regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000,
+ regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000,
+ regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000,
+ regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000,
+ regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,
+ regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000,
+ regk_iop_sw_spu_set = 0x00000001,
+ regk_iop_sw_spu_wr = 0x00000003,
+ regk_iop_sw_spu_yes = 0x00000001
+};
+#endif /* __iop_sw_spu_defs_h */
--- /dev/null
+#ifndef __iop_version_defs_h
+#define __iop_version_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: iop_version.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope iop_version */
+
+/* Register r_version, scope iop_version, type r */
+typedef struct {
+ unsigned int nr : 8;
+ unsigned int dummy1 : 24;
+} reg_iop_version_r_version;
+#define REG_RD_ADDR_iop_version_r_version 0
+
+
+/* Constants */
+enum {
+ regk_iop_version_v2_0 = 0x00000002
+};
+#endif /* __iop_version_defs_h */
--- /dev/null
+#ifndef __l2cache_defs_h
+#define __l2cache_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: l2cache.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile l2cache_defs.h l2cache.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope l2cache */
+
+/* Register rw_cfg, scope l2cache, type rw */
+typedef struct {
+ unsigned int en : 1;
+ unsigned int dummy1 : 31;
+} reg_l2cache_rw_cfg;
+#define REG_RD_ADDR_l2cache_rw_cfg 0
+#define REG_WR_ADDR_l2cache_rw_cfg 0
+
+/* Register rw_ctrl, scope l2cache, type rw */
+typedef struct {
+ unsigned int dummy1 : 7;
+ unsigned int cbase : 9;
+ unsigned int dummy2 : 4;
+ unsigned int csize : 10;
+ unsigned int dummy3 : 2;
+} reg_l2cache_rw_ctrl;
+#define REG_RD_ADDR_l2cache_rw_ctrl 4
+#define REG_WR_ADDR_l2cache_rw_ctrl 4
+
+/* Register rw_idxop, scope l2cache, type rw */
+typedef struct {
+ unsigned int idx : 10;
+ unsigned int dummy1 : 14;
+ unsigned int way : 3;
+ unsigned int dummy2 : 2;
+ unsigned int cmd : 3;
+} reg_l2cache_rw_idxop;
+#define REG_RD_ADDR_l2cache_rw_idxop 8
+#define REG_WR_ADDR_l2cache_rw_idxop 8
+
+/* Register rw_addrop_addr, scope l2cache, type rw */
+typedef struct {
+ unsigned int addr : 32;
+} reg_l2cache_rw_addrop_addr;
+#define REG_RD_ADDR_l2cache_rw_addrop_addr 12
+#define REG_WR_ADDR_l2cache_rw_addrop_addr 12
+
+/* Register rw_addrop_ctrl, scope l2cache, type rw */
+typedef struct {
+ unsigned int size : 16;
+ unsigned int dummy1 : 13;
+ unsigned int cmd : 3;
+} reg_l2cache_rw_addrop_ctrl;
+#define REG_RD_ADDR_l2cache_rw_addrop_ctrl 16
+#define REG_WR_ADDR_l2cache_rw_addrop_ctrl 16
+
+
+/* Constants */
+enum {
+ regk_l2cache_flush = 0x00000001,
+ regk_l2cache_no = 0x00000000,
+ regk_l2cache_rw_addrop_addr_default = 0x00000000,
+ regk_l2cache_rw_addrop_ctrl_default = 0x00000000,
+ regk_l2cache_rw_cfg_default = 0x00000000,
+ regk_l2cache_rw_ctrl_default = 0x00000000,
+ regk_l2cache_rw_idxop_default = 0x00000000,
+ regk_l2cache_yes = 0x00000001
+};
+#endif /* __l2cache_defs_h */
--- /dev/null
+#ifndef __marb_bar_defs_h
+#define __marb_bar_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: marb_bar.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope marb_bar */
+
+#define STRIDE_marb_bar_rw_ddr2_slots 4
+/* Register rw_ddr2_slots, scope marb_bar, type rw */
+typedef struct {
+ unsigned int owner : 4;
+ unsigned int dummy1 : 28;
+} reg_marb_bar_rw_ddr2_slots;
+#define REG_RD_ADDR_marb_bar_rw_ddr2_slots 0
+#define REG_WR_ADDR_marb_bar_rw_ddr2_slots 0
+
+/* Register rw_h264_rd_burst, scope marb_bar, type rw */
+typedef struct {
+ unsigned int ddr2_bsize : 2;
+ unsigned int dummy1 : 30;
+} reg_marb_bar_rw_h264_rd_burst;
+#define REG_RD_ADDR_marb_bar_rw_h264_rd_burst 256
+#define REG_WR_ADDR_marb_bar_rw_h264_rd_burst 256
+
+/* Register rw_h264_wr_burst, scope marb_bar, type rw */
+typedef struct {
+ unsigned int ddr2_bsize : 2;
+ unsigned int dummy1 : 30;
+} reg_marb_bar_rw_h264_wr_burst;
+#define REG_RD_ADDR_marb_bar_rw_h264_wr_burst 260
+#define REG_WR_ADDR_marb_bar_rw_h264_wr_burst 260
+
+/* Register rw_ccd_burst, scope marb_bar, type rw */
+typedef struct {
+ unsigned int ddr2_bsize : 2;
+ unsigned int dummy1 : 30;
+} reg_marb_bar_rw_ccd_burst;
+#define REG_RD_ADDR_marb_bar_rw_ccd_burst 264
+#define REG_WR_ADDR_marb_bar_rw_ccd_burst 264
+
+/* Register rw_vin_wr_burst, scope marb_bar, type rw */
+typedef struct {
+ unsigned int ddr2_bsize : 2;
+ unsigned int dummy1 : 30;
+} reg_marb_bar_rw_vin_wr_burst;
+#define REG_RD_ADDR_marb_bar_rw_vin_wr_burst 268
+#define REG_WR_ADDR_marb_bar_rw_vin_wr_burst 268
+
+/* Register rw_vin_rd_burst, scope marb_bar, type rw */
+typedef struct {
+ unsigned int ddr2_bsize : 2;
+ unsigned int dummy1 : 30;
+} reg_marb_bar_rw_vin_rd_burst;
+#define REG_RD_ADDR_marb_bar_rw_vin_rd_burst 272
+#define REG_WR_ADDR_marb_bar_rw_vin_rd_burst 272
+
+/* Register rw_sclr_rd_burst, scope marb_bar, type rw */
+typedef struct {
+ unsigned int ddr2_bsize : 2;
+ unsigned int dummy1 : 30;
+} reg_marb_bar_rw_sclr_rd_burst;
+#define REG_RD_ADDR_marb_bar_rw_sclr_rd_burst 276
+#define REG_WR_ADDR_marb_bar_rw_sclr_rd_burst 276
+
+/* Register rw_vout_burst, scope marb_bar, type rw */
+typedef struct {
+ unsigned int ddr2_bsize : 2;
+ unsigned int dummy1 : 30;
+} reg_marb_bar_rw_vout_burst;
+#define REG_RD_ADDR_marb_bar_rw_vout_burst 280
+#define REG_WR_ADDR_marb_bar_rw_vout_burst 280
+
+/* Register rw_sclr_fifo_burst, scope marb_bar, type rw */
+typedef struct {
+ unsigned int ddr2_bsize : 2;
+ unsigned int dummy1 : 30;
+} reg_marb_bar_rw_sclr_fifo_burst;
+#define REG_RD_ADDR_marb_bar_rw_sclr_fifo_burst 284
+#define REG_WR_ADDR_marb_bar_rw_sclr_fifo_burst 284
+
+/* Register rw_l2cache_burst, scope marb_bar, type rw */
+typedef struct {
+ unsigned int ddr2_bsize : 2;
+ unsigned int dummy1 : 30;
+} reg_marb_bar_rw_l2cache_burst;
+#define REG_RD_ADDR_marb_bar_rw_l2cache_burst 288
+#define REG_WR_ADDR_marb_bar_rw_l2cache_burst 288
+
+/* Register rw_intr_mask, scope marb_bar, type rw */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_bar_rw_intr_mask;
+#define REG_RD_ADDR_marb_bar_rw_intr_mask 292
+#define REG_WR_ADDR_marb_bar_rw_intr_mask 292
+
+/* Register rw_ack_intr, scope marb_bar, type rw */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_bar_rw_ack_intr;
+#define REG_RD_ADDR_marb_bar_rw_ack_intr 296
+#define REG_WR_ADDR_marb_bar_rw_ack_intr 296
+
+/* Register r_intr, scope marb_bar, type r */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_bar_r_intr;
+#define REG_RD_ADDR_marb_bar_r_intr 300
+
+/* Register r_masked_intr, scope marb_bar, type r */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_bar_r_masked_intr;
+#define REG_RD_ADDR_marb_bar_r_masked_intr 304
+
+/* Register rw_stop_mask, scope marb_bar, type rw */
+typedef struct {
+ unsigned int h264_rd : 1;
+ unsigned int h264_wr : 1;
+ unsigned int ccd : 1;
+ unsigned int vin_wr : 1;
+ unsigned int vin_rd : 1;
+ unsigned int sclr_rd : 1;
+ unsigned int vout : 1;
+ unsigned int sclr_fifo : 1;
+ unsigned int l2cache : 1;
+ unsigned int dummy1 : 23;
+} reg_marb_bar_rw_stop_mask;
+#define REG_RD_ADDR_marb_bar_rw_stop_mask 308
+#define REG_WR_ADDR_marb_bar_rw_stop_mask 308
+
+/* Register r_stopped, scope marb_bar, type r */
+typedef struct {
+ unsigned int h264_rd : 1;
+ unsigned int h264_wr : 1;
+ unsigned int ccd : 1;
+ unsigned int vin_wr : 1;
+ unsigned int vin_rd : 1;
+ unsigned int sclr_rd : 1;
+ unsigned int vout : 1;
+ unsigned int sclr_fifo : 1;
+ unsigned int l2cache : 1;
+ unsigned int dummy1 : 23;
+} reg_marb_bar_r_stopped;
+#define REG_RD_ADDR_marb_bar_r_stopped 312
+
+/* Register rw_no_snoop, scope marb_bar, type rw */
+typedef struct {
+ unsigned int h264_rd : 1;
+ unsigned int h264_wr : 1;
+ unsigned int ccd : 1;
+ unsigned int vin_wr : 1;
+ unsigned int vin_rd : 1;
+ unsigned int sclr_rd : 1;
+ unsigned int vout : 1;
+ unsigned int sclr_fifo : 1;
+ unsigned int l2cache : 1;
+ unsigned int dummy1 : 23;
+} reg_marb_bar_rw_no_snoop;
+#define REG_RD_ADDR_marb_bar_rw_no_snoop 576
+#define REG_WR_ADDR_marb_bar_rw_no_snoop 576
+
+
+/* Constants */
+enum {
+ regk_marb_bar_ccd = 0x00000002,
+ regk_marb_bar_h264_rd = 0x00000000,
+ regk_marb_bar_h264_wr = 0x00000001,
+ regk_marb_bar_l2cache = 0x00000008,
+ regk_marb_bar_no = 0x00000000,
+ regk_marb_bar_r_stopped_default = 0x00000000,
+ regk_marb_bar_rw_ccd_burst_default = 0x00000000,
+ regk_marb_bar_rw_ddr2_slots_default = 0x00000000,
+ regk_marb_bar_rw_ddr2_slots_size = 0x00000040,
+ regk_marb_bar_rw_h264_rd_burst_default = 0x00000000,
+ regk_marb_bar_rw_h264_wr_burst_default = 0x00000000,
+ regk_marb_bar_rw_intr_mask_default = 0x00000000,
+ regk_marb_bar_rw_l2cache_burst_default = 0x00000000,
+ regk_marb_bar_rw_no_snoop_default = 0x00000000,
+ regk_marb_bar_rw_sclr_fifo_burst_default = 0x00000000,
+ regk_marb_bar_rw_sclr_rd_burst_default = 0x00000000,
+ regk_marb_bar_rw_stop_mask_default = 0x00000000,
+ regk_marb_bar_rw_vin_rd_burst_default = 0x00000000,
+ regk_marb_bar_rw_vin_wr_burst_default = 0x00000000,
+ regk_marb_bar_rw_vout_burst_default = 0x00000000,
+ regk_marb_bar_sclr_fifo = 0x00000007,
+ regk_marb_bar_sclr_rd = 0x00000005,
+ regk_marb_bar_vin_rd = 0x00000004,
+ regk_marb_bar_vin_wr = 0x00000003,
+ regk_marb_bar_vout = 0x00000006,
+ regk_marb_bar_yes = 0x00000001
+};
+#endif /* __marb_bar_defs_h */
+#ifndef __marb_bar_bp_defs_h
+#define __marb_bar_bp_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: marb_bar.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile marb_bar_defs.h marb_bar.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope marb_bar_bp */
+
+/* Register rw_first_addr, scope marb_bar_bp, type rw */
+typedef unsigned int reg_marb_bar_bp_rw_first_addr;
+#define REG_RD_ADDR_marb_bar_bp_rw_first_addr 0
+#define REG_WR_ADDR_marb_bar_bp_rw_first_addr 0
+
+/* Register rw_last_addr, scope marb_bar_bp, type rw */
+typedef unsigned int reg_marb_bar_bp_rw_last_addr;
+#define REG_RD_ADDR_marb_bar_bp_rw_last_addr 4
+#define REG_WR_ADDR_marb_bar_bp_rw_last_addr 4
+
+/* Register rw_op, scope marb_bar_bp, type rw */
+typedef struct {
+ unsigned int rd : 1;
+ unsigned int wr : 1;
+ unsigned int rd_excl : 1;
+ unsigned int pri_wr : 1;
+ unsigned int us_rd : 1;
+ unsigned int us_wr : 1;
+ unsigned int us_rd_excl : 1;
+ unsigned int us_pri_wr : 1;
+ unsigned int dummy1 : 24;
+} reg_marb_bar_bp_rw_op;
+#define REG_RD_ADDR_marb_bar_bp_rw_op 8
+#define REG_WR_ADDR_marb_bar_bp_rw_op 8
+
+/* Register rw_clients, scope marb_bar_bp, type rw */
+typedef struct {
+ unsigned int h264_rd : 1;
+ unsigned int h264_wr : 1;
+ unsigned int ccd : 1;
+ unsigned int vin_wr : 1;
+ unsigned int vin_rd : 1;
+ unsigned int sclr_rd : 1;
+ unsigned int vout : 1;
+ unsigned int sclr_fifo : 1;
+ unsigned int l2cache : 1;
+ unsigned int dummy1 : 23;
+} reg_marb_bar_bp_rw_clients;
+#define REG_RD_ADDR_marb_bar_bp_rw_clients 12
+#define REG_WR_ADDR_marb_bar_bp_rw_clients 12
+
+/* Register rw_options, scope marb_bar_bp, type rw */
+typedef struct {
+ unsigned int wrap : 1;
+ unsigned int dummy1 : 31;
+} reg_marb_bar_bp_rw_options;
+#define REG_RD_ADDR_marb_bar_bp_rw_options 16
+#define REG_WR_ADDR_marb_bar_bp_rw_options 16
+
+/* Register r_brk_addr, scope marb_bar_bp, type r */
+typedef unsigned int reg_marb_bar_bp_r_brk_addr;
+#define REG_RD_ADDR_marb_bar_bp_r_brk_addr 20
+
+/* Register r_brk_op, scope marb_bar_bp, type r */
+typedef struct {
+ unsigned int rd : 1;
+ unsigned int wr : 1;
+ unsigned int rd_excl : 1;
+ unsigned int pri_wr : 1;
+ unsigned int us_rd : 1;
+ unsigned int us_wr : 1;
+ unsigned int us_rd_excl : 1;
+ unsigned int us_pri_wr : 1;
+ unsigned int dummy1 : 24;
+} reg_marb_bar_bp_r_brk_op;
+#define REG_RD_ADDR_marb_bar_bp_r_brk_op 24
+
+/* Register r_brk_clients, scope marb_bar_bp, type r */
+typedef struct {
+ unsigned int h264_rd : 1;
+ unsigned int h264_wr : 1;
+ unsigned int ccd : 1;
+ unsigned int vin_wr : 1;
+ unsigned int vin_rd : 1;
+ unsigned int sclr_rd : 1;
+ unsigned int vout : 1;
+ unsigned int sclr_fifo : 1;
+ unsigned int l2cache : 1;
+ unsigned int dummy1 : 23;
+} reg_marb_bar_bp_r_brk_clients;
+#define REG_RD_ADDR_marb_bar_bp_r_brk_clients 28
+
+/* Register r_brk_first_client, scope marb_bar_bp, type r */
+typedef struct {
+ unsigned int h264_rd : 1;
+ unsigned int h264_wr : 1;
+ unsigned int ccd : 1;
+ unsigned int vin_wr : 1;
+ unsigned int vin_rd : 1;
+ unsigned int sclr_rd : 1;
+ unsigned int vout : 1;
+ unsigned int sclr_fifo : 1;
+ unsigned int l2cache : 1;
+ unsigned int dummy1 : 23;
+} reg_marb_bar_bp_r_brk_first_client;
+#define REG_RD_ADDR_marb_bar_bp_r_brk_first_client 32
+
+/* Register r_brk_size, scope marb_bar_bp, type r */
+typedef unsigned int reg_marb_bar_bp_r_brk_size;
+#define REG_RD_ADDR_marb_bar_bp_r_brk_size 36
+
+/* Register rw_ack, scope marb_bar_bp, type rw */
+typedef unsigned int reg_marb_bar_bp_rw_ack;
+#define REG_RD_ADDR_marb_bar_bp_rw_ack 40
+#define REG_WR_ADDR_marb_bar_bp_rw_ack 40
+
+
+/* Constants */
+enum {
+ regk_marb_bar_bp_no = 0x00000000,
+ regk_marb_bar_bp_rw_op_default = 0x00000000,
+ regk_marb_bar_bp_rw_options_default = 0x00000000,
+ regk_marb_bar_bp_yes = 0x00000001
+};
+#endif /* __marb_bar_bp_defs_h */
--- /dev/null
+#ifndef __marb_foo_defs_h
+#define __marb_foo_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: marb_foo.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope marb_foo */
+
+#define STRIDE_marb_foo_rw_intm_slots 4
+/* Register rw_intm_slots, scope marb_foo, type rw */
+typedef struct {
+ unsigned int owner : 4;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_intm_slots;
+#define REG_RD_ADDR_marb_foo_rw_intm_slots 0
+#define REG_WR_ADDR_marb_foo_rw_intm_slots 0
+
+#define STRIDE_marb_foo_rw_l2_slots 4
+/* Register rw_l2_slots, scope marb_foo, type rw */
+typedef struct {
+ unsigned int owner : 4;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_l2_slots;
+#define REG_RD_ADDR_marb_foo_rw_l2_slots 256
+#define REG_WR_ADDR_marb_foo_rw_l2_slots 256
+
+#define STRIDE_marb_foo_rw_regs_slots 4
+/* Register rw_regs_slots, scope marb_foo, type rw */
+typedef struct {
+ unsigned int owner : 4;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_regs_slots;
+#define REG_RD_ADDR_marb_foo_rw_regs_slots 512
+#define REG_WR_ADDR_marb_foo_rw_regs_slots 512
+
+/* Register rw_sclr_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_sclr_burst;
+#define REG_RD_ADDR_marb_foo_rw_sclr_burst 528
+#define REG_WR_ADDR_marb_foo_rw_sclr_burst 528
+
+/* Register rw_dma0_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_dma0_burst;
+#define REG_RD_ADDR_marb_foo_rw_dma0_burst 532
+#define REG_WR_ADDR_marb_foo_rw_dma0_burst 532
+
+/* Register rw_dma1_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_dma1_burst;
+#define REG_RD_ADDR_marb_foo_rw_dma1_burst 536
+#define REG_WR_ADDR_marb_foo_rw_dma1_burst 536
+
+/* Register rw_dma2_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_dma2_burst;
+#define REG_RD_ADDR_marb_foo_rw_dma2_burst 540
+#define REG_WR_ADDR_marb_foo_rw_dma2_burst 540
+
+/* Register rw_dma3_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_dma3_burst;
+#define REG_RD_ADDR_marb_foo_rw_dma3_burst 544
+#define REG_WR_ADDR_marb_foo_rw_dma3_burst 544
+
+/* Register rw_dma4_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_dma4_burst;
+#define REG_RD_ADDR_marb_foo_rw_dma4_burst 548
+#define REG_WR_ADDR_marb_foo_rw_dma4_burst 548
+
+/* Register rw_dma5_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_dma5_burst;
+#define REG_RD_ADDR_marb_foo_rw_dma5_burst 552
+#define REG_WR_ADDR_marb_foo_rw_dma5_burst 552
+
+/* Register rw_dma6_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_dma6_burst;
+#define REG_RD_ADDR_marb_foo_rw_dma6_burst 556
+#define REG_WR_ADDR_marb_foo_rw_dma6_burst 556
+
+/* Register rw_dma7_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_dma7_burst;
+#define REG_RD_ADDR_marb_foo_rw_dma7_burst 560
+#define REG_WR_ADDR_marb_foo_rw_dma7_burst 560
+
+/* Register rw_dma9_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_dma9_burst;
+#define REG_RD_ADDR_marb_foo_rw_dma9_burst 564
+#define REG_WR_ADDR_marb_foo_rw_dma9_burst 564
+
+/* Register rw_dma11_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_dma11_burst;
+#define REG_RD_ADDR_marb_foo_rw_dma11_burst 568
+#define REG_WR_ADDR_marb_foo_rw_dma11_burst 568
+
+/* Register rw_cpui_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_cpui_burst;
+#define REG_RD_ADDR_marb_foo_rw_cpui_burst 572
+#define REG_WR_ADDR_marb_foo_rw_cpui_burst 572
+
+/* Register rw_cpud_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_cpud_burst;
+#define REG_RD_ADDR_marb_foo_rw_cpud_burst 576
+#define REG_WR_ADDR_marb_foo_rw_cpud_burst 576
+
+/* Register rw_iop_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_iop_burst;
+#define REG_RD_ADDR_marb_foo_rw_iop_burst 580
+#define REG_WR_ADDR_marb_foo_rw_iop_burst 580
+
+/* Register rw_ccdstat_burst, scope marb_foo, type rw */
+typedef struct {
+ unsigned int intm_bsize : 2;
+ unsigned int l2_bsize : 2;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_ccdstat_burst;
+#define REG_RD_ADDR_marb_foo_rw_ccdstat_burst 584
+#define REG_WR_ADDR_marb_foo_rw_ccdstat_burst 584
+
+/* Register rw_intr_mask, scope marb_foo, type rw */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_intr_mask;
+#define REG_RD_ADDR_marb_foo_rw_intr_mask 588
+#define REG_WR_ADDR_marb_foo_rw_intr_mask 588
+
+/* Register rw_ack_intr, scope marb_foo, type rw */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_rw_ack_intr;
+#define REG_RD_ADDR_marb_foo_rw_ack_intr 592
+#define REG_WR_ADDR_marb_foo_rw_ack_intr 592
+
+/* Register r_intr, scope marb_foo, type r */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_r_intr;
+#define REG_RD_ADDR_marb_foo_r_intr 596
+
+/* Register r_masked_intr, scope marb_foo, type r */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_foo_r_masked_intr;
+#define REG_RD_ADDR_marb_foo_r_masked_intr 600
+
+/* Register rw_stop_mask, scope marb_foo, type rw */
+typedef struct {
+ unsigned int sclr : 1;
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma9 : 1;
+ unsigned int dma11 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int ccdstat : 1;
+ unsigned int dummy1 : 17;
+} reg_marb_foo_rw_stop_mask;
+#define REG_RD_ADDR_marb_foo_rw_stop_mask 604
+#define REG_WR_ADDR_marb_foo_rw_stop_mask 604
+
+/* Register r_stopped, scope marb_foo, type r */
+typedef struct {
+ unsigned int sclr : 1;
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma9 : 1;
+ unsigned int dma11 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int ccdstat : 1;
+ unsigned int dummy1 : 17;
+} reg_marb_foo_r_stopped;
+#define REG_RD_ADDR_marb_foo_r_stopped 608
+
+/* Register rw_no_snoop, scope marb_foo, type rw */
+typedef struct {
+ unsigned int sclr : 1;
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma9 : 1;
+ unsigned int dma11 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int ccdstat : 1;
+ unsigned int dummy1 : 17;
+} reg_marb_foo_rw_no_snoop;
+#define REG_RD_ADDR_marb_foo_rw_no_snoop 896
+#define REG_WR_ADDR_marb_foo_rw_no_snoop 896
+
+/* Register rw_no_snoop_rq, scope marb_foo, type rw */
+typedef struct {
+ unsigned int dummy1 : 11;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int dummy2 : 19;
+} reg_marb_foo_rw_no_snoop_rq;
+#define REG_RD_ADDR_marb_foo_rw_no_snoop_rq 900
+#define REG_WR_ADDR_marb_foo_rw_no_snoop_rq 900
+
+
+/* Constants */
+enum {
+ regk_marb_foo_ccdstat = 0x0000000e,
+ regk_marb_foo_cpud = 0x0000000c,
+ regk_marb_foo_cpui = 0x0000000b,
+ regk_marb_foo_dma0 = 0x00000001,
+ regk_marb_foo_dma1 = 0x00000002,
+ regk_marb_foo_dma11 = 0x0000000a,
+ regk_marb_foo_dma2 = 0x00000003,
+ regk_marb_foo_dma3 = 0x00000004,
+ regk_marb_foo_dma4 = 0x00000005,
+ regk_marb_foo_dma5 = 0x00000006,
+ regk_marb_foo_dma6 = 0x00000007,
+ regk_marb_foo_dma7 = 0x00000008,
+ regk_marb_foo_dma9 = 0x00000009,
+ regk_marb_foo_iop = 0x0000000d,
+ regk_marb_foo_no = 0x00000000,
+ regk_marb_foo_r_stopped_default = 0x00000000,
+ regk_marb_foo_rw_ccdstat_burst_default = 0x00000000,
+ regk_marb_foo_rw_cpud_burst_default = 0x00000000,
+ regk_marb_foo_rw_cpui_burst_default = 0x00000000,
+ regk_marb_foo_rw_dma0_burst_default = 0x00000000,
+ regk_marb_foo_rw_dma11_burst_default = 0x00000000,
+ regk_marb_foo_rw_dma1_burst_default = 0x00000000,
+ regk_marb_foo_rw_dma2_burst_default = 0x00000000,
+ regk_marb_foo_rw_dma3_burst_default = 0x00000000,
+ regk_marb_foo_rw_dma4_burst_default = 0x00000000,
+ regk_marb_foo_rw_dma5_burst_default = 0x00000000,
+ regk_marb_foo_rw_dma6_burst_default = 0x00000000,
+ regk_marb_foo_rw_dma7_burst_default = 0x00000000,
+ regk_marb_foo_rw_dma9_burst_default = 0x00000000,
+ regk_marb_foo_rw_intm_slots_default = 0x00000000,
+ regk_marb_foo_rw_intm_slots_size = 0x00000040,
+ regk_marb_foo_rw_intr_mask_default = 0x00000000,
+ regk_marb_foo_rw_iop_burst_default = 0x00000000,
+ regk_marb_foo_rw_l2_slots_default = 0x00000000,
+ regk_marb_foo_rw_l2_slots_size = 0x00000040,
+ regk_marb_foo_rw_no_snoop_default = 0x00000000,
+ regk_marb_foo_rw_no_snoop_rq_default = 0x00000000,
+ regk_marb_foo_rw_regs_slots_default = 0x00000000,
+ regk_marb_foo_rw_regs_slots_size = 0x00000004,
+ regk_marb_foo_rw_sclr_burst_default = 0x00000000,
+ regk_marb_foo_rw_stop_mask_default = 0x00000000,
+ regk_marb_foo_sclr = 0x00000000,
+ regk_marb_foo_yes = 0x00000001
+};
+#endif /* __marb_foo_defs_h */
+#ifndef __marb_foo_bp_defs_h
+#define __marb_foo_bp_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: marb_foo.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile marb_foo_defs.h marb_foo.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope marb_foo_bp */
+
+/* Register rw_first_addr, scope marb_foo_bp, type rw */
+typedef unsigned int reg_marb_foo_bp_rw_first_addr;
+#define REG_RD_ADDR_marb_foo_bp_rw_first_addr 0
+#define REG_WR_ADDR_marb_foo_bp_rw_first_addr 0
+
+/* Register rw_last_addr, scope marb_foo_bp, type rw */
+typedef unsigned int reg_marb_foo_bp_rw_last_addr;
+#define REG_RD_ADDR_marb_foo_bp_rw_last_addr 4
+#define REG_WR_ADDR_marb_foo_bp_rw_last_addr 4
+
+/* Register rw_op, scope marb_foo_bp, type rw */
+typedef struct {
+ unsigned int rd : 1;
+ unsigned int wr : 1;
+ unsigned int rd_excl : 1;
+ unsigned int pri_wr : 1;
+ unsigned int us_rd : 1;
+ unsigned int us_wr : 1;
+ unsigned int us_rd_excl : 1;
+ unsigned int us_pri_wr : 1;
+ unsigned int dummy1 : 24;
+} reg_marb_foo_bp_rw_op;
+#define REG_RD_ADDR_marb_foo_bp_rw_op 8
+#define REG_WR_ADDR_marb_foo_bp_rw_op 8
+
+/* Register rw_clients, scope marb_foo_bp, type rw */
+typedef struct {
+ unsigned int sclr : 1;
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma9 : 1;
+ unsigned int dma11 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int ccdstat : 1;
+ unsigned int dummy1 : 17;
+} reg_marb_foo_bp_rw_clients;
+#define REG_RD_ADDR_marb_foo_bp_rw_clients 12
+#define REG_WR_ADDR_marb_foo_bp_rw_clients 12
+
+/* Register rw_options, scope marb_foo_bp, type rw */
+typedef struct {
+ unsigned int wrap : 1;
+ unsigned int dummy1 : 31;
+} reg_marb_foo_bp_rw_options;
+#define REG_RD_ADDR_marb_foo_bp_rw_options 16
+#define REG_WR_ADDR_marb_foo_bp_rw_options 16
+
+/* Register r_brk_addr, scope marb_foo_bp, type r */
+typedef unsigned int reg_marb_foo_bp_r_brk_addr;
+#define REG_RD_ADDR_marb_foo_bp_r_brk_addr 20
+
+/* Register r_brk_op, scope marb_foo_bp, type r */
+typedef struct {
+ unsigned int rd : 1;
+ unsigned int wr : 1;
+ unsigned int rd_excl : 1;
+ unsigned int pri_wr : 1;
+ unsigned int us_rd : 1;
+ unsigned int us_wr : 1;
+ unsigned int us_rd_excl : 1;
+ unsigned int us_pri_wr : 1;
+ unsigned int dummy1 : 24;
+} reg_marb_foo_bp_r_brk_op;
+#define REG_RD_ADDR_marb_foo_bp_r_brk_op 24
+
+/* Register r_brk_clients, scope marb_foo_bp, type r */
+typedef struct {
+ unsigned int sclr : 1;
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma9 : 1;
+ unsigned int dma11 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int ccdstat : 1;
+ unsigned int dummy1 : 17;
+} reg_marb_foo_bp_r_brk_clients;
+#define REG_RD_ADDR_marb_foo_bp_r_brk_clients 28
+
+/* Register r_brk_first_client, scope marb_foo_bp, type r */
+typedef struct {
+ unsigned int sclr : 1;
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma9 : 1;
+ unsigned int dma11 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int ccdstat : 1;
+ unsigned int dummy1 : 17;
+} reg_marb_foo_bp_r_brk_first_client;
+#define REG_RD_ADDR_marb_foo_bp_r_brk_first_client 32
+
+/* Register r_brk_size, scope marb_foo_bp, type r */
+typedef unsigned int reg_marb_foo_bp_r_brk_size;
+#define REG_RD_ADDR_marb_foo_bp_r_brk_size 36
+
+/* Register rw_ack, scope marb_foo_bp, type rw */
+typedef unsigned int reg_marb_foo_bp_rw_ack;
+#define REG_RD_ADDR_marb_foo_bp_rw_ack 40
+#define REG_WR_ADDR_marb_foo_bp_rw_ack 40
+
+
+/* Constants */
+enum {
+ regk_marb_foo_bp_no = 0x00000000,
+ regk_marb_foo_bp_rw_op_default = 0x00000000,
+ regk_marb_foo_bp_rw_options_default = 0x00000000,
+ regk_marb_foo_bp_yes = 0x00000001
+};
+#endif /* __marb_foo_bp_defs_h */
--- /dev/null
+#ifndef __pinmux_defs_h
+#define __pinmux_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: pinmux.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile pinmux_defs.h pinmux.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope pinmux */
+
+/* Register rw_hwprot, scope pinmux, type rw */
+typedef struct {
+ unsigned int eth : 1;
+ unsigned int eth_mdio : 1;
+ unsigned int geth : 1;
+ unsigned int tg : 1;
+ unsigned int tg_clk : 1;
+ unsigned int vout : 1;
+ unsigned int vout_sync : 1;
+ unsigned int ser1 : 1;
+ unsigned int ser2 : 1;
+ unsigned int ser3 : 1;
+ unsigned int ser4 : 1;
+ unsigned int sser : 1;
+ unsigned int pwm0 : 1;
+ unsigned int pwm1 : 1;
+ unsigned int pwm2 : 1;
+ unsigned int timer0 : 1;
+ unsigned int timer1 : 1;
+ unsigned int pio : 1;
+ unsigned int i2c0 : 1;
+ unsigned int i2c1 : 1;
+ unsigned int i2c1_sda1 : 1;
+ unsigned int i2c1_sda2 : 1;
+ unsigned int i2c1_sda3 : 1;
+ unsigned int i2c1_sen : 1;
+ unsigned int dummy1 : 8;
+} reg_pinmux_rw_hwprot;
+#define REG_RD_ADDR_pinmux_rw_hwprot 0
+#define REG_WR_ADDR_pinmux_rw_hwprot 0
+
+/* Register rw_gio_pa, scope pinmux, type rw */
+typedef struct {
+ unsigned int pa0 : 1;
+ unsigned int pa1 : 1;
+ unsigned int pa2 : 1;
+ unsigned int pa3 : 1;
+ unsigned int pa4 : 1;
+ unsigned int pa5 : 1;
+ unsigned int pa6 : 1;
+ unsigned int pa7 : 1;
+ unsigned int pa8 : 1;
+ unsigned int pa9 : 1;
+ unsigned int pa10 : 1;
+ unsigned int pa11 : 1;
+ unsigned int pa12 : 1;
+ unsigned int pa13 : 1;
+ unsigned int pa14 : 1;
+ unsigned int pa15 : 1;
+ unsigned int pa16 : 1;
+ unsigned int pa17 : 1;
+ unsigned int pa18 : 1;
+ unsigned int pa19 : 1;
+ unsigned int pa20 : 1;
+ unsigned int pa21 : 1;
+ unsigned int pa22 : 1;
+ unsigned int pa23 : 1;
+ unsigned int pa24 : 1;
+ unsigned int pa25 : 1;
+ unsigned int pa26 : 1;
+ unsigned int pa27 : 1;
+ unsigned int pa28 : 1;
+ unsigned int pa29 : 1;
+ unsigned int pa30 : 1;
+ unsigned int pa31 : 1;
+} reg_pinmux_rw_gio_pa;
+#define REG_RD_ADDR_pinmux_rw_gio_pa 4
+#define REG_WR_ADDR_pinmux_rw_gio_pa 4
+
+/* Register rw_gio_pb, scope pinmux, type rw */
+typedef struct {
+ unsigned int pb0 : 1;
+ unsigned int pb1 : 1;
+ unsigned int pb2 : 1;
+ unsigned int pb3 : 1;
+ unsigned int pb4 : 1;
+ unsigned int pb5 : 1;
+ unsigned int pb6 : 1;
+ unsigned int pb7 : 1;
+ unsigned int pb8 : 1;
+ unsigned int pb9 : 1;
+ unsigned int pb10 : 1;
+ unsigned int pb11 : 1;
+ unsigned int pb12 : 1;
+ unsigned int pb13 : 1;
+ unsigned int pb14 : 1;
+ unsigned int pb15 : 1;
+ unsigned int pb16 : 1;
+ unsigned int pb17 : 1;
+ unsigned int pb18 : 1;
+ unsigned int pb19 : 1;
+ unsigned int pb20 : 1;
+ unsigned int pb21 : 1;
+ unsigned int pb22 : 1;
+ unsigned int pb23 : 1;
+ unsigned int pb24 : 1;
+ unsigned int pb25 : 1;
+ unsigned int pb26 : 1;
+ unsigned int pb27 : 1;
+ unsigned int pb28 : 1;
+ unsigned int pb29 : 1;
+ unsigned int pb30 : 1;
+ unsigned int pb31 : 1;
+} reg_pinmux_rw_gio_pb;
+#define REG_RD_ADDR_pinmux_rw_gio_pb 8
+#define REG_WR_ADDR_pinmux_rw_gio_pb 8
+
+/* Register rw_gio_pc, scope pinmux, type rw */
+typedef struct {
+ unsigned int pc0 : 1;
+ unsigned int pc1 : 1;
+ unsigned int pc2 : 1;
+ unsigned int pc3 : 1;
+ unsigned int pc4 : 1;
+ unsigned int pc5 : 1;
+ unsigned int pc6 : 1;
+ unsigned int pc7 : 1;
+ unsigned int pc8 : 1;
+ unsigned int pc9 : 1;
+ unsigned int pc10 : 1;
+ unsigned int pc11 : 1;
+ unsigned int pc12 : 1;
+ unsigned int pc13 : 1;
+ unsigned int pc14 : 1;
+ unsigned int pc15 : 1;
+ unsigned int dummy1 : 16;
+} reg_pinmux_rw_gio_pc;
+#define REG_RD_ADDR_pinmux_rw_gio_pc 12
+#define REG_WR_ADDR_pinmux_rw_gio_pc 12
+
+/* Register rw_iop_pa, scope pinmux, type rw */
+typedef struct {
+ unsigned int pa0 : 1;
+ unsigned int pa1 : 1;
+ unsigned int pa2 : 1;
+ unsigned int pa3 : 1;
+ unsigned int pa4 : 1;
+ unsigned int pa5 : 1;
+ unsigned int pa6 : 1;
+ unsigned int pa7 : 1;
+ unsigned int pa8 : 1;
+ unsigned int pa9 : 1;
+ unsigned int pa10 : 1;
+ unsigned int pa11 : 1;
+ unsigned int pa12 : 1;
+ unsigned int pa13 : 1;
+ unsigned int pa14 : 1;
+ unsigned int pa15 : 1;
+ unsigned int pa16 : 1;
+ unsigned int pa17 : 1;
+ unsigned int pa18 : 1;
+ unsigned int pa19 : 1;
+ unsigned int pa20 : 1;
+ unsigned int pa21 : 1;
+ unsigned int pa22 : 1;
+ unsigned int pa23 : 1;
+ unsigned int pa24 : 1;
+ unsigned int pa25 : 1;
+ unsigned int pa26 : 1;
+ unsigned int pa27 : 1;
+ unsigned int pa28 : 1;
+ unsigned int pa29 : 1;
+ unsigned int pa30 : 1;
+ unsigned int pa31 : 1;
+} reg_pinmux_rw_iop_pa;
+#define REG_RD_ADDR_pinmux_rw_iop_pa 16
+#define REG_WR_ADDR_pinmux_rw_iop_pa 16
+
+/* Register rw_iop_pb, scope pinmux, type rw */
+typedef struct {
+ unsigned int pb0 : 1;
+ unsigned int pb1 : 1;
+ unsigned int pb2 : 1;
+ unsigned int pb3 : 1;
+ unsigned int pb4 : 1;
+ unsigned int pb5 : 1;
+ unsigned int pb6 : 1;
+ unsigned int pb7 : 1;
+ unsigned int dummy1 : 24;
+} reg_pinmux_rw_iop_pb;
+#define REG_RD_ADDR_pinmux_rw_iop_pb 20
+#define REG_WR_ADDR_pinmux_rw_iop_pb 20
+
+/* Register rw_iop_pio, scope pinmux, type rw */
+typedef struct {
+ unsigned int d0 : 1;
+ unsigned int d1 : 1;
+ unsigned int d2 : 1;
+ unsigned int d3 : 1;
+ unsigned int d4 : 1;
+ unsigned int d5 : 1;
+ unsigned int d6 : 1;
+ unsigned int d7 : 1;
+ unsigned int rd_n : 1;
+ unsigned int wr_n : 1;
+ unsigned int a0 : 1;
+ unsigned int a1 : 1;
+ unsigned int ce0_n : 1;
+ unsigned int ce1_n : 1;
+ unsigned int ce2_n : 1;
+ unsigned int rdy : 1;
+ unsigned int dummy1 : 16;
+} reg_pinmux_rw_iop_pio;
+#define REG_RD_ADDR_pinmux_rw_iop_pio 24
+#define REG_WR_ADDR_pinmux_rw_iop_pio 24
+
+/* Register rw_iop_usb, scope pinmux, type rw */
+typedef struct {
+ unsigned int usb0 : 1;
+ unsigned int dummy1 : 31;
+} reg_pinmux_rw_iop_usb;
+#define REG_RD_ADDR_pinmux_rw_iop_usb 28
+#define REG_WR_ADDR_pinmux_rw_iop_usb 28
+
+
+/* Constants */
+enum {
+ regk_pinmux_no = 0x00000000,
+ regk_pinmux_rw_gio_pa_default = 0x00000000,
+ regk_pinmux_rw_gio_pb_default = 0x00000000,
+ regk_pinmux_rw_gio_pc_default = 0x00000000,
+ regk_pinmux_rw_hwprot_default = 0x00000000,
+ regk_pinmux_rw_iop_pa_default = 0x00000000,
+ regk_pinmux_rw_iop_pb_default = 0x00000000,
+ regk_pinmux_rw_iop_pio_default = 0x00000000,
+ regk_pinmux_rw_iop_usb_default = 0x00000001,
+ regk_pinmux_yes = 0x00000001
+};
+#endif /* __pinmux_defs_h */
--- /dev/null
+#ifndef __pio_defs_h
+#define __pio_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: pio.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile pio_defs.h pio.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope pio */
+
+/* Register rw_data, scope pio, type rw */
+typedef unsigned int reg_pio_rw_data;
+#define REG_RD_ADDR_pio_rw_data 64
+#define REG_WR_ADDR_pio_rw_data 64
+
+/* Register rw_io_access0, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access0;
+#define REG_RD_ADDR_pio_rw_io_access0 0
+#define REG_WR_ADDR_pio_rw_io_access0 0
+
+/* Register rw_io_access1, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access1;
+#define REG_RD_ADDR_pio_rw_io_access1 4
+#define REG_WR_ADDR_pio_rw_io_access1 4
+
+/* Register rw_io_access2, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access2;
+#define REG_RD_ADDR_pio_rw_io_access2 8
+#define REG_WR_ADDR_pio_rw_io_access2 8
+
+/* Register rw_io_access3, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access3;
+#define REG_RD_ADDR_pio_rw_io_access3 12
+#define REG_WR_ADDR_pio_rw_io_access3 12
+
+/* Register rw_io_access4, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access4;
+#define REG_RD_ADDR_pio_rw_io_access4 16
+#define REG_WR_ADDR_pio_rw_io_access4 16
+
+/* Register rw_io_access5, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access5;
+#define REG_RD_ADDR_pio_rw_io_access5 20
+#define REG_WR_ADDR_pio_rw_io_access5 20
+
+/* Register rw_io_access6, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access6;
+#define REG_RD_ADDR_pio_rw_io_access6 24
+#define REG_WR_ADDR_pio_rw_io_access6 24
+
+/* Register rw_io_access7, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access7;
+#define REG_RD_ADDR_pio_rw_io_access7 28
+#define REG_WR_ADDR_pio_rw_io_access7 28
+
+/* Register rw_io_access8, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access8;
+#define REG_RD_ADDR_pio_rw_io_access8 32
+#define REG_WR_ADDR_pio_rw_io_access8 32
+
+/* Register rw_io_access9, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access9;
+#define REG_RD_ADDR_pio_rw_io_access9 36
+#define REG_WR_ADDR_pio_rw_io_access9 36
+
+/* Register rw_io_access10, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access10;
+#define REG_RD_ADDR_pio_rw_io_access10 40
+#define REG_WR_ADDR_pio_rw_io_access10 40
+
+/* Register rw_io_access11, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access11;
+#define REG_RD_ADDR_pio_rw_io_access11 44
+#define REG_WR_ADDR_pio_rw_io_access11 44
+
+/* Register rw_io_access12, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access12;
+#define REG_RD_ADDR_pio_rw_io_access12 48
+#define REG_WR_ADDR_pio_rw_io_access12 48
+
+/* Register rw_io_access13, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access13;
+#define REG_RD_ADDR_pio_rw_io_access13 52
+#define REG_WR_ADDR_pio_rw_io_access13 52
+
+/* Register rw_io_access14, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access14;
+#define REG_RD_ADDR_pio_rw_io_access14 56
+#define REG_WR_ADDR_pio_rw_io_access14 56
+
+/* Register rw_io_access15, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_pio_rw_io_access15;
+#define REG_RD_ADDR_pio_rw_io_access15 60
+#define REG_WR_ADDR_pio_rw_io_access15 60
+
+/* Register rw_ce0_cfg, scope pio, type rw */
+typedef struct {
+ unsigned int lw : 6;
+ unsigned int ew : 3;
+ unsigned int zw : 3;
+ unsigned int aw : 2;
+ unsigned int mode : 2;
+ unsigned int dummy1 : 16;
+} reg_pio_rw_ce0_cfg;
+#define REG_RD_ADDR_pio_rw_ce0_cfg 68
+#define REG_WR_ADDR_pio_rw_ce0_cfg 68
+
+/* Register rw_ce1_cfg, scope pio, type rw */
+typedef struct {
+ unsigned int lw : 6;
+ unsigned int ew : 3;
+ unsigned int zw : 3;
+ unsigned int aw : 2;
+ unsigned int mode : 2;
+ unsigned int dummy1 : 16;
+} reg_pio_rw_ce1_cfg;
+#define REG_RD_ADDR_pio_rw_ce1_cfg 72
+#define REG_WR_ADDR_pio_rw_ce1_cfg 72
+
+/* Register rw_ce2_cfg, scope pio, type rw */
+typedef struct {
+ unsigned int lw : 6;
+ unsigned int ew : 3;
+ unsigned int zw : 3;
+ unsigned int aw : 2;
+ unsigned int mode : 2;
+ unsigned int dummy1 : 16;
+} reg_pio_rw_ce2_cfg;
+#define REG_RD_ADDR_pio_rw_ce2_cfg 76
+#define REG_WR_ADDR_pio_rw_ce2_cfg 76
+
+/* Register rw_dout, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int rd_n : 1;
+ unsigned int wr_n : 1;
+ unsigned int a0 : 1;
+ unsigned int a1 : 1;
+ unsigned int ce0_n : 1;
+ unsigned int ce1_n : 1;
+ unsigned int ce2_n : 1;
+ unsigned int rdy : 1;
+ unsigned int dummy1 : 16;
+} reg_pio_rw_dout;
+#define REG_RD_ADDR_pio_rw_dout 80
+#define REG_WR_ADDR_pio_rw_dout 80
+
+/* Register rw_oe, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int rd_n : 1;
+ unsigned int wr_n : 1;
+ unsigned int a0 : 1;
+ unsigned int a1 : 1;
+ unsigned int ce0_n : 1;
+ unsigned int ce1_n : 1;
+ unsigned int ce2_n : 1;
+ unsigned int rdy : 1;
+ unsigned int dummy1 : 16;
+} reg_pio_rw_oe;
+#define REG_RD_ADDR_pio_rw_oe 84
+#define REG_WR_ADDR_pio_rw_oe 84
+
+/* Register rw_man_ctrl, scope pio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int rd_n : 1;
+ unsigned int wr_n : 1;
+ unsigned int a0 : 1;
+ unsigned int a1 : 1;
+ unsigned int ce0_n : 1;
+ unsigned int ce1_n : 1;
+ unsigned int ce2_n : 1;
+ unsigned int rdy : 1;
+ unsigned int dummy1 : 16;
+} reg_pio_rw_man_ctrl;
+#define REG_RD_ADDR_pio_rw_man_ctrl 88
+#define REG_WR_ADDR_pio_rw_man_ctrl 88
+
+/* Register r_din, scope pio, type r */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int rd_n : 1;
+ unsigned int wr_n : 1;
+ unsigned int a0 : 1;
+ unsigned int a1 : 1;
+ unsigned int ce0_n : 1;
+ unsigned int ce1_n : 1;
+ unsigned int ce2_n : 1;
+ unsigned int rdy : 1;
+ unsigned int dummy1 : 16;
+} reg_pio_r_din;
+#define REG_RD_ADDR_pio_r_din 92
+
+/* Register r_stat, scope pio, type r */
+typedef struct {
+ unsigned int busy : 1;
+ unsigned int dummy1 : 31;
+} reg_pio_r_stat;
+#define REG_RD_ADDR_pio_r_stat 96
+
+/* Register rw_intr_mask, scope pio, type rw */
+typedef struct {
+ unsigned int rdy : 1;
+ unsigned int dummy1 : 31;
+} reg_pio_rw_intr_mask;
+#define REG_RD_ADDR_pio_rw_intr_mask 100
+#define REG_WR_ADDR_pio_rw_intr_mask 100
+
+/* Register rw_ack_intr, scope pio, type rw */
+typedef struct {
+ unsigned int rdy : 1;
+ unsigned int dummy1 : 31;
+} reg_pio_rw_ack_intr;
+#define REG_RD_ADDR_pio_rw_ack_intr 104
+#define REG_WR_ADDR_pio_rw_ack_intr 104
+
+/* Register r_intr, scope pio, type r */
+typedef struct {
+ unsigned int rdy : 1;
+ unsigned int dummy1 : 31;
+} reg_pio_r_intr;
+#define REG_RD_ADDR_pio_r_intr 108
+
+/* Register r_masked_intr, scope pio, type r */
+typedef struct {
+ unsigned int rdy : 1;
+ unsigned int dummy1 : 31;
+} reg_pio_r_masked_intr;
+#define REG_RD_ADDR_pio_r_masked_intr 112
+
+
+/* Constants */
+enum {
+ regk_pio_a2 = 0x00000003,
+ regk_pio_no = 0x00000000,
+ regk_pio_normal = 0x00000000,
+ regk_pio_rd = 0x00000001,
+ regk_pio_rw_ce0_cfg_default = 0x00000000,
+ regk_pio_rw_ce1_cfg_default = 0x00000000,
+ regk_pio_rw_ce2_cfg_default = 0x00000000,
+ regk_pio_rw_intr_mask_default = 0x00000000,
+ regk_pio_rw_man_ctrl_default = 0x00000000,
+ regk_pio_rw_oe_default = 0x00000000,
+ regk_pio_wr = 0x00000002,
+ regk_pio_wr_ce2 = 0x00000003,
+ regk_pio_yes = 0x00000001,
+ regk_pio_yes_all = 0x000000ff
+};
+#endif /* __pio_defs_h */
--- /dev/null
+#ifndef __reg_map_h
+#define __reg_map_h
+
+/*
+ * This file is autogenerated from
+ * file: reg.rmap
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -base 0xb0000000 -map marb_bar.r marb_foo.r ccd_top.r ccd_stat.r ccd_tg.r ccd_dp.r ccd.r iop_sap_in.r iop_sap_out.r iop_sw_cfg.r iop_sw_cpu.r iop_sw_mpu.r iop_sw_spu.r iop_version.r iop_crc_par.r iop_dmc_in.r iop_dmc_out.r iop_fifo_in_extra.r iop_fifo_in.r iop_fifo_out_extra.r iop_fifo_out.r iop_mc.r iop_mpu.r iop_scrc_in.r iop_scrc_out.r iop_spu.r iop_timer_grp.r iop_trigger_grp.r iop.r -outfile reg_map.h reg.rmap
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+typedef enum {
+ regi_ccd = 0xb0000000,
+ regi_ccd_top = 0xb0000000,
+ regi_ccd_dp = 0xb0000400,
+ regi_ccd_stat = 0xb0000800,
+ regi_ccd_tg = 0xb0001000,
+ regi_cfg = 0xb0002000,
+ regi_clkgen = 0xb0004000,
+ regi_ddr2_ctrl = 0xb0006000,
+ regi_dma0 = 0xb0008000,
+ regi_dma1 = 0xb000a000,
+ regi_dma11 = 0xb000c000,
+ regi_dma2 = 0xb000e000,
+ regi_dma3 = 0xb0010000,
+ regi_dma4 = 0xb0012000,
+ regi_dma5 = 0xb0014000,
+ regi_dma6 = 0xb0016000,
+ regi_dma7 = 0xb0018000,
+ regi_dma9 = 0xb001a000,
+ regi_eth = 0xb001c000,
+ regi_gio = 0xb0020000,
+ regi_h264 = 0xb0022000,
+ regi_hist = 0xb0026000,
+ regi_iop = 0xb0028000,
+ regi_iop_version = 0xb0028000,
+ regi_iop_fifo_in_extra = 0xb0028040,
+ regi_iop_fifo_out_extra = 0xb0028080,
+ regi_iop_trigger_grp0 = 0xb00280c0,
+ regi_iop_trigger_grp1 = 0xb0028100,
+ regi_iop_trigger_grp2 = 0xb0028140,
+ regi_iop_trigger_grp3 = 0xb0028180,
+ regi_iop_trigger_grp4 = 0xb00281c0,
+ regi_iop_trigger_grp5 = 0xb0028200,
+ regi_iop_trigger_grp6 = 0xb0028240,
+ regi_iop_trigger_grp7 = 0xb0028280,
+ regi_iop_crc_par = 0xb0028300,
+ regi_iop_dmc_in = 0xb0028380,
+ regi_iop_dmc_out = 0xb0028400,
+ regi_iop_fifo_in = 0xb0028480,
+ regi_iop_fifo_out = 0xb0028500,
+ regi_iop_scrc_in = 0xb0028580,
+ regi_iop_scrc_out = 0xb0028600,
+ regi_iop_timer_grp0 = 0xb0028680,
+ regi_iop_timer_grp1 = 0xb0028700,
+ regi_iop_sap_in = 0xb0028800,
+ regi_iop_sap_out = 0xb0028900,
+ regi_iop_spu = 0xb0028a00,
+ regi_iop_sw_cfg = 0xb0028b00,
+ regi_iop_sw_cpu = 0xb0028c00,
+ regi_iop_sw_mpu = 0xb0028d00,
+ regi_iop_sw_spu = 0xb0028e00,
+ regi_iop_mpu = 0xb0029000,
+ regi_irq = 0xb002a000,
+ regi_irq2 = 0xb006a000,
+ regi_jpeg = 0xb002c000,
+ regi_l2cache = 0xb0030000,
+ regi_marb_bar = 0xb0032000,
+ regi_marb_bar_bp0 = 0xb0032140,
+ regi_marb_bar_bp1 = 0xb0032180,
+ regi_marb_bar_bp2 = 0xb00321c0,
+ regi_marb_bar_bp3 = 0xb0032200,
+ regi_marb_foo = 0xb0034000,
+ regi_marb_foo_bp0 = 0xb0034280,
+ regi_marb_foo_bp1 = 0xb00342c0,
+ regi_marb_foo_bp2 = 0xb0034300,
+ regi_marb_foo_bp3 = 0xb0034340,
+ regi_pinmux = 0xb0038000,
+ regi_pio = 0xb0036000,
+ regi_sclr = 0xb003a000,
+ regi_sclr_fifo = 0xb003c000,
+ regi_ser0 = 0xb003e000,
+ regi_ser1 = 0xb0040000,
+ regi_ser2 = 0xb0042000,
+ regi_ser3 = 0xb0044000,
+ regi_ser4 = 0xb0046000,
+ regi_sser = 0xb0048000,
+ regi_strcop = 0xb004a000,
+ regi_strdma0 = 0xb004e000,
+ regi_strdma1 = 0xb0050000,
+ regi_strdma2 = 0xb0052000,
+ regi_strdma3 = 0xb0054000,
+ regi_strdma5 = 0xb0056000,
+ regi_strmux = 0xb004c000,
+ regi_timer0 = 0xb0058000,
+ regi_timer1 = 0xb005a000,
+ regi_timer2 = 0xb006e000,
+ regi_trace = 0xb005c000,
+ regi_vin = 0xb005e000,
+ regi_vout = 0xb0060000
+} reg_scope_instances;
+#endif /* __reg_map_h */
--- /dev/null
+#ifndef __strmux_defs_h
+#define __strmux_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: strmux.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile strmux_defs.h strmux.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope strmux */
+
+/* Register rw_cfg, scope strmux, type rw */
+typedef struct {
+ unsigned int dma0 : 2;
+ unsigned int dma1 : 2;
+ unsigned int dma2 : 2;
+ unsigned int dma3 : 2;
+ unsigned int dma4 : 2;
+ unsigned int dma5 : 2;
+ unsigned int dma6 : 2;
+ unsigned int dma7 : 2;
+ unsigned int dummy1 : 2;
+ unsigned int dma9 : 2;
+ unsigned int dummy2 : 2;
+ unsigned int dma11 : 2;
+ unsigned int dummy3 : 8;
+} reg_strmux_rw_cfg;
+#define REG_RD_ADDR_strmux_rw_cfg 0
+#define REG_WR_ADDR_strmux_rw_cfg 0
+
+
+/* Constants */
+enum {
+ regk_strmux_eth = 0x00000001,
+ regk_strmux_h264 = 0x00000001,
+ regk_strmux_iop = 0x00000001,
+ regk_strmux_jpeg = 0x00000001,
+ regk_strmux_off = 0x00000000,
+ regk_strmux_rw_cfg_default = 0x00000000,
+ regk_strmux_ser0 = 0x00000002,
+ regk_strmux_ser1 = 0x00000002,
+ regk_strmux_ser2 = 0x00000002,
+ regk_strmux_ser3 = 0x00000002,
+ regk_strmux_ser4 = 0x00000002,
+ regk_strmux_sser = 0x00000001,
+ regk_strmux_strcop = 0x00000001
+};
+#endif /* __strmux_defs_h */
--- /dev/null
+#ifndef __timer_defs_h
+#define __timer_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: timer.r
+ *
+ * by ../../../tools/rdesc/bin/rdes2c -outfile timer_defs.h timer.r
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope timer */
+
+/* Register rw_tmr0_div, scope timer, type rw */
+typedef unsigned int reg_timer_rw_tmr0_div;
+#define REG_RD_ADDR_timer_rw_tmr0_div 0
+#define REG_WR_ADDR_timer_rw_tmr0_div 0
+
+/* Register r_tmr0_data, scope timer, type r */
+typedef unsigned int reg_timer_r_tmr0_data;
+#define REG_RD_ADDR_timer_r_tmr0_data 4
+
+/* Register rw_tmr0_ctrl, scope timer, type rw */
+typedef struct {
+ unsigned int op : 2;
+ unsigned int freq : 3;
+ unsigned int dummy1 : 27;
+} reg_timer_rw_tmr0_ctrl;
+#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8
+#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8
+
+/* Register rw_tmr1_div, scope timer, type rw */
+typedef unsigned int reg_timer_rw_tmr1_div;
+#define REG_RD_ADDR_timer_rw_tmr1_div 16
+#define REG_WR_ADDR_timer_rw_tmr1_div 16
+
+/* Register r_tmr1_data, scope timer, type r */
+typedef unsigned int reg_timer_r_tmr1_data;
+#define REG_RD_ADDR_timer_r_tmr1_data 20
+
+/* Register rw_tmr1_ctrl, scope timer, type rw */
+typedef struct {
+ unsigned int op : 2;
+ unsigned int freq : 3;
+ unsigned int dummy1 : 27;
+} reg_timer_rw_tmr1_ctrl;
+#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24
+#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24
+
+/* Register rs_cnt_data, scope timer, type rs */
+typedef struct {
+ unsigned int tmr : 24;
+ unsigned int cnt : 8;
+} reg_timer_rs_cnt_data;
+#define REG_RD_ADDR_timer_rs_cnt_data 32
+
+/* Register r_cnt_data, scope timer, type r */
+typedef struct {
+ unsigned int tmr : 24;
+ unsigned int cnt : 8;
+} reg_timer_r_cnt_data;
+#define REG_RD_ADDR_timer_r_cnt_data 36
+
+/* Register rw_cnt_cfg, scope timer, type rw */
+typedef struct {
+ unsigned int clk : 2;
+ unsigned int dummy1 : 30;
+} reg_timer_rw_cnt_cfg;
+#define REG_RD_ADDR_timer_rw_cnt_cfg 40
+#define REG_WR_ADDR_timer_rw_cnt_cfg 40
+
+/* Register rw_trig, scope timer, type rw */
+typedef unsigned int reg_timer_rw_trig;
+#define REG_RD_ADDR_timer_rw_trig 48
+#define REG_WR_ADDR_timer_rw_trig 48
+
+/* Register rw_trig_cfg, scope timer, type rw */
+typedef struct {
+ unsigned int tmr : 2;
+ unsigned int dummy1 : 30;
+} reg_timer_rw_trig_cfg;
+#define REG_RD_ADDR_timer_rw_trig_cfg 52
+#define REG_WR_ADDR_timer_rw_trig_cfg 52
+
+/* Register r_time, scope timer, type r */
+typedef unsigned int reg_timer_r_time;
+#define REG_RD_ADDR_timer_r_time 56
+
+/* Register rw_out, scope timer, type rw */
+typedef struct {
+ unsigned int tmr : 2;
+ unsigned int dummy1 : 30;
+} reg_timer_rw_out;
+#define REG_RD_ADDR_timer_rw_out 60
+#define REG_WR_ADDR_timer_rw_out 60
+
+/* Register rw_wd_ctrl, scope timer, type rw */
+typedef struct {
+ unsigned int cnt : 8;
+ unsigned int cmd : 1;
+ unsigned int key : 7;
+ unsigned int dummy1 : 16;
+} reg_timer_rw_wd_ctrl;
+#define REG_RD_ADDR_timer_rw_wd_ctrl 64
+#define REG_WR_ADDR_timer_rw_wd_ctrl 64
+
+/* Register r_wd_stat, scope timer, type r */
+typedef struct {
+ unsigned int cnt : 8;
+ unsigned int cmd : 1;
+ unsigned int dummy1 : 23;
+} reg_timer_r_wd_stat;
+#define REG_RD_ADDR_timer_r_wd_stat 68
+
+/* Register rw_intr_mask, scope timer, type rw */
+typedef struct {
+ unsigned int tmr0 : 1;
+ unsigned int tmr1 : 1;
+ unsigned int cnt : 1;
+ unsigned int trig : 1;
+ unsigned int dummy1 : 28;
+} reg_timer_rw_intr_mask;
+#define REG_RD_ADDR_timer_rw_intr_mask 72
+#define REG_WR_ADDR_timer_rw_intr_mask 72
+
+/* Register rw_ack_intr, scope timer, type rw */
+typedef struct {
+ unsigned int tmr0 : 1;
+ unsigned int tmr1 : 1;
+ unsigned int cnt : 1;
+ unsigned int trig : 1;
+ unsigned int dummy1 : 28;
+} reg_timer_rw_ack_intr;
+#define REG_RD_ADDR_timer_rw_ack_intr 76
+#define REG_WR_ADDR_timer_rw_ack_intr 76
+
+/* Register r_intr, scope timer, type r */
+typedef struct {
+ unsigned int tmr0 : 1;
+ unsigned int tmr1 : 1;
+ unsigned int cnt : 1;
+ unsigned int trig : 1;
+ unsigned int dummy1 : 28;
+} reg_timer_r_intr;
+#define REG_RD_ADDR_timer_r_intr 80
+
+/* Register r_masked_intr, scope timer, type r */
+typedef struct {
+ unsigned int tmr0 : 1;
+ unsigned int tmr1 : 1;
+ unsigned int cnt : 1;
+ unsigned int trig : 1;
+ unsigned int dummy1 : 28;
+} reg_timer_r_masked_intr;
+#define REG_RD_ADDR_timer_r_masked_intr 84
+
+/* Register rw_test, scope timer, type rw */
+typedef struct {
+ unsigned int dis : 1;
+ unsigned int en : 1;
+ unsigned int dummy1 : 30;
+} reg_timer_rw_test;
+#define REG_RD_ADDR_timer_rw_test 88
+#define REG_WR_ADDR_timer_rw_test 88
+
+
+/* Constants */
+enum {
+ regk_timer_ext = 0x00000001,
+ regk_timer_f100 = 0x00000007,
+ regk_timer_f29_493 = 0x00000004,
+ regk_timer_f32 = 0x00000005,
+ regk_timer_f32_768 = 0x00000006,
+ regk_timer_f90 = 0x00000003,
+ regk_timer_hold = 0x00000001,
+ regk_timer_ld = 0x00000000,
+ regk_timer_no = 0x00000000,
+ regk_timer_off = 0x00000000,
+ regk_timer_run = 0x00000002,
+ regk_timer_rw_cnt_cfg_default = 0x00000000,
+ regk_timer_rw_intr_mask_default = 0x00000000,
+ regk_timer_rw_out_default = 0x00000000,
+ regk_timer_rw_test_default = 0x00000000,
+ regk_timer_rw_tmr0_ctrl_default = 0x00000000,
+ regk_timer_rw_tmr1_ctrl_default = 0x00000000,
+ regk_timer_rw_trig_cfg_default = 0x00000000,
+ regk_timer_start = 0x00000001,
+ regk_timer_stop = 0x00000000,
+ regk_timer_time = 0x00000001,
+ regk_timer_tmr0 = 0x00000002,
+ regk_timer_tmr1 = 0x00000003,
+ regk_timer_vclk = 0x00000002,
+ regk_timer_yes = 0x00000001
+};
+#endif /* __timer_defs_h */
--- /dev/null
+#ifndef _ASM_ARCH_MEMMAP_H
+#define _ASM_ARCH_MEMMAP_H
+
+#define MEM_INTMEM_START (0x38000000)
+#define MEM_INTMEM_SIZE (0x00018000)
+#define MEM_DRAM_START (0x40000000)
+
+#define MEM_NON_CACHEABLE (0x80000000)
+
+#endif
--- /dev/null
+#ifndef _ASM_CRIS_ARCH_PINMUX_H
+#define _ASM_CRIS_ARCH_PINMUX_H
+
+#define PORT_A 0
+#define PORT_B 1
+#define PORT_C 2
+
+enum pin_mode {
+ pinmux_none = 0,
+ pinmux_fixed,
+ pinmux_gpio,
+ pinmux_iop
+};
+
+enum fixed_function {
+ pinmux_eth,
+ pinmux_geth,
+ pinmux_tg_ccd,
+ pinmux_tg_cmos,
+ pinmux_vout,
+ pinmux_ser1,
+ pinmux_ser2,
+ pinmux_ser3,
+ pinmux_ser4,
+ pinmux_sser,
+ pinmux_pio,
+ pinmux_pwm0,
+ pinmux_pwm1,
+ pinmux_pwm2,
+ pinmux_i2c0,
+ pinmux_i2c1,
+ pinmux_i2c1_3wire,
+ pinmux_i2c1_sda1,
+ pinmux_i2c1_sda2,
+ pinmux_i2c1_sda3,
+};
+
+int crisv32_pinmux_init(void);
+int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
+int crisv32_pinmux_alloc_fixed(enum fixed_function function);
+int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
+int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
+void crisv32_pinmux_dump(void);
+
+#endif
--- /dev/null
+#include <hwregs/asm/reg_map_asm.h>
+#include <hwregs/asm/gio_defs_asm.h>
+#include <hwregs/asm/pio_defs_asm.h>
+#include <hwregs/asm/clkgen_defs_asm.h>
+#include <hwregs/asm/pinmux_defs_asm.h>
+
+ .macro GIO_INIT
+ move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
+ move.d $r0, [$r1]
+
+ move.d 0xFFFFFFFF, $r0
+ move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pa), $r1
+ move.d $r0, [$r1]
+ move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pb), $r1
+ move.d $r0, [$r1]
+ move.d REG_ADDR(pinmux, regi_pinmux, rw_gio_pc), $r1
+ move.d $r0, [$r1]
+ .endm
+
+ .macro START_CLOCKS
+ move.d REG_ADDR(clkgen, regi_clkgen, rw_clk_ctrl), $r1
+ move.d [$r1], $r0
+ or.d REG_STATE(clkgen, rw_clk_ctrl, cpu, yes) | \
+ REG_STATE(clkgen, rw_clk_ctrl, ddr2, yes) | \
+ REG_STATE(clkgen, rw_clk_ctrl, memarb_bar_ddr, yes), $r0
+ move.d $r0, [$r1]
+ .endm
+
+ .macro SETUP_WAIT_STATES
+ move.d REG_ADDR(pio, regi_pio, rw_ce0_cfg), $r0
+ move.d CONFIG_ETRAX_PIO_CE0_CFG, $r1
+ move.d $r1, [$r0]
+ move.d REG_ADDR(pio, regi_pio, rw_ce1_cfg), $r0
+ move.d CONFIG_ETRAX_PIO_CE1_CFG, $r1
+ move.d $r1, [$r0]
+ move.d REG_ADDR(pio, regi_pio, rw_ce2_cfg), $r0
+ move.d CONFIG_ETRAX_PIO_CE2_CFG, $r1
+ move.d $r1, [$r0]
+ .endm
--- /dev/null
+#ifndef _ASM_CRIS_ARCH_ARBITER_H
+#define _ASM_CRIS_ARCH_ARBITER_H
+
+#define EXT_REGION 0
+#define INT_REGION 1
+
+typedef void (watch_callback)(void);
+
+enum {
+ arbiter_all_dmas = 0x3ff,
+ arbiter_cpu = 0xc00,
+ arbiter_all_clients = 0x3fff
+};
+
+enum {
+ arbiter_all_read = 0x55,
+ arbiter_all_write = 0xaa,
+ arbiter_all_accesses = 0xff
+};
+
+int crisv32_arbiter_allocate_bandwidth(int client, int region,
+ unsigned long bandwidth);
+int crisv32_arbiter_watch(unsigned long start, unsigned long size,
+ unsigned long clients, unsigned long accesses,
+ watch_callback * cb);
+int crisv32_arbiter_unwatch(int id);
+
+#endif
--- /dev/null
+#ifndef __bif_core_defs_asm_h
+#define __bif_core_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/bif/rtl/bif_core_regs.r
+ * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
+ * last modfied: Mon Apr 11 16:06:33 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r
+ * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_grp1_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp1_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp1_cfg___lw___width 6
+#define reg_bif_core_rw_grp1_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp1_cfg___ew___width 3
+#define reg_bif_core_rw_grp1_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp1_cfg___zw___width 3
+#define reg_bif_core_rw_grp1_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp1_cfg___aw___width 2
+#define reg_bif_core_rw_grp1_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp1_cfg___dw___width 2
+#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp1_cfg___ewb___width 2
+#define reg_bif_core_rw_grp1_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp1_cfg___bw___width 1
+#define reg_bif_core_rw_grp1_cfg___bw___bit 18
+#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp1_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp1_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp1_cfg___mode___width 1
+#define reg_bif_core_rw_grp1_cfg___mode___bit 21
+#define reg_bif_core_rw_grp1_cfg_offset 0
+
+/* Register rw_grp2_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp2_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp2_cfg___lw___width 6
+#define reg_bif_core_rw_grp2_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp2_cfg___ew___width 3
+#define reg_bif_core_rw_grp2_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp2_cfg___zw___width 3
+#define reg_bif_core_rw_grp2_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp2_cfg___aw___width 2
+#define reg_bif_core_rw_grp2_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp2_cfg___dw___width 2
+#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp2_cfg___ewb___width 2
+#define reg_bif_core_rw_grp2_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp2_cfg___bw___width 1
+#define reg_bif_core_rw_grp2_cfg___bw___bit 18
+#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp2_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp2_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp2_cfg___mode___width 1
+#define reg_bif_core_rw_grp2_cfg___mode___bit 21
+#define reg_bif_core_rw_grp2_cfg_offset 4
+
+/* Register rw_grp3_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp3_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp3_cfg___lw___width 6
+#define reg_bif_core_rw_grp3_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp3_cfg___ew___width 3
+#define reg_bif_core_rw_grp3_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp3_cfg___zw___width 3
+#define reg_bif_core_rw_grp3_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp3_cfg___aw___width 2
+#define reg_bif_core_rw_grp3_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp3_cfg___dw___width 2
+#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp3_cfg___ewb___width 2
+#define reg_bif_core_rw_grp3_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp3_cfg___bw___width 1
+#define reg_bif_core_rw_grp3_cfg___bw___bit 18
+#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp3_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp3_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp3_cfg___mode___width 1
+#define reg_bif_core_rw_grp3_cfg___mode___bit 21
+#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24
+#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2
+#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26
+#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2
+#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28
+#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2
+#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30
+#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2
+#define reg_bif_core_rw_grp3_cfg_offset 8
+
+/* Register rw_grp4_cfg, scope bif_core, type rw */
+#define reg_bif_core_rw_grp4_cfg___lw___lsb 0
+#define reg_bif_core_rw_grp4_cfg___lw___width 6
+#define reg_bif_core_rw_grp4_cfg___ew___lsb 6
+#define reg_bif_core_rw_grp4_cfg___ew___width 3
+#define reg_bif_core_rw_grp4_cfg___zw___lsb 9
+#define reg_bif_core_rw_grp4_cfg___zw___width 3
+#define reg_bif_core_rw_grp4_cfg___aw___lsb 12
+#define reg_bif_core_rw_grp4_cfg___aw___width 2
+#define reg_bif_core_rw_grp4_cfg___dw___lsb 14
+#define reg_bif_core_rw_grp4_cfg___dw___width 2
+#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16
+#define reg_bif_core_rw_grp4_cfg___ewb___width 2
+#define reg_bif_core_rw_grp4_cfg___bw___lsb 18
+#define reg_bif_core_rw_grp4_cfg___bw___width 1
+#define reg_bif_core_rw_grp4_cfg___bw___bit 18
+#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19
+#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1
+#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19
+#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20
+#define reg_bif_core_rw_grp4_cfg___erc_en___width 1
+#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20
+#define reg_bif_core_rw_grp4_cfg___mode___lsb 21
+#define reg_bif_core_rw_grp4_cfg___mode___width 1
+#define reg_bif_core_rw_grp4_cfg___mode___bit 21
+#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26
+#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2
+#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28
+#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2
+#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30
+#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2
+#define reg_bif_core_rw_grp4_cfg_offset 12
+
+/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0
+#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5
+#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5
+#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3
+#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8
+#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8
+#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9
+#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9
+#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10
+#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3
+#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13
+#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13
+#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14
+#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1
+#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14
+#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15
+#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5
+#define reg_bif_core_rw_sdram_cfg_grp0_offset 16
+
+/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0
+#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5
+#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5
+#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3
+#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8
+#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8
+#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9
+#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9
+#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10
+#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3
+#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13
+#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13
+#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14
+#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1
+#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14
+#define reg_bif_core_rw_sdram_cfg_grp1_offset 20
+
+/* Register rw_sdram_timing, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_timing___cl___lsb 0
+#define reg_bif_core_rw_sdram_timing___cl___width 3
+#define reg_bif_core_rw_sdram_timing___rcd___lsb 3
+#define reg_bif_core_rw_sdram_timing___rcd___width 3
+#define reg_bif_core_rw_sdram_timing___rp___lsb 6
+#define reg_bif_core_rw_sdram_timing___rp___width 3
+#define reg_bif_core_rw_sdram_timing___rc___lsb 9
+#define reg_bif_core_rw_sdram_timing___rc___width 2
+#define reg_bif_core_rw_sdram_timing___dpl___lsb 11
+#define reg_bif_core_rw_sdram_timing___dpl___width 2
+#define reg_bif_core_rw_sdram_timing___pde___lsb 13
+#define reg_bif_core_rw_sdram_timing___pde___width 1
+#define reg_bif_core_rw_sdram_timing___pde___bit 13
+#define reg_bif_core_rw_sdram_timing___ref___lsb 14
+#define reg_bif_core_rw_sdram_timing___ref___width 2
+#define reg_bif_core_rw_sdram_timing___cpd___lsb 16
+#define reg_bif_core_rw_sdram_timing___cpd___width 1
+#define reg_bif_core_rw_sdram_timing___cpd___bit 16
+#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17
+#define reg_bif_core_rw_sdram_timing___sdcke___width 1
+#define reg_bif_core_rw_sdram_timing___sdcke___bit 17
+#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18
+#define reg_bif_core_rw_sdram_timing___sdclk___width 1
+#define reg_bif_core_rw_sdram_timing___sdclk___bit 18
+#define reg_bif_core_rw_sdram_timing_offset 24
+
+/* Register rw_sdram_cmd, scope bif_core, type rw */
+#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0
+#define reg_bif_core_rw_sdram_cmd___cmd___width 3
+#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3
+#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15
+#define reg_bif_core_rw_sdram_cmd_offset 28
+
+/* Register rs_sdram_ref_stat, scope bif_core, type rs */
+#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0
+#define reg_bif_core_rs_sdram_ref_stat___ok___width 1
+#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0
+#define reg_bif_core_rs_sdram_ref_stat_offset 32
+
+/* Register r_sdram_ref_stat, scope bif_core, type r */
+#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0
+#define reg_bif_core_r_sdram_ref_stat___ok___width 1
+#define reg_bif_core_r_sdram_ref_stat___ok___bit 0
+#define reg_bif_core_r_sdram_ref_stat_offset 36
+
+
+/* Constants */
+#define regk_bif_core_bank2 0x00000000
+#define regk_bif_core_bank4 0x00000001
+#define regk_bif_core_bit10 0x0000000a
+#define regk_bif_core_bit11 0x0000000b
+#define regk_bif_core_bit12 0x0000000c
+#define regk_bif_core_bit13 0x0000000d
+#define regk_bif_core_bit14 0x0000000e
+#define regk_bif_core_bit15 0x0000000f
+#define regk_bif_core_bit16 0x00000010
+#define regk_bif_core_bit17 0x00000011
+#define regk_bif_core_bit18 0x00000012
+#define regk_bif_core_bit19 0x00000013
+#define regk_bif_core_bit20 0x00000014
+#define regk_bif_core_bit21 0x00000015
+#define regk_bif_core_bit22 0x00000016
+#define regk_bif_core_bit23 0x00000017
+#define regk_bif_core_bit24 0x00000018
+#define regk_bif_core_bit25 0x00000019
+#define regk_bif_core_bit26 0x0000001a
+#define regk_bif_core_bit27 0x0000001b
+#define regk_bif_core_bit28 0x0000001c
+#define regk_bif_core_bit29 0x0000001d
+#define regk_bif_core_bit9 0x00000009
+#define regk_bif_core_bw16 0x00000001
+#define regk_bif_core_bw32 0x00000000
+#define regk_bif_core_bwe 0x00000000
+#define regk_bif_core_cwe 0x00000001
+#define regk_bif_core_e15us 0x00000001
+#define regk_bif_core_e7800ns 0x00000002
+#define regk_bif_core_grp0 0x00000000
+#define regk_bif_core_grp1 0x00000001
+#define regk_bif_core_mrs 0x00000003
+#define regk_bif_core_no 0x00000000
+#define regk_bif_core_none 0x00000000
+#define regk_bif_core_nop 0x00000000
+#define regk_bif_core_off 0x00000000
+#define regk_bif_core_pre 0x00000002
+#define regk_bif_core_r_sdram_ref_stat_default 0x00000001
+#define regk_bif_core_rd 0x00000002
+#define regk_bif_core_ref 0x00000001
+#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001
+#define regk_bif_core_rw_grp1_cfg_default 0x000006cf
+#define regk_bif_core_rw_grp2_cfg_default 0x000006cf
+#define regk_bif_core_rw_grp3_cfg_default 0x000006cf
+#define regk_bif_core_rw_grp4_cfg_default 0x000006cf
+#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000
+#define regk_bif_core_slf 0x00000004
+#define regk_bif_core_wr 0x00000001
+#define regk_bif_core_yes 0x00000001
+#endif /* __bif_core_defs_asm_h */
--- /dev/null
+#ifndef __config_defs_asm_h
+#define __config_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../rtl/config_regs.r
+ * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
+ * last modfied: Thu Mar 4 12:34:39 2004
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r
+ * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register r_bootsel, scope config, type r */
+#define reg_config_r_bootsel___boot_mode___lsb 0
+#define reg_config_r_bootsel___boot_mode___width 3
+#define reg_config_r_bootsel___full_duplex___lsb 3
+#define reg_config_r_bootsel___full_duplex___width 1
+#define reg_config_r_bootsel___full_duplex___bit 3
+#define reg_config_r_bootsel___user___lsb 4
+#define reg_config_r_bootsel___user___width 1
+#define reg_config_r_bootsel___user___bit 4
+#define reg_config_r_bootsel___pll___lsb 5
+#define reg_config_r_bootsel___pll___width 1
+#define reg_config_r_bootsel___pll___bit 5
+#define reg_config_r_bootsel___flash_bw___lsb 6
+#define reg_config_r_bootsel___flash_bw___width 1
+#define reg_config_r_bootsel___flash_bw___bit 6
+#define reg_config_r_bootsel_offset 0
+
+/* Register rw_clk_ctrl, scope config, type rw */
+#define reg_config_rw_clk_ctrl___pll___lsb 0
+#define reg_config_rw_clk_ctrl___pll___width 1
+#define reg_config_rw_clk_ctrl___pll___bit 0
+#define reg_config_rw_clk_ctrl___cpu___lsb 1
+#define reg_config_rw_clk_ctrl___cpu___width 1
+#define reg_config_rw_clk_ctrl___cpu___bit 1
+#define reg_config_rw_clk_ctrl___iop___lsb 2
+#define reg_config_rw_clk_ctrl___iop___width 1
+#define reg_config_rw_clk_ctrl___iop___bit 2
+#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3
+#define reg_config_rw_clk_ctrl___dma01_eth0___width 1
+#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3
+#define reg_config_rw_clk_ctrl___dma23___lsb 4
+#define reg_config_rw_clk_ctrl___dma23___width 1
+#define reg_config_rw_clk_ctrl___dma23___bit 4
+#define reg_config_rw_clk_ctrl___dma45___lsb 5
+#define reg_config_rw_clk_ctrl___dma45___width 1
+#define reg_config_rw_clk_ctrl___dma45___bit 5
+#define reg_config_rw_clk_ctrl___dma67___lsb 6
+#define reg_config_rw_clk_ctrl___dma67___width 1
+#define reg_config_rw_clk_ctrl___dma67___bit 6
+#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7
+#define reg_config_rw_clk_ctrl___dma89_strcop___width 1
+#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7
+#define reg_config_rw_clk_ctrl___bif___lsb 8
+#define reg_config_rw_clk_ctrl___bif___width 1
+#define reg_config_rw_clk_ctrl___bif___bit 8
+#define reg_config_rw_clk_ctrl___fix_io___lsb 9
+#define reg_config_rw_clk_ctrl___fix_io___width 1
+#define reg_config_rw_clk_ctrl___fix_io___bit 9
+#define reg_config_rw_clk_ctrl_offset 4
+
+/* Register rw_pad_ctrl, scope config, type rw */
+#define reg_config_rw_pad_ctrl___usb_susp___lsb 0
+#define reg_config_rw_pad_ctrl___usb_susp___width 1
+#define reg_config_rw_pad_ctrl___usb_susp___bit 0
+#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1
+#define reg_config_rw_pad_ctrl___phyrst_n___width 1
+#define reg_config_rw_pad_ctrl___phyrst_n___bit 1
+#define reg_config_rw_pad_ctrl_offset 8
+
+
+/* Constants */
+#define regk_config_bw16 0x00000000
+#define regk_config_bw32 0x00000001
+#define regk_config_master 0x00000005
+#define regk_config_nand 0x00000003
+#define regk_config_net_rx 0x00000001
+#define regk_config_net_tx_rx 0x00000002
+#define regk_config_no 0x00000000
+#define regk_config_none 0x00000007
+#define regk_config_nor 0x00000000
+#define regk_config_rw_clk_ctrl_default 0x00000002
+#define regk_config_rw_pad_ctrl_default 0x00000000
+#define regk_config_ser 0x00000004
+#define regk_config_slave 0x00000006
+#define regk_config_yes 0x00000001
+#endif /* __config_defs_asm_h */
--- /dev/null
+#ifndef __gio_defs_asm_h
+#define __gio_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/gio/rtl/gio_regs.r
+ * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
+ * last modfied: Mon Apr 11 16:07:47 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r
+ * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_pa_dout, scope gio, type rw */
+#define reg_gio_rw_pa_dout___data___lsb 0
+#define reg_gio_rw_pa_dout___data___width 8
+#define reg_gio_rw_pa_dout_offset 0
+
+/* Register r_pa_din, scope gio, type r */
+#define reg_gio_r_pa_din___data___lsb 0
+#define reg_gio_r_pa_din___data___width 8
+#define reg_gio_r_pa_din_offset 4
+
+/* Register rw_pa_oe, scope gio, type rw */
+#define reg_gio_rw_pa_oe___oe___lsb 0
+#define reg_gio_rw_pa_oe___oe___width 8
+#define reg_gio_rw_pa_oe_offset 8
+
+/* Register rw_intr_cfg, scope gio, type rw */
+#define reg_gio_rw_intr_cfg___pa0___lsb 0
+#define reg_gio_rw_intr_cfg___pa0___width 3
+#define reg_gio_rw_intr_cfg___pa1___lsb 3
+#define reg_gio_rw_intr_cfg___pa1___width 3
+#define reg_gio_rw_intr_cfg___pa2___lsb 6
+#define reg_gio_rw_intr_cfg___pa2___width 3
+#define reg_gio_rw_intr_cfg___pa3___lsb 9
+#define reg_gio_rw_intr_cfg___pa3___width 3
+#define reg_gio_rw_intr_cfg___pa4___lsb 12
+#define reg_gio_rw_intr_cfg___pa4___width 3
+#define reg_gio_rw_intr_cfg___pa5___lsb 15
+#define reg_gio_rw_intr_cfg___pa5___width 3
+#define reg_gio_rw_intr_cfg___pa6___lsb 18
+#define reg_gio_rw_intr_cfg___pa6___width 3
+#define reg_gio_rw_intr_cfg___pa7___lsb 21
+#define reg_gio_rw_intr_cfg___pa7___width 3
+#define reg_gio_rw_intr_cfg_offset 12
+
+/* Register rw_intr_mask, scope gio, type rw */
+#define reg_gio_rw_intr_mask___pa0___lsb 0
+#define reg_gio_rw_intr_mask___pa0___width 1
+#define reg_gio_rw_intr_mask___pa0___bit 0
+#define reg_gio_rw_intr_mask___pa1___lsb 1
+#define reg_gio_rw_intr_mask___pa1___width 1
+#define reg_gio_rw_intr_mask___pa1___bit 1
+#define reg_gio_rw_intr_mask___pa2___lsb 2
+#define reg_gio_rw_intr_mask___pa2___width 1
+#define reg_gio_rw_intr_mask___pa2___bit 2
+#define reg_gio_rw_intr_mask___pa3___lsb 3
+#define reg_gio_rw_intr_mask___pa3___width 1
+#define reg_gio_rw_intr_mask___pa3___bit 3
+#define reg_gio_rw_intr_mask___pa4___lsb 4
+#define reg_gio_rw_intr_mask___pa4___width 1
+#define reg_gio_rw_intr_mask___pa4___bit 4
+#define reg_gio_rw_intr_mask___pa5___lsb 5
+#define reg_gio_rw_intr_mask___pa5___width 1
+#define reg_gio_rw_intr_mask___pa5___bit 5
+#define reg_gio_rw_intr_mask___pa6___lsb 6
+#define reg_gio_rw_intr_mask___pa6___width 1
+#define reg_gio_rw_intr_mask___pa6___bit 6
+#define reg_gio_rw_intr_mask___pa7___lsb 7
+#define reg_gio_rw_intr_mask___pa7___width 1
+#define reg_gio_rw_intr_mask___pa7___bit 7
+#define reg_gio_rw_intr_mask_offset 16
+
+/* Register rw_ack_intr, scope gio, type rw */
+#define reg_gio_rw_ack_intr___pa0___lsb 0
+#define reg_gio_rw_ack_intr___pa0___width 1
+#define reg_gio_rw_ack_intr___pa0___bit 0
+#define reg_gio_rw_ack_intr___pa1___lsb 1
+#define reg_gio_rw_ack_intr___pa1___width 1
+#define reg_gio_rw_ack_intr___pa1___bit 1
+#define reg_gio_rw_ack_intr___pa2___lsb 2
+#define reg_gio_rw_ack_intr___pa2___width 1
+#define reg_gio_rw_ack_intr___pa2___bit 2
+#define reg_gio_rw_ack_intr___pa3___lsb 3
+#define reg_gio_rw_ack_intr___pa3___width 1
+#define reg_gio_rw_ack_intr___pa3___bit 3
+#define reg_gio_rw_ack_intr___pa4___lsb 4
+#define reg_gio_rw_ack_intr___pa4___width 1
+#define reg_gio_rw_ack_intr___pa4___bit 4
+#define reg_gio_rw_ack_intr___pa5___lsb 5
+#define reg_gio_rw_ack_intr___pa5___width 1
+#define reg_gio_rw_ack_intr___pa5___bit 5
+#define reg_gio_rw_ack_intr___pa6___lsb 6
+#define reg_gio_rw_ack_intr___pa6___width 1
+#define reg_gio_rw_ack_intr___pa6___bit 6
+#define reg_gio_rw_ack_intr___pa7___lsb 7
+#define reg_gio_rw_ack_intr___pa7___width 1
+#define reg_gio_rw_ack_intr___pa7___bit 7
+#define reg_gio_rw_ack_intr_offset 20
+
+/* Register r_intr, scope gio, type r */
+#define reg_gio_r_intr___pa0___lsb 0
+#define reg_gio_r_intr___pa0___width 1
+#define reg_gio_r_intr___pa0___bit 0
+#define reg_gio_r_intr___pa1___lsb 1
+#define reg_gio_r_intr___pa1___width 1
+#define reg_gio_r_intr___pa1___bit 1
+#define reg_gio_r_intr___pa2___lsb 2
+#define reg_gio_r_intr___pa2___width 1
+#define reg_gio_r_intr___pa2___bit 2
+#define reg_gio_r_intr___pa3___lsb 3
+#define reg_gio_r_intr___pa3___width 1
+#define reg_gio_r_intr___pa3___bit 3
+#define reg_gio_r_intr___pa4___lsb 4
+#define reg_gio_r_intr___pa4___width 1
+#define reg_gio_r_intr___pa4___bit 4
+#define reg_gio_r_intr___pa5___lsb 5
+#define reg_gio_r_intr___pa5___width 1
+#define reg_gio_r_intr___pa5___bit 5
+#define reg_gio_r_intr___pa6___lsb 6
+#define reg_gio_r_intr___pa6___width 1
+#define reg_gio_r_intr___pa6___bit 6
+#define reg_gio_r_intr___pa7___lsb 7
+#define reg_gio_r_intr___pa7___width 1
+#define reg_gio_r_intr___pa7___bit 7
+#define reg_gio_r_intr_offset 24
+
+/* Register r_masked_intr, scope gio, type r */
+#define reg_gio_r_masked_intr___pa0___lsb 0
+#define reg_gio_r_masked_intr___pa0___width 1
+#define reg_gio_r_masked_intr___pa0___bit 0
+#define reg_gio_r_masked_intr___pa1___lsb 1
+#define reg_gio_r_masked_intr___pa1___width 1
+#define reg_gio_r_masked_intr___pa1___bit 1
+#define reg_gio_r_masked_intr___pa2___lsb 2
+#define reg_gio_r_masked_intr___pa2___width 1
+#define reg_gio_r_masked_intr___pa2___bit 2
+#define reg_gio_r_masked_intr___pa3___lsb 3
+#define reg_gio_r_masked_intr___pa3___width 1
+#define reg_gio_r_masked_intr___pa3___bit 3
+#define reg_gio_r_masked_intr___pa4___lsb 4
+#define reg_gio_r_masked_intr___pa4___width 1
+#define reg_gio_r_masked_intr___pa4___bit 4
+#define reg_gio_r_masked_intr___pa5___lsb 5
+#define reg_gio_r_masked_intr___pa5___width 1
+#define reg_gio_r_masked_intr___pa5___bit 5
+#define reg_gio_r_masked_intr___pa6___lsb 6
+#define reg_gio_r_masked_intr___pa6___width 1
+#define reg_gio_r_masked_intr___pa6___bit 6
+#define reg_gio_r_masked_intr___pa7___lsb 7
+#define reg_gio_r_masked_intr___pa7___width 1
+#define reg_gio_r_masked_intr___pa7___bit 7
+#define reg_gio_r_masked_intr_offset 28
+
+/* Register rw_pb_dout, scope gio, type rw */
+#define reg_gio_rw_pb_dout___data___lsb 0
+#define reg_gio_rw_pb_dout___data___width 18
+#define reg_gio_rw_pb_dout_offset 32
+
+/* Register r_pb_din, scope gio, type r */
+#define reg_gio_r_pb_din___data___lsb 0
+#define reg_gio_r_pb_din___data___width 18
+#define reg_gio_r_pb_din_offset 36
+
+/* Register rw_pb_oe, scope gio, type rw */
+#define reg_gio_rw_pb_oe___oe___lsb 0
+#define reg_gio_rw_pb_oe___oe___width 18
+#define reg_gio_rw_pb_oe_offset 40
+
+/* Register rw_pc_dout, scope gio, type rw */
+#define reg_gio_rw_pc_dout___data___lsb 0
+#define reg_gio_rw_pc_dout___data___width 18
+#define reg_gio_rw_pc_dout_offset 48
+
+/* Register r_pc_din, scope gio, type r */
+#define reg_gio_r_pc_din___data___lsb 0
+#define reg_gio_r_pc_din___data___width 18
+#define reg_gio_r_pc_din_offset 52
+
+/* Register rw_pc_oe, scope gio, type rw */
+#define reg_gio_rw_pc_oe___oe___lsb 0
+#define reg_gio_rw_pc_oe___oe___width 18
+#define reg_gio_rw_pc_oe_offset 56
+
+/* Register rw_pd_dout, scope gio, type rw */
+#define reg_gio_rw_pd_dout___data___lsb 0
+#define reg_gio_rw_pd_dout___data___width 18
+#define reg_gio_rw_pd_dout_offset 64
+
+/* Register r_pd_din, scope gio, type r */
+#define reg_gio_r_pd_din___data___lsb 0
+#define reg_gio_r_pd_din___data___width 18
+#define reg_gio_r_pd_din_offset 68
+
+/* Register rw_pd_oe, scope gio, type rw */
+#define reg_gio_rw_pd_oe___oe___lsb 0
+#define reg_gio_rw_pd_oe___oe___width 18
+#define reg_gio_rw_pd_oe_offset 72
+
+/* Register rw_pe_dout, scope gio, type rw */
+#define reg_gio_rw_pe_dout___data___lsb 0
+#define reg_gio_rw_pe_dout___data___width 18
+#define reg_gio_rw_pe_dout_offset 80
+
+/* Register r_pe_din, scope gio, type r */
+#define reg_gio_r_pe_din___data___lsb 0
+#define reg_gio_r_pe_din___data___width 18
+#define reg_gio_r_pe_din_offset 84
+
+/* Register rw_pe_oe, scope gio, type rw */
+#define reg_gio_rw_pe_oe___oe___lsb 0
+#define reg_gio_rw_pe_oe___oe___width 18
+#define reg_gio_rw_pe_oe_offset 88
+
+
+/* Constants */
+#define regk_gio_anyedge 0x00000007
+#define regk_gio_hi 0x00000001
+#define regk_gio_lo 0x00000002
+#define regk_gio_negedge 0x00000006
+#define regk_gio_no 0x00000000
+#define regk_gio_off 0x00000000
+#define regk_gio_posedge 0x00000005
+#define regk_gio_rw_intr_cfg_default 0x00000000
+#define regk_gio_rw_intr_mask_default 0x00000000
+#define regk_gio_rw_pa_oe_default 0x00000000
+#define regk_gio_rw_pb_oe_default 0x00000000
+#define regk_gio_rw_pc_oe_default 0x00000000
+#define regk_gio_rw_pd_oe_default 0x00000000
+#define regk_gio_rw_pe_oe_default 0x00000000
+#define regk_gio_set 0x00000003
+#define regk_gio_yes 0x00000001
+#endif /* __gio_defs_asm_h */
--- /dev/null
+#ifndef __pinmux_defs_asm_h
+#define __pinmux_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
+ * last modfied: Mon Apr 11 16:09:11 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_pa, scope pinmux, type rw */
+#define reg_pinmux_rw_pa___pa0___lsb 0
+#define reg_pinmux_rw_pa___pa0___width 1
+#define reg_pinmux_rw_pa___pa0___bit 0
+#define reg_pinmux_rw_pa___pa1___lsb 1
+#define reg_pinmux_rw_pa___pa1___width 1
+#define reg_pinmux_rw_pa___pa1___bit 1
+#define reg_pinmux_rw_pa___pa2___lsb 2
+#define reg_pinmux_rw_pa___pa2___width 1
+#define reg_pinmux_rw_pa___pa2___bit 2
+#define reg_pinmux_rw_pa___pa3___lsb 3
+#define reg_pinmux_rw_pa___pa3___width 1
+#define reg_pinmux_rw_pa___pa3___bit 3
+#define reg_pinmux_rw_pa___pa4___lsb 4
+#define reg_pinmux_rw_pa___pa4___width 1
+#define reg_pinmux_rw_pa___pa4___bit 4
+#define reg_pinmux_rw_pa___pa5___lsb 5
+#define reg_pinmux_rw_pa___pa5___width 1
+#define reg_pinmux_rw_pa___pa5___bit 5
+#define reg_pinmux_rw_pa___pa6___lsb 6
+#define reg_pinmux_rw_pa___pa6___width 1
+#define reg_pinmux_rw_pa___pa6___bit 6
+#define reg_pinmux_rw_pa___pa7___lsb 7
+#define reg_pinmux_rw_pa___pa7___width 1
+#define reg_pinmux_rw_pa___pa7___bit 7
+#define reg_pinmux_rw_pa___csp2_n___lsb 8
+#define reg_pinmux_rw_pa___csp2_n___width 1
+#define reg_pinmux_rw_pa___csp2_n___bit 8
+#define reg_pinmux_rw_pa___csp3_n___lsb 9
+#define reg_pinmux_rw_pa___csp3_n___width 1
+#define reg_pinmux_rw_pa___csp3_n___bit 9
+#define reg_pinmux_rw_pa___csp5_n___lsb 10
+#define reg_pinmux_rw_pa___csp5_n___width 1
+#define reg_pinmux_rw_pa___csp5_n___bit 10
+#define reg_pinmux_rw_pa___csp6_n___lsb 11
+#define reg_pinmux_rw_pa___csp6_n___width 1
+#define reg_pinmux_rw_pa___csp6_n___bit 11
+#define reg_pinmux_rw_pa___hsh4___lsb 12
+#define reg_pinmux_rw_pa___hsh4___width 1
+#define reg_pinmux_rw_pa___hsh4___bit 12
+#define reg_pinmux_rw_pa___hsh5___lsb 13
+#define reg_pinmux_rw_pa___hsh5___width 1
+#define reg_pinmux_rw_pa___hsh5___bit 13
+#define reg_pinmux_rw_pa___hsh6___lsb 14
+#define reg_pinmux_rw_pa___hsh6___width 1
+#define reg_pinmux_rw_pa___hsh6___bit 14
+#define reg_pinmux_rw_pa___hsh7___lsb 15
+#define reg_pinmux_rw_pa___hsh7___width 1
+#define reg_pinmux_rw_pa___hsh7___bit 15
+#define reg_pinmux_rw_pa_offset 0
+
+/* Register rw_hwprot, scope pinmux, type rw */
+#define reg_pinmux_rw_hwprot___ser1___lsb 0
+#define reg_pinmux_rw_hwprot___ser1___width 1
+#define reg_pinmux_rw_hwprot___ser1___bit 0
+#define reg_pinmux_rw_hwprot___ser2___lsb 1
+#define reg_pinmux_rw_hwprot___ser2___width 1
+#define reg_pinmux_rw_hwprot___ser2___bit 1
+#define reg_pinmux_rw_hwprot___ser3___lsb 2
+#define reg_pinmux_rw_hwprot___ser3___width 1
+#define reg_pinmux_rw_hwprot___ser3___bit 2
+#define reg_pinmux_rw_hwprot___sser0___lsb 3
+#define reg_pinmux_rw_hwprot___sser0___width 1
+#define reg_pinmux_rw_hwprot___sser0___bit 3
+#define reg_pinmux_rw_hwprot___sser1___lsb 4
+#define reg_pinmux_rw_hwprot___sser1___width 1
+#define reg_pinmux_rw_hwprot___sser1___bit 4
+#define reg_pinmux_rw_hwprot___ata0___lsb 5
+#define reg_pinmux_rw_hwprot___ata0___width 1
+#define reg_pinmux_rw_hwprot___ata0___bit 5
+#define reg_pinmux_rw_hwprot___ata1___lsb 6
+#define reg_pinmux_rw_hwprot___ata1___width 1
+#define reg_pinmux_rw_hwprot___ata1___bit 6
+#define reg_pinmux_rw_hwprot___ata2___lsb 7
+#define reg_pinmux_rw_hwprot___ata2___width 1
+#define reg_pinmux_rw_hwprot___ata2___bit 7
+#define reg_pinmux_rw_hwprot___ata3___lsb 8
+#define reg_pinmux_rw_hwprot___ata3___width 1
+#define reg_pinmux_rw_hwprot___ata3___bit 8
+#define reg_pinmux_rw_hwprot___ata___lsb 9
+#define reg_pinmux_rw_hwprot___ata___width 1
+#define reg_pinmux_rw_hwprot___ata___bit 9
+#define reg_pinmux_rw_hwprot___eth1___lsb 10
+#define reg_pinmux_rw_hwprot___eth1___width 1
+#define reg_pinmux_rw_hwprot___eth1___bit 10
+#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11
+#define reg_pinmux_rw_hwprot___eth1_mgm___width 1
+#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11
+#define reg_pinmux_rw_hwprot___timer___lsb 12
+#define reg_pinmux_rw_hwprot___timer___width 1
+#define reg_pinmux_rw_hwprot___timer___bit 12
+#define reg_pinmux_rw_hwprot___p21___lsb 13
+#define reg_pinmux_rw_hwprot___p21___width 1
+#define reg_pinmux_rw_hwprot___p21___bit 13
+#define reg_pinmux_rw_hwprot_offset 4
+
+/* Register rw_pb_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pb_gio___pb0___lsb 0
+#define reg_pinmux_rw_pb_gio___pb0___width 1
+#define reg_pinmux_rw_pb_gio___pb0___bit 0
+#define reg_pinmux_rw_pb_gio___pb1___lsb 1
+#define reg_pinmux_rw_pb_gio___pb1___width 1
+#define reg_pinmux_rw_pb_gio___pb1___bit 1
+#define reg_pinmux_rw_pb_gio___pb2___lsb 2
+#define reg_pinmux_rw_pb_gio___pb2___width 1
+#define reg_pinmux_rw_pb_gio___pb2___bit 2
+#define reg_pinmux_rw_pb_gio___pb3___lsb 3
+#define reg_pinmux_rw_pb_gio___pb3___width 1
+#define reg_pinmux_rw_pb_gio___pb3___bit 3
+#define reg_pinmux_rw_pb_gio___pb4___lsb 4
+#define reg_pinmux_rw_pb_gio___pb4___width 1
+#define reg_pinmux_rw_pb_gio___pb4___bit 4
+#define reg_pinmux_rw_pb_gio___pb5___lsb 5
+#define reg_pinmux_rw_pb_gio___pb5___width 1
+#define reg_pinmux_rw_pb_gio___pb5___bit 5
+#define reg_pinmux_rw_pb_gio___pb6___lsb 6
+#define reg_pinmux_rw_pb_gio___pb6___width 1
+#define reg_pinmux_rw_pb_gio___pb6___bit 6
+#define reg_pinmux_rw_pb_gio___pb7___lsb 7
+#define reg_pinmux_rw_pb_gio___pb7___width 1
+#define reg_pinmux_rw_pb_gio___pb7___bit 7
+#define reg_pinmux_rw_pb_gio___pb8___lsb 8
+#define reg_pinmux_rw_pb_gio___pb8___width 1
+#define reg_pinmux_rw_pb_gio___pb8___bit 8
+#define reg_pinmux_rw_pb_gio___pb9___lsb 9
+#define reg_pinmux_rw_pb_gio___pb9___width 1
+#define reg_pinmux_rw_pb_gio___pb9___bit 9
+#define reg_pinmux_rw_pb_gio___pb10___lsb 10
+#define reg_pinmux_rw_pb_gio___pb10___width 1
+#define reg_pinmux_rw_pb_gio___pb10___bit 10
+#define reg_pinmux_rw_pb_gio___pb11___lsb 11
+#define reg_pinmux_rw_pb_gio___pb11___width 1
+#define reg_pinmux_rw_pb_gio___pb11___bit 11
+#define reg_pinmux_rw_pb_gio___pb12___lsb 12
+#define reg_pinmux_rw_pb_gio___pb12___width 1
+#define reg_pinmux_rw_pb_gio___pb12___bit 12
+#define reg_pinmux_rw_pb_gio___pb13___lsb 13
+#define reg_pinmux_rw_pb_gio___pb13___width 1
+#define reg_pinmux_rw_pb_gio___pb13___bit 13
+#define reg_pinmux_rw_pb_gio___pb14___lsb 14
+#define reg_pinmux_rw_pb_gio___pb14___width 1
+#define reg_pinmux_rw_pb_gio___pb14___bit 14
+#define reg_pinmux_rw_pb_gio___pb15___lsb 15
+#define reg_pinmux_rw_pb_gio___pb15___width 1
+#define reg_pinmux_rw_pb_gio___pb15___bit 15
+#define reg_pinmux_rw_pb_gio___pb16___lsb 16
+#define reg_pinmux_rw_pb_gio___pb16___width 1
+#define reg_pinmux_rw_pb_gio___pb16___bit 16
+#define reg_pinmux_rw_pb_gio___pb17___lsb 17
+#define reg_pinmux_rw_pb_gio___pb17___width 1
+#define reg_pinmux_rw_pb_gio___pb17___bit 17
+#define reg_pinmux_rw_pb_gio_offset 8
+
+/* Register rw_pb_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pb_iop___pb0___lsb 0
+#define reg_pinmux_rw_pb_iop___pb0___width 1
+#define reg_pinmux_rw_pb_iop___pb0___bit 0
+#define reg_pinmux_rw_pb_iop___pb1___lsb 1
+#define reg_pinmux_rw_pb_iop___pb1___width 1
+#define reg_pinmux_rw_pb_iop___pb1___bit 1
+#define reg_pinmux_rw_pb_iop___pb2___lsb 2
+#define reg_pinmux_rw_pb_iop___pb2___width 1
+#define reg_pinmux_rw_pb_iop___pb2___bit 2
+#define reg_pinmux_rw_pb_iop___pb3___lsb 3
+#define reg_pinmux_rw_pb_iop___pb3___width 1
+#define reg_pinmux_rw_pb_iop___pb3___bit 3
+#define reg_pinmux_rw_pb_iop___pb4___lsb 4
+#define reg_pinmux_rw_pb_iop___pb4___width 1
+#define reg_pinmux_rw_pb_iop___pb4___bit 4
+#define reg_pinmux_rw_pb_iop___pb5___lsb 5
+#define reg_pinmux_rw_pb_iop___pb5___width 1
+#define reg_pinmux_rw_pb_iop___pb5___bit 5
+#define reg_pinmux_rw_pb_iop___pb6___lsb 6
+#define reg_pinmux_rw_pb_iop___pb6___width 1
+#define reg_pinmux_rw_pb_iop___pb6___bit 6
+#define reg_pinmux_rw_pb_iop___pb7___lsb 7
+#define reg_pinmux_rw_pb_iop___pb7___width 1
+#define reg_pinmux_rw_pb_iop___pb7___bit 7
+#define reg_pinmux_rw_pb_iop___pb8___lsb 8
+#define reg_pinmux_rw_pb_iop___pb8___width 1
+#define reg_pinmux_rw_pb_iop___pb8___bit 8
+#define reg_pinmux_rw_pb_iop___pb9___lsb 9
+#define reg_pinmux_rw_pb_iop___pb9___width 1
+#define reg_pinmux_rw_pb_iop___pb9___bit 9
+#define reg_pinmux_rw_pb_iop___pb10___lsb 10
+#define reg_pinmux_rw_pb_iop___pb10___width 1
+#define reg_pinmux_rw_pb_iop___pb10___bit 10
+#define reg_pinmux_rw_pb_iop___pb11___lsb 11
+#define reg_pinmux_rw_pb_iop___pb11___width 1
+#define reg_pinmux_rw_pb_iop___pb11___bit 11
+#define reg_pinmux_rw_pb_iop___pb12___lsb 12
+#define reg_pinmux_rw_pb_iop___pb12___width 1
+#define reg_pinmux_rw_pb_iop___pb12___bit 12
+#define reg_pinmux_rw_pb_iop___pb13___lsb 13
+#define reg_pinmux_rw_pb_iop___pb13___width 1
+#define reg_pinmux_rw_pb_iop___pb13___bit 13
+#define reg_pinmux_rw_pb_iop___pb14___lsb 14
+#define reg_pinmux_rw_pb_iop___pb14___width 1
+#define reg_pinmux_rw_pb_iop___pb14___bit 14
+#define reg_pinmux_rw_pb_iop___pb15___lsb 15
+#define reg_pinmux_rw_pb_iop___pb15___width 1
+#define reg_pinmux_rw_pb_iop___pb15___bit 15
+#define reg_pinmux_rw_pb_iop___pb16___lsb 16
+#define reg_pinmux_rw_pb_iop___pb16___width 1
+#define reg_pinmux_rw_pb_iop___pb16___bit 16
+#define reg_pinmux_rw_pb_iop___pb17___lsb 17
+#define reg_pinmux_rw_pb_iop___pb17___width 1
+#define reg_pinmux_rw_pb_iop___pb17___bit 17
+#define reg_pinmux_rw_pb_iop_offset 12
+
+/* Register rw_pc_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pc_gio___pc0___lsb 0
+#define reg_pinmux_rw_pc_gio___pc0___width 1
+#define reg_pinmux_rw_pc_gio___pc0___bit 0
+#define reg_pinmux_rw_pc_gio___pc1___lsb 1
+#define reg_pinmux_rw_pc_gio___pc1___width 1
+#define reg_pinmux_rw_pc_gio___pc1___bit 1
+#define reg_pinmux_rw_pc_gio___pc2___lsb 2
+#define reg_pinmux_rw_pc_gio___pc2___width 1
+#define reg_pinmux_rw_pc_gio___pc2___bit 2
+#define reg_pinmux_rw_pc_gio___pc3___lsb 3
+#define reg_pinmux_rw_pc_gio___pc3___width 1
+#define reg_pinmux_rw_pc_gio___pc3___bit 3
+#define reg_pinmux_rw_pc_gio___pc4___lsb 4
+#define reg_pinmux_rw_pc_gio___pc4___width 1
+#define reg_pinmux_rw_pc_gio___pc4___bit 4
+#define reg_pinmux_rw_pc_gio___pc5___lsb 5
+#define reg_pinmux_rw_pc_gio___pc5___width 1
+#define reg_pinmux_rw_pc_gio___pc5___bit 5
+#define reg_pinmux_rw_pc_gio___pc6___lsb 6
+#define reg_pinmux_rw_pc_gio___pc6___width 1
+#define reg_pinmux_rw_pc_gio___pc6___bit 6
+#define reg_pinmux_rw_pc_gio___pc7___lsb 7
+#define reg_pinmux_rw_pc_gio___pc7___width 1
+#define reg_pinmux_rw_pc_gio___pc7___bit 7
+#define reg_pinmux_rw_pc_gio___pc8___lsb 8
+#define reg_pinmux_rw_pc_gio___pc8___width 1
+#define reg_pinmux_rw_pc_gio___pc8___bit 8
+#define reg_pinmux_rw_pc_gio___pc9___lsb 9
+#define reg_pinmux_rw_pc_gio___pc9___width 1
+#define reg_pinmux_rw_pc_gio___pc9___bit 9
+#define reg_pinmux_rw_pc_gio___pc10___lsb 10
+#define reg_pinmux_rw_pc_gio___pc10___width 1
+#define reg_pinmux_rw_pc_gio___pc10___bit 10
+#define reg_pinmux_rw_pc_gio___pc11___lsb 11
+#define reg_pinmux_rw_pc_gio___pc11___width 1
+#define reg_pinmux_rw_pc_gio___pc11___bit 11
+#define reg_pinmux_rw_pc_gio___pc12___lsb 12
+#define reg_pinmux_rw_pc_gio___pc12___width 1
+#define reg_pinmux_rw_pc_gio___pc12___bit 12
+#define reg_pinmux_rw_pc_gio___pc13___lsb 13
+#define reg_pinmux_rw_pc_gio___pc13___width 1
+#define reg_pinmux_rw_pc_gio___pc13___bit 13
+#define reg_pinmux_rw_pc_gio___pc14___lsb 14
+#define reg_pinmux_rw_pc_gio___pc14___width 1
+#define reg_pinmux_rw_pc_gio___pc14___bit 14
+#define reg_pinmux_rw_pc_gio___pc15___lsb 15
+#define reg_pinmux_rw_pc_gio___pc15___width 1
+#define reg_pinmux_rw_pc_gio___pc15___bit 15
+#define reg_pinmux_rw_pc_gio___pc16___lsb 16
+#define reg_pinmux_rw_pc_gio___pc16___width 1
+#define reg_pinmux_rw_pc_gio___pc16___bit 16
+#define reg_pinmux_rw_pc_gio___pc17___lsb 17
+#define reg_pinmux_rw_pc_gio___pc17___width 1
+#define reg_pinmux_rw_pc_gio___pc17___bit 17
+#define reg_pinmux_rw_pc_gio_offset 16
+
+/* Register rw_pc_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pc_iop___pc0___lsb 0
+#define reg_pinmux_rw_pc_iop___pc0___width 1
+#define reg_pinmux_rw_pc_iop___pc0___bit 0
+#define reg_pinmux_rw_pc_iop___pc1___lsb 1
+#define reg_pinmux_rw_pc_iop___pc1___width 1
+#define reg_pinmux_rw_pc_iop___pc1___bit 1
+#define reg_pinmux_rw_pc_iop___pc2___lsb 2
+#define reg_pinmux_rw_pc_iop___pc2___width 1
+#define reg_pinmux_rw_pc_iop___pc2___bit 2
+#define reg_pinmux_rw_pc_iop___pc3___lsb 3
+#define reg_pinmux_rw_pc_iop___pc3___width 1
+#define reg_pinmux_rw_pc_iop___pc3___bit 3
+#define reg_pinmux_rw_pc_iop___pc4___lsb 4
+#define reg_pinmux_rw_pc_iop___pc4___width 1
+#define reg_pinmux_rw_pc_iop___pc4___bit 4
+#define reg_pinmux_rw_pc_iop___pc5___lsb 5
+#define reg_pinmux_rw_pc_iop___pc5___width 1
+#define reg_pinmux_rw_pc_iop___pc5___bit 5
+#define reg_pinmux_rw_pc_iop___pc6___lsb 6
+#define reg_pinmux_rw_pc_iop___pc6___width 1
+#define reg_pinmux_rw_pc_iop___pc6___bit 6
+#define reg_pinmux_rw_pc_iop___pc7___lsb 7
+#define reg_pinmux_rw_pc_iop___pc7___width 1
+#define reg_pinmux_rw_pc_iop___pc7___bit 7
+#define reg_pinmux_rw_pc_iop___pc8___lsb 8
+#define reg_pinmux_rw_pc_iop___pc8___width 1
+#define reg_pinmux_rw_pc_iop___pc8___bit 8
+#define reg_pinmux_rw_pc_iop___pc9___lsb 9
+#define reg_pinmux_rw_pc_iop___pc9___width 1
+#define reg_pinmux_rw_pc_iop___pc9___bit 9
+#define reg_pinmux_rw_pc_iop___pc10___lsb 10
+#define reg_pinmux_rw_pc_iop___pc10___width 1
+#define reg_pinmux_rw_pc_iop___pc10___bit 10
+#define reg_pinmux_rw_pc_iop___pc11___lsb 11
+#define reg_pinmux_rw_pc_iop___pc11___width 1
+#define reg_pinmux_rw_pc_iop___pc11___bit 11
+#define reg_pinmux_rw_pc_iop___pc12___lsb 12
+#define reg_pinmux_rw_pc_iop___pc12___width 1
+#define reg_pinmux_rw_pc_iop___pc12___bit 12
+#define reg_pinmux_rw_pc_iop___pc13___lsb 13
+#define reg_pinmux_rw_pc_iop___pc13___width 1
+#define reg_pinmux_rw_pc_iop___pc13___bit 13
+#define reg_pinmux_rw_pc_iop___pc14___lsb 14
+#define reg_pinmux_rw_pc_iop___pc14___width 1
+#define reg_pinmux_rw_pc_iop___pc14___bit 14
+#define reg_pinmux_rw_pc_iop___pc15___lsb 15
+#define reg_pinmux_rw_pc_iop___pc15___width 1
+#define reg_pinmux_rw_pc_iop___pc15___bit 15
+#define reg_pinmux_rw_pc_iop___pc16___lsb 16
+#define reg_pinmux_rw_pc_iop___pc16___width 1
+#define reg_pinmux_rw_pc_iop___pc16___bit 16
+#define reg_pinmux_rw_pc_iop___pc17___lsb 17
+#define reg_pinmux_rw_pc_iop___pc17___width 1
+#define reg_pinmux_rw_pc_iop___pc17___bit 17
+#define reg_pinmux_rw_pc_iop_offset 20
+
+/* Register rw_pd_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pd_gio___pd0___lsb 0
+#define reg_pinmux_rw_pd_gio___pd0___width 1
+#define reg_pinmux_rw_pd_gio___pd0___bit 0
+#define reg_pinmux_rw_pd_gio___pd1___lsb 1
+#define reg_pinmux_rw_pd_gio___pd1___width 1
+#define reg_pinmux_rw_pd_gio___pd1___bit 1
+#define reg_pinmux_rw_pd_gio___pd2___lsb 2
+#define reg_pinmux_rw_pd_gio___pd2___width 1
+#define reg_pinmux_rw_pd_gio___pd2___bit 2
+#define reg_pinmux_rw_pd_gio___pd3___lsb 3
+#define reg_pinmux_rw_pd_gio___pd3___width 1
+#define reg_pinmux_rw_pd_gio___pd3___bit 3
+#define reg_pinmux_rw_pd_gio___pd4___lsb 4
+#define reg_pinmux_rw_pd_gio___pd4___width 1
+#define reg_pinmux_rw_pd_gio___pd4___bit 4
+#define reg_pinmux_rw_pd_gio___pd5___lsb 5
+#define reg_pinmux_rw_pd_gio___pd5___width 1
+#define reg_pinmux_rw_pd_gio___pd5___bit 5
+#define reg_pinmux_rw_pd_gio___pd6___lsb 6
+#define reg_pinmux_rw_pd_gio___pd6___width 1
+#define reg_pinmux_rw_pd_gio___pd6___bit 6
+#define reg_pinmux_rw_pd_gio___pd7___lsb 7
+#define reg_pinmux_rw_pd_gio___pd7___width 1
+#define reg_pinmux_rw_pd_gio___pd7___bit 7
+#define reg_pinmux_rw_pd_gio___pd8___lsb 8
+#define reg_pinmux_rw_pd_gio___pd8___width 1
+#define reg_pinmux_rw_pd_gio___pd8___bit 8
+#define reg_pinmux_rw_pd_gio___pd9___lsb 9
+#define reg_pinmux_rw_pd_gio___pd9___width 1
+#define reg_pinmux_rw_pd_gio___pd9___bit 9
+#define reg_pinmux_rw_pd_gio___pd10___lsb 10
+#define reg_pinmux_rw_pd_gio___pd10___width 1
+#define reg_pinmux_rw_pd_gio___pd10___bit 10
+#define reg_pinmux_rw_pd_gio___pd11___lsb 11
+#define reg_pinmux_rw_pd_gio___pd11___width 1
+#define reg_pinmux_rw_pd_gio___pd11___bit 11
+#define reg_pinmux_rw_pd_gio___pd12___lsb 12
+#define reg_pinmux_rw_pd_gio___pd12___width 1
+#define reg_pinmux_rw_pd_gio___pd12___bit 12
+#define reg_pinmux_rw_pd_gio___pd13___lsb 13
+#define reg_pinmux_rw_pd_gio___pd13___width 1
+#define reg_pinmux_rw_pd_gio___pd13___bit 13
+#define reg_pinmux_rw_pd_gio___pd14___lsb 14
+#define reg_pinmux_rw_pd_gio___pd14___width 1
+#define reg_pinmux_rw_pd_gio___pd14___bit 14
+#define reg_pinmux_rw_pd_gio___pd15___lsb 15
+#define reg_pinmux_rw_pd_gio___pd15___width 1
+#define reg_pinmux_rw_pd_gio___pd15___bit 15
+#define reg_pinmux_rw_pd_gio___pd16___lsb 16
+#define reg_pinmux_rw_pd_gio___pd16___width 1
+#define reg_pinmux_rw_pd_gio___pd16___bit 16
+#define reg_pinmux_rw_pd_gio___pd17___lsb 17
+#define reg_pinmux_rw_pd_gio___pd17___width 1
+#define reg_pinmux_rw_pd_gio___pd17___bit 17
+#define reg_pinmux_rw_pd_gio_offset 24
+
+/* Register rw_pd_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pd_iop___pd0___lsb 0
+#define reg_pinmux_rw_pd_iop___pd0___width 1
+#define reg_pinmux_rw_pd_iop___pd0___bit 0
+#define reg_pinmux_rw_pd_iop___pd1___lsb 1
+#define reg_pinmux_rw_pd_iop___pd1___width 1
+#define reg_pinmux_rw_pd_iop___pd1___bit 1
+#define reg_pinmux_rw_pd_iop___pd2___lsb 2
+#define reg_pinmux_rw_pd_iop___pd2___width 1
+#define reg_pinmux_rw_pd_iop___pd2___bit 2
+#define reg_pinmux_rw_pd_iop___pd3___lsb 3
+#define reg_pinmux_rw_pd_iop___pd3___width 1
+#define reg_pinmux_rw_pd_iop___pd3___bit 3
+#define reg_pinmux_rw_pd_iop___pd4___lsb 4
+#define reg_pinmux_rw_pd_iop___pd4___width 1
+#define reg_pinmux_rw_pd_iop___pd4___bit 4
+#define reg_pinmux_rw_pd_iop___pd5___lsb 5
+#define reg_pinmux_rw_pd_iop___pd5___width 1
+#define reg_pinmux_rw_pd_iop___pd5___bit 5
+#define reg_pinmux_rw_pd_iop___pd6___lsb 6
+#define reg_pinmux_rw_pd_iop___pd6___width 1
+#define reg_pinmux_rw_pd_iop___pd6___bit 6
+#define reg_pinmux_rw_pd_iop___pd7___lsb 7
+#define reg_pinmux_rw_pd_iop___pd7___width 1
+#define reg_pinmux_rw_pd_iop___pd7___bit 7
+#define reg_pinmux_rw_pd_iop___pd8___lsb 8
+#define reg_pinmux_rw_pd_iop___pd8___width 1
+#define reg_pinmux_rw_pd_iop___pd8___bit 8
+#define reg_pinmux_rw_pd_iop___pd9___lsb 9
+#define reg_pinmux_rw_pd_iop___pd9___width 1
+#define reg_pinmux_rw_pd_iop___pd9___bit 9
+#define reg_pinmux_rw_pd_iop___pd10___lsb 10
+#define reg_pinmux_rw_pd_iop___pd10___width 1
+#define reg_pinmux_rw_pd_iop___pd10___bit 10
+#define reg_pinmux_rw_pd_iop___pd11___lsb 11
+#define reg_pinmux_rw_pd_iop___pd11___width 1
+#define reg_pinmux_rw_pd_iop___pd11___bit 11
+#define reg_pinmux_rw_pd_iop___pd12___lsb 12
+#define reg_pinmux_rw_pd_iop___pd12___width 1
+#define reg_pinmux_rw_pd_iop___pd12___bit 12
+#define reg_pinmux_rw_pd_iop___pd13___lsb 13
+#define reg_pinmux_rw_pd_iop___pd13___width 1
+#define reg_pinmux_rw_pd_iop___pd13___bit 13
+#define reg_pinmux_rw_pd_iop___pd14___lsb 14
+#define reg_pinmux_rw_pd_iop___pd14___width 1
+#define reg_pinmux_rw_pd_iop___pd14___bit 14
+#define reg_pinmux_rw_pd_iop___pd15___lsb 15
+#define reg_pinmux_rw_pd_iop___pd15___width 1
+#define reg_pinmux_rw_pd_iop___pd15___bit 15
+#define reg_pinmux_rw_pd_iop___pd16___lsb 16
+#define reg_pinmux_rw_pd_iop___pd16___width 1
+#define reg_pinmux_rw_pd_iop___pd16___bit 16
+#define reg_pinmux_rw_pd_iop___pd17___lsb 17
+#define reg_pinmux_rw_pd_iop___pd17___width 1
+#define reg_pinmux_rw_pd_iop___pd17___bit 17
+#define reg_pinmux_rw_pd_iop_offset 28
+
+/* Register rw_pe_gio, scope pinmux, type rw */
+#define reg_pinmux_rw_pe_gio___pe0___lsb 0
+#define reg_pinmux_rw_pe_gio___pe0___width 1
+#define reg_pinmux_rw_pe_gio___pe0___bit 0
+#define reg_pinmux_rw_pe_gio___pe1___lsb 1
+#define reg_pinmux_rw_pe_gio___pe1___width 1
+#define reg_pinmux_rw_pe_gio___pe1___bit 1
+#define reg_pinmux_rw_pe_gio___pe2___lsb 2
+#define reg_pinmux_rw_pe_gio___pe2___width 1
+#define reg_pinmux_rw_pe_gio___pe2___bit 2
+#define reg_pinmux_rw_pe_gio___pe3___lsb 3
+#define reg_pinmux_rw_pe_gio___pe3___width 1
+#define reg_pinmux_rw_pe_gio___pe3___bit 3
+#define reg_pinmux_rw_pe_gio___pe4___lsb 4
+#define reg_pinmux_rw_pe_gio___pe4___width 1
+#define reg_pinmux_rw_pe_gio___pe4___bit 4
+#define reg_pinmux_rw_pe_gio___pe5___lsb 5
+#define reg_pinmux_rw_pe_gio___pe5___width 1
+#define reg_pinmux_rw_pe_gio___pe5___bit 5
+#define reg_pinmux_rw_pe_gio___pe6___lsb 6
+#define reg_pinmux_rw_pe_gio___pe6___width 1
+#define reg_pinmux_rw_pe_gio___pe6___bit 6
+#define reg_pinmux_rw_pe_gio___pe7___lsb 7
+#define reg_pinmux_rw_pe_gio___pe7___width 1
+#define reg_pinmux_rw_pe_gio___pe7___bit 7
+#define reg_pinmux_rw_pe_gio___pe8___lsb 8
+#define reg_pinmux_rw_pe_gio___pe8___width 1
+#define reg_pinmux_rw_pe_gio___pe8___bit 8
+#define reg_pinmux_rw_pe_gio___pe9___lsb 9
+#define reg_pinmux_rw_pe_gio___pe9___width 1
+#define reg_pinmux_rw_pe_gio___pe9___bit 9
+#define reg_pinmux_rw_pe_gio___pe10___lsb 10
+#define reg_pinmux_rw_pe_gio___pe10___width 1
+#define reg_pinmux_rw_pe_gio___pe10___bit 10
+#define reg_pinmux_rw_pe_gio___pe11___lsb 11
+#define reg_pinmux_rw_pe_gio___pe11___width 1
+#define reg_pinmux_rw_pe_gio___pe11___bit 11
+#define reg_pinmux_rw_pe_gio___pe12___lsb 12
+#define reg_pinmux_rw_pe_gio___pe12___width 1
+#define reg_pinmux_rw_pe_gio___pe12___bit 12
+#define reg_pinmux_rw_pe_gio___pe13___lsb 13
+#define reg_pinmux_rw_pe_gio___pe13___width 1
+#define reg_pinmux_rw_pe_gio___pe13___bit 13
+#define reg_pinmux_rw_pe_gio___pe14___lsb 14
+#define reg_pinmux_rw_pe_gio___pe14___width 1
+#define reg_pinmux_rw_pe_gio___pe14___bit 14
+#define reg_pinmux_rw_pe_gio___pe15___lsb 15
+#define reg_pinmux_rw_pe_gio___pe15___width 1
+#define reg_pinmux_rw_pe_gio___pe15___bit 15
+#define reg_pinmux_rw_pe_gio___pe16___lsb 16
+#define reg_pinmux_rw_pe_gio___pe16___width 1
+#define reg_pinmux_rw_pe_gio___pe16___bit 16
+#define reg_pinmux_rw_pe_gio___pe17___lsb 17
+#define reg_pinmux_rw_pe_gio___pe17___width 1
+#define reg_pinmux_rw_pe_gio___pe17___bit 17
+#define reg_pinmux_rw_pe_gio_offset 32
+
+/* Register rw_pe_iop, scope pinmux, type rw */
+#define reg_pinmux_rw_pe_iop___pe0___lsb 0
+#define reg_pinmux_rw_pe_iop___pe0___width 1
+#define reg_pinmux_rw_pe_iop___pe0___bit 0
+#define reg_pinmux_rw_pe_iop___pe1___lsb 1
+#define reg_pinmux_rw_pe_iop___pe1___width 1
+#define reg_pinmux_rw_pe_iop___pe1___bit 1
+#define reg_pinmux_rw_pe_iop___pe2___lsb 2
+#define reg_pinmux_rw_pe_iop___pe2___width 1
+#define reg_pinmux_rw_pe_iop___pe2___bit 2
+#define reg_pinmux_rw_pe_iop___pe3___lsb 3
+#define reg_pinmux_rw_pe_iop___pe3___width 1
+#define reg_pinmux_rw_pe_iop___pe3___bit 3
+#define reg_pinmux_rw_pe_iop___pe4___lsb 4
+#define reg_pinmux_rw_pe_iop___pe4___width 1
+#define reg_pinmux_rw_pe_iop___pe4___bit 4
+#define reg_pinmux_rw_pe_iop___pe5___lsb 5
+#define reg_pinmux_rw_pe_iop___pe5___width 1
+#define reg_pinmux_rw_pe_iop___pe5___bit 5
+#define reg_pinmux_rw_pe_iop___pe6___lsb 6
+#define reg_pinmux_rw_pe_iop___pe6___width 1
+#define reg_pinmux_rw_pe_iop___pe6___bit 6
+#define reg_pinmux_rw_pe_iop___pe7___lsb 7
+#define reg_pinmux_rw_pe_iop___pe7___width 1
+#define reg_pinmux_rw_pe_iop___pe7___bit 7
+#define reg_pinmux_rw_pe_iop___pe8___lsb 8
+#define reg_pinmux_rw_pe_iop___pe8___width 1
+#define reg_pinmux_rw_pe_iop___pe8___bit 8
+#define reg_pinmux_rw_pe_iop___pe9___lsb 9
+#define reg_pinmux_rw_pe_iop___pe9___width 1
+#define reg_pinmux_rw_pe_iop___pe9___bit 9
+#define reg_pinmux_rw_pe_iop___pe10___lsb 10
+#define reg_pinmux_rw_pe_iop___pe10___width 1
+#define reg_pinmux_rw_pe_iop___pe10___bit 10
+#define reg_pinmux_rw_pe_iop___pe11___lsb 11
+#define reg_pinmux_rw_pe_iop___pe11___width 1
+#define reg_pinmux_rw_pe_iop___pe11___bit 11
+#define reg_pinmux_rw_pe_iop___pe12___lsb 12
+#define reg_pinmux_rw_pe_iop___pe12___width 1
+#define reg_pinmux_rw_pe_iop___pe12___bit 12
+#define reg_pinmux_rw_pe_iop___pe13___lsb 13
+#define reg_pinmux_rw_pe_iop___pe13___width 1
+#define reg_pinmux_rw_pe_iop___pe13___bit 13
+#define reg_pinmux_rw_pe_iop___pe14___lsb 14
+#define reg_pinmux_rw_pe_iop___pe14___width 1
+#define reg_pinmux_rw_pe_iop___pe14___bit 14
+#define reg_pinmux_rw_pe_iop___pe15___lsb 15
+#define reg_pinmux_rw_pe_iop___pe15___width 1
+#define reg_pinmux_rw_pe_iop___pe15___bit 15
+#define reg_pinmux_rw_pe_iop___pe16___lsb 16
+#define reg_pinmux_rw_pe_iop___pe16___width 1
+#define reg_pinmux_rw_pe_iop___pe16___bit 16
+#define reg_pinmux_rw_pe_iop___pe17___lsb 17
+#define reg_pinmux_rw_pe_iop___pe17___width 1
+#define reg_pinmux_rw_pe_iop___pe17___bit 17
+#define reg_pinmux_rw_pe_iop_offset 36
+
+/* Register rw_usb_phy, scope pinmux, type rw */
+#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0
+#define reg_pinmux_rw_usb_phy___en_usb0___width 1
+#define reg_pinmux_rw_usb_phy___en_usb0___bit 0
+#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1
+#define reg_pinmux_rw_usb_phy___en_usb1___width 1
+#define reg_pinmux_rw_usb_phy___en_usb1___bit 1
+#define reg_pinmux_rw_usb_phy_offset 40
+
+
+/* Constants */
+#define regk_pinmux_no 0x00000000
+#define regk_pinmux_rw_hwprot_default 0x00000000
+#define regk_pinmux_rw_pa_default 0x00000000
+#define regk_pinmux_rw_pb_gio_default 0x00000000
+#define regk_pinmux_rw_pb_iop_default 0x00000000
+#define regk_pinmux_rw_pc_gio_default 0x00000000
+#define regk_pinmux_rw_pc_iop_default 0x00000000
+#define regk_pinmux_rw_pd_gio_default 0x00000000
+#define regk_pinmux_rw_pd_iop_default 0x00000000
+#define regk_pinmux_rw_pe_gio_default 0x00000000
+#define regk_pinmux_rw_pe_iop_default 0x00000000
+#define regk_pinmux_rw_usb_phy_default 0x00000000
+#define regk_pinmux_yes 0x00000001
+#endif /* __pinmux_defs_asm_h */
--- /dev/null
+#ifndef __reg_map_h
+#define __reg_map_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../mod/fakereg.rmap
+ * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
+ * last modified: Wed Feb 11 20:53:25 2004
+ * file: ../../rtl/global.rmap
+ * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
+ * last modified: Mon Aug 18 17:08:23 2003
+ * file: ../../mod/modreg.rmap
+ * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
+ * last modified: Fri Feb 20 16:40:04 2004
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
+ * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+#define regi_artpec_mod 0xb7044000
+#define regi_ata 0xb0032000
+#define regi_ata_mod 0xb7006000
+#define regi_barber 0xb701a000
+#define regi_bif_core 0xb0014000
+#define regi_bif_dma 0xb0016000
+#define regi_bif_slave 0xb0018000
+#define regi_bif_slave_ext 0xac000000
+#define regi_bus_master 0xb703c000
+#define regi_config 0xb003c000
+#define regi_dma0 0xb0000000
+#define regi_dma1 0xb0002000
+#define regi_dma2 0xb0004000
+#define regi_dma3 0xb0006000
+#define regi_dma4 0xb0008000
+#define regi_dma5 0xb000a000
+#define regi_dma6 0xb000c000
+#define regi_dma7 0xb000e000
+#define regi_dma8 0xb0010000
+#define regi_dma9 0xb0012000
+#define regi_eth0 0xb0034000
+#define regi_eth1 0xb0036000
+#define regi_eth_mod 0xb7004000
+#define regi_eth_mod1 0xb701c000
+#define regi_eth_strmod 0xb7008000
+#define regi_eth_strmod1 0xb7032000
+#define regi_ext_dma 0xb703a000
+#define regi_ext_mem 0xb7046000
+#define regi_gen_io 0xb7016000
+#define regi_gio 0xb001a000
+#define regi_hook 0xb7000000
+#define regi_iop 0xb0020000
+#define regi_irq 0xb001c000
+#define regi_irq_nmi 0xb701e000
+#define regi_marb 0xb003e000
+#define regi_marb_bp0 0xb003e240
+#define regi_marb_bp1 0xb003e280
+#define regi_marb_bp2 0xb003e2c0
+#define regi_marb_bp3 0xb003e300
+#define regi_nand_mod 0xb7014000
+#define regi_p21 0xb002e000
+#define regi_p21_mod 0xb7042000
+#define regi_pci_mod 0xb7010000
+#define regi_pin_test 0xb7018000
+#define regi_pinmux 0xb0038000
+#define regi_sdram_chk 0xb703e000
+#define regi_sdram_mod 0xb7012000
+#define regi_ser0 0xb0026000
+#define regi_ser1 0xb0028000
+#define regi_ser2 0xb002a000
+#define regi_ser3 0xb002c000
+#define regi_ser_mod0 0xb7020000
+#define regi_ser_mod1 0xb7022000
+#define regi_ser_mod2 0xb7024000
+#define regi_ser_mod3 0xb7026000
+#define regi_smif_stat 0xb700e000
+#define regi_sser0 0xb0022000
+#define regi_sser1 0xb0024000
+#define regi_sser_mod0 0xb700a000
+#define regi_sser_mod1 0xb700c000
+#define regi_strcop 0xb0030000
+#define regi_strmux 0xb003a000
+#define regi_strmux_tst 0xb7040000
+#define regi_tap 0xb7002000
+#define regi_timer 0xb001e000
+#define regi_timer_mod 0xb7034000
+#define regi_trace 0xb0040000
+#define regi_usb0 0xb7028000
+#define regi_usb1 0xb702a000
+#define regi_usb2 0xb702c000
+#define regi_usb3 0xb702e000
+#define regi_usb_dev 0xb7030000
+#define regi_utmi_mod0 0xb7036000
+#define regi_utmi_mod1 0xb7038000
+#endif /* __reg_map_h */
--- /dev/null
+#ifndef __timer_defs_asm_h
+#define __timer_defs_asm_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/timer/rtl/timer_regs.r
+ * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
+ * last modfied: Mon Apr 11 16:09:53 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r
+ * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+
+#ifndef REG_FIELD
+#define REG_FIELD( scope, reg, field, value ) \
+ REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_FIELD_X_( value, shift ) ((value) << shift)
+#endif
+
+#ifndef REG_STATE
+#define REG_STATE( scope, reg, field, symbolic_value ) \
+ REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
+#define REG_STATE_X_( k, shift ) (k << shift)
+#endif
+
+#ifndef REG_MASK
+#define REG_MASK( scope, reg, field ) \
+ REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
+#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
+#endif
+
+#ifndef REG_LSB
+#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
+#endif
+
+#ifndef REG_BIT
+#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
+#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
+ STRIDE_##scope##_##reg )
+#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
+ ((inst) + offs + (index) * stride)
+#endif
+
+/* Register rw_tmr0_div, scope timer, type rw */
+#define reg_timer_rw_tmr0_div_offset 0
+
+/* Register r_tmr0_data, scope timer, type r */
+#define reg_timer_r_tmr0_data_offset 4
+
+/* Register rw_tmr0_ctrl, scope timer, type rw */
+#define reg_timer_rw_tmr0_ctrl___op___lsb 0
+#define reg_timer_rw_tmr0_ctrl___op___width 2
+#define reg_timer_rw_tmr0_ctrl___freq___lsb 2
+#define reg_timer_rw_tmr0_ctrl___freq___width 3
+#define reg_timer_rw_tmr0_ctrl_offset 8
+
+/* Register rw_tmr1_div, scope timer, type rw */
+#define reg_timer_rw_tmr1_div_offset 16
+
+/* Register r_tmr1_data, scope timer, type r */
+#define reg_timer_r_tmr1_data_offset 20
+
+/* Register rw_tmr1_ctrl, scope timer, type rw */
+#define reg_timer_rw_tmr1_ctrl___op___lsb 0
+#define reg_timer_rw_tmr1_ctrl___op___width 2
+#define reg_timer_rw_tmr1_ctrl___freq___lsb 2
+#define reg_timer_rw_tmr1_ctrl___freq___width 3
+#define reg_timer_rw_tmr1_ctrl_offset 24
+
+/* Register rs_cnt_data, scope timer, type rs */
+#define reg_timer_rs_cnt_data___tmr___lsb 0
+#define reg_timer_rs_cnt_data___tmr___width 24
+#define reg_timer_rs_cnt_data___cnt___lsb 24
+#define reg_timer_rs_cnt_data___cnt___width 8
+#define reg_timer_rs_cnt_data_offset 32
+
+/* Register r_cnt_data, scope timer, type r */
+#define reg_timer_r_cnt_data___tmr___lsb 0
+#define reg_timer_r_cnt_data___tmr___width 24
+#define reg_timer_r_cnt_data___cnt___lsb 24
+#define reg_timer_r_cnt_data___cnt___width 8
+#define reg_timer_r_cnt_data_offset 36
+
+/* Register rw_cnt_cfg, scope timer, type rw */
+#define reg_timer_rw_cnt_cfg___clk___lsb 0
+#define reg_timer_rw_cnt_cfg___clk___width 2
+#define reg_timer_rw_cnt_cfg_offset 40
+
+/* Register rw_trig, scope timer, type rw */
+#define reg_timer_rw_trig_offset 48
+
+/* Register rw_trig_cfg, scope timer, type rw */
+#define reg_timer_rw_trig_cfg___tmr___lsb 0
+#define reg_timer_rw_trig_cfg___tmr___width 2
+#define reg_timer_rw_trig_cfg_offset 52
+
+/* Register r_time, scope timer, type r */
+#define reg_timer_r_time_offset 56
+
+/* Register rw_out, scope timer, type rw */
+#define reg_timer_rw_out___tmr___lsb 0
+#define reg_timer_rw_out___tmr___width 2
+#define reg_timer_rw_out_offset 60
+
+/* Register rw_wd_ctrl, scope timer, type rw */
+#define reg_timer_rw_wd_ctrl___cnt___lsb 0
+#define reg_timer_rw_wd_ctrl___cnt___width 8
+#define reg_timer_rw_wd_ctrl___cmd___lsb 8
+#define reg_timer_rw_wd_ctrl___cmd___width 1
+#define reg_timer_rw_wd_ctrl___cmd___bit 8
+#define reg_timer_rw_wd_ctrl___key___lsb 9
+#define reg_timer_rw_wd_ctrl___key___width 7
+#define reg_timer_rw_wd_ctrl_offset 64
+
+/* Register r_wd_stat, scope timer, type r */
+#define reg_timer_r_wd_stat___cnt___lsb 0
+#define reg_timer_r_wd_stat___cnt___width 8
+#define reg_timer_r_wd_stat___cmd___lsb 8
+#define reg_timer_r_wd_stat___cmd___width 1
+#define reg_timer_r_wd_stat___cmd___bit 8
+#define reg_timer_r_wd_stat_offset 68
+
+/* Register rw_intr_mask, scope timer, type rw */
+#define reg_timer_rw_intr_mask___tmr0___lsb 0
+#define reg_timer_rw_intr_mask___tmr0___width 1
+#define reg_timer_rw_intr_mask___tmr0___bit 0
+#define reg_timer_rw_intr_mask___tmr1___lsb 1
+#define reg_timer_rw_intr_mask___tmr1___width 1
+#define reg_timer_rw_intr_mask___tmr1___bit 1
+#define reg_timer_rw_intr_mask___cnt___lsb 2
+#define reg_timer_rw_intr_mask___cnt___width 1
+#define reg_timer_rw_intr_mask___cnt___bit 2
+#define reg_timer_rw_intr_mask___trig___lsb 3
+#define reg_timer_rw_intr_mask___trig___width 1
+#define reg_timer_rw_intr_mask___trig___bit 3
+#define reg_timer_rw_intr_mask_offset 72
+
+/* Register rw_ack_intr, scope timer, type rw */
+#define reg_timer_rw_ack_intr___tmr0___lsb 0
+#define reg_timer_rw_ack_intr___tmr0___width 1
+#define reg_timer_rw_ack_intr___tmr0___bit 0
+#define reg_timer_rw_ack_intr___tmr1___lsb 1
+#define reg_timer_rw_ack_intr___tmr1___width 1
+#define reg_timer_rw_ack_intr___tmr1___bit 1
+#define reg_timer_rw_ack_intr___cnt___lsb 2
+#define reg_timer_rw_ack_intr___cnt___width 1
+#define reg_timer_rw_ack_intr___cnt___bit 2
+#define reg_timer_rw_ack_intr___trig___lsb 3
+#define reg_timer_rw_ack_intr___trig___width 1
+#define reg_timer_rw_ack_intr___trig___bit 3
+#define reg_timer_rw_ack_intr_offset 76
+
+/* Register r_intr, scope timer, type r */
+#define reg_timer_r_intr___tmr0___lsb 0
+#define reg_timer_r_intr___tmr0___width 1
+#define reg_timer_r_intr___tmr0___bit 0
+#define reg_timer_r_intr___tmr1___lsb 1
+#define reg_timer_r_intr___tmr1___width 1
+#define reg_timer_r_intr___tmr1___bit 1
+#define reg_timer_r_intr___cnt___lsb 2
+#define reg_timer_r_intr___cnt___width 1
+#define reg_timer_r_intr___cnt___bit 2
+#define reg_timer_r_intr___trig___lsb 3
+#define reg_timer_r_intr___trig___width 1
+#define reg_timer_r_intr___trig___bit 3
+#define reg_timer_r_intr_offset 80
+
+/* Register r_masked_intr, scope timer, type r */
+#define reg_timer_r_masked_intr___tmr0___lsb 0
+#define reg_timer_r_masked_intr___tmr0___width 1
+#define reg_timer_r_masked_intr___tmr0___bit 0
+#define reg_timer_r_masked_intr___tmr1___lsb 1
+#define reg_timer_r_masked_intr___tmr1___width 1
+#define reg_timer_r_masked_intr___tmr1___bit 1
+#define reg_timer_r_masked_intr___cnt___lsb 2
+#define reg_timer_r_masked_intr___cnt___width 1
+#define reg_timer_r_masked_intr___cnt___bit 2
+#define reg_timer_r_masked_intr___trig___lsb 3
+#define reg_timer_r_masked_intr___trig___width 1
+#define reg_timer_r_masked_intr___trig___bit 3
+#define reg_timer_r_masked_intr_offset 84
+
+/* Register rw_test, scope timer, type rw */
+#define reg_timer_rw_test___dis___lsb 0
+#define reg_timer_rw_test___dis___width 1
+#define reg_timer_rw_test___dis___bit 0
+#define reg_timer_rw_test___en___lsb 1
+#define reg_timer_rw_test___en___width 1
+#define reg_timer_rw_test___en___bit 1
+#define reg_timer_rw_test_offset 88
+
+
+/* Constants */
+#define regk_timer_ext 0x00000001
+#define regk_timer_f100 0x00000007
+#define regk_timer_f29_493 0x00000004
+#define regk_timer_f32 0x00000005
+#define regk_timer_f32_768 0x00000006
+#define regk_timer_hold 0x00000001
+#define regk_timer_ld 0x00000000
+#define regk_timer_no 0x00000000
+#define regk_timer_off 0x00000000
+#define regk_timer_run 0x00000002
+#define regk_timer_rw_cnt_cfg_default 0x00000000
+#define regk_timer_rw_intr_mask_default 0x00000000
+#define regk_timer_rw_out_default 0x00000000
+#define regk_timer_rw_test_default 0x00000000
+#define regk_timer_rw_tmr0_ctrl_default 0x00000000
+#define regk_timer_rw_tmr1_ctrl_default 0x00000000
+#define regk_timer_rw_trig_cfg_default 0x00000000
+#define regk_timer_start 0x00000001
+#define regk_timer_stop 0x00000000
+#define regk_timer_time 0x00000001
+#define regk_timer_tmr0 0x00000002
+#define regk_timer_tmr1 0x00000003
+#define regk_timer_yes 0x00000001
+#endif /* __timer_defs_asm_h */
--- /dev/null
+#ifndef __bif_core_defs_h
+#define __bif_core_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/bif/rtl/bif_core_regs.r
+ * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp
+ * last modfied: Mon Apr 11 16:06:33 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r
+ * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope bif_core */
+
+/* Register rw_grp1_cfg, scope bif_core, type rw */
+typedef struct {
+ unsigned int lw : 6;
+ unsigned int ew : 3;
+ unsigned int zw : 3;
+ unsigned int aw : 2;
+ unsigned int dw : 2;
+ unsigned int ewb : 2;
+ unsigned int bw : 1;
+ unsigned int wr_extend : 1;
+ unsigned int erc_en : 1;
+ unsigned int mode : 1;
+ unsigned int dummy1 : 10;
+} reg_bif_core_rw_grp1_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0
+#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0
+
+/* Register rw_grp2_cfg, scope bif_core, type rw */
+typedef struct {
+ unsigned int lw : 6;
+ unsigned int ew : 3;
+ unsigned int zw : 3;
+ unsigned int aw : 2;
+ unsigned int dw : 2;
+ unsigned int ewb : 2;
+ unsigned int bw : 1;
+ unsigned int wr_extend : 1;
+ unsigned int erc_en : 1;
+ unsigned int mode : 1;
+ unsigned int dummy1 : 10;
+} reg_bif_core_rw_grp2_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4
+#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4
+
+/* Register rw_grp3_cfg, scope bif_core, type rw */
+typedef struct {
+ unsigned int lw : 6;
+ unsigned int ew : 3;
+ unsigned int zw : 3;
+ unsigned int aw : 2;
+ unsigned int dw : 2;
+ unsigned int ewb : 2;
+ unsigned int bw : 1;
+ unsigned int wr_extend : 1;
+ unsigned int erc_en : 1;
+ unsigned int mode : 1;
+ unsigned int dummy1 : 2;
+ unsigned int gated_csp0 : 2;
+ unsigned int gated_csp1 : 2;
+ unsigned int gated_csp2 : 2;
+ unsigned int gated_csp3 : 2;
+} reg_bif_core_rw_grp3_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8
+#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8
+
+/* Register rw_grp4_cfg, scope bif_core, type rw */
+typedef struct {
+ unsigned int lw : 6;
+ unsigned int ew : 3;
+ unsigned int zw : 3;
+ unsigned int aw : 2;
+ unsigned int dw : 2;
+ unsigned int ewb : 2;
+ unsigned int bw : 1;
+ unsigned int wr_extend : 1;
+ unsigned int erc_en : 1;
+ unsigned int mode : 1;
+ unsigned int dummy1 : 4;
+ unsigned int gated_csp4 : 2;
+ unsigned int gated_csp5 : 2;
+ unsigned int gated_csp6 : 2;
+} reg_bif_core_rw_grp4_cfg;
+#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12
+#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12
+
+/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */
+typedef struct {
+ unsigned int bank_sel : 5;
+ unsigned int ca : 3;
+ unsigned int type : 1;
+ unsigned int bw : 1;
+ unsigned int sh : 3;
+ unsigned int wmm : 1;
+ unsigned int sh16 : 1;
+ unsigned int grp_sel : 5;
+ unsigned int dummy1 : 12;
+} reg_bif_core_rw_sdram_cfg_grp0;
+#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16
+#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16
+
+/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */
+typedef struct {
+ unsigned int bank_sel : 5;
+ unsigned int ca : 3;
+ unsigned int type : 1;
+ unsigned int bw : 1;
+ unsigned int sh : 3;
+ unsigned int wmm : 1;
+ unsigned int sh16 : 1;
+ unsigned int dummy1 : 17;
+} reg_bif_core_rw_sdram_cfg_grp1;
+#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20
+#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20
+
+/* Register rw_sdram_timing, scope bif_core, type rw */
+typedef struct {
+ unsigned int cl : 3;
+ unsigned int rcd : 3;
+ unsigned int rp : 3;
+ unsigned int rc : 2;
+ unsigned int dpl : 2;
+ unsigned int pde : 1;
+ unsigned int ref : 2;
+ unsigned int cpd : 1;
+ unsigned int sdcke : 1;
+ unsigned int sdclk : 1;
+ unsigned int dummy1 : 13;
+} reg_bif_core_rw_sdram_timing;
+#define REG_RD_ADDR_bif_core_rw_sdram_timing 24
+#define REG_WR_ADDR_bif_core_rw_sdram_timing 24
+
+/* Register rw_sdram_cmd, scope bif_core, type rw */
+typedef struct {
+ unsigned int cmd : 3;
+ unsigned int mrs_data : 15;
+ unsigned int dummy1 : 14;
+} reg_bif_core_rw_sdram_cmd;
+#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28
+#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28
+
+/* Register rs_sdram_ref_stat, scope bif_core, type rs */
+typedef struct {
+ unsigned int ok : 1;
+ unsigned int dummy1 : 31;
+} reg_bif_core_rs_sdram_ref_stat;
+#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32
+
+/* Register r_sdram_ref_stat, scope bif_core, type r */
+typedef struct {
+ unsigned int ok : 1;
+ unsigned int dummy1 : 31;
+} reg_bif_core_r_sdram_ref_stat;
+#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36
+
+
+/* Constants */
+enum {
+ regk_bif_core_bank2 = 0x00000000,
+ regk_bif_core_bank4 = 0x00000001,
+ regk_bif_core_bit10 = 0x0000000a,
+ regk_bif_core_bit11 = 0x0000000b,
+ regk_bif_core_bit12 = 0x0000000c,
+ regk_bif_core_bit13 = 0x0000000d,
+ regk_bif_core_bit14 = 0x0000000e,
+ regk_bif_core_bit15 = 0x0000000f,
+ regk_bif_core_bit16 = 0x00000010,
+ regk_bif_core_bit17 = 0x00000011,
+ regk_bif_core_bit18 = 0x00000012,
+ regk_bif_core_bit19 = 0x00000013,
+ regk_bif_core_bit20 = 0x00000014,
+ regk_bif_core_bit21 = 0x00000015,
+ regk_bif_core_bit22 = 0x00000016,
+ regk_bif_core_bit23 = 0x00000017,
+ regk_bif_core_bit24 = 0x00000018,
+ regk_bif_core_bit25 = 0x00000019,
+ regk_bif_core_bit26 = 0x0000001a,
+ regk_bif_core_bit27 = 0x0000001b,
+ regk_bif_core_bit28 = 0x0000001c,
+ regk_bif_core_bit29 = 0x0000001d,
+ regk_bif_core_bit9 = 0x00000009,
+ regk_bif_core_bw16 = 0x00000001,
+ regk_bif_core_bw32 = 0x00000000,
+ regk_bif_core_bwe = 0x00000000,
+ regk_bif_core_cwe = 0x00000001,
+ regk_bif_core_e15us = 0x00000001,
+ regk_bif_core_e7800ns = 0x00000002,
+ regk_bif_core_grp0 = 0x00000000,
+ regk_bif_core_grp1 = 0x00000001,
+ regk_bif_core_mrs = 0x00000003,
+ regk_bif_core_no = 0x00000000,
+ regk_bif_core_none = 0x00000000,
+ regk_bif_core_nop = 0x00000000,
+ regk_bif_core_off = 0x00000000,
+ regk_bif_core_pre = 0x00000002,
+ regk_bif_core_r_sdram_ref_stat_default = 0x00000001,
+ regk_bif_core_rd = 0x00000002,
+ regk_bif_core_ref = 0x00000001,
+ regk_bif_core_rs_sdram_ref_stat_default = 0x00000001,
+ regk_bif_core_rw_grp1_cfg_default = 0x000006cf,
+ regk_bif_core_rw_grp2_cfg_default = 0x000006cf,
+ regk_bif_core_rw_grp3_cfg_default = 0x000006cf,
+ regk_bif_core_rw_grp4_cfg_default = 0x000006cf,
+ regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000,
+ regk_bif_core_slf = 0x00000004,
+ regk_bif_core_wr = 0x00000001,
+ regk_bif_core_yes = 0x00000001
+};
+#endif /* __bif_core_defs_h */
--- /dev/null
+#ifndef __bif_dma_defs_h
+#define __bif_dma_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/bif/rtl/bif_dma_regs.r
+ * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp
+ * last modfied: Mon Apr 11 16:06:33 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r
+ * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope bif_dma */
+
+/* Register rw_ch0_ctrl, scope bif_dma, type rw */
+typedef struct {
+ unsigned int bw : 2;
+ unsigned int burst_len : 1;
+ unsigned int cont : 1;
+ unsigned int end_pad : 1;
+ unsigned int cnt : 1;
+ unsigned int dreq_pin : 3;
+ unsigned int dreq_mode : 2;
+ unsigned int tc_in_pin : 3;
+ unsigned int tc_in_mode : 2;
+ unsigned int bus_mode : 2;
+ unsigned int rate_en : 1;
+ unsigned int wr_all : 1;
+ unsigned int dummy1 : 12;
+} reg_bif_dma_rw_ch0_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0
+#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0
+
+/* Register rw_ch0_addr, scope bif_dma, type rw */
+typedef struct {
+ unsigned int addr : 32;
+} reg_bif_dma_rw_ch0_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4
+#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4
+
+/* Register rw_ch0_start, scope bif_dma, type rw */
+typedef struct {
+ unsigned int run : 1;
+ unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch0_start;
+#define REG_RD_ADDR_bif_dma_rw_ch0_start 8
+#define REG_WR_ADDR_bif_dma_rw_ch0_start 8
+
+/* Register rw_ch0_cnt, scope bif_dma, type rw */
+typedef struct {
+ unsigned int start_cnt : 16;
+ unsigned int dummy1 : 16;
+} reg_bif_dma_rw_ch0_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12
+#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12
+
+/* Register r_ch0_stat, scope bif_dma, type r */
+typedef struct {
+ unsigned int cnt : 16;
+ unsigned int dummy1 : 15;
+ unsigned int run : 1;
+} reg_bif_dma_r_ch0_stat;
+#define REG_RD_ADDR_bif_dma_r_ch0_stat 16
+
+/* Register rw_ch1_ctrl, scope bif_dma, type rw */
+typedef struct {
+ unsigned int bw : 2;
+ unsigned int burst_len : 1;
+ unsigned int cont : 1;
+ unsigned int end_discard : 1;
+ unsigned int cnt : 1;
+ unsigned int dreq_pin : 3;
+ unsigned int dreq_mode : 2;
+ unsigned int tc_in_pin : 3;
+ unsigned int tc_in_mode : 2;
+ unsigned int bus_mode : 2;
+ unsigned int rate_en : 1;
+ unsigned int dummy1 : 13;
+} reg_bif_dma_rw_ch1_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32
+#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32
+
+/* Register rw_ch1_addr, scope bif_dma, type rw */
+typedef struct {
+ unsigned int addr : 32;
+} reg_bif_dma_rw_ch1_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36
+#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36
+
+/* Register rw_ch1_start, scope bif_dma, type rw */
+typedef struct {
+ unsigned int run : 1;
+ unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch1_start;
+#define REG_RD_ADDR_bif_dma_rw_ch1_start 40
+#define REG_WR_ADDR_bif_dma_rw_ch1_start 40
+
+/* Register rw_ch1_cnt, scope bif_dma, type rw */
+typedef struct {
+ unsigned int start_cnt : 16;
+ unsigned int dummy1 : 16;
+} reg_bif_dma_rw_ch1_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44
+#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44
+
+/* Register r_ch1_stat, scope bif_dma, type r */
+typedef struct {
+ unsigned int cnt : 16;
+ unsigned int dummy1 : 15;
+ unsigned int run : 1;
+} reg_bif_dma_r_ch1_stat;
+#define REG_RD_ADDR_bif_dma_r_ch1_stat 48
+
+/* Register rw_ch2_ctrl, scope bif_dma, type rw */
+typedef struct {
+ unsigned int bw : 2;
+ unsigned int burst_len : 1;
+ unsigned int cont : 1;
+ unsigned int end_pad : 1;
+ unsigned int cnt : 1;
+ unsigned int dreq_pin : 3;
+ unsigned int dreq_mode : 2;
+ unsigned int tc_in_pin : 3;
+ unsigned int tc_in_mode : 2;
+ unsigned int bus_mode : 2;
+ unsigned int rate_en : 1;
+ unsigned int wr_all : 1;
+ unsigned int dummy1 : 12;
+} reg_bif_dma_rw_ch2_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64
+#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64
+
+/* Register rw_ch2_addr, scope bif_dma, type rw */
+typedef struct {
+ unsigned int addr : 32;
+} reg_bif_dma_rw_ch2_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68
+#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68
+
+/* Register rw_ch2_start, scope bif_dma, type rw */
+typedef struct {
+ unsigned int run : 1;
+ unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch2_start;
+#define REG_RD_ADDR_bif_dma_rw_ch2_start 72
+#define REG_WR_ADDR_bif_dma_rw_ch2_start 72
+
+/* Register rw_ch2_cnt, scope bif_dma, type rw */
+typedef struct {
+ unsigned int start_cnt : 16;
+ unsigned int dummy1 : 16;
+} reg_bif_dma_rw_ch2_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76
+#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76
+
+/* Register r_ch2_stat, scope bif_dma, type r */
+typedef struct {
+ unsigned int cnt : 16;
+ unsigned int dummy1 : 15;
+ unsigned int run : 1;
+} reg_bif_dma_r_ch2_stat;
+#define REG_RD_ADDR_bif_dma_r_ch2_stat 80
+
+/* Register rw_ch3_ctrl, scope bif_dma, type rw */
+typedef struct {
+ unsigned int bw : 2;
+ unsigned int burst_len : 1;
+ unsigned int cont : 1;
+ unsigned int end_discard : 1;
+ unsigned int cnt : 1;
+ unsigned int dreq_pin : 3;
+ unsigned int dreq_mode : 2;
+ unsigned int tc_in_pin : 3;
+ unsigned int tc_in_mode : 2;
+ unsigned int bus_mode : 2;
+ unsigned int rate_en : 1;
+ unsigned int dummy1 : 13;
+} reg_bif_dma_rw_ch3_ctrl;
+#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96
+#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96
+
+/* Register rw_ch3_addr, scope bif_dma, type rw */
+typedef struct {
+ unsigned int addr : 32;
+} reg_bif_dma_rw_ch3_addr;
+#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100
+#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100
+
+/* Register rw_ch3_start, scope bif_dma, type rw */
+typedef struct {
+ unsigned int run : 1;
+ unsigned int dummy1 : 31;
+} reg_bif_dma_rw_ch3_start;
+#define REG_RD_ADDR_bif_dma_rw_ch3_start 104
+#define REG_WR_ADDR_bif_dma_rw_ch3_start 104
+
+/* Register rw_ch3_cnt, scope bif_dma, type rw */
+typedef struct {
+ unsigned int start_cnt : 16;
+ unsigned int dummy1 : 16;
+} reg_bif_dma_rw_ch3_cnt;
+#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108
+#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108
+
+/* Register r_ch3_stat, scope bif_dma, type r */
+typedef struct {
+ unsigned int cnt : 16;
+ unsigned int dummy1 : 15;
+ unsigned int run : 1;
+} reg_bif_dma_r_ch3_stat;
+#define REG_RD_ADDR_bif_dma_r_ch3_stat 112
+
+/* Register rw_intr_mask, scope bif_dma, type rw */
+typedef struct {
+ unsigned int ext_dma0 : 1;
+ unsigned int ext_dma1 : 1;
+ unsigned int ext_dma2 : 1;
+ unsigned int ext_dma3 : 1;
+ unsigned int dummy1 : 28;
+} reg_bif_dma_rw_intr_mask;
+#define REG_RD_ADDR_bif_dma_rw_intr_mask 128
+#define REG_WR_ADDR_bif_dma_rw_intr_mask 128
+
+/* Register rw_ack_intr, scope bif_dma, type rw */
+typedef struct {
+ unsigned int ext_dma0 : 1;
+ unsigned int ext_dma1 : 1;
+ unsigned int ext_dma2 : 1;
+ unsigned int ext_dma3 : 1;
+ unsigned int dummy1 : 28;
+} reg_bif_dma_rw_ack_intr;
+#define REG_RD_ADDR_bif_dma_rw_ack_intr 132
+#define REG_WR_ADDR_bif_dma_rw_ack_intr 132
+
+/* Register r_intr, scope bif_dma, type r */
+typedef struct {
+ unsigned int ext_dma0 : 1;
+ unsigned int ext_dma1 : 1;
+ unsigned int ext_dma2 : 1;
+ unsigned int ext_dma3 : 1;
+ unsigned int dummy1 : 28;
+} reg_bif_dma_r_intr;
+#define REG_RD_ADDR_bif_dma_r_intr 136
+
+/* Register r_masked_intr, scope bif_dma, type r */
+typedef struct {
+ unsigned int ext_dma0 : 1;
+ unsigned int ext_dma1 : 1;
+ unsigned int ext_dma2 : 1;
+ unsigned int ext_dma3 : 1;
+ unsigned int dummy1 : 28;
+} reg_bif_dma_r_masked_intr;
+#define REG_RD_ADDR_bif_dma_r_masked_intr 140
+
+/* Register rw_pin0_cfg, scope bif_dma, type rw */
+typedef struct {
+ unsigned int master_ch : 2;
+ unsigned int master_mode : 3;
+ unsigned int slave_ch : 2;
+ unsigned int slave_mode : 3;
+ unsigned int dummy1 : 22;
+} reg_bif_dma_rw_pin0_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160
+#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160
+
+/* Register rw_pin1_cfg, scope bif_dma, type rw */
+typedef struct {
+ unsigned int master_ch : 2;
+ unsigned int master_mode : 3;
+ unsigned int slave_ch : 2;
+ unsigned int slave_mode : 3;
+ unsigned int dummy1 : 22;
+} reg_bif_dma_rw_pin1_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164
+#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164
+
+/* Register rw_pin2_cfg, scope bif_dma, type rw */
+typedef struct {
+ unsigned int master_ch : 2;
+ unsigned int master_mode : 3;
+ unsigned int slave_ch : 2;
+ unsigned int slave_mode : 3;
+ unsigned int dummy1 : 22;
+} reg_bif_dma_rw_pin2_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168
+#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168
+
+/* Register rw_pin3_cfg, scope bif_dma, type rw */
+typedef struct {
+ unsigned int master_ch : 2;
+ unsigned int master_mode : 3;
+ unsigned int slave_ch : 2;
+ unsigned int slave_mode : 3;
+ unsigned int dummy1 : 22;
+} reg_bif_dma_rw_pin3_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172
+#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172
+
+/* Register rw_pin4_cfg, scope bif_dma, type rw */
+typedef struct {
+ unsigned int master_ch : 2;
+ unsigned int master_mode : 3;
+ unsigned int slave_ch : 2;
+ unsigned int slave_mode : 3;
+ unsigned int dummy1 : 22;
+} reg_bif_dma_rw_pin4_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176
+#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176
+
+/* Register rw_pin5_cfg, scope bif_dma, type rw */
+typedef struct {
+ unsigned int master_ch : 2;
+ unsigned int master_mode : 3;
+ unsigned int slave_ch : 2;
+ unsigned int slave_mode : 3;
+ unsigned int dummy1 : 22;
+} reg_bif_dma_rw_pin5_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180
+#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180
+
+/* Register rw_pin6_cfg, scope bif_dma, type rw */
+typedef struct {
+ unsigned int master_ch : 2;
+ unsigned int master_mode : 3;
+ unsigned int slave_ch : 2;
+ unsigned int slave_mode : 3;
+ unsigned int dummy1 : 22;
+} reg_bif_dma_rw_pin6_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184
+#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184
+
+/* Register rw_pin7_cfg, scope bif_dma, type rw */
+typedef struct {
+ unsigned int master_ch : 2;
+ unsigned int master_mode : 3;
+ unsigned int slave_ch : 2;
+ unsigned int slave_mode : 3;
+ unsigned int dummy1 : 22;
+} reg_bif_dma_rw_pin7_cfg;
+#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188
+#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188
+
+/* Register r_pin_stat, scope bif_dma, type r */
+typedef struct {
+ unsigned int pin0 : 1;
+ unsigned int pin1 : 1;
+ unsigned int pin2 : 1;
+ unsigned int pin3 : 1;
+ unsigned int pin4 : 1;
+ unsigned int pin5 : 1;
+ unsigned int pin6 : 1;
+ unsigned int pin7 : 1;
+ unsigned int dummy1 : 24;
+} reg_bif_dma_r_pin_stat;
+#define REG_RD_ADDR_bif_dma_r_pin_stat 192
+
+
+/* Constants */
+enum {
+ regk_bif_dma_as_master = 0x00000001,
+ regk_bif_dma_as_slave = 0x00000001,
+ regk_bif_dma_burst1 = 0x00000000,
+ regk_bif_dma_burst8 = 0x00000001,
+ regk_bif_dma_bw16 = 0x00000001,
+ regk_bif_dma_bw32 = 0x00000002,
+ regk_bif_dma_bw8 = 0x00000000,
+ regk_bif_dma_dack = 0x00000006,
+ regk_bif_dma_dack_inv = 0x00000007,
+ regk_bif_dma_force = 0x00000001,
+ regk_bif_dma_hi = 0x00000003,
+ regk_bif_dma_inv = 0x00000003,
+ regk_bif_dma_lo = 0x00000002,
+ regk_bif_dma_master = 0x00000001,
+ regk_bif_dma_no = 0x00000000,
+ regk_bif_dma_norm = 0x00000002,
+ regk_bif_dma_off = 0x00000000,
+ regk_bif_dma_rw_ch0_ctrl_default = 0x00000000,
+ regk_bif_dma_rw_ch0_start_default = 0x00000000,
+ regk_bif_dma_rw_ch1_ctrl_default = 0x00000000,
+ regk_bif_dma_rw_ch1_start_default = 0x00000000,
+ regk_bif_dma_rw_ch2_ctrl_default = 0x00000000,
+ regk_bif_dma_rw_ch2_start_default = 0x00000000,
+ regk_bif_dma_rw_ch3_ctrl_default = 0x00000000,
+ regk_bif_dma_rw_ch3_start_default = 0x00000000,
+ regk_bif_dma_rw_intr_mask_default = 0x00000000,
+ regk_bif_dma_rw_pin0_cfg_default = 0x00000000,
+ regk_bif_dma_rw_pin1_cfg_default = 0x00000000,
+ regk_bif_dma_rw_pin2_cfg_default = 0x00000000,
+ regk_bif_dma_rw_pin3_cfg_default = 0x00000000,
+ regk_bif_dma_rw_pin4_cfg_default = 0x00000000,
+ regk_bif_dma_rw_pin5_cfg_default = 0x00000000,
+ regk_bif_dma_rw_pin6_cfg_default = 0x00000000,
+ regk_bif_dma_rw_pin7_cfg_default = 0x00000000,
+ regk_bif_dma_slave = 0x00000002,
+ regk_bif_dma_sreq = 0x00000006,
+ regk_bif_dma_sreq_inv = 0x00000007,
+ regk_bif_dma_tc = 0x00000004,
+ regk_bif_dma_tc_inv = 0x00000005,
+ regk_bif_dma_yes = 0x00000001
+};
+#endif /* __bif_dma_defs_h */
--- /dev/null
+#ifndef __bif_slave_defs_h
+#define __bif_slave_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/bif/rtl/bif_slave_regs.r
+ * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp
+ * last modfied: Mon Apr 11 16:06:34 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r
+ * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope bif_slave */
+
+/* Register rw_slave_cfg, scope bif_slave, type rw */
+typedef struct {
+ unsigned int slave_id : 3;
+ unsigned int use_slave_id : 1;
+ unsigned int boot_rdy : 1;
+ unsigned int loopback : 1;
+ unsigned int dis : 1;
+ unsigned int dummy1 : 25;
+} reg_bif_slave_rw_slave_cfg;
+#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0
+#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0
+
+/* Register r_slave_mode, scope bif_slave, type r */
+typedef struct {
+ unsigned int ch0_mode : 1;
+ unsigned int ch1_mode : 1;
+ unsigned int ch2_mode : 1;
+ unsigned int ch3_mode : 1;
+ unsigned int dummy1 : 28;
+} reg_bif_slave_r_slave_mode;
+#define REG_RD_ADDR_bif_slave_r_slave_mode 4
+
+/* Register rw_ch0_cfg, scope bif_slave, type rw */
+typedef struct {
+ unsigned int rd_hold : 2;
+ unsigned int access_mode : 1;
+ unsigned int access_ctrl : 1;
+ unsigned int data_cs : 2;
+ unsigned int dummy1 : 26;
+} reg_bif_slave_rw_ch0_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16
+#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16
+
+/* Register rw_ch1_cfg, scope bif_slave, type rw */
+typedef struct {
+ unsigned int rd_hold : 2;
+ unsigned int access_mode : 1;
+ unsigned int access_ctrl : 1;
+ unsigned int data_cs : 2;
+ unsigned int dummy1 : 26;
+} reg_bif_slave_rw_ch1_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20
+#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20
+
+/* Register rw_ch2_cfg, scope bif_slave, type rw */
+typedef struct {
+ unsigned int rd_hold : 2;
+ unsigned int access_mode : 1;
+ unsigned int access_ctrl : 1;
+ unsigned int data_cs : 2;
+ unsigned int dummy1 : 26;
+} reg_bif_slave_rw_ch2_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24
+#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24
+
+/* Register rw_ch3_cfg, scope bif_slave, type rw */
+typedef struct {
+ unsigned int rd_hold : 2;
+ unsigned int access_mode : 1;
+ unsigned int access_ctrl : 1;
+ unsigned int data_cs : 2;
+ unsigned int dummy1 : 26;
+} reg_bif_slave_rw_ch3_cfg;
+#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28
+#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28
+
+/* Register rw_arb_cfg, scope bif_slave, type rw */
+typedef struct {
+ unsigned int brin_mode : 1;
+ unsigned int brout_mode : 3;
+ unsigned int bg_mode : 3;
+ unsigned int release : 2;
+ unsigned int acquire : 1;
+ unsigned int settle_time : 2;
+ unsigned int dram_ctrl : 1;
+ unsigned int dummy1 : 19;
+} reg_bif_slave_rw_arb_cfg;
+#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32
+#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32
+
+/* Register r_arb_stat, scope bif_slave, type r */
+typedef struct {
+ unsigned int init_mode : 1;
+ unsigned int mode : 1;
+ unsigned int brin : 1;
+ unsigned int brout : 1;
+ unsigned int bg : 1;
+ unsigned int dummy1 : 27;
+} reg_bif_slave_r_arb_stat;
+#define REG_RD_ADDR_bif_slave_r_arb_stat 36
+
+/* Register rw_intr_mask, scope bif_slave, type rw */
+typedef struct {
+ unsigned int bus_release : 1;
+ unsigned int bus_acquire : 1;
+ unsigned int dummy1 : 30;
+} reg_bif_slave_rw_intr_mask;
+#define REG_RD_ADDR_bif_slave_rw_intr_mask 64
+#define REG_WR_ADDR_bif_slave_rw_intr_mask 64
+
+/* Register rw_ack_intr, scope bif_slave, type rw */
+typedef struct {
+ unsigned int bus_release : 1;
+ unsigned int bus_acquire : 1;
+ unsigned int dummy1 : 30;
+} reg_bif_slave_rw_ack_intr;
+#define REG_RD_ADDR_bif_slave_rw_ack_intr 68
+#define REG_WR_ADDR_bif_slave_rw_ack_intr 68
+
+/* Register r_intr, scope bif_slave, type r */
+typedef struct {
+ unsigned int bus_release : 1;
+ unsigned int bus_acquire : 1;
+ unsigned int dummy1 : 30;
+} reg_bif_slave_r_intr;
+#define REG_RD_ADDR_bif_slave_r_intr 72
+
+/* Register r_masked_intr, scope bif_slave, type r */
+typedef struct {
+ unsigned int bus_release : 1;
+ unsigned int bus_acquire : 1;
+ unsigned int dummy1 : 30;
+} reg_bif_slave_r_masked_intr;
+#define REG_RD_ADDR_bif_slave_r_masked_intr 76
+
+
+/* Constants */
+enum {
+ regk_bif_slave_active_hi = 0x00000003,
+ regk_bif_slave_active_lo = 0x00000002,
+ regk_bif_slave_addr = 0x00000000,
+ regk_bif_slave_always = 0x00000001,
+ regk_bif_slave_at_idle = 0x00000002,
+ regk_bif_slave_burst_end = 0x00000003,
+ regk_bif_slave_dma = 0x00000001,
+ regk_bif_slave_hi = 0x00000003,
+ regk_bif_slave_inv = 0x00000001,
+ regk_bif_slave_lo = 0x00000002,
+ regk_bif_slave_local = 0x00000001,
+ regk_bif_slave_master = 0x00000000,
+ regk_bif_slave_mode_reg = 0x00000001,
+ regk_bif_slave_no = 0x00000000,
+ regk_bif_slave_norm = 0x00000000,
+ regk_bif_slave_on_access = 0x00000000,
+ regk_bif_slave_rw_arb_cfg_default = 0x00000000,
+ regk_bif_slave_rw_ch0_cfg_default = 0x00000000,
+ regk_bif_slave_rw_ch1_cfg_default = 0x00000000,
+ regk_bif_slave_rw_ch2_cfg_default = 0x00000000,
+ regk_bif_slave_rw_ch3_cfg_default = 0x00000000,
+ regk_bif_slave_rw_intr_mask_default = 0x00000000,
+ regk_bif_slave_rw_slave_cfg_default = 0x00000000,
+ regk_bif_slave_shared = 0x00000000,
+ regk_bif_slave_slave = 0x00000001,
+ regk_bif_slave_t0ns = 0x00000003,
+ regk_bif_slave_t10ns = 0x00000002,
+ regk_bif_slave_t20ns = 0x00000003,
+ regk_bif_slave_t30ns = 0x00000002,
+ regk_bif_slave_t40ns = 0x00000001,
+ regk_bif_slave_t50ns = 0x00000000,
+ regk_bif_slave_yes = 0x00000001,
+ regk_bif_slave_z = 0x00000004
+};
+#endif /* __bif_slave_defs_h */
--- /dev/null
+#ifndef __config_defs_h
+#define __config_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../rtl/config_regs.r
+ * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp
+ * last modfied: Thu Mar 4 12:34:39 2004
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r
+ * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope config */
+
+/* Register r_bootsel, scope config, type r */
+typedef struct {
+ unsigned int boot_mode : 3;
+ unsigned int full_duplex : 1;
+ unsigned int user : 1;
+ unsigned int pll : 1;
+ unsigned int flash_bw : 1;
+ unsigned int dummy1 : 25;
+} reg_config_r_bootsel;
+#define REG_RD_ADDR_config_r_bootsel 0
+
+/* Register rw_clk_ctrl, scope config, type rw */
+typedef struct {
+ unsigned int pll : 1;
+ unsigned int cpu : 1;
+ unsigned int iop : 1;
+ unsigned int dma01_eth0 : 1;
+ unsigned int dma23 : 1;
+ unsigned int dma45 : 1;
+ unsigned int dma67 : 1;
+ unsigned int dma89_strcop : 1;
+ unsigned int bif : 1;
+ unsigned int fix_io : 1;
+ unsigned int dummy1 : 22;
+} reg_config_rw_clk_ctrl;
+#define REG_RD_ADDR_config_rw_clk_ctrl 4
+#define REG_WR_ADDR_config_rw_clk_ctrl 4
+
+/* Register rw_pad_ctrl, scope config, type rw */
+typedef struct {
+ unsigned int usb_susp : 1;
+ unsigned int phyrst_n : 1;
+ unsigned int dummy1 : 30;
+} reg_config_rw_pad_ctrl;
+#define REG_RD_ADDR_config_rw_pad_ctrl 8
+#define REG_WR_ADDR_config_rw_pad_ctrl 8
+
+
+/* Constants */
+enum {
+ regk_config_bw16 = 0x00000000,
+ regk_config_bw32 = 0x00000001,
+ regk_config_master = 0x00000005,
+ regk_config_nand = 0x00000003,
+ regk_config_net_rx = 0x00000001,
+ regk_config_net_tx_rx = 0x00000002,
+ regk_config_no = 0x00000000,
+ regk_config_none = 0x00000007,
+ regk_config_nor = 0x00000000,
+ regk_config_rw_clk_ctrl_default = 0x00000002,
+ regk_config_rw_pad_ctrl_default = 0x00000000,
+ regk_config_ser = 0x00000004,
+ regk_config_slave = 0x00000006,
+ regk_config_yes = 0x00000001
+};
+#endif /* __config_defs_h */
--- /dev/null
+#ifndef __gio_defs_h
+#define __gio_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/gio/rtl/gio_regs.r
+ * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp
+ * last modfied: Mon Apr 11 16:07:47 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r
+ * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope gio */
+
+/* Register rw_pa_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pa_dout;
+#define REG_RD_ADDR_gio_rw_pa_dout 0
+#define REG_WR_ADDR_gio_rw_pa_dout 0
+
+/* Register r_pa_din, scope gio, type r */
+typedef struct {
+ unsigned int data : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_r_pa_din;
+#define REG_RD_ADDR_gio_r_pa_din 4
+
+/* Register rw_pa_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 8;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_pa_oe;
+#define REG_RD_ADDR_gio_rw_pa_oe 8
+#define REG_WR_ADDR_gio_rw_pa_oe 8
+
+/* Register rw_intr_cfg, scope gio, type rw */
+typedef struct {
+ unsigned int pa0 : 3;
+ unsigned int pa1 : 3;
+ unsigned int pa2 : 3;
+ unsigned int pa3 : 3;
+ unsigned int pa4 : 3;
+ unsigned int pa5 : 3;
+ unsigned int pa6 : 3;
+ unsigned int pa7 : 3;
+ unsigned int dummy1 : 8;
+} reg_gio_rw_intr_cfg;
+#define REG_RD_ADDR_gio_rw_intr_cfg 12
+#define REG_WR_ADDR_gio_rw_intr_cfg 12
+
+/* Register rw_intr_mask, scope gio, type rw */
+typedef struct {
+ unsigned int pa0 : 1;
+ unsigned int pa1 : 1;
+ unsigned int pa2 : 1;
+ unsigned int pa3 : 1;
+ unsigned int pa4 : 1;
+ unsigned int pa5 : 1;
+ unsigned int pa6 : 1;
+ unsigned int pa7 : 1;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_intr_mask;
+#define REG_RD_ADDR_gio_rw_intr_mask 16
+#define REG_WR_ADDR_gio_rw_intr_mask 16
+
+/* Register rw_ack_intr, scope gio, type rw */
+typedef struct {
+ unsigned int pa0 : 1;
+ unsigned int pa1 : 1;
+ unsigned int pa2 : 1;
+ unsigned int pa3 : 1;
+ unsigned int pa4 : 1;
+ unsigned int pa5 : 1;
+ unsigned int pa6 : 1;
+ unsigned int pa7 : 1;
+ unsigned int dummy1 : 24;
+} reg_gio_rw_ack_intr;
+#define REG_RD_ADDR_gio_rw_ack_intr 20
+#define REG_WR_ADDR_gio_rw_ack_intr 20
+
+/* Register r_intr, scope gio, type r */
+typedef struct {
+ unsigned int pa0 : 1;
+ unsigned int pa1 : 1;
+ unsigned int pa2 : 1;
+ unsigned int pa3 : 1;
+ unsigned int pa4 : 1;
+ unsigned int pa5 : 1;
+ unsigned int pa6 : 1;
+ unsigned int pa7 : 1;
+ unsigned int dummy1 : 24;
+} reg_gio_r_intr;
+#define REG_RD_ADDR_gio_r_intr 24
+
+/* Register r_masked_intr, scope gio, type r */
+typedef struct {
+ unsigned int pa0 : 1;
+ unsigned int pa1 : 1;
+ unsigned int pa2 : 1;
+ unsigned int pa3 : 1;
+ unsigned int pa4 : 1;
+ unsigned int pa5 : 1;
+ unsigned int pa6 : 1;
+ unsigned int pa7 : 1;
+ unsigned int dummy1 : 24;
+} reg_gio_r_masked_intr;
+#define REG_RD_ADDR_gio_r_masked_intr 28
+
+/* Register rw_pb_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_rw_pb_dout;
+#define REG_RD_ADDR_gio_rw_pb_dout 32
+#define REG_WR_ADDR_gio_rw_pb_dout 32
+
+/* Register r_pb_din, scope gio, type r */
+typedef struct {
+ unsigned int data : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_r_pb_din;
+#define REG_RD_ADDR_gio_r_pb_din 36
+
+/* Register rw_pb_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_rw_pb_oe;
+#define REG_RD_ADDR_gio_rw_pb_oe 40
+#define REG_WR_ADDR_gio_rw_pb_oe 40
+
+/* Register rw_pc_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_rw_pc_dout;
+#define REG_RD_ADDR_gio_rw_pc_dout 48
+#define REG_WR_ADDR_gio_rw_pc_dout 48
+
+/* Register r_pc_din, scope gio, type r */
+typedef struct {
+ unsigned int data : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_r_pc_din;
+#define REG_RD_ADDR_gio_r_pc_din 52
+
+/* Register rw_pc_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_rw_pc_oe;
+#define REG_RD_ADDR_gio_rw_pc_oe 56
+#define REG_WR_ADDR_gio_rw_pc_oe 56
+
+/* Register rw_pd_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_rw_pd_dout;
+#define REG_RD_ADDR_gio_rw_pd_dout 64
+#define REG_WR_ADDR_gio_rw_pd_dout 64
+
+/* Register r_pd_din, scope gio, type r */
+typedef struct {
+ unsigned int data : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_r_pd_din;
+#define REG_RD_ADDR_gio_r_pd_din 68
+
+/* Register rw_pd_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_rw_pd_oe;
+#define REG_RD_ADDR_gio_rw_pd_oe 72
+#define REG_WR_ADDR_gio_rw_pd_oe 72
+
+/* Register rw_pe_dout, scope gio, type rw */
+typedef struct {
+ unsigned int data : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_rw_pe_dout;
+#define REG_RD_ADDR_gio_rw_pe_dout 80
+#define REG_WR_ADDR_gio_rw_pe_dout 80
+
+/* Register r_pe_din, scope gio, type r */
+typedef struct {
+ unsigned int data : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_r_pe_din;
+#define REG_RD_ADDR_gio_r_pe_din 84
+
+/* Register rw_pe_oe, scope gio, type rw */
+typedef struct {
+ unsigned int oe : 18;
+ unsigned int dummy1 : 14;
+} reg_gio_rw_pe_oe;
+#define REG_RD_ADDR_gio_rw_pe_oe 88
+#define REG_WR_ADDR_gio_rw_pe_oe 88
+
+
+/* Constants */
+enum {
+ regk_gio_anyedge = 0x00000007,
+ regk_gio_hi = 0x00000001,
+ regk_gio_lo = 0x00000002,
+ regk_gio_negedge = 0x00000006,
+ regk_gio_no = 0x00000000,
+ regk_gio_off = 0x00000000,
+ regk_gio_posedge = 0x00000005,
+ regk_gio_rw_intr_cfg_default = 0x00000000,
+ regk_gio_rw_intr_mask_default = 0x00000000,
+ regk_gio_rw_pa_oe_default = 0x00000000,
+ regk_gio_rw_pb_oe_default = 0x00000000,
+ regk_gio_rw_pc_oe_default = 0x00000000,
+ regk_gio_rw_pd_oe_default = 0x00000000,
+ regk_gio_rw_pe_oe_default = 0x00000000,
+ regk_gio_set = 0x00000003,
+ regk_gio_yes = 0x00000001
+};
+#endif /* __gio_defs_h */
--- /dev/null
+/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version
+ from ../../inst/intr_vect/rtl/guinness/ivmask.config.r
+version . */
+
+#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
+#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R
+#define MEMARB_INTR_VECT 0x31
+#define GEN_IO_INTR_VECT 0x32
+#define GIO_INTR_VECT GEN_IO_INTR_VECT
+#define IOP0_INTR_VECT 0x33
+#define IOP1_INTR_VECT 0x34
+#define IOP2_INTR_VECT 0x35
+#define IOP3_INTR_VECT 0x36
+#define DMA0_INTR_VECT 0x37
+#define DMA1_INTR_VECT 0x38
+#define DMA2_INTR_VECT 0x39
+#define DMA3_INTR_VECT 0x3a
+#define DMA4_INTR_VECT 0x3b
+#define DMA5_INTR_VECT 0x3c
+#define DMA6_INTR_VECT 0x3d
+#define DMA7_INTR_VECT 0x3e
+#define DMA8_INTR_VECT 0x3f
+#define DMA9_INTR_VECT 0x40
+#define ATA_INTR_VECT 0x41
+#define SSER0_INTR_VECT 0x42
+#define SSER1_INTR_VECT 0x43
+#define SER0_INTR_VECT 0x44
+#define SER1_INTR_VECT 0x45
+#define SER2_INTR_VECT 0x46
+#define SER3_INTR_VECT 0x47
+#define P21_INTR_VECT 0x48
+#define ETH0_INTR_VECT 0x49
+#define ETH1_INTR_VECT 0x4a
+#define TIMER_INTR_VECT 0x4b
+#define TIMER0_INTR_VECT TIMER_INTR_VECT
+#define BIF_ARB_INTR_VECT 0x4c
+#define BIF_DMA_INTR_VECT 0x4d
+#define EXT_INTR_VECT 0x4e
+#define IPI_INTR_VECT 0x4f
+#define NBR_INTR_VECT 0x50
+#endif
/*
* This file is autogenerated from
* file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
+ * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
* last modfied: Mon Apr 11 16:08:03 2005
- *
+ *
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
- * id: $Id: intr_vect_defs.h,v 1.8 2005/04/24 18:30:58 starvik Exp $
+ * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
/* C-code for register scope intr_vect */
+#define STRIDE_intr_vect_rw_mask 0
/* Register rw_mask, scope intr_vect, type rw */
typedef struct {
unsigned int memarb : 1;
unsigned int p21 : 1;
unsigned int eth0 : 1;
unsigned int eth1 : 1;
- unsigned int timer : 1;
+ unsigned int timer0 : 1;
unsigned int bif_arb : 1;
unsigned int bif_dma : 1;
unsigned int ext : 1;
#define REG_RD_ADDR_intr_vect_rw_mask 0
#define REG_WR_ADDR_intr_vect_rw_mask 0
+#define STRIDE_intr_vect_r_vect 0
/* Register r_vect, scope intr_vect, type r */
typedef struct {
unsigned int memarb : 1;
} reg_intr_vect_r_vect;
#define REG_RD_ADDR_intr_vect_r_vect 4
+#define STRIDE_intr_vect_r_masked_vect 0
/* Register r_masked_vect, scope intr_vect, type r */
typedef struct {
unsigned int memarb : 1;
#define REG_RD_ADDR_intr_vect_r_guru 16
/* Register rw_ipi, scope intr_vect, type rw */
-typedef struct
+typedef struct
{
unsigned int vector;
} reg_intr_vect_rw_ipi;
--- /dev/null
+#ifndef __marb_bp_defs_h
+#define __marb_bp_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/memarb/rtl/guinness/marb_top.r
+ * id: <not found>
+ * last modfied: Fri Nov 7 15:36:04 2003
+ *
+ * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r
+ * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+/* C-code for register scope marb_bp */
+
+/* Register rw_first_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_first_addr;
+#define REG_RD_ADDR_marb_bp_rw_first_addr 0
+#define REG_WR_ADDR_marb_bp_rw_first_addr 0
+
+/* Register rw_last_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_last_addr;
+#define REG_RD_ADDR_marb_bp_rw_last_addr 4
+#define REG_WR_ADDR_marb_bp_rw_last_addr 4
+
+/* Register rw_op, scope marb_bp, type rw */
+typedef struct {
+ unsigned int read : 1;
+ unsigned int write : 1;
+ unsigned int read_excl : 1;
+ unsigned int pri_write : 1;
+ unsigned int us_read : 1;
+ unsigned int us_write : 1;
+ unsigned int us_read_excl : 1;
+ unsigned int us_pri_write : 1;
+ unsigned int dummy1 : 24;
+} reg_marb_bp_rw_op;
+#define REG_RD_ADDR_marb_bp_rw_op 8
+#define REG_WR_ADDR_marb_bp_rw_op 8
+
+/* Register rw_clients, scope marb_bp, type rw */
+typedef struct {
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma8 : 1;
+ unsigned int dma9 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int slave : 1;
+ unsigned int dummy1 : 18;
+} reg_marb_bp_rw_clients;
+#define REG_RD_ADDR_marb_bp_rw_clients 12
+#define REG_WR_ADDR_marb_bp_rw_clients 12
+
+/* Register rw_options, scope marb_bp, type rw */
+typedef struct {
+ unsigned int wrap : 1;
+ unsigned int dummy1 : 31;
+} reg_marb_bp_rw_options;
+#define REG_RD_ADDR_marb_bp_rw_options 16
+#define REG_WR_ADDR_marb_bp_rw_options 16
+
+/* Register r_break_addr, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_break_addr;
+#define REG_RD_ADDR_marb_bp_r_break_addr 20
+
+/* Register r_break_op, scope marb_bp, type r */
+typedef struct {
+ unsigned int read : 1;
+ unsigned int write : 1;
+ unsigned int read_excl : 1;
+ unsigned int pri_write : 1;
+ unsigned int us_read : 1;
+ unsigned int us_write : 1;
+ unsigned int us_read_excl : 1;
+ unsigned int us_pri_write : 1;
+ unsigned int dummy1 : 24;
+} reg_marb_bp_r_break_op;
+#define REG_RD_ADDR_marb_bp_r_break_op 24
+
+/* Register r_break_clients, scope marb_bp, type r */
+typedef struct {
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma8 : 1;
+ unsigned int dma9 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int slave : 1;
+ unsigned int dummy1 : 18;
+} reg_marb_bp_r_break_clients;
+#define REG_RD_ADDR_marb_bp_r_break_clients 28
+
+/* Register r_break_first_client, scope marb_bp, type r */
+typedef struct {
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma8 : 1;
+ unsigned int dma9 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int slave : 1;
+ unsigned int dummy1 : 18;
+} reg_marb_bp_r_break_first_client;
+#define REG_RD_ADDR_marb_bp_r_break_first_client 32
+
+/* Register r_break_size, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_break_size;
+#define REG_RD_ADDR_marb_bp_r_break_size 36
+
+/* Register rw_ack, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_ack;
+#define REG_RD_ADDR_marb_bp_rw_ack 40
+#define REG_WR_ADDR_marb_bp_rw_ack 40
+
+
+/* Constants */
+enum {
+ regk_marb_bp_no = 0x00000000,
+ regk_marb_bp_rw_op_default = 0x00000000,
+ regk_marb_bp_rw_options_default = 0x00000000,
+ regk_marb_bp_yes = 0x00000001
+};
+#endif /* __marb_bp_defs_h */
--- /dev/null
+#ifndef __marb_defs_h
+#define __marb_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/memarb/rtl/guinness/marb_top.r
+ * id: <not found>
+ * last modfied: Mon Apr 11 16:12:16 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
+ * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope marb */
+
+#define STRIDE_marb_rw_int_slots 4
+/* Register rw_int_slots, scope marb, type rw */
+typedef struct {
+ unsigned int owner : 4;
+ unsigned int dummy1 : 28;
+} reg_marb_rw_int_slots;
+#define REG_RD_ADDR_marb_rw_int_slots 0
+#define REG_WR_ADDR_marb_rw_int_slots 0
+
+#define STRIDE_marb_rw_ext_slots 4
+/* Register rw_ext_slots, scope marb, type rw */
+typedef struct {
+ unsigned int owner : 4;
+ unsigned int dummy1 : 28;
+} reg_marb_rw_ext_slots;
+#define REG_RD_ADDR_marb_rw_ext_slots 256
+#define REG_WR_ADDR_marb_rw_ext_slots 256
+
+#define STRIDE_marb_rw_regs_slots 4
+/* Register rw_regs_slots, scope marb, type rw */
+typedef struct {
+ unsigned int owner : 4;
+ unsigned int dummy1 : 28;
+} reg_marb_rw_regs_slots;
+#define REG_RD_ADDR_marb_rw_regs_slots 512
+#define REG_WR_ADDR_marb_rw_regs_slots 512
+
+/* Register rw_intr_mask, scope marb, type rw */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_rw_intr_mask;
+#define REG_RD_ADDR_marb_rw_intr_mask 528
+#define REG_WR_ADDR_marb_rw_intr_mask 528
+
+/* Register rw_ack_intr, scope marb, type rw */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_rw_ack_intr;
+#define REG_RD_ADDR_marb_rw_ack_intr 532
+#define REG_WR_ADDR_marb_rw_ack_intr 532
+
+/* Register r_intr, scope marb, type r */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_r_intr;
+#define REG_RD_ADDR_marb_r_intr 536
+
+/* Register r_masked_intr, scope marb, type r */
+typedef struct {
+ unsigned int bp0 : 1;
+ unsigned int bp1 : 1;
+ unsigned int bp2 : 1;
+ unsigned int bp3 : 1;
+ unsigned int dummy1 : 28;
+} reg_marb_r_masked_intr;
+#define REG_RD_ADDR_marb_r_masked_intr 540
+
+/* Register rw_stop_mask, scope marb, type rw */
+typedef struct {
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma8 : 1;
+ unsigned int dma9 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int slave : 1;
+ unsigned int dummy1 : 18;
+} reg_marb_rw_stop_mask;
+#define REG_RD_ADDR_marb_rw_stop_mask 544
+#define REG_WR_ADDR_marb_rw_stop_mask 544
+
+/* Register r_stopped, scope marb, type r */
+typedef struct {
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma8 : 1;
+ unsigned int dma9 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int slave : 1;
+ unsigned int dummy1 : 18;
+} reg_marb_r_stopped;
+#define REG_RD_ADDR_marb_r_stopped 548
+
+/* Register rw_no_snoop, scope marb, type rw */
+typedef struct {
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma8 : 1;
+ unsigned int dma9 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int slave : 1;
+ unsigned int dummy1 : 18;
+} reg_marb_rw_no_snoop;
+#define REG_RD_ADDR_marb_rw_no_snoop 832
+#define REG_WR_ADDR_marb_rw_no_snoop 832
+
+/* Register rw_no_snoop_rq, scope marb, type rw */
+typedef struct {
+ unsigned int dummy1 : 10;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int dummy2 : 20;
+} reg_marb_rw_no_snoop_rq;
+#define REG_RD_ADDR_marb_rw_no_snoop_rq 836
+#define REG_WR_ADDR_marb_rw_no_snoop_rq 836
+
+
+/* Constants */
+enum {
+ regk_marb_cpud = 0x0000000b,
+ regk_marb_cpui = 0x0000000a,
+ regk_marb_dma0 = 0x00000000,
+ regk_marb_dma1 = 0x00000001,
+ regk_marb_dma2 = 0x00000002,
+ regk_marb_dma3 = 0x00000003,
+ regk_marb_dma4 = 0x00000004,
+ regk_marb_dma5 = 0x00000005,
+ regk_marb_dma6 = 0x00000006,
+ regk_marb_dma7 = 0x00000007,
+ regk_marb_dma8 = 0x00000008,
+ regk_marb_dma9 = 0x00000009,
+ regk_marb_iop = 0x0000000c,
+ regk_marb_no = 0x00000000,
+ regk_marb_r_stopped_default = 0x00000000,
+ regk_marb_rw_ext_slots_default = 0x00000000,
+ regk_marb_rw_ext_slots_size = 0x00000040,
+ regk_marb_rw_int_slots_default = 0x00000000,
+ regk_marb_rw_int_slots_size = 0x00000040,
+ regk_marb_rw_intr_mask_default = 0x00000000,
+ regk_marb_rw_no_snoop_default = 0x00000000,
+ regk_marb_rw_no_snoop_rq_default = 0x00000000,
+ regk_marb_rw_regs_slots_default = 0x00000000,
+ regk_marb_rw_regs_slots_size = 0x00000004,
+ regk_marb_rw_stop_mask_default = 0x00000000,
+ regk_marb_slave = 0x0000000d,
+ regk_marb_yes = 0x00000001
+};
+#endif /* __marb_defs_h */
+#ifndef __marb_bp_defs_h
+#define __marb_bp_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/memarb/rtl/guinness/marb_top.r
+ * id: <not found>
+ * last modfied: Mon Apr 11 16:12:16 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r
+ * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope marb_bp */
+
+/* Register rw_first_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_first_addr;
+#define REG_RD_ADDR_marb_bp_rw_first_addr 0
+#define REG_WR_ADDR_marb_bp_rw_first_addr 0
+
+/* Register rw_last_addr, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_last_addr;
+#define REG_RD_ADDR_marb_bp_rw_last_addr 4
+#define REG_WR_ADDR_marb_bp_rw_last_addr 4
+
+/* Register rw_op, scope marb_bp, type rw */
+typedef struct {
+ unsigned int rd : 1;
+ unsigned int wr : 1;
+ unsigned int rd_excl : 1;
+ unsigned int pri_wr : 1;
+ unsigned int us_rd : 1;
+ unsigned int us_wr : 1;
+ unsigned int us_rd_excl : 1;
+ unsigned int us_pri_wr : 1;
+ unsigned int dummy1 : 24;
+} reg_marb_bp_rw_op;
+#define REG_RD_ADDR_marb_bp_rw_op 8
+#define REG_WR_ADDR_marb_bp_rw_op 8
+
+/* Register rw_clients, scope marb_bp, type rw */
+typedef struct {
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma8 : 1;
+ unsigned int dma9 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int slave : 1;
+ unsigned int dummy1 : 18;
+} reg_marb_bp_rw_clients;
+#define REG_RD_ADDR_marb_bp_rw_clients 12
+#define REG_WR_ADDR_marb_bp_rw_clients 12
+
+/* Register rw_options, scope marb_bp, type rw */
+typedef struct {
+ unsigned int wrap : 1;
+ unsigned int dummy1 : 31;
+} reg_marb_bp_rw_options;
+#define REG_RD_ADDR_marb_bp_rw_options 16
+#define REG_WR_ADDR_marb_bp_rw_options 16
+
+/* Register r_brk_addr, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_brk_addr;
+#define REG_RD_ADDR_marb_bp_r_brk_addr 20
+
+/* Register r_brk_op, scope marb_bp, type r */
+typedef struct {
+ unsigned int rd : 1;
+ unsigned int wr : 1;
+ unsigned int rd_excl : 1;
+ unsigned int pri_wr : 1;
+ unsigned int us_rd : 1;
+ unsigned int us_wr : 1;
+ unsigned int us_rd_excl : 1;
+ unsigned int us_pri_wr : 1;
+ unsigned int dummy1 : 24;
+} reg_marb_bp_r_brk_op;
+#define REG_RD_ADDR_marb_bp_r_brk_op 24
+
+/* Register r_brk_clients, scope marb_bp, type r */
+typedef struct {
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma8 : 1;
+ unsigned int dma9 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int slave : 1;
+ unsigned int dummy1 : 18;
+} reg_marb_bp_r_brk_clients;
+#define REG_RD_ADDR_marb_bp_r_brk_clients 28
+
+/* Register r_brk_first_client, scope marb_bp, type r */
+typedef struct {
+ unsigned int dma0 : 1;
+ unsigned int dma1 : 1;
+ unsigned int dma2 : 1;
+ unsigned int dma3 : 1;
+ unsigned int dma4 : 1;
+ unsigned int dma5 : 1;
+ unsigned int dma6 : 1;
+ unsigned int dma7 : 1;
+ unsigned int dma8 : 1;
+ unsigned int dma9 : 1;
+ unsigned int cpui : 1;
+ unsigned int cpud : 1;
+ unsigned int iop : 1;
+ unsigned int slave : 1;
+ unsigned int dummy1 : 18;
+} reg_marb_bp_r_brk_first_client;
+#define REG_RD_ADDR_marb_bp_r_brk_first_client 32
+
+/* Register r_brk_size, scope marb_bp, type r */
+typedef unsigned int reg_marb_bp_r_brk_size;
+#define REG_RD_ADDR_marb_bp_r_brk_size 36
+
+/* Register rw_ack, scope marb_bp, type rw */
+typedef unsigned int reg_marb_bp_rw_ack;
+#define REG_RD_ADDR_marb_bp_rw_ack 40
+#define REG_WR_ADDR_marb_bp_rw_ack 40
+
+
+/* Constants */
+enum {
+ regk_marb_bp_no = 0x00000000,
+ regk_marb_bp_rw_op_default = 0x00000000,
+ regk_marb_bp_rw_options_default = 0x00000000,
+ regk_marb_bp_yes = 0x00000001
+};
+#endif /* __marb_bp_defs_h */
--- /dev/null
+#ifndef __pinmux_defs_h
+#define __pinmux_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp
+ * last modfied: Mon Apr 11 16:09:11 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r
+ * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope pinmux */
+
+/* Register rw_pa, scope pinmux, type rw */
+typedef struct {
+ unsigned int pa0 : 1;
+ unsigned int pa1 : 1;
+ unsigned int pa2 : 1;
+ unsigned int pa3 : 1;
+ unsigned int pa4 : 1;
+ unsigned int pa5 : 1;
+ unsigned int pa6 : 1;
+ unsigned int pa7 : 1;
+ unsigned int csp2_n : 1;
+ unsigned int csp3_n : 1;
+ unsigned int csp5_n : 1;
+ unsigned int csp6_n : 1;
+ unsigned int hsh4 : 1;
+ unsigned int hsh5 : 1;
+ unsigned int hsh6 : 1;
+ unsigned int hsh7 : 1;
+ unsigned int dummy1 : 16;
+} reg_pinmux_rw_pa;
+#define REG_RD_ADDR_pinmux_rw_pa 0
+#define REG_WR_ADDR_pinmux_rw_pa 0
+
+/* Register rw_hwprot, scope pinmux, type rw */
+typedef struct {
+ unsigned int ser1 : 1;
+ unsigned int ser2 : 1;
+ unsigned int ser3 : 1;
+ unsigned int sser0 : 1;
+ unsigned int sser1 : 1;
+ unsigned int ata0 : 1;
+ unsigned int ata1 : 1;
+ unsigned int ata2 : 1;
+ unsigned int ata3 : 1;
+ unsigned int ata : 1;
+ unsigned int eth1 : 1;
+ unsigned int eth1_mgm : 1;
+ unsigned int timer : 1;
+ unsigned int p21 : 1;
+ unsigned int dummy1 : 18;
+} reg_pinmux_rw_hwprot;
+#define REG_RD_ADDR_pinmux_rw_hwprot 4
+#define REG_WR_ADDR_pinmux_rw_hwprot 4
+
+/* Register rw_pb_gio, scope pinmux, type rw */
+typedef struct {
+ unsigned int pb0 : 1;
+ unsigned int pb1 : 1;
+ unsigned int pb2 : 1;
+ unsigned int pb3 : 1;
+ unsigned int pb4 : 1;
+ unsigned int pb5 : 1;
+ unsigned int pb6 : 1;
+ unsigned int pb7 : 1;
+ unsigned int pb8 : 1;
+ unsigned int pb9 : 1;
+ unsigned int pb10 : 1;
+ unsigned int pb11 : 1;
+ unsigned int pb12 : 1;
+ unsigned int pb13 : 1;
+ unsigned int pb14 : 1;
+ unsigned int pb15 : 1;
+ unsigned int pb16 : 1;
+ unsigned int pb17 : 1;
+ unsigned int dummy1 : 14;
+} reg_pinmux_rw_pb_gio;
+#define REG_RD_ADDR_pinmux_rw_pb_gio 8
+#define REG_WR_ADDR_pinmux_rw_pb_gio 8
+
+/* Register rw_pb_iop, scope pinmux, type rw */
+typedef struct {
+ unsigned int pb0 : 1;
+ unsigned int pb1 : 1;
+ unsigned int pb2 : 1;
+ unsigned int pb3 : 1;
+ unsigned int pb4 : 1;
+ unsigned int pb5 : 1;
+ unsigned int pb6 : 1;
+ unsigned int pb7 : 1;
+ unsigned int pb8 : 1;
+ unsigned int pb9 : 1;
+ unsigned int pb10 : 1;
+ unsigned int pb11 : 1;
+ unsigned int pb12 : 1;
+ unsigned int pb13 : 1;
+ unsigned int pb14 : 1;
+ unsigned int pb15 : 1;
+ unsigned int pb16 : 1;
+ unsigned int pb17 : 1;
+ unsigned int dummy1 : 14;
+} reg_pinmux_rw_pb_iop;
+#define REG_RD_ADDR_pinmux_rw_pb_iop 12
+#define REG_WR_ADDR_pinmux_rw_pb_iop 12
+
+/* Register rw_pc_gio, scope pinmux, type rw */
+typedef struct {
+ unsigned int pc0 : 1;
+ unsigned int pc1 : 1;
+ unsigned int pc2 : 1;
+ unsigned int pc3 : 1;
+ unsigned int pc4 : 1;
+ unsigned int pc5 : 1;
+ unsigned int pc6 : 1;
+ unsigned int pc7 : 1;
+ unsigned int pc8 : 1;
+ unsigned int pc9 : 1;
+ unsigned int pc10 : 1;
+ unsigned int pc11 : 1;
+ unsigned int pc12 : 1;
+ unsigned int pc13 : 1;
+ unsigned int pc14 : 1;
+ unsigned int pc15 : 1;
+ unsigned int pc16 : 1;
+ unsigned int pc17 : 1;
+ unsigned int dummy1 : 14;
+} reg_pinmux_rw_pc_gio;
+#define REG_RD_ADDR_pinmux_rw_pc_gio 16
+#define REG_WR_ADDR_pinmux_rw_pc_gio 16
+
+/* Register rw_pc_iop, scope pinmux, type rw */
+typedef struct {
+ unsigned int pc0 : 1;
+ unsigned int pc1 : 1;
+ unsigned int pc2 : 1;
+ unsigned int pc3 : 1;
+ unsigned int pc4 : 1;
+ unsigned int pc5 : 1;
+ unsigned int pc6 : 1;
+ unsigned int pc7 : 1;
+ unsigned int pc8 : 1;
+ unsigned int pc9 : 1;
+ unsigned int pc10 : 1;
+ unsigned int pc11 : 1;
+ unsigned int pc12 : 1;
+ unsigned int pc13 : 1;
+ unsigned int pc14 : 1;
+ unsigned int pc15 : 1;
+ unsigned int pc16 : 1;
+ unsigned int pc17 : 1;
+ unsigned int dummy1 : 14;
+} reg_pinmux_rw_pc_iop;
+#define REG_RD_ADDR_pinmux_rw_pc_iop 20
+#define REG_WR_ADDR_pinmux_rw_pc_iop 20
+
+/* Register rw_pd_gio, scope pinmux, type rw */
+typedef struct {
+ unsigned int pd0 : 1;
+ unsigned int pd1 : 1;
+ unsigned int pd2 : 1;
+ unsigned int pd3 : 1;
+ unsigned int pd4 : 1;
+ unsigned int pd5 : 1;
+ unsigned int pd6 : 1;
+ unsigned int pd7 : 1;
+ unsigned int pd8 : 1;
+ unsigned int pd9 : 1;
+ unsigned int pd10 : 1;
+ unsigned int pd11 : 1;
+ unsigned int pd12 : 1;
+ unsigned int pd13 : 1;
+ unsigned int pd14 : 1;
+ unsigned int pd15 : 1;
+ unsigned int pd16 : 1;
+ unsigned int pd17 : 1;
+ unsigned int dummy1 : 14;
+} reg_pinmux_rw_pd_gio;
+#define REG_RD_ADDR_pinmux_rw_pd_gio 24
+#define REG_WR_ADDR_pinmux_rw_pd_gio 24
+
+/* Register rw_pd_iop, scope pinmux, type rw */
+typedef struct {
+ unsigned int pd0 : 1;
+ unsigned int pd1 : 1;
+ unsigned int pd2 : 1;
+ unsigned int pd3 : 1;
+ unsigned int pd4 : 1;
+ unsigned int pd5 : 1;
+ unsigned int pd6 : 1;
+ unsigned int pd7 : 1;
+ unsigned int pd8 : 1;
+ unsigned int pd9 : 1;
+ unsigned int pd10 : 1;
+ unsigned int pd11 : 1;
+ unsigned int pd12 : 1;
+ unsigned int pd13 : 1;
+ unsigned int pd14 : 1;
+ unsigned int pd15 : 1;
+ unsigned int pd16 : 1;
+ unsigned int pd17 : 1;
+ unsigned int dummy1 : 14;
+} reg_pinmux_rw_pd_iop;
+#define REG_RD_ADDR_pinmux_rw_pd_iop 28
+#define REG_WR_ADDR_pinmux_rw_pd_iop 28
+
+/* Register rw_pe_gio, scope pinmux, type rw */
+typedef struct {
+ unsigned int pe0 : 1;
+ unsigned int pe1 : 1;
+ unsigned int pe2 : 1;
+ unsigned int pe3 : 1;
+ unsigned int pe4 : 1;
+ unsigned int pe5 : 1;
+ unsigned int pe6 : 1;
+ unsigned int pe7 : 1;
+ unsigned int pe8 : 1;
+ unsigned int pe9 : 1;
+ unsigned int pe10 : 1;
+ unsigned int pe11 : 1;
+ unsigned int pe12 : 1;
+ unsigned int pe13 : 1;
+ unsigned int pe14 : 1;
+ unsigned int pe15 : 1;
+ unsigned int pe16 : 1;
+ unsigned int pe17 : 1;
+ unsigned int dummy1 : 14;
+} reg_pinmux_rw_pe_gio;
+#define REG_RD_ADDR_pinmux_rw_pe_gio 32
+#define REG_WR_ADDR_pinmux_rw_pe_gio 32
+
+/* Register rw_pe_iop, scope pinmux, type rw */
+typedef struct {
+ unsigned int pe0 : 1;
+ unsigned int pe1 : 1;
+ unsigned int pe2 : 1;
+ unsigned int pe3 : 1;
+ unsigned int pe4 : 1;
+ unsigned int pe5 : 1;
+ unsigned int pe6 : 1;
+ unsigned int pe7 : 1;
+ unsigned int pe8 : 1;
+ unsigned int pe9 : 1;
+ unsigned int pe10 : 1;
+ unsigned int pe11 : 1;
+ unsigned int pe12 : 1;
+ unsigned int pe13 : 1;
+ unsigned int pe14 : 1;
+ unsigned int pe15 : 1;
+ unsigned int pe16 : 1;
+ unsigned int pe17 : 1;
+ unsigned int dummy1 : 14;
+} reg_pinmux_rw_pe_iop;
+#define REG_RD_ADDR_pinmux_rw_pe_iop 36
+#define REG_WR_ADDR_pinmux_rw_pe_iop 36
+
+/* Register rw_usb_phy, scope pinmux, type rw */
+typedef struct {
+ unsigned int en_usb0 : 1;
+ unsigned int en_usb1 : 1;
+ unsigned int dummy1 : 30;
+} reg_pinmux_rw_usb_phy;
+#define REG_RD_ADDR_pinmux_rw_usb_phy 40
+#define REG_WR_ADDR_pinmux_rw_usb_phy 40
+
+
+/* Constants */
+enum {
+ regk_pinmux_no = 0x00000000,
+ regk_pinmux_rw_hwprot_default = 0x00000000,
+ regk_pinmux_rw_pa_default = 0x00000000,
+ regk_pinmux_rw_pb_gio_default = 0x00000000,
+ regk_pinmux_rw_pb_iop_default = 0x00000000,
+ regk_pinmux_rw_pc_gio_default = 0x00000000,
+ regk_pinmux_rw_pc_iop_default = 0x00000000,
+ regk_pinmux_rw_pd_gio_default = 0x00000000,
+ regk_pinmux_rw_pd_iop_default = 0x00000000,
+ regk_pinmux_rw_pe_gio_default = 0x00000000,
+ regk_pinmux_rw_pe_iop_default = 0x00000000,
+ regk_pinmux_rw_usb_phy_default = 0x00000000,
+ regk_pinmux_yes = 0x00000001
+};
+#endif /* __pinmux_defs_h */
/*
* This file is autogenerated from
* file: ../../mod/fakereg.rmap
- * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
+ * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp
* last modified: Wed Feb 11 20:53:25 2004
* file: ../../rtl/global.rmap
- * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
+ * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp
* last modified: Mon Aug 18 17:08:23 2003
* file: ../../mod/modreg.rmap
- * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
+ * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp
* last modified: Fri Feb 20 16:40:04 2004
- *
+ *
* by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap
- * id: $Id: reg_map.h,v 1.7 2005/04/24 18:30:58 starvik Exp $
+ * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
regi_strcop = 0xb0030000,
regi_strmux = 0xb003a000,
regi_timer = 0xb001e000,
+ regi_timer0 = 0xb001e000,
regi_timer2 = 0xb005e000,
regi_trace = 0xb0040000,
} reg_scope_instances;
--- /dev/null
+#ifndef __strmux_defs_h
+#define __strmux_defs_h
+
+/*
+ * This file is autogenerated from
+ * file: ../../inst/strmux/rtl/guinness/strmux_regs.r
+ * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp
+ * last modfied: Mon Apr 11 16:09:43 2005
+ *
+ * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r
+ * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $
+ * Any changes here will be lost.
+ *
+ * -*- buffer-read-only: t -*-
+ */
+/* Main access macros */
+#ifndef REG_RD
+#define REG_RD( scope, inst, reg ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR
+#define REG_WR( scope, inst, reg, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_VECT
+#define REG_RD_VECT( scope, inst, reg, index ) \
+ REG_READ( reg_##scope##_##reg, \
+ (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_VECT
+#define REG_WR_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( reg_##scope##_##reg, \
+ (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT
+#define REG_RD_INT( scope, inst, reg ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT
+#define REG_WR_INT( scope, inst, reg, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_RD_INT_VECT
+#define REG_RD_INT_VECT( scope, inst, reg, index ) \
+ REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+#ifndef REG_WR_INT_VECT
+#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
+ REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg, (val) )
+#endif
+
+#ifndef REG_TYPE_CONV
+#define REG_TYPE_CONV( type, orgtype, val ) \
+ ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
+#endif
+
+#ifndef reg_page_size
+#define reg_page_size 8192
+#endif
+
+#ifndef REG_ADDR
+#define REG_ADDR( scope, inst, reg ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg )
+#endif
+
+#ifndef REG_ADDR_VECT
+#define REG_ADDR_VECT( scope, inst, reg, index ) \
+ ( (inst) + REG_RD_ADDR_##scope##_##reg + \
+ (index) * STRIDE_##scope##_##reg )
+#endif
+
+/* C-code for register scope strmux */
+
+/* Register rw_cfg, scope strmux, type rw */
+typedef struct {
+ unsigned int dma0 : 3;
+ unsigned int dma1 : 3;
+ unsigned int dma2 : 3;
+ unsigned int dma3 : 3;
+ unsigned int dma4 : 3;
+ unsigned int dma5 : 3;
+ unsigned int dma6 : 3;
+ unsigned int dma7 : 3;
+ unsigned int dma8 : 3;
+ unsigned int dma9 : 3;
+ unsigned int dummy1 : 2;
+} reg_strmux_rw_cfg;
+#define REG_RD_ADDR_strmux_rw_cfg 0
+#define REG_WR_ADDR_strmux_rw_cfg 0
+
+
+/* Constants */
+enum {
+ regk_strmux_ata = 0x00000003,
+ regk_strmux_eth0 = 0x00000001,
+ regk_strmux_eth1 = 0x00000004,
+ regk_strmux_ext0 = 0x00000001,
+ regk_strmux_ext1 = 0x00000001,
+ regk_strmux_ext2 = 0x00000001,
+ regk_strmux_ext3 = 0x00000001,
+ regk_strmux_iop0 = 0x00000002,
+ regk_strmux_iop1 = 0x00000001,
+ regk_strmux_off = 0x00000000,
+ regk_strmux_p21 = 0x00000004,
+ regk_strmux_rw_cfg_default = 0x00000000,
+ regk_strmux_ser0 = 0x00000002,
+ regk_strmux_ser1 = 0x00000002,
+ regk_strmux_ser2 = 0x00000004,
+ regk_strmux_ser3 = 0x00000003,
+ regk_strmux_sser0 = 0x00000003,
+ regk_strmux_sser1 = 0x00000003,
+ regk_strmux_strcop = 0x00000002
+};
+#endif /* __strmux_defs_h */
/*
* This file is autogenerated from
* file: ../../inst/timer/rtl/timer_regs.r
- * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
+ * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp
* last modfied: Mon Apr 11 16:09:53 2005
- *
+ *
* by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r
- * id: $Id: timer_defs.h,v 1.6 2005/04/24 18:30:58 starvik Exp $
+ * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $
* Any changes here will be lost.
*
* -*- buffer-read-only: t -*-
--- /dev/null
+#ifndef _ASM_CRIS_ARCH_PINMUX_H
+#define _ASM_CRIS_ARCH_PINMUX_H
+
+#define PORT_B 0
+#define PORT_C 1
+#define PORT_D 2
+#define PORT_E 3
+
+enum pin_mode {
+ pinmux_none = 0,
+ pinmux_fixed,
+ pinmux_gpio,
+ pinmux_iop
+};
+
+enum fixed_function {
+ pinmux_ser1,
+ pinmux_ser2,
+ pinmux_ser3,
+ pinmux_sser0,
+ pinmux_sser1,
+ pinmux_ata0,
+ pinmux_ata1,
+ pinmux_ata2,
+ pinmux_ata3,
+ pinmux_ata,
+ pinmux_eth1,
+ pinmux_timer
+};
+
+int crisv32_pinmux_init(void);
+int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
+int crisv32_pinmux_alloc_fixed(enum fixed_function function);
+int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
+int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
+void crisv32_pinmux_dump(void);
+
+#endif
--- /dev/null
+#include <hwregs/asm/reg_map_asm.h>
+#include <hwregs/asm/bif_core_defs_asm.h>
+#include <hwregs/asm/gio_defs_asm.h>
+#include <hwregs/asm/config_defs_asm.h>
+
+ .macro GIO_INIT
+ move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1
+ move.d $r0, [$r1]
+
+ move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0
+ move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1
+ move.d $r0, [$r1]
+ .endm
+
+ .macro START_CLOCKS
+ move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1
+ move.d [$r1], $r0
+ or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \
+ REG_STATE(config, rw_clk_ctrl, bif, yes) | \
+ REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0
+ move.d $r0, [$r1]
+ .endm
+
+ .macro SETUP_WAIT_STATES
+ ;; Set up waitstates etc
+ move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0
+ move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1
+ move.d $r1, [$r0]
+ move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0
+ move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1
+ move.d $r1, [$r0]
+ move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0
+ move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1
+ move.d $r1, [$r0]
+ move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0
+ move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1
+ move.d $r1, [$r0]
+#ifdef CONFIG_ETRAX_VCS_SIM
+ ;; Set up minimal flash waitstates
+ move.d 0, $r10
+ move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r11
+ move.d $r10, [$r11]
+#endif
+ .endm
#define THREAD_usp 4 /* offsetof(struct thread_struct, usp) */
#define THREAD_ccs 8 /* offsetof(struct thread_struct, ccs) */
-#define TASK_pid 149 /* offsetof(struct task_struct, pid) */
+#define TASK_pid 151 /* offsetof(struct task_struct, pid) */
#define LCLONE_VM 256 /* CLONE_VM */
#define LCLONE_UNTRACED 8388608 /* CLONE_UNTRACED */
#define PAGE_OFFSET KSEG_C /* kseg_c is mapped to physical ram. */
/*
- * Macros to convert between physical and virtual addresses. By stripiing a
+ * Macros to convert between physical and virtual addresses. By stripping a
* selected bit it's possible to convert between KSEG_x and 0x40000000 where the
* DRAM really resides. DRAM is virtually at 0xc.
*/
-#ifndef CONFIG_ETRAXFS_SIM
+#ifndef CONFIG_ETRAX_VCS_SIM
#define __pa(x) ((unsigned long)(x) & 0x7fffffff)
#define __va(x) ((void *)((unsigned long)(x) | 0x80000000))
#else
int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode);
int crisv32_pinmux_alloc_fixed(enum fixed_function function);
int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin);
+int crisv32_pinmux_dealloc_fixed(enum fixed_function function);
void crisv32_pinmux_dump(void);
#endif
* User-space process size. This is hardcoded into a few places, so don't
* changed it unless everything's clear!
*/
-#ifndef CONFIG_ETRAXFS_SIM
+#ifndef CONFIG_ETRAX_VCS_SIM
#define TASK_SIZE (0xB0000000UL)
#else
#define TASK_SIZE (0xA0000000UL)
#ifndef __ASM_ARCH_SPINLOCK_H
#define __ASM_ARCH_SPINLOCK_H
-#include <asm/system.h>
+#include <linux/spinlock_types.h>
#define RW_LOCK_BIAS 0x01000000
-#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
-#define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0)
-
-#define spin_is_locked(x) (*(volatile signed char *)(&(x)->lock) <= 0)
-#define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x))
extern void cris_spin_unlock(void *l, int val);
extern void cris_spin_lock(void *l);
-extern int cris_spin_trylock(void* l);
+extern int cris_spin_trylock(void *l);
-static inline void _raw_spin_unlock(spinlock_t *lock)
+static inline int __raw_spin_is_locked(raw_spinlock_t *x)
+{
+ return *(volatile signed char *)(&(x)->slock) <= 0;
+}
+
+static inline void __raw_spin_unlock(raw_spinlock_t *lock)
{
__asm__ volatile ("move.d %1,%0" \
- : "=m" (lock->lock) \
+ : "=m" (lock->slock) \
: "r" (1) \
: "memory");
}
-static inline int _raw_spin_trylock(spinlock_t *lock)
+static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
+{
+ while (__raw_spin_is_locked(lock))
+ cpu_relax();
+}
+
+static inline int __raw_spin_trylock(raw_spinlock_t *lock)
{
- return cris_spin_trylock((void*)&lock->lock);
+ return cris_spin_trylock((void *)&lock->slock);
}
-static inline void _raw_spin_lock(spinlock_t *lock)
+static inline void __raw_spin_lock(raw_spinlock_t *lock)
{
- cris_spin_lock((void*)&lock->lock);
+ cris_spin_lock((void *)&lock->slock);
}
-static inline void _raw_spin_lock_flags (spinlock_t *lock, unsigned long flags)
+static inline void
+__raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
{
- _raw_spin_lock(lock);
+ __raw_spin_lock(lock);
}
/*
* can "mix" irq-safe locks - any writer needs to get a
* irq-safe write-lock, but readers can get non-irqsafe
* read-locks.
+ *
*/
-typedef struct {
- spinlock_t lock;
- volatile int counter;
-#ifdef CONFIG_PREEMPT
- unsigned int break_lock;
-#endif
-} rwlock_t;
-
-#define RW_LOCK_UNLOCKED (rwlock_t) { {1}, 0 }
-
-#define rwlock_init(lp) do { *(lp) = RW_LOCK_UNLOCKED; } while (0)
-
-/**
- * read_can_lock - would read_trylock() succeed?
- * @lock: the rwlock in question.
- */
-#define read_can_lock(x) ((int)(x)->counter >= 0)
-
-/**
- * write_can_lock - would write_trylock() succeed?
- * @lock: the rwlock in question.
- */
-#define write_can_lock(x) ((x)->counter == 0)
-
-#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
-/* read_lock, read_unlock are pretty straightforward. Of course it somehow
- * sucks we end up saving/restoring flags twice for read_lock_irqsave aso. */
-
-static __inline__ void _raw_read_lock(rwlock_t *rw)
+static inline int __raw_read_can_lock(raw_rwlock_t *x)
{
- unsigned long flags;
- local_irq_save(flags);
- _raw_spin_lock(&rw->lock);
-
- rw->counter++;
-
- _raw_spin_unlock(&rw->lock);
- local_irq_restore(flags);
+ return (int)(x)->lock > 0;
}
-static __inline__ void _raw_read_unlock(rwlock_t *rw)
+static inline int __raw_write_can_lock(raw_rwlock_t *x)
{
- unsigned long flags;
- local_irq_save(flags);
- _raw_spin_lock(&rw->lock);
-
- rw->counter--;
-
- _raw_spin_unlock(&rw->lock);
- local_irq_restore(flags);
+ return (x)->lock == RW_LOCK_BIAS;
}
-/* write_lock is less trivial. We optimistically grab the lock and check
- * if we surprised any readers. If so we release the lock and wait till
- * they're all gone before trying again
- *
- * Also note that we don't use the _irqsave / _irqrestore suffixes here.
- * If we're called with interrupts enabled and we've got readers (or other
- * writers) in interrupt handlers someone fucked up and we'd dead-lock
- * sooner or later anyway. prumpf */
-
-static __inline__ void _raw_write_lock(rwlock_t *rw)
+static inline void __raw_read_lock(raw_rwlock_t *rw)
{
-retry:
- _raw_spin_lock(&rw->lock);
-
- if(rw->counter != 0) {
- /* this basically never happens */
- _raw_spin_unlock(&rw->lock);
-
- while(rw->counter != 0);
-
- goto retry;
- }
-
- /* got it. now leave without unlocking */
- rw->counter = -1; /* remember we are locked */
+ __raw_spin_lock(&rw->slock);
+ while (rw->lock == 0);
+ rw->lock--;
+ __raw_spin_unlock(&rw->slock);
}
-/* write_unlock is absolutely trivial - we don't have to wait for anything */
-
-static __inline__ void _raw_write_unlock(rwlock_t *rw)
+static inline void __raw_write_lock(raw_rwlock_t *rw)
{
- rw->counter = 0;
- _raw_spin_unlock(&rw->lock);
+ __raw_spin_lock(&rw->slock);
+ while (rw->lock != RW_LOCK_BIAS);
+ rw->lock == 0;
+ __raw_spin_unlock(&rw->slock);
}
-static __inline__ int _raw_write_trylock(rwlock_t *rw)
+static inline void __raw_read_unlock(raw_rwlock_t *rw)
{
- _raw_spin_lock(&rw->lock);
- if (rw->counter != 0) {
- /* this basically never happens */
- _raw_spin_unlock(&rw->lock);
-
- return 0;
- }
+ __raw_spin_lock(&rw->slock);
+ rw->lock++;
+ __raw_spin_unlock(&rw->slock);
+}
- /* got it. now leave without unlocking */
- rw->counter = -1; /* remember we are locked */
- return 1;
+static inline void __raw_write_unlock(raw_rwlock_t *rw)
+{
+ __raw_spin_lock(&rw->slock);
+ while (rw->lock != RW_LOCK_BIAS);
+ rw->lock == RW_LOCK_BIAS;
+ __raw_spin_unlock(&rw->slock);
}
-static __inline__ int is_read_locked(rwlock_t *rw)
+static inline int __raw_read_trylock(raw_rwlock_t *rw)
{
- return rw->counter > 0;
+ int ret = 0;
+ __raw_spin_lock(&rw->slock);
+ if (rw->lock != 0) {
+ rw->lock--;
+ ret = 1;
+ }
+ __raw_spin_unlock(&rw->slock);
+ return ret;
}
-static __inline__ int is_write_locked(rwlock_t *rw)
+static inline int __raw_write_trylock(raw_rwlock_t *rw)
{
- return rw->counter < 0;
+ int ret = 0;
+ __raw_spin_lock(&rw->slock);
+ if (rw->lock == RW_LOCK_BIAS) {
+ rw->lock == 0;
+ ret = 1;
+ }
+ __raw_spin_unlock(&rw->slock);
+ return 1;
}
+
#define _raw_spin_relax(lock) cpu_relax()
#define _raw_read_relax(lock) cpu_relax()
#define _raw_write_relax(lock) cpu_relax()
#define local_irq_save(x) \
__asm__ __volatile__ ("move $ccs, %0\n\tdi" : "=rm" (x) : : "memory");
-#ifdef CONFIG_SMP
-typedef struct {
- volatile unsigned int lock __attribute__ ((aligned(4)));
-#ifdef CONFIG_PREEMPT
- unsigned int break_lock;
-#endif
-} spinlock_t;
-#endif
-
#endif /* _ASM_CRIS_ARCH_SYSTEM_H */
#ifndef _ASM_CRIS_ARCH_TIMEX_H
#define _ASM_CRIS_ARCH_TIMEX_H
-#include <asm/arch/hwregs/reg_map.h>
-#include <asm/arch/hwregs/reg_rdwr.h>
-#include <asm/arch/hwregs/timer_defs.h>
+#include <hwregs/reg_map.h>
+#include <hwregs/reg_rdwr.h>
+#include <hwregs/timer_defs.h>
/*
* The clock runs at 100MHz, we divide it by 1000000. If you change anything
/* Convert the value in step of 10 ns to 1us without overflow: */
#define GET_JIFFIES_USEC() \
- ( (TIMER0_DIV - REG_RD(timer, regi_timer, r_tmr0_data)) /100 )
+ ((TIMER0_DIV - REG_RD(timer, regi_timer0, r_tmr0_data)) / 100)
extern unsigned long get_ns_in_jiffie(void);
".endif\n\t" \
"break 13" \
: "=r" (__a) \
- : "r" (__n_)); \
+ : "r" (__n_) \
+ : "memory"); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
".endif\n\t" \
"break 13" \
: "=r" (__a) \
- : "r" (__n_), "0" (__a)); \
+ : "r" (__n_), "0" (__a) \
+ : "memory"); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
".endif\n\t" \
"break 13" \
: "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b)); \
+ : "r" (__n_), "0" (__a), "r" (__b) \
+ : "memory"); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
".endif\n\t" \
"break 13" \
: "=r" (__a) \
- : "r" (__n_), "0" (__a), "r" (__b), "r" (__c)); \
+ : "r" (__n_), "0" (__a), "r" (__b), "r" (__c) \
+ : "memory"); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
"break 13" \
: "=r" (__a) \
: "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d)); \
+ "r" (__c), "r" (__d)\
+ : "memory"); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
"break 13" \
: "=r" (__a) \
: "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d), "h" (__e)); \
+ "r" (__c), "r" (__d), "h" (__e) \
+ : "memory"); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
"break 13" \
: "=r" (__a) \
: "r" (__n_), "0" (__a), "r" (__b), \
- "r" (__c), "r" (__d), "h" (__e), "x" (__f)); \
+ "r" (__c), "r" (__d), "h" (__e), "x" (__f) \
+ : "memory"); \
if (__a >= 0) \
return (type) __a; \
errno = -__a; \
unsigned long flags;
int retval;
cris_atomic_save(v, flags);
- retval = (v->counter)++;
+ retval = ++(v->counter);
cris_atomic_restore(v, flags);
return retval;
}
unsigned long flags;
int retval;
cris_atomic_save(v, flags);
- retval = (v->counter)--;
+ retval = --(v->counter);
cris_atomic_restore(v, flags);
return retval;
}
*/
#define PARTITION_TABLE_OFFSET 10
-#define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */
+#define PARTITION_TABLE_MAGIC 0xbeef /* Not a good magic */
/* The partitiontable_head is located at offset +10: */
struct partitiontable_head {
- __u16 magic; /* PARTITION_TABLE_MAGIC */
- __u16 size; /* Length of ptable block (not header) */
- __u32 checksum; /* simple longword sum */
+ __u16 magic; /* PARTITION_TABLE_MAGIC */
+ __u16 size; /* Length of ptable block (entries + end marker) */
+ __u32 checksum; /* simple longword sum, over entries + end marker */
};
/* And followed by partition table entries */
struct partitiontable_entry {
- __u32 offset; /* Offset is relative to the sector the ptable is in */
- __u32 size;
- __u32 checksum; /* simple longword sum */
- __u16 type;
- __u16 flags; /* bit 0: ro/rw = 1/0 */
- __u32 future0; /* 16 bytes reserved for future use */
+ __u32 offset; /* relative to the sector the ptable is in */
+ __u32 size; /* in bytes */
+ __u32 checksum; /* simple longword sum */
+ __u16 type; /* see type codes below */
+ __u16 flags; /* bit 0: ro/rw = 1/0 */
+ __u32 future0; /* 16 bytes reserved for future use */
__u32 future1;
__u32 future2;
__u32 future3;
#define PARTITIONTABLE_END_MARKER 0xFFFFFFFF
#define PARTITIONTABLE_END_MARKER_SIZE 4
-/*#define PARTITION_TYPE_RESCUE 0x0000?*/ /* Not used, maybe it should? */
+#define PARTITIONTABLE_END_PAD 10
+
+/* Complete structure for whole partition table */
+/* note that table may end before CONFIG_ETRAX_PTABLE_ENTRIES by setting
+ * offset of the last entry + 1 to PARTITIONTABLE_END_MARKER.
+ */
+struct partitiontable {
+ __u8 skip[PARTITION_TABLE_OFFSET];
+ struct partitiontable_head head;
+ struct partitiontable_entry entries[];
+};
+
#define PARTITION_TYPE_PARAM 0x0001
#define PARTITION_TYPE_KERNEL 0x0002
#define PARTITION_TYPE_JFFS 0x0003
+#define PARTITION_TYPE_JFFS2 0x0000
+
+#define PARTITION_FLAGS_READONLY_MASK 0x0001
+#define PARTITION_FLAGS_READONLY 0x0001
/* The master mtd for the entire flash. */
-extern struct mtd_info* axisflash_mtd;
+extern struct mtd_info *axisflash_mtd;
#endif
#ifndef _CRIS_BUG_H
#define _CRIS_BUG_H
-#include <asm-generic/bug.h>
+#include <asm/arch/bug.h>
#endif
extern unsigned long loops_per_usec; /* arch/cris/mm/init.c */
+/* May be defined by arch/delay.h. */
+#ifndef udelay
static inline void udelay(unsigned long usecs)
{
__delay(usecs * loops_per_usec);
}
+#endif
#endif /* defined(_CRIS_DELAY_H) */
{
}
-#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
-extern int
-dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
- dma_addr_t device_addr, size_t size, int flags);
-
-extern void
-dma_release_declared_memory(struct device *dev);
-
-extern void *
-dma_mark_declared_memory_occupied(struct device *dev,
- dma_addr_t device_addr, size_t size);
#endif
-/* $Id: etraxgpio.h,v 1.8 2002/06/17 15:53:07 johana Exp $ */
/*
* The following devices are accessable using this driver using
- * GPIO_MAJOR (120) and a couple of minor numbers:
- * For ETRAX 100LX (ARCH_V10):
+ * GPIO_MAJOR (120) and a couple of minor numbers.
+ *
+ * For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10):
* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
* /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction
* /dev/leds minor 2, Access to leds depending on kernelconfig
* /dev/gpiog minor 3
- g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG
- g1-g7 and g25-g31 is both input and outputs but on different pins
- Also note that some bits change pins depending on what interfaces
- are enabled.
+ * g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG
+ * g1-g7 and g25-g31 is both input and outputs but on different pins
+ * Also note that some bits change pins depending on what interfaces
+ * are enabled.
*
+ * For ETRAX FS (CONFIG_ETRAXFS):
+ * /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
+ * /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
+ * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
+ * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
+ * /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction
+ * /dev/leds minor 2, Access to leds depending on kernelconfig
*
- * For ETRAX FS (ARCH_V32):
+ * For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
* /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
- * /dev/gpioc minor 2, 18 bit GPIO, each bit can change direction
- * /dev/gpiod minor 3, 18 bit GPIO, each bit can change direction
- * /dev/gpioe minor 4, 18 bit GPIO, each bit can change direction
- * /dev/leds minor 5, Access to leds depending on kernelconfig
+ * /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
+ * /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
+ * /dev/leds minor 2, Access to leds depending on kernelconfig
+ * /dev/pwm0 minor 16, PWM channel 0 on PA30
+ * /dev/pwm1 minor 17, PWM channel 1 on PA31
+ * /dev/pwm2 minor 18, PWM channel 2 on PB26
*
*/
#ifndef _ASM_ETRAXGPIO_H
#define GPIO_MINOR_G 3
#define GPIO_MINOR_LAST 3
#endif
-#ifdef CONFIG_ETRAX_ARCH_V32
+
+#ifdef CONFIG_ETRAXFS
#define ETRAXGPIO_IOCTYPE 43
#define GPIO_MINOR_A 0
#define GPIO_MINOR_B 1
#define GPIO_MINOR_C 3
#define GPIO_MINOR_D 4
#define GPIO_MINOR_E 5
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+#define GPIO_MINOR_V 6
+#define GPIO_MINOR_LAST 6
+#else
#define GPIO_MINOR_LAST 5
#endif
+#endif
+
+#ifdef CONFIG_CRIS_MACH_ARTPEC3
+#define ETRAXGPIO_IOCTYPE 43
+#define GPIO_MINOR_A 0
+#define GPIO_MINOR_B 1
+#define GPIO_MINOR_LEDS 2
+#define GPIO_MINOR_C 3
+#define GPIO_MINOR_D 4
+#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
+#define GPIO_MINOR_V 6
+#define GPIO_MINOR_LAST 6
+#else
+#define GPIO_MINOR_LAST 4
+#endif
+#define GPIO_MINOR_PWM0 16
+#define GPIO_MINOR_PWM1 17
+#define GPIO_MINOR_PWM2 18
+#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2
+#endif
/* supported ioctl _IOC_NR's */
/* GPIO direction ioctl's */
#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */
-#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input,
+#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input,
returns mask with current inputs (obsolete) */
#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output,
returns mask with current outputs (obsolete)*/
#define IO_GET_PWR_BT 0xE
/* Bit toggling in driver settings */
-/* bit set in low byte0 is CLK mask (0x00FF),
- bit set in byte1 is DATA mask (0xFF00)
+/* bit set in low byte0 is CLK mask (0x00FF),
+ bit set in byte1 is DATA mask (0xFF00)
msb, data_mask[7:0] , clk_mask[7:0]
*/
-#define IO_CFG_WRITE_MODE 0xF
+#define IO_CFG_WRITE_MODE 0xF
#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \
- ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) )
+ ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) )
/* The following 4 ioctl's take a pointer as argument and handles
* 32 bit ports (port G) properly.
* *arg updated with current output pins.
*/
+/* The following ioctl's are applicable to the PWM channels only */
+
+#define IO_PWM_SET_MODE 0x20
+
+enum io_pwm_mode {
+ PWM_OFF = 0, /* disabled, deallocated */
+ PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */
+ PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */
+ PWM_VARFREQ = 3 /* individually configurable high/low periods */
+};
+
+struct io_pwm_set_mode {
+ enum io_pwm_mode mode;
+};
+
+/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns
+ * from 10ns (value = 0) to 81920ns (value = 8191)
+ * (Resulting frequencies range from 50 MHz (10ns + 10ns) down to
+ * 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty
+ * cycle (81920 + 10ns or 10ns + 81920ns, respectively).)
+ */
+#define IO_PWM_SET_PERIOD 0x21
+
+struct io_pwm_set_period {
+ unsigned int lo; /* 0..8191 */
+ unsigned int hi; /* 0..8191 */
+};
+
+/* Only for modes PWM_STANDARD and PWM_FAST.
+ * For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from
+ * 0 (value = 0) to 255/256 (value = 255).
+ * For PWM_FAST, set duty cycle of PWM output signal from
+ * 0% (value = 0) to 100% (value = 255). Output signal in this mode
+ * is a 10ns pulse surrounded by a high or low level depending on duty
+ * cycle (except for 0% and 100% which result in a constant output).
+ * Resulting output frequency varies from 50 MHz at 50% duty cycle,
+ * down to 390 kHz at min/max duty cycle.
+ */
+#define IO_PWM_SET_DUTY 0x22
+struct io_pwm_set_duty {
+ int duty; /* 0..255 */
+};
#endif
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
-/* The following is junk needed for the arch-independent code but which
- * we never use in the CRIS port
+/* I/O port access. Normally there is no I/O space on CRIS but when
+ * Cardbus/PCI is enabled the request is passed through the bridge.
*/
#define IO_SPACE_LIMIT 0xffff
typedef struct { unsigned long pte; } pte_t;
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct page *pgtable_t;
#endif
#define pte_val(x) ((x).pte)
/* Currently we assume that HZ=100 is good for CRIS. */
#ifdef __KERNEL__
-# define HZ 100 /* Internal kernel timer frequency */
+# define HZ CONFIG_HZ /* Internal kernel timer frequency */
# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
#endif
#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, pte)
#define pmd_populate(mm, pmd, pte) pmd_set(pmd, page_address(pte))
+#define pmd_pgtable(pmd) pmd_page(pmd)
/*
* Allocate and free page tables.
return pte;
}
-static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
struct page *pte;
pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
+ pgtable_page_ctor(pte);
return pte;
}
free_page((unsigned long)pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
+ pgtable_page_dtor(pte);
__free_page(pte);
}
-
-#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
+#define __pte_free_tlb(tlb,pte) \
+do { \
+ pgtable_page_dtor(pte); \
+ tlb_remove_page((tlb), pte); \
+} while (0)
#define check_pgt_cache() do { } while (0)
#define pte_unmap(pte) do { } while (0)
#define pte_unmap_nested(pte) do { } while (0)
#define pte_pfn(x) ((unsigned long)(__va((x).pte)) >> PAGE_SHIFT)
-#define pfn_pte(pfn, prot) __pte((__pa((pfn) << PAGE_SHIFT)) | pgprot_val(prot))
+#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
#define pte_ERROR(e) \
printk("%s:%d: bad pte %p(%08lx).\n", __FILE__, __LINE__, &(e), pte_val(e))
#endif
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
#ifdef __KERNEL__
struct task_struct;
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
+
/* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
-/* $Id: rtc.h,v 1.7 2002/11/04 07:32:09 starvik Exp $ */
#ifndef __RTC_H__
#define __RTC_H__
-
-
#ifdef CONFIG_ETRAX_DS1302
/* Dallas DS1302 clock/calendar register numbers. */
# define RTC_SECONDS 0
# define RTC_CONTROL 7
/* Bits in CONTROL register. */
-# define RTC_CONTROL_WRITEPROTECT 0x80
-# define RTC_TRICKLECHARGER 8
-
+# define RTC_CONTROL_WRITEPROTECT 0x80
+# define RTC_TRICKLECHARGER 8
+
/* Bits in TRICKLECHARGER register TCS TCS TCS TCS DS DS RS RS. */
-# define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */
-# define RTC_TCR_1DIOD 0x04 /* xxxx01xx */
-# define RTC_TCR_2DIOD 0x08 /* xxxx10xx */
-# define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */
-# define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */
-# define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */
-# define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */
+# define RTC_TCR_PATTERN 0xA0 /* 1010xxxx */
+# define RTC_TCR_1DIOD 0x04 /* xxxx01xx */
+# define RTC_TCR_2DIOD 0x08 /* xxxx10xx */
+# define RTC_TCR_DISABLED 0x00 /* xxxxxx00 Disabled */
+# define RTC_TCR_2KOHM 0x01 /* xxxxxx01 2KOhm */
+# define RTC_TCR_4KOHM 0x02 /* xxxxxx10 4kOhm */
+# define RTC_TCR_8KOHM 0x03 /* xxxxxx11 8kOhm */
#elif defined(CONFIG_ETRAX_PCF8563)
/* I2C bus slave registers. */
/*
* The struct used to pass data via the following ioctl. Similar to the
- * struct tm in <time.h>, but it needs to be here so that the kernel
+ * struct tm in <time.h>, but it needs to be here so that the kernel
* source is self contained, allowing cross-compiles, etc. etc.
*/
struct rtc_time {
/* ioctl() calls that are permitted to the /dev/rtc interface. */
#define RTC_MAGIC 'p'
-#define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time) /* Read RTC time. */
-#define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time) /* Set RTC time. */
-#define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int)
-#define RTC_VLOW_RD _IOR(RTC_MAGIC, 0x11, int) /* Voltage Low detector */
-#define RTC_VLOW_SET _IO(RTC_MAGIC, 0x12) /* Clear voltage low information */
-#define RTC_MAX_IOCTL 0x12
+/* Read RTC time. */
+#define RTC_RD_TIME _IOR(RTC_MAGIC, 0x09, struct rtc_time)
+/* Set RTC time. */
+#define RTC_SET_TIME _IOW(RTC_MAGIC, 0x0a, struct rtc_time)
+#define RTC_SET_CHARGE _IOW(RTC_MAGIC, 0x0b, int)
+/* Voltage low detector */
+#define RTC_VL_READ _IOR(RTC_MAGIC, 0x13, int)
+/* Clear voltage low information */
+#define RTC_VL_CLR _IO(RTC_MAGIC, 0x14)
+#define RTC_MAX_IOCTL 0x14
#endif /* __RTC_H__ */
#include <linux/cpumask.h>
extern cpumask_t phys_cpu_present_map;
-#define cpu_possible_map phys_cpu_present_map
+extern cpumask_t cpu_possible_map;
-#define __smp_processor_id() (current_thread_info()->cpu)
+#define raw_smp_processor_id() (current_thread_info()->cpu)
#endif
/* Values for SSP_FRAME_SYNC */
#define NORMAL_SYNC 1
#define EARLY_SYNC 2
+#define SECOND_WORD_SYNC 0x40000
#define BIT_SYNC 4
#define WORD_SYNC 8
#define __NR_epoll_pwait 319
#define __NR_utimensat 320
#define __NR_signalfd 321
-#define __NR_timerfd 322
+#define __NR_timerfd_create 322
#define __NR_eventfd 323
#define __NR_fallocate 324
+#define __NR_timerfd_settime 315
+#define __NR_timerfd_gettime 316
#ifdef __KERNEL__
+++ /dev/null
-/*
- * FRV doesn't do AOUT format. This header file should be removed as
- * soon as fs/exec.c and fs/proc/kcore.c and the archs that require
- * them to include linux/a.out.h are fixed.
- */
#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
-#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-static inline
-unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v)
-{
- unsigned long old, tmp;
-
- asm volatile(
- "0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- " and%I3 %1,%3,%2 \n"
- " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
- " beq icc3,#0,0b \n"
- : "+U"(*v), "=&r"(old), "=r"(tmp)
- : "NPr"(~mask)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- return old;
-}
-
-static inline
-unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v)
-{
- unsigned long old, tmp;
-
- asm volatile(
- "0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- " or%I3 %1,%3,%2 \n"
- " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
- " beq icc3,#0,0b \n"
- : "+U"(*v), "=&r"(old), "=r"(tmp)
- : "NPr"(mask)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- return old;
-}
-
-static inline
-unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v)
-{
- unsigned long old, tmp;
-
- asm volatile(
- "0: \n"
- " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
- " ckeq icc3,cc7 \n"
- " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
- " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
- " xor%I3 %1,%3,%2 \n"
- " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
- " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
- " beq icc3,#0,0b \n"
- : "+U"(*v), "=&r"(old), "=r"(tmp)
- : "NPr"(mask)
- : "memory", "cc7", "cc3", "icc3"
- );
-
- return old;
-}
-
-#else
-
-extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v);
-extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v);
-extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v);
-
-#endif
-
-#define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v))
-#define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v))
-
/*****************************************************************************/
/*
* exchange value with memory
#include <linux/compiler.h>
#include <asm/byteorder.h>
-#include <asm/system.h>
-#include <asm/atomic.h>
#ifdef __KERNEL__
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
+#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
+static inline
+unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v)
+{
+ unsigned long old, tmp;
+
+ asm volatile(
+ "0: \n"
+ " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
+ " ckeq icc3,cc7 \n"
+ " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
+ " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
+ " and%I3 %1,%3,%2 \n"
+ " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
+ " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
+ " beq icc3,#0,0b \n"
+ : "+U"(*v), "=&r"(old), "=r"(tmp)
+ : "NPr"(~mask)
+ : "memory", "cc7", "cc3", "icc3"
+ );
+
+ return old;
+}
+
+static inline
+unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v)
+{
+ unsigned long old, tmp;
+
+ asm volatile(
+ "0: \n"
+ " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
+ " ckeq icc3,cc7 \n"
+ " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
+ " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
+ " or%I3 %1,%3,%2 \n"
+ " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
+ " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
+ " beq icc3,#0,0b \n"
+ : "+U"(*v), "=&r"(old), "=r"(tmp)
+ : "NPr"(mask)
+ : "memory", "cc7", "cc3", "icc3"
+ );
+
+ return old;
+}
+
+static inline
+unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v)
+{
+ unsigned long old, tmp;
+
+ asm volatile(
+ "0: \n"
+ " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
+ " ckeq icc3,cc7 \n"
+ " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
+ " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
+ " xor%I3 %1,%3,%2 \n"
+ " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
+ " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
+ " beq icc3,#0,0b \n"
+ : "+U"(*v), "=&r"(old), "=r"(tmp)
+ : "NPr"(mask)
+ : "memory", "cc7", "cc3", "icc3"
+ );
+
+ return old;
+}
+
+#else
+
+extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v);
+extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v);
+extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v);
+
+#endif
+
+#define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v))
+#define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v))
+
static inline int test_and_clear_bit(int nr, volatile void *addr)
{
volatile unsigned long *ptr = addr;
typedef struct { pmd_t pue[1]; } pud_t;
typedef struct { pud_t pge[1]; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct page *pgtable_t;
#define pte_val(x) ((x).pte)
#define pmd_val(x) ((x).ste[0])
#define _ASM_PARAM_H
#ifdef __KERNEL__
-#define HZ 1000 /* Internal kernel timer frequency */
+#define HZ CONFIG_HZ /* Internal kernel timer frequency */
#define USER_HZ 100 /* .. some user interfaces are in "ticks" */
#define CLOCKS_PER_SEC (USER_HZ) /* like times() */
#endif
do { \
__set_pmd((PMD), page_to_pfn(PAGE) << PAGE_SHIFT | _PAGE_TABLE); \
} while(0)
+#define pmd_pgtable(pmd) pmd_page(pmd)
/*
* Allocate and free page tables.
extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long);
-extern struct page *pte_alloc_one(struct mm_struct *, unsigned long);
+extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long);
static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
{
free_page((unsigned long)pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
+ pgtable_page_dtor(pte);
__free_page(pte);
}
-#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
+#define __pte_free_tlb(tlb,pte) \
+do { \
+ pgtable_page_dtor(pte); \
+ tlb_remove_page((tlb),(pte)); \
+} while (0)
/*
* allocating and freeing a pmd is trivial: the 1-entry pmd is
#endif
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
#undef __FD_SET
#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
#undef __FD_ZERO
#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif
#include <linux/types.h>
#include <linux/linkage.h>
+#include <linux/kernel.h>
struct thread_struct;
{
switch (size) {
case 4:
- return cmpxchg(ptr, old, new);
+ return cmpxchg((unsigned long *)ptr, old, new);
default:
return __cmpxchg_local_generic(ptr, old, new, size);
}
+ifeq ($(wildcard include/asm-$(SRCARCH)/a.out.h),include/asm-$(SRCARCH)/a.out.h)
unifdef-y += a.out.h
+endif
unifdef-y += auxvec.h
unifdef-y += byteorder.h
unifdef-y += errno.h
* in the low address range. Architectures for which this is not
* true can't use this generic implementation.
*/
-extern unsigned int fastcall ioread8(void __iomem *);
-extern unsigned int fastcall ioread16(void __iomem *);
-extern unsigned int fastcall ioread16be(void __iomem *);
-extern unsigned int fastcall ioread32(void __iomem *);
-extern unsigned int fastcall ioread32be(void __iomem *);
+extern unsigned int ioread8(void __iomem *);
+extern unsigned int ioread16(void __iomem *);
+extern unsigned int ioread16be(void __iomem *);
+extern unsigned int ioread32(void __iomem *);
+extern unsigned int ioread32be(void __iomem *);
-extern void fastcall iowrite8(u8, void __iomem *);
-extern void fastcall iowrite16(u16, void __iomem *);
-extern void fastcall iowrite16be(u16, void __iomem *);
-extern void fastcall iowrite32(u32, void __iomem *);
-extern void fastcall iowrite32be(u32, void __iomem *);
+extern void iowrite8(u8, void __iomem *);
+extern void iowrite16(u16, void __iomem *);
+extern void iowrite16be(u16, void __iomem *);
+extern void iowrite32(u32, void __iomem *);
+extern void iowrite32be(u32, void __iomem *);
/*
* "string" versions of the above. Note that they
* memory across multiple ports, use "memcpy_toio()"
* and friends.
*/
-extern void fastcall ioread8_rep(void __iomem *port, void *buf, unsigned long count);
-extern void fastcall ioread16_rep(void __iomem *port, void *buf, unsigned long count);
-extern void fastcall ioread32_rep(void __iomem *port, void *buf, unsigned long count);
+extern void ioread8_rep(void __iomem *port, void *buf, unsigned long count);
+extern void ioread16_rep(void __iomem *port, void *buf, unsigned long count);
+extern void ioread32_rep(void __iomem *port, void *buf, unsigned long count);
-extern void fastcall iowrite8_rep(void __iomem *port, const void *buf, unsigned long count);
-extern void fastcall iowrite16_rep(void __iomem *port, const void *buf, unsigned long count);
-extern void fastcall iowrite32_rep(void __iomem *port, const void *buf, unsigned long count);
+extern void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count);
+extern void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count);
+extern void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count);
/* Create a virtual mapping cookie for an IO port range */
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
* 1 even when the "1" assertion wasn't true.
*/
static inline void
-__mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *))
+__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
{
if (unlikely(atomic_dec_return(count) < 0))
fail_fn(count);
* or anything the slow path function returns.
*/
static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *))
+__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
{
if (unlikely(atomic_dec_return(count) < 0))
return fail_fn(count);
* to return 0 otherwise.
*/
static inline void
-__mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *))
+__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
{
smp_mb();
if (unlikely(atomic_inc_return(count) <= 0))
* even when the "1" assertion wasn't true.
*/
static inline void
-__mutex_fastpath_lock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *))
+__mutex_fastpath_lock(atomic_t *count, void (*fail_fn)(atomic_t *))
{
if (unlikely(atomic_xchg(count, 0) != 1))
fail_fn(count);
* or anything the slow path function returns
*/
static inline int
-__mutex_fastpath_lock_retval(atomic_t *count, fastcall int (*fail_fn)(atomic_t *))
+__mutex_fastpath_lock_retval(atomic_t *count, int (*fail_fn)(atomic_t *))
{
if (unlikely(atomic_xchg(count, 0) != 1))
return fail_fn(count);
* to return 0 otherwise.
*/
static inline void
-__mutex_fastpath_unlock(atomic_t *count, fastcall void (*fail_fn)(atomic_t *))
+__mutex_fastpath_unlock(atomic_t *count, void (*fail_fn)(atomic_t *))
{
smp_mb();
if (unlikely(atomic_xchg(count, 1) != 0))
return 0;
}
+#ifndef user_termios_to_kernel_termios
#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
+#endif
+
+#ifndef kernel_termios_to_user_termios
#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+#endif
+
#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-#ifdef __KERNEL__
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-
-#endif
-
#endif /* __H8300_A_OUT_H__ */
#ifndef HZ
-#define HZ 100
+#define HZ CONFIG_HZ
#endif
#ifdef __KERNEL__
#endif
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
#undef __FD_SET
#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
#undef __FD_ZERO
#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif
*/
#define TASK_SIZE (0xFFFFFFFFUL)
+#ifdef __KERNEL__
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
+#endif
+
/*
* This decides where the kernel will search for a free chunk of vm
* space during mmap's. We won't be using it
#define N_SYMSIZE(x) 0
#define N_TXTOFF(x) 0
-#ifdef __KERNEL__
-#include <asm/ustack.h>
-#endif
#endif /* _ASM_IA64_A_OUT_H */
#endif
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
+ typedef struct page *pgtable_t;
# define pte_val(x) ((x).pte)
# define pmd_val(x) ((x).pmd)
typedef unsigned long pmd_t;
typedef unsigned long pgd_t;
typedef unsigned long pgprot_t;
+ typedef struct page *pgtable_t;
# endif
# define pte_val(x) (x)
#define __pmd_free_tlb(tlb, pmd) pmd_free((tlb)->mm, pmd)
static inline void
-pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, struct page *pte)
+pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, pgtable_t pte)
{
pmd_val(*pmd_entry) = page_to_phys(pte);
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
static inline void
pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte)
pmd_val(*pmd_entry) = __pa(pte);
}
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
- unsigned long addr)
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr)
{
- void *pg = quicklist_alloc(0, GFP_KERNEL, NULL);
- return pg ? virt_to_page(pg) : NULL;
+ struct page *page;
+ void *pg;
+
+ pg = quicklist_alloc(0, GFP_KERNEL, NULL);
+ if (!pg)
+ return NULL;
+ page = virt_to_page(pg);
+ pgtable_page_ctor(page);
+ return page;
}
static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
return quicklist_alloc(0, GFP_KERNEL, NULL);
}
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
+ pgtable_page_dtor(pte);
quicklist_free_page(0, NULL, pte);
}
unsigned long, long);
extern void ia64_flush_fph (struct task_struct *);
extern void ia64_sync_fph (struct task_struct *);
+ extern void ia64_sync_krbs(void);
extern long ia64_sync_user_rbs (struct task_struct *, struct switch_stack *,
unsigned long, unsigned long);
extern void ia64_increment_ip (struct pt_regs *pt);
extern void ia64_decrement_ip (struct pt_regs *pt);
+ extern void ia64_ptrace_stop(void);
+ #define arch_ptrace_stop(code, info) \
+ ia64_ptrace_stop()
+ #define arch_ptrace_stop_needed(code, info) \
+ (!test_thread_flag(TIF_RESTORE_RSE))
+
+ extern void ptrace_attach_sync_user_rbs (struct task_struct *);
+ #define arch_ptrace_attach(child) \
+ ptrace_attach_sync_user_rbs(child)
+
#endif /* !__KERNEL__ */
/* pt_all_user_regs is used for PTRACE_GETREGS PTRACE_SETREGS */
#define alloc_task_struct() ((struct task_struct *)__get_free_pages(GFP_KERNEL | __GFP_COMP, KERNEL_STACK_SIZE_ORDER))
#define free_task_struct(tsk) free_pages((unsigned long) (tsk), KERNEL_STACK_SIZE_ORDER)
+#define tsk_set_notify_resume(tsk) \
+ set_ti_thread_flag(task_thread_info(tsk), TIF_NOTIFY_RESUME)
+extern void tsk_clear_notify_resume(struct task_struct *tsk);
#endif /* !__ASSEMBLY */
/*
#define TIF_SYSCALL_AUDIT 3 /* syscall auditing active */
#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */
#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
-#define TIF_PERFMON_WORK 6 /* work for pfm_handle_work() */
+#define TIF_NOTIFY_RESUME 6 /* resumption notification requested */
#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */
#define TIF_MEMDIE 17
#define TIF_MCA_INIT 18 /* this task is processing MCA or INIT */
#define TIF_DB_DISABLED 19 /* debug trap disabled for fsyscall */
#define TIF_FREEZE 20 /* is freezing for suspend */
+#define TIF_RESTORE_RSE 21 /* user RBS is newer than kernel RBS */
#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
#define _TIF_SYSCALL_TRACEAUDIT (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP)
#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK)
-#define _TIF_PERFMON_WORK (1 << TIF_PERFMON_WORK)
+#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
#define _TIF_MCA_INIT (1 << TIF_MCA_INIT)
#define _TIF_DB_DISABLED (1 << TIF_DB_DISABLED)
#define _TIF_FREEZE (1 << TIF_FREEZE)
+#define _TIF_RESTORE_RSE (1 << TIF_RESTORE_RSE)
/* "work to do on user-return" bits */
-#define TIF_ALLWORK_MASK (_TIF_SIGPENDING|_TIF_PERFMON_WORK|_TIF_SYSCALL_AUDIT|\
+#define TIF_ALLWORK_MASK (_TIF_SIGPENDING|_TIF_NOTIFY_RESUME|_TIF_SYSCALL_AUDIT|\
_TIF_NEED_RESCHED| _TIF_SYSCALL_TRACE|\
_TIF_RESTORE_SIGMASK)
/* like TIF_ALLWORK_BITS but sans TIF_SYSCALL_TRACE or TIF_SYSCALL_AUDIT */
#define __NR_signalfd 1307
#define __NR_timerfd 1308
#define __NR_eventfd 1309
+#define __NR_timerfd_create 1310
+#define __NR_timerfd_settime 1311
+#define __NR_timerfd_gettime 1312
#ifdef __KERNEL__
-#define NR_syscalls 286 /* length of syscall table */
+#define NR_syscalls 289 /* length of syscall table */
/*
* The following defines stop scripts/checksyscalls.sh from complaining about
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-#ifdef __KERNEL__
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-
-#endif
-
#endif /* _ASM_M32R_A_OUT_H */
#define PTE_MASK PAGE_MASK
typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct page *pgtable_t;
#define pmd_val(x) ((x).pmd)
#define pgd_val(x) ((x).pgd)
#define _ASM_M32R_PARAM_H
#ifdef __KERNEL__
-# define HZ 100 /* Internal kernel timer frequency */
+# define HZ CONFIG_HZ /* Internal kernel timer frequency */
# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
#endif
set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte)))
static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
- struct page *pte)
+ pgtable_t pte)
{
set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte)));
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
/*
* Allocate and free page tables.
return pte;
}
-static __inline__ struct page *pte_alloc_one(struct mm_struct *mm,
+static __inline__ pgtable_t pte_alloc_one(struct mm_struct *mm,
unsigned long address)
{
struct page *pte = alloc_page(GFP_KERNEL|__GFP_ZERO);
-
+ pgtable_page_ctor(pte);
return pte;
}
free_page((unsigned long)pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
+ pgtable_page_dtor(pte);
__free_page(pte);
}
#endif
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
#undef __FD_SET
static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
}
}
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif /* _ASM_M32R_POSIX_TYPES_H */
#define TASK_SIZE (0x00400000UL)
#endif
+#ifdef __KERNEL__
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
+#endif
+
/* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
--- /dev/null
+/* a.out coredump register dumper
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_A_OUT_CORE_H
+#define _ASM_A_OUT_CORE_H
+
+#ifdef __KERNEL__
+
+#include <linux/user.h>
+#include <linux/elfcore.h>
+
+/*
+ * fill in the user structure for an a.out core dump
+ */
+static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
+{
+ struct switch_stack *sw;
+
+/* changed the size calculations - should hopefully work better. lbt */
+ dump->magic = CMAGIC;
+ dump->start_code = 0;
+ dump->start_stack = rdusp() & ~(PAGE_SIZE - 1);
+ dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
+ dump->u_dsize = ((unsigned long) (current->mm->brk +
+ (PAGE_SIZE-1))) >> PAGE_SHIFT;
+ dump->u_dsize -= dump->u_tsize;
+ dump->u_ssize = 0;
+
+ if (dump->start_stack < TASK_SIZE)
+ dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;
+
+ dump->u_ar0 = offsetof(struct user, regs);
+ sw = ((struct switch_stack *)regs) - 1;
+ dump->regs.d1 = regs->d1;
+ dump->regs.d2 = regs->d2;
+ dump->regs.d3 = regs->d3;
+ dump->regs.d4 = regs->d4;
+ dump->regs.d5 = regs->d5;
+ dump->regs.d6 = sw->d6;
+ dump->regs.d7 = sw->d7;
+ dump->regs.a0 = regs->a0;
+ dump->regs.a1 = regs->a1;
+ dump->regs.a2 = regs->a2;
+ dump->regs.a3 = sw->a3;
+ dump->regs.a4 = sw->a4;
+ dump->regs.a5 = sw->a5;
+ dump->regs.a6 = sw->a6;
+ dump->regs.d0 = regs->d0;
+ dump->regs.orig_d0 = regs->orig_d0;
+ dump->regs.stkadj = regs->stkadj;
+ dump->regs.sr = regs->sr;
+ dump->regs.pc = regs->pc;
+ dump->regs.fmtvec = (regs->format << 12) | regs->vector;
+ /* dump floating point stuff */
+ dump->u_fpvalid = dump_fpu (regs, &dump->m68kfp);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_A_OUT_CORE_H */
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-#ifdef __KERNEL__
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-
-#endif
-
#endif /* __M68K_A_OUT_H__ */
extern pmd_t *get_pointer_table(void);
extern int free_pointer_table(pmd_t *);
-
static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
{
pte_t *pte;
free_page((unsigned long) pte);
}
-static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
pte_t *pte;
nocache_page(pte);
}
kunmap(pte);
-
+ pgtable_page_ctor(page);
return page;
}
-static inline void pte_free(struct mm_struct *mm, struct page *page)
+static inline void pte_free(struct mm_struct *mm, pgtable_t page)
{
+ pgtable_page_dtor(page);
cache_page(kmap(page));
kunmap(page);
__free_page(page);
}
-static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *page)
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t page)
{
+ pgtable_page_dtor(page);
cache_page(kmap(page));
kunmap(page);
__free_page(page);
pmd_set(pmd, pte);
}
-static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *page)
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page)
{
pmd_set(pmd, page_address(page));
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pmd_t *pmd)
{
typedef struct { unsigned long pmd[16]; } pmd_t;
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct page *pgtable_t;
#define pte_val(x) ((x).pte)
#define pmd_val(x) ((&x)->pmd[0])
#define _M68K_PARAM_H
#ifdef __KERNEL__
-# define HZ 100 /* Internal kernel timer frequency */
+# define HZ CONFIG_HZ /* Internal kernel timer frequency */
# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
#endif
#endif
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
#undef __FD_SET
#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
#undef __FD_ZERO
#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif
#define TASK_SIZE (0x0E000000UL)
#endif
+#ifdef __KERNEL__
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
+#endif
+
/* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
free_page((unsigned long) pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *page)
+static inline void pte_free(struct mm_struct *mm, pgtable_t page)
{
+ pgtable_page_dtor(page);
__free_page(page);
}
-#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
+#define __pte_free_tlb(tlb,pte) \
+do { \
+ pgtable_page_dtor(pte); \
+ tlb_remove_page((tlb), pte); \
+} while (0)
static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
unsigned long address)
return (pte_t *) (page);
}
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+ unsigned long address)
{
struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0);
return NULL;
clear_highpage(page);
+ pgtable_page_ctor(page);
return page;
}
pmd_val(*pmd) = __pa((unsigned long)pte);
}
-static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *page)
+static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page)
{
pmd_val(*pmd) = __pa((unsigned long)page_address(page));
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
/*
* allocating and freeing a pmd is trivial: the 1-entry pmd is
#ifndef _M68KNOMMU_PARAM_H
#define _M68KNOMMU_PARAM_H
-
-#if defined(CONFIG_CLEOPATRA)
-#define HZ 1000
-#endif
-#ifndef HZ
-#define HZ 100
-#endif
+#define HZ CONFIG_HZ
#ifdef __KERNEL__
#define USER_HZ HZ
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-#ifdef __KERNEL__
-
-#ifdef CONFIG_32BIT
-#define STACK_TOP TASK_SIZE
-#endif
-#ifdef CONFIG_64BIT
-#define STACK_TOP \
- (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
-#endif
-#define STACK_TOP_MAX TASK_SIZE
-
-#endif
-
#endif /* _ASM_A_OUT_H */
#define pte_val(x) ((x).pte)
#define __pte(x) ((pte_t) { (x) } )
#endif
+typedef struct page *pgtable_t;
/*
* For 3-level pagetables we defines these ourselves, for 2-level the
}
static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
- struct page *pte)
+ pgtable_t pte)
{
set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
/*
* Initialize a new pmd table with invalid pointers.
struct page *pte;
pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER);
- if (pte)
+ if (pte) {
clear_highpage(pte);
-
+ pgtable_page_ctor(pte);
+ }
return pte;
}
free_pages((unsigned long)pte, PTE_ORDER);
}
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
+ pgtable_page_dtor(pte);
__free_pages(pte, PTE_ORDER);
}
-#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte))
+#define __pte_free_tlb(tlb,pte) \
+do { \
+ pgtable_page_dtor(pte); \
+ tlb_remove_page((tlb), pte); \
+} while (0)
#ifdef CONFIG_32BIT
#endif
} __kernel_fsid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
#undef __FD_SET
static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
}
}
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif /* _ASM_POSIX_TYPES_H */
* so don't change it unless you know what you are doing.
*/
#define TASK_SIZE 0x7fff8000UL
+#define STACK_TOP TASK_SIZE
/*
* This decides where the kernel will search for a free chunk of vm
*/
#define TASK_SIZE32 0x7fff8000UL
#define TASK_SIZE 0x10000000000UL
+#define STACK_TOP \
+ (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
/*
* This decides where the kernel will search for a free chunk of vm
(test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
#endif
+#ifdef __KERNEL__
+#define STACK_TOP_MAX TASK_SIZE
+#endif
+
#define NUM_FPU_REGS 32
typedef __u64 fpureg_t;
--- /dev/null
+proc
+unit
--- /dev/null
+include include/asm-generic/Kbuild.asm
+
+unifdef-y += termios.h
+unifdef-y += ptrace.h
+unifdef-y += page.h
--- /dev/null
+/* MN10300 Atomic counter operations
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_ATOMIC_H
+#define _ASM_ATOMIC_H
+
+#ifdef CONFIG_SMP
+#error not SMP safe
+#endif
+
+/*
+ * Atomic operations that C can't guarantee us. Useful for
+ * resource counting etc..
+ */
+
+/*
+ * Make sure gcc doesn't try to be clever and move things around
+ * on us. We need to use _exactly_ the address the user gave us,
+ * not some alias that contains the same information.
+ */
+typedef struct {
+ int counter;
+} atomic_t;
+
+#define ATOMIC_INIT(i) { (i) }
+
+#ifdef __KERNEL__
+
+/**
+ * atomic_read - read atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically reads the value of @v. Note that the guaranteed
+ * useful range of an atomic_t is only 24 bits.
+ */
+#define atomic_read(v) ((v)->counter)
+
+/**
+ * atomic_set - set atomic variable
+ * @v: pointer of type atomic_t
+ * @i: required value
+ *
+ * Atomically sets the value of @v to @i. Note that the guaranteed
+ * useful range of an atomic_t is only 24 bits.
+ */
+#define atomic_set(v, i) (((v)->counter) = (i))
+
+#include <asm/system.h>
+
+/**
+ * atomic_add_return - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v and returns the result
+ * Note that the guaranteed useful range of an atomic_t is only 24 bits.
+ */
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+ unsigned long flags;
+ int temp;
+
+ local_irq_save(flags);
+ temp = v->counter;
+ temp += i;
+ v->counter = temp;
+ local_irq_restore(flags);
+
+ return temp;
+}
+
+/**
+ * atomic_sub_return - subtract integer from atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v and returns the result
+ * Note that the guaranteed useful range of an atomic_t is only 24 bits.
+ */
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+ unsigned long flags;
+ int temp;
+
+ local_irq_save(flags);
+ temp = v->counter;
+ temp -= i;
+ v->counter = temp;
+ local_irq_restore(flags);
+
+ return temp;
+}
+
+static inline int atomic_add_negative(int i, atomic_t *v)
+{
+ return atomic_add_return(i, v) < 0;
+}
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+ atomic_add_return(i, v);
+}
+
+static inline void atomic_sub(int i, atomic_t *v)
+{
+ atomic_sub_return(i, v);
+}
+
+static inline void atomic_inc(atomic_t *v)
+{
+ atomic_add_return(1, v);
+}
+
+static inline void atomic_dec(atomic_t *v)
+{
+ atomic_sub_return(1, v);
+}
+
+#define atomic_dec_return(v) atomic_sub_return(1, (v))
+#define atomic_inc_return(v) atomic_add_return(1, (v))
+
+#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
+#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
+#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
+
+#define atomic_add_unless(v, a, u) \
+({ \
+ int c, old; \
+ c = atomic_read(v); \
+ while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
+ c = old; \
+ c != (u); \
+})
+
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+{
+ unsigned long flags;
+
+ mask = ~mask;
+ local_irq_save(flags);
+ *addr &= mask;
+ local_irq_restore(flags);
+}
+
+#define atomic_xchg(ptr, v) (xchg(&(ptr)->counter, (v)))
+#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
+
+/* Atomic operations are already serializing on MN10300??? */
+#define smp_mb__before_atomic_dec() barrier()
+#define smp_mb__after_atomic_dec() barrier()
+#define smp_mb__before_atomic_inc() barrier()
+#define smp_mb__after_atomic_inc() barrier()
+
+#include <asm-generic/atomic.h>
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_ATOMIC_H */
--- /dev/null
+#ifndef _ASM_AUXVEC_H
+#define _ASM_AUXVEC_H
+
+#endif
--- /dev/null
+/* MN10300 bit operations
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ *
+ * These have to be done with inline assembly: that way the bit-setting
+ * is guaranteed to be atomic. All bit operations return 0 if the bit
+ * was cleared before the operation and != 0 if it was not.
+ *
+ * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
+ */
+#ifndef __ASM_BITOPS_H
+#define __ASM_BITOPS_H
+
+#include <asm/cpu-regs.h>
+
+#define smp_mb__before_clear_bit() barrier()
+#define smp_mb__after_clear_bit() barrier()
+
+/*
+ * set bit
+ */
+#define __set_bit(nr, addr) \
+({ \
+ volatile unsigned char *_a = (unsigned char *)(addr); \
+ const unsigned shift = (nr) & 7; \
+ _a += (nr) >> 3; \
+ \
+ asm volatile("bset %2,(%1) # set_bit reg" \
+ : "=m"(*_a) \
+ : "a"(_a), "d"(1 << shift), "m"(*_a) \
+ : "memory", "cc"); \
+})
+
+#define set_bit(nr, addr) __set_bit((nr), (addr))
+
+/*
+ * clear bit
+ */
+#define ___clear_bit(nr, addr) \
+({ \
+ volatile unsigned char *_a = (unsigned char *)(addr); \
+ const unsigned shift = (nr) & 7; \
+ _a += (nr) >> 3; \
+ \
+ asm volatile("bclr %2,(%1) # clear_bit reg" \
+ : "=m"(*_a) \
+ : "a"(_a), "d"(1 << shift), "m"(*_a) \
+ : "memory", "cc"); \
+})
+
+#define clear_bit(nr, addr) ___clear_bit((nr), (addr))
+
+
+static inline void __clear_bit(int nr, volatile void *addr)
+{
+ unsigned int *a = (unsigned int *) addr;
+ int mask;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ *a &= ~mask;
+}
+
+/*
+ * test bit
+ */
+static inline int test_bit(int nr, const volatile void *addr)
+{
+ return 1UL & (((const unsigned int *) addr)[nr >> 5] >> (nr & 31));
+}
+
+/*
+ * change bit
+ */
+static inline void __change_bit(int nr, volatile void *addr)
+{
+ int mask;
+ unsigned int *a = (unsigned int *) addr;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ *a ^= mask;
+}
+
+extern void change_bit(int nr, volatile void *addr);
+
+/*
+ * test and set bit
+ */
+#define __test_and_set_bit(nr,addr) \
+({ \
+ volatile unsigned char *_a = (unsigned char *)(addr); \
+ const unsigned shift = (nr) & 7; \
+ unsigned epsw; \
+ _a += (nr) >> 3; \
+ \
+ asm volatile("bset %3,(%2) # test_set_bit reg\n" \
+ "mov epsw,%1" \
+ : "=m"(*_a), "=d"(epsw) \
+ : "a"(_a), "d"(1 << shift), "m"(*_a) \
+ : "memory", "cc"); \
+ \
+ !(epsw & EPSW_FLAG_Z); \
+})
+
+#define test_and_set_bit(nr, addr) __test_and_set_bit((nr), (addr))
+
+/*
+ * test and clear bit
+ */
+#define __test_and_clear_bit(nr, addr) \
+({ \
+ volatile unsigned char *_a = (unsigned char *)(addr); \
+ const unsigned shift = (nr) & 7; \
+ unsigned epsw; \
+ _a += (nr) >> 3; \
+ \
+ asm volatile("bclr %3,(%2) # test_clear_bit reg\n" \
+ "mov epsw,%1" \
+ : "=m"(*_a), "=d"(epsw) \
+ : "a"(_a), "d"(1 << shift), "m"(*_a) \
+ : "memory", "cc"); \
+ \
+ !(epsw & EPSW_FLAG_Z); \
+})
+
+#define test_and_clear_bit(nr, addr) __test_and_clear_bit((nr), (addr))
+
+/*
+ * test and change bit
+ */
+static inline int __test_and_change_bit(int nr, volatile void *addr)
+{
+ int mask, retval;
+ unsigned int *a = (unsigned int *)addr;
+
+ a += nr >> 5;
+ mask = 1 << (nr & 0x1f);
+ retval = (mask & *a) != 0;
+ *a ^= mask;
+
+ return retval;
+}
+
+extern int test_and_change_bit(int nr, volatile void *addr);
+
+#include <asm-generic/bitops/lock.h>
+
+#ifdef __KERNEL__
+
+/**
+ * __ffs - find first bit set
+ * @x: the word to search
+ *
+ * - return 31..0 to indicate bit 31..0 most least significant bit set
+ * - if no bits are set in x, the result is undefined
+ */
+static inline __attribute__((const))
+unsigned long __ffs(unsigned long x)
+{
+ int bit;
+ asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(x & -x));
+ return bit;
+}
+
+/*
+ * special slimline version of fls() for calculating ilog2_u32()
+ * - note: no protection against n == 0
+ */
+static inline __attribute__((const))
+int __ilog2_u32(u32 n)
+{
+ int bit;
+ asm("bsch %2,%0" : "=r"(bit) : "0"(0), "r"(n));
+ return bit;
+}
+
+/**
+ * fls - find last bit set
+ * @x: the word to search
+ *
+ * This is defined the same way as ffs:
+ * - return 32..1 to indicate bit 31..0 most significant bit set
+ * - return 0 to indicate no bits set
+ */
+static inline __attribute__((const))
+int fls(int x)
+{
+ return (x != 0) ? __ilog2_u32(x) + 1 : 0;
+}
+
+/**
+ * ffs - find first bit set
+ * @x: the word to search
+ *
+ * - return 32..1 to indicate bit 31..0 most least significant bit set
+ * - return 0 to indicate no bits set
+ */
+static inline __attribute__((const))
+int ffs(int x)
+{
+ /* Note: (x & -x) gives us a mask that is the least significant
+ * (rightmost) 1-bit of the value in x.
+ */
+ return fls(x & -x);
+}
+
+#include <asm-generic/bitops/ffz.h>
+#include <asm-generic/bitops/fls64.h>
+#include <asm-generic/bitops/find.h>
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/hweight.h>
+
+#define ext2_set_bit_atomic(lock, nr, addr) \
+ test_and_set_bit((nr) ^ 0x18, (addr))
+#define ext2_clear_bit_atomic(lock, nr, addr) \
+ test_and_clear_bit((nr) ^ 0x18, (addr))
+
+#include <asm-generic/bitops/ext2-non-atomic.h>
+#include <asm-generic/bitops/minix-le.h>
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_BITOPS_H */
--- /dev/null
+/* MN10300 Kernel bug reporting
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_BUG_H
+#define _ASM_BUG_H
+
+/*
+ * Tell the user there is some problem.
+ */
+#define _debug_bug_trap() \
+do { \
+ asm volatile( \
+ " syscall 15 \n" \
+ "0: \n" \
+ " .section __bug_table,\"a\" \n" \
+ " .long 0b,%0,%1 \n" \
+ " .previous \n" \
+ : \
+ : "i"(__FILE__), "i"(__LINE__) \
+ ); \
+} while (0)
+
+#define BUG() _debug_bug_trap()
+
+#define HAVE_ARCH_BUG
+#include <asm-generic/bug.h>
+
+#endif /* _ASM_BUG_H */
--- /dev/null
+/* MN10300 Checks for architecture-dependent bugs
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_BUGS_H
+#define _ASM_BUGS_H
+
+#include <asm/processor.h>
+
+static inline void __init check_bugs(void)
+{
+}
+
+#endif /* _ASM_BUGS_H */
--- /dev/null
+/* AM33v2 on-board bus controller registers
+ *
+ * Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_BUSCTL_REGS_H
+#define _ASM_BUSCTL_REGS_H
+
+#include <asm/cpu-regs.h>
+
+#ifdef __KERNEL__
+
+/* bus controller registers */
+#define BCCR __SYSREG(0xc0002000, u32) /* bus controller control reg */
+#define BCCR_B0AD 0x00000003 /* block 0 (80000000-83ffffff) bus allocation */
+#define BCCR_B1AD 0x0000000c /* block 1 (84000000-87ffffff) bus allocation */
+#define BCCR_B2AD 0x00000030 /* block 2 (88000000-8bffffff) bus allocation */
+#define BCCR_B3AD 0x000000c0 /* block 3 (8c000000-8fffffff) bus allocation */
+#define BCCR_B4AD 0x00000300 /* block 4 (90000000-93ffffff) bus allocation */
+#define BCCR_B5AD 0x00000c00 /* block 5 (94000000-97ffffff) bus allocation */
+#define BCCR_B6AD 0x00003000 /* block 6 (98000000-9bffffff) bus allocation */
+#define BCCR_B7AD 0x0000c000 /* block 7 (9c000000-9fffffff) bus allocation */
+#define BCCR_BxAD_EXBUS 0x0 /* - direct to system bus controller */
+#define BCCR_BxAD_OPEXBUS 0x1 /* - direct to memory bus controller */
+#define BCCR_BxAD_OCMBUS 0x2 /* - direct to on chip memory */
+#define BCCR_API 0x00070000 /* bus arbitration priority */
+#define BCCR_API_DMACICD 0x00000000 /* - DMA > CI > CD */
+#define BCCR_API_DMACDCI 0x00010000 /* - DMA > CD > CI */
+#define BCCR_API_CICDDMA 0x00020000 /* - CI > CD > DMA */
+#define BCCR_API_CDCIDMA 0x00030000 /* - CD > CI > DMA */
+#define BCCR_API_ROUNDROBIN 0x00040000 /* - round robin */
+#define BCCR_BEPRI_DMACICD 0x00c00000 /* bus error address priority */
+#define BCCR_BEPRI_DMACDCI 0x00000000 /* - DMA > CI > CD */
+#define BCCR_BEPRI_CICDDMA 0x00400000 /* - DMA > CD > CI */
+#define BCCR_BEPRI_CDCIDMA 0x00800000 /* - CI > CD > DMA */
+#define BCCR_BEPRI 0x00c00000 /* - CD > CI > DMA */
+#define BCCR_TMON 0x03000000 /* timeout value settings */
+#define BCCR_TMON_16IOCLK 0x00000000 /* - 16 IOCLK cycles */
+#define BCCR_TMON_256IOCLK 0x01000000 /* - 256 IOCLK cycles */
+#define BCCR_TMON_4096IOCLK 0x02000000 /* - 4096 IOCLK cycles */
+#define BCCR_TMON_65536IOCLK 0x03000000 /* - 65536 IOCLK cycles */
+#define BCCR_TMOE 0x10000000 /* timeout detection enable */
+
+#define BCBERR __SYSREG(0xc0002010, u32) /* bus error source reg */
+#define BCBERR_BESB 0x0000001f /* erroneous access destination space */
+#define BCBERR_BESB_MON 0x00000001 /* - monitor space */
+#define BCBERR_BESB_IO 0x00000002 /* - IO bus */
+#define BCBERR_BESB_EX 0x00000004 /* - EX bus */
+#define BCBERR_BESB_OPEX 0x00000008 /* - OpEX bus */
+#define BCBERR_BESB_OCM 0x00000010 /* - on chip memory */
+#define BCBERR_BERW 0x00000100 /* type of access */
+#define BCBERR_BERW_WRITE 0x00000000 /* - write */
+#define BCBERR_BERW_READ 0x00000100 /* - read */
+#define BCBERR_BESD 0x00000200 /* error detector */
+#define BCBERR_BESD_BCU 0x00000000 /* - BCU detected error */
+#define BCBERR_BESD_SLAVE_BUS 0x00000200 /* - slave bus detected error */
+#define BCBERR_BEBST 0x00000400 /* type of access */
+#define BCBERR_BEBST_SINGLE 0x00000000 /* - single */
+#define BCBERR_BEBST_BURST 0x00000400 /* - burst */
+#define BCBERR_BEME 0x00000800 /* multiple bus error flag */
+#define BCBERR_BEMR 0x00007000 /* master bus that caused the error */
+#define BCBERR_BEMR_NOERROR 0x00000000 /* - no error */
+#define BCBERR_BEMR_CI 0x00001000 /* - CPU instruction fetch bus caused error */
+#define BCBERR_BEMR_CD 0x00002000 /* - CPU data bus caused error */
+#define BCBERR_BEMR_DMA 0x00004000 /* - DMA bus caused error */
+
+#define BCBEAR __SYSREGC(0xc0002020, u32) /* bus error address reg */
+
+/* system bus controller registers */
+#define SBBASE(X) __SYSREG(0xd8c00100 + (X) * 0x10, u32) /* SBC base addr regs */
+#define SBBASE_BE 0x00000001 /* bank enable */
+#define SBBASE_BAM 0x0000fffe /* bank address mask [31:17] */
+#define SBBASE_BBA 0xfffe0000 /* bank base address [31:17] */
+
+#define SBCNTRL0(X) __SYSREG(0xd8c00200 + (X) * 0x10, u32) /* SBC bank ctrl0 regs */
+#define SBCNTRL0_WEH 0x00000f00 /* write enable hold */
+#define SBCNTRL0_REH 0x0000f000 /* read enable hold */
+#define SBCNTRL0_RWH 0x000f0000 /* SRW signal hold */
+#define SBCNTRL0_CSH 0x00f00000 /* chip select hold */
+#define SBCNTRL0_DAH 0x0f000000 /* data hold */
+#define SBCNTRL0_ADH 0xf0000000 /* address hold */
+
+#define SBCNTRL1(X) __SYSREG(0xd8c00204 + (X) * 0x10, u32) /* SBC bank ctrl1 regs */
+#define SBCNTRL1_WED 0x00000f00 /* write enable delay */
+#define SBCNTRL1_RED 0x0000f000 /* read enable delay */
+#define SBCNTRL1_RWD 0x000f0000 /* SRW signal delay */
+#define SBCNTRL1_ASW 0x00f00000 /* address strobe width */
+#define SBCNTRL1_CSD 0x0f000000 /* chip select delay */
+#define SBCNTRL1_ASD 0xf0000000 /* address strobe delay */
+
+#define SBCNTRL2(X) __SYSREG(0xd8c00208 + (X) * 0x10, u32) /* SBC bank ctrl2 regs */
+#define SBCNTRL2_WC 0x000000ff /* wait count */
+#define SBCNTRL2_BWC 0x00000f00 /* burst wait count */
+#define SBCNTRL2_WM 0x01000000 /* wait mode setting */
+#define SBCNTRL2_WM_FIXEDWAIT 0x00000000 /* - fixed wait access */
+#define SBCNTRL2_WM_HANDSHAKE 0x01000000 /* - handshake access */
+#define SBCNTRL2_BM 0x02000000 /* bus synchronisation mode */
+#define SBCNTRL2_BM_SYNC 0x00000000 /* - synchronous mode */
+#define SBCNTRL2_BM_ASYNC 0x02000000 /* - asynchronous mode */
+#define SBCNTRL2_BW 0x04000000 /* bus width */
+#define SBCNTRL2_BW_32 0x00000000 /* - 32 bits */
+#define SBCNTRL2_BW_16 0x04000000 /* - 16 bits */
+#define SBCNTRL2_RWINV 0x08000000 /* R/W signal invert polarity */
+#define SBCNTRL2_RWINV_NORM 0x00000000 /* - normal (read high) */
+#define SBCNTRL2_RWINV_INV 0x08000000 /* - inverted (read low) */
+#define SBCNTRL2_BT 0x70000000 /* bus type setting */
+#define SBCNTRL2_BT_SRAM 0x00000000 /* - SRAM interface */
+#define SBCNTRL2_BT_ADMUX 0x00000000 /* - addr/data multiplexed interface */
+#define SBCNTRL2_BT_BROM 0x00000000 /* - burst ROM interface */
+#define SBCNTRL2_BTSE 0x80000000 /* burst enable */
+
+/* memory bus controller */
+#define SDBASE(X) __SYSREG(0xda000008 + (X) * 0x4, u32) /* MBC base addr regs */
+#define SDBASE_CE 0x00000001 /* chip enable */
+#define SDBASE_CBAM 0x0000fff0 /* chip base address mask [31:20] */
+#define SDBASE_CBAM_SHIFT 16
+#define SDBASE_CBA 0xfff00000 /* chip base address [31:20] */
+
+#define SDRAMBUS __SYSREG(0xda000000, u32) /* bus mode control reg */
+#define SDRAMBUS_REFEN 0x00000004 /* refresh enable */
+#define SDRAMBUS_TRC 0x00000018 /* refresh command delay time */
+#define SDRAMBUS_BSTPT 0x00000020 /* burst stop command enable */
+#define SDRAMBUS_PONSEQ 0x00000040 /* power on sequence */
+#define SDRAMBUS_SELFREQ 0x00000080 /* self-refresh mode request */
+#define SDRAMBUS_SELFON 0x00000100 /* self-refresh mode on */
+#define SDRAMBUS_SIZE 0x00030000 /* SDRAM size */
+#define SDRAMBUS_SIZE_64Mbit 0x00010000 /* 64Mbit SDRAM (x16) */
+#define SDRAMBUS_SIZE_128Mbit 0x00020000 /* 128Mbit SDRAM (x16) */
+#define SDRAMBUS_SIZE_256Mbit 0x00030000 /* 256Mbit SDRAM (x16) */
+#define SDRAMBUS_TRASWAIT 0x000c0000 /* row address precharge command cycle number */
+#define SDRAMBUS_REFNUM 0x00300000 /* refresh command number */
+#define SDRAMBUS_BSTWAIT 0x00c00000 /* burst stop command cycle */
+#define SDRAMBUS_SETWAIT 0x03000000 /* mode register setting command cycle */
+#define SDRAMBUS_PREWAIT 0x0c000000 /* precharge command cycle */
+#define SDRAMBUS_RASLATE 0x30000000 /* RAS latency */
+#define SDRAMBUS_CASLATE 0xc0000000 /* CAS latency */
+
+#define SDREFCNT __SYSREG(0xda000004, u32) /* refresh period reg */
+#define SDREFCNT_PERI 0x00000fff /* refresh period */
+
+#define SDSHDW __SYSREG(0xda000010, u32) /* test reg */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_BUSCTL_REGS_H */
--- /dev/null
+/* MN10300 Byte-order primitive construction
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_BYTEORDER_H
+#define _ASM_BYTEORDER_H
+
+#include <asm/types.h>
+
+#ifdef __GNUC__
+
+static inline __attribute__((const))
+__u32 ___arch__swab32(__u32 x)
+{
+ __u32 ret;
+ asm("swap %1,%0" : "=r" (ret) : "r" (x));
+ return ret;
+}
+
+static inline __attribute__((const))
+__u16 ___arch__swab16(__u16 x)
+{
+ __u16 ret;
+ asm("swaph %1,%0" : "=r" (ret) : "r" (x));
+ return ret;
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+# define __BYTEORDER_HAS_U64__
+# define __SWAB_64_THRU_32__
+#endif
+
+#endif /* __GNUC__ */
+
+#include <linux/byteorder/little_endian.h>
+
+#endif /* _ASM_BYTEORDER_H */
--- /dev/null
+/* MN10300 cache management registers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_CACHE_H
+#define _ASM_CACHE_H
+
+#include <asm/cpu-regs.h>
+#include <asm/proc/cache.h>
+
+#ifndef __ASSEMBLY__
+#define L1_CACHE_DISPARITY (L1_CACHE_NENTRIES * L1_CACHE_BYTES)
+#else
+#define L1_CACHE_DISPARITY L1_CACHE_NENTRIES * L1_CACHE_BYTES
+#endif
+
+/* data cache purge registers
+ * - read from the register to unconditionally purge that cache line
+ * - write address & 0xffffff00 to conditionally purge that cache line
+ * - clear LSB to request invalidation as well
+ */
+#define DCACHE_PURGE(WAY, ENTRY) \
+ __SYSREG(0xc8400000 + (WAY) * L1_CACHE_WAYDISP + \
+ (ENTRY) * L1_CACHE_BYTES, u32)
+
+#define DCACHE_PURGE_WAY0(ENTRY) \
+ __SYSREG(0xc8400000 + 0 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
+#define DCACHE_PURGE_WAY1(ENTRY) \
+ __SYSREG(0xc8400000 + 1 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
+#define DCACHE_PURGE_WAY2(ENTRY) \
+ __SYSREG(0xc8400000 + 2 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
+#define DCACHE_PURGE_WAY3(ENTRY) \
+ __SYSREG(0xc8400000 + 3 * L1_CACHE_WAYDISP + (ENTRY) * L1_CACHE_BYTES, u32)
+
+/* instruction cache access registers */
+#define ICACHE_DATA(WAY, ENTRY, OFF) \
+ __SYSREG(0xc8000000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
+#define ICACHE_TAG(WAY, ENTRY) \
+ __SYSREG(0xc8100000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
+
+/* instruction cache access registers */
+#define DCACHE_DATA(WAY, ENTRY, OFF) \
+ __SYSREG(0xc8200000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10 + (OFF) * 4, u32)
+#define DCACHE_TAG(WAY, ENTRY) \
+ __SYSREG(0xc8300000 + (WAY) * L1_CACHE_WAYDISP + (ENTRY) * 0x10, u32)
+
+#endif /* _ASM_CACHE_H */
--- /dev/null
+/* MN10300 Cache flushing
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_CACHEFLUSH_H
+#define _ASM_CACHEFLUSH_H
+
+#ifndef __ASSEMBLY__
+
+/* Keep includes the same across arches. */
+#include <linux/mm.h>
+
+/*
+ * virtually-indexed cache managment (our cache is physically indexed)
+ */
+#define flush_cache_all() do {} while (0)
+#define flush_cache_mm(mm) do {} while (0)
+#define flush_cache_dup_mm(mm) do {} while (0)
+#define flush_cache_range(mm, start, end) do {} while (0)
+#define flush_cache_page(vma, vmaddr, pfn) do {} while (0)
+#define flush_cache_vmap(start, end) do {} while (0)
+#define flush_cache_vunmap(start, end) do {} while (0)
+#define flush_dcache_page(page) do {} while (0)
+#define flush_dcache_mmap_lock(mapping) do {} while (0)
+#define flush_dcache_mmap_unlock(mapping) do {} while (0)
+
+/*
+ * physically-indexed cache managment
+ */
+#ifndef CONFIG_MN10300_CACHE_DISABLED
+
+extern void flush_icache_range(unsigned long start, unsigned long end);
+extern void flush_icache_page(struct vm_area_struct *vma, struct page *pg);
+
+#else
+
+#define flush_icache_range(start, end) do {} while (0)
+#define flush_icache_page(vma, pg) do {} while (0)
+
+#endif
+
+#define flush_icache_user_range(vma, pg, adr, len) \
+ flush_icache_range(adr, adr + len)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+ do { \
+ memcpy(dst, src, len); \
+ flush_icache_page(vma, page); \
+ } while (0)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+ memcpy(dst, src, len)
+
+/*
+ * primitive routines
+ */
+#ifndef CONFIG_MN10300_CACHE_DISABLED
+extern void mn10300_icache_inv(void);
+extern void mn10300_dcache_inv(void);
+extern void mn10300_dcache_inv_page(unsigned start);
+extern void mn10300_dcache_inv_range(unsigned start, unsigned end);
+extern void mn10300_dcache_inv_range2(unsigned start, unsigned size);
+#ifdef CONFIG_MN10300_CACHE_WBACK
+extern void mn10300_dcache_flush(void);
+extern void mn10300_dcache_flush_page(unsigned start);
+extern void mn10300_dcache_flush_range(unsigned start, unsigned end);
+extern void mn10300_dcache_flush_range2(unsigned start, unsigned size);
+extern void mn10300_dcache_flush_inv(void);
+extern void mn10300_dcache_flush_inv_page(unsigned start);
+extern void mn10300_dcache_flush_inv_range(unsigned start, unsigned end);
+extern void mn10300_dcache_flush_inv_range2(unsigned start, unsigned size);
+#else
+#define mn10300_dcache_flush() do {} while (0)
+#define mn10300_dcache_flush_page(start) do {} while (0)
+#define mn10300_dcache_flush_range(start, end) do {} while (0)
+#define mn10300_dcache_flush_range2(start, size) do {} while (0)
+#define mn10300_dcache_flush_inv() mn10300_dcache_inv()
+#define mn10300_dcache_flush_inv_page(start) \
+ mn10300_dcache_inv_page((start))
+#define mn10300_dcache_flush_inv_range(start, end) \
+ mn10300_dcache_inv_range((start), (end))
+#define mn10300_dcache_flush_inv_range2(start, size) \
+ mn10300_dcache_inv_range2((start), (size))
+#endif /* CONFIG_MN10300_CACHE_WBACK */
+#else
+#define mn10300_icache_inv() do {} while (0)
+#define mn10300_dcache_inv() do {} while (0)
+#define mn10300_dcache_inv_page(start) do {} while (0)
+#define mn10300_dcache_inv_range(start, end) do {} while (0)
+#define mn10300_dcache_inv_range2(start, size) do {} while (0)
+#define mn10300_dcache_flush() do {} while (0)
+#define mn10300_dcache_flush_inv_page(start) do {} while (0)
+#define mn10300_dcache_flush_inv() do {} while (0)
+#define mn10300_dcache_flush_inv_range(start, end) do {} while (0)
+#define mn10300_dcache_flush_inv_range2(start, size) do {} while (0)
+#define mn10300_dcache_flush_page(start) do {} while (0)
+#define mn10300_dcache_flush_range(start, end) do {} while (0)
+#define mn10300_dcache_flush_range2(start, size) do {} while (0)
+#endif /* CONFIG_MN10300_CACHE_DISABLED */
+
+/*
+ * internal debugging function
+ */
+#ifdef CONFIG_DEBUG_PAGEALLOC
+extern void kernel_map_pages(struct page *page, int numpages, int enable);
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_CACHEFLUSH_H */
--- /dev/null
+/* MN10300 Optimised checksumming code
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_CHECKSUM_H
+#define _ASM_CHECKSUM_H
+
+extern __wsum csum_partial(const void *buff, int len, __wsum sum);
+extern __wsum csum_partial_copy_nocheck(const void *src, void *dst,
+ int len, __wsum sum);
+extern __wsum csum_partial_copy_from_user(const void *src, void *dst,
+ int len, __wsum sum,
+ int *err_ptr);
+extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
+extern __wsum csum_partial(const void *buff, int len, __wsum sum);
+extern __sum16 ip_compute_csum(const void *buff, int len);
+
+#define csum_partial_copy_fromuser csum_partial_copy
+extern __wsum csum_partial_copy(const void *src, void *dst, int len,
+ __wsum sum);
+
+static inline __sum16 csum_fold(__wsum sum)
+{
+ asm(
+ " add %1,%0 \n"
+ " addc 0xffff,%0 \n"
+ : "=r" (sum)
+ : "r" (sum << 16), "0" (sum & 0xffff0000)
+ : "cc"
+ );
+ return (~sum) >> 16;
+}
+
+static inline __wsum csum_tcpudp_nofold(unsigned long saddr,
+ unsigned long daddr,
+ unsigned short len,
+ unsigned short proto,
+ __wsum sum)
+{
+ __wsum tmp;
+
+ tmp = (__wsum) ntohs(len) << 16;
+ tmp += (__wsum) proto << 8;
+
+ asm(
+ " add %1,%0 \n"
+ " addc %2,%0 \n"
+ " addc %3,%0 \n"
+ " addc 0,%0 \n"
+ : "=r" (sum)
+ : "r" (daddr), "r"(saddr), "r"(tmp), "0"(sum)
+ : "cc"
+ );
+ return sum;
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline __sum16 csum_tcpudp_magic(unsigned long saddr,
+ unsigned long daddr,
+ unsigned short len,
+ unsigned short proto,
+ __wsum sum)
+{
+ return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
+}
+
+#undef _HAVE_ARCH_IPV6_CSUM
+
+/*
+ * Copy and checksum to user
+ */
+#define HAVE_CSUM_COPY_USER
+extern __wsum csum_and_copy_to_user(const void *src, void *dst, int len,
+ __wsum sum, int *err_ptr);
+
+
+#endif /* _ASM_CHECKSUM_H */
--- /dev/null
+/* MN10300 Core system registers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_CPU_REGS_H
+#define _ASM_CPU_REGS_H
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#endif
+
+#ifdef CONFIG_MN10300_CPU_AM33V2
+/* we tell the compiler to pretend to be AM33 so that it doesn't try and use
+ * the FP regs, but tell the assembler that we're actually allowed AM33v2
+ * instructions */
+#ifndef __ASSEMBLY__
+asm(" .am33_2\n");
+#else
+.am33_2
+#endif
+#endif
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+#define __SYSREG(ADDR, TYPE) (*(volatile TYPE *)(ADDR))
+#define __SYSREGC(ADDR, TYPE) (*(const volatile TYPE *)(ADDR))
+#else
+#define __SYSREG(ADDR, TYPE) ADDR
+#define __SYSREGC(ADDR, TYPE) ADDR
+#endif
+
+/* CPU registers */
+#define EPSW_FLAG_Z 0x00000001 /* zero flag */
+#define EPSW_FLAG_N 0x00000002 /* negative flag */
+#define EPSW_FLAG_C 0x00000004 /* carry flag */
+#define EPSW_FLAG_V 0x00000008 /* overflow flag */
+#define EPSW_IM 0x00000700 /* interrupt mode */
+#define EPSW_IM_0 0x00000000 /* interrupt mode 0 */
+#define EPSW_IM_1 0x00000100 /* interrupt mode 1 */
+#define EPSW_IM_2 0x00000200 /* interrupt mode 2 */
+#define EPSW_IM_3 0x00000300 /* interrupt mode 3 */
+#define EPSW_IM_4 0x00000400 /* interrupt mode 4 */
+#define EPSW_IM_5 0x00000500 /* interrupt mode 5 */
+#define EPSW_IM_6 0x00000600 /* interrupt mode 6 */
+#define EPSW_IM_7 0x00000700 /* interrupt mode 7 */
+#define EPSW_IE 0x00000800 /* interrupt enable */
+#define EPSW_S 0x00003000 /* software auxilliary bits */
+#define EPSW_T 0x00008000 /* trace enable */
+#define EPSW_nSL 0x00010000 /* not supervisor level */
+#define EPSW_NMID 0x00020000 /* nonmaskable interrupt disable */
+#define EPSW_nAR 0x00040000 /* register bank control */
+#define EPSW_ML 0x00080000 /* monitor level */
+#define EPSW_FE 0x00100000 /* FPU enable */
+
+/* FPU registers */
+#define FPCR_EF_I 0x00000001 /* inexact result FPU exception flag */
+#define FPCR_EF_U 0x00000002 /* underflow FPU exception flag */
+#define FPCR_EF_O 0x00000004 /* overflow FPU exception flag */
+#define FPCR_EF_Z 0x00000008 /* zero divide FPU exception flag */
+#define FPCR_EF_V 0x00000010 /* invalid operand FPU exception flag */
+#define FPCR_EE_I 0x00000020 /* inexact result FPU exception enable */
+#define FPCR_EE_U 0x00000040 /* underflow FPU exception enable */
+#define FPCR_EE_O 0x00000080 /* overflow FPU exception enable */
+#define FPCR_EE_Z 0x00000100 /* zero divide FPU exception enable */
+#define FPCR_EE_V 0x00000200 /* invalid operand FPU exception enable */
+#define FPCR_EC_I 0x00000400 /* inexact result FPU exception cause */
+#define FPCR_EC_U 0x00000800 /* underflow FPU exception cause */
+#define FPCR_EC_O 0x00001000 /* overflow FPU exception cause */
+#define FPCR_EC_Z 0x00002000 /* zero divide FPU exception cause */
+#define FPCR_EC_V 0x00004000 /* invalid operand FPU exception cause */
+#define FPCR_RM 0x00030000 /* rounding mode */
+#define FPCR_RM_NEAREST 0x00000000 /* - round to nearest value */
+#define FPCR_FCC_U 0x00040000 /* FPU unordered condition code */
+#define FPCR_FCC_E 0x00080000 /* FPU equal condition code */
+#define FPCR_FCC_G 0x00100000 /* FPU greater than condition code */
+#define FPCR_FCC_L 0x00200000 /* FPU less than condition code */
+#define FPCR_INIT 0x00000000 /* no exceptions, rounding to nearest */
+
+/* CPU control registers */
+#define CPUP __SYSREG(0xc0000020, u16) /* CPU pipeline register */
+#define CPUP_DWBD 0x0020 /* write buffer disable flag */
+#define CPUP_IPFD 0x0040 /* instruction prefetch disable flag */
+#define CPUP_EXM 0x0080 /* exception operation mode */
+#define CPUP_EXM_AM33V1 0x0000 /* - AM33 v1 exception mode */
+#define CPUP_EXM_AM33V2 0x0080 /* - AM33 v2 exception mode */
+
+#define CPUM __SYSREG(0xc0000040, u16) /* CPU mode register */
+#define CPUM_SLEEP 0x0004 /* set to enter sleep state */
+#define CPUM_HALT 0x0008 /* set to enter halt state */
+#define CPUM_STOP 0x0010 /* set to enter stop state */
+
+#define CPUREV __SYSREGC(0xc0000050, u32) /* CPU revision register */
+#define CPUREV_TYPE 0x0000000f /* CPU type */
+#define CPUREV_TYPE_S 0
+#define CPUREV_TYPE_AM33V1 0x00000000 /* - AM33 V1 core, AM33/1.00 arch */
+#define CPUREV_TYPE_AM33V2 0x00000001 /* - AM33 V2 core, AM33/2.00 arch */
+#define CPUREV_TYPE_AM34V1 0x00000002 /* - AM34 V1 core, AM33/2.00 arch */
+#define CPUREV_REVISION 0x000000f0 /* CPU revision */
+#define CPUREV_REVISION_S 4
+#define CPUREV_ICWAY 0x00000f00 /* number of instruction cache ways */
+#define CPUREV_ICWAY_S 8
+#define CPUREV_ICSIZE 0x0000f000 /* instruction cache way size */
+#define CPUREV_ICSIZE_S 12
+#define CPUREV_DCWAY 0x000f0000 /* number of data cache ways */
+#define CPUREV_DCWAY_S 16
+#define CPUREV_DCSIZE 0x00f00000 /* data cache way size */
+#define CPUREV_DCSIZE_S 20
+#define CPUREV_FPUTYPE 0x0f000000 /* FPU core type */
+#define CPUREV_FPUTYPE_NONE 0x00000000 /* - no FPU core implemented */
+#define CPUREV_OCDCTG 0xf0000000 /* on-chip debug function category */
+
+#define DCR __SYSREG(0xc0000030, u16) /* Debug control register */
+
+/* interrupt/exception control registers */
+#define IVAR0 __SYSREG(0xc0000000, u16) /* interrupt vector 0 */
+#define IVAR1 __SYSREG(0xc0000004, u16) /* interrupt vector 1 */
+#define IVAR2 __SYSREG(0xc0000008, u16) /* interrupt vector 2 */
+#define IVAR3 __SYSREG(0xc000000c, u16) /* interrupt vector 3 */
+#define IVAR4 __SYSREG(0xc0000010, u16) /* interrupt vector 4 */
+#define IVAR5 __SYSREG(0xc0000014, u16) /* interrupt vector 5 */
+#define IVAR6 __SYSREG(0xc0000018, u16) /* interrupt vector 6 */
+
+#define TBR __SYSREG(0xc0000024, u32) /* Trap table base */
+#define TBR_TB 0xff000000 /* table base address bits 31-24 */
+#define TBR_INT_CODE 0x00ffffff /* interrupt code */
+
+#define DEAR __SYSREG(0xc0000038, u32) /* Data access exception address */
+
+#define sISR __SYSREG(0xc0000044, u32) /* Supervisor interrupt status */
+#define sISR_IRQICE 0x00000001 /* ICE interrupt */
+#define sISR_ISTEP 0x00000002 /* single step interrupt */
+#define sISR_MISSA 0x00000004 /* memory access address misalignment fault */
+#define sISR_UNIMP 0x00000008 /* unimplemented instruction execution fault */
+#define sISR_PIEXE 0x00000010 /* program interrupt */
+#define sISR_MEMERR 0x00000020 /* illegal memory access fault */
+#define sISR_IBREAK 0x00000040 /* instraction break interrupt */
+#define sISR_DBSRL 0x00000080 /* debug serial interrupt */
+#define sISR_PERIDB 0x00000100 /* peripheral debug interrupt */
+#define sISR_EXUNIMP 0x00000200 /* unimplemented ex-instruction execution fault */
+#define sISR_OBREAK 0x00000400 /* operand break interrupt */
+#define sISR_PRIV 0x00000800 /* privileged instruction execution fault */
+#define sISR_BUSERR 0x00001000 /* bus error fault */
+#define sISR_DBLFT 0x00002000 /* double fault */
+#define sISR_DBG 0x00008000 /* debug reserved interrupt */
+#define sISR_ITMISS 0x00010000 /* instruction TLB miss */
+#define sISR_DTMISS 0x00020000 /* data TLB miss */
+#define sISR_ITEX 0x00040000 /* instruction TLB access exception */
+#define sISR_DTEX 0x00080000 /* data TLB access exception */
+#define sISR_ILGIA 0x00100000 /* illegal instruction access exception */
+#define sISR_ILGDA 0x00200000 /* illegal data access exception */
+#define sISR_IOIA 0x00400000 /* internal I/O space instruction access excep */
+#define sISR_PRIVA 0x00800000 /* privileged space instruction access excep */
+#define sISR_PRIDA 0x01000000 /* privileged space data access excep */
+#define sISR_DISA 0x02000000 /* data space instruction access excep */
+#define sISR_SYSC 0x04000000 /* system call instruction excep */
+#define sISR_FPUD 0x08000000 /* FPU disabled excep */
+#define sISR_FPUUI 0x10000000 /* FPU unimplemented instruction excep */
+#define sISR_FPUOP 0x20000000 /* FPU operation excep */
+#define sISR_NE 0x80000000 /* multiple synchronous exceptions excep */
+
+/* cache control registers */
+#define CHCTR __SYSREG(0xc0000070, u16) /* cache control */
+#define CHCTR_ICEN 0x0001 /* instruction cache enable */
+#define CHCTR_DCEN 0x0002 /* data cache enable */
+#define CHCTR_ICBUSY 0x0004 /* instruction cache busy */
+#define CHCTR_DCBUSY 0x0008 /* data cache busy */
+#define CHCTR_ICINV 0x0010 /* instruction cache invalidate */
+#define CHCTR_DCINV 0x0020 /* data cache invalidate */
+#define CHCTR_DCWTMD 0x0040 /* data cache writing mode */
+#define CHCTR_DCWTMD_WRBACK 0x0000 /* - write back mode */
+#define CHCTR_DCWTMD_WRTHROUGH 0x0040 /* - write through mode */
+#define CHCTR_DCALMD 0x0080 /* data cache allocation mode */
+#define CHCTR_ICWMD 0x0f00 /* instruction cache way mode */
+#define CHCTR_DCWMD 0xf000 /* data cache way mode */
+
+/* MMU control registers */
+#define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */
+#define MMUCTR_IRP 0x0000003f /* instruction TLB replace pointer */
+#define MMUCTR_ITE 0x00000040 /* instruction TLB enable */
+#define MMUCTR_IIV 0x00000080 /* instruction TLB invalidate */
+#define MMUCTR_ITL 0x00000700 /* instruction TLB lock pointer */
+#define MMUCTR_ITL_NOLOCK 0x00000000 /* - no lock */
+#define MMUCTR_ITL_LOCK0 0x00000100 /* - entry 0 locked */
+#define MMUCTR_ITL_LOCK0_1 0x00000200 /* - entry 0-1 locked */
+#define MMUCTR_ITL_LOCK0_3 0x00000300 /* - entry 0-3 locked */
+#define MMUCTR_ITL_LOCK0_7 0x00000400 /* - entry 0-7 locked */
+#define MMUCTR_ITL_LOCK0_15 0x00000500 /* - entry 0-15 locked */
+#define MMUCTR_CE 0x00008000 /* cacheable bit enable */
+#define MMUCTR_DRP 0x003f0000 /* data TLB replace pointer */
+#define MMUCTR_DTE 0x00400000 /* data TLB enable */
+#define MMUCTR_DIV 0x00800000 /* data TLB invalidate */
+#define MMUCTR_DTL 0x07000000 /* data TLB lock pointer */
+#define MMUCTR_DTL_NOLOCK 0x00000000 /* - no lock */
+#define MMUCTR_DTL_LOCK0 0x01000000 /* - entry 0 locked */
+#define MMUCTR_DTL_LOCK0_1 0x02000000 /* - entry 0-1 locked */
+#define MMUCTR_DTL_LOCK0_3 0x03000000 /* - entry 0-3 locked */
+#define MMUCTR_DTL_LOCK0_7 0x04000000 /* - entry 0-7 locked */
+#define MMUCTR_DTL_LOCK0_15 0x05000000 /* - entry 0-15 locked */
+
+#define PIDR __SYSREG(0xc0000094, u16) /* PID register */
+#define PIDR_PID 0x00ff /* process identifier */
+
+#define PTBR __SYSREG(0xc0000098, unsigned long) /* Page table base register */
+
+#define IPTEL __SYSREG(0xc00000a0, u32) /* instruction TLB entry */
+#define DPTEL __SYSREG(0xc00000b0, u32) /* data TLB entry */
+#define xPTEL_V 0x00000001 /* TLB entry valid */
+#define xPTEL_UNUSED1 0x00000002 /* unused bit */
+#define xPTEL_UNUSED2 0x00000004 /* unused bit */
+#define xPTEL_C 0x00000008 /* cached if set */
+#define xPTEL_PV 0x00000010 /* page valid */
+#define xPTEL_D 0x00000020 /* dirty */
+#define xPTEL_PR 0x000001c0 /* page protection */
+#define xPTEL_PR_ROK 0x00000000 /* - R/O kernel */
+#define xPTEL_PR_RWK 0x00000100 /* - R/W kernel */
+#define xPTEL_PR_ROK_ROU 0x00000080 /* - R/O kernel and R/O user */
+#define xPTEL_PR_RWK_ROU 0x00000180 /* - R/W kernel and R/O user */
+#define xPTEL_PR_RWK_RWU 0x000001c0 /* - R/W kernel and R/W user */
+#define xPTEL_G 0x00000200 /* global (use PID if 0) */
+#define xPTEL_PS 0x00000c00 /* page size */
+#define xPTEL_PS_4Kb 0x00000000 /* - 4Kb page */
+#define xPTEL_PS_128Kb 0x00000400 /* - 128Kb page */
+#define xPTEL_PS_1Kb 0x00000800 /* - 1Kb page */
+#define xPTEL_PS_4Mb 0x00000c00 /* - 4Mb page */
+#define xPTEL_PPN 0xfffff006 /* physical page number */
+
+#define xPTEL_V_BIT 0 /* bit numbers corresponding to above masks */
+#define xPTEL_UNUSED1_BIT 1
+#define xPTEL_UNUSED2_BIT 2
+#define xPTEL_C_BIT 3
+#define xPTEL_PV_BIT 4
+#define xPTEL_D_BIT 5
+#define xPTEL_G_BIT 9
+
+#define IPTEU __SYSREG(0xc00000a4, u32) /* instruction TLB virtual addr */
+#define DPTEU __SYSREG(0xc00000b4, u32) /* data TLB virtual addr */
+#define xPTEU_VPN 0xfffffc00 /* virtual page number */
+#define xPTEU_PID 0x000000ff /* process identifier to which applicable */
+
+#define IPTEL2 __SYSREG(0xc00000a8, u32) /* instruction TLB entry */
+#define DPTEL2 __SYSREG(0xc00000b8, u32) /* data TLB entry */
+#define xPTEL2_V 0x00000001 /* TLB entry valid */
+#define xPTEL2_C 0x00000002 /* cacheable */
+#define xPTEL2_PV 0x00000004 /* page valid */
+#define xPTEL2_D 0x00000008 /* dirty */
+#define xPTEL2_PR 0x00000070 /* page protection */
+#define xPTEL2_PR_ROK 0x00000000 /* - R/O kernel */
+#define xPTEL2_PR_RWK 0x00000040 /* - R/W kernel */
+#define xPTEL2_PR_ROK_ROU 0x00000020 /* - R/O kernel and R/O user */
+#define xPTEL2_PR_RWK_ROU 0x00000060 /* - R/W kernel and R/O user */
+#define xPTEL2_PR_RWK_RWU 0x00000070 /* - R/W kernel and R/W user */
+#define xPTEL2_G 0x00000080 /* global (use PID if 0) */
+#define xPTEL2_PS 0x00000300 /* page size */
+#define xPTEL2_PS_4Kb 0x00000000 /* - 4Kb page */
+#define xPTEL2_PS_128Kb 0x00000100 /* - 128Kb page */
+#define xPTEL2_PS_1Kb 0x00000200 /* - 1Kb page */
+#define xPTEL2_PS_4Mb 0x00000300 /* - 4Mb page */
+#define xPTEL2_PPN 0xfffffc00 /* physical page number */
+
+#define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */
+#define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */
+#define MMUFCR_DFC __SYSREGC(0xc000009e, u16) /* MMU data exception cause */
+#define MMUFCR_xFC_TLBMISS 0x0001 /* TLB miss flag */
+#define MMUFCR_xFC_INITWR 0x0002 /* initial write excep flag */
+#define MMUFCR_xFC_PGINVAL 0x0004 /* page invalid excep flag */
+#define MMUFCR_xFC_PROTVIOL 0x0008 /* protection violation excep flag */
+#define MMUFCR_xFC_ACCESS 0x0010 /* access level flag */
+#define MMUFCR_xFC_ACCESS_USR 0x0000 /* - user mode */
+#define MMUFCR_xFC_ACCESS_SR 0x0010 /* - supervisor mode */
+#define MMUFCR_xFC_TYPE 0x0020 /* access type flag */
+#define MMUFCR_xFC_TYPE_READ 0x0000 /* - read */
+#define MMUFCR_xFC_TYPE_WRITE 0x0020 /* - write */
+#define MMUFCR_xFC_PR 0x01c0 /* page protection flag */
+#define MMUFCR_xFC_PR_ROK 0x0000 /* - R/O kernel */
+#define MMUFCR_xFC_PR_RWK 0x0100 /* - R/W kernel */
+#define MMUFCR_xFC_PR_ROK_ROU 0x0080 /* - R/O kernel and R/O user */
+#define MMUFCR_xFC_PR_RWK_ROU 0x0180 /* - R/W kernel and R/O user */
+#define MMUFCR_xFC_PR_RWK_RWU 0x01c0 /* - R/W kernel and R/W user */
+#define MMUFCR_xFC_ILLADDR 0x0200 /* illegal address excep flag */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_CPU_REGS_H */
--- /dev/null
+#include <asm-generic/cputime.h>
--- /dev/null
+/* MN10300 Current task structure accessor
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_CURRENT_H
+#define _ASM_CURRENT_H
+
+#include <linux/thread_info.h>
+
+/*
+ * dedicate E2 to keeping the current task pointer
+ */
+#ifdef CONFIG_MN10300_CURRENT_IN_E2
+
+register struct task_struct *const current asm("e2") __attribute__((used));
+
+#define get_current() current
+
+extern struct task_struct *__current;
+
+#else
+static inline __attribute__((const))
+struct task_struct *get_current(void)
+{
+ return current_thread_info()->task;
+}
+
+#define current get_current()
+#endif
+
+#endif /* _ASM_CURRENT_H */
--- /dev/null
+/* MN10300 Uninterruptible delay routines
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_DELAY_H
+#define _ASM_DELAY_H
+
+extern void __udelay(unsigned long usecs);
+extern void __delay(unsigned long loops);
+
+#define udelay(n) __udelay(n)
+
+#endif /* _ASM_DELAY_H */
--- /dev/null
+#include <asm-generic/device.h>
--- /dev/null
+/* MN10300 64-bit division
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_DIV64
+#define _ASM_DIV64
+
+#include <linux/types.h>
+
+extern void ____unhandled_size_in_do_div___(void);
+
+/*
+ * divide n by base, leaving the result in n and returning the remainder
+ * - we can do this quite efficiently on the MN10300 by cascading the divides
+ * through the MDR register
+ */
+#define do_div(n, base) \
+({ \
+ unsigned __rem = 0; \
+ if (sizeof(n) <= 4) { \
+ asm("mov %1,mdr \n" \
+ "divu %2,%0 \n" \
+ "mov mdr,%1 \n" \
+ : "+r"(n), "=d"(__rem) \
+ : "r"(base), "1"(__rem) \
+ : "cc" \
+ ); \
+ } else if (sizeof(n) <= 8) { \
+ union { \
+ unsigned long long l; \
+ u32 w[2]; \
+ } __quot; \
+ __quot.l = n; \
+ asm("mov %0,mdr \n" /* MDR = 0 */ \
+ "divu %3,%1 \n" \
+ /* __quot.MSL = __div.MSL / base, */ \
+ /* MDR = MDR:__div.MSL % base */ \
+ "divu %3,%2 \n" \
+ /* __quot.LSL = MDR:__div.LSL / base, */ \
+ /* MDR = MDR:__div.LSL % base */ \
+ "mov mdr,%0 \n" \
+ : "=d"(__rem), "=r"(__quot.w[1]), "=r"(__quot.w[0]) \
+ : "r"(base), "0"(__rem), "1"(__quot.w[1]), \
+ "2"(__quot.w[0]) \
+ : "cc" \
+ ); \
+ n = __quot.l; \
+ } else { \
+ ____unhandled_size_in_do_div___(); \
+ } \
+ __rem; \
+})
+
+/*
+ * do an unsigned 32-bit multiply and divide with intermediate 64-bit product
+ * so as not to lose accuracy
+ * - we use the MDR register to hold the MSW of the product
+ */
+static inline __attribute__((const))
+unsigned __muldiv64u(unsigned val, unsigned mult, unsigned div)
+{
+ unsigned result;
+
+ asm("mulu %2,%0 \n" /* MDR:val = val*mult */
+ "divu %3,%0 \n" /* val = MDR:val/div;
+ * MDR = MDR:val%div */
+ : "=r"(result)
+ : "0"(val), "ir"(mult), "r"(div)
+ );
+
+ return result;
+}
+
+/*
+ * do a signed 32-bit multiply and divide with intermediate 64-bit product so
+ * as not to lose accuracy
+ * - we use the MDR register to hold the MSW of the product
+ */
+static inline __attribute__((const))
+signed __muldiv64s(signed val, signed mult, signed div)
+{
+ signed result;
+
+ asm("mul %2,%0 \n" /* MDR:val = val*mult */
+ "div %3,%0 \n" /* val = MDR:val/div;
+ * MDR = MDR:val%div */
+ : "=r"(result)
+ : "0"(val), "ir"(mult), "r"(div)
+ );
+
+ return result;
+}
+
+extern __attribute__((const))
+uint64_t div64_64(uint64_t dividend, uint64_t divisor);
+
+#endif /* _ASM_DIV64 */
--- /dev/null
+/* DMA mapping routines for the MN10300 arch
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_DMA_MAPPING_H
+#define _ASM_DMA_MAPPING_H
+
+#include <linux/mm.h>
+#include <linux/scatterlist.h>
+
+#include <asm/cache.h>
+#include <asm/io.h>
+
+extern void *dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, int flag);
+
+extern void dma_free_coherent(struct device *dev, size_t size,
+ void *vaddr, dma_addr_t dma_handle);
+
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent((d), (s), (h), (f))
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent((d), (s), (v), (h))
+
+/*
+ * Map a single buffer of the indicated size for DMA in streaming mode. The
+ * 32-bit bus address to use is returned.
+ *
+ * Once the device is given the dma address, the device owns this memory until
+ * either pci_unmap_single or pci_dma_sync_single is performed.
+ */
+static inline
+dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
+ enum dma_data_direction direction)
+{
+ BUG_ON(direction == DMA_NONE);
+ mn10300_dcache_flush_inv();
+ return virt_to_bus(ptr);
+}
+
+/*
+ * Unmap a single streaming mode DMA translation. The dma_addr and size must
+ * match what was provided for in a previous pci_map_single call. All other
+ * usages are undefined.
+ *
+ * After this call, reads by the cpu to the buffer are guarenteed to see
+ * whatever the device wrote there.
+ */
+static inline
+void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
+ enum dma_data_direction direction)
+{
+ BUG_ON(direction == DMA_NONE);
+}
+
+/*
+ * Map a set of buffers described by scatterlist in streaming mode for DMA.
+ * This is the scather-gather version of the above pci_map_single interface.
+ * Here the scatter gather list elements are each tagged with the appropriate
+ * dma address and length. They are obtained via sg_dma_{address,length}(SG).
+ *
+ * NOTE: An implementation may be able to use a smaller number of DMA
+ * address/length pairs than there are SG table elements. (for example
+ * via virtual mapping capabilities) The routine returns the number of
+ * addr/length pairs actually used, at most nents.
+ *
+ * Device ownership issues as mentioned above for pci_map_single are the same
+ * here.
+ */
+static inline
+int dma_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
+ enum dma_data_direction direction)
+{
+ struct scatterlist *sg;
+ int i;
+
+ BUG_ON(!valid_dma_direction(direction));
+ WARN_ON(nents == 0 || sglist[0].length == 0);
+
+ for_each_sg(sglist, sg, nents, i) {
+ BUG_ON(!sg_page(sg));
+
+ sg->dma_address = sg_phys(sg);
+ }
+
+ mn10300_dcache_flush_inv();
+ return nents;
+}
+
+/*
+ * Unmap a set of streaming mode DMA translations.
+ * Again, cpu read rules concerning calls here are the same as for
+ * pci_unmap_single() above.
+ */
+static inline
+void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
+ enum dma_data_direction direction)
+{
+ BUG_ON(!valid_dma_direction(direction));
+}
+
+/*
+ * pci_{map,unmap}_single_page maps a kernel page to a dma_addr_t. identical
+ * to pci_map_single, but takes a struct page instead of a virtual address
+ */
+static inline
+dma_addr_t dma_map_page(struct device *dev, struct page *page,
+ unsigned long offset, size_t size,
+ enum dma_data_direction direction)
+{
+ BUG_ON(direction == DMA_NONE);
+ return page_to_bus(page) + offset;
+}
+
+static inline
+void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
+ enum dma_data_direction direction)
+{
+ BUG_ON(direction == DMA_NONE);
+}
+
+/*
+ * Make physical memory consistent for a single streaming mode DMA translation
+ * after a transfer.
+ *
+ * If you perform a pci_map_single() but wish to interrogate the buffer using
+ * the cpu, yet do not wish to teardown the PCI dma mapping, you must call this
+ * function before doing so. At the next point you give the PCI dma address
+ * back to the card, the device again owns the buffer.
+ */
+static inline
+void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
+ size_t size, enum dma_data_direction direction)
+{
+}
+
+static inline
+void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
+ size_t size, enum dma_data_direction direction)
+{
+ mn10300_dcache_flush_inv();
+}
+
+static inline
+void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
+ unsigned long offset, size_t size,
+ enum dma_data_direction direction)
+{
+}
+
+static inline void
+dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
+ unsigned long offset, size_t size,
+ enum dma_data_direction direction)
+{
+ mn10300_dcache_flush_inv();
+}
+
+
+/*
+ * Make physical memory consistent for a set of streaming mode DMA translations
+ * after a transfer.
+ *
+ * The same as pci_dma_sync_single but for a scatter-gather list, same rules
+ * and usage.
+ */
+static inline
+void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
+ int nelems, enum dma_data_direction direction)
+{
+}
+
+static inline
+void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+ int nelems, enum dma_data_direction direction)
+{
+ mn10300_dcache_flush_inv();
+}
+
+static inline
+int dma_mapping_error(dma_addr_t dma_addr)
+{
+ return 0;
+}
+
+/*
+ * Return whether the given PCI device DMA address mask can be supported
+ * properly. For example, if your device can only drive the low 24-bits during
+ * PCI bus mastering, then you would pass 0x00ffffff as the mask to this
+ * function.
+ */
+static inline
+int dma_supported(struct device *dev, u64 mask)
+{
+ /*
+ * we fall back to GFP_DMA when the mask isn't all 1s, so we can't
+ * guarantee allocations that must be within a tighter range than
+ * GFP_DMA
+ */
+ if (mask < 0x00ffffff)
+ return 0;
+ return 1;
+}
+
+static inline
+int dma_set_mask(struct device *dev, u64 mask)
+{
+ if (!dev->dma_mask || !dma_supported(dev, mask))
+ return -EIO;
+
+ *dev->dma_mask = mask;
+ return 0;
+}
+
+static inline
+int dma_get_cache_alignment(void)
+{
+ return 1 << L1_CACHE_SHIFT;
+}
+
+#define dma_is_consistent(d) (1)
+
+static inline
+void dma_cache_sync(void *vaddr, size_t size,
+ enum dma_data_direction direction)
+{
+ mn10300_dcache_flush_inv();
+}
+
+#endif
--- /dev/null
+/* MN10300 ISA DMA handlers and definitions
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_DMA_H
+#define _ASM_DMA_H
+
+#include <asm/system.h>
+#include <linux/spinlock.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+
+#undef MAX_DMA_CHANNELS /* switch off linux/kernel/dma.c */
+#define MAX_DMA_ADDRESS 0xbfffffff
+
+extern spinlock_t dma_spin_lock;
+
+static inline unsigned long claim_dma_lock(void)
+{
+ unsigned long flags;
+ spin_lock_irqsave(&dma_spin_lock, flags);
+ return flags;
+}
+
+static inline void release_dma_lock(unsigned long flags)
+{
+ spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* enable/disable a specific DMA channel */
+static inline void enable_dma(unsigned int dmanr)
+{
+}
+
+static inline void disable_dma(unsigned int dmanr)
+{
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ * Use this once to initialize the FF to a known state.
+ * After that, keep track of it. :-)
+ * --- In order to do that, the DMA routines below should ---
+ * --- only be used while holding the DMA lock ! ---
+ */
+static inline void clear_dma_ff(unsigned int dmanr)
+{
+}
+
+/* set mode (above) for a specific DMA channel */
+static inline void set_dma_mode(unsigned int dmanr, char mode)
+{
+}
+
+/* Set only the page register bits of the transfer address.
+ * This is used for successive transfers when we know the contents of
+ * the lower 16 bits of the DMA current address register, but a 64k boundary
+ * may have been crossed.
+ */
+static inline void set_dma_page(unsigned int dmanr, char pagenr)
+{
+}
+
+
+/* Set transfer address & page bits for specific DMA channel.
+ * Assumes dma flipflop is clear.
+ */
+static inline void set_dma_addr(unsigned int dmanr, unsigned int a)
+{
+}
+
+
+/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
+ * a specific DMA channel.
+ * You must ensure the parameters are valid.
+ * NOTE: from a manual: "the number of transfers is one more
+ * than the initial word count"! This is taken into account.
+ * Assumes dma flip-flop is clear.
+ * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
+ */
+static inline void set_dma_count(unsigned int dmanr, unsigned int count)
+{
+}
+
+
+/* Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * If called before the channel has been used, it may return 1.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ *
+ * Assumes DMA flip-flop is clear.
+ */
+static inline int get_dma_residue(unsigned int dmanr)
+{
+ return 0;
+}
+
+
+/* These are in kernel/dma.c: */
+extern int request_dma(unsigned int dmanr, const char *device_id);
+extern void free_dma(unsigned int dmanr);
+
+/* From PCI */
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy (0)
+#endif
+
+#endif /* _ASM_DMA_H */
--- /dev/null
+/* MN10300 on-board DMA controller registers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_DMACTL_REGS_H
+#define _ASM_DMACTL_REGS_H
+
+#include <asm/cpu-regs.h>
+
+#ifdef __KERNEL__
+
+/* DMA registers */
+#define DMxCTR(N) __SYSREG(0xd2000000 + ((N) * 0x100), u32) /* control reg */
+#define DMxCTR_BG 0x0000001f /* transfer request source */
+#define DMxCTR_BG_SOFT 0x00000000 /* - software source */
+#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */
+#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */
+#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */
+#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */
+#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */
+#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */
+#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */
+#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */
+#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */
+#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */
+#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */
+#define DMxCTR_BG_AFE 0x0000000d /* - analogue front-end interrupt source */
+#define DMxCTR_BG_ADC 0x0000000e /* - A/D conversion end interrupt source */
+#define DMxCTR_BG_IRDA 0x0000000f /* - IrDA interrupt source */
+#define DMxCTR_BG_RTC 0x00000010 /* - RTC interrupt source */
+#define DMxCTR_BG_XIRQ0 0x00000011 /* - XIRQ0 pin interrupt source */
+#define DMxCTR_BG_XIRQ1 0x00000012 /* - XIRQ1 pin interrupt source */
+#define DMxCTR_BG_XDMR0 0x00000013 /* - external request 0 source (XDMR0 pin) */
+#define DMxCTR_BG_XDMR1 0x00000014 /* - external request 1 source (XDMR1 pin) */
+#define DMxCTR_SAM 0x000000e0 /* DMA transfer src addr mode */
+#define DMxCTR_SAM_INCR 0x00000000 /* - increment */
+#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */
+#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */
+#define DMxCTR_DAM 0x00000000 /* DMA transfer dest addr mode */
+#define DMxCTR_DAM_INCR 0x00000000 /* - increment */
+#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */
+#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */
+#define DMxCTR_TM 0x00001800 /* DMA transfer mode */
+#define DMxCTR_TM_BATCH 0x00000000 /* - batch transfer */
+#define DMxCTR_TM_INTERM 0x00001000 /* - intermittent transfer */
+#define DMxCTR_UT 0x00006000 /* DMA transfer unit */
+#define DMxCTR_UT_1 0x00000000 /* - 1 byte */
+#define DMxCTR_UT_2 0x00002000 /* - 2 byte */
+#define DMxCTR_UT_4 0x00004000 /* - 4 byte */
+#define DMxCTR_UT_16 0x00006000 /* - 16 byte */
+#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */
+#define DMxCTR_RQM 0x00060000 /* external request input source mode */
+#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */
+#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */
+#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */
+#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */
+#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */
+#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */
+
+#define DMxSRC(N) __SYSREG(0xd2000004 + ((N) * 0x100), u32) /* control reg */
+
+#define DMxDST(N) __SYSREG(0xd2000008 + ((N) * 0x100), u32) /* src addr reg */
+
+#define DMxSIZ(N) __SYSREG(0xd200000c + ((N) * 0x100), u32) /* dest addr reg */
+#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */
+
+#define DMxCYC(N) __SYSREG(0xd2000010 + ((N) * 0x100), u32) /* intermittent
+ * size reg */
+#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */
+
+#define DM0IRQ 16 /* DMA channel 0 complete IRQ */
+#define DM1IRQ 17 /* DMA channel 1 complete IRQ */
+#define DM2IRQ 18 /* DMA channel 2 complete IRQ */
+#define DM3IRQ 19 /* DMA channel 3 complete IRQ */
+
+#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
+#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
+#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
+#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
+
+#ifndef __ASSEMBLY__
+
+struct mn10300_dmactl_regs {
+ u32 ctr;
+ const void *src;
+ void *dst;
+ u32 siz;
+ u32 cyc;
+} __attribute__((aligned(0x100)));
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_DMACTL_REGS_H */
--- /dev/null
+/* MN10300 ELF constant and register definitions
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_ELF_H
+#define _ASM_ELF_H
+
+#include <linux/utsname.h>
+#include <asm/ptrace.h>
+#include <asm/user.h>
+
+/*
+ * AM33 relocations
+ */
+#define R_MN10300_NONE 0 /* No reloc. */
+#define R_MN10300_32 1 /* Direct 32 bit. */
+#define R_MN10300_16 2 /* Direct 16 bit. */
+#define R_MN10300_8 3 /* Direct 8 bit. */
+#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */
+#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */
+#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */
+#define R_MN10300_24 9 /* Direct 24 bit. */
+#define R_MN10300_RELATIVE 23 /* Adjust by program base. */
+
+/*
+ * ELF register definitions..
+ */
+typedef unsigned long elf_greg_t;
+
+#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+#define ELF_NFPREG 32
+typedef float elf_fpreg_t;
+
+typedef struct {
+ elf_fpreg_t fpregs[ELF_NFPREG];
+ u_int32_t fpcr;
+} elf_fpregset_t;
+
+extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture
+ */
+#define elf_check_arch(x) \
+ (((x)->e_machine == EM_CYGNUS_MN10300) || \
+ ((x)->e_machine == EM_MN10300))
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS ELFCLASS32
+#define ELF_DATA ELFDATA2LSB
+#define ELF_ARCH EM_MN10300
+
+/*
+ * ELF process initialiser
+ */
+#define ELF_PLAT_INIT(_r, load_addr) \
+do { \
+ struct pt_regs *_ur = current->thread.uregs; \
+ _ur->a3 = 0; _ur->a2 = 0; _ur->d3 = 0; _ur->d2 = 0; \
+ _ur->mcvf = 0; _ur->mcrl = 0; _ur->mcrh = 0; _ur->mdrq = 0; \
+ _ur->e1 = 0; _ur->e0 = 0; _ur->e7 = 0; _ur->e6 = 0; \
+ _ur->e5 = 0; _ur->e4 = 0; _ur->e3 = 0; _ur->e2 = 0; \
+ _ur->lar = 0; _ur->lir = 0; _ur->mdr = 0; \
+ _ur->a1 = 0; _ur->a0 = 0; _ur->d1 = 0; _ur->d0 = 0; \
+} while (0)
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE 4096
+
+/*
+ * This is the location that an ET_DYN program is loaded if exec'ed. Typical
+ * use of this is to invoke "./ld.so someprog" to test out a new version of
+ * the loader. We need to make sure that it is out of the way of the program
+ * that it will "exec", and that there is sufficient room for the brk.
+ * - must clear the VMALLOC area
+ */
+#define ELF_ET_DYN_BASE 0x04000000
+
+/*
+ * regs is struct pt_regs, pr_reg is elf_gregset_t (which is
+ * now struct user_regs, they are different)
+ * - ELF_CORE_COPY_REGS has been guessed, and may be wrong
+ */
+#define ELF_CORE_COPY_REGS(pr_reg, regs) \
+do { \
+ pr_reg[0] = regs->a3; \
+ pr_reg[1] = regs->a2; \
+ pr_reg[2] = regs->d3; \
+ pr_reg[3] = regs->d2; \
+ pr_reg[4] = regs->mcvf; \
+ pr_reg[5] = regs->mcrl; \
+ pr_reg[6] = regs->mcrh; \
+ pr_reg[7] = regs->mdrq; \
+ pr_reg[8] = regs->e1; \
+ pr_reg[9] = regs->e0; \
+ pr_reg[10] = regs->e7; \
+ pr_reg[11] = regs->e6; \
+ pr_reg[12] = regs->e5; \
+ pr_reg[13] = regs->e4; \
+ pr_reg[14] = regs->e3; \
+ pr_reg[15] = regs->e2; \
+ pr_reg[16] = regs->sp; \
+ pr_reg[17] = regs->lar; \
+ pr_reg[18] = regs->lir; \
+ pr_reg[19] = regs->mdr; \
+ pr_reg[20] = regs->a1; \
+ pr_reg[21] = regs->a0; \
+ pr_reg[22] = regs->d1; \
+ pr_reg[23] = regs->d0; \
+ pr_reg[24] = regs->orig_d0; \
+ pr_reg[25] = regs->epsw; \
+ pr_reg[26] = regs->pc; \
+} while (0);
+
+/*
+ * This yields a mask that user programs can use to figure out what
+ * instruction set this CPU supports. This could be done in user space,
+ * but it's not easy, and we've already done it here.
+ */
+#define ELF_HWCAP (0)
+
+/*
+ * This yields a string that ld.so will use to load implementation
+ * specific libraries for optimization. This is more specific in
+ * intent than poking at uname or /proc/cpuinfo.
+ *
+ * For the moment, we have only optimizations for the Intel generations,
+ * but that could change...
+ */
+#define ELF_PLATFORM (NULL)
+
+#ifdef __KERNEL__
+#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX)
+#endif
+
+#endif /* _ASM_ELF_H */
--- /dev/null
+#include <asm-generic/emergency-restart.h>
--- /dev/null
+#include <asm-generic/errno.h>
--- /dev/null
+/* MN10300 Microcontroller core exceptions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_EXCEPTIONS_H
+#define _ASM_EXCEPTIONS_H
+
+#include <linux/linkage.h>
+
+/*
+ * define the breakpoint instruction opcode to use
+ * - note that the JTAG unit steals 0xFF, so we want to avoid that if we can
+ * (can use 0xF7)
+ */
+#define GDBSTUB_BKPT 0xFF
+
+#ifndef __ASSEMBLY__
+
+/*
+ * enumeration of exception codes (as extracted from TBR MSW)
+ */
+enum exception_code {
+ EXCEP_RESET = 0x000000, /* reset */
+
+ /* MMU exceptions */
+ EXCEP_ITLBMISS = 0x000100, /* instruction TLB miss */
+ EXCEP_DTLBMISS = 0x000108, /* data TLB miss */
+ EXCEP_IAERROR = 0x000110, /* instruction address */
+ EXCEP_DAERROR = 0x000118, /* data address */
+
+ /* system exceptions */
+ EXCEP_TRAP = 0x000128, /* program interrupt (PI instruction) */
+ EXCEP_ISTEP = 0x000130, /* single step */
+ EXCEP_IBREAK = 0x000150, /* instruction breakpoint */
+ EXCEP_OBREAK = 0x000158, /* operand breakpoint */
+ EXCEP_PRIVINS = 0x000160, /* privileged instruction execution */
+ EXCEP_UNIMPINS = 0x000168, /* unimplemented instruction execution */
+ EXCEP_UNIMPEXINS = 0x000170, /* unimplemented extended instruction execution */
+ EXCEP_MEMERR = 0x000178, /* illegal memory access */
+ EXCEP_MISALIGN = 0x000180, /* misalignment */
+ EXCEP_BUSERROR = 0x000188, /* bus error */
+ EXCEP_ILLINSACC = 0x000190, /* illegal instruction access */
+ EXCEP_ILLDATACC = 0x000198, /* illegal data access */
+ EXCEP_IOINSACC = 0x0001a0, /* I/O space instruction access */
+ EXCEP_PRIVINSACC = 0x0001a8, /* privileged space instruction access */
+ EXCEP_PRIVDATACC = 0x0001b0, /* privileged space data access */
+ EXCEP_DATINSACC = 0x0001b8, /* data space instruction access */
+ EXCEP_DOUBLE_FAULT = 0x000200, /* double fault */
+
+ /* FPU exceptions */
+ EXCEP_FPU_DISABLED = 0x0001c0, /* FPU disabled */
+ EXCEP_FPU_UNIMPINS = 0x0001c8, /* FPU unimplemented operation */
+ EXCEP_FPU_OPERATION = 0x0001d0, /* FPU operation */
+
+ /* interrupts */
+ EXCEP_WDT = 0x000240, /* watchdog timer overflow */
+ EXCEP_NMI = 0x000248, /* non-maskable interrupt */
+ EXCEP_IRQ_LEVEL0 = 0x000280, /* level 0 maskable interrupt */
+ EXCEP_IRQ_LEVEL1 = 0x000288, /* level 1 maskable interrupt */
+ EXCEP_IRQ_LEVEL2 = 0x000290, /* level 2 maskable interrupt */
+ EXCEP_IRQ_LEVEL3 = 0x000298, /* level 3 maskable interrupt */
+ EXCEP_IRQ_LEVEL4 = 0x0002a0, /* level 4 maskable interrupt */
+ EXCEP_IRQ_LEVEL5 = 0x0002a8, /* level 5 maskable interrupt */
+ EXCEP_IRQ_LEVEL6 = 0x0002b0, /* level 6 maskable interrupt */
+
+ /* system calls */
+ EXCEP_SYSCALL0 = 0x000300, /* system call 0 */
+ EXCEP_SYSCALL1 = 0x000308, /* system call 1 */
+ EXCEP_SYSCALL2 = 0x000310, /* system call 2 */
+ EXCEP_SYSCALL3 = 0x000318, /* system call 3 */
+ EXCEP_SYSCALL4 = 0x000320, /* system call 4 */
+ EXCEP_SYSCALL5 = 0x000328, /* system call 5 */
+ EXCEP_SYSCALL6 = 0x000330, /* system call 6 */
+ EXCEP_SYSCALL7 = 0x000338, /* system call 7 */
+ EXCEP_SYSCALL8 = 0x000340, /* system call 8 */
+ EXCEP_SYSCALL9 = 0x000348, /* system call 9 */
+ EXCEP_SYSCALL10 = 0x000350, /* system call 10 */
+ EXCEP_SYSCALL11 = 0x000358, /* system call 11 */
+ EXCEP_SYSCALL12 = 0x000360, /* system call 12 */
+ EXCEP_SYSCALL13 = 0x000368, /* system call 13 */
+ EXCEP_SYSCALL14 = 0x000370, /* system call 14 */
+ EXCEP_SYSCALL15 = 0x000378, /* system call 15 */
+};
+
+extern void __set_intr_stub(enum exception_code code, void *handler);
+extern void set_intr_stub(enum exception_code code, void *handler);
+extern void set_jtag_stub(enum exception_code code, void *handler);
+
+struct pt_regs;
+
+extern asmlinkage void __common_exception(void);
+extern asmlinkage void itlb_miss(void);
+extern asmlinkage void dtlb_miss(void);
+extern asmlinkage void itlb_aerror(void);
+extern asmlinkage void dtlb_aerror(void);
+extern asmlinkage void raw_bus_error(void);
+extern asmlinkage void double_fault(void);
+extern asmlinkage int system_call(struct pt_regs *);
+extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code);
+extern asmlinkage void nmi(struct pt_regs *, enum exception_code);
+extern asmlinkage void uninitialised_exception(struct pt_regs *,
+ enum exception_code);
+extern asmlinkage void irq_handler(void);
+extern asmlinkage void profile_handler(void);
+extern asmlinkage void nmi_handler(void);
+extern asmlinkage void misalignment(struct pt_regs *, enum exception_code);
+
+extern void die(const char *, struct pt_regs *, enum exception_code)
+ ATTRIB_NORET;
+
+extern int die_if_no_fixup(const char *, struct pt_regs *, enum exception_code);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_EXCEPTIONS_H */
--- /dev/null
+/* MN10300 Frame buffer stuff
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_FB_H
+#define _ASM_FB_H
+
+#include <linux/fb.h>
+
+#define fb_pgprotect(...) do {} while (0)
+
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+ return 0;
+}
+
+#endif /* _ASM_FB_H */
--- /dev/null
+#include <asm-generic/fcntl.h>
--- /dev/null
+/* MN10300 FPU definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ * Derived from include/asm-i386/i387.h: Copyright (C) 1994 Linus Torvalds
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_FPU_H
+#define _ASM_FPU_H
+
+#include <asm/processor.h>
+#include <asm/sigcontext.h>
+#include <asm/user.h>
+
+#ifdef __KERNEL__
+
+/* the task that owns the FPU state */
+extern struct task_struct *fpu_state_owner;
+
+#define set_using_fpu(tsk) \
+do { \
+ (tsk)->thread.fpu_flags |= THREAD_USING_FPU; \
+} while (0)
+
+#define clear_using_fpu(tsk) \
+do { \
+ (tsk)->thread.fpu_flags &= ~THREAD_USING_FPU; \
+} while (0)
+
+#define is_using_fpu(tsk) ((tsk)->thread.fpu_flags & THREAD_USING_FPU)
+
+#define unlazy_fpu(tsk) \
+do { \
+ preempt_disable(); \
+ if (fpu_state_owner == (tsk)) \
+ fpu_save(&tsk->thread.fpu_state); \
+ preempt_enable(); \
+} while (0)
+
+#define exit_fpu() \
+do { \
+ struct task_struct *__tsk = current; \
+ preempt_disable(); \
+ if (fpu_state_owner == __tsk) \
+ fpu_state_owner = NULL; \
+ preempt_enable(); \
+} while (0)
+
+#define flush_fpu() \
+do { \
+ struct task_struct *__tsk = current; \
+ preempt_disable(); \
+ if (fpu_state_owner == __tsk) { \
+ fpu_state_owner = NULL; \
+ __tsk->thread.uregs->epsw &= ~EPSW_FE; \
+ } \
+ preempt_enable(); \
+ clear_using_fpu(__tsk); \
+} while (0)
+
+extern asmlinkage void fpu_init_state(void);
+extern asmlinkage void fpu_kill_state(struct task_struct *);
+extern asmlinkage void fpu_disabled(struct pt_regs *, enum exception_code);
+extern asmlinkage void fpu_exception(struct pt_regs *, enum exception_code);
+
+#ifdef CONFIG_FPU
+extern asmlinkage void fpu_save(struct fpu_state_struct *);
+extern asmlinkage void fpu_restore(struct fpu_state_struct *);
+#else
+#define fpu_save(a)
+#define fpu_restore(a)
+#endif /* CONFIG_FPU */
+
+/*
+ * signal frame handlers
+ */
+extern int fpu_setup_sigcontext(struct fpucontext *buf);
+extern int fpu_restore_sigcontext(struct fpucontext *buf);
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_FPU_H */
--- /dev/null
+/* MN10300 Microcontroller core system register definitions -*- asm -*-
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_FRAME_INC
+#define _ASM_FRAME_INC
+
+#ifndef __ASSEMBLY__
+#error not for use in C files
+#endif
+
+#ifndef __ASM_OFFSETS_H__
+#include <asm/asm-offsets.h>
+#endif
+
+#define pi break
+
+#define fp a3
+
+###############################################################################
+#
+# build a stack frame from the registers
+# - the caller has subtracted 4 from SP before coming here
+#
+###############################################################################
+.macro SAVE_ALL
+ add -4,sp # next exception frame ptr save area
+ movm [other],(sp)
+ mov usp,a1
+ mov a1,(sp) # USP in MOVM[other] dummy slot
+ movm [d2,d3,a2,a3,exreg0,exreg1,exother],(sp)
+ mov sp,fp # FRAME pointer in A3
+ add -12,sp # allow for calls to be made
+ mov (__frame),a1
+ mov a1,(REG_NEXT,fp)
+ mov fp,(__frame)
+
+ and ~EPSW_FE,epsw # disable the FPU inside the kernel
+
+ # we may be holding current in E2
+#ifdef CONFIG_MN10300_CURRENT_IN_E2
+ mov (__current),e2
+#endif
+.endm
+
+###############################################################################
+#
+# restore the registers from a stack frame
+#
+###############################################################################
+.macro RESTORE_ALL
+ # peel back the stack to the calling frame
+ # - this permits execve() to discard extra frames due to kernel syscalls
+ mov (__frame),fp
+ mov fp,sp
+ mov (REG_NEXT,fp),d0 # userspace has regs->next == 0
+ mov d0,(__frame)
+
+#ifndef CONFIG_MN10300_USING_JTAG
+ mov (REG_EPSW,fp),d0
+ btst EPSW_T,d0
+ beq 99f
+
+ or EPSW_NMID,epsw
+ movhu (DCR),d1
+ or 0x0001, d1
+ movhu d1,(DCR)
+
+99:
+#endif
+ movm (sp),[d2,d3,a2,a3,exreg0,exreg1,exother]
+
+ # must restore usp even if returning to kernel space,
+ # when CONFIG_PREEMPT is enabled.
+ mov (sp),a1 # USP in MOVM[other] dummy slot
+ mov a1,usp
+
+ movm (sp),[other]
+ add 8,sp
+ rti
+
+.endm
+
+
+#endif /* _ASM_FRAME_INC */
--- /dev/null
+#include <asm-generic/futex.h>
--- /dev/null
+/* MN10300 Kernel GDB stub definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ * - Derived from asm-mips/gdb-stub.h (c) 1995 Andreas Busse
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_GDB_STUB_H
+#define _ASM_GDB_STUB_H
+
+#include <asm/exceptions.h>
+
+/*
+ * register ID numbers in GDB remote protocol
+ */
+
+#define GDB_REGID_PC 9
+#define GDB_REGID_FP 7
+#define GDB_REGID_SP 8
+
+/*
+ * virtual stack layout for the GDB exception handler
+ */
+#define NUMREGS 64
+
+#define GDB_FR_D0 (0 * 4)
+#define GDB_FR_D1 (1 * 4)
+#define GDB_FR_D2 (2 * 4)
+#define GDB_FR_D3 (3 * 4)
+#define GDB_FR_A0 (4 * 4)
+#define GDB_FR_A1 (5 * 4)
+#define GDB_FR_A2 (6 * 4)
+#define GDB_FR_A3 (7 * 4)
+
+#define GDB_FR_SP (8 * 4)
+#define GDB_FR_PC (9 * 4)
+#define GDB_FR_MDR (10 * 4)
+#define GDB_FR_EPSW (11 * 4)
+#define GDB_FR_LIR (12 * 4)
+#define GDB_FR_LAR (13 * 4)
+#define GDB_FR_MDRQ (14 * 4)
+
+#define GDB_FR_E0 (15 * 4)
+#define GDB_FR_E1 (16 * 4)
+#define GDB_FR_E2 (17 * 4)
+#define GDB_FR_E3 (18 * 4)
+#define GDB_FR_E4 (19 * 4)
+#define GDB_FR_E5 (20 * 4)
+#define GDB_FR_E6 (21 * 4)
+#define GDB_FR_E7 (22 * 4)
+
+#define GDB_FR_SSP (23 * 4)
+#define GDB_FR_MSP (24 * 4)
+#define GDB_FR_USP (25 * 4)
+#define GDB_FR_MCRH (26 * 4)
+#define GDB_FR_MCRL (27 * 4)
+#define GDB_FR_MCVF (28 * 4)
+
+#define GDB_FR_FPCR (29 * 4)
+#define GDB_FR_DUMMY0 (30 * 4)
+#define GDB_FR_DUMMY1 (31 * 4)
+
+#define GDB_FR_FS0 (32 * 4)
+
+#define GDB_FR_SIZE (NUMREGS * 4)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * This is the same as above, but for the high-level
+ * part of the GDB stub.
+ */
+
+struct gdb_regs {
+ /* saved main processor registers */
+ u32 d0, d1, d2, d3, a0, a1, a2, a3;
+ u32 sp, pc, mdr, epsw, lir, lar, mdrq;
+ u32 e0, e1, e2, e3, e4, e5, e6, e7;
+ u32 ssp, msp, usp, mcrh, mcrl, mcvf;
+
+ /* saved floating point registers */
+ u32 fpcr, _dummy0, _dummy1;
+ u32 fs0, fs1, fs2, fs3, fs4, fs5, fs6, fs7;
+ u32 fs8, fs9, fs10, fs11, fs12, fs13, fs14, fs15;
+ u32 fs16, fs17, fs18, fs19, fs20, fs21, fs22, fs23;
+ u32 fs24, fs25, fs26, fs27, fs28, fs29, fs30, fs31;
+};
+
+/*
+ * Prototypes
+ */
+extern void show_registers_only(struct pt_regs *regs);
+
+extern asmlinkage void gdbstub_init(void);
+extern asmlinkage void gdbstub_exit(int status);
+extern asmlinkage void gdbstub_io_init(void);
+extern asmlinkage void gdbstub_io_set_baud(unsigned baud);
+extern asmlinkage int gdbstub_io_rx_char(unsigned char *_ch, int nonblock);
+extern asmlinkage void gdbstub_io_tx_char(unsigned char ch);
+extern asmlinkage void gdbstub_io_tx_flush(void);
+
+extern asmlinkage void gdbstub_io_rx_handler(void);
+extern asmlinkage void gdbstub_rx_irq(struct pt_regs *, enum exception_code);
+extern asmlinkage int gdbstub_intercept(struct pt_regs *, enum exception_code);
+extern asmlinkage void gdbstub_exception(struct pt_regs *, enum exception_code);
+extern asmlinkage void __gdbstub_bug_trap(void);
+extern asmlinkage void __gdbstub_pause(void);
+extern asmlinkage void start_kernel(void);
+
+#ifndef CONFIG_MN10300_CACHE_DISABLED
+extern asmlinkage void gdbstub_purge_cache(void);
+#else
+#define gdbstub_purge_cache() do {} while (0)
+#endif
+
+/* Used to prevent crashes in memory access */
+extern asmlinkage int gdbstub_read_byte(const u8 *, u8 *);
+extern asmlinkage int gdbstub_read_word(const u8 *, u8 *);
+extern asmlinkage int gdbstub_read_dword(const u8 *, u8 *);
+extern asmlinkage int gdbstub_write_byte(u32, u8 *);
+extern asmlinkage int gdbstub_write_word(u32, u8 *);
+extern asmlinkage int gdbstub_write_dword(u32, u8 *);
+
+extern asmlinkage void gdbstub_read_byte_guard(void);
+extern asmlinkage void gdbstub_read_byte_cont(void);
+extern asmlinkage void gdbstub_read_word_guard(void);
+extern asmlinkage void gdbstub_read_word_cont(void);
+extern asmlinkage void gdbstub_read_dword_guard(void);
+extern asmlinkage void gdbstub_read_dword_cont(void);
+extern asmlinkage void gdbstub_write_byte_guard(void);
+extern asmlinkage void gdbstub_write_byte_cont(void);
+extern asmlinkage void gdbstub_write_word_guard(void);
+extern asmlinkage void gdbstub_write_word_cont(void);
+extern asmlinkage void gdbstub_write_dword_guard(void);
+extern asmlinkage void gdbstub_write_dword_cont(void);
+
+extern u8 gdbstub_rx_buffer[PAGE_SIZE];
+extern u32 gdbstub_rx_inp;
+extern u32 gdbstub_rx_outp;
+extern u8 gdbstub_rx_overflow;
+extern u8 gdbstub_busy;
+extern u8 gdbstub_rx_unget;
+
+#ifdef CONFIG_GDBSTUB_DEBUGGING
+extern void gdbstub_printk(const char *fmt, ...)
+ __attribute__((format(printf, 1, 2)));
+#else
+static inline __attribute__((format(printf, 1, 2)))
+void gdbstub_printk(const char *fmt, ...)
+{
+}
+#endif
+
+#ifdef CONFIG_GDBSTUB_DEBUG_ENTRY
+#define gdbstub_entry(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
+#else
+#define gdbstub_entry(FMT, ...) ({ 0; })
+#endif
+
+#ifdef CONFIG_GDBSTUB_DEBUG_PROTOCOL
+#define gdbstub_proto(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
+#else
+#define gdbstub_proto(FMT, ...) ({ 0; })
+#endif
+
+#ifdef CONFIG_GDBSTUB_DEBUG_IO
+#define gdbstub_io(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
+#else
+#define gdbstub_io(FMT, ...) ({ 0; })
+#endif
+
+#ifdef CONFIG_GDBSTUB_DEBUG_BREAKPOINT
+#define gdbstub_bkpt(FMT, ...) gdbstub_printk(FMT, ##__VA_ARGS__)
+#else
+#define gdbstub_bkpt(FMT, ...) ({ 0; })
+#endif
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _ASM_GDB_STUB_H */
--- /dev/null
+/* MN10300 Hardware IRQ statistics and management
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Modified by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_HARDIRQ_H
+#define _ASM_HARDIRQ_H
+
+#include <linux/threads.h>
+#include <linux/irq.h>
+#include <asm/exceptions.h>
+
+/* assembly code in softirq.h is sensitive to the offsets of these fields */
+typedef struct {
+ unsigned int __softirq_pending;
+ unsigned long idle_timestamp;
+ unsigned int __nmi_count; /* arch dependent */
+ unsigned int __irq_count; /* arch dependent */
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
+
+extern void ack_bad_irq(int irq);
+
+/*
+ * manipulate stubs in the MN10300 CPU Trap/Interrupt Vector table
+ * - these should jump to __common_exception in entry.S unless there's a good
+ * reason to do otherwise (see trap_preinit() in traps.c)
+ */
+typedef void (*intr_stub_fnx)(struct pt_regs *regs,
+ enum exception_code intcode);
+
+/*
+ * manipulate pointers in the Exception table (see entry.S)
+ * - these are indexed by decoding the lower 24 bits of the TBR register
+ * - note that the MN103E010 doesn't always trap through the correct vector,
+ * but does always set the TBR correctly
+ */
+extern asmlinkage void set_excp_vector(enum exception_code code,
+ intr_stub_fnx handler);
+
+#endif /* _ASM_HARDIRQ_H */
--- /dev/null
+/* MN10300 Virtual kernel memory mappings for high memory
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ * - Derived from include/asm-i386/highmem.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_HIGHMEM_H
+#define _ASM_HIGHMEM_H
+
+#ifdef __KERNEL__
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <asm/kmap_types.h>
+#include <asm/pgtable.h>
+
+/* undef for production */
+#undef HIGHMEM_DEBUG
+
+/* declarations for highmem.c */
+extern unsigned long highstart_pfn, highend_pfn;
+
+extern pte_t *kmap_pte;
+extern pgprot_t kmap_prot;
+extern pte_t *pkmap_page_table;
+
+extern void __init kmap_init(void);
+
+/*
+ * Right now we initialize only a single pte table. It can be extended
+ * easily, subsequent pte tables have to be allocated in one physical
+ * chunk of RAM.
+ */
+#define PKMAP_BASE 0xfe000000UL
+#define LAST_PKMAP 1024
+#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
+#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+
+extern unsigned long __fastcall kmap_high(struct page *page);
+extern void __fastcall kunmap_high(struct page *page);
+
+static inline unsigned long kmap(struct page *page)
+{
+ if (in_interrupt())
+ BUG();
+ if (page < highmem_start_page)
+ return page_address(page);
+ return kmap_high(page);
+}
+
+static inline void kunmap(struct page *page)
+{
+ if (in_interrupt())
+ BUG();
+ if (page < highmem_start_page)
+ return;
+ kunmap_high(page);
+}
+
+/*
+ * The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
+ * gives a more generic (and caching) interface. But kmap_atomic can
+ * be used in IRQ contexts, so in some (very limited) cases we need
+ * it.
+ */
+static inline unsigned long kmap_atomic(struct page *page, enum km_type type)
+{
+ enum fixed_addresses idx;
+ unsigned long vaddr;
+
+ if (page < highmem_start_page)
+ return page_address(page);
+
+ idx = type + KM_TYPE_NR * smp_processor_id();
+ vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+#if HIGHMEM_DEBUG
+ if (!pte_none(*(kmap_pte - idx)))
+ BUG();
+#endif
+ set_pte(kmap_pte - idx, mk_pte(page, kmap_prot));
+ __flush_tlb_one(vaddr);
+
+ return vaddr;
+}
+
+static inline void kunmap_atomic(unsigned long vaddr, enum km_type type)
+{
+#if HIGHMEM_DEBUG
+ enum fixed_addresses idx = type + KM_TYPE_NR * smp_processor_id();
+
+ if (vaddr < FIXADDR_START) /* FIXME */
+ return;
+
+ if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx))
+ BUG();
+
+ /*
+ * force other mappings to Oops if they'll try to access
+ * this pte without first remap it
+ */
+ pte_clear(kmap_pte - idx);
+ __flush_tlb_one(vaddr);
+#endif
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_HIGHMEM_H */
--- /dev/null
+/* MN10300 Hardware interrupt definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_HW_IRQ_H
+#define _ASM_HW_IRQ_H
+
+#endif /* _ASM_HW_IRQ_H */
--- /dev/null
+/* MN10300 Arch-specific IDE code
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ * - Derived from include/asm-i386/ide.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_IDE_H
+#define _ASM_IDE_H
+
+#ifdef __KERNEL__
+
+#include <asm/intctl-regs.h>
+
+#undef SUPPORT_SLOW_DATA_PORTS
+#define SUPPORT_SLOW_DATA_PORTS 0
+
+#undef SUPPORT_VLB_SYNC
+#define SUPPORT_VLB_SYNC 0
+
+#ifndef MAX_HWIFS
+#define MAX_HWIFS 8
+#endif
+
+/*
+ * some bits needed for parts of the IDE subsystem to compile
+ */
+#define __ide_mm_insw(port, addr, n) \
+ insw((unsigned long) (port), (addr), (n))
+#define __ide_mm_insl(port, addr, n) \
+ insl((unsigned long) (port), (addr), (n))
+#define __ide_mm_outsw(port, addr, n) \
+ outsw((unsigned long) (port), (addr), (n))
+#define __ide_mm_outsl(port, addr, n) \
+ outsl((unsigned long) (port), (addr), (n))
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_IDE_H */
--- /dev/null
+/* MN10300 On-board interrupt controller registers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_INTCTL_REGS_H
+#define _ASM_INTCTL_REGS_H
+
+#include <asm/cpu-regs.h>
+
+#ifdef __KERNEL__
+
+/* interrupt controller registers */
+#define GxICR(X) __SYSREG(0xd4000000 + (X) * 4, u16) /* group irq ctrl regs */
+
+#define IAGR __SYSREG(0xd4000100, u16) /* intr acceptance group reg */
+#define IAGR_GN 0x00fc /* group number register
+ * (documentation _has_ to be wrong)
+ */
+
+#define EXTMD __SYSREG(0xd4000200, u16) /* external pin intr spec reg */
+#define GET_XIRQ_TRIGGER(X) ((EXTMD >> ((X) * 2)) & 3)
+
+#define SET_XIRQ_TRIGGER(X,Y) \
+do { \
+ u16 x = EXTMD; \
+ x &= ~(3 << ((X) * 2)); \
+ x |= ((Y) & 3) << ((X) * 2); \
+ EXTMD = x; \
+} while (0)
+
+#define XIRQ_TRIGGER_LOWLEVEL 0
+#define XIRQ_TRIGGER_HILEVEL 1
+#define XIRQ_TRIGGER_NEGEDGE 2
+#define XIRQ_TRIGGER_POSEDGE 3
+
+/* non-maskable interrupt control */
+#define NMIIRQ 0
+#define NMICR GxICR(NMIIRQ) /* NMI control register */
+#define NMICR_NMIF 0x0001 /* NMI pin interrupt flag */
+#define NMICR_WDIF 0x0002 /* watchdog timer overflow flag */
+#define NMICR_ABUSERR 0x0008 /* async bus error flag */
+
+/* maskable interrupt control */
+#define GxICR_DETECT 0x0001 /* interrupt detect flag */
+#define GxICR_REQUEST 0x0010 /* interrupt request flag */
+#define GxICR_ENABLE 0x0100 /* interrupt enable flag */
+#define GxICR_LEVEL 0x7000 /* interrupt priority level */
+#define GxICR_LEVEL_0 0x0000 /* - level 0 */
+#define GxICR_LEVEL_1 0x1000 /* - level 1 */
+#define GxICR_LEVEL_2 0x2000 /* - level 2 */
+#define GxICR_LEVEL_3 0x3000 /* - level 3 */
+#define GxICR_LEVEL_4 0x4000 /* - level 4 */
+#define GxICR_LEVEL_5 0x5000 /* - level 5 */
+#define GxICR_LEVEL_6 0x6000 /* - level 6 */
+#define GxICR_LEVEL_SHIFT 12
+
+#ifndef __ASSEMBLY__
+extern void set_intr_level(int irq, u16 level);
+extern void set_intr_postackable(int irq);
+#endif
+
+/* external interrupts */
+#define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_INTCTL_REGS_H */
--- /dev/null
+/* MN10300 I/O port emulation and memory-mapped I/O
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_IO_H
+#define _ASM_IO_H
+
+#include <asm/page.h> /* I/O is all done through memory accesses */
+#include <asm/cpu-regs.h>
+#include <asm/cacheflush.h>
+
+#define mmiowb() do {} while (0)
+
+/*****************************************************************************/
+/*
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the x86 architecture, we just read/write the
+ * memory location directly.
+ */
+static inline u8 readb(const volatile void __iomem *addr)
+{
+ return *(const volatile u8 *) addr;
+}
+
+static inline u16 readw(const volatile void __iomem *addr)
+{
+ return *(const volatile u16 *) addr;
+}
+
+static inline u32 readl(const volatile void __iomem *addr)
+{
+ return *(const volatile u32 *) addr;
+}
+
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+
+#define readb_relaxed readb
+#define readw_relaxed readw
+#define readl_relaxed readl
+
+static inline void writeb(u8 b, volatile void __iomem *addr)
+{
+ *(volatile u8 *) addr = b;
+}
+
+static inline void writew(u16 b, volatile void __iomem *addr)
+{
+ *(volatile u16 *) addr = b;
+}
+
+static inline void writel(u32 b, volatile void __iomem *addr)
+{
+ *(volatile u32 *) addr = b;
+}
+
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+
+/*****************************************************************************/
+/*
+ * traditional input/output functions
+ */
+static inline u8 inb_local(unsigned long addr)
+{
+ return readb((volatile void __iomem *) addr);
+}
+
+static inline void outb_local(u8 b, unsigned long addr)
+{
+ return writeb(b, (volatile void __iomem *) addr);
+}
+
+static inline u8 inb(unsigned long addr)
+{
+ return readb((volatile void __iomem *) addr);
+}
+
+static inline u16 inw(unsigned long addr)
+{
+ return readw((volatile void __iomem *) addr);
+}
+
+static inline u32 inl(unsigned long addr)
+{
+ return readl((volatile void __iomem *) addr);
+}
+
+static inline void outb(u8 b, unsigned long addr)
+{
+ return writeb(b, (volatile void __iomem *) addr);
+}
+
+static inline void outw(u16 b, unsigned long addr)
+{
+ return writew(b, (volatile void __iomem *) addr);
+}
+
+static inline void outl(u32 b, unsigned long addr)
+{
+ return writel(b, (volatile void __iomem *) addr);
+}
+
+#define inb_p(addr) inb(addr)
+#define inw_p(addr) inw(addr)
+#define inl_p(addr) inl(addr)
+#define outb_p(x, addr) outb((x), (addr))
+#define outw_p(x, addr) outw((x), (addr))
+#define outl_p(x, addr) outl((x), (addr))
+
+static inline void insb(unsigned long addr, void *buffer, int count)
+{
+ if (count) {
+ u8 *buf = buffer;
+ do {
+ u8 x = inb(addr);
+ *buf++ = x;
+ } while (--count);
+ }
+}
+
+static inline void insw(unsigned long addr, void *buffer, int count)
+{
+ if (count) {
+ u16 *buf = buffer;
+ do {
+ u16 x = inw(addr);
+ *buf++ = x;
+ } while (--count);
+ }
+}
+
+static inline void insl(unsigned long addr, void *buffer, int count)
+{
+ if (count) {
+ u32 *buf = buffer;
+ do {
+ u32 x = inl(addr);
+ *buf++ = x;
+ } while (--count);
+ }
+}
+
+static inline void outsb(unsigned long addr, const void *buffer, int count)
+{
+ if (count) {
+ const u8 *buf = buffer;
+ do {
+ outb(*buf++, addr);
+ } while (--count);
+ }
+}
+
+static inline void outsw(unsigned long addr, const void *buffer, int count)
+{
+ if (count) {
+ const u16 *buf = buffer;
+ do {
+ outw(*buf++, addr);
+ } while (--count);
+ }
+}
+
+extern void __outsl(unsigned long addr, const void *buffer, int count);
+static inline void outsl(unsigned long addr, const void *buffer, int count)
+{
+ if ((unsigned long) buffer & 0x3)
+ return __outsl(addr, buffer, count);
+
+ if (count) {
+ const u32 *buf = buffer;
+ do {
+ outl(*buf++, addr);
+ } while (--count);
+ }
+}
+
+#define ioread8(addr) readb(addr)
+#define ioread16(addr) readw(addr)
+#define ioread32(addr) readl(addr)
+
+#define iowrite8(v, addr) writeb((v), (addr))
+#define iowrite16(v, addr) writew((v), (addr))
+#define iowrite32(v, addr) writel((v), (addr))
+
+#define ioread8_rep(p, dst, count) \
+ insb((unsigned long) (p), (dst), (count))
+#define ioread16_rep(p, dst, count) \
+ insw((unsigned long) (p), (dst), (count))
+#define ioread32_rep(p, dst, count) \
+ insl((unsigned long) (p), (dst), (count))
+
+#define iowrite8_rep(p, src, count) \
+ outsb((unsigned long) (p), (src), (count))
+#define iowrite16_rep(p, src, count) \
+ outsw((unsigned long) (p), (src), (count))
+#define iowrite32_rep(p, src, count) \
+ outsl((unsigned long) (p), (src), (count))
+
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#ifdef __KERNEL__
+
+#include <linux/vmalloc.h>
+#define __io_virt(x) ((void *) (x))
+
+/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
+struct pci_dev;
+extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
+static inline void pci_iounmap(struct pci_dev *dev, void __iomem *p)
+{
+}
+
+/*
+ * Change virtual addresses to physical addresses and vv.
+ * These are pretty trivial
+ */
+static inline unsigned long virt_to_phys(volatile void *address)
+{
+ return __pa(address);
+}
+
+static inline void *phys_to_virt(unsigned long address)
+{
+ return __va(address);
+}
+
+/*
+ * Change "struct page" to physical address.
+ */
+static inline void *__ioremap(unsigned long offset, unsigned long size,
+ unsigned long flags)
+{
+ return (void *) offset;
+}
+
+static inline void *ioremap(unsigned long offset, unsigned long size)
+{
+ return (void *) offset;
+}
+
+/*
+ * This one maps high address device memory and turns off caching for that
+ * area. it's useful if some control registers are in such an area and write
+ * combining or read caching is not desirable:
+ */
+static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
+{
+ return (void *) (offset | 0x20000000);
+}
+
+static inline void iounmap(void *addr)
+{
+}
+
+static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
+{
+ return (void __iomem *) port;
+}
+
+static inline void ioport_unmap(void __iomem *p)
+{
+}
+
+#define xlate_dev_kmem_ptr(p) ((void *) (p))
+#define xlate_dev_mem_ptr(p) ((void *) (p))
+
+/*
+ * PCI bus iomem addresses must be in the region 0x80000000-0x9fffffff
+ */
+static inline unsigned long virt_to_bus(volatile void *address)
+{
+ return ((unsigned long) address) & ~0x20000000;
+}
+
+static inline void *bus_to_virt(unsigned long address)
+{
+ return (void *) address;
+}
+
+#define page_to_bus page_to_phys
+
+#define memset_io(a, b, c) memset(__io_virt(a), (b), (c))
+#define memcpy_fromio(a, b, c) memcpy((a), __io_virt(b), (c))
+#define memcpy_toio(a, b, c) memcpy(__io_virt(a), (b), (c))
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IO_H */
--- /dev/null
+#include <asm-generic/ioctl.h>
--- /dev/null
+#ifndef _ASM_IOCTLS_H
+#define _ASM_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+/* 0x54 is just a magic number to make these relatively unique ('T') */
+
+#define TCGETS 0x5401
+#define TCSETS 0x5402
+#define TCSETSW 0x5403
+#define TCSETSF 0x5404
+#define TCGETA 0x5405
+#define TCSETA 0x5406
+#define TCSETAW 0x5407
+#define TCSETAF 0x5408
+#define TCSBRK 0x5409
+#define TCXONC 0x540A
+#define TCFLSH 0x540B
+#define TIOCEXCL 0x540C
+#define TIOCNXCL 0x540D
+#define TIOCSCTTY 0x540E
+#define TIOCGPGRP 0x540F
+#define TIOCSPGRP 0x5410
+#define TIOCOUTQ 0x5411
+#define TIOCSTI 0x5412
+#define TIOCGWINSZ 0x5413
+#define TIOCSWINSZ 0x5414
+#define TIOCMGET 0x5415
+#define TIOCMBIS 0x5416
+#define TIOCMBIC 0x5417
+#define TIOCMSET 0x5418
+#define TIOCGSOFTCAR 0x5419
+#define TIOCSSOFTCAR 0x541A
+#define FIONREAD 0x541B
+#define TIOCINQ FIONREAD
+#define TIOCLINUX 0x541C
+#define TIOCCONS 0x541D
+#define TIOCGSERIAL 0x541E
+#define TIOCSSERIAL 0x541F
+#define TIOCPKT 0x5420
+#define FIONBIO 0x5421
+#define TIOCNOTTY 0x5422
+#define TIOCSETD 0x5423
+#define TIOCGETD 0x5424
+#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
+/* #define TIOCTTYGSTRUCT 0x5426 - Former debugging-only ioctl */
+#define TIOCSBRK 0x5427 /* BSD compatibility */
+#define TIOCCBRK 0x5428 /* BSD compatibility */
+#define TIOCGSID 0x5429 /* Return the session ID of FD */
+#define TCGETS2 _IOR('T', 0x2A, struct termios2)
+#define TCSETS2 _IOW('T', 0x2B, struct termios2)
+#define TCSETSW2 _IOW('T', 0x2C, struct termios2)
+#define TCSETSF2 _IOW('T', 0x2D, struct termios2)
+#define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number
+ * (of pty-mux device) */
+#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */
+
+#define FIONCLEX 0x5450
+#define FIOCLEX 0x5451
+#define FIOASYNC 0x5452
+#define TIOCSERCONFIG 0x5453
+#define TIOCSERGWILD 0x5454
+#define TIOCSERSWILD 0x5455
+#define TIOCGLCKTRMIOS 0x5456
+#define TIOCSLCKTRMIOS 0x5457
+#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
+#define TIOCSERGETLSR 0x5459 /* Get line status register */
+#define TIOCSERGETMULTI 0x545A /* Get multiport config */
+#define TIOCSERSETMULTI 0x545B /* Set multiport config */
+
+#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
+#define TIOCGHAYESESP 0x545E /* Get Hayes ESP configuration */
+#define TIOCSHAYESESP 0x545F /* Set Hayes ESP configuration */
+#define FIOQSIZE 0x5460
+
+/* Used for packet mode */
+#define TIOCPKT_DATA 0
+#define TIOCPKT_FLUSHREAD 1
+#define TIOCPKT_FLUSHWRITE 2
+#define TIOCPKT_STOP 4
+#define TIOCPKT_START 8
+#define TIOCPKT_NOSTOP 16
+#define TIOCPKT_DOSTOP 32
+
+#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
+
+#endif /* _ASM_IOCTLS_H */
--- /dev/null
+#include <asm-generic/ipc.h>
--- /dev/null
+#ifndef _ASM_IPCBUF_H_
+#define _ASM_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for MN10300 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit mode_t and seq
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct ipc64_perm
+{
+ __kernel_key_t key;
+ __kernel_uid32_t uid;
+ __kernel_gid32_t gid;
+ __kernel_uid32_t cuid;
+ __kernel_gid32_t cgid;
+ __kernel_mode_t mode;
+ unsigned short __pad1;
+ unsigned short seq;
+ unsigned short __pad2;
+ unsigned long __unused1;
+ unsigned long __unused2;
+};
+
+#endif /* _ASM_IPCBUF_H */
--- /dev/null
+/* MN10300 Hardware interrupt definitions
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Modified by David Howells (dhowells@redhat.com)
+ * - Derived from include/asm-i386/irq.h:
+ * - (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_IRQ_H
+#define _ASM_IRQ_H
+
+#include <asm/intctl-regs.h>
+#include <asm/reset-regs.h>
+#include <asm/proc/irq.h>
+
+/* this number is used when no interrupt has been assigned */
+#define NO_IRQ INT_MAX
+
+/* hardware irq numbers */
+#define NR_IRQS GxICR_NUM_IRQS
+
+/* external hardware irq numbers */
+#define NR_XIRQS GxICR_NUM_XIRQS
+
+#define irq_canonicalize(IRQ) (IRQ)
+
+#endif /* _ASM_IRQ_H */
--- /dev/null
+/* MN10300 IRQ registers pointer definition
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_IRQ_REGS_H
+#define _ASM_IRQ_REGS_H
+
+/*
+ * Per-cpu current frame pointer - the location of the last exception frame on
+ * the stack
+ */
+#define ARCH_HAS_OWN_IRQ_REGS
+
+#ifndef __ASSEMBLY__
+#define get_irq_regs() (__frame)
+#endif
+
+#endif /* _ASM_IRQ_REGS_H */
--- /dev/null
+/* MN10300 In-kernel death knells
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_KDEBUG_H
+#define _ASM_KDEBUG_H
+
+/* Grossly misnamed. */
+enum die_val {
+ DIE_OOPS = 1,
+ DIE_BREAKPOINT,
+ DIE_GPF,
+};
+
+#endif /* _ASM_KDEBUG_H */
--- /dev/null
+/* MN10300 kmap_atomic() slot IDs
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_KMAP_TYPES_H
+#define _ASM_KMAP_TYPES_H
+
+enum km_type {
+ KM_BOUNCE_READ,
+ KM_SKB_SUNRPC_DATA,
+ KM_SKB_DATA_SOFTIRQ,
+ KM_USER0,
+ KM_USER1,
+ KM_BIO_SRC_IRQ,
+ KM_BIO_DST_IRQ,
+ KM_PTE0,
+ KM_PTE1,
+ KM_IRQ0,
+ KM_IRQ1,
+ KM_SOFTIRQ0,
+ KM_SOFTIRQ1,
+ KM_TYPE_NR
+};
+
+#endif /* _ASM_KMAP_TYPES_H */
--- /dev/null
+/* MN10300 Kernel Probes support
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by Mark Salter (msalter@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public Licence as published by
+ * the Free Software Foundation; either version 2 of the Licence, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public Licence for more details.
+ *
+ * You should have received a copy of the GNU General Public Licence
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ */
+#ifndef _ASM_KPROBES_H
+#define _ASM_KPROBES_H
+
+#include <linux/types.h>
+#include <linux/ptrace.h>
+
+struct kprobe;
+
+typedef unsigned char kprobe_opcode_t;
+#define BREAKPOINT_INSTRUCTION 0xff
+#define MAX_INSN_SIZE 8
+#define MAX_STACK_SIZE 128
+
+/* Architecture specific copy of original instruction */
+struct arch_specific_insn {
+ /* copy of original instruction
+ */
+ kprobe_opcode_t insn[MAX_INSN_SIZE];
+};
+
+extern const int kretprobe_blacklist_size;
+
+extern int kprobe_exceptions_notify(struct notifier_block *self,
+ unsigned long val, void *data);
+
+#define flush_insn_slot(p) do {} while (0)
+
+extern void arch_remove_kprobe(struct kprobe *p);
+
+#endif /* _ASM_KPROBES_H */
--- /dev/null
+/* MN10300 Linkage and calling-convention overrides
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_LINKAGE_H
+#define _ASM_LINKAGE_H
+
+/* don't override anything */
+#define asmlinkage
+#define FASTCALL(x) x
+#define fastcall
+
+#define __ALIGN .align 4,0xcb
+#define __ALIGN_STR ".align 4,0xcb"
+
+#endif
--- /dev/null
+#include <asm-generic/local.h>
--- /dev/null
+#include <asm/rtc-regs.h>
--- /dev/null
+/* MN10300 Constants for mmap and co.
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * - Derived from asm-x86/mman.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_MMAN_H
+#define _ASM_MMAN_H
+
+#include <asm-generic/mman.h>
+
+#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
+#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
+#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
+#define MAP_LOCKED 0x2000 /* pages are locked */
+#define MAP_NORESERVE 0x4000 /* don't check for reservations */
+#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
+#define MAP_NONBLOCK 0x10000 /* do not block on IO */
+
+#define MCL_CURRENT 1 /* lock all current mappings */
+#define MCL_FUTURE 2 /* lock all future mappings */
+
+#endif /* _ASM_MMAN_H */
--- /dev/null
+/* MN10300 Memory management context
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ * - Derived from include/asm-frv/mmu.h
+ */
+
+#ifndef _ASM_MMU_H
+#define _ASM_MMU_H
+
+/*
+ * MMU context
+ */
+typedef struct {
+ unsigned long tlbpid[NR_CPUS]; /* TLB PID for this process on
+ * each CPU */
+} mm_context_t;
+
+#endif /* _ASM_MMU_H */
--- /dev/null
+/* MN10300 MMU context management
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Modified by David Howells (dhowells@redhat.com)
+ * - Derived from include/asm-m32r/mmu_context.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ *
+ *
+ * This implements an algorithm to provide TLB PID mappings to provide
+ * selective access to the TLB for processes, thus reducing the number of TLB
+ * flushes required.
+ *
+ * Note, however, that the M32R algorithm is technically broken as it does not
+ * handle version wrap-around, and could, theoretically, have a problem with a
+ * very long lived program that sleeps long enough for the version number to
+ * wrap all the way around so that its TLB mappings appear valid once again.
+ */
+#ifndef _ASM_MMU_CONTEXT_H
+#define _ASM_MMU_CONTEXT_H
+
+#include <asm/atomic.h>
+#include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+#include <asm-generic/mm_hooks.h>
+
+#define MMU_CONTEXT_TLBPID_MASK 0x000000ffUL
+#define MMU_CONTEXT_VERSION_MASK 0xffffff00UL
+#define MMU_CONTEXT_FIRST_VERSION 0x00000100UL
+#define MMU_NO_CONTEXT 0x00000000UL
+
+extern unsigned long mmu_context_cache[NR_CPUS];
+#define mm_context(mm) (mm->context.tlbpid[smp_processor_id()])
+
+#define enter_lazy_tlb(mm, tsk) do {} while (0)
+
+#ifdef CONFIG_SMP
+#define cpu_ran_vm(cpu, task) \
+ cpu_set((cpu), (task)->cpu_vm_mask)
+#define cpu_maybe_ran_vm(cpu, task) \
+ cpu_test_and_set((cpu), (task)->cpu_vm_mask)
+#else
+#define cpu_ran_vm(cpu, task) do {} while (0)
+#define cpu_maybe_ran_vm(cpu, task) true
+#endif /* CONFIG_SMP */
+
+/*
+ * allocate an MMU context
+ */
+static inline unsigned long allocate_mmu_context(struct mm_struct *mm)
+{
+ unsigned long *pmc = &mmu_context_cache[smp_processor_id()];
+ unsigned long mc = ++(*pmc);
+
+ if (!(mc & MMU_CONTEXT_TLBPID_MASK)) {
+ /* we exhausted the TLB PIDs of this version on this CPU, so we
+ * flush this CPU's TLB in its entirety and start new cycle */
+ flush_tlb_all();
+
+ /* fix the TLB version if needed (we avoid version #0 so as to
+ * distingush MMU_NO_CONTEXT) */
+ if (!mc)
+ *pmc = mc = MMU_CONTEXT_FIRST_VERSION;
+ }
+ mm_context(mm) = mc;
+ return mc;
+}
+
+/*
+ * get an MMU context if one is needed
+ */
+static inline unsigned long get_mmu_context(struct mm_struct *mm)
+{
+ unsigned long mc = MMU_NO_CONTEXT, cache;
+
+ if (mm) {
+ cache = mmu_context_cache[smp_processor_id()];
+ mc = mm_context(mm);
+
+ /* if we have an old version of the context, replace it */
+ if ((mc ^ cache) & MMU_CONTEXT_VERSION_MASK)
+ mc = allocate_mmu_context(mm);
+ }
+ return mc;
+}
+
+/*
+ * initialise the context related info for a new mm_struct instance
+ */
+static inline int init_new_context(struct task_struct *tsk,
+ struct mm_struct *mm)
+{
+ int num_cpus = NR_CPUS, i;
+
+ for (i = 0; i < num_cpus; i++)
+ mm->context.tlbpid[i] = MMU_NO_CONTEXT;
+ return 0;
+}
+
+/*
+ * destroy context related info for an mm_struct that is about to be put to
+ * rest
+ */
+#define destroy_context(mm) do { } while (0)
+
+/*
+ * after we have set current->mm to a new value, this activates the context for
+ * the new mm so we see the new mappings.
+ */
+static inline void activate_context(struct mm_struct *mm, int cpu)
+{
+ PIDR = get_mmu_context(mm) & MMU_CONTEXT_TLBPID_MASK;
+}
+
+/*
+ * change between virtual memory sets
+ */
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+ struct task_struct *tsk)
+{
+ int cpu = smp_processor_id();
+
+ if (prev != next) {
+ cpu_ran_vm(cpu, next);
+ activate_context(next, cpu);
+ PTBR = (unsigned long) next->pgd;
+ } else if (!cpu_maybe_ran_vm(cpu, next)) {
+ activate_context(next, cpu);
+ }
+}
+
+#define deactivate_mm(tsk, mm) do {} while (0)
+#define activate_mm(prev, next) switch_mm((prev), (next), NULL)
+
+#endif /* _ASM_MMU_CONTEXT_H */
--- /dev/null
+/* MN10300 Arch-specific module definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by Mark Salter (msalter@redhat.com)
+ * Derived from include/asm-i386/module.h
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_MODULE_H
+#define _ASM_MODULE_H
+
+struct mod_arch_specific {
+};
+
+#define Elf_Shdr Elf32_Shdr
+#define Elf_Sym Elf32_Sym
+#define Elf_Ehdr Elf32_Ehdr
+
+/*
+ * Include the MN10300 architecture version.
+ */
+#define MODULE_ARCH_VERMAGIC __stringify(PROCESSOR_MODEL_NAME) " "
+
+#endif /* _ASM_MODULE_H */
--- /dev/null
+#ifndef _ASM_MSGBUF_H
+#define _ASM_MSGBUF_H
+
+/*
+ * The msqid64_ds structure for MN10300 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct msqid64_ds {
+ struct ipc64_perm msg_perm;
+ __kernel_time_t msg_stime; /* last msgsnd time */
+ unsigned long __unused1;
+ __kernel_time_t msg_rtime; /* last msgrcv time */
+ unsigned long __unused2;
+ __kernel_time_t msg_ctime; /* last change time */
+ unsigned long __unused3;
+ unsigned long msg_cbytes; /* current number of bytes on queue */
+ unsigned long msg_qnum; /* number of messages in queue */
+ unsigned long msg_qbytes; /* max number of bytes on queue */
+ __kernel_pid_t msg_lspid; /* pid of last msgsnd */
+ __kernel_pid_t msg_lrpid; /* last receive pid */
+ unsigned long __unused4;
+ unsigned long __unused5;
+};
+
+#endif /* _ASM_MSGBUF_H */
--- /dev/null
+/* MN10300 Mutex fastpath
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ *
+ *
+ * TODO: implement optimized primitives instead, or leave the generic
+ * implementation in place, or pick the atomic_xchg() based generic
+ * implementation. (see asm-generic/mutex-xchg.h for details)
+ */
+#include <asm-generic/mutex-null.h>
--- /dev/null
+/* Emulation stuff
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_NAMEI_H
+#define _ASM_NAMEI_H
+
+/* This dummy routine maybe changed to something useful
+ * for /usr/gnemul/ emulation stuff.
+ * Look at asm-sparc/namei.h for details.
+ */
+
+#define __emul_prefix() NULL
+
+#endif /* _ASM_NAMEI_H */
--- /dev/null
+/* MN10300 NMI handling
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_NMI_H
+#define _ASM_NMI_H
+
+#endif /* _ASM_NMI_H */
--- /dev/null
+/* MN10300 Page table definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_PAGE_H
+#define _ASM_PAGE_H
+
+/* PAGE_SHIFT determines the page size */
+#define PAGE_SHIFT 12
+
+#ifndef __ASSEMBLY__
+#define PAGE_SIZE (1UL << PAGE_SHIFT)
+#define PAGE_MASK (~(PAGE_SIZE - 1))
+#else
+#define PAGE_SIZE +(1 << PAGE_SHIFT) /* unary plus marks an
+ * immediate val not an addr */
+#define PAGE_MASK +(~(PAGE_SIZE - 1))
+#endif
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+#define clear_page(page) memset((void *)(page), 0, PAGE_SIZE)
+#define copy_page(to, from) memcpy((void *)(to), (void *)(from), PAGE_SIZE)
+
+#define clear_user_page(addr, vaddr, page) clear_page(addr)
+#define copy_user_page(vto, vfrom, vaddr, to) copy_page(vto, vfrom)
+
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { unsigned long pte; } pte_t;
+typedef struct { unsigned long pgd; } pgd_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct page *pgtable_t;
+
+#define PTE_MASK PAGE_MASK
+#define HPAGE_SHIFT 22
+
+#ifdef CONFIG_HUGETLB_PAGE
+#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
+#define HPAGE_MASK (~(HPAGE_SIZE - 1))
+#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
+#endif
+
+#define pte_val(x) ((x).pte)
+#define pgd_val(x) ((x).pgd)
+#define pgprot_val(x) ((x).pgprot)
+
+#define __pte(x) ((pte_t) { (x) })
+#define __pgd(x) ((pgd_t) { (x) })
+#define __pgprot(x) ((pgprot_t) { (x) })
+
+#include <asm-generic/pgtable-nopmd.h>
+
+#endif /* !__ASSEMBLY__ */
+
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & PAGE_MASK)
+
+/*
+ * This handles the memory map.. We could make this a config
+ * option, but too many people screw it up, and too few need
+ * it.
+ *
+ * A __PAGE_OFFSET of 0xC0000000 means that the kernel has
+ * a virtual address space of one gigabyte, which limits the
+ * amount of physical memory you can use to about 950MB.
+ */
+
+#ifndef __ASSEMBLY__
+
+/* Pure 2^n version of get_order */
+static inline int get_order(unsigned long size) __attribute__((const));
+static inline int get_order(unsigned long size)
+{
+ int order;
+
+ size = (size - 1) >> (PAGE_SHIFT - 1);
+ order = -1;
+ do {
+ size >>= 1;
+ order++;
+ } while (size);
+ return order;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#include <asm/page_offset.h>
+
+#define __PAGE_OFFSET (PAGE_OFFSET_RAW)
+#define PAGE_OFFSET ((unsigned long) __PAGE_OFFSET)
+
+/*
+ * main RAM and kernel working space are coincident at 0x90000000, but to make
+ * life more interesting, there's also an uncached virtual shadow at 0xb0000000
+ * - these mappings are fixed in the MMU
+ */
+#define __pfn_disp (CONFIG_KERNEL_RAM_BASE_ADDRESS >> PAGE_SHIFT)
+
+#define __pa(x) ((unsigned long)(x))
+#define __va(x) ((void *)(unsigned long)(x))
+#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
+#define pfn_to_page(pfn) (mem_map + ((pfn) - __pfn_disp))
+#define page_to_pfn(page) ((unsigned long)((page) - mem_map) + __pfn_disp)
+
+#define pfn_valid(pfn) \
+({ \
+ unsigned long __pfn = (pfn) - __pfn_disp; \
+ __pfn < max_mapnr; \
+})
+
+#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
+#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
+
+#define VM_DATA_DEFAULT_FLAGS \
+ (VM_READ | VM_WRITE | \
+ ((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \
+ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_PAGE_H */
--- /dev/null
+/* MN10300 Kernel base address
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ */
+#ifndef _ASM_PAGE_OFFSET_H
+#define _ASM_PAGE_OFFSET_H
+
+#define PAGE_OFFSET_RAW CONFIG_KERNEL_RAM_BASE_ADDRESS
+
+#endif
--- /dev/null
+/* MN10300 Kernel parameters
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_PARAM_H
+#define _ASM_PARAM_H
+
+#ifdef __KERNEL__
+#define HZ 1000 /* Internal kernel timer frequency */
+#define USER_HZ 100 /* .. some user interfaces are in
+ * "ticks" */
+#define CLOCKS_PER_SEC (USER_HZ) /* like times() */
+#endif
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE 4096
+
+#ifndef NOGROUP
+#define NOGROUP (-1)
+#endif
+
+#define MAXHOSTNAMELEN 64 /* max length of hostname */
+#define COMMAND_LINE_SIZE 256
+
+#endif /* _ASM_PARAM_H */
--- /dev/null
+/* MN10300 PCI definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_PCI_H
+#define _ASM_PCI_H
+
+#ifdef __KERNEL__
+#include <linux/mm.h> /* for struct page */
+
+#if 0
+#define __pcbdebug(FMT, ADDR, ...) \
+ printk(KERN_DEBUG "PCIBRIDGE[%08x]: "FMT"\n", \
+ (u32)(ADDR), ##__VA_ARGS__)
+
+#define __pcidebug(FMT, BUS, DEVFN, WHERE,...) \
+do { \
+ printk(KERN_DEBUG "PCI[%02x:%02x.%x + %02x]: "FMT"\n", \
+ (BUS)->number, \
+ PCI_SLOT(DEVFN), \
+ PCI_FUNC(DEVFN), \
+ (u32)(WHERE), ##__VA_ARGS__); \
+} while (0)
+
+#else
+#define __pcbdebug(FMT, ADDR, ...) do {} while (0)
+#define __pcidebug(FMT, BUS, DEVFN, WHERE, ...) do {} while (0)
+#endif
+
+/* Can be used to override the logic in pci_scan_bus for skipping
+ * already-configured bus numbers - to be used for buggy BIOSes or
+ * architectures with incomplete PCI setup by the loader */
+
+#ifdef CONFIG_PCI
+#define pcibios_assign_all_busses() 1
+extern void unit_pci_init(void);
+#else
+#define pcibios_assign_all_busses() 0
+#endif
+
+extern unsigned long pci_mem_start;
+#define PCIBIOS_MIN_IO 0xBE000004
+#define PCIBIOS_MIN_MEM 0xB8000000
+
+void pcibios_set_master(struct pci_dev *dev);
+void pcibios_penalize_isa_irq(int irq);
+
+/* Dynamic DMA mapping stuff.
+ * i386 has everything mapped statically.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/scatterlist.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+
+struct pci_dev;
+
+/* The PCI address space does equal the physical memory
+ * address space. The networking and block device layers use
+ * this boolean for bounce buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS (1)
+
+
+/* This is always fine. */
+#define pci_dac_dma_supported(pci_dev, mask) (0)
+
+/*
+ * These macros should be used after a pci_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns.
+ */
+#define sg_dma_address(sg) ((sg)->dma_address)
+#define sg_dma_len(sg) ((sg)->length)
+
+/* Return the index of the PCI controller for device. */
+static inline int pci_controller_num(struct pci_dev *dev)
+{
+ return 0;
+}
+
+#define HAVE_PCI_MMAP
+extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+ enum pci_mmap_state mmap_state,
+ int write_combine);
+
+#endif /* __KERNEL__ */
+
+/* implement the pci_ DMA API in terms of the generic device dma_ one */
+#include <asm-generic/pci-dma-compat.h>
+
+/**
+ * pcibios_resource_to_bus - convert resource to PCI bus address
+ * @dev: device which owns this resource
+ * @region: converted bus-centric region (start,end)
+ * @res: resource to convert
+ *
+ * Convert a resource to a PCI device bus address or bus window.
+ */
+extern void pcibios_resource_to_bus(struct pci_dev *dev,
+ struct pci_bus_region *region,
+ struct resource *res);
+
+extern void pcibios_bus_to_resource(struct pci_dev *dev,
+ struct resource *res,
+ struct pci_bus_region *region);
+
+static inline struct resource *
+pcibios_select_root(struct pci_dev *pdev, struct resource *res)
+{
+ struct resource *root = NULL;
+
+ if (res->flags & IORESOURCE_IO)
+ root = &ioport_resource;
+ if (res->flags & IORESOURCE_MEM)
+ root = &iomem_resource;
+
+ return root;
+}
+
+#define pcibios_scan_all_fns(a, b) 0
+
+#endif /* _ASM_PCI_H */
--- /dev/null
+#include <asm-generic/percpu.h>
--- /dev/null
+/* MN10300 Page and page table/directory allocation
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_PGALLOC_H
+#define _ASM_PGALLOC_H
+
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <linux/threads.h>
+#include <linux/mm.h> /* for struct page */
+
+struct mm_struct;
+struct page;
+
+/* attach a page table to a PMD entry */
+#define pmd_populate_kernel(mm, pmd, pte) \
+ set_pmd(pmd, __pmd(__pa(pte) | _PAGE_TABLE))
+
+static inline
+void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte)
+{
+ set_pmd(pmd, __pmd((page_to_pfn(pte) << PAGE_SHIFT) | _PAGE_TABLE));
+}
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
+/*
+ * Allocate and free page tables.
+ */
+
+extern pgd_t *pgd_alloc(struct mm_struct *);
+extern void pgd_free(struct mm_struct *, pgd_t *);
+
+extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long);
+extern struct page *pte_alloc_one(struct mm_struct *, unsigned long);
+
+static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
+{
+ free_page((unsigned long) pte);
+}
+
+static inline void pte_free(struct mm_struct *mm, struct page *pte)
+{
+ __free_page(pte);
+}
+
+
+#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte))
+
+#endif /* _ASM_PGALLOC_H */
--- /dev/null
+/* MN10300 Page table manipulators and constants
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ *
+ *
+ * The Linux memory management assumes a three-level page table setup. On
+ * the i386, we use that, but "fold" the mid level into the top-level page
+ * table, so that we physically have the same two-level page table as the
+ * i386 mmu expects.
+ *
+ * This file contains the functions and defines necessary to modify and use
+ * the i386 page table tree for the purposes of the MN10300 TLB handler
+ * functions.
+ */
+#ifndef _ASM_PGTABLE_H
+#define _ASM_PGTABLE_H
+
+#include <asm/cpu-regs.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <linux/threads.h>
+
+#include <asm/bitops.h>
+
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+extern unsigned long empty_zero_page[1024];
+extern spinlock_t pgd_lock;
+extern struct page *pgd_list;
+
+extern void pmd_ctor(void *, struct kmem_cache *, unsigned long);
+extern void pgtable_cache_init(void);
+extern void paging_init(void);
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * The Linux mn10300 paging architecture only implements both the traditional
+ * 2-level page tables
+ */
+#define PGDIR_SHIFT 22
+#define PTRS_PER_PGD 1024
+#define PTRS_PER_PUD 1 /* we don't really have any PUD physically */
+#define PTRS_PER_PMD 1 /* we don't really have any PMD physically */
+#define PTRS_PER_PTE 1024
+
+#define PGD_SIZE PAGE_SIZE
+#define PMD_SIZE (1UL << PMD_SHIFT)
+#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK (~(PGDIR_SIZE - 1))
+
+#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
+#define FIRST_USER_ADDRESS 0
+
+#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
+#define KERNEL_PGD_PTRS (PTRS_PER_PGD - USER_PGD_PTRS)
+
+#define TWOLEVEL_PGDIR_SHIFT 22
+#define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
+#define BOOT_KERNEL_PGD_PTRS (1024 - BOOT_USER_PGD_PTRS)
+
+#ifndef __ASSEMBLY__
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+#endif
+
+/*
+ * Unfortunately, due to the way the MMU works on the MN10300, the vmalloc VM
+ * area has to be in the lower half of the virtual address range (the upper
+ * half is not translated through the TLB).
+ *
+ * So in this case, the vmalloc area goes at the bottom of the address map
+ * (leaving a hole at the very bottom to catch addressing errors), and
+ * userspace starts immediately above.
+ *
+ * The vmalloc() routines also leaves a hole of 4kB between each vmalloced
+ * area to catch addressing errors.
+ */
+#define VMALLOC_OFFSET (8 * 1024 * 1024)
+#define VMALLOC_START (0x70000000)
+#define VMALLOC_END (0x7C000000)
+
+#ifndef __ASSEMBLY__
+extern pte_t kernel_vmalloc_ptes[(VMALLOC_END - VMALLOC_START) / PAGE_SIZE];
+#endif
+
+/* IPTEL/DPTEL bit assignments */
+#define _PAGE_BIT_VALID xPTEL_V_BIT
+#define _PAGE_BIT_ACCESSED xPTEL_UNUSED1_BIT /* mustn't be loaded into IPTEL/DPTEL */
+#define _PAGE_BIT_NX xPTEL_UNUSED2_BIT /* mustn't be loaded into IPTEL/DPTEL */
+#define _PAGE_BIT_CACHE xPTEL_C_BIT
+#define _PAGE_BIT_PRESENT xPTEL_PV_BIT
+#define _PAGE_BIT_DIRTY xPTEL_D_BIT
+#define _PAGE_BIT_GLOBAL xPTEL_G_BIT
+
+#define _PAGE_VALID xPTEL_V
+#define _PAGE_ACCESSED xPTEL_UNUSED1
+#define _PAGE_NX xPTEL_UNUSED2 /* no-execute bit */
+#define _PAGE_CACHE xPTEL_C
+#define _PAGE_PRESENT xPTEL_PV
+#define _PAGE_DIRTY xPTEL_D
+#define _PAGE_PROT xPTEL_PR
+#define _PAGE_PROT_RKNU xPTEL_PR_ROK
+#define _PAGE_PROT_WKNU xPTEL_PR_RWK
+#define _PAGE_PROT_RKRU xPTEL_PR_ROK_ROU
+#define _PAGE_PROT_WKRU xPTEL_PR_RWK_ROU
+#define _PAGE_PROT_WKWU xPTEL_PR_RWK_RWU
+#define _PAGE_GLOBAL xPTEL_G
+#define _PAGE_PSE xPTEL_PS_4Mb /* 4MB page */
+
+#define _PAGE_FILE xPTEL_UNUSED1_BIT /* set:pagecache unset:swap */
+
+#define __PAGE_PROT_UWAUX 0x040
+#define __PAGE_PROT_USER 0x080
+#define __PAGE_PROT_WRITE 0x100
+
+#define _PAGE_PRESENTV (_PAGE_PRESENT|_PAGE_VALID)
+#define _PAGE_PROTNONE 0x000 /* If not present */
+
+#ifndef __ASSEMBLY__
+
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+
+#define _PAGE_TABLE (_PAGE_PRESENTV | _PAGE_PROT_WKNU | _PAGE_ACCESSED | _PAGE_DIRTY)
+#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
+
+#define __PAGE_NONE (_PAGE_PRESENTV | _PAGE_PROT_RKNU | _PAGE_ACCESSED | _PAGE_CACHE)
+#define __PAGE_SHARED (_PAGE_PRESENTV | _PAGE_PROT_WKWU | _PAGE_ACCESSED | _PAGE_CACHE)
+#define __PAGE_COPY (_PAGE_PRESENTV | _PAGE_PROT_RKRU | _PAGE_ACCESSED | _PAGE_CACHE)
+#define __PAGE_READONLY (_PAGE_PRESENTV | _PAGE_PROT_RKRU | _PAGE_ACCESSED | _PAGE_CACHE)
+
+#define PAGE_NONE __pgprot(__PAGE_NONE | _PAGE_NX)
+#define PAGE_SHARED_NOEXEC __pgprot(__PAGE_SHARED | _PAGE_NX)
+#define PAGE_COPY_NOEXEC __pgprot(__PAGE_COPY | _PAGE_NX)
+#define PAGE_READONLY_NOEXEC __pgprot(__PAGE_READONLY | _PAGE_NX)
+#define PAGE_SHARED_EXEC __pgprot(__PAGE_SHARED)
+#define PAGE_COPY_EXEC __pgprot(__PAGE_COPY)
+#define PAGE_READONLY_EXEC __pgprot(__PAGE_READONLY)
+#define PAGE_COPY PAGE_COPY_NOEXEC
+#define PAGE_READONLY PAGE_READONLY_NOEXEC
+#define PAGE_SHARED PAGE_SHARED_EXEC
+
+#define __PAGE_KERNEL_BASE (_PAGE_PRESENTV | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_GLOBAL)
+
+#define __PAGE_KERNEL (__PAGE_KERNEL_BASE | _PAGE_PROT_WKNU | _PAGE_CACHE | _PAGE_NX)
+#define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL_BASE | _PAGE_PROT_WKNU | _PAGE_NX)
+#define __PAGE_KERNEL_EXEC (__PAGE_KERNEL & ~_PAGE_NX)
+#define __PAGE_KERNEL_RO (__PAGE_KERNEL_BASE | _PAGE_PROT_RKNU | _PAGE_CACHE | _PAGE_NX)
+#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
+#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
+
+#define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
+#define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
+#define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC)
+#define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
+#define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
+#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
+
+/*
+ * Whilst the MN10300 can do page protection for execute (given separate data
+ * and insn TLBs), we are not supporting it at the moment. Write permission,
+ * however, always implies read permission (but not execute permission).
+ */
+#define __P000 PAGE_NONE
+#define __P001 PAGE_READONLY_NOEXEC
+#define __P010 PAGE_COPY_NOEXEC
+#define __P011 PAGE_COPY_NOEXEC
+#define __P100 PAGE_READONLY_EXEC
+#define __P101 PAGE_READONLY_EXEC
+#define __P110 PAGE_COPY_EXEC
+#define __P111 PAGE_COPY_EXEC
+
+#define __S000 PAGE_NONE
+#define __S001 PAGE_READONLY_NOEXEC
+#define __S010 PAGE_SHARED_NOEXEC
+#define __S011 PAGE_SHARED_NOEXEC
+#define __S100 PAGE_READONLY_EXEC
+#define __S101 PAGE_READONLY_EXEC
+#define __S110 PAGE_SHARED_EXEC
+#define __S111 PAGE_SHARED_EXEC
+
+/*
+ * Define this to warn about kernel memory accesses that are
+ * done without a 'verify_area(VERIFY_WRITE,..)'
+ */
+#undef TEST_VERIFY_AREA
+
+#define pte_present(x) (pte_val(x) & _PAGE_VALID)
+#define pte_clear(mm, addr, xp) \
+do { \
+ set_pte_at((mm), (addr), (xp), __pte(0)); \
+} while (0)
+
+#define pmd_none(x) (!pmd_val(x))
+#define pmd_present(x) (!pmd_none(x))
+#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
+#define pmd_bad(x) 0
+
+
+#define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
+
+#ifndef __ASSEMBLY__
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static inline int pte_user(pte_t pte) { return pte_val(pte) & __PAGE_PROT_USER; }
+static inline int pte_read(pte_t pte) { return pte_val(pte) & __PAGE_PROT_USER; }
+static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
+static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_write(pte_t pte) { return pte_val(pte) & __PAGE_PROT_WRITE; }
+
+/*
+ * The following only works if pte_present() is not true.
+ */
+static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
+
+static inline pte_t pte_rdprotect(pte_t pte)
+{
+ pte_val(pte) &= ~(__PAGE_PROT_USER|__PAGE_PROT_UWAUX); return pte;
+}
+static inline pte_t pte_exprotect(pte_t pte)
+{
+ pte_val(pte) |= _PAGE_NX; return pte;
+}
+
+static inline pte_t pte_wrprotect(pte_t pte)
+{
+ pte_val(pte) &= ~(__PAGE_PROT_WRITE|__PAGE_PROT_UWAUX); return pte;
+}
+
+static inline pte_t pte_mkclean(pte_t pte) { pte_val(pte) &= ~_PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkold(pte_t pte) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkexec(pte_t pte) { pte_val(pte) &= ~_PAGE_NX; return pte; }
+
+static inline pte_t pte_mkread(pte_t pte)
+{
+ pte_val(pte) |= __PAGE_PROT_USER;
+ if (pte_write(pte))
+ pte_val(pte) |= __PAGE_PROT_UWAUX;
+ return pte;
+}
+static inline pte_t pte_mkwrite(pte_t pte)
+{
+ pte_val(pte) |= __PAGE_PROT_WRITE;
+ if (pte_val(pte) & __PAGE_PROT_USER)
+ pte_val(pte) |= __PAGE_PROT_UWAUX;
+ return pte;
+}
+
+#define pte_ERROR(e) \
+ printk(KERN_ERR "%s:%d: bad pte %08lx.\n", \
+ __FILE__, __LINE__, pte_val(e))
+#define pgd_ERROR(e) \
+ printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
+ __FILE__, __LINE__, pgd_val(e))
+
+/*
+ * The "pgd_xxx()" functions here are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ */
+#define pgd_clear(xp) do { } while (0)
+
+/*
+ * Certain architectures need to do special things when PTEs
+ * within a page table are directly modified. Thus, the following
+ * hook is made available.
+ */
+#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
+#define set_pte_at(mm, addr, ptep, pteval) set_pte((ptep), (pteval))
+#define set_pte_atomic(pteptr, pteval) set_pte((pteptr), (pteval))
+
+/*
+ * (pmds are folded into pgds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
+
+#define ptep_get_and_clear(mm, addr, ptep) \
+ __pte(xchg(&(ptep)->pte, 0))
+#define pte_same(a, b) (pte_val(a) == pte_val(b))
+#define pte_page(x) pfn_to_page(pte_pfn(x))
+#define pte_none(x) (!pte_val(x))
+#define pte_pfn(x) ((unsigned long) (pte_val(x) >> PAGE_SHIFT))
+#define __pfn_addr(pfn) ((pfn) << PAGE_SHIFT)
+#define pfn_pte(pfn, prot) __pte(__pfn_addr(pfn) | pgprot_val(prot))
+#define pfn_pmd(pfn, prot) __pmd(__pfn_addr(pfn) | pgprot_val(prot))
+
+/*
+ * All present user pages are user-executable:
+ */
+static inline int pte_exec(pte_t pte)
+{
+ return pte_user(pte);
+}
+
+/*
+ * All present pages are kernel-executable:
+ */
+static inline int pte_exec_kernel(pte_t pte)
+{
+ return 1;
+}
+
+/*
+ * Bits 0 and 1 are taken, split up the 29 bits of offset
+ * into this range:
+ */
+#define PTE_FILE_MAX_BITS 29
+
+#define pte_to_pgoff(pte) (pte_val(pte) >> 2)
+#define pgoff_to_pte(off) __pte((off) << 2 | _PAGE_FILE)
+
+/* Encode and de-code a swap entry */
+#define __swp_type(x) (((x).val >> 2) & 0x3f)
+#define __swp_offset(x) ((x).val >> 8)
+#define __swp_entry(type, offset) \
+ ((swp_entry_t) { ((type) << 2) | ((offset) << 8) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x) __pte((x).val)
+
+static inline
+int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned long addr,
+ pte_t *ptep)
+{
+ if (!pte_dirty(*ptep))
+ return 0;
+ return test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte);
+}
+
+static inline
+int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
+ pte_t *ptep)
+{
+ if (!pte_young(*ptep))
+ return 0;
+ return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte);
+}
+
+static inline
+void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+{
+ pte_val(*ptep) &= ~(__PAGE_PROT_WRITE|__PAGE_PROT_UWAUX);
+}
+
+static inline void ptep_mkdirty(pte_t *ptep)
+{
+ set_bit(_PAGE_BIT_DIRTY, &ptep->pte);
+}
+
+/*
+ * Macro to mark a page protection value as "uncacheable". On processors which
+ * do not support it, this is a no-op.
+ */
+#define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_CACHE)
+
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+
+#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
+#define mk_pte_huge(entry) \
+ ((entry).pte |= _PAGE_PRESENT | _PAGE_PSE | _PAGE_VALID)
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+ pte_val(pte) &= _PAGE_CHG_MASK;
+ pte_val(pte) |= pgprot_val(newprot);
+ return pte;
+}
+
+#define page_pte(page) page_pte_prot((page), __pgprot(0))
+
+#define pmd_page_kernel(pmd) \
+ ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
+
+#define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
+
+#define pmd_large(pmd) \
+ ((pmd_val(pmd) & (_PAGE_PSE | _PAGE_PRESENT)) == \
+ (_PAGE_PSE | _PAGE_PRESENT))
+
+/*
+ * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
+ *
+ * this macro returns the index of the entry in the pgd page which would
+ * control the given virtual address
+ */
+#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
+
+/*
+ * pgd_offset() returns a (pgd_t *)
+ * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
+ */
+#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
+
+/*
+ * a shortcut which implies the use of the kernel's pgd, instead
+ * of a process's
+ */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/*
+ * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
+ *
+ * this macro returns the index of the entry in the pmd page which would
+ * control the given virtual address
+ */
+#define pmd_index(address) \
+ (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
+
+/*
+ * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
+ *
+ * this macro returns the index of the entry in the pte page which would
+ * control the given virtual address
+ */
+#define pte_index(address) \
+ (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+
+#define pte_offset_kernel(dir, address) \
+ ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address))
+
+/*
+ * Make a given kernel text page executable/non-executable.
+ * Returns the previous executability setting of that page (which
+ * is used to restore the previous state). Used by the SMP bootup code.
+ * NOTE: this is an __init function for security reasons.
+ */
+static inline int set_kernel_exec(unsigned long vaddr, int enable)
+{
+ return 0;
+}
+
+#define pte_offset_map(dir, address) \
+ ((pte_t *) page_address(pmd_page(*(dir))) + pte_index(address))
+#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
+#define pte_unmap(pte) do {} while (0)
+#define pte_unmap_nested(pte) do {} while (0)
+
+/*
+ * The MN10300 has external MMU info in the form of a TLB: this is adapted from
+ * the kernel page tables containing the necessary information by tlb-mn10300.S
+ */
+extern void update_mmu_cache(struct vm_area_struct *vma,
+ unsigned long address, pte_t pte);
+
+#endif /* !__ASSEMBLY__ */
+
+#define kern_addr_valid(addr) (1)
+
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
+ remap_pfn_range((vma), (vaddr), (pfn), (size), (prot))
+
+#define MK_IOSPACE_PFN(space, pfn) (pfn)
+#define GET_IOSPACE(pfn) 0
+#define GET_PFN(pfn) (pfn)
+
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+#define __HAVE_ARCH_PTEP_MKDIRTY
+#define __HAVE_ARCH_PTE_SAME
+#include <asm-generic/pgtable.h>
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_PGTABLE_H */
--- /dev/null
+/* MN10300 On-board I/O port module registers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_PIO_REGS_H
+#define _ASM_PIO_REGS_H
+
+#include <asm/cpu-regs.h>
+#include <asm/intctl-regs.h>
+
+#ifdef __KERNEL__
+
+/* I/O port 0 */
+#define P0MD __SYSREG(0xdb000000, u16) /* mode reg */
+#define P0MD_0 0x0003 /* mask */
+#define P0MD_0_IN 0x0000 /* input mode */
+#define P0MD_0_OUT 0x0001 /* output mode */
+#define P0MD_0_TM0IO 0x0002 /* timer 0 I/O mode */
+#define P0MD_0_EYECLK 0x0003 /* test signal output (clock) */
+#define P0MD_1 0x000c
+#define P0MD_1_IN 0x0000
+#define P0MD_1_OUT 0x0004
+#define P0MD_1_TM1IO 0x0008 /* timer 1 I/O mode */
+#define P0MD_1_EYED 0x000c /* test signal output (data) */
+#define P0MD_2 0x0030
+#define P0MD_2_IN 0x0000
+#define P0MD_2_OUT 0x0010
+#define P0MD_2_TM2IO 0x0020 /* timer 2 I/O mode */
+#define P0MD_3 0x00c0
+#define P0MD_3_IN 0x0000
+#define P0MD_3_OUT 0x0040
+#define P0MD_3_TM3IO 0x0080 /* timer 3 I/O mode */
+#define P0MD_4 0x0300
+#define P0MD_4_IN 0x0000
+#define P0MD_4_OUT 0x0100
+#define P0MD_4_TM4IO 0x0200 /* timer 4 I/O mode */
+#define P0MD_4_XCTS 0x0300 /* XCTS input for serial port 2 */
+#define P0MD_5 0x0c00
+#define P0MD_5_IN 0x0000
+#define P0MD_5_OUT 0x0400
+#define P0MD_5_TM5IO 0x0800 /* timer 5 I/O mode */
+#define P0MD_6 0x3000
+#define P0MD_6_IN 0x0000
+#define P0MD_6_OUT 0x1000
+#define P0MD_6_TM6IOA 0x2000 /* timer 6 I/O mode A */
+#define P0MD_7 0xc000
+#define P0MD_7_IN 0x0000
+#define P0MD_7_OUT 0x4000
+#define P0MD_7_TM6IOB 0x8000 /* timer 6 I/O mode B */
+
+#define P0IN __SYSREG(0xdb000004, u8) /* in reg */
+#define P0OUT __SYSREG(0xdb000008, u8) /* out reg */
+
+#define P0TMIO __SYSREG(0xdb00000c, u8) /* TM pin I/O control reg */
+#define P0TMIO_TM0_IN 0x00
+#define P0TMIO_TM0_OUT 0x01
+#define P0TMIO_TM1_IN 0x00
+#define P0TMIO_TM1_OUT 0x02
+#define P0TMIO_TM2_IN 0x00
+#define P0TMIO_TM2_OUT 0x04
+#define P0TMIO_TM3_IN 0x00
+#define P0TMIO_TM3_OUT 0x08
+#define P0TMIO_TM4_IN 0x00
+#define P0TMIO_TM4_OUT 0x10
+#define P0TMIO_TM5_IN 0x00
+#define P0TMIO_TM5_OUT 0x20
+#define P0TMIO_TM6A_IN 0x00
+#define P0TMIO_TM6A_OUT 0x40
+#define P0TMIO_TM6B_IN 0x00
+#define P0TMIO_TM6B_OUT 0x80
+
+/* I/O port 1 */
+#define P1MD __SYSREG(0xdb000100, u16) /* mode reg */
+#define P1MD_0 0x0003 /* mask */
+#define P1MD_0_IN 0x0000 /* input mode */
+#define P1MD_0_OUT 0x0001 /* output mode */
+#define P1MD_0_TM7IO 0x0002 /* timer 7 I/O mode */
+#define P1MD_0_ADTRG 0x0003 /* A/D converter trigger mode */
+#define P1MD_1 0x000c
+#define P1MD_1_IN 0x0000
+#define P1MD_1_OUT 0x0004
+#define P1MD_1_TM8IO 0x0008 /* timer 8 I/O mode */
+#define P1MD_1_XDMR0 0x000c /* DMA request input 0 mode */
+#define P1MD_2 0x0030
+#define P1MD_2_IN 0x0000
+#define P1MD_2_OUT 0x0010
+#define P1MD_2_TM9IO 0x0020 /* timer 9 I/O mode */
+#define P1MD_2_XDMR1 0x0030 /* DMA request input 1 mode */
+#define P1MD_3 0x00c0
+#define P1MD_3_IN 0x0000
+#define P1MD_3_OUT 0x0040
+#define P1MD_3_TM10IO 0x0080 /* timer 10 I/O mode */
+#define P1MD_3_FRQS0 0x00c0 /* CPU clock multiplier setting input 0 mode */
+#define P1MD_4 0x0300
+#define P1MD_4_IN 0x0000
+#define P1MD_4_OUT 0x0100
+#define P1MD_4_TM11IO 0x0200 /* timer 11 I/O mode */
+#define P1MD_4_FRQS1 0x0300 /* CPU clock multiplier setting input 1 mode */
+
+#define P1IN __SYSREG(0xdb000104, u8) /* in reg */
+#define P1OUT __SYSREG(0xdb000108, u8) /* out reg */
+#define P1TMIO __SYSREG(0xdb00010c, u8) /* TM pin I/O control reg */
+#define P1TMIO_TM11_IN 0x00
+#define P1TMIO_TM11_OUT 0x01
+#define P1TMIO_TM10_IN 0x00
+#define P1TMIO_TM10_OUT 0x02
+#define P1TMIO_TM9_IN 0x00
+#define P1TMIO_TM9_OUT 0x04
+#define P1TMIO_TM8_IN 0x00
+#define P1TMIO_TM8_OUT 0x08
+#define P1TMIO_TM7_IN 0x00
+#define P1TMIO_TM7_OUT 0x10
+
+/* I/O port 2 */
+#define P2MD __SYSREG(0xdb000200, u16) /* mode reg */
+#define P2MD_0 0x0003 /* mask */
+#define P2MD_0_IN 0x0000 /* input mode */
+#define P2MD_0_OUT 0x0001 /* output mode */
+#define P2MD_0_BOOTBW 0x0003 /* boot bus width selector mode */
+#define P2MD_1 0x000c
+#define P2MD_1_IN 0x0000
+#define P2MD_1_OUT 0x0004
+#define P2MD_1_BOOTSEL 0x000c /* boot device selector mode */
+#define P2MD_2 0x0030
+#define P2MD_2_IN 0x0000
+#define P2MD_2_OUT 0x0010
+#define P2MD_3 0x00c0
+#define P2MD_3_IN 0x0000
+#define P2MD_3_OUT 0x0040
+#define P2MD_3_CKIO 0x00c0 /* mode */
+#define P2MD_4 0x0300
+#define P2MD_4_IN 0x0000
+#define P2MD_4_OUT 0x0100
+#define P2MD_4_CMOD 0x0300 /* mode */
+
+#define P2IN __SYSREG(0xdb000204, u8) /* in reg */
+#define P2OUT __SYSREG(0xdb000208, u8) /* out reg */
+#define P2TMIO __SYSREG(0xdb00020c, u8) /* TM pin I/O control reg */
+
+/* I/O port 3 */
+#define P3MD __SYSREG(0xdb000300, u16) /* mode reg */
+#define P3MD_0 0x0003 /* mask */
+#define P3MD_0_IN 0x0000 /* input mode */
+#define P3MD_0_OUT 0x0001 /* output mode */
+#define P3MD_0_AFRXD 0x0002 /* AFR interface mode */
+#define P3MD_1 0x000c
+#define P3MD_1_IN 0x0000
+#define P3MD_1_OUT 0x0004
+#define P3MD_1_AFTXD 0x0008 /* AFR interface mode */
+#define P3MD_2 0x0030
+#define P3MD_2_IN 0x0000
+#define P3MD_2_OUT 0x0010
+#define P3MD_2_AFSCLK 0x0020 /* AFR interface mode */
+#define P3MD_3 0x00c0
+#define P3MD_3_IN 0x0000
+#define P3MD_3_OUT 0x0040
+#define P3MD_3_AFFS 0x0080 /* AFR interface mode */
+#define P3MD_4 0x0300
+#define P3MD_4_IN 0x0000
+#define P3MD_4_OUT 0x0100
+#define P3MD_4_AFEHC 0x0200 /* AFR interface mode */
+
+#define P3IN __SYSREG(0xdb000304, u8) /* in reg */
+#define P3OUT __SYSREG(0xdb000308, u8) /* out reg */
+
+/* I/O port 4 */
+#define P4MD __SYSREG(0xdb000400, u16) /* mode reg */
+#define P4MD_0 0x0003 /* mask */
+#define P4MD_0_IN 0x0000 /* input mode */
+#define P4MD_0_OUT 0x0001 /* output mode */
+#define P4MD_0_SCL0 0x0002 /* I2C/serial mode */
+#define P4MD_1 0x000c
+#define P4MD_1_IN 0x0000
+#define P4MD_1_OUT 0x0004
+#define P4MD_1_SDA0 0x0008
+#define P4MD_2 0x0030
+#define P4MD_2_IN 0x0000
+#define P4MD_2_OUT 0x0010
+#define P4MD_2_SCL1 0x0020
+#define P4MD_3 0x00c0
+#define P4MD_3_IN 0x0000
+#define P4MD_3_OUT 0x0040
+#define P4MD_3_SDA1 0x0080
+#define P4MD_4 0x0300
+#define P4MD_4_IN 0x0000
+#define P4MD_4_OUT 0x0100
+#define P4MD_4_SBO0 0x0200
+#define P4MD_5 0x0c00
+#define P4MD_5_IN 0x0000
+#define P4MD_5_OUT 0x0400
+#define P4MD_5_SBO1 0x0800
+#define P4MD_6 0x3000
+#define P4MD_6_IN 0x0000
+#define P4MD_6_OUT 0x1000
+#define P4MD_6_SBT0 0x2000
+#define P4MD_7 0xc000
+#define P4MD_7_IN 0x0000
+#define P4MD_7_OUT 0x4000
+#define P4MD_7_SBT1 0x8000
+
+#define P4IN __SYSREG(0xdb000404, u8) /* in reg */
+#define P4OUT __SYSREG(0xdb000408, u8) /* out reg */
+
+/* I/O port 5 */
+#define P5MD __SYSREG(0xdb000500, u16) /* mode reg */
+#define P5MD_0 0x0003 /* mask */
+#define P5MD_0_IN 0x0000 /* input mode */
+#define P5MD_0_OUT 0x0001 /* output mode */
+#define P5MD_0_IRTXD 0x0002 /* IrDA mode */
+#define P5MD_0_SOUT 0x0004 /* serial mode */
+#define P5MD_1 0x000c
+#define P5MD_1_IN 0x0000
+#define P5MD_1_OUT 0x0004
+#define P5MD_1_IRRXDS 0x0008 /* IrDA mode */
+#define P5MD_1_SIN 0x000c /* serial mode */
+#define P5MD_2 0x0030
+#define P5MD_2_IN 0x0000
+#define P5MD_2_OUT 0x0010
+#define P5MD_2_IRRXDF 0x0020 /* IrDA mode */
+
+#define P5IN __SYSREG(0xdb000504, u8) /* in reg */
+#define P5OUT __SYSREG(0xdb000508, u8) /* out reg */
+
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_PIO_REGS_H */
--- /dev/null
+#include <asm-generic/poll.h>
--- /dev/null
+/* MN10300 POSIX types
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_POSIX_TYPES_H
+#define _ASM_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc. Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned short __kernel_ipc_pid_t;
+typedef unsigned short __kernel_uid_t;
+typedef unsigned short __kernel_gid_t;
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_timer_t;
+typedef int __kernel_clockid_t;
+typedef int __kernel_daddr_t;
+typedef char * __kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+typedef unsigned short __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+ int val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+ int __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef __FD_SET
+static inline void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef __FD_CLR
+static inline void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+
+#undef __FD_ISSET
+static inline int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+ unsigned long __tmp = __fd / __NFDBITS;
+ unsigned long __rem = __fd % __NFDBITS;
+ return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static inline void __FD_ZERO(__kernel_fd_set *__p)
+{
+ unsigned long *__tmp = __p->fds_bits;
+ int __i;
+
+ if (__builtin_constant_p(__FDSET_LONGS)) {
+ switch (__FDSET_LONGS) {
+ case 16:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ __tmp[ 4] = 0; __tmp[ 5] = 0;
+ __tmp[ 6] = 0; __tmp[ 7] = 0;
+ __tmp[ 8] = 0; __tmp[ 9] = 0;
+ __tmp[10] = 0; __tmp[11] = 0;
+ __tmp[12] = 0; __tmp[13] = 0;
+ __tmp[14] = 0; __tmp[15] = 0;
+ return;
+
+ case 8:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ __tmp[ 4] = 0; __tmp[ 5] = 0;
+ __tmp[ 6] = 0; __tmp[ 7] = 0;
+ return;
+
+ case 4:
+ __tmp[ 0] = 0; __tmp[ 1] = 0;
+ __tmp[ 2] = 0; __tmp[ 3] = 0;
+ return;
+ }
+ }
+ __i = __FDSET_LONGS;
+ while (__i) {
+ __i--;
+ *__tmp = 0;
+ __tmp++;
+ }
+}
+
+#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif /* _ASM_POSIX_TYPES_H */
--- /dev/null
+/* MN103E010 Cache specification
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_PROC_CACHE_H
+#define _ASM_PROC_CACHE_H
+
+/* L1 cache */
+
+#define L1_CACHE_NWAYS 4 /* number of ways in caches */
+#define L1_CACHE_NENTRIES 256 /* number of entries in each way */
+#define L1_CACHE_BYTES 16 /* bytes per entry */
+#define L1_CACHE_SHIFT 4 /* shift for bytes per entry */
+#define L1_CACHE_WAYDISP 0x1000 /* displacement of one way from the next */
+
+#define L1_CACHE_TAG_VALID 0x00000001 /* cache tag valid bit */
+#define L1_CACHE_TAG_DIRTY 0x00000008 /* data cache tag dirty bit */
+#define L1_CACHE_TAG_ENTRY 0x00000ff0 /* cache tag entry address mask */
+#define L1_CACHE_TAG_ADDRESS 0xfffff000 /* cache tag line address mask */
+
+/*
+ * specification of the interval between interrupt checking intervals whilst
+ * managing the cache with the interrupts disabled
+ */
+#define MN10300_DCACHE_INV_RANGE_INTR_LOG2_INTERVAL 4
+
+#endif /* _ASM_PROC_CACHE_H */
--- /dev/null
+/* MN103E010-specific clocks
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_PROC_CLOCK_H
+#define _ASM_PROC_CLOCK_H
+
+#include <asm/unit/clock.h>
+
+#define MN10300_WDCLK MN10300_IOCLK
+
+#endif /* _ASM_PROC_CLOCK_H */
--- /dev/null
+/* MN103E010 On-board interrupt controller numbers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_PROC_IRQ_H
+#define _ASM_PROC_IRQ_H
+
+#ifdef __KERNEL__
+
+#define GxICR_NUM_IRQS 42
+
+#define GxICR_NUM_XIRQS 8
+
+#define XIRQ0 34
+#define XIRQ1 35
+#define XIRQ2 36
+#define XIRQ3 37
+#define XIRQ4 38
+#define XIRQ5 39
+#define XIRQ6 40
+#define XIRQ7 41
+
+#define XIRQ2IRQ(num) (XIRQ0 + num)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_PROC_IRQ_H */
--- /dev/null
+/* MN103E010 Processor description
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_PROC_PROC_H
+#define _ASM_PROC_PROC_H
+
+#define PROCESSOR_VENDOR_NAME "Matsushita"
+#define PROCESSOR_MODEL_NAME "mn103e010"
+
+#endif /* _ASM_PROC_PROC_H */
--- /dev/null
+/* MN10300 Processor specifics
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_PROCESSOR_H
+#define _ASM_PROCESSOR_H
+
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include <asm/cpu-regs.h>
+#include <linux/threads.h>
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+struct mm_struct;
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() \
+({ \
+ void *__pc; \
+ asm("mov pc,%0" : "=a"(__pc)); \
+ __pc; \
+})
+
+extern void show_registers(struct pt_regs *regs);
+
+/*
+ * CPU type and hardware bug flags. Kept separately for each CPU.
+ * Members of this structure are referenced in head.S, so think twice
+ * before touching them. [mj]
+ */
+
+struct mn10300_cpuinfo {
+ int type;
+ unsigned long loops_per_sec;
+ char hard_math;
+ unsigned long *pgd_quick;
+ unsigned long *pte_quick;
+ unsigned long pgtable_cache_sz;
+};
+
+extern struct mn10300_cpuinfo boot_cpu_data;
+
+#define cpu_data &boot_cpu_data
+#define current_cpu_data boot_cpu_data
+
+extern void identify_cpu(struct mn10300_cpuinfo *);
+extern void print_cpu_info(struct mn10300_cpuinfo *);
+extern void dodgy_tsc(void);
+#define cpu_relax() do {} while (0)
+
+/*
+ * User space process size: 1.75GB (default).
+ */
+#define TASK_SIZE 0x70000000
+
+/*
+ * Where to put the userspace stack by default
+ */
+#define STACK_TOP 0x70000000
+#define STACK_TOP_MAX STACK_TOP
+
+/* This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE 0x30000000
+
+typedef struct {
+ unsigned long seg;
+} mm_segment_t;
+
+struct fpu_state_struct {
+ unsigned long fs[32]; /* fpu registers */
+ unsigned long fpcr; /* fpu control register */
+};
+
+struct thread_struct {
+ struct pt_regs *uregs; /* userspace register frame */
+ unsigned long pc; /* kernel PC */
+ unsigned long sp; /* kernel SP */
+ unsigned long a3; /* kernel FP */
+ unsigned long wchan;
+ unsigned long usp;
+ struct pt_regs *__frame;
+ unsigned long fpu_flags;
+#define THREAD_USING_FPU 0x00000001 /* T if this task is using the FPU */
+ struct fpu_state_struct fpu_state;
+};
+
+#define INIT_THREAD \
+{ \
+ .uregs = init_uregs, \
+ .pc = 0, \
+ .sp = 0, \
+ .a3 = 0, \
+ .wchan = 0, \
+ .__frame = NULL, \
+}
+
+#define INIT_MMAP \
+{ &init_mm, 0, 0, NULL, PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, 1, \
+ NULL, NULL }
+
+/*
+ * do necessary setup to start up a newly executed thread
+ * - need to discard the frame stacked by the kernel thread invoking the execve
+ * syscall (see RESTORE_ALL macro)
+ */
+#define start_thread(regs, new_pc, new_sp) do { \
+ set_fs(USER_DS); \
+ __frame = current->thread.uregs; \
+ __frame->epsw = EPSW_nSL | EPSW_IE | EPSW_IM; \
+ __frame->pc = new_pc; \
+ __frame->sp = new_sp; \
+} while (0)
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+extern void prepare_to_copy(struct task_struct *tsk);
+
+/*
+ * create a kernel thread without removing it from tasklists
+ */
+extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+extern unsigned long thread_saved_pc(struct task_struct *tsk);
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define task_pt_regs(task) \
+({ \
+ struct pt_regs *__regs__; \
+ __regs__ = (struct pt_regs *) (KSTK_TOP(task_stack_page(task)) - 8); \
+ __regs__ - 1; \
+})
+
+#define KSTK_EIP(task) (task_pt_regs(task)->pc)
+#define KSTK_ESP(task) (task_pt_regs(task)->sp)
+
+#define KSTK_TOP(info) \
+({ \
+ (unsigned long)(info) + THREAD_SIZE; \
+})
+
+#define ARCH_HAS_PREFETCH
+#define ARCH_HAS_PREFETCHW
+
+static inline void prefetch(const void *x)
+{
+#ifndef CONFIG_MN10300_CACHE_DISABLED
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ asm volatile ("nop; nop; dcpf (%0)" : : "r"(x));
+#else
+ asm volatile ("dcpf (%0)" : : "r"(x));
+#endif
+#endif
+}
+
+static inline void prefetchw(const void *x)
+{
+#ifndef CONFIG_MN10300_CACHE_DISABLED
+#ifdef CONFIG_MN10300_PROC_MN103E010
+ asm volatile ("nop; nop; dcpf (%0)" : : "r"(x));
+#else
+ asm volatile ("dcpf (%0)" : : "r"(x));
+#endif
+#endif
+}
+
+#endif /* _ASM_PROCESSOR_H */
--- /dev/null
+/* MN10300 Exception frame layout and ptrace constants
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_PTRACE_H
+#define _ASM_PTRACE_H
+
+#define PT_A3 0
+#define PT_A2 1
+#define PT_D3 2
+#define PT_D2 3
+#define PT_MCVF 4
+#define PT_MCRL 5
+#define PT_MCRH 6
+#define PT_MDRQ 7
+#define PT_E1 8
+#define PT_E0 9
+#define PT_E7 10
+#define PT_E6 11
+#define PT_E5 12
+#define PT_E4 13
+#define PT_E3 14
+#define PT_E2 15
+#define PT_SP 16
+#define PT_LAR 17
+#define PT_LIR 18
+#define PT_MDR 19
+#define PT_A1 20
+#define PT_A0 21
+#define PT_D1 22
+#define PT_D0 23
+#define PT_ORIG_D0 24
+#define PT_EPSW 25
+#define PT_PC 26
+#define NR_PTREGS 27
+
+#ifndef __ASSEMBLY__
+/*
+ * This defines the way registers are stored in the event of an exception
+ * - the strange order is due to the MOVM instruction
+ */
+struct pt_regs {
+ unsigned long a3; /* syscall arg 3 */
+ unsigned long a2; /* syscall arg 4 */
+ unsigned long d3; /* syscall arg 5 */
+ unsigned long d2; /* syscall arg 6 */
+ unsigned long mcvf;
+ unsigned long mcrl;
+ unsigned long mcrh;
+ unsigned long mdrq;
+ unsigned long e1;
+ unsigned long e0;
+ unsigned long e7;
+ unsigned long e6;
+ unsigned long e5;
+ unsigned long e4;
+ unsigned long e3;
+ unsigned long e2;
+ unsigned long sp;
+ unsigned long lar;
+ unsigned long lir;
+ unsigned long mdr;
+ unsigned long a1;
+ unsigned long a0; /* syscall arg 1 */
+ unsigned long d1; /* syscall arg 2 */
+ unsigned long d0; /* syscall ret */
+ struct pt_regs *next; /* next frame pointer */
+ unsigned long orig_d0; /* syscall number */
+ unsigned long epsw;
+ unsigned long pc;
+};
+#endif
+
+extern struct pt_regs *__frame; /* current frame pointer */
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS 12
+#define PTRACE_SETREGS 13
+#define PTRACE_GETFPREGS 14
+#define PTRACE_SETFPREGS 15
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD 0x00000001
+
+#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+#define user_mode(regs) (((regs)->epsw & EPSW_nSL) == EPSW_nSL)
+#define instruction_pointer(regs) ((regs)->pc)
+extern void show_regs(struct pt_regs *);
+#endif
+
+#define profile_pc(regs) ((regs)->pc)
+
+#endif /* _ASM_PTRACE_H */
--- /dev/null
+/* MN10300 Reset controller and watchdog timer definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_RESET_REGS_H
+#define _ASM_RESET_REGS_H
+
+#include <asm/cpu-regs.h>
+#include <asm/exceptions.h>
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_MN10300_WD_TIMER
+#define ARCH_HAS_NMI_WATCHDOG /* See include/linux/nmi.h */
+#endif
+
+/*
+ * watchdog timer registers
+ */
+#define WDBC __SYSREGC(0xc0001000, u8) /* watchdog binary counter reg */
+
+#define WDCTR __SYSREG(0xc0001002, u8) /* watchdog timer control reg */
+#define WDCTR_WDCK 0x07 /* clock source selection */
+#define WDCTR_WDCK_256th 0x00 /* - OSCI/256 */
+#define WDCTR_WDCK_1024th 0x01 /* - OSCI/1024 */
+#define WDCTR_WDCK_2048th 0x02 /* - OSCI/2048 */
+#define WDCTR_WDCK_16384th 0x03 /* - OSCI/16384 */
+#define WDCTR_WDCK_65536th 0x04 /* - OSCI/65536 */
+#define WDCTR_WDRST 0x40 /* binary counter reset */
+#define WDCTR_WDCNE 0x80 /* watchdog timer enable */
+
+#define RSTCTR __SYSREG(0xc0001004, u8) /* reset control reg */
+#define RSTCTR_CHIPRST 0x01 /* chip reset */
+#define RSTCTR_DBFRST 0x02 /* double fault reset flag */
+#define RSTCTR_WDTRST 0x04 /* watchdog timer reset flag */
+#define RSTCTR_WDREN 0x08 /* watchdog timer reset enable */
+
+#ifndef __ASSEMBLY__
+
+static inline void mn10300_proc_hard_reset(void)
+{
+ RSTCTR &= ~RSTCTR_CHIPRST;
+ RSTCTR |= RSTCTR_CHIPRST;
+}
+
+extern unsigned int watchdog_alert_counter;
+
+extern void watchdog_go(void);
+extern asmlinkage void watchdog_handler(void);
+extern asmlinkage
+void watchdog_interrupt(struct pt_regs *, enum exception_code);
+
+#endif
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_RESET_REGS_H */
--- /dev/null
+#include <asm-generic/resource.h>
--- /dev/null
+/* MN10300 on-chip Real-Time Clock registers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_RTC_REGS_H
+#define _ASM_RTC_REGS_H
+
+#include <asm/intctl-regs.h>
+
+#ifdef __KERNEL__
+
+#define RTSCR __SYSREG(0xd8600000, u8) /* RTC seconds count reg */
+#define RTSAR __SYSREG(0xd8600001, u8) /* RTC seconds alarm reg */
+#define RTMCR __SYSREG(0xd8600002, u8) /* RTC minutes count reg */
+#define RTMAR __SYSREG(0xd8600003, u8) /* RTC minutes alarm reg */
+#define RTHCR __SYSREG(0xd8600004, u8) /* RTC hours count reg */
+#define RTHAR __SYSREG(0xd8600005, u8) /* RTC hours alarm reg */
+#define RTDWCR __SYSREG(0xd8600006, u8) /* RTC day of the week count reg */
+#define RTDMCR __SYSREG(0xd8600007, u8) /* RTC days count reg */
+#define RTMTCR __SYSREG(0xd8600008, u8) /* RTC months count reg */
+#define RTYCR __SYSREG(0xd8600009, u8) /* RTC years count reg */
+
+#define RTCRA __SYSREG(0xd860000a, u8)/* RTC control reg A */
+#define RTCRA_RS 0x0f /* periodic timer interrupt cycle setting */
+#define RTCRA_RS_NONE 0x00 /* - off */
+#define RTCRA_RS_3_90625ms 0x01 /* - 3.90625ms (1/256s) */
+#define RTCRA_RS_7_8125ms 0x02 /* - 7.8125ms (1/128s) */
+#define RTCRA_RS_122_070us 0x03 /* - 122.070us (1/8192s) */
+#define RTCRA_RS_244_141us 0x04 /* - 244.141us (1/4096s) */
+#define RTCRA_RS_488_281us 0x05 /* - 488.281us (1/2048s) */
+#define RTCRA_RS_976_5625us 0x06 /* - 976.5625us (1/1024s) */
+#define RTCRA_RS_1_953125ms 0x07 /* - 1.953125ms (1/512s) */
+#define RTCRA_RS_3_90624ms 0x08 /* - 3.90624ms (1/256s) */
+#define RTCRA_RS_7_8125ms_b 0x09 /* - 7.8125ms (1/128s) */
+#define RTCRA_RS_15_625ms 0x0a /* - 15.625ms (1/64s) */
+#define RTCRA_RS_31_25ms 0x0b /* - 31.25ms (1/32s) */
+#define RTCRA_RS_62_5ms 0x0c /* - 62.5ms (1/16s) */
+#define RTCRA_RS_125ms 0x0d /* - 125ms (1/8s) */
+#define RTCRA_RS_250ms 0x0e /* - 250ms (1/4s) */
+#define RTCRA_RS_500ms 0x0f /* - 500ms (1/2s) */
+#define RTCRA_DVR 0x40 /* divider reset */
+#define RTCRA_UIP 0x80 /* clock update flag */
+
+#define RTCRB __SYSREG(0xd860000b, u8) /* RTC control reg B */
+#define RTCRB_DSE 0x01 /* daylight savings time enable */
+#define RTCRB_TM 0x02 /* time format */
+#define RTCRB_TM_12HR 0x00 /* - 12 hour format */
+#define RTCRB_TM_24HR 0x02 /* - 24 hour format */
+#define RTCRB_DM 0x04 /* numeric value format */
+#define RTCRB_DM_BCD 0x00 /* - BCD */
+#define RTCRB_DM_BINARY 0x04 /* - binary */
+#define RTCRB_UIE 0x10 /* update interrupt disable */
+#define RTCRB_AIE 0x20 /* alarm interrupt disable */
+#define RTCRB_PIE 0x40 /* periodic interrupt disable */
+#define RTCRB_SET 0x80 /* clock update enable */
+
+#define RTSRC __SYSREG(0xd860000c, u8) /* RTC status reg C */
+#define RTSRC_UF 0x10 /* update end interrupt flag */
+#define RTSRC_AF 0x20 /* alarm interrupt flag */
+#define RTSRC_PF 0x40 /* periodic interrupt flag */
+#define RTSRC_IRQF 0x80 /* interrupt flag */
+
+#define RTIRQ 32
+#define RTICR GxICR(RTIRQ)
+
+/*
+ * MC146818 RTC compatibility defs for the MN10300 on-chip RTC
+ */
+#define RTC_PORT(x) 0xd8600000
+#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
+
+#define CMOS_READ(addr) __SYSREG(0xd8600000 + (addr), u8)
+#define CMOS_WRITE(val, addr) \
+ do { __SYSREG(0xd8600000 + (addr), u8) = val; } while (0)
+
+#define RTC_IRQ RTIRQ
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_RTC_REGS_H */
--- /dev/null
+/* MN10300 Real time clock definitions
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_RTC_H
+#define _ASM_RTC_H
+
+#ifdef CONFIG_MN10300_RTC
+
+#include <linux/init.h>
+
+extern void check_rtc_time(void);
+extern void __init calibrate_clock(void);
+extern unsigned long __init get_initial_rtc_time(void);
+
+#else /* !CONFIG_MN10300_RTC */
+
+static inline void check_rtc_time(void)
+{
+}
+
+static inline void calibrate_clock(void)
+{
+}
+
+static inline unsigned long get_initial_rtc_time(void)
+{
+ return 0;
+}
+
+#endif /* !CONFIG_MN10300_RTC */
+
+#include <asm-generic/rtc.h>
+
+#endif /* _ASM_RTC_H */
--- /dev/null
+/* MN10300 Scatterlist definitions
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_SCATTERLIST_H
+#define _ASM_SCATTERLIST_H
+
+#include <asm/types.h>
+
+/*
+ * Drivers must set either ->address or (preferred) page and ->offset
+ * to indicate where data must be transferred to/from.
+ *
+ * Using page is recommended since it handles highmem data as well as
+ * low mem. ->address is restricted to data which has a virtual mapping, and
+ * it will go away in the future. Updating to page can be automated very
+ * easily -- something like
+ *
+ * sg->address = some_ptr;
+ *
+ * can be rewritten as
+ *
+ * sg_set_page(virt_to_page(some_ptr));
+ * sg->offset = (unsigned long) some_ptr & ~PAGE_MASK;
+ *
+ * and that's it. There's no excuse for not highmem enabling YOUR driver. /jens
+ */
+struct scatterlist {
+#ifdef CONFIG_DEBUG_SG
+ unsigned long sg_magic;
+#endif
+ unsigned long page_link;
+ unsigned int offset; /* for highmem, page offset */
+ dma_addr_t dma_address;
+ unsigned int length;
+};
+
+#define ISA_DMA_THRESHOLD (0x00ffffff)
+
+#endif /* _ASM_SCATTERLIST_H */
--- /dev/null
+#include <asm-generic/sections.h>
--- /dev/null
+/* MN10300 Semaphores
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_SEMAPHORE_H
+#define _ASM_SEMAPHORE_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/linkage.h>
+#include <linux/wait.h>
+#include <linux/spinlock.h>
+#include <linux/rwsem.h>
+
+#define SEMAPHORE_DEBUG 0
+
+/*
+ * the semaphore definition
+ * - if count is >0 then there are tokens available on the semaphore for down
+ * to collect
+ * - if count is <=0 then there are no spare tokens, and anyone that wants one
+ * must wait
+ * - if wait_list is not empty, then there are processes waiting for the
+ * semaphore
+ */
+struct semaphore {
+ atomic_t count; /* it's not really atomic, it's
+ * just that certain modules
+ * expect to be able to access
+ * it directly */
+ spinlock_t wait_lock;
+ struct list_head wait_list;
+#if SEMAPHORE_DEBUG
+ unsigned __magic;
+#endif
+};
+
+#if SEMAPHORE_DEBUG
+# define __SEM_DEBUG_INIT(name) , (long)&(name).__magic
+#else
+# define __SEM_DEBUG_INIT(name)
+#endif
+
+
+#define __SEMAPHORE_INITIALIZER(name, init_count) \
+{ \
+ .count = ATOMIC_INIT(init_count), \
+ .wait_lock = __SPIN_LOCK_UNLOCKED((name).wait_lock), \
+ .wait_list = LIST_HEAD_INIT((name).wait_list) \
+ __SEM_DEBUG_INIT(name) \
+}
+
+#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
+ struct semaphore name = __SEMAPHORE_INITIALIZER(name, count)
+
+#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1)
+#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0)
+
+static inline void sema_init(struct semaphore *sem, int val)
+{
+ *sem = (struct semaphore) __SEMAPHORE_INITIALIZER(*sem, val);
+}
+
+static inline void init_MUTEX(struct semaphore *sem)
+{
+ sema_init(sem, 1);
+}
+
+static inline void init_MUTEX_LOCKED(struct semaphore *sem)
+{
+ sema_init(sem, 0);
+}
+
+extern void __down(struct semaphore *sem, unsigned long flags);
+extern int __down_interruptible(struct semaphore *sem, unsigned long flags);
+extern void __up(struct semaphore *sem);
+
+static inline void down(struct semaphore *sem)
+{
+ unsigned long flags;
+ int count;
+
+#if SEMAPHORE_DEBUG
+ CHECK_MAGIC(sem->__magic);
+#endif
+
+ spin_lock_irqsave(&sem->wait_lock, flags);
+ count = atomic_read(&sem->count);
+ if (likely(count > 0)) {
+ atomic_set(&sem->count, count - 1);
+ spin_unlock_irqrestore(&sem->wait_lock, flags);
+ } else {
+ __down(sem, flags);
+ }
+}
+
+static inline int down_interruptible(struct semaphore *sem)
+{
+ unsigned long flags;
+ int count, ret = 0;
+
+#if SEMAPHORE_DEBUG
+ CHECK_MAGIC(sem->__magic);
+#endif
+
+ spin_lock_irqsave(&sem->wait_lock, flags);
+ count = atomic_read(&sem->count);
+ if (likely(count > 0)) {
+ atomic_set(&sem->count, count - 1);
+ spin_unlock_irqrestore(&sem->wait_lock, flags);
+ } else {
+ ret = __down_interruptible(sem, flags);
+ }
+ return ret;
+}
+
+/*
+ * non-blockingly attempt to down() a semaphore.
+ * - returns zero if we acquired it
+ */
+static inline int down_trylock(struct semaphore *sem)
+{
+ unsigned long flags;
+ int count, success = 0;
+
+#if SEMAPHORE_DEBUG
+ CHECK_MAGIC(sem->__magic);
+#endif
+
+ spin_lock_irqsave(&sem->wait_lock, flags);
+ count = atomic_read(&sem->count);
+ if (likely(count > 0)) {
+ atomic_set(&sem->count, count - 1);
+ success = 1;
+ }
+ spin_unlock_irqrestore(&sem->wait_lock, flags);
+ return !success;
+}
+
+static inline void up(struct semaphore *sem)
+{
+ unsigned long flags;
+
+#if SEMAPHORE_DEBUG
+ CHECK_MAGIC(sem->__magic);
+#endif
+
+ spin_lock_irqsave(&sem->wait_lock, flags);
+ if (!list_empty(&sem->wait_list))
+ __up(sem);
+ else
+ atomic_set(&sem->count, atomic_read(&sem->count) + 1);
+ spin_unlock_irqrestore(&sem->wait_lock, flags);
+}
+
+static inline int sem_getcount(struct semaphore *sem)
+{
+ return atomic_read(&sem->count);
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+#ifndef _ASM_SEMBUF_H
+#define _ASM_SEMBUF_H
+
+/*
+ * The semid64_ds structure for MN10300 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct semid64_ds {
+ struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
+ __kernel_time_t sem_otime; /* last semop time */
+ unsigned long __unused1;
+ __kernel_time_t sem_ctime; /* last change time */
+ unsigned long __unused2;
+ unsigned long sem_nsems; /* no. of semaphores in array */
+ unsigned long __unused3;
+ unsigned long __unused4;
+};
+
+#endif /* _ASM_SEMBUF_H */
--- /dev/null
+/* MN10300 on-board serial port module registers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_SERIAL_REGS_H
+#define _ASM_SERIAL_REGS_H
+
+#include <asm/cpu-regs.h>
+#include <asm/intctl-regs.h>
+
+#ifdef __KERNEL__
+
+/* serial port 0 */
+#define SC0CTR __SYSREG(0xd4002000, u16) /* control reg */
+#define SC01CTR_CK 0x0007 /* clock source select */
+#define SC0CTR_CK_TM8UFLOW_8 0x0000 /* - 1/8 timer 8 underflow (serial port 0 only) */
+#define SC1CTR_CK_TM9UFLOW_8 0x0000 /* - 1/8 timer 9 underflow (serial port 1 only) */
+#define SC01CTR_CK_IOCLK_8 0x0001 /* - 1/8 IOCLK */
+#define SC01CTR_CK_IOCLK_32 0x0002 /* - 1/32 IOCLK */
+#define SC0CTR_CK_TM2UFLOW_2 0x0003 /* - 1/2 timer 2 underflow (serial port 0 only) */
+#define SC1CTR_CK_TM3UFLOW_2 0x0003 /* - 1/2 timer 3 underflow (serial port 1 only) */
+#define SC0CTR_CK_TM0UFLOW_8 0x0004 /* - 1/8 timer 1 underflow (serial port 0 only) */
+#define SC1CTR_CK_TM1UFLOW_8 0x0004 /* - 1/8 timer 2 underflow (serial port 1 only) */
+#define SC0CTR_CK_TM2UFLOW_8 0x0005 /* - 1/8 timer 2 underflow (serial port 0 only) */
+#define SC1CTR_CK_TM3UFLOW_8 0x0005 /* - 1/8 timer 3 underflow (serial port 1 only) */
+#define SC01CTR_CK_EXTERN_8 0x0006 /* - 1/8 external closk */
+#define SC01CTR_CK_EXTERN 0x0007 /* - external closk */
+#define SC01CTR_STB 0x0008 /* stop bit select */
+#define SC01CTR_STB_1BIT 0x0000 /* - 1 stop bit */
+#define SC01CTR_STB_2BIT 0x0008 /* - 2 stop bits */
+#define SC01CTR_PB 0x0070 /* parity bit select */
+#define SC01CTR_PB_NONE 0x0000 /* - no parity */
+#define SC01CTR_PB_FIXED0 0x0040 /* - fixed at 0 */
+#define SC01CTR_PB_FIXED1 0x0050 /* - fixed at 1 */
+#define SC01CTR_PB_EVEN 0x0060 /* - even parity */
+#define SC01CTR_PB_ODD 0x0070 /* - odd parity */
+#define SC01CTR_CLN 0x0080 /* character length */
+#define SC01CTR_CLN_7BIT 0x0000 /* - 7 bit chars */
+#define SC01CTR_CLN_8BIT 0x0080 /* - 8 bit chars */
+#define SC01CTR_TOE 0x0100 /* T input output enable */
+#define SC01CTR_OD 0x0200 /* bit order select */
+#define SC01CTR_OD_LSBFIRST 0x0000 /* - LSB first */
+#define SC01CTR_OD_MSBFIRST 0x0200 /* - MSB first */
+#define SC01CTR_MD 0x0c00 /* mode select */
+#define SC01CTR_MD_STST_SYNC 0x0000 /* - start-stop synchronous */
+#define SC01CTR_MD_CLOCK_SYNC1 0x0400 /* - clock synchronous 1 */
+#define SC01CTR_MD_I2C 0x0800 /* - I2C mode */
+#define SC01CTR_MD_CLOCK_SYNC2 0x0c00 /* - clock synchronous 2 */
+#define SC01CTR_IIC 0x1000 /* I2C mode select */
+#define SC01CTR_BKE 0x2000 /* break transmit enable */
+#define SC01CTR_RXE 0x4000 /* receive enable */
+#define SC01CTR_TXE 0x8000 /* transmit enable */
+
+#define SC0ICR __SYSREG(0xd4002004, u8) /* interrupt control reg */
+#define SC01ICR_DMD 0x80 /* output data mode */
+#define SC01ICR_TD 0x20 /* transmit DMA trigger cause */
+#define SC01ICR_TI 0x10 /* transmit interrupt cause */
+#define SC01ICR_RES 0x04 /* receive error select */
+#define SC01ICR_RI 0x01 /* receive interrupt cause */
+
+#define SC0TXB __SYSREG(0xd4002008, u8) /* transmit buffer reg */
+#define SC0RXB __SYSREG(0xd4002009, u8) /* receive buffer reg */
+
+#define SC0STR __SYSREG(0xd400200c, u16) /* status reg */
+#define SC01STR_OEF 0x0001 /* overrun error found */
+#define SC01STR_PEF 0x0002 /* parity error found */
+#define SC01STR_FEF 0x0004 /* framing error found */
+#define SC01STR_RBF 0x0010 /* receive buffer status */
+#define SC01STR_TBF 0x0020 /* transmit buffer status */
+#define SC01STR_RXF 0x0040 /* receive status */
+#define SC01STR_TXF 0x0080 /* transmit status */
+#define SC01STR_STF 0x0100 /* I2C start sequence found */
+#define SC01STR_SPF 0x0200 /* I2C stop sequence found */
+
+#define SC0RXIRQ 20 /* timer 0 Receive IRQ */
+#define SC0TXIRQ 21 /* timer 0 Transmit IRQ */
+
+#define SC0RXICR GxICR(SC0RXIRQ) /* serial 0 receive intr ctrl reg */
+#define SC0TXICR GxICR(SC0TXIRQ) /* serial 0 transmit intr ctrl reg */
+
+/* serial port 1 */
+#define SC1CTR __SYSREG(0xd4002010, u16) /* serial port 1 control */
+#define SC1ICR __SYSREG(0xd4002014, u8) /* interrupt control reg */
+#define SC1TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
+#define SC1RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
+#define SC1STR __SYSREG(0xd400201c, u16) /* status reg */
+
+#define SC1RXIRQ 22 /* timer 1 Receive IRQ */
+#define SC1TXIRQ 23 /* timer 1 Transmit IRQ */
+
+#define SC1RXICR GxICR(SC1RXIRQ) /* serial 1 receive intr ctrl reg */
+#define SC1TXICR GxICR(SC1TXIRQ) /* serial 1 transmit intr ctrl reg */
+
+/* serial port 2 */
+#define SC2CTR __SYSREG(0xd4002020, u16) /* control reg */
+#define SC2CTR_CK 0x0003 /* clock source select */
+#define SC2CTR_CK_TM10UFLOW 0x0000 /* - timer 10 underflow */
+#define SC2CTR_CK_TM2UFLOW 0x0001 /* - timer 2 underflow */
+#define SC2CTR_CK_EXTERN 0x0002 /* - external closk */
+#define SC2CTR_CK_TM3UFLOW 0x0003 /* - timer 3 underflow */
+#define SC2CTR_STB 0x0008 /* stop bit select */
+#define SC2CTR_STB_1BIT 0x0000 /* - 1 stop bit */
+#define SC2CTR_STB_2BIT 0x0008 /* - 2 stop bits */
+#define SC2CTR_PB 0x0070 /* parity bit select */
+#define SC2CTR_PB_NONE 0x0000 /* - no parity */
+#define SC2CTR_PB_FIXED0 0x0040 /* - fixed at 0 */
+#define SC2CTR_PB_FIXED1 0x0050 /* - fixed at 1 */
+#define SC2CTR_PB_EVEN 0x0060 /* - even parity */
+#define SC2CTR_PB_ODD 0x0070 /* - odd parity */
+#define SC2CTR_CLN 0x0080 /* character length */
+#define SC2CTR_CLN_7BIT 0x0000 /* - 7 bit chars */
+#define SC2CTR_CLN_8BIT 0x0080 /* - 8 bit chars */
+#define SC2CTR_TWE 0x0100 /* transmit wait enable (enable XCTS control) */
+#define SC2CTR_OD 0x0200 /* bit order select */
+#define SC2CTR_OD_LSBFIRST 0x0000 /* - LSB first */
+#define SC2CTR_OD_MSBFIRST 0x0200 /* - MSB first */
+#define SC2CTR_TWS 0x1000 /* transmit wait select */
+#define SC2CTR_TWS_XCTS_HIGH 0x0000 /* - interrupt TX when XCTS high */
+#define SC2CTR_TWS_XCTS_LOW 0x1000 /* - interrupt TX when XCTS low */
+#define SC2CTR_BKE 0x2000 /* break transmit enable */
+#define SC2CTR_RXE 0x4000 /* receive enable */
+#define SC2CTR_TXE 0x8000 /* transmit enable */
+
+#define SC2ICR __SYSREG(0xd4002024, u8) /* interrupt control reg */
+#define SC2ICR_TD 0x20 /* transmit DMA trigger cause */
+#define SC2ICR_TI 0x10 /* transmit interrupt cause */
+#define SC2ICR_RES 0x04 /* receive error select */
+#define SC2ICR_RI 0x01 /* receive interrupt cause */
+
+#define SC2TXB __SYSREG(0xd4002018, u8) /* transmit buffer reg */
+#define SC2RXB __SYSREG(0xd4002019, u8) /* receive buffer reg */
+#define SC2STR __SYSREG(0xd400201c, u8) /* status reg */
+#define SC2STR_OEF 0x0001 /* overrun error found */
+#define SC2STR_PEF 0x0002 /* parity error found */
+#define SC2STR_FEF 0x0004 /* framing error found */
+#define SC2STR_CTS 0x0008 /* XCTS input pin status (0 means high) */
+#define SC2STR_RBF 0x0010 /* receive buffer status */
+#define SC2STR_TBF 0x0020 /* transmit buffer status */
+#define SC2STR_RXF 0x0040 /* receive status */
+#define SC2STR_TXF 0x0080 /* transmit status */
+
+#define SC2TIM __SYSREG(0xd400202d, u8) /* status reg */
+
+#define SC2RXIRQ 24 /* serial 2 Receive IRQ */
+#define SC2TXIRQ 25 /* serial 2 Transmit IRQ */
+
+#define SC2RXICR GxICR(SC2RXIRQ) /* serial 2 receive intr ctrl reg */
+#define SC2TXICR GxICR(SC2TXIRQ) /* serial 2 transmit intr ctrl reg */
+
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_SERIAL_REGS_H */
--- /dev/null
+/* Standard UART definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+/*
+ * The ASB2305 has an 18.432 MHz clock the UART
+ */
+#define BASE_BAUD (18432000 / 16)
+
+/* Standard COM flags (except for COM4, because of the 8514 problem) */
+#ifdef CONFIG_SERIAL_DETECT_IRQ
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
+#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
+#else
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
+#endif
+
+#ifdef CONFIG_SERIAL_MANY_PORTS
+#define FOURPORT_FLAGS ASYNC_FOURPORT
+#define ACCENT_FLAGS 0
+#define BOCA_FLAGS 0
+#define HUB6_FLAGS 0
+#define RS_TABLE_SIZE 64
+#else
+#define RS_TABLE_SIZE
+#endif
+
+#include <asm/unit/serial.h>
--- /dev/null
+/* MN10300 Setup declarations
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_SETUP_H
+#define _ASM_SETUP_H
+
+extern void __init unit_setup(void);
+extern void __init unit_init_IRQ(void);
+
+#endif /* _ASM_SETUP_H */
--- /dev/null
+#ifndef _ASM_SHMBUF_H
+#define _ASM_SHMBUF_H
+
+/*
+ * The shmid64_ds structure for MN10300 architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct shmid64_ds {
+ struct ipc64_perm shm_perm; /* operation perms */
+ size_t shm_segsz; /* size of segment (bytes) */
+ __kernel_time_t shm_atime; /* last attach time */
+ unsigned long __unused1;
+ __kernel_time_t shm_dtime; /* last detach time */
+ unsigned long __unused2;
+ __kernel_time_t shm_ctime; /* last change time */
+ unsigned long __unused3;
+ __kernel_pid_t shm_cpid; /* pid of creator */
+ __kernel_pid_t shm_lpid; /* pid of last operator */
+ unsigned long shm_nattch; /* no. of current attaches */
+ unsigned long __unused4;
+ unsigned long __unused5;
+};
+
+struct shminfo64 {
+ unsigned long shmmax;
+ unsigned long shmmin;
+ unsigned long shmmni;
+ unsigned long shmseg;
+ unsigned long shmall;
+ unsigned long __unused1;
+ unsigned long __unused2;
+ unsigned long __unused3;
+ unsigned long __unused4;
+};
+
+#endif /* _ASM_SHMBUF_H */
--- /dev/null
+#ifndef _ASM_SHMPARAM_H
+#define _ASM_SHMPARAM_H
+
+#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
+
+#endif /* _ASM_SHMPARAM_H */
--- /dev/null
+/* MN10300 Userspace signal context
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_SIGCONTEXT_H
+#define _ASM_SIGCONTEXT_H
+
+struct fpucontext {
+ /* Regular FPU environment */
+ unsigned long fs[32]; /* fpu registers */
+ unsigned long fpcr; /* fpu control register */
+};
+
+struct sigcontext {
+ unsigned long d0;
+ unsigned long d1;
+ unsigned long d2;
+ unsigned long d3;
+ unsigned long a0;
+ unsigned long a1;
+ unsigned long a2;
+ unsigned long a3;
+ unsigned long e0;
+ unsigned long e1;
+ unsigned long e2;
+ unsigned long e3;
+ unsigned long e4;
+ unsigned long e5;
+ unsigned long e6;
+ unsigned long e7;
+ unsigned long lar;
+ unsigned long lir;
+ unsigned long mdr;
+ unsigned long mcvf;
+ unsigned long mcrl;
+ unsigned long mcrh;
+ unsigned long mdrq;
+ unsigned long sp;
+ unsigned long epsw;
+ unsigned long pc;
+ struct fpucontext *fpucontext;
+ unsigned long oldmask;
+};
+
+
+#endif /* _ASM_SIGCONTEXT_H */
--- /dev/null
+#include <asm-generic/siginfo.h>
--- /dev/null
+/* MN10300 Signal definitions
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_SIGNAL_H
+#define _ASM_SIGNAL_H
+
+#include <linux/types.h>
+
+/* Avoid too many header ordering problems. */
+struct siginfo;
+
+#ifdef __KERNEL__
+/* Most things should be clean enough to redefine this at will, if care
+ is taken to make libc match. */
+
+#define _NSIG 64
+#define _NSIG_BPW 32
+#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t; /* at least 32 bits */
+
+typedef struct {
+ unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#else
+/* Here we must cater to libcs that poke about in kernel headers. */
+
+#define NSIG 32
+typedef unsigned long sigset_t;
+
+#endif /* __KERNEL__ */
+
+#define SIGHUP 1
+#define SIGINT 2
+#define SIGQUIT 3
+#define SIGILL 4
+#define SIGTRAP 5
+#define SIGABRT 6
+#define SIGIOT 6
+#define SIGBUS 7
+#define SIGFPE 8
+#define SIGKILL 9
+#define SIGUSR1 10
+#define SIGSEGV 11
+#define SIGUSR2 12
+#define SIGPIPE 13
+#define SIGALRM 14
+#define SIGTERM 15
+#define SIGSTKFLT 16
+#define SIGCHLD 17
+#define SIGCONT 18
+#define SIGSTOP 19
+#define SIGTSTP 20
+#define SIGTTIN 21
+#define SIGTTOU 22
+#define SIGURG 23
+#define SIGXCPU 24
+#define SIGXFSZ 25
+#define SIGVTALRM 26
+#define SIGPROF 27
+#define SIGWINCH 28
+#define SIGIO 29
+#define SIGPOLL SIGIO
+/*
+#define SIGLOST 29
+*/
+#define SIGPWR 30
+#define SIGSYS 31
+#define SIGUNUSED 31
+
+/* These should not be considered constants from userland. */
+#define SIGRTMIN 32
+#define SIGRTMAX (_NSIG-1)
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP 0x00000001U
+#define SA_NOCLDWAIT 0x00000002U
+#define SA_SIGINFO 0x00000004U
+#define SA_ONSTACK 0x08000000U
+#define SA_RESTART 0x10000000U
+#define SA_NODEFER 0x40000000U
+#define SA_RESETHAND 0x80000000U
+
+#define SA_NOMASK SA_NODEFER
+#define SA_ONESHOT SA_RESETHAND
+
+#define SA_RESTORER 0x04000000
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK 1
+#define SS_DISABLE 2
+
+#define MINSIGSTKSZ 2048
+#define SIGSTKSZ 8192
+
+#include <asm-generic/signal.h>
+
+#ifdef __KERNEL__
+struct old_sigaction {
+ __sighandler_t sa_handler;
+ old_sigset_t sa_mask;
+ unsigned long sa_flags;
+ __sigrestore_t sa_restorer;
+};
+
+struct sigaction {
+ __sighandler_t sa_handler;
+ unsigned long sa_flags;
+ __sigrestore_t sa_restorer;
+ sigset_t sa_mask; /* mask last for extensibility */
+};
+
+struct k_sigaction {
+ struct sigaction sa;
+};
+#else
+/* Here we must cater to libcs that poke about in kernel headers. */
+
+struct sigaction {
+ union {
+ __sighandler_t _sa_handler;
+ void (*_sa_sigaction)(int, struct siginfo *, void *);
+ } _u;
+ sigset_t sa_mask;
+ unsigned long sa_flags;
+ void (*sa_restorer)(void);
+};
+
+#define sa_handler _u._sa_handler
+#define sa_sigaction _u._sa_sigaction
+
+#endif /* __KERNEL__ */
+
+typedef struct sigaltstack {
+ void __user *ss_sp;
+ int ss_flags;
+ size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+
+
+struct pt_regs;
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_SIGNAL_H */
--- /dev/null
+/* MN10300 SMP support
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_SMP_H
+#define _ASM_SMP_H
+
+#ifdef CONFIG_SMP
+#error SMP not yet supported for MN10300
+#endif
+
+#endif
--- /dev/null
+#ifndef _ASM_SOCKET_H
+#define _ASM_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockopt(2) */
+#define SOL_SOCKET 1
+
+#define SO_DEBUG 1
+#define SO_REUSEADDR 2
+#define SO_TYPE 3
+#define SO_ERROR 4
+#define SO_DONTROUTE 5
+#define SO_BROADCAST 6
+#define SO_SNDBUF 7
+#define SO_RCVBUF 8
+#define SO_SNDBUFFORCE 32
+#define SO_RCVBUFFORCE 33
+#define SO_KEEPALIVE 9
+#define SO_OOBINLINE 10
+#define SO_NO_CHECK 11
+#define SO_PRIORITY 12
+#define SO_LINGER 13
+#define SO_BSDCOMPAT 14
+/* To add :#define SO_REUSEPORT 15 */
+#define SO_PASSCRED 16
+#define SO_PEERCRED 17
+#define SO_RCVLOWAT 18
+#define SO_SNDLOWAT 19
+#define SO_RCVTIMEO 20
+#define SO_SNDTIMEO 21
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION 22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT 23
+#define SO_SECURITY_ENCRYPTION_NETWORK 24
+
+#define SO_BINDTODEVICE 25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER 26
+#define SO_DETACH_FILTER 27
+
+#define SO_PEERNAME 28
+#define SO_TIMESTAMP 29
+#define SCM_TIMESTAMP SO_TIMESTAMP
+
+#define SO_ACCEPTCONN 30
+
+#define SO_PEERSEC 31
+#define SO_PASSSEC 34
+#define SO_TIMESTAMPNS 35
+#define SCM_TIMESTAMPNS SO_TIMESTAMPNS
+
+#endif /* _ASM_SOCKET_H */
--- /dev/null
+#ifndef _ASM_SOCKIOS_H
+#define _ASM_SOCKIOS_H
+
+/* Socket-level I/O control calls. */
+#define FIOSETOWN 0x8901
+#define SIOCSPGRP 0x8902
+#define FIOGETOWN 0x8903
+#define SIOCGPGRP 0x8904
+#define SIOCATMARK 0x8905
+#define SIOCGSTAMP 0x8906 /* Get stamp */
+#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
+
+#endif /* _ASM_SOCKIOS_H */
--- /dev/null
+/* MN10300 spinlock support
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_SPINLOCK_H
+#define _ASM_SPINLOCK_H
+
+#error SMP spinlocks not implemented for MN10300
+
+#endif /* _ASM_SPINLOCK_H */
--- /dev/null
+#ifndef _ASM_STAT_H
+#define _ASM_STAT_H
+
+struct __old_kernel_stat {
+ unsigned short st_dev;
+ unsigned short st_ino;
+ unsigned short st_mode;
+ unsigned short st_nlink;
+ unsigned short st_uid;
+ unsigned short st_gid;
+ unsigned short st_rdev;
+ unsigned long st_size;
+ unsigned long st_atime;
+ unsigned long st_mtime;
+ unsigned long st_ctime;
+};
+
+struct stat {
+ unsigned long st_dev;
+ unsigned long st_ino;
+ unsigned short st_mode;
+ unsigned short st_nlink;
+ unsigned short st_uid;
+ unsigned short st_gid;
+ unsigned long st_rdev;
+ unsigned long st_size;
+ unsigned long st_blksize;
+ unsigned long st_blocks;
+ unsigned long st_atime;
+ unsigned long st_atime_nsec;
+ unsigned long st_mtime;
+ unsigned long st_mtime_nsec;
+ unsigned long st_ctime;
+ unsigned long st_ctime_nsec;
+ unsigned long __unused4;
+ unsigned long __unused5;
+};
+
+/* This matches struct stat64 in glibc2.1, hence the absolutely
+ * insane amounts of padding around dev_t's.
+ */
+struct stat64 {
+ unsigned long long st_dev;
+ unsigned char __pad0[4];
+
+#define STAT64_HAS_BROKEN_ST_INO 1
+ unsigned long __st_ino;
+
+ unsigned int st_mode;
+ unsigned int st_nlink;
+
+ unsigned long st_uid;
+ unsigned long st_gid;
+
+ unsigned long long st_rdev;
+ unsigned char __pad3[4];
+
+ long long st_size;
+ unsigned long st_blksize;
+
+ unsigned long st_blocks; /* Number 512-byte blocks allocated. */
+ unsigned long __pad4; /* future possible st_blocks high bits */
+
+ unsigned long st_atime;
+ unsigned long st_atime_nsec;
+
+ unsigned long st_mtime;
+ unsigned int st_mtime_nsec;
+
+ unsigned long st_ctime;
+ unsigned long st_ctime_nsec;
+
+ unsigned long long st_ino;
+};
+
+#define STAT_HAVE_NSEC 1
+
+#endif /* _ASM_STAT_H */
--- /dev/null
+#include <asm-generic/statfs.h>
--- /dev/null
+/* MN10300 Optimised string functions
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Modified by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_STRING_H
+#define _ASM_STRING_H
+
+#define __HAVE_ARCH_MEMSET
+#define __HAVE_ARCH_MEMCPY
+#define __HAVE_ARCH_MEMMOVE
+
+extern void *memset(void *dest, int ch, size_t count);
+extern void *memcpy(void *dest, const void *src, size_t count);
+extern void *memmove(void *dest, const void *src, size_t count);
+
+
+extern void __struct_cpy_bug(void);
+#define struct_cpy(x, y) \
+({ \
+ if (sizeof(*(x)) != sizeof(*(y))) \
+ __struct_cpy_bug; \
+ memcpy(x, y, sizeof(*(x))); \
+})
+
+#endif /* _ASM_STRING_H */
--- /dev/null
+/* MN10300 System definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_SYSTEM_H
+#define _ASM_SYSTEM_H
+
+#include <asm/cpu-regs.h>
+
+#ifdef __KERNEL__
+#ifndef __ASSEMBLY__
+
+#include <linux/kernel.h>
+
+struct task_struct;
+struct thread_struct;
+
+extern asmlinkage
+struct task_struct *__switch_to(struct thread_struct *prev,
+ struct thread_struct *next,
+ struct task_struct *prev_task);
+
+/* context switching is now performed out-of-line in switch_to.S */
+#define switch_to(prev, next, last) \
+do { \
+ current->thread.wchan = (u_long) __builtin_return_address(0); \
+ (last) = __switch_to(&(prev)->thread, &(next)->thread, (prev)); \
+ mb(); \
+ current->thread.wchan = 0; \
+} while (0)
+
+#define arch_align_stack(x) (x)
+
+#define nop() asm volatile ("nop")
+
+#endif /* !__ASSEMBLY__ */
+
+/*
+ * Force strict CPU ordering.
+ * And yes, this is required on UP too when we're talking
+ * to devices.
+ *
+ * For now, "wmb()" doesn't actually do anything, as all
+ * Intel CPU's follow what Intel calls a *Processor Order*,
+ * in which all writes are seen in the program order even
+ * outside the CPU.
+ *
+ * I expect future Intel CPU's to have a weaker ordering,
+ * but I'd also expect them to finally get their act together
+ * and add some real memory barriers if so.
+ *
+ * Some non intel clones support out of order store. wmb() ceases to be a
+ * nop for these.
+ */
+
+#define mb() asm volatile ("": : :"memory")
+#define rmb() mb()
+#define wmb() asm volatile ("": : :"memory")
+
+#ifdef CONFIG_SMP
+#define smp_mb() mb()
+#define smp_rmb() rmb()
+#define smp_wmb() wmb()
+#else
+#define smp_mb() barrier()
+#define smp_rmb() barrier()
+#define smp_wmb() barrier()
+#endif
+
+#define set_mb(var, value) do { var = value; mb(); } while (0)
+#define set_wmb(var, value) do { var = value; wmb(); } while (0)
+
+#define read_barrier_depends() do {} while (0)
+#define smp_read_barrier_depends() do {} while (0)
+
+/*****************************************************************************/
+/*
+ * interrupt control
+ * - "disabled": run in IM1/2
+ * - level 0 - GDB stub
+ * - level 1 - virtual serial DMA (if present)
+ * - level 5 - normal interrupt priority
+ * - level 6 - timer interrupt
+ * - "enabled": run in IM7
+ */
+#ifdef CONFIG_MN10300_TTYSM
+#define MN10300_CLI_LEVEL EPSW_IM_2
+#else
+#define MN10300_CLI_LEVEL EPSW_IM_1
+#endif
+
+#define local_save_flags(x) \
+do { \
+ typecheck(unsigned long, x); \
+ asm volatile( \
+ " mov epsw,%0 \n" \
+ : "=d"(x) \
+ ); \
+} while (0)
+
+#define local_irq_disable() \
+do { \
+ asm volatile( \
+ " and %0,epsw \n" \
+ " or %1,epsw \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ : \
+ : "i"(~EPSW_IM), "i"(EPSW_IE | MN10300_CLI_LEVEL) \
+ ); \
+} while (0)
+
+#define local_irq_save(x) \
+do { \
+ local_save_flags(x); \
+ local_irq_disable(); \
+} while (0)
+
+/*
+ * we make sure local_irq_enable() doesn't cause priority inversion
+ */
+#ifndef __ASSEMBLY__
+
+extern unsigned long __mn10300_irq_enabled_epsw;
+
+#endif
+
+#define local_irq_enable() \
+do { \
+ unsigned long tmp; \
+ \
+ asm volatile( \
+ " mov epsw,%0 \n" \
+ " and %1,%0 \n" \
+ " or %2,%0 \n" \
+ " mov %0,epsw \n" \
+ : "=&d"(tmp) \
+ : "i"(~EPSW_IM), "r"(__mn10300_irq_enabled_epsw) \
+ ); \
+} while (0)
+
+#define local_irq_restore(x) \
+do { \
+ typecheck(unsigned long, x); \
+ asm volatile( \
+ " mov %0,epsw \n" \
+ " nop \n" \
+ " nop \n" \
+ " nop \n" \
+ : \
+ : "d"(x) \
+ : "memory", "cc" \
+ ); \
+} while (0)
+
+#define irqs_disabled() \
+({ \
+ unsigned long flags; \
+ local_save_flags(flags); \
+ (flags & EPSW_IM) <= MN10300_CLI_LEVEL; \
+})
+
+/* hook to save power by halting the CPU
+ * - called from the idle loop
+ * - must reenable interrupts (which takes three instruction cycles to complete)
+ */
+#define safe_halt() \
+do { \
+ asm volatile(" or %0,epsw \n" \
+ " nop \n" \
+ " nop \n" \
+ " bset %2,(%1) \n" \
+ : \
+ : "i"(EPSW_IE|EPSW_IM), "n"(&CPUM), "i"(CPUM_SLEEP)\
+ : "cc" \
+ ); \
+} while (0)
+
+#define STI or EPSW_IE|EPSW_IM,epsw
+#define CLI and ~EPSW_IM,epsw; or EPSW_IE|MN10300_CLI_LEVEL,epsw; nop; nop; nop
+
+/*****************************************************************************/
+/*
+ * MN10300 doesn't actually have an exchange instruction
+ */
+#ifndef __ASSEMBLY__
+
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((struct __xchg_dummy *)(x))
+
+static inline
+unsigned long __xchg(volatile unsigned long *m, unsigned long val)
+{
+ unsigned long retval;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ retval = *m;
+ *m = val;
+ local_irq_restore(flags);
+ return retval;
+}
+
+#define xchg(ptr, v) \
+ ((__typeof__(*(ptr))) __xchg((unsigned long *)(ptr), \
+ (unsigned long)(v)))
+
+static inline unsigned long __cmpxchg(volatile unsigned long *m,
+ unsigned long old, unsigned long new)
+{
+ unsigned long retval;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ retval = *m;
+ if (retval == old)
+ *m = new;
+ local_irq_restore(flags);
+ return retval;
+}
+
+#define cmpxchg(ptr, o, n) \
+ ((__typeof__(*(ptr))) __cmpxchg((unsigned long *)(ptr), \
+ (unsigned long)(o), \
+ (unsigned long)(n)))
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_SYSTEM_H */
--- /dev/null
+#ifndef _ASM_TERMBITS_H
+#define _ASM_TERMBITS_H
+
+#include <linux/posix_types.h>
+
+typedef unsigned char cc_t;
+typedef unsigned int speed_t;
+typedef unsigned int tcflag_t;
+
+#define NCCS 19
+struct termios {
+ tcflag_t c_iflag; /* input mode flags */
+ tcflag_t c_oflag; /* output mode flags */
+ tcflag_t c_cflag; /* control mode flags */
+ tcflag_t c_lflag; /* local mode flags */
+ cc_t c_line; /* line discipline */
+ cc_t c_cc[NCCS]; /* control characters */
+};
+
+struct termios2 {
+ tcflag_t c_iflag; /* input mode flags */
+ tcflag_t c_oflag; /* output mode flags */
+ tcflag_t c_cflag; /* control mode flags */
+ tcflag_t c_lflag; /* local mode flags */
+ cc_t c_line; /* line discipline */
+ cc_t c_cc[NCCS]; /* control characters */
+ speed_t c_ispeed; /* input speed */
+ speed_t c_ospeed; /* output speed */
+};
+
+struct ktermios {
+ tcflag_t c_iflag; /* input mode flags */
+ tcflag_t c_oflag; /* output mode flags */
+ tcflag_t c_cflag; /* control mode flags */
+ tcflag_t c_lflag; /* local mode flags */
+ cc_t c_line; /* line discipline */
+ cc_t c_cc[NCCS]; /* control characters */
+ speed_t c_ispeed; /* input speed */
+ speed_t c_ospeed; /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VTIME 5
+#define VMIN 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+#define VSUSP 10
+#define VEOL 11
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+#define VEOL2 16
+
+
+/* c_iflag bits */
+#define IGNBRK 0000001
+#define BRKINT 0000002
+#define IGNPAR 0000004
+#define PARMRK 0000010
+#define INPCK 0000020
+#define ISTRIP 0000040
+#define INLCR 0000100
+#define IGNCR 0000200
+#define ICRNL 0000400
+#define IUCLC 0001000
+#define IXON 0002000
+#define IXANY 0004000
+#define IXOFF 0010000
+#define IMAXBEL 0020000
+#define IUTF8 0040000
+
+/* c_oflag bits */
+#define OPOST 0000001
+#define OLCUC 0000002
+#define ONLCR 0000004
+#define OCRNL 0000010
+#define ONOCR 0000020
+#define ONLRET 0000040
+#define OFILL 0000100
+#define OFDEL 0000200
+#define NLDLY 0000400
+#define NL0 0000000
+#define NL1 0000400
+#define CRDLY 0003000
+#define CR0 0000000
+#define CR1 0001000
+#define CR2 0002000
+#define CR3 0003000
+#define TABDLY 0014000
+#define TAB0 0000000
+#define TAB1 0004000
+#define TAB2 0010000
+#define TAB3 0014000
+#define XTABS 0014000
+#define BSDLY 0020000
+#define BS0 0000000
+#define BS1 0020000
+#define VTDLY 0040000
+#define VT0 0000000
+#define VT1 0040000
+#define FFDLY 0100000
+#define FF0 0000000
+#define FF1 0100000
+
+/* c_cflag bit meaning */
+#define CBAUD 0010017
+#define B0 0000000 /* hang up */
+#define B50 0000001
+#define B75 0000002
+#define B110 0000003
+#define B134 0000004
+#define B150 0000005
+#define B200 0000006
+#define B300 0000007
+#define B600 0000010
+#define B1200 0000011
+#define B1800 0000012
+#define B2400 0000013
+#define B4800 0000014
+#define B9600 0000015
+#define B19200 0000016
+#define B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE 0000060
+#define CS5 0000000
+#define CS6 0000020
+#define CS7 0000040
+#define CS8 0000060
+#define CSTOPB 0000100
+#define CREAD 0000200
+#define PARENB 0000400
+#define PARODD 0001000
+#define HUPCL 0002000
+#define CLOCAL 0004000
+#define CBAUDEX 0010000
+#define BOTHER 0010000
+#define B57600 0010001
+#define B115200 0010002
+#define B230400 0010003
+#define B460800 0010004
+#define B500000 0010005
+#define B576000 0010006
+#define B921600 0010007
+#define B1000000 0010010
+#define B1152000 0010011
+#define B1500000 0010012
+#define B2000000 0010013
+#define B2500000 0010014
+#define B3000000 0010015
+#define B3500000 0010016
+#define B4000000 0010017
+#define CIBAUD 002003600000 /* input baud rate (not used) */
+#define CTVB 004000000000 /* VisioBraille Terminal flow control */
+#define CMSPAR 010000000000 /* mark or space (stick) parity */
+#define CRTSCTS 020000000000 /* flow control */
+
+#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define ISIG 0000001
+#define ICANON 0000002
+#define XCASE 0000004
+#define ECHO 0000010
+#define ECHOE 0000020
+#define ECHOK 0000040
+#define ECHONL 0000100
+#define NOFLSH 0000200
+#define TOSTOP 0000400
+#define ECHOCTL 0001000
+#define ECHOPRT 0002000
+#define ECHOKE 0004000
+#define FLUSHO 0010000
+#define PENDIN 0040000
+#define IEXTEN 0100000
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF 0
+#define TCOON 1
+#define TCIOFF 2
+#define TCION 3
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH 0
+#define TCOFLUSH 1
+#define TCIOFLUSH 2
+
+/* tcsetattr uses these */
+#define TCSANOW 0
+#define TCSADRAIN 1
+#define TCSAFLUSH 2
+
+#endif /* _ASM_TERMBITS_H */
--- /dev/null
+#ifndef _ASM_TERMIOS_H
+#define _ASM_TERMIOS_H
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct winsize {
+ unsigned short ws_row;
+ unsigned short ws_col;
+ unsigned short ws_xpixel;
+ unsigned short ws_ypixel;
+};
+
+#define NCC 8
+struct termio {
+ unsigned short c_iflag; /* input mode flags */
+ unsigned short c_oflag; /* output mode flags */
+ unsigned short c_cflag; /* control mode flags */
+ unsigned short c_lflag; /* local mode flags */
+ unsigned char c_line; /* line discipline */
+ unsigned char c_cc[NCC]; /* control characters */
+};
+
+#ifdef __KERNEL__
+/* intr=^C quit=^| erase=del kill=^U
+ eof=^D vtime=\0 vmin=\1 sxtc=\0
+ start=^Q stop=^S susp=^Z eol=\0
+ reprint=^R discard=^U werase=^W lnext=^V
+ eol2=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
+#endif
+
+/* modem lines */
+#define TIOCM_LE 0x001
+#define TIOCM_DTR 0x002
+#define TIOCM_RTS 0x004
+#define TIOCM_ST 0x008
+#define TIOCM_SR 0x010
+#define TIOCM_CTS 0x020
+#define TIOCM_CAR 0x040
+#define TIOCM_RNG 0x080
+#define TIOCM_DSR 0x100
+#define TIOCM_CD TIOCM_CAR
+#define TIOCM_RI TIOCM_RNG
+#define TIOCM_OUT1 0x2000
+#define TIOCM_OUT2 0x4000
+#define TIOCM_LOOP 0x8000
+
+#define TIOCM_MODEM_BITS TIOCM_OUT2 /* IRDA support */
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
+ unsigned short __tmp; \
+ get_user(__tmp, &(termio)->x); \
+ *(unsigned short *) &(termios)->x = __tmp; \
+}
+
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+ SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
+ SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
+ SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
+ SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
+ copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+ put_user((termios)->c_iflag, &(termio)->c_iflag); \
+ put_user((termios)->c_oflag, &(termio)->c_oflag); \
+ put_user((termios)->c_cflag, &(termio)->c_cflag); \
+ put_user((termios)->c_lflag, &(termio)->c_lflag); \
+ put_user((termios)->c_line, &(termio)->c_line); \
+ copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+})
+
+#define user_termios_to_kernel_termios(k, u) \
+ copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) \
+ copy_to_user(u, k, sizeof(struct termios2))
+#define user_termios_to_kernel_termios_1(k, u) \
+ copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios_1(u, k) \
+ copy_to_user(u, k, sizeof(struct termios))
+
+#endif /* _ASM_TERMIOS_H */
--- /dev/null
+/* MN10300 Low-level thread information
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#include <asm/page.h>
+
+#ifndef __ASSEMBLY__
+#include <asm/processor.h>
+#endif
+
+#define PREEMPT_ACTIVE 0x10000000
+
+#ifdef CONFIG_4KSTACKS
+#define THREAD_SIZE (4096)
+#else
+#define THREAD_SIZE (8192)
+#endif
+
+#define STACK_WARN (THREAD_SIZE / 8)
+
+/*
+ * low level task data that entry.S needs immediate access to
+ * - this struct should fit entirely inside of one cache line
+ * - this struct shares the supervisor stack pages
+ * - if the contents of this structure are changed, the assembly constants
+ * must also be changed
+ */
+#ifndef __ASSEMBLY__
+
+struct thread_info {
+ struct task_struct *task; /* main task structure */
+ struct exec_domain *exec_domain; /* execution domain */
+ unsigned long flags; /* low level flags */
+ __u32 cpu; /* current CPU */
+ __s32 preempt_count; /* 0 => preemptable, <0 => BUG */
+
+ mm_segment_t addr_limit; /* thread address space:
+ 0-0xBFFFFFFF for user-thead
+ 0-0xFFFFFFFF for kernel-thread
+ */
+ struct restart_block restart_block;
+
+ __u8 supervisor_stack[0];
+};
+
+#else /* !__ASSEMBLY__ */
+
+#ifndef __ASM_OFFSETS_H__
+#include <asm/asm-offsets.h>
+#endif
+
+#endif
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ *
+ * preempt_count needs to be 1 initially, until the scheduler is functional.
+ */
+#ifndef __ASSEMBLY__
+
+#define INIT_THREAD_INFO(tsk) \
+{ \
+ .task = &tsk, \
+ .exec_domain = &default_exec_domain, \
+ .flags = 0, \
+ .cpu = 0, \
+ .preempt_count = 1, \
+ .addr_limit = KERNEL_DS, \
+ .restart_block = { \
+ .fn = do_no_restart_syscall, \
+ }, \
+}
+
+#define init_thread_info (init_thread_union.thread_info)
+#define init_stack (init_thread_union.stack)
+#define init_uregs \
+ ((struct pt_regs *) \
+ ((unsigned long) init_stack + THREAD_SIZE - sizeof(struct pt_regs)))
+
+extern struct thread_info *__current_ti;
+
+/* how to get the thread information struct from C */
+static inline __attribute__((const))
+struct thread_info *current_thread_info(void)
+{
+ struct thread_info *ti;
+ asm("mov sp,%0\n"
+ "and %1,%0\n"
+ : "=d" (ti)
+ : "i" (~(THREAD_SIZE - 1))
+ : "cc");
+ return ti;
+}
+
+/* how to get the current stack pointer from C */
+static inline unsigned long current_stack_pointer(void)
+{
+ unsigned long sp;
+ asm("mov sp,%0; ":"=r" (sp));
+ return sp;
+}
+
+/* thread information allocation */
+#ifdef CONFIG_DEBUG_STACK_USAGE
+#define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL)
+#else
+#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
+#endif
+
+#define free_thread_info(ti) kfree((ti))
+#define get_thread_info(ti) get_task_struct((ti)->task)
+#define put_thread_info(ti) put_task_struct((ti)->task)
+
+#else /* !__ASSEMBLY__ */
+
+#ifndef __VMLINUX_LDS__
+/* how to get the thread information struct from ASM */
+.macro GET_THREAD_INFO reg
+ mov sp,\reg
+ and -THREAD_SIZE,\reg
+.endm
+#endif
+#endif
+
+/*
+ * thread information flags
+ * - these are process state flags that various assembly files may need to
+ * access
+ * - pending work-to-be-done flags are in LSW
+ * - other flags in MSW
+ */
+#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
+#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */
+#define TIF_SIGPENDING 2 /* signal pending */
+#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
+#define TIF_SINGLESTEP 4 /* restore singlestep on return to user mode */
+#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
+#define TIF_POLLING_NRFLAG 16 /* true if poll_idle() is polling TIF_NEED_RESCHED */
+#define TIF_MEMDIE 17 /* OOM killer killed process */
+#define TIF_FREEZE 18 /* freezing for suspend */
+
+#define _TIF_SYSCALL_TRACE +(1 << TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME +(1 << TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING +(1 << TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED +(1 << TIF_NEED_RESCHED)
+#define _TIF_SINGLESTEP +(1 << TIF_SINGLESTEP)
+#define _TIF_RESTORE_SIGMASK +(1 << TIF_RESTORE_SIGMASK)
+#define _TIF_POLLING_NRFLAG +(1 << TIF_POLLING_NRFLAG)
+#define _TIF_FREEZE +(1 << TIF_FREEZE)
+
+#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
+#define _TIF_ALLWORK_MASK 0x0000FFFF /* work to do on any return to u-space */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_THREAD_INFO_H */
--- /dev/null
+/* AM33v2 on-board timer module registers
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_TIMER_REGS_H
+#define _ASM_TIMER_REGS_H
+
+#include <asm/cpu-regs.h>
+#include <asm/intctl-regs.h>
+
+#ifdef __KERNEL__
+
+/* timer prescalar control */
+#define TMPSCNT __SYSREG(0xd4003071, u8) /* timer prescaler control */
+#define TMPSCNT_ENABLE 0x80 /* timer prescaler enable */
+#define TMPSCNT_DISABLE 0x00 /* timer prescaler disable */
+
+/* 8 bit timers */
+#define TM0MD __SYSREG(0xd4003000, u8) /* timer 0 mode register */
+#define TM0MD_SRC 0x07 /* timer source */
+#define TM0MD_SRC_IOCLK 0x00 /* - IOCLK */
+#define TM0MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
+#define TM0MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
+#define TM0MD_SRC_TM2IO 0x03 /* - TM2IO pin input */
+#define TM0MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
+#define TM0MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
+#define TM0MD_SRC_TM0IO 0x07 /* - TM0IO pin input */
+#define TM0MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
+#define TM0MD_COUNT_ENABLE 0x80 /* timer count enable */
+
+#define TM1MD __SYSREG(0xd4003001, u8) /* timer 1 mode register */
+#define TM1MD_SRC 0x07 /* timer source */
+#define TM1MD_SRC_IOCLK 0x00 /* - IOCLK */
+#define TM1MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
+#define TM1MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
+#define TM1MD_SRC_TM0CASCADE 0x03 /* - cascade with timer 0 */
+#define TM1MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
+#define TM1MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
+#define TM1MD_SRC_TM1IO 0x07 /* - TM1IO pin input */
+#define TM1MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
+#define TM1MD_COUNT_ENABLE 0x80 /* timer count enable */
+
+#define TM2MD __SYSREG(0xd4003002, u8) /* timer 2 mode register */
+#define TM2MD_SRC 0x07 /* timer source */
+#define TM2MD_SRC_IOCLK 0x00 /* - IOCLK */
+#define TM2MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
+#define TM2MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
+#define TM2MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 1 */
+#define TM2MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
+#define TM2MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
+#define TM2MD_SRC_TM2IO 0x07 /* - TM2IO pin input */
+#define TM2MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
+#define TM2MD_COUNT_ENABLE 0x80 /* timer count enable */
+
+#define TM3MD __SYSREG(0xd4003003, u8) /* timer 3 mode register */
+#define TM3MD_SRC 0x07 /* timer source */
+#define TM3MD_SRC_IOCLK 0x00 /* - IOCLK */
+#define TM3MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
+#define TM3MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
+#define TM3MD_SRC_TM1CASCADE 0x03 /* - cascade with timer 2 */
+#define TM3MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
+#define TM3MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
+#define TM3MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
+#define TM3MD_SRC_TM3IO 0x07 /* - TM3IO pin input */
+#define TM3MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
+#define TM3MD_COUNT_ENABLE 0x80 /* timer count enable */
+
+#define TM01MD __SYSREG(0xd4003000, u16) /* timer 0:1 mode register */
+
+#define TM0BR __SYSREG(0xd4003010, u8) /* timer 0 base register */
+#define TM1BR __SYSREG(0xd4003011, u8) /* timer 1 base register */
+#define TM2BR __SYSREG(0xd4003012, u8) /* timer 2 base register */
+#define TM3BR __SYSREG(0xd4003013, u8) /* timer 3 base register */
+#define TM01BR __SYSREG(0xd4003010, u16) /* timer 0:1 base register */
+
+#define TM0BC __SYSREGC(0xd4003020, u8) /* timer 0 binary counter */
+#define TM1BC __SYSREGC(0xd4003021, u8) /* timer 1 binary counter */
+#define TM2BC __SYSREGC(0xd4003022, u8) /* timer 2 binary counter */
+#define TM3BC __SYSREGC(0xd4003023, u8) /* timer 3 binary counter */
+#define TM01BC __SYSREGC(0xd4003020, u16) /* timer 0:1 binary counter */
+
+#define TM0IRQ 2 /* timer 0 IRQ */
+#define TM1IRQ 3 /* timer 1 IRQ */
+#define TM2IRQ 4 /* timer 2 IRQ */
+#define TM3IRQ 5 /* timer 3 IRQ */
+
+#define TM0ICR GxICR(TM0IRQ) /* timer 0 uflow intr ctrl reg */
+#define TM1ICR GxICR(TM1IRQ) /* timer 1 uflow intr ctrl reg */
+#define TM2ICR GxICR(TM2IRQ) /* timer 2 uflow intr ctrl reg */
+#define TM3ICR GxICR(TM3IRQ) /* timer 3 uflow intr ctrl reg */
+
+/* 16-bit timers 4,5 & 7-11 */
+#define TM4MD __SYSREG(0xd4003080, u8) /* timer 4 mode register */
+#define TM4MD_SRC 0x07 /* timer source */
+#define TM4MD_SRC_IOCLK 0x00 /* - IOCLK */
+#define TM4MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
+#define TM4MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
+#define TM4MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
+#define TM4MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
+#define TM4MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
+#define TM4MD_SRC_TM4IO 0x07 /* - TM4IO pin input */
+#define TM4MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
+#define TM4MD_COUNT_ENABLE 0x80 /* timer count enable */
+
+#define TM5MD __SYSREG(0xd4003082, u8) /* timer 5 mode register */
+#define TM5MD_SRC 0x07 /* timer source */
+#define TM5MD_SRC_IOCLK 0x00 /* - IOCLK */
+#define TM5MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
+#define TM5MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
+#define TM5MD_SRC_TM4CASCADE 0x03 /* - cascade with timer 4 */
+#define TM5MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
+#define TM5MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
+#define TM5MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
+#define TM5MD_SRC_TM5IO 0x07 /* - TM5IO pin input */
+#define TM5MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
+#define TM5MD_COUNT_ENABLE 0x80 /* timer count enable */
+
+#define TM7MD __SYSREG(0xd4003086, u8) /* timer 7 mode register */
+#define TM7MD_SRC 0x07 /* timer source */
+#define TM7MD_SRC_IOCLK 0x00 /* - IOCLK */
+#define TM7MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
+#define TM7MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
+#define TM7MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
+#define TM7MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
+#define TM7MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
+#define TM7MD_SRC_TM7IO 0x07 /* - TM7IO pin input */
+#define TM7MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
+#define TM7MD_COUNT_ENABLE 0x80 /* timer count enable */
+
+#define TM8MD __SYSREG(0xd4003088, u8) /* timer 8 mode register */
+#define TM8MD_SRC 0x07 /* timer source */
+#define TM8MD_SRC_IOCLK 0x00 /* - IOCLK */
+#define TM8MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
+#define TM8MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
+#define TM8MD_SRC_TM7CASCADE 0x03 /* - cascade with timer 7 */
+#define TM8MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
+#define TM8MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
+#define TM8MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
+#define TM8MD_SRC_TM8IO 0x07 /* - TM8IO pin input */
+#define TM8MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
+#define TM8MD_COUNT_ENABLE 0x80 /* timer count enable */
+
+#define TM9MD __SYSREG(0xd400308a, u8) /* timer 9 mode register */
+#define TM9MD_SRC 0x07 /* timer source */
+#define TM9MD_SRC_IOCLK 0x00 /* - IOCLK */
+#define TM9MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
+#define TM9MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
+#define TM9MD_SRC_TM8CASCADE 0x03 /* - cascade with timer 8 */
+#define TM9MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
+#define TM9MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
+#define TM9MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
+#define TM9MD_SRC_TM9IO 0x07 /* - TM9IO pin input */
+#define TM9MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
+#define TM9MD_COUNT_ENABLE 0x80 /* timer count enable */
+
+#define TM10MD __SYSREG(0xd400308c, u8) /* timer 10 mode register */
+#define TM10MD_SRC 0x07 /* timer source */
+#define TM10MD_SRC_IOCLK 0x00 /* - IOCLK */
+#define TM10MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
+#define TM10MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
+#define TM10MD_SRC_TM9CASCADE 0x03 /* - cascade with timer 9 */
+#define TM10MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
+#define TM10MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
+#define TM10MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
+#define TM10MD_SRC_TM10IO 0x07 /* - TM10IO pin input */
+#define TM10MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
+#define TM10MD_COUNT_ENABLE 0x80 /* timer count enable */
+
+#define TM11MD __SYSREG(0xd400308e, u8) /* timer 11 mode register */
+#define TM11MD_SRC 0x07 /* timer source */
+#define TM11MD_SRC_IOCLK 0x00 /* - IOCLK */
+#define TM11MD_SRC_IOCLK_8 0x01 /* - 1/8 IOCLK */
+#define TM11MD_SRC_IOCLK_32 0x02 /* - 1/32 IOCLK */
+#define TM11MD_SRC_TM7CASCADE 0x03 /* - cascade with timer 7 */
+#define TM11MD_SRC_TM0UFLOW 0x04 /* - timer 0 underflow */
+#define TM11MD_SRC_TM1UFLOW 0x05 /* - timer 1 underflow */
+#define TM11MD_SRC_TM2UFLOW 0x06 /* - timer 2 underflow */
+#define TM11MD_SRC_TM11IO 0x07 /* - TM11IO pin input */
+#define TM11MD_INIT_COUNTER 0x40 /* initialize TMnBC = TMnBR */
+#define TM11MD_COUNT_ENABLE 0x80 /* timer count enable */
+
+#define TM4BR __SYSREG(0xd4003090, u16) /* timer 4 base register */
+#define TM5BR __SYSREG(0xd4003092, u16) /* timer 5 base register */
+#define TM7BR __SYSREG(0xd4003096, u16) /* timer 7 base register */
+#define TM8BR __SYSREG(0xd4003098, u16) /* timer 8 base register */
+#define TM9BR __SYSREG(0xd400309a, u16) /* timer 9 base register */
+#define TM10BR __SYSREG(0xd400309c, u16) /* timer 10 base register */
+#define TM11BR __SYSREG(0xd400309e, u16) /* timer 11 base register */
+#define TM45BR __SYSREG(0xd4003090, u32) /* timer 4:5 base register */
+
+#define TM4BC __SYSREG(0xd40030a0, u16) /* timer 4 binary counter */
+#define TM5BC __SYSREG(0xd40030a2, u16) /* timer 5 binary counter */
+#define TM45BC __SYSREG(0xd40030a0, u32) /* timer 4:5 binary counter */
+
+#define TM7BC __SYSREG(0xd40030a6, u16) /* timer 7 binary counter */
+#define TM8BC __SYSREG(0xd40030a8, u16) /* timer 8 binary counter */
+#define TM9BC __SYSREG(0xd40030aa, u16) /* timer 9 binary counter */
+#define TM10BC __SYSREG(0xd40030ac, u16) /* timer 10 binary counter */
+#define TM11BC __SYSREG(0xd40030ae, u16) /* timer 11 binary counter */
+
+#define TM4IRQ 6 /* timer 4 IRQ */
+#define TM5IRQ 7 /* timer 5 IRQ */
+#define TM7IRQ 11 /* timer 7 IRQ */
+#define TM8IRQ 12 /* timer 8 IRQ */
+#define TM9IRQ 13 /* timer 9 IRQ */
+#define TM10IRQ 14 /* timer 10 IRQ */
+#define TM11IRQ 15 /* timer 11 IRQ */
+
+#define TM4ICR GxICR(TM4IRQ) /* timer 4 uflow intr ctrl reg */
+#define TM5ICR GxICR(TM5IRQ) /* timer 5 uflow intr ctrl reg */
+#define TM7ICR GxICR(TM7IRQ) /* timer 7 uflow intr ctrl reg */
+#define TM8ICR GxICR(TM8IRQ) /* timer 8 uflow intr ctrl reg */
+#define TM9ICR GxICR(TM9IRQ) /* timer 9 uflow intr ctrl reg */
+#define TM10ICR GxICR(TM10IRQ) /* timer 10 uflow intr ctrl reg */
+#define TM11ICR GxICR(TM11IRQ) /* timer 11 uflow intr ctrl reg */
+
+/* 16-bit timer 6 */
+#define TM6MD __SYSREG(0xd4003084, u16) /* timer6 mode register */
+#define TM6MD_SRC 0x0007 /* timer source */
+#define TM6MD_SRC_IOCLK 0x0000 /* - IOCLK */
+#define TM6MD_SRC_IOCLK_8 0x0001 /* - 1/8 IOCLK */
+#define TM6MD_SRC_IOCLK_32 0x0002 /* - 1/32 IOCLK */
+#define TM6MD_SRC_TM0UFLOW 0x0004 /* - timer 0 underflow */
+#define TM6MD_SRC_TM1UFLOW 0x0005 /* - timer 1 underflow */
+#define TM6MD_SRC_TM6IOB_BOTH 0x0006 /* - TM6IOB pin input (both edges) */
+#define TM6MD_SRC_TM6IOB_SINGLE 0x0007 /* - TM6IOB pin input (single edge) */
+#define TM6MD_CLR_ENABLE 0x0010 /* clear count enable */
+#define TM6MD_ONESHOT_ENABLE 0x0040 /* oneshot count */
+#define TM6MD_TRIG_ENABLE 0x0080 /* TM6IOB pin trigger enable */
+#define TM6MD_PWM 0x3800 /* PWM output mode */
+#define TM6MD_PWM_DIS 0x0000 /* - disabled */
+#define TM6MD_PWM_10BIT 0x1000 /* - 10 bits mode */
+#define TM6MD_PWM_11BIT 0x1800 /* - 11 bits mode */
+#define TM6MD_PWM_12BIT 0x3000 /* - 12 bits mode */
+#define TM6MD_PWM_14BIT 0x3800 /* - 14 bits mode */
+#define TM6MD_INIT_COUNTER 0x4000 /* initialize TMnBC to zero */
+#define TM6MD_COUNT_ENABLE 0x8000 /* timer count enable */
+
+#define TM6MDA __SYSREG(0xd40030b4, u8) /* timer6 cmp/cap A mode reg */
+#define TM6MDA_OUT 0x07 /* output select */
+#define TM6MDA_OUT_SETA_RESETB 0x00 /* - set at match A, reset at match B */
+#define TM6MDA_OUT_SETA_RESETOV 0x01 /* - set at match A, reset at overflow */
+#define TM6MDA_OUT_SETA 0x02 /* - set at match A */
+#define TM6MDA_OUT_RESETA 0x03 /* - reset at match A */
+#define TM6MDA_OUT_TOGGLE 0x04 /* - toggle on match A */
+#define TM6MDA_MODE 0xc0 /* compare A register mode */
+#define TM6MDA_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */
+#define TM6MDA_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */
+#define TM6MDA_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */
+#define TM6MDA_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */
+#define TM6MDA_EDGE 0x20 /* compare A edge select */
+#define TM6MDA_EDGE_FALLING 0x00 /* capture on falling edge */
+#define TM6MDA_EDGE_RISING 0x20 /* capture on rising edge */
+#define TM6MDA_CAPTURE_ENABLE 0x10 /* capture enable */
+
+#define TM6MDB __SYSREG(0xd40030b5, u8) /* timer6 cmp/cap B mode reg */
+#define TM6MDB_OUT 0x07 /* output select */
+#define TM6MDB_OUT_SETB_RESETA 0x00 /* - set at match B, reset at match A */
+#define TM6MDB_OUT_SETB_RESETOV 0x01 /* - set at match B */
+#define TM6MDB_OUT_RESETB 0x03 /* - reset at match B */
+#define TM6MDB_OUT_TOGGLE 0x04 /* - toggle on match B */
+#define TM6MDB_MODE 0xc0 /* compare B register mode */
+#define TM6MDB_MODE_CMP_SINGLE 0x00 /* - compare, single buffer mode */
+#define TM6MDB_MODE_CMP_DOUBLE 0x40 /* - compare, double buffer mode */
+#define TM6MDB_MODE_CAP_S_EDGE 0x80 /* - capture, single edge mode */
+#define TM6MDB_MODE_CAP_D_EDGE 0xc0 /* - capture, double edge mode */
+#define TM6MDB_EDGE 0x20 /* compare B edge select */
+#define TM6MDB_EDGE_FALLING 0x00 /* capture on falling edge */
+#define TM6MDB_EDGE_RISING 0x20 /* capture on rising edge */
+#define TM6MDB_CAPTURE_ENABLE 0x10 /* capture enable */
+
+#define TM6CA __SYSREG(0xd40030c4, u16) /* timer6 cmp/capture reg A */
+#define TM6CB __SYSREG(0xd40030d4, u16) /* timer6 cmp/capture reg B */
+#define TM6BC __SYSREG(0xd40030a4, u16) /* timer6 binary counter */
+
+#define TM6IRQ 6 /* timer 6 IRQ */
+#define TM6AIRQ 9 /* timer 6A IRQ */
+#define TM6BIRQ 10 /* timer 6B IRQ */
+
+#define TM6ICR GxICR(TM6IRQ) /* timer 6 uflow intr ctrl reg */
+#define TM6AICR GxICR(TM6AIRQ) /* timer 6A intr control reg */
+#define TM6BICR GxICR(TM6BIRQ) /* timer 6B intr control reg */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_TIMER_REGS_H */
--- /dev/null
+/* MN10300 Architecture time management specifications
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_TIMEX_H
+#define _ASM_TIMEX_H
+
+#include <asm/hardirq.h>
+#include <asm/unit/timex.h>
+
+#define TICK_SIZE (tick_nsec / 1000)
+
+#define CLOCK_TICK_RATE 1193180 /* Underlying HZ - this should probably be set
+ * to something appropriate, but what? */
+
+extern cycles_t cacheflush_time;
+
+#ifdef __KERNEL__
+
+static inline cycles_t get_cycles(void)
+{
+ return read_timestamp_counter();
+}
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_TIMEX_H */
--- /dev/null
+/* MN10300 TLB definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_TLB_H
+#define _ASM_TLB_H
+
+#include <asm/tlbflush.h>
+
+extern void check_pgt_cache(void);
+
+/*
+ * we don't need any special per-pte or per-vma handling...
+ */
+#define tlb_start_vma(tlb, vma) do { } while (0)
+#define tlb_end_vma(tlb, vma) do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
+
+/*
+ * .. because we flush the whole mm when it fills up
+ */
+#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
+
+/* for now, just use the generic stuff */
+#include <asm-generic/tlb.h>
+
+#endif /* _ASM_TLB_H */
--- /dev/null
+/* MN10300 TLB flushing functions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_TLBFLUSH_H
+#define _ASM_TLBFLUSH_H
+
+#include <asm/processor.h>
+
+#define __flush_tlb() \
+do { \
+ int w; \
+ __asm__ __volatile__ \
+ (" mov %1,%0 \n" \
+ " or %2,%0 \n" \
+ " mov %0,%1 \n" \
+ : "=d"(w) \
+ : "m"(MMUCTR), "i"(MMUCTR_IIV|MMUCTR_DIV) \
+ : "memory" \
+ ); \
+} while (0)
+
+#define __flush_tlb_all() __flush_tlb()
+#define __flush_tlb_one(addr) __flush_tlb()
+
+
+/*
+ * TLB flushing:
+ *
+ * - flush_tlb() flushes the current mm struct TLBs
+ * - flush_tlb_all() flushes all processes TLBs
+ * - flush_tlb_mm(mm) flushes the specified mm context TLB's
+ * - flush_tlb_page(vma, vmaddr) flushes one page
+ * - flush_tlb_range(mm, start, end) flushes a range of pages
+ * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
+ */
+#define flush_tlb_all() \
+do { \
+ preempt_disable(); \
+ __flush_tlb_all(); \
+ preempt_enable(); \
+} while (0)
+
+#define flush_tlb_mm(mm) \
+do { \
+ preempt_disable(); \
+ __flush_tlb_all(); \
+ preempt_enable(); \
+} while (0)
+
+#define flush_tlb_range(vma, start, end) \
+do { \
+ unsigned long __s __attribute__((unused)) = (start); \
+ unsigned long __e __attribute__((unused)) = (end); \
+ preempt_disable(); \
+ __flush_tlb_all(); \
+ preempt_enable(); \
+} while (0)
+
+
+#define __flush_tlb_global() flush_tlb_all()
+#define flush_tlb() flush_tlb_all()
+#define flush_tlb_kernel_range(start, end) \
+do { \
+ unsigned long __s __attribute__((unused)) = (start); \
+ unsigned long __e __attribute__((unused)) = (end); \
+ flush_tlb_all(); \
+} while (0)
+
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
+
+#define flush_tlb_pgtables(mm, start, end) do {} while (0)
+
+#endif /* _ASM_TLBFLUSH_H */
--- /dev/null
+#include <asm-generic/topology.h>
--- /dev/null
+/* MN10300 Basic type definitions
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_TYPES_H
+#define _ASM_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+/* Dma addresses are 32-bits wide. */
+typedef u32 dma_addr_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_TYPES_H */
--- /dev/null
+/* MN10300 userspace access functions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_UACCESS_H
+#define _ASM_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include <linux/sched.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/errno.h>
+
+#define VERIFY_READ 0
+#define VERIFY_WRITE 1
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not. If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ *
+ * For historical reasons, these macros are grossly misnamed.
+ */
+
+#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
+
+#define KERNEL_XDS MAKE_MM_SEG(0xBFFFFFFF)
+#define KERNEL_DS MAKE_MM_SEG(0x9FFFFFFF)
+#define USER_DS MAKE_MM_SEG(TASK_SIZE)
+
+#define get_ds() (KERNEL_DS)
+#define get_fs() (current_thread_info()->addr_limit)
+#define set_fs(x) (current_thread_info()->addr_limit = (x))
+#define __kernel_ds_p() (current_thread_info()->addr_limit.seg == 0x9FFFFFFF)
+
+#define segment_eq(a, b) ((a).seg == (b).seg)
+
+#define __addr_ok(addr) \
+ ((unsigned long)(addr) < (current_thread_info()->addr_limit.seg))
+
+/*
+ * check that a range of addresses falls within the current address limit
+ */
+static inline int ___range_ok(unsigned long addr, unsigned int size)
+{
+ int flag = 1, tmp;
+
+ asm(" add %3,%1 \n" /* set C-flag if addr + size > 4Gb */
+ " bcs 0f \n"
+ " cmp %4,%1 \n" /* jump if addr+size>limit (error) */
+ " bhi 0f \n"
+ " clr %0 \n" /* mark okay */
+ "0: \n"
+ : "=r"(flag), "=&r"(tmp)
+ : "1"(addr), "ir"(size),
+ "r"(current_thread_info()->addr_limit.seg), "0"(flag)
+ : "cc"
+ );
+
+ return flag;
+}
+
+#define __range_ok(addr, size) ___range_ok((unsigned long)(addr), (u32)(size))
+
+#define access_ok(type, addr, size) (__range_ok((addr), (size)) == 0)
+#define __access_ok(addr, size) (__range_ok((addr), (size)) == 0)
+
+static inline int verify_area(int type, const void *addr, unsigned long size)
+{
+ return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue. No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path. This means when everything is well,
+ * we don't even have to jump over them. Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry
+{
+ unsigned long insn, fixup;
+};
+
+/* Returns 0 if exception not found and fixup otherwise. */
+extern int fixup_exception(struct pt_regs *regs);
+
+#define put_user(x, ptr) __put_user_check((x), (ptr), sizeof(*(ptr)))
+#define get_user(x, ptr) __get_user_check((x), (ptr), sizeof(*(ptr)))
+
+/*
+ * The "__xxx" versions do not do address space checking, useful when
+ * doing multiple accesses to the same area (the user has to do the
+ * checks by hand with "access_ok()")
+ */
+#define __put_user(x, ptr) __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
+#define __get_user(x, ptr) __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
+
+/*
+ * The "xxx_ret" versions return constant specified in third argument, if
+ * something bad happens. These macros can be optimized for the
+ * case of just returning from the function xxx_ret is used.
+ */
+
+#define put_user_ret(x, ptr, ret) \
+ ({ if (put_user((x), (ptr))) return (ret); })
+#define get_user_ret(x, ptr, ret) \
+ ({ if (get_user((x), (ptr))) return (ret); })
+#define __put_user_ret(x, ptr, ret) \
+ ({ if (__put_user((x), (ptr))) return (ret); })
+#define __get_user_ret(x, ptr, ret) \
+ ({ if (__get_user((x), (ptr))) return (ret); })
+
+struct __large_struct { unsigned long buf[100]; };
+#define __m(x) (*(struct __large_struct *)(x))
+
+#define __get_user_nocheck(x, ptr, size) \
+({ \
+ __typeof(*(ptr)) __gu_val; \
+ unsigned long __gu_addr; \
+ int __gu_err; \
+ __gu_addr = (unsigned long) (ptr); \
+ switch (size) { \
+ case 1: __get_user_asm("bu"); break; \
+ case 2: __get_user_asm("hu"); break; \
+ case 4: __get_user_asm("" ); break; \
+ default: __get_user_unknown(); break; \
+ } \
+ x = (__typeof__(*(ptr))) __gu_val; \
+ __gu_err; \
+})
+
+#define __get_user_check(x, ptr, size) \
+({ \
+ __typeof__(*(ptr)) __gu_val; \
+ unsigned long __gu_addr; \
+ int __gu_err; \
+ __gu_addr = (unsigned long) (ptr); \
+ if (likely(__access_ok(__gu_addr,size))) { \
+ switch (size) { \
+ case 1: __get_user_asm("bu"); break; \
+ case 2: __get_user_asm("hu"); break; \
+ case 4: __get_user_asm("" ); break; \
+ default: __get_user_unknown(); break; \
+ } \
+ } \
+ else { \
+ __gu_err = -EFAULT; \
+ __gu_val = 0; \
+ } \
+ x = (__typeof__(*(ptr))) __gu_val; \
+ __gu_err; \
+})
+
+#define __get_user_asm(INSN) \
+({ \
+ asm volatile( \
+ "1:\n" \
+ " mov"INSN" %2,%1\n" \
+ " mov 0,%0\n" \
+ "2:\n" \
+ " .section .fixup,\"ax\"\n" \
+ "3:\n\t" \
+ " mov %3,%0\n" \
+ " jmp 2b\n" \
+ " .previous\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 1b, 3b\n" \
+ " .previous" \
+ : "=&r" (__gu_err), "=&r" (__gu_val) \
+ : "m" (__m(__gu_addr)), "i" (-EFAULT)); \
+})
+
+extern int __get_user_unknown(void);
+
+#define __put_user_nocheck(x, ptr, size) \
+({ \
+ union { \
+ __typeof__(*(ptr)) val; \
+ u32 bits[2]; \
+ } __pu_val; \
+ unsigned long __pu_addr; \
+ int __pu_err; \
+ __pu_val.val = (x); \
+ __pu_addr = (unsigned long) (ptr); \
+ switch (size) { \
+ case 1: __put_user_asm("bu"); break; \
+ case 2: __put_user_asm("hu"); break; \
+ case 4: __put_user_asm("" ); break; \
+ case 8: __put_user_asm8(); break; \
+ default: __pu_err = __put_user_unknown(); break; \
+ } \
+ __pu_err; \
+})
+
+#define __put_user_check(x, ptr, size) \
+({ \
+ union { \
+ __typeof__(*(ptr)) val; \
+ u32 bits[2]; \
+ } __pu_val; \
+ unsigned long __pu_addr; \
+ int __pu_err; \
+ __pu_val.val = (x); \
+ __pu_addr = (unsigned long) (ptr); \
+ if (likely(__access_ok(__pu_addr, size))) { \
+ switch (size) { \
+ case 1: __put_user_asm("bu"); break; \
+ case 2: __put_user_asm("hu"); break; \
+ case 4: __put_user_asm("" ); break; \
+ case 8: __put_user_asm8(); break; \
+ default: __pu_err = __put_user_unknown(); break; \
+ } \
+ } \
+ else { \
+ __pu_err = -EFAULT; \
+ } \
+ __pu_err; \
+})
+
+#define __put_user_asm(INSN) \
+({ \
+ asm volatile( \
+ "1:\n" \
+ " mov"INSN" %1,%2\n" \
+ " mov 0,%0\n" \
+ "2:\n" \
+ " .section .fixup,\"ax\"\n" \
+ "3:\n" \
+ " mov %3,%0\n" \
+ " jmp 2b\n" \
+ " .previous\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 1b, 3b\n" \
+ " .previous" \
+ : "=&r" (__pu_err) \
+ : "r" (__pu_val.val), "m" (__m(__pu_addr)), \
+ "i" (-EFAULT) \
+ ); \
+})
+
+#define __put_user_asm8() \
+({ \
+ asm volatile( \
+ "1: mov %1,%3 \n" \
+ "2: mov %2,%4 \n" \
+ " mov 0,%0 \n" \
+ "3: \n" \
+ " .section .fixup,\"ax\" \n" \
+ "4: \n" \
+ " mov %5,%0 \n" \
+ " jmp 2b \n" \
+ " .previous \n" \
+ " .section __ex_table,\"a\"\n" \
+ " .balign 4 \n" \
+ " .long 1b, 4b \n" \
+ " .long 2b, 4b \n" \
+ " .previous \n" \
+ : "=&r" (__pu_err) \
+ : "r" (__pu_val.bits[0]), "r" (__pu_val.bits[1]), \
+ "m" (__m(__pu_addr)), "m" (__m(__pu_addr+4)), \
+ "i" (-EFAULT) \
+ ); \
+})
+
+extern int __put_user_unknown(void);
+
+
+/*
+ * Copy To/From Userspace
+ */
+/* Generic arbitrary sized copy. */
+#define __copy_user(to, from, size) \
+do { \
+ if (size) { \
+ void *__to = to; \
+ const void *__from = from; \
+ int w; \
+ asm volatile( \
+ "0: movbu (%0),%3;\n" \
+ "1: movbu %3,(%1);\n" \
+ " inc %0;\n" \
+ " inc %1;\n" \
+ " add -1,%2;\n" \
+ " bne 0b;\n" \
+ "2:\n" \
+ " .section .fixup,\"ax\"\n" \
+ "3: jmp 2b\n" \
+ " .previous\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,3b\n" \
+ " .long 1b,3b\n" \
+ " .previous\n" \
+ : "=a"(__from), "=a"(__to), "=r"(size), "=&r"(w)\
+ : "0"(__from), "1"(__to), "2"(size) \
+ : "memory"); \
+ } \
+} while (0)
+
+#define __copy_user_zeroing(to, from, size) \
+do { \
+ if (size) { \
+ void *__to = to; \
+ const void *__from = from; \
+ int w; \
+ asm volatile( \
+ "0: movbu (%0),%3;\n" \
+ "1: movbu %3,(%1);\n" \
+ " inc %0;\n" \
+ " inc %1;\n" \
+ " add -1,%2;\n" \
+ " bne 0b;\n" \
+ "2:\n" \
+ " .section .fixup,\"ax\"\n" \
+ "3:\n" \
+ " mov %2,%0\n" \
+ " clr %3\n" \
+ "4: movbu %3,(%1);\n" \
+ " inc %1;\n" \
+ " add -1,%2;\n" \
+ " bne 4b;\n" \
+ " mov %0,%2\n" \
+ " jmp 2b\n" \
+ " .previous\n" \
+ " .section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,3b\n" \
+ " .long 1b,3b\n" \
+ " .previous\n" \
+ : "=a"(__from), "=a"(__to), "=r"(size), "=&r"(w)\
+ : "0"(__from), "1"(__to), "2"(size) \
+ : "memory"); \
+ } \
+} while (0)
+
+/* We let the __ versions of copy_from/to_user inline, because they're often
+ * used in fast paths and have only a small space overhead.
+ */
+static inline
+unsigned long __generic_copy_from_user_nocheck(void *to, const void *from,
+ unsigned long n)
+{
+ __copy_user_zeroing(to, from, n);
+ return n;
+}
+
+static inline
+unsigned long __generic_copy_to_user_nocheck(void *to, const void *from,
+ unsigned long n)
+{
+ __copy_user(to, from, n);
+ return n;
+}
+
+
+#if 0
+#error don't use - these macros don't increment to & from pointers
+/* Optimize just a little bit when we know the size of the move. */
+#define __constant_copy_user(to, from, size) \
+do { \
+ asm volatile( \
+ " mov %0,a0;\n" \
+ "0: movbu (%1),d3;\n" \
+ "1: movbu d3,(%2);\n" \
+ " add -1,a0;\n" \
+ " bne 0b;\n" \
+ "2:;" \
+ ".section .fixup,\"ax\"\n" \
+ "3: jmp 2b\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,3b\n" \
+ " .long 1b,3b\n" \
+ ".previous" \
+ : \
+ : "d"(size), "d"(to), "d"(from) \
+ : "d3", "a0"); \
+} while (0)
+
+/* Optimize just a little bit when we know the size of the move. */
+#define __constant_copy_user_zeroing(to, from, size) \
+do { \
+ asm volatile( \
+ " mov %0,a0;\n" \
+ "0: movbu (%1),d3;\n" \
+ "1: movbu d3,(%2);\n" \
+ " add -1,a0;\n" \
+ " bne 0b;\n" \
+ "2:;" \
+ ".section .fixup,\"ax\"\n" \
+ "3: jmp 2b\n" \
+ ".previous\n" \
+ ".section __ex_table,\"a\"\n" \
+ " .balign 4\n" \
+ " .long 0b,3b\n" \
+ " .long 1b,3b\n" \
+ ".previous" \
+ : \
+ : "d"(size), "d"(to), "d"(from) \
+ : "d3", "a0"); \
+} while (0)
+
+static inline
+unsigned long __constant_copy_to_user(void *to, const void *from,
+ unsigned long n)
+{
+ if (access_ok(VERIFY_WRITE, to, n))
+ __constant_copy_user(to, from, n);
+ return n;
+}
+
+static inline
+unsigned long __constant_copy_from_user(void *to, const void *from,
+ unsigned long n)
+{
+ if (access_ok(VERIFY_READ, from, n))
+ __constant_copy_user_zeroing(to, from, n);
+ return n;
+}
+
+static inline
+unsigned long __constant_copy_to_user_nocheck(void *to, const void *from,
+ unsigned long n)
+{
+ __constant_copy_user(to, from, n);
+ return n;
+}
+
+static inline
+unsigned long __constant_copy_from_user_nocheck(void *to, const void *from,
+ unsigned long n)
+{
+ __constant_copy_user_zeroing(to, from, n);
+ return n;
+}
+#endif
+
+extern unsigned long __generic_copy_to_user(void __user *, const void *,
+ unsigned long);
+extern unsigned long __generic_copy_from_user(void *, const void __user *,
+ unsigned long);
+
+#define __copy_to_user_inatomic(to, from, n) \
+ __generic_copy_to_user_nocheck((to), (from), (n))
+#define __copy_from_user_inatomic(to, from, n) \
+ __generic_copy_from_user_nocheck((to), (from), (n))
+
+#define __copy_to_user(to, from, n) \
+({ \
+ might_sleep(); \
+ __copy_to_user_inatomic((to), (from), (n)); \
+})
+
+#define __copy_from_user(to, from, n) \
+({ \
+ might_sleep(); \
+ __copy_from_user_inatomic((to), (from), (n)); \
+})
+
+
+#define copy_to_user(to, from, n) __generic_copy_to_user((to), (from), (n))
+#define copy_from_user(to, from, n) __generic_copy_from_user((to), (from), (n))
+
+extern long strncpy_from_user(char *dst, const char __user *src, long count);
+extern long __strncpy_from_user(char *dst, const char __user *src, long count);
+extern long strnlen_user(const char __user *str, long n);
+#define strlen_user(str) strnlen_user(str, ~0UL >> 1)
+extern unsigned long clear_user(void __user *mem, unsigned long len);
+extern unsigned long __clear_user(void __user *mem, unsigned long len);
+
+#endif /* _ASM_UACCESS_H */
--- /dev/null
+/* MN10300 User context
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_UCONTEXT_H
+#define _ASM_UCONTEXT_H
+
+struct ucontext {
+ unsigned long uc_flags;
+ struct ucontext *uc_link;
+ stack_t uc_stack;
+ struct sigcontext uc_mcontext;
+ sigset_t uc_sigmask; /* mask last for extensibility */
+};
+
+#endif /* _ASM_UCONTEXT_H */
--- /dev/null
+/* MN10300 Unaligned memory access handling
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_UNALIGNED_H
+#define _ASM_UNALIGNED_H
+
+#include <asm/types.h>
+
+#if 0
+extern int __bug_unaligned_x(void *ptr);
+
+/*
+ * What is the most efficient way of loading/storing an unaligned value?
+ *
+ * That is the subject of this file. Efficiency here is defined as
+ * minimum code size with minimum register usage for the common cases.
+ * It is currently not believed that long longs are common, so we
+ * trade efficiency for the chars, shorts and longs against the long
+ * longs.
+ *
+ * Current stats with gcc 2.7.2.2 for these functions:
+ *
+ * ptrsize get: code regs put: code regs
+ * 1 1 1 1 2
+ * 2 3 2 3 2
+ * 4 7 3 7 3
+ * 8 20 6 16 6
+ *
+ * gcc 2.95.1 seems to code differently:
+ *
+ * ptrsize get: code regs put: code regs
+ * 1 1 1 1 2
+ * 2 3 2 3 2
+ * 4 7 4 7 4
+ * 8 19 8 15 6
+ *
+ * which may or may not be more efficient (depending upon whether
+ * you can afford the extra registers). Hopefully the gcc 2.95
+ * is inteligent enough to decide if it is better to use the
+ * extra register, but evidence so far seems to suggest otherwise.
+ *
+ * Unfortunately, gcc is not able to optimise the high word
+ * out of long long >> 32, or the low word from long long << 32
+ */
+
+#define __get_unaligned_2(__p) \
+ (__p[0] | __p[1] << 8)
+
+#define __get_unaligned_4(__p) \
+ (__p[0] | __p[1] << 8 | __p[2] << 16 | __p[3] << 24)
+
+#define get_unaligned(ptr) \
+({ \
+ unsigned int __v1, __v2; \
+ __typeof__(*(ptr)) __v; \
+ __u8 *__p = (__u8 *)(ptr); \
+ \
+ switch (sizeof(*(ptr))) { \
+ case 1: __v = *(ptr); break; \
+ case 2: __v = __get_unaligned_2(__p); break; \
+ case 4: __v = __get_unaligned_4(__p); break; \
+ case 8: \
+ __v2 = __get_unaligned_4((__p+4)); \
+ __v1 = __get_unaligned_4(__p); \
+ __v = ((unsigned long long)__v2 << 32 | __v1); \
+ break; \
+ default: __v = __bug_unaligned_x(__p); break; \
+ } \
+ __v; \
+})
+
+
+static inline void __put_unaligned_2(__u32 __v, register __u8 *__p)
+{
+ *__p++ = __v;
+ *__p++ = __v >> 8;
+}
+
+static inline void __put_unaligned_4(__u32 __v, register __u8 *__p)
+{
+ __put_unaligned_2(__v >> 16, __p + 2);
+ __put_unaligned_2(__v, __p);
+}
+
+static inline void __put_unaligned_8(const unsigned long long __v, __u8 *__p)
+{
+ /*
+ * tradeoff: 8 bytes of stack for all unaligned puts (2
+ * instructions), or an extra register in the long long
+ * case - go for the extra register.
+ */
+ __put_unaligned_4(__v >> 32, __p + 4);
+ __put_unaligned_4(__v, __p);
+}
+
+/*
+ * Try to store an unaligned value as efficiently as possible.
+ */
+#define put_unaligned(val, ptr) \
+ ({ \
+ switch (sizeof(*(ptr))) { \
+ case 1: \
+ *(ptr) = (val); \
+ break; \
+ case 2: \
+ __put_unaligned_2((val), (__u8 *)(ptr)); \
+ break; \
+ case 4: \
+ __put_unaligned_4((val), (__u8 *)(ptr)); \
+ break; \
+ case 8: \
+ __put_unaligned_8((val), (__u8 *)(ptr)); \
+ break; \
+ default: \
+ __bug_unaligned_x(ptr); \
+ break; \
+ } \
+ (void) 0; \
+ })
+
+
+#else
+
+#define get_unaligned(ptr) (*(ptr))
+#define put_unaligned(val, ptr) ({ *(ptr) = (val); (void) 0; })
+
+#endif
+
+#endif
--- /dev/null
+/* MN10300 System call number list
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_UNISTD_H
+#define _ASM_UNISTD_H
+
+#define __NR_restart_syscall 0
+#define __NR_exit 1
+#define __NR_fork 2
+#define __NR_read 3
+#define __NR_write 4
+#define __NR_open 5
+#define __NR_close 6
+#define __NR_waitpid 7
+#define __NR_creat 8
+#define __NR_link 9
+#define __NR_unlink 10
+#define __NR_execve 11
+#define __NR_chdir 12
+#define __NR_time 13
+#define __NR_mknod 14
+#define __NR_chmod 15
+#define __NR_lchown 16
+#define __NR_break 17
+#define __NR_oldstat 18
+#define __NR_lseek 19
+#define __NR_getpid 20
+#define __NR_mount 21
+#define __NR_umount 22
+#define __NR_setuid 23
+#define __NR_getuid 24
+#define __NR_stime 25
+#define __NR_ptrace 26
+#define __NR_alarm 27
+#define __NR_oldfstat 28
+#define __NR_pause 29
+#define __NR_utime 30
+#define __NR_stty 31
+#define __NR_gtty 32
+#define __NR_access 33
+#define __NR_nice 34
+#define __NR_ftime 35
+#define __NR_sync 36
+#define __NR_kill 37
+#define __NR_rename 38
+#define __NR_mkdir 39
+#define __NR_rmdir 40
+#define __NR_dup 41
+#define __NR_pipe 42
+#define __NR_times 43
+#define __NR_prof 44
+#define __NR_brk 45
+#define __NR_setgid 46
+#define __NR_getgid 47
+#define __NR_signal 48
+#define __NR_geteuid 49
+#define __NR_getegid 50
+#define __NR_acct 51
+#define __NR_umount2 52
+#define __NR_lock 53
+#define __NR_ioctl 54
+#define __NR_fcntl 55
+#define __NR_mpx 56
+#define __NR_setpgid 57
+#define __NR_ulimit 58
+#define __NR_oldolduname 59
+#define __NR_umask 60
+#define __NR_chroot 61
+#define __NR_ustat 62
+#define __NR_dup2 63
+#define __NR_getppid 64
+#define __NR_getpgrp 65
+#define __NR_setsid 66
+#define __NR_sigaction 67
+#define __NR_sgetmask 68
+#define __NR_ssetmask 69
+#define __NR_setreuid 70
+#define __NR_setregid 71
+#define __NR_sigsuspend 72
+#define __NR_sigpending 73
+#define __NR_sethostname 74
+#define __NR_setrlimit 75
+#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */
+#define __NR_getrusage 77
+#define __NR_gettimeofday 78
+#define __NR_settimeofday 79
+#define __NR_getgroups 80
+#define __NR_setgroups 81
+#define __NR_select 82
+#define __NR_symlink 83
+#define __NR_oldlstat 84
+#define __NR_readlink 85
+#define __NR_uselib 86
+#define __NR_swapon 87
+#define __NR_reboot 88
+#define __NR_readdir 89
+#define __NR_mmap 90
+#define __NR_munmap 91
+#define __NR_truncate 92
+#define __NR_ftruncate 93
+#define __NR_fchmod 94
+#define __NR_fchown 95
+#define __NR_getpriority 96
+#define __NR_setpriority 97
+#define __NR_profil 98
+#define __NR_statfs 99
+#define __NR_fstatfs 100
+#define __NR_ioperm 101
+#define __NR_socketcall 102
+#define __NR_syslog 103
+#define __NR_setitimer 104
+#define __NR_getitimer 105
+#define __NR_stat 106
+#define __NR_lstat 107
+#define __NR_fstat 108
+#define __NR_olduname 109
+#define __NR_iopl 110
+#define __NR_vhangup 111
+#define __NR_idle 112
+#define __NR_vm86old 113
+#define __NR_wait4 114
+#define __NR_swapoff 115
+#define __NR_sysinfo 116
+#define __NR_ipc 117
+#define __NR_fsync 118
+#define __NR_sigreturn 119
+#define __NR_clone 120
+#define __NR_setdomainname 121
+#define __NR_uname 122
+#define __NR_modify_ldt 123
+#define __NR_adjtimex 124
+#define __NR_mprotect 125
+#define __NR_sigprocmask 126
+#define __NR_create_module 127
+#define __NR_init_module 128
+#define __NR_delete_module 129
+#define __NR_get_kernel_syms 130
+#define __NR_quotactl 131
+#define __NR_getpgid 132
+#define __NR_fchdir 133
+#define __NR_bdflush 134
+#define __NR_sysfs 135
+#define __NR_personality 136
+#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
+#define __NR_setfsuid 138
+#define __NR_setfsgid 139
+#define __NR__llseek 140
+#define __NR_getdents 141
+#define __NR__newselect 142
+#define __NR_flock 143
+#define __NR_msync 144
+#define __NR_readv 145
+#define __NR_writev 146
+#define __NR_getsid 147
+#define __NR_fdatasync 148
+#define __NR__sysctl 149
+#define __NR_mlock 150
+#define __NR_munlock 151
+#define __NR_mlockall 152
+#define __NR_munlockall 153
+#define __NR_sched_setparam 154
+#define __NR_sched_getparam 155
+#define __NR_sched_setscheduler 156
+#define __NR_sched_getscheduler 157
+#define __NR_sched_yield 158
+#define __NR_sched_get_priority_max 159
+#define __NR_sched_get_priority_min 160
+#define __NR_sched_rr_get_interval 161
+#define __NR_nanosleep 162
+#define __NR_mremap 163
+#define __NR_setresuid 164
+#define __NR_getresuid 165
+#define __NR_vm86 166
+#define __NR_query_module 167
+#define __NR_poll 168
+#define __NR_nfsservctl 169
+#define __NR_setresgid 170
+#define __NR_getresgid 171
+#define __NR_prctl 172
+#define __NR_rt_sigreturn 173
+#define __NR_rt_sigaction 174
+#define __NR_rt_sigprocmask 175
+#define __NR_rt_sigpending 176
+#define __NR_rt_sigtimedwait 177
+#define __NR_rt_sigqueueinfo 178
+#define __NR_rt_sigsuspend 179
+#define __NR_pread64 180
+#define __NR_pwrite64 181
+#define __NR_chown 182
+#define __NR_getcwd 183
+#define __NR_capget 184
+#define __NR_capset 185
+#define __NR_sigaltstack 186
+#define __NR_sendfile 187
+#define __NR_getpmsg 188 /* some people actually want streams */
+#define __NR_putpmsg 189 /* some people actually want streams */
+#define __NR_vfork 190
+#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */
+#define __NR_mmap2 192
+#define __NR_truncate64 193
+#define __NR_ftruncate64 194
+#define __NR_stat64 195
+#define __NR_lstat64 196
+#define __NR_fstat64 197
+#define __NR_lchown32 198
+#define __NR_getuid32 199
+#define __NR_getgid32 200
+#define __NR_geteuid32 201
+#define __NR_getegid32 202
+#define __NR_setreuid32 203
+#define __NR_setregid32 204
+#define __NR_getgroups32 205
+#define __NR_setgroups32 206
+#define __NR_fchown32 207
+#define __NR_setresuid32 208
+#define __NR_getresuid32 209
+#define __NR_setresgid32 210
+#define __NR_getresgid32 211
+#define __NR_chown32 212
+#define __NR_setuid32 213
+#define __NR_setgid32 214
+#define __NR_setfsuid32 215
+#define __NR_setfsgid32 216
+#define __NR_pivot_root 217
+#define __NR_mincore 218
+#define __NR_madvise 219
+#define __NR_madvise1 219 /* delete when C lib stub is removed */
+#define __NR_getdents64 220
+#define __NR_fcntl64 221
+/* 223 is unused */
+#define __NR_gettid 224
+#define __NR_readahead 225
+#define __NR_setxattr 226
+#define __NR_lsetxattr 227
+#define __NR_fsetxattr 228
+#define __NR_getxattr 229
+#define __NR_lgetxattr 230
+#define __NR_fgetxattr 231
+#define __NR_listxattr 232
+#define __NR_llistxattr 233
+#define __NR_flistxattr 234
+#define __NR_removexattr 235
+#define __NR_lremovexattr 236
+#define __NR_fremovexattr 237
+#define __NR_tkill 238
+#define __NR_sendfile64 239
+#define __NR_futex 240
+#define __NR_sched_setaffinity 241
+#define __NR_sched_getaffinity 242
+#define __NR_set_thread_area 243
+#define __NR_get_thread_area 244
+#define __NR_io_setup 245
+#define __NR_io_destroy 246
+#define __NR_io_getevents 247
+#define __NR_io_submit 248
+#define __NR_io_cancel 249
+#define __NR_fadvise64 250
+
+#define __NR_exit_group 252
+#define __NR_lookup_dcookie 253
+#define __NR_epoll_create 254
+#define __NR_epoll_ctl 255
+#define __NR_epoll_wait 256
+#define __NR_remap_file_pages 257
+#define __NR_set_tid_address 258
+#define __NR_timer_create 259
+#define __NR_timer_settime (__NR_timer_create+1)
+#define __NR_timer_gettime (__NR_timer_create+2)
+#define __NR_timer_getoverrun (__NR_timer_create+3)
+#define __NR_timer_delete (__NR_timer_create+4)
+#define __NR_clock_settime (__NR_timer_create+5)
+#define __NR_clock_gettime (__NR_timer_create+6)
+#define __NR_clock_getres (__NR_timer_create+7)
+#define __NR_clock_nanosleep (__NR_timer_create+8)
+#define __NR_statfs64 268
+#define __NR_fstatfs64 269
+#define __NR_tgkill 270
+#define __NR_utimes 271
+#define __NR_fadvise64_64 272
+#define __NR_vserver 273
+#define __NR_mbind 274
+#define __NR_get_mempolicy 275
+#define __NR_set_mempolicy 276
+#define __NR_mq_open 277
+#define __NR_mq_unlink (__NR_mq_open+1)
+#define __NR_mq_timedsend (__NR_mq_open+2)
+#define __NR_mq_timedreceive (__NR_mq_open+3)
+#define __NR_mq_notify (__NR_mq_open+4)
+#define __NR_mq_getsetattr (__NR_mq_open+5)
+#define __NR_kexec_load 283
+#define __NR_waitid 284
+#define __NR_add_key 286
+#define __NR_request_key 287
+#define __NR_keyctl 288
+#define __NR_cacheflush 289
+#define __NR_ioprio_set 290
+#define __NR_ioprio_get 291
+#define __NR_inotify_init 292
+#define __NR_inotify_add_watch 293
+#define __NR_inotify_rm_watch 294
+#define __NR_migrate_pages 295
+#define __NR_openat 296
+#define __NR_mkdirat 297
+#define __NR_mknodat 298
+#define __NR_fchownat 299
+#define __NR_futimesat 300
+#define __NR_fstatat64 301
+#define __NR_unlinkat 302
+#define __NR_renameat 303
+#define __NR_linkat 304
+#define __NR_symlinkat 305
+#define __NR_readlinkat 306
+#define __NR_fchmodat 307
+#define __NR_faccessat 308
+#define __NR_pselect6 309
+#define __NR_ppoll 310
+#define __NR_unshare 311
+#define __NR_set_robust_list 312
+#define __NR_get_robust_list 313
+#define __NR_splice 314
+#define __NR_sync_file_range 315
+#define __NR_tee 316
+#define __NR_vmsplice 317
+#define __NR_move_pages 318
+#define __NR_getcpu 319
+#define __NR_epoll_pwait 320
+#define __NR_utimensat 321
+#define __NR_signalfd 322
+#define __NR_timerfd_create 323
+#define __NR_eventfd 324
+#define __NR_fallocate 325
+#define __NR_timerfd_settime 326
+#define __NR_timerfd_gettime 327
+
+#ifdef __KERNEL__
+
+#define NR_syscalls 326
+
+/*
+ * specify the deprecated syscalls we want to support on this arch
+ */
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_OLD_STAT
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_SIGNAL
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_WAITPID
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#ifndef cond_syscall
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall");
+#endif
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_UNISTD_H */
--- /dev/null
+/* ASB2303-specific clocks
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_UNIT_CLOCK_H
+#define _ASM_UNIT_CLOCK_H
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_MN10300_RTC
+
+extern unsigned long mn10300_ioclk; /* IOCLK (crystal speed) in HZ */
+extern unsigned long mn10300_iobclk;
+extern unsigned long mn10300_tsc_per_HZ;
+
+#define MN10300_IOCLK ((unsigned long)mn10300_ioclk)
+/* If this processors has a another clock, uncomment the below. */
+/* #define MN10300_IOBCLK ((unsigned long)mn10300_iobclk) */
+
+#else /* !CONFIG_MN10300_RTC */
+
+#define MN10300_IOCLK 33333333UL
+/* #define MN10300_IOBCLK 66666666UL */
+
+#endif /* !CONFIG_MN10300_RTC */
+
+#define MN10300_JCCLK MN10300_IOCLK
+#define MN10300_TSCCLK MN10300_IOCLK
+
+#ifdef CONFIG_MN10300_RTC
+#define MN10300_TSC_PER_HZ ((unsigned long)mn10300_tsc_per_HZ)
+#else /* !CONFIG_MN10300_RTC */
+#define MN10300_TSC_PER_HZ (MN10300_TSCCLK/HZ)
+#endif /* !CONFIG_MN10300_RTC */
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_UNIT_CLOCK_H */
--- /dev/null
+/* ASB2303-specific LEDs
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_UNIT_LEDS_H
+#define _ASM_UNIT_LEDS_H
+
+#include <asm/pio-regs.h>
+#include <asm/cpu-regs.h>
+#include <asm/exceptions.h>
+
+#define ASB2303_GPIO0DEF __SYSREG(0xDB000000, u32)
+#define ASB2303_7SEGLEDS __SYSREG(0xDB000008, u32)
+
+/*
+ * use the 7-segment LEDs to indicate states
+ */
+
+/* flip the 7-segment LEDs between "G" and "-" */
+#define mn10300_set_gdbleds(ONOFF) \
+do { \
+ ASB2303_7SEGLEDS = (ONOFF) ? 0x85 : 0x7f; \
+} while (0)
+
+/* indicate double-fault by displaying "d" on the LEDs */
+#define mn10300_set_dbfleds \
+ mov 0x43,d0 ; \
+ movbu d0,(ASB2303_7SEGLEDS)
+
+#ifndef __ASSEMBLY__
+extern void peripheral_leds_display_exception(enum exception_code code);
+extern void peripheral_leds_led_chase(void);
+extern void debug_to_serial(const char *p, int n);
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_UNIT_LEDS_H */
--- /dev/null
+/* ASB2303-specific 8250 serial ports
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_UNIT_SERIAL_H
+#define _ASM_UNIT_SERIAL_H
+
+#include <asm/cpu-regs.h>
+#include <asm/proc/irq.h>
+#include <linux/serial_reg.h>
+
+#define SERIAL_PORT0_BASE_ADDRESS 0xA6FB0000
+#define SERIAL_PORT1_BASE_ADDRESS 0xA6FC0000
+
+#define SERIAL_IRQ XIRQ0 /* Dual serial (PC16552) (Hi) */
+
+/*
+ * dispose of the /dev/ttyS0 and /dev/ttyS1 serial ports
+ */
+#ifndef CONFIG_GDBSTUB_ON_TTYSx
+
+#define SERIAL_PORT_DFNS \
+ { \
+ .baud_base = BASE_BAUD, \
+ .irq = SERIAL_IRQ, \
+ .flags = STD_COM_FLAGS, \
+ .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \
+ .iomem_reg_shift = 2, \
+ .io_type = SERIAL_IO_MEM, \
+ }, \
+ { \
+ .baud_base = BASE_BAUD, \
+ .irq = SERIAL_IRQ, \
+ .flags = STD_COM_FLAGS, \
+ .iomem_base = (u8 *) SERIAL_PORT1_BASE_ADDRESS, \
+ .iomem_reg_shift = 2, \
+ .io_type = SERIAL_IO_MEM, \
+ },
+
+#ifndef __ASSEMBLY__
+
+static inline void __debug_to_serial(const char *p, int n)
+{
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#else /* CONFIG_GDBSTUB_ON_TTYSx */
+
+#define SERIAL_PORT_DFNS /* both stolen by gdb-stub because they share an IRQ */
+
+#if defined(CONFIG_GDBSTUB_ON_TTYS0)
+#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
+#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
+#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
+#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
+#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
+#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
+#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
+#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
+#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
+#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8)
+#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8)
+#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8)
+#define GDBPORT_SERIAL_IRQ SERIAL_IRQ
+
+#elif defined(CONFIG_GDBSTUB_ON_TTYS1)
+#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_RX * 4, u8)
+#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_TX * 4, u8)
+#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLL * 4, u8)
+#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLM * 4, u8)
+#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IER * 4, u8)
+#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IIR * 4, u8)
+#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_FCR * 4, u8)
+#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LCR * 4, u8)
+#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MCR * 4, u8)
+#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LSR * 4, u8)
+#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MSR * 4, u8)
+#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_SCR * 4, u8)
+#define GDBPORT_SERIAL_IRQ SERIAL_IRQ
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define LSR_WAIT_FOR(STATE) \
+do { \
+ while (!(GDBPORT_SERIAL_LSR & UART_LSR_##STATE)) {} \
+} while (0)
+#define FLOWCTL_WAIT_FOR(LINE) \
+do { \
+ while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE)) {} \
+} while (0)
+#define FLOWCTL_CLEAR(LINE) \
+do { \
+ GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; \
+} while (0)
+#define FLOWCTL_SET(LINE) \
+do { \
+ GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; \
+} while (0)
+#define FLOWCTL_QUERY(LINE) ({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; })
+
+static inline void __debug_to_serial(const char *p, int n)
+{
+ char ch;
+
+ FLOWCTL_SET(DTR);
+
+ for (; n > 0; n--) {
+ LSR_WAIT_FOR(THRE);
+ FLOWCTL_WAIT_FOR(CTS);
+
+ ch = *p++;
+ if (ch == 0x0a) {
+ GDBPORT_SERIAL_TX = 0x0d;
+ LSR_WAIT_FOR(THRE);
+ FLOWCTL_WAIT_FOR(CTS);
+ }
+ GDBPORT_SERIAL_TX = ch;
+ }
+
+ FLOWCTL_CLEAR(DTR);
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* CONFIG_GDBSTUB_ON_TTYSx */
+
+#endif /* _ASM_UNIT_SERIAL_H */
--- /dev/null
+/* Support for the SMC91C111 NIC on an ASB2303
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_UNIT_SMC91111_H
+#define _ASM_UNIT_SMC91111_H
+
+#include <asm/intctl-regs.h>
+
+#define SMC91111_BASE 0xAA000300UL
+#define SMC91111_BASE_END 0xAA000400UL
+#define SMC91111_IRQ XIRQ3
+
+#define SMC_CAN_USE_8BIT 0
+#define SMC_CAN_USE_16BIT 1
+#define SMC_CAN_USE_32BIT 0
+#define SMC_NOWAIT 1
+#define SMC_IRQ_FLAGS (0)
+
+#if SMC_CAN_USE_8BIT
+#define SMC_inb(a, r) inb((unsigned long) ((a) + (r)))
+#define SMC_outb(v, a, r) outb(v, (unsigned long) ((a) + (r)))
+#endif
+
+#if SMC_CAN_USE_16BIT
+#define SMC_inw(a, r) inw((unsigned long) ((a) + (r)))
+#define SMC_outw(v, a, r) outw(v, (unsigned long) ((a) + (r)))
+#define SMC_insw(a, r, p, l) insw((unsigned long) ((a) + (r)), (p), (l))
+#define SMC_outsw(a, r, p, l) outsw((unsigned long) ((a) + (r)), (p), (l))
+#endif
+
+#if SMC_CAN_USE_32BIT
+#define SMC_inl(a, r) inl((unsigned long) ((a) + (r)))
+#define SMC_outl(v, a, r) outl(v, (unsigned long) ((a) + (r)))
+#define SMC_insl(a, r, p, l) insl((unsigned long) ((a) + (r)), (p), (l))
+#define SMC_outsl(a, r, p, l) outsl((unsigned long) ((a) + (r)), (p), (l))
+#endif
+
+#define RPC_LSA_DEFAULT RPC_LED_100_10
+#define RPC_LSB_DEFAULT RPC_LED_TX_RX
+
+#define set_irq_type(irq, type)
+
+#endif /* _ASM_UNIT_SMC91111_H */
--- /dev/null
+/* ASB2303-specific timer specifcations
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_UNIT_TIMEX_H
+#define _ASM_UNIT_TIMEX_H
+
+#ifndef __ASSEMBLY__
+#include <linux/irq.h>
+#endif /* __ASSEMBLY__ */
+
+#include <asm/timer-regs.h>
+#include <asm/unit/clock.h>
+
+/*
+ * jiffies counter specifications
+ */
+
+#define TMJCBR_MAX 0xffff
+#define TMJCBC TM01BC
+
+#define TMJCMD TM01MD
+#define TMJCBR TM01BR
+#define TMJCIRQ TM1IRQ
+#define TMJCICR TM1ICR
+#define TMJCICR_LEVEL GxICR_LEVEL_5
+
+#ifndef __ASSEMBLY__
+
+static inline void startup_jiffies_counter(void)
+{
+ unsigned rate;
+ u16 md, t16;
+
+ /* use as little prescaling as possible to avoid losing accuracy */
+ md = TM0MD_SRC_IOCLK;
+ rate = MN10300_JCCLK / HZ;
+
+ if (rate > TMJCBR_MAX) {
+ md = TM0MD_SRC_IOCLK_8;
+ rate = MN10300_JCCLK / 8 / HZ;
+
+ if (rate > TMJCBR_MAX) {
+ md = TM0MD_SRC_IOCLK_32;
+ rate = MN10300_JCCLK / 32 / HZ;
+
+ if (rate > TMJCBR_MAX)
+ BUG();
+ }
+ }
+
+ TMJCBR = rate - 1;
+ t16 = TMJCBR;
+
+ TMJCMD =
+ md |
+ TM1MD_SRC_TM0CASCADE << 8 |
+ TM0MD_INIT_COUNTER |
+ TM1MD_INIT_COUNTER << 8;
+
+ TMJCMD =
+ md |
+ TM1MD_SRC_TM0CASCADE << 8 |
+ TM0MD_COUNT_ENABLE |
+ TM1MD_COUNT_ENABLE << 8;
+
+ t16 = TMJCMD;
+
+ TMJCICR |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST;
+ t16 = TMJCICR;
+}
+
+static inline void shutdown_jiffies_counter(void)
+{
+}
+
+#endif /* !__ASSEMBLY__ */
+
+
+/*
+ * timestamp counter specifications
+ */
+
+#define TMTSCBR_MAX 0xffffffff
+#define TMTSCBC TM45BC
+
+#ifndef __ASSEMBLY__
+
+static inline void startup_timestamp_counter(void)
+{
+ /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time
+ * - count down from 4Gig-1 to 0 and wrap at IOCLK rate
+ */
+ TM45BR = TMTSCBR_MAX;
+
+ TM4MD = TM4MD_SRC_IOCLK;
+ TM4MD |= TM4MD_INIT_COUNTER;
+ TM4MD &= ~TM4MD_INIT_COUNTER;
+ TM4ICR = 0;
+
+ TM5MD = TM5MD_SRC_TM4CASCADE;
+ TM5MD |= TM5MD_INIT_COUNTER;
+ TM5MD &= ~TM5MD_INIT_COUNTER;
+ TM5ICR = 0;
+
+ TM5MD |= TM5MD_COUNT_ENABLE;
+ TM4MD |= TM4MD_COUNT_ENABLE;
+}
+
+static inline void shutdown_timestamp_counter(void)
+{
+ TM4MD = 0;
+ TM5MD = 0;
+}
+
+/*
+ * we use a cascaded pair of 16-bit down-counting timers to count I/O
+ * clock cycles for the purposes of time keeping
+ */
+typedef unsigned long cycles_t;
+
+static inline cycles_t read_timestamp_counter(void)
+{
+ return (cycles_t)TMTSCBC;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_UNIT_TIMEX_H */
--- /dev/null
+/* ASB2305-specific clocks
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_UNIT_CLOCK_H
+#define _ASM_UNIT_CLOCK_H
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_MN10300_RTC
+
+extern unsigned long mn10300_ioclk; /* IOCLK (crystal speed) in HZ */
+extern unsigned long mn10300_iobclk;
+extern unsigned long mn10300_tsc_per_HZ;
+
+#define MN10300_IOCLK ((unsigned long)mn10300_ioclk)
+/* If this processors has a another clock, uncomment the below. */
+/* #define MN10300_IOBCLK ((unsigned long)mn10300_iobclk) */
+
+#else /* !CONFIG_MN10300_RTC */
+
+#define MN10300_IOCLK 33333333UL
+/* #define MN10300_IOBCLK 66666666UL */
+
+#endif /* !CONFIG_MN10300_RTC */
+
+#define MN10300_JCCLK MN10300_IOCLK
+#define MN10300_TSCCLK MN10300_IOCLK
+
+#ifdef CONFIG_MN10300_RTC
+#define MN10300_TSC_PER_HZ ((unsigned long)mn10300_tsc_per_HZ)
+#else /* !CONFIG_MN10300_RTC */
+#define MN10300_TSC_PER_HZ (MN10300_TSCCLK/HZ)
+#endif /* !CONFIG_MN10300_RTC */
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_UNIT_CLOCK_H */
--- /dev/null
+/* ASB2305-specific LEDs
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_UNIT_LEDS_H
+#define _ASM_UNIT_LEDS_H
+
+#include <asm/pio-regs.h>
+#include <asm/cpu-regs.h>
+#include <asm/exceptions.h>
+
+#define ASB2305_7SEGLEDS __SYSREG(0xA6F90000, u32)
+
+/* perform a hard reset by driving PIO06 low */
+#define mn10300_unit_hard_reset() \
+do { \
+ P0OUT &= 0xbf; \
+ P0MD = (P0MD & P0MD_6) | P0MD_6_OUT; \
+} while (0)
+
+/*
+ * use the 7-segment LEDs to indicate states
+ */
+/* indicate double-fault by displaying "db-f" on the LEDs */
+#define mn10300_set_dbfleds \
+ mov 0x43077f1d,d0 ; \
+ mov d0,(ASB2305_7SEGLEDS)
+
+/* flip the 7-segment LEDs between "Gdb-" and "----" */
+#define mn10300_set_gdbleds(ONOFF) \
+do { \
+ ASB2305_7SEGLEDS = (ONOFF) ? 0x8543077f : 0x7f7f7f7f; \
+} while (0)
+
+#ifndef __ASSEMBLY__
+extern void peripheral_leds_display_exception(enum exception_code);
+extern void peripheral_leds_led_chase(void);
+extern void peripheral_leds7x4_display_dec(unsigned int, unsigned int);
+extern void peripheral_leds7x4_display_hex(unsigned int, unsigned int);
+extern void peripheral_leds7x4_display_minssecs(unsigned int, unsigned int);
+extern void peripheral_leds7x4_display_rtc(void);
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_UNIT_LEDS_H */
--- /dev/null
+/* ASB2305-specific 8250 serial ports
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_UNIT_SERIAL_H
+#define _ASM_UNIT_SERIAL_H
+
+#include <asm/cpu/cpu-regs.h>
+#include <asm/proc/irq.h>
+#include <linux/serial_reg.h>
+
+#define SERIAL_PORT0_BASE_ADDRESS 0xA6FB0000
+#define ASB2305_DEBUG_MCR __SYSREG(0xA6FB0000 + UART_MCR * 2, u8)
+
+#define SERIAL_IRQ XIRQ0 /* Dual serial (PC16552) (Hi) */
+
+/*
+ * dispose of the /dev/ttyS0 serial port
+ */
+#ifndef CONFIG_GDBSTUB_ON_TTYSx
+
+#define SERIAL_PORT_DFNS \
+ { \
+ .baud_base = BASE_BAUD, \
+ .irq = SERIAL_IRQ, \
+ .flags = STD_COM_FLAGS, \
+ .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \
+ .iomem_reg_shift = 2, \
+ .io_type = SERIAL_IO_MEM, \
+ },
+
+#ifndef __ASSEMBLY__
+
+static inline void __debug_to_serial(const char *p, int n)
+{
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#else /* CONFIG_GDBSTUB_ON_TTYSx */
+
+#define SERIAL_PORT_DFNS /* stolen by gdb-stub */
+
+#if defined(CONFIG_GDBSTUB_ON_TTYS0)
+#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
+#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
+#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
+#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
+#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
+#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
+#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
+#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
+#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
+#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8)
+#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8)
+#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8)
+#define GDBPORT_SERIAL_IRQ SERIAL_IRQ
+
+#elif defined(CONFIG_GDBSTUB_ON_TTYS1)
+#error The ASB2305 doesnt have a /dev/ttyS1
+#endif
+
+#ifndef __ASSEMBLY__
+
+#define TTYS0_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
+#define TTYS0_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
+#define TTYS0_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8)
+#define TTYS0_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8)
+
+#define LSR_WAIT_FOR(STATE) \
+do { \
+ while (!(TTYS0_LSR & UART_LSR_##STATE)) {} \
+} while (0)
+#define FLOWCTL_WAIT_FOR(LINE) \
+do { \
+ while (!(TTYS0_MSR & UART_MSR_##LINE)) {} \
+} while (0)
+#define FLOWCTL_CLEAR(LINE) \
+do { \
+ TTYS0_MCR &= ~UART_MCR_##LINE; \
+} while (0)
+#define FLOWCTL_SET(LINE) \
+do { \
+ TTYS0_MCR |= UART_MCR_##LINE; \
+} while (0)
+#define FLOWCTL_QUERY(LINE) ({ TTYS0_MSR & UART_MSR_##LINE; })
+
+static inline void __debug_to_serial(const char *p, int n)
+{
+ char ch;
+
+ FLOWCTL_SET(DTR);
+
+ for (; n > 0; n--) {
+ LSR_WAIT_FOR(THRE);
+ FLOWCTL_WAIT_FOR(CTS);
+
+ ch = *p++;
+ if (ch == 0x0a) {
+ TTYS0_TX = 0x0d;
+ LSR_WAIT_FOR(THRE);
+ FLOWCTL_WAIT_FOR(CTS);
+ }
+ TTYS0_TX = ch;
+ }
+
+ FLOWCTL_CLEAR(DTR);
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* CONFIG_GDBSTUB_ON_TTYSx */
+
+#endif /* _ASM_UNIT_SERIAL_H */
--- /dev/null
+/* ASB2305 timer specifcations
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_UNIT_TIMEX_H
+#define _ASM_UNIT_TIMEX_H
+
+#ifndef __ASSEMBLY__
+#include <linux/irq.h>
+#endif /* __ASSEMBLY__ */
+
+#include <asm/cpu/timer-regs.h>
+#include <asm/unit/clock.h>
+
+/*
+ * jiffies counter specifications
+ */
+
+#define TMJCBR_MAX 0xffff
+#define TMJCBC TM01BC
+
+#define TMJCMD TM01MD
+#define TMJCBR TM01BR
+#define TMJCIRQ TM1IRQ
+#define TMJCICR TM1ICR
+#define TMJCICR_LEVEL GxICR_LEVEL_5
+
+#ifndef __ASSEMBLY__
+
+static inline void startup_jiffies_counter(void)
+{
+ unsigned rate;
+ u16 md, t16;
+
+ /* use as little prescaling as possible to avoid losing accuracy */
+ md = TM0MD_SRC_IOCLK;
+ rate = MN10300_JCCLK / HZ;
+
+ if (rate > TMJCBR_MAX) {
+ md = TM0MD_SRC_IOCLK_8;
+ rate = MN10300_JCCLK / 8 / HZ;
+
+ if (rate > TMJCBR_MAX) {
+ md = TM0MD_SRC_IOCLK_32;
+ rate = MN10300_JCCLK / 32 / HZ;
+
+ if (rate > TMJCBR_MAX)
+ BUG();
+ }
+ }
+
+ TMJCBR = rate - 1;
+ t16 = TMJCBR;
+
+ TMJCMD =
+ md |
+ TM1MD_SRC_TM0CASCADE << 8 |
+ TM0MD_INIT_COUNTER |
+ TM1MD_INIT_COUNTER << 8;
+
+ TMJCMD =
+ md |
+ TM1MD_SRC_TM0CASCADE << 8 |
+ TM0MD_COUNT_ENABLE |
+ TM1MD_COUNT_ENABLE << 8;
+
+ t16 = TMJCMD;
+
+ TMJCICR |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST;
+ t16 = TMJCICR;
+}
+
+static inline void shutdown_jiffies_counter(void)
+{
+}
+
+#endif /* !__ASSEMBLY__ */
+
+
+/*
+ * timestamp counter specifications
+ */
+
+#define TMTSCBR_MAX 0xffffffff
+#define TMTSCBC TM45BC
+
+#ifndef __ASSEMBLY__
+
+static inline void startup_timestamp_counter(void)
+{
+ /* set up timer 4 & 5 cascaded as a 32-bit counter to count real time
+ * - count down from 4Gig-1 to 0 and wrap at IOCLK rate
+ */
+ TM45BR = TMTSCBR_MAX;
+
+ TM4MD = TM4MD_SRC_IOCLK;
+ TM4MD |= TM4MD_INIT_COUNTER;
+ TM4MD &= ~TM4MD_INIT_COUNTER;
+ TM4ICR = 0;
+
+ TM5MD = TM5MD_SRC_TM4CASCADE;
+ TM5MD |= TM5MD_INIT_COUNTER;
+ TM5MD &= ~TM5MD_INIT_COUNTER;
+ TM5ICR = 0;
+
+ TM5MD |= TM5MD_COUNT_ENABLE;
+ TM4MD |= TM4MD_COUNT_ENABLE;
+}
+
+static inline void shutdown_timestamp_counter(void)
+{
+ TM4MD = 0;
+ TM5MD = 0;
+}
+
+/*
+ * we use a cascaded pair of 16-bit down-counting timers to count I/O
+ * clock cycles for the purposes of time keeping
+ */
+typedef unsigned long cycles_t;
+
+static inline cycles_t read_timestamp_counter(void)
+{
+ return (cycles_t) TMTSCBC;
+}
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_UNIT_TIMEX_H */
--- /dev/null
+/* MN10300 User process data
+ *
+ * Copyright (C) 2007 Matsushita Electric Industrial Co., Ltd.
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+#ifndef _ASM_USER_H
+#define _ASM_USER_H
+
+#include <asm/page.h>
+#include <linux/ptrace.h>
+
+#ifndef __ASSEMBLY__
+/*
+ * When the kernel dumps core, it starts by dumping the user struct - this will
+ * be used by gdb to figure out where the data and stack segments are within
+ * the file, and what virtual addresses to use.
+ */
+struct user {
+ /* We start with the registers, to mimic the way that "memory" is
+ * returned from the ptrace(3,...) function.
+ */
+ struct pt_regs regs; /* Where the registers are actually stored */
+
+ /* The rest of this junk is to help gdb figure out what goes where */
+ unsigned long int u_tsize; /* Text segment size (pages). */
+ unsigned long int u_dsize; /* Data segment size (pages). */
+ unsigned long int u_ssize; /* Stack segment size (pages). */
+ unsigned long start_code; /* Starting virtual address of text. */
+ unsigned long start_stack; /* Starting virtual address of stack area.
+ This is actually the bottom of the stack,
+ the top of the stack is always found in the
+ esp register. */
+ long int signal; /* Signal that caused the core dump. */
+ int reserved; /* No longer used */
+ struct user_pt_regs *u_ar0; /* Used by gdb to help find the values for */
+
+ /* the registers */
+ unsigned long magic; /* To uniquely identify a core file */
+ char u_comm[32]; /* User command that was responsible */
+};
+#endif
+
+#define NBPG PAGE_SIZE
+#define UPAGES 1
+#define HOST_TEXT_START_ADDR +(u.start_code)
+#define HOST_STACK_END_ADDR +(u.start_stack + u.u_ssize * NBPG)
+
+#endif /* _ASM_USER_H */
--- /dev/null
+/* MN10300 VGA register definitions
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_VGA_H
+#define _ASM_VGA_H
+
+
+
+#endif /* _ASM_VGA_H */
--- /dev/null
+#include <asm-generic/xor.h>
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-#ifdef __KERNEL__
-
-/* XXX: STACK_TOP actually should be STACK_BOTTOM for parisc.
- * prumpf */
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX DEFAULT_TASK_SIZE
-
-#endif
-
#endif /* __A_OUT_GNU_H__ */
#endif /* STRICT_MM_TYPECHECKS */
+typedef struct page *pgtable_t;
typedef struct __physmem_range {
unsigned long start_pfn;
#define pmd_populate(mm, pmd, pte_page) \
pmd_populate_kernel(mm, pmd, page_address(pte_page))
+#define pmd_pgtable(pmd) pmd_page(pmd)
-static inline struct page *
+static inline pgtable_t
pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
struct page *page = alloc_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
+ if (page)
+ pgtable_page_ctor(page);
return page;
}
free_page((unsigned long)pte);
}
-#define pte_free(mm, page) pte_free_kernel(page_address(page))
+static inline void pte_free_kernel(struct mm_struct *mm, struct page *pte)
+{
+ pgtable_page_dtor(pte);
+ pte_free_kernel(page_address((pte));
+}
#define check_pgt_cache() do { } while (0)
typedef unsigned int __kernel_old_dev_t;
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
/* compatibility stuff */
typedef __kernel_uid_t __kernel_old_uid_t;
typedef __kernel_gid_t __kernel_old_gid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
#undef __FD_SET
static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
}
}
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif
#define DEFAULT_MAP_BASE DEFAULT_MAP_BASE32
#endif
+#ifdef __KERNEL__
+
+/* XXX: STACK_TOP actually should be STACK_BOTTOM for parisc.
+ * prumpf */
+
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX DEFAULT_TASK_SIZE
+
+#endif
+
#ifndef __ASSEMBLY__
/*
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-#ifdef __KERNEL__
-#ifdef __powerpc64__
-
-#define STACK_TOP_USER64 TASK_SIZE_USER64
-#define STACK_TOP_USER32 TASK_SIZE_USER32
-
-#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
- STACK_TOP_USER32 : STACK_TOP_USER64)
-
-#define STACK_TOP_MAX STACK_TOP_USER64
-
-#else /* __powerpc64__ */
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-
-#endif /* __powerpc64__ */
-#endif /* __KERNEL__ */
-
#endif /* _ASM_POWERPC_A_OUT_H */
struct vm_area_struct;
+typedef struct page *pgtable_t;
+
#include <asm-generic/memory_model.h>
#endif /* __ASSEMBLY__ */
(pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
#define pmd_populate(mm, pmd, pte) \
(pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
+#define pmd_pgtable(pmd) pmd_page(pmd)
#else
#define pmd_populate_kernel(mm, pmd, pte) \
(pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
#define pmd_populate(mm, pmd, pte) \
(pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT)
+#define pmd_pgtable(pmd) pmd_page(pmd)
#endif
extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
-extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr);
+extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte);
-extern void pte_free(struct mm_struct *mm, struct page *pte);
+extern void pte_free(struct mm_struct *mm, pgtable_t pte);
#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte))
#define pmd_populate(mm, pmd, pte_page) \
pmd_populate_kernel(mm, pmd, page_address(pte_page))
#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte))
+#define pmd_pgtable(pmd) pmd_page(pmd)
#else /* CONFIG_PPC_64K_PAGES */
#define pmd_populate(mm, pmd, pte_page) \
pmd_populate_kernel(mm, pmd, page_address(pte_page))
+#define pmd_pgtable(pmd) pmd_page(pmd)
#endif /* CONFIG_PPC_64K_PAGES */
return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
}
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+ unsigned long address)
{
- pte_t *pte = pte_alloc_one_kernel(mm, address);
- return pte ? virt_to_page(pte) : NULL;
+ struct page *page;
+ pte_t *pte;
+
+ pte = pte_alloc_one_kernel(mm, address);
+ if (!pte)
+ return NULL;
+ page = virt_to_page(pte);
+ pgtable_page_ctor(page);
+ return page;
}
static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
free_page((unsigned long)pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *ptepage)
+static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
{
+ pgtable_page_dtor(ptepage);
__free_page(ptepage);
}
extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
-#define __pte_free_tlb(tlb, ptepage) \
+#define __pte_free_tlb(tlb,ptepage) \
+do { \
+ pgtable_page_dtor(ptepage); \
pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \
- PTE_NONCACHE_NUM, PTE_TABLE_SIZE-1))
+ PTE_NONCACHE_NUM, PTE_TABLE_SIZE-1)); \
+} while (0)
#define __pmd_free_tlb(tlb, pmd) \
pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \
PMD_CACHE_NUM, PMD_TABLE_SIZE-1))
#define UN_BIS(r,v) (UN_OUT((r), UN_IN(r) | (v)))
#define UN_BIC(r,v) (UN_OUT((r), UN_IN(r) & ~(v)))
+/* Uninorth variant:
+ *
+ * 0 = not uninorth
+ * 1 = U1.x or U2.x
+ * 3 = U3
+ * 4 = U4
+ */
+extern int pmac_get_uninorth_variant(void);
#endif /* __ASM_POWERPC_PMAC_FEATURE_H */
#endif /* __KERNEL__ */
#else /* __GNUC__ */
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
- || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
+#if defined(__KERNEL__)
/* With GNU C, use inline functions instead so args are evaluated only once: */
#undef __FD_SET
}
}
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif /* __GNUC__ */
#endif /* _ASM_POWERPC_POSIX_TYPES_H */
TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
#endif
+#ifdef __KERNEL__
+#ifdef __powerpc64__
+
+#define STACK_TOP_USER64 TASK_SIZE_USER64
+#define STACK_TOP_USER32 TASK_SIZE_USER32
+
+#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
+ STACK_TOP_USER32 : STACK_TOP_USER64)
+
+#define STACK_TOP_MAX STACK_TOP_USER64
+
+#else /* __powerpc64__ */
+
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
+
+#endif /* __powerpc64__ */
+#endif /* __KERNEL__ */
+
typedef struct {
unsigned long seg;
} mm_segment_t;
(pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
#define pmd_populate(mm, pmd, pte) \
(pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
+#define pmd_pgtable(pmd) pmd_page(pmd)
#else
#define pmd_populate_kernel(mm, pmd, pte) \
(pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
#define pmd_populate(mm, pmd, pte) \
(pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT)
+#define pmd_pgtable(pmd) pmd_page(pmd)
#endif
extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
-extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr);
+extern pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long addr);
extern void pte_free_kernel(struct mm_struct *mm, pte_t *pte);
-extern void pte_free(struct mm_struct *mm, struct page *pte);
+extern void pte_free(struct mm_struct *mm, pgtable_t pte);
#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, (pte))
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-#ifdef __KERNEL__
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX DEFAULT_TASK_SIZE
-
-#endif
-
#endif /* __A_OUT_GNU_H__ */
#define TIOCSBRK 0x5427 /* BSD compatibility */
#define TIOCCBRK 0x5428 /* BSD compatibility */
#define TIOCGSID 0x5429 /* Return the session ID of FD */
+#define TCGETS2 _IOR('T',0x2A, struct termios2)
+#define TCSETS2 _IOW('T',0x2B, struct termios2)
+#define TCSETSW2 _IOW('T',0x2C, struct termios2)
+#define TCSETSF2 _IOW('T',0x2D, struct termios2)
#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
#endif /* __s390x__ */
+typedef struct page *pgtable_t;
+
#define __pte(x) ((pte_t) { (x) } )
#define __pmd(x) ((pmd_t) { (x) } )
#define __pgd(x) ((pgd_t) { (x) } )
}
static inline void
-pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *page)
+pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t page)
{
pte_t *pte = (pte_t *)page_to_phys(page);
pmd_t *shadow_pmd = get_shadow_table(pmd);
if (shadow_pmd && shadow_pte)
pmd_populate_kernel(mm, shadow_pmd, shadow_pte);
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
/*
* page table entry allocation/free routines.
#endif /* __s390x__ */
+#ifdef __KERNEL__
+
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX DEFAULT_TASK_SIZE
+
+#endif
+
#define HAVE_ARCH_PICK_MMAP_LAYOUT
typedef struct {
/* Forward declaration, a strange C thing */
struct task_struct;
struct mm_struct;
+struct seq_file;
/* Free all resources held by a thread. */
extern void release_thread(struct task_struct *);
/*
* Print register of task into buffer. Used in fs/proc/array.c.
*/
-extern char *task_show_regs(struct task_struct *task, char *buffer);
+extern void task_show_regs(struct seq_file *m, struct task_struct *task);
extern void show_registers(struct pt_regs *regs);
extern void show_code(struct pt_regs *regs);
#define HUPCL 0002000
#define CLOCAL 0004000
#define CBAUDEX 0010000
+#define BOTHER 0010000
#define B57600 0010001
#define B115200 0010002
#define B230400 0010003
#define B3000000 0010015
#define B3500000 0010016
#define B4000000 0010017
-#define CIBAUD 002003600000 /* input baud rate (not used) */
+#define CIBAUD 002003600000 /* input baud rate */
#define CMSPAR 010000000000 /* mark or space (stick) parity */
#define CRTSCTS 020000000000 /* flow control */
+#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
+
/* c_lflag bits */
#define ISIG 0000001
#define ICANON 0000002
*/
#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
+
#include <asm-generic/termios.h>
#endif /* __KERNEL__ */
* pte_free_tlb frees a pte table and clears the CRSTE for the
* page table from the tlb.
*/
-static inline void pte_free_tlb(struct mmu_gather *tlb, struct page *page)
+static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t page)
{
if (!tlb->fullmm) {
tlb->array[tlb->nr_ptes++] = page;
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-#ifdef __KERNEL__
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-
-#endif
-
#endif /* __ASM_SH_A_OUT_H */
#define __pgd(x) ((pgd_t) { (x) } )
#define __pgprot(x) ((pgprot_t) { (x) } )
+typedef struct page *pgtable_t;
+
#endif /* !__ASSEMBLY__ */
/*
}
static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
- struct page *pte)
+ pgtable_t pte)
{
set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
static inline void pgd_ctor(void *x)
{
return quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
}
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+ unsigned long address)
{
- void *pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
- return pg ? virt_to_page(pg) : NULL;
+ struct page *page;
+ void *pg;
+
+ pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
+ if (!pg)
+ return NULL;
+ page = virt_to_page(pg);
+ pgtable_page_ctor(page);
+ return page;
}
static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
quicklist_free(QUICK_PT, NULL, pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
+ pgtable_page_dtor(pte);
quicklist_free_page(QUICK_PT, NULL, pte);
}
-#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
+#define __pte_free_tlb(tlb,pte) \
+do { \
+ pgtable_page_dtor(pte); \
+ tlb_remove_page((tlb), (pte)); \
+} while (0)
/*
* allocating and freeing a pmd is trivial: the 1-entry pmd is
*/
#define TASK_SIZE 0x7c000000UL
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
+
/* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
*/
#define TASK_SIZE 0x7ffff000UL
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
+
/* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
*/
--- /dev/null
+/* a.out coredump register dumper
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_A_OUT_CORE_H
+#define _ASM_A_OUT_CORE_H
+
+#ifdef __KERNEL__
+
+#include <linux/user.h>
+
+/*
+ * fill in the user structure for an a.out core dump
+ */
+static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
+{
+ unsigned long first_stack_page;
+
+ dump->magic = SUNOS_CORE_MAGIC;
+ dump->len = sizeof(struct user);
+ dump->regs.psr = regs->psr;
+ dump->regs.pc = regs->pc;
+ dump->regs.npc = regs->npc;
+ dump->regs.y = regs->y;
+ /* fuck me plenty */
+ memcpy(&dump->regs.regs[0], ®s->u_regs[1], (sizeof(unsigned long) * 15));
+ dump->uexec = current->thread.core_exec;
+ dump->u_tsize = (((unsigned long) current->mm->end_code) -
+ ((unsigned long) current->mm->start_code)) & ~(PAGE_SIZE - 1);
+ dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1)));
+ dump->u_dsize -= dump->u_tsize;
+ dump->u_dsize &= ~(PAGE_SIZE - 1);
+ first_stack_page = (regs->u_regs[UREG_FP] & ~(PAGE_SIZE - 1));
+ dump->u_ssize = (TASK_SIZE - first_stack_page) & ~(PAGE_SIZE - 1);
+ memcpy(&dump->fpu.fpstatus.fregs.regs[0], ¤t->thread.float_regs[0], (sizeof(unsigned long) * 32));
+ dump->fpu.fpstatus.fsr = current->thread.fsr;
+ dump->fpu.fpstatus.flags = dump->fpu.fpstatus.extra = 0;
+ dump->fpu.fpstatus.fpq_count = current->thread.fpqdepth;
+ memcpy(&dump->fpu.fpstatus.fpq[0], ¤t->thread.fpqueue[0],
+ ((sizeof(unsigned long) * 2) * 16));
+ dump->sigcode = 0;
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_A_OUT_CORE_H */
#define N_RELOCATION_INFO_DECLARED 1
-#ifdef __KERNEL__
-
-#include <asm/page.h>
-
-#define STACK_TOP (PAGE_OFFSET - PAGE_SIZE)
-#define STACK_TOP_MAX STACK_TOP
-
-#endif /* __KERNEL__ */
-
#endif /* __SPARC_A_OUT_H__ */
#endif
+typedef struct page *pgtable_t;
+
extern unsigned long sparc_unmapped_base;
BTFIXUPDEF_SETHI(sparc_unmapped_base)
#define _ASMSPARC_PARAM_H
#ifdef __KERNEL__
-# define HZ 100 /* Internal kernel timer frequency */
+# define HZ CONFIG_HZ /* Internal kernel timer frequency */
# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ)
#endif
BTFIXUPDEF_CALL(void, pmd_populate, pmd_t *, struct page *)
#define pmd_populate(MM, PMD, PTE) BTFIXUP_CALL(pmd_populate)(PMD, PTE)
+#define pmd_pgtable(pmd) pmd_page(pmd)
BTFIXUPDEF_CALL(void, pmd_set, pmd_t *, pte_t *)
#define pmd_populate_kernel(MM, PMD, PTE) BTFIXUP_CALL(pmd_set)(PMD, PTE)
-BTFIXUPDEF_CALL(struct page *, pte_alloc_one, struct mm_struct *, unsigned long)
+BTFIXUPDEF_CALL(pgtable_t , pte_alloc_one, struct mm_struct *, unsigned long)
#define pte_alloc_one(mm, address) BTFIXUP_CALL(pte_alloc_one)(mm, address)
BTFIXUPDEF_CALL(pte_t *, pte_alloc_one_kernel, struct mm_struct *, unsigned long)
#define pte_alloc_one_kernel(mm, addr) BTFIXUP_CALL(pte_alloc_one_kernel)(mm, addr)
BTFIXUPDEF_CALL(void, free_pte_fast, pte_t *)
#define pte_free_kernel(mm, pte) BTFIXUP_CALL(free_pte_fast)(pte)
-BTFIXUPDEF_CALL(void, pte_free, struct page *)
+BTFIXUPDEF_CALL(void, pte_free, pgtable_t )
#define pte_free(mm, pte) BTFIXUP_CALL(pte_free)(pte)
#define __pte_free_tlb(tlb, pte) pte_free((tlb)->mm, pte)
#endif
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
#undef __FD_SET
static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
}
}
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif /* !(__ARCH_SPARC_POSIX_TYPES_H) */
* we can make our access_ok test faster
*/
#define TASK_SIZE PAGE_OFFSET
+#ifdef __KERNEL__
+#define STACK_TOP (PAGE_OFFSET - PAGE_SIZE)
+#define STACK_TOP_MAX STACK_TOP
+#endif /* __KERNEL__ */
struct task_struct;
#include <linux/string.h>
#include <linux/errno.h>
#include <asm/vac-ops.h>
-#include <asm/a.out.h>
#endif
#ifndef __ASSEMBLY__
--- /dev/null
+/* a.out coredump register dumper
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_A_OUT_CORE_H
+#define _ASM_A_OUT_CORE_H
+
+#ifdef __KERNEL__
+
+#include <linux/user.h>
+
+/*
+ * fill in the user structure for an a.out core dump
+ */
+static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
+{
+ /* Only should be used for SunOS and ancient a.out
+ * SparcLinux binaries... Not worth implementing.
+ */
+ memset(dump, 0, sizeof(struct user));
+}
+
+#endif /* __KERNEL__ */
+#endif /* _ASM_A_OUT_CORE_H */
#define N_RELOCATION_INFO_DECLARED 1
-#ifdef __KERNEL__
-
-#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
-#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
-
-#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
- STACK_TOP32 : STACK_TOP64)
-
-#define STACK_TOP_MAX STACK_TOP64
-
-#endif
-
#endif /* !(__ASSEMBLY__) */
#endif /* !(__SPARC64_A_OUT_H__) */
/*
* These are used to set parameters in the core dumps.
*/
-#ifndef ELF_ARCH
#define ELF_ARCH EM_SPARCV9
#define ELF_CLASS ELFCLASS64
#define ELF_DATA ELFDATA2MSB
unsigned long pr_gsr;
unsigned long pr_fprs;
} elf_fpregset_t;
-#endif
+
+/* Format of 32-bit elf_gregset_t is:
+ * G0 --> G7
+ * O0 --> O7
+ * L0 --> L7
+ * I0 --> I7
+ * PSR, PC, nPC, Y, WIM, TBR
+ */
+typedef unsigned int compat_elf_greg_t;
+#define COMPAT_ELF_NGREG 38
+typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG];
+
+typedef struct {
+ union {
+ unsigned int pr_regs[32];
+ unsigned long pr_dregs[16];
+ } pr_fr;
+ unsigned int __unused;
+ unsigned int pr_fsr;
+ unsigned char pr_qcnt;
+ unsigned char pr_q_entrysize;
+ unsigned char pr_en;
+ unsigned int pr_q[64];
+} compat_elf_fpregset_t;
+
+/* UltraSparc extensions. Still unused, but will be eventually. */
+typedef struct {
+ unsigned int pr_type;
+ unsigned int pr_align;
+ union {
+ struct {
+ union {
+ unsigned int pr_regs[32];
+ unsigned long pr_dregs[16];
+ long double pr_qregs[8];
+ } pr_xfr;
+ } pr_v8p;
+ unsigned int pr_xfsr;
+ unsigned int pr_fprs;
+ unsigned int pr_xg[8];
+ unsigned int pr_xo[8];
+ unsigned long pr_tstate;
+ unsigned int pr_filler[8];
+ } pr_un;
+} elf_xregset_t;
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
-#ifndef elf_check_arch
-#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH) /* Might be EM_SPARCV9 or EM_SPARC */
-#endif
+#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
+#define compat_elf_check_arch(x) ((x)->e_machine == EM_SPARC || \
+ (x)->e_machine == EM_SPARC32PLUS)
+#define compat_start_thread start_thread32
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE PAGE_SIZE
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
-#ifndef ELF_ET_DYN_BASE
-#define ELF_ET_DYN_BASE 0x0000010000000000UL
-#endif
+#define ELF_ET_DYN_BASE 0x0000010000000000UL
+#define COMPAT_ELF_ET_DYN_BASE 0x0000000070000000UL
/* This yields a mask that user programs can use to figure out what
#endif /* (STRICT_MM_TYPECHECKS) */
+typedef struct page *pgtable_t;
+
#define TASK_UNMAPPED_BASE (test_thread_flag(TIF_32BIT) ? \
(_AC(0x0000000070000000,UL)) : \
(_AC(0xfffff80000000000,UL) + (1UL << 32UL)))
return quicklist_alloc(0, GFP_KERNEL, NULL);
}
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
- unsigned long address)
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
+ unsigned long address)
{
- void *pg = quicklist_alloc(0, GFP_KERNEL, NULL);
- return pg ? virt_to_page(pg) : NULL;
+ struct page *page;
+ void *pg;
+
+ pg = quicklist_alloc(0, GFP_KERNEL, NULL);
+ if (!pg)
+ return NULL;
+ page = virt_to_page(pg);
+ pgtable_page_ctor(page);
+ return page;
}
static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
quicklist_free(0, NULL, pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *ptepage)
+static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
{
+ pgtable_page_dtor(ptepage);
quicklist_free_page(0, NULL, ptepage);
}
#define pmd_populate_kernel(MM, PMD, PTE) pmd_set(PMD, PTE)
#define pmd_populate(MM,PMD,PTE_PAGE) \
pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE))
+#define pmd_pgtable(pmd) pmd_page(pmd)
static inline void check_pgt_cache(void)
{
#endif
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
#undef __FD_SET
static inline void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
}
}
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif /* !(__ARCH_SPARC64_POSIX_TYPES_H) */
#define current_text_addr() ({ void *pc; __asm__("rd %%pc, %0" : "=r" (pc)); pc; })
#include <asm/asi.h>
-#include <asm/a.out.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/page.h>
#else
#define VPTE_SIZE (1 << (VA_BITS - PAGE_SHIFT + 3))
#endif
+
#define TASK_SIZE ((unsigned long)-VPTE_SIZE)
+#ifdef __KERNEL__
+
+#define STACK_TOP32 ((1UL << 32UL) - PAGE_SIZE)
+#define STACK_TOP64 (0x0000080000000000UL - (1UL << 32UL))
+
+#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
+ STACK_TOP32 : STACK_TOP64)
+
+#define STACK_TOP_MAX STACK_TOP64
+
+#endif
#ifndef __ASSEMBLY__
#ifdef __KERNEL__
+#define __ARCH_WANT_COMPAT_SYS_PTRACE
+
#define force_successful_syscall_return() \
do { current_thread_info()->syscall_noerror = 1; \
} while (0)
#include <linux/compiler.h>
#include <linux/sched.h>
#include <linux/string.h>
-#include <asm/a.out.h>
#include <asm/asi.h>
#include <asm/system.h>
#include <asm/spitfire.h>
#ifndef _SPARC64_USER_H
#define _SPARC64_USER_H
-#include <asm/a.out.h>
+#include <linux/a.out.h>
struct sunos_regs {
unsigned int psr, pc, npc, y;
unsigned int regs[15];
--- /dev/null
+/* a.out coredump register dumper
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef __UM_A_OUT_CORE_H
+#define __UM_A_OUT_CORE_H
+
+#ifdef __KERNEL__
+
+#include <linux/user.h>
+
+/*
+ * fill in the user structure for an a.out core dump
+ */
+static inline void aout_dump_thread(struct pt_regs *regs, struct user *u)
+{
+}
+
+#endif /* __KERNEL__ */
+#endif /* __UM_A_OUT_CORE_H */
#include "asm/arch/a.out.h"
-#undef STACK_TOP
-#undef STACK_TOP_MAX
-
-extern unsigned long stacksizelim;
-
-#define STACK_ROOM (stacksizelim)
-
-#define STACK_TOP (TASK_SIZE - 2 * PAGE_SIZE)
-
-#define STACK_TOP_MAX STACK_TOP
-
#endif
#ifndef __UM_FIXMAP_H
#define __UM_FIXMAP_H
+#include <asm/processor.h>
#include <asm/system.h>
#include <asm/kmap_types.h>
#include <asm/archparam.h>
* at the top of mem..
*/
-#define FIXADDR_TOP (CONFIG_TOP_ADDR - 2 * PAGE_SIZE)
+#define FIXADDR_TOP (TASK_SIZE - 2 * PAGE_SIZE)
#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct page *pgtable_t;
+
#define pgd_val(x) ((x).pgd)
#define pgprot_val(x) ((x).pgprot)
set_pmd(pmd, __pmd(_PAGE_TABLE + \
((unsigned long long)page_to_pfn(pte) << \
(unsigned long long) PAGE_SHIFT)))
+#define pmd_pgtable(pmd) pmd_page(pmd)
/*
* Allocate and free page tables.
extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long);
-extern struct page *pte_alloc_one(struct mm_struct *, unsigned long);
+extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long);
static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
{
free_page((unsigned long) pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
+ pgtable_page_dtor(pte);
__free_page(pte);
}
-#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
+#define __pte_free_tlb(tlb,pte) \
+do { \
+ pgtable_page_dtor(pte); \
+ tlb_remove_page((tlb),(pte)); \
+} while (0)
#ifdef CONFIG_3_LEVEL_PGTABLES
struct task_struct;
#include "asm/ptrace.h"
-#include "asm/pgtable.h"
#include "registers.h"
#include "sysdep/archsetjmp.h"
/*
* User space process size: 3GB (default).
*/
-#define TASK_SIZE (CONFIG_TOP_ADDR & PGDIR_MASK)
+extern unsigned long task_size;
+
+#define TASK_SIZE (task_size)
+
+#undef STACK_TOP
+#undef STACK_TOP_MAX
+
+extern unsigned long stacksizelim;
+
+#define STACK_ROOM (stacksizelim)
+#define STACK_TOP (TASK_SIZE - 2 * PAGE_SIZE)
+#define STACK_TOP_MAX STACK_TOP
/* This decides where the kernel will search for a free chunk of vm
* space during mmap's.
#define cpu_relax() rep_nop()
#define INIT_ARCH_THREAD { .debugregs = { [ 0 ... 7 ] = 0 }, \
- .debugregs_seq = 0, \
+ .debugregs_seq = 0, \
.fs = 0, \
.faultinfo = { 0, 0, 0 } }
static inline void arch_copy_thread(struct arch_thread *from,
struct arch_thread *to)
{
+ to->fs = from->fs;
}
#include "asm/arch/user.h"
#define V850E_TIMER_D_TMCD_CS_MIN 1 /* min 2^1 divider */
-/* For <asm/param.h> */
-#ifndef HZ
-#define HZ 100
-#endif
-
-
#endif /* __V850_ANNA_H__ */
#define V850E_TIMER_D_TMCD_CS_MIN 2 /* min 2^2 divider */
-/* For <asm/param.h> */
-#ifndef HZ
-#define HZ 100
-#endif
-
-
#endif /* __V850_AS85EP1_H__ */
#endif
-/* For <asm/param.h> */
-#ifndef HZ
-#define HZ 122 /* actually, 8.192ms ticks =~ 122.07 */
-#endif
-
-
#endif /* __V850_FPGA85E2C_H__ */
#define MAXHOSTNAMELEN 64 /* max length of hostname */
#ifdef __KERNEL__
-#include <asm/machdep.h> /* For HZ */
-
+# define HZ CONFIG_HZ
# define USER_HZ 100
# define CLOCKS_PER_SEC USER_HZ
#endif
typedef unsigned int __kernel_old_dev_t;
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
/* We used to include <asm/bitops.h> here, which seems the right thing, but
it caused nasty include-file definition order problems. Removing the
#define __FD_ZERO(fd_set) \
memset (fd_set, 0, sizeof (*(fd_set *)fd_set))
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif /* __V850_POSIX_TYPES_H__ */
#endif /* CONFIG_RTE_MB_A_PCI */
-/* For <asm/param.h> */
-#ifndef HZ
-#define HZ 100
-#endif
-
-
#ifndef __ASSEMBLY__
extern void rte_cb_early_init (void);
extern void rte_cb_init_irqs (void);
#define R0_RAM_ADDR 0xFFFFF000
-/* For <asm/param.h> */
-#ifndef HZ
-#define HZ 24 /* Minimum supported frequency. */
-#endif
-
/* For <asm/irq.h> */
#define NUM_CPU_IRQS 6
#define R0_RAM_ADDR 0xFFFFE000
-/* For <asm/param.h> */
-#ifndef HZ
-#define HZ 24 /* Minimum supported frequency. */
-#endif
-
-
#endif /* __V850_SIM85E2_H__ */
--- /dev/null
+/* a.out coredump register dumper
+ *
+ * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _ASM_A_OUT_CORE_H
+#define _ASM_A_OUT_CORE_H
+
+#ifdef __KERNEL__
+#ifdef CONFIG_X86_32
+
+#include <linux/user.h>
+#include <linux/elfcore.h>
+
+/*
+ * fill in the user structure for an a.out core dump
+ */
+static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
+{
+ u16 gs;
+
+/* changed the size calculations - should hopefully work better. lbt */
+ dump->magic = CMAGIC;
+ dump->start_code = 0;
+ dump->start_stack = regs->sp & ~(PAGE_SIZE - 1);
+ dump->u_tsize = ((unsigned long) current->mm->end_code) >> PAGE_SHIFT;
+ dump->u_dsize = ((unsigned long) (current->mm->brk + (PAGE_SIZE-1))) >> PAGE_SHIFT;
+ dump->u_dsize -= dump->u_tsize;
+ dump->u_ssize = 0;
+ dump->u_debugreg[0] = current->thread.debugreg0;
+ dump->u_debugreg[1] = current->thread.debugreg1;
+ dump->u_debugreg[2] = current->thread.debugreg2;
+ dump->u_debugreg[3] = current->thread.debugreg3;
+ dump->u_debugreg[4] = 0;
+ dump->u_debugreg[5] = 0;
+ dump->u_debugreg[6] = current->thread.debugreg6;
+ dump->u_debugreg[7] = current->thread.debugreg7;
+
+ if (dump->start_stack < TASK_SIZE)
+ dump->u_ssize = ((unsigned long) (TASK_SIZE - dump->start_stack)) >> PAGE_SHIFT;
+
+ dump->regs.bx = regs->bx;
+ dump->regs.cx = regs->cx;
+ dump->regs.dx = regs->dx;
+ dump->regs.si = regs->si;
+ dump->regs.di = regs->di;
+ dump->regs.bp = regs->bp;
+ dump->regs.ax = regs->ax;
+ dump->regs.ds = (u16)regs->ds;
+ dump->regs.es = (u16)regs->es;
+ dump->regs.fs = (u16)regs->fs;
+ savesegment(gs,gs);
+ dump->regs.orig_ax = regs->orig_ax;
+ dump->regs.ip = regs->ip;
+ dump->regs.cs = (u16)regs->cs;
+ dump->regs.flags = regs->flags;
+ dump->regs.sp = regs->sp;
+ dump->regs.ss = (u16)regs->ss;
+
+ dump->u_fpvalid = dump_fpu (regs, &dump->i387);
+}
+
+#endif /* CONFIG_X86_32 */
+#endif /* __KERNEL__ */
+#endif /* _ASM_A_OUT_CORE_H */
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
-#ifdef __KERNEL__
-# include <linux/thread_info.h>
-# define STACK_TOP TASK_SIZE
-# ifdef CONFIG_X86_32
-# define STACK_TOP_MAX STACK_TOP
-# else
-# define STACK_TOP_MAX TASK_SIZE64
-# endif
-#endif
-
#endif /* _ASM_X86_A_OUT_H */
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_X86_PAE */
+#ifndef __ASSEMBLY__
+typedef struct page *pgtable_t;
+#endif
+
#ifdef CONFIG_HUGETLB_PAGE
#define HAVE_ARCH_HUGETLB_UNMAPPED_AREA
#endif
typedef unsigned long pgprotval_t;
typedef unsigned long phys_addr_t;
+typedef struct page *pgtable_t;
+
typedef struct { pteval_t pte; } pte_t;
#define vmemmap ((struct page *)VMEMMAP_START)
paravirt_alloc_pt(mm, pfn);
set_pmd(pmd, __pmd(((pteval_t)pfn << PAGE_SHIFT) | _PAGE_TABLE));
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
/*
* Allocate and free page tables.
extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
extern pte_t *pte_alloc_one_kernel(struct mm_struct *, unsigned long);
-extern struct page *pte_alloc_one(struct mm_struct *, unsigned long);
+extern pgtable_t pte_alloc_one(struct mm_struct *, unsigned long);
static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
{
free_page((unsigned long)pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
+ pgtable_page_dtor(pte);
__free_page(pte);
}
#define pgd_populate(mm, pgd, pud) \
set_pgd(pgd, __pgd(_PAGE_TABLE | __pa(pud)))
+#define pmd_pgtable(pmd) pmd_page(pmd)
+
static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, struct page *pte)
{
set_pmd(pmd, __pmd(_PAGE_TABLE | (page_to_pfn(pte) << PAGE_SHIFT)));
return (pte_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT);
}
-static inline struct page *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+static inline pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
{
- void *p = (void *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT);
+ struct page *page;
+ void *p;
+
+ p = (void *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT);
if (!p)
return NULL;
- return virt_to_page(p);
+ page = virt_to_page(p);
+ pgtable_page_ctor(page);
+ return page;
}
/* Should really implement gc for free page table pages. This could be
free_page((unsigned long)pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *pte)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
+ pgtable_page_dtor(pte);
__free_page(pte);
}
-#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte))
+#define __pte_free_tlb(tlb,pte) \
+do { \
+ pgtable_page_dtor((pte)); \
+ tlb_remove_page((tlb), (pte)); \
+} while (0)
#define __pmd_free_tlb(tlb,x) tlb_remove_page((tlb),virt_to_page(x))
#define __pud_free_tlb(tlb,x) tlb_remove_page((tlb),virt_to_page(x))
#endif
typedef struct {
-#if defined(__KERNEL__) || defined(__USE_ALL)
int val[2];
-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
- int __val[2];
-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
} __kernel_fsid_t;
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+#if defined(__KERNEL__)
#undef __FD_SET
#define __FD_SET(fd,fdsetp) \
"2" ((__kernel_fd_set *) (fdsetp)) : "memory"); \
} while (0)
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif
* User space process size: 3GB (default).
*/
#define TASK_SIZE (PAGE_OFFSET)
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
#define INIT_THREAD { \
.sp0 = sizeof(init_stack) + (long)&init_stack, \
#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
IA32_PAGE_OFFSET : TASK_SIZE64)
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX TASK_SIZE64
+
#define INIT_THREAD { \
.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
}
#ifndef _XTENSA_A_OUT_H
#define _XTENSA_A_OUT_H
-/* Note: the kernel needs the a.out definitions, even if only ELF is used. */
-
-#define STACK_TOP TASK_SIZE
-#define STACK_TOP_MAX STACK_TOP
-
struct exec
{
unsigned long a_info;
typedef struct { unsigned long pte; } pte_t; /* page table entry */
typedef struct { unsigned long pgd; } pgd_t; /* PGD table entry */
typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct page *pgtable_t;
#define pte_val(x) ((x).pte)
#define pgd_val(x) ((x).pgd)
#define _XTENSA_PARAM_H
#ifdef __KERNEL__
-# define HZ 100 /* internal timer frequency */
+# define HZ CONFIG_HZ /* internal timer frequency */
# define USER_HZ 100 /* for user interfaces in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ) /* frequnzy at which times() counts */
#endif
(pmd_val(*(pmdp)) = ((unsigned long)ptep))
#define pmd_populate(mm, pmdp, page) \
(pmd_val(*(pmdp)) = ((unsigned long)page_to_virt(page)))
+#define pmd_pgtable(pmd) pmd_page(pmd)
static inline pgd_t*
pgd_alloc(struct mm_struct *mm)
return kmem_cache_alloc(pgtable_cache, GFP_KERNEL|__GFP_REPEAT);
}
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
- unsigned long addr)
+static inline pte_token_t pte_alloc_one(struct mm_struct *mm,
+ unsigned long addr)
{
- return virt_to_page(pte_alloc_one_kernel(mm, addr));
+ struct page *page;
+
+ page = virt_to_page(pte_alloc_one_kernel(mm, addr));
+ pgtable_page_ctor(page);
+ return page;
}
static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
kmem_cache_free(pgtable_cache, pte);
}
-static inline void pte_free(struct mm_struct *mm, struct page *page)
+static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
{
- kmem_cache_free(pgtable_cache, page_address(page));
+ pgtable_page_dtor(pte);
+ kmem_cache_free(pgtable_cache, page_address(pte));
}
+#define pmd_pgtable(pmd) pmd_page(pmd)
#endif /* __KERNEL__ */
#endif /* _XTENSA_PGALLOC_H */
#else /* __GNUC__ */
-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
- || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
+#if defined(__KERNEL__)
/* With GNU C, use inline functions instead so args are evaluated only once: */
#undef __FD_SET
}
}
-#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+#endif /* defined(__KERNEL__) */
#endif /* __GNUC__ */
#endif /* _XTENSA_POSIX_TYPES_H */
*/
#define TASK_SIZE __XTENSA_UL_CONST(0x40000000)
+#define STACK_TOP TASK_SIZE
+#define STACK_TOP_MAX STACK_TOP
/*
* General exception cause assigned to debug exceptions. Debug exceptions go
#define __NR_signalfd 304
__SYSCALL(304, sys_signalfd, 3)
-#define __NR_timerfd 305
-__SYSCALL(305, sys_timerfd, 4)
+/* 305 was __NR_timerfd */
+__SYSCALL(305, sys_ni_syscall, 0)
#define __NR_eventfd 306
__SYSCALL(306, sys_eventfd, 1)
unifdef-y += types.h
unifdef-y += udf_fs_i.h
unifdef-y += udp.h
-unifdef-y += ufs_fs.h
unifdef-y += uinput.h
unifdef-y += uio.h
unifdef-y += unistd.h
#ifndef __A_OUT_GNU_H__
#define __A_OUT_GNU_H__
+#ifdef CONFIG_ARCH_SUPPORTS_AOUT
+
#define __GNU_EXEC_MACROS__
#ifndef __STRUCT_EXEC_OVERRIDE__
#endif /* __STRUCT_EXEC_OVERRIDE__ */
+#ifndef __ASSEMBLY__
+
/* these go in the N_MACHTYPE field */
enum machine_type {
#if defined (M_OLDSUN2)
};
#endif /* no N_RELOCATION_INFO_DECLARED. */
-
+#endif /*__ASSEMBLY__ */
+#else /* CONFIG_ARCH_SUPPORTS_AOUT */
+#ifndef __ASSEMBLY__
+struct exec {
+};
+#endif
+#endif /* CONFIG_ARCH_SUPPORTS_AOUT */
#endif /* __A_OUT_GNU_H__ */
--- /dev/null
+#ifndef __LINUX_ATMEL_PWM_H
+#define __LINUX_ATMEL_PWM_H
+
+/**
+ * struct pwm_channel - driver handle to a PWM channel
+ * @regs: base of this channel's registers
+ * @index: number of this channel (0..31)
+ * @mck: base clock rate, which can be prescaled and maybe subdivided
+ *
+ * Drivers initialize a pwm_channel structure using pwm_channel_alloc().
+ * Then they configure its clock rate (derived from MCK), alignment,
+ * polarity, and duty cycle by writing directly to the channel registers,
+ * before enabling the channel by calling pwm_channel_enable().
+ *
+ * After emitting a PWM signal for the desired length of time, drivers
+ * may then pwm_channel_disable() or pwm_channel_free(). Both of these
+ * disable the channel, but when it's freed the IRQ is deconfigured and
+ * the channel must later be re-allocated and reconfigured.
+ *
+ * Note that if the period or duty cycle need to be changed while the
+ * PWM channel is operating, drivers must use the PWM_CUPD double buffer
+ * mechanism, either polling until they change or getting implicitly
+ * notified through a once-per-period interrupt handler.
+ */
+struct pwm_channel {
+ void __iomem *regs;
+ unsigned index;
+ unsigned long mck;
+};
+
+extern int pwm_channel_alloc(int index, struct pwm_channel *ch);
+extern int pwm_channel_free(struct pwm_channel *ch);
+
+extern int pwm_clk_alloc(unsigned prescale, unsigned div);
+extern void pwm_clk_free(unsigned clk);
+
+extern int __pwm_channel_onoff(struct pwm_channel *ch, int enabled);
+
+#define pwm_channel_enable(ch) __pwm_channel_onoff((ch), 1)
+#define pwm_channel_disable(ch) __pwm_channel_onoff((ch), 0)
+
+/* periodic interrupts, mostly for CUPD changes to period or cycle */
+extern int pwm_channel_handler(struct pwm_channel *ch,
+ void (*handler)(struct pwm_channel *ch));
+
+/* per-channel registers (banked at pwm_channel->regs) */
+#define PWM_CMR 0x00 /* mode register */
+#define PWM_CPR_CPD (1 << 10) /* set: CUPD modifies period */
+#define PWM_CPR_CPOL (1 << 9) /* set: idle high */
+#define PWM_CPR_CALG (1 << 8) /* set: center align */
+#define PWM_CPR_CPRE (0xf << 0) /* mask: rate is mck/(2^pre) */
+#define PWM_CPR_CLKA (0xb << 0) /* rate CLKA */
+#define PWM_CPR_CLKB (0xc << 0) /* rate CLKB */
+#define PWM_CDTY 0x04 /* duty cycle (max of CPRD) */
+#define PWM_CPRD 0x08 /* period (count up from zero) */
+#define PWM_CCNT 0x0c /* counter (20 bits?) */
+#define PWM_CUPD 0x10 /* update CPRD (or CDTY) next period */
+
+static inline void
+pwm_channel_writel(struct pwm_channel *pwmc, unsigned offset, u32 val)
+{
+ __raw_writel(val, pwmc->regs + offset);
+}
+
+static inline u32 pwm_channel_readl(struct pwm_channel *pwmc, unsigned offset)
+{
+ return __raw_readl(pwmc->regs + offset);
+}
+
+#endif /* __LINUX_ATMEL_PWM_H */
#define BLK_MAX_CDB 16
/*
- * try to put the fields that are referenced together in the same cacheline
+ * try to put the fields that are referenced together in the same cacheline.
+ * if you modify this structure, be sure to check block/blk-core.c:rq_init()
+ * as well!
*/
struct request {
struct list_head queuelist;
#define htons(x) ___htons(x)
#define ntohs(x) ___ntohs(x)
+static inline void le16_add_cpu(__le16 *var, u16 val)
+{
+ *var = cpu_to_le16(le16_to_cpu(*var) + val);
+}
+
+static inline void le32_add_cpu(__le32 *var, u32 val)
+{
+ *var = cpu_to_le32(le32_to_cpu(*var) + val);
+}
+
+static inline void le64_add_cpu(__le64 *var, u64 val)
+{
+ *var = cpu_to_le64(le64_to_cpu(*var) + val);
+}
+
+static inline void be16_add_cpu(__be16 *var, u16 val)
+{
+ *var = cpu_to_be16(be16_to_cpu(*var) + val);
+}
+
+static inline void be32_add_cpu(__be32 *var, u32 val)
+{
+ *var = cpu_to_be32(be32_to_cpu(*var) + val);
+}
+
+static inline void be64_add_cpu(__be64 *var, u64 val)
+{
+ *var = cpu_to_be64(be64_to_cpu(*var) + val);
+}
+
#endif /* KERNEL */
#endif /* _LINUX_BYTEORDER_GENERIC_H */
extern void __cpuset_memory_pressure_bump(void);
extern const struct file_operations proc_cpuset_operations;
-extern char *cpuset_task_status_allowed(struct task_struct *task, char *buffer);
+struct seq_file;
+extern void cpuset_task_status_allowed(struct seq_file *m,
+ struct task_struct *task);
extern void cpuset_lock(void);
extern void cpuset_unlock(void);
static inline void cpuset_memory_pressure_bump(void) {}
-static inline char *cpuset_task_status_allowed(struct task_struct *task,
- char *buffer)
+static inline void cpuset_task_status_allowed(struct seq_file *m,
+ struct task_struct *task)
{
- return buffer;
}
static inline void cpuset_lock(void) {}
struct dca_provider {
struct dca_ops *ops;
- struct class_device *cd;
+ struct device *cd;
int id;
};
#ifdef CONFIG_DMAR
struct intel_iommu;
-extern char *dmar_get_fault_reason(u8 fault_reason);
+extern const char *dmar_get_fault_reason(u8 fault_reason);
/* Can't use the common MSI interrupt functions
* since DMAR is not a pci device
DMI_DEV_TYPE_ETHERNET,
DMI_DEV_TYPE_TOKENRING,
DMI_DEV_TYPE_SOUND,
+ DMI_DEV_TYPE_PATA,
+ DMI_DEV_TYPE_SATA,
+ DMI_DEV_TYPE_SAS,
DMI_DEV_TYPE_IPMI = -1,
- DMI_DEV_TYPE_OEM_STRING = -2
+ DMI_DEV_TYPE_OEM_STRING = -2,
};
struct dmi_header {
#define EM_V850 87 /* NEC v850 */
#define EM_M32R 88 /* Renesas M32R */
#define EM_H8_300 46 /* Renesas H8/300,300H,H8S */
+#define EM_MN10300 89 /* Panasonic/MEI MN10300, AM33 */
#define EM_BLACKFIN 106 /* ADI Blackfin Processor */
#define EM_FRV 0x5441 /* Fujitsu FR-V */
#define EM_AVR32 0x18ad /* Atmel AVR32 */
#define EM_CYGNUS_M32R 0x9041
/* This is the old interim value for S/390 architecture */
#define EM_S390_OLD 0xA390
+/* Also Panasonic/MEI MN10300, AM33 */
+#define EM_CYGNUS_MN10300 0xbeef
#endif /* _LINUX_ELF_EM_H */
* in /proc/mounts will be "type.subtype"
*/
char *s_subtype;
+
+ /*
+ * Saved mount options for lazy filesystems using
+ * generic_show_options()
+ */
+ char *s_options;
};
extern struct timespec current_fs_time(struct super_block *sb);
const struct file_operations *);
extern void unregister_chrdev(unsigned int, const char *);
extern void unregister_chrdev_region(dev_t, unsigned);
-extern int chrdev_open(struct inode *, struct file *);
extern void chrdev_show(struct seq_file *,off_t);
/* fs/block_dev.c */
unsigned long, loff_t, loff_t *, size_t, ssize_t);
extern ssize_t do_sync_read(struct file *filp, char __user *buf, size_t len, loff_t *ppos);
extern ssize_t do_sync_write(struct file *filp, const char __user *buf, size_t len, loff_t *ppos);
-extern void do_generic_mapping_read(struct address_space *mapping,
- struct file_ra_state *, struct file *,
- loff_t *, read_descriptor_t *, read_actor_t);
extern int generic_segment_checks(const struct iovec *iov,
unsigned long *nr_segs, size_t *count, int access_flags);
}
#endif
-static inline void do_generic_file_read(struct file * filp, loff_t *ppos,
- read_descriptor_t * desc,
- read_actor_t actor)
-{
- do_generic_mapping_read(filp->f_mapping,
- &filp->f_ra,
- filp,
- ppos,
- desc,
- actor);
-}
-
#ifdef CONFIG_BLOCK
ssize_t __blockdev_direct_IO(int rw, struct kiocb *iocb, struct inode *inode,
struct block_device *bdev, const struct iovec *iov, loff_t offset,
extern void file_update_time(struct file *file);
+extern int generic_show_options(struct seq_file *m, struct vfsmount *mnt);
+extern void save_mount_options(struct super_block *sb, char *options);
+
static inline ino_t parent_ino(struct dentry *dentry)
{
ino_t res;
static struct file_operations __fops = { \
.owner = THIS_MODULE, \
.open = __fops ## _open, \
- .release = simple_attr_close, \
+ .release = simple_attr_release, \
.read = simple_attr_read, \
.write = simple_attr_write, \
};
}
int simple_attr_open(struct inode *inode, struct file *file,
- u64 (*get)(void *), void (*set)(void *, u64),
+ int (*get)(void *, u64 *), int (*set)(void *, u64),
const char *fmt);
-int simple_attr_close(struct inode *inode, struct file *file);
+int simple_attr_release(struct inode *inode, struct file *file);
ssize_t simple_attr_read(struct file *file, char __user *buf,
size_t len, loff_t *ppos);
ssize_t simple_attr_write(struct file *file, const char __user *buf,
__le32 nr_sects; /* nr of sectors in partition */
} __attribute__((packed));
+struct disk_stats {
+ unsigned long sectors[2]; /* READs and WRITEs */
+ unsigned long ios[2];
+ unsigned long merges[2];
+ unsigned long ticks[2];
+ unsigned long io_ticks;
+ unsigned long time_in_queue;
+};
+
struct hd_struct {
sector_t start_sect;
sector_t nr_sects;
struct device dev;
struct kobject *holder_dir;
- unsigned ios[2], sectors[2]; /* READs and WRITEs */
int policy, partno;
#ifdef CONFIG_FAIL_MAKE_REQUEST
int make_it_fail;
+#endif
+ unsigned long stamp;
+ int in_flight;
+#ifdef CONFIG_SMP
+ struct disk_stats *dkstats;
+#else
+ struct disk_stats dkstats;
#endif
};
#define GENHD_FL_SUPPRESS_PARTITION_INFO 32
#define GENHD_FL_FAIL 64
-struct disk_stats {
- unsigned long sectors[2]; /* READs and WRITEs */
- unsigned long ios[2];
- unsigned long merges[2];
- unsigned long ticks[2];
- unsigned long io_ticks;
- unsigned long time_in_queue;
-};
-
+
struct gendisk {
int major; /* major number of driver */
int first_minor;
* The __ variants should only be called in critical sections. The full
* variants disable/enable preemption.
*/
+static inline struct hd_struct *get_part(struct gendisk *gendiskp,
+ sector_t sector)
+{
+ struct hd_struct *part;
+ int i;
+ for (i = 0; i < gendiskp->minors - 1; i++) {
+ part = gendiskp->part[i];
+ if (part && part->start_sect <= sector
+ && sector < part->start_sect + part->nr_sects)
+ return part;
+ }
+ return NULL;
+}
+
#ifdef CONFIG_SMP
#define __disk_stat_add(gendiskp, field, addnd) \
(per_cpu_ptr(gendiskp->dkstats, smp_processor_id())->field += addnd)
memset(per_cpu_ptr(gendiskp->dkstats, i), value,
sizeof (struct disk_stats));
}
+
+#define __part_stat_add(part, field, addnd) \
+ (per_cpu_ptr(part->dkstats, smp_processor_id())->field += addnd)
+
+#define __all_stat_add(gendiskp, field, addnd, sector) \
+({ \
+ struct hd_struct *part = get_part(gendiskp, sector); \
+ if (part) \
+ __part_stat_add(part, field, addnd); \
+ __disk_stat_add(gendiskp, field, addnd); \
+})
+
+#define part_stat_read(part, field) \
+({ \
+ typeof(part->dkstats->field) res = 0; \
+ int i; \
+ for_each_possible_cpu(i) \
+ res += per_cpu_ptr(part->dkstats, i)->field; \
+ res; \
+})
+
+static inline void part_stat_set_all(struct hd_struct *part, int value) {
+ int i;
+ for_each_possible_cpu(i)
+ memset(per_cpu_ptr(part->dkstats, i), value,
+ sizeof(struct disk_stats));
+}
#else
#define __disk_stat_add(gendiskp, field, addnd) \
(gendiskp->dkstats.field += addnd)
#define disk_stat_read(gendiskp, field) (gendiskp->dkstats.field)
-static inline void disk_stat_set_all(struct gendisk *gendiskp, int value) {
+static inline void disk_stat_set_all(struct gendisk *gendiskp, int value)
+{
memset(&gendiskp->dkstats, value, sizeof (struct disk_stats));
}
+
+#define __part_stat_add(part, field, addnd) \
+ (part->dkstats.field += addnd)
+
+#define __all_stat_add(gendiskp, field, addnd, sector) \
+({ \
+ struct hd_struct *part = get_part(gendiskp, sector); \
+ if (part) \
+ part->dkstats.field += addnd; \
+ __disk_stat_add(gendiskp, field, addnd); \
+})
+
+#define part_stat_read(part, field) (part->dkstats.field)
+
+static inline void part_stat_set_all(struct hd_struct *part, int value)
+{
+ memset(&part->dkstats, value, sizeof(struct disk_stats));
+}
+
#endif
#define disk_stat_add(gendiskp, field, addnd) \
#define disk_stat_sub(gendiskp, field, subnd) \
disk_stat_add(gendiskp, field, -subnd)
+#define part_stat_add(gendiskp, field, addnd) \
+ do { \
+ preempt_disable(); \
+ __part_stat_add(gendiskp, field, addnd);\
+ preempt_enable(); \
+ } while (0)
+
+#define __part_stat_dec(gendiskp, field) __part_stat_add(gendiskp, field, -1)
+#define part_stat_dec(gendiskp, field) part_stat_add(gendiskp, field, -1)
+
+#define __part_stat_inc(gendiskp, field) __part_stat_add(gendiskp, field, 1)
+#define part_stat_inc(gendiskp, field) part_stat_add(gendiskp, field, 1)
+
+#define __part_stat_sub(gendiskp, field, subnd) \
+ __part_stat_add(gendiskp, field, -subnd)
+#define part_stat_sub(gendiskp, field, subnd) \
+ part_stat_add(gendiskp, field, -subnd)
+
+#define all_stat_add(gendiskp, field, addnd, sector) \
+ do { \
+ preempt_disable(); \
+ __all_stat_add(gendiskp, field, addnd, sector); \
+ preempt_enable(); \
+ } while (0)
+
+#define __all_stat_dec(gendiskp, field, sector) \
+ __all_stat_add(gendiskp, field, -1, sector)
+#define all_stat_dec(gendiskp, field, sector) \
+ all_stat_add(gendiskp, field, -1, sector)
+
+#define __all_stat_inc(gendiskp, field, sector) \
+ __all_stat_add(gendiskp, field, 1, sector)
+#define all_stat_inc(gendiskp, field, sector) \
+ all_stat_add(gendiskp, field, 1, sector)
+
+#define __all_stat_sub(gendiskp, field, subnd, sector) \
+ __all_stat_add(gendiskp, field, -subnd, sector)
+#define all_stat_sub(gendiskp, field, subnd, sector) \
+ all_stat_add(gendiskp, field, -subnd, sector)
/* Inlines to alloc and free disk stats in struct gendisk */
#ifdef CONFIG_SMP
{
free_percpu(disk->dkstats);
}
+
+static inline int init_part_stats(struct hd_struct *part)
+{
+ part->dkstats = alloc_percpu(struct disk_stats);
+ if (!part->dkstats)
+ return 0;
+ return 1;
+}
+
+static inline void free_part_stats(struct hd_struct *part)
+{
+ free_percpu(part->dkstats);
+}
+
#else /* CONFIG_SMP */
static inline int init_disk_stats(struct gendisk *disk)
{
static inline void free_disk_stats(struct gendisk *disk)
{
}
+
+static inline int init_part_stats(struct hd_struct *part)
+{
+ return 1;
+}
+
+static inline void free_part_stats(struct hd_struct *part)
+{
+}
#endif /* CONFIG_SMP */
/* drivers/block/ll_rw_blk.c */
extern void disk_round_stats(struct gendisk *disk);
+extern void part_round_stats(struct hd_struct *part);
/* drivers/block/genhd.c */
extern int get_blkdev_list(char *, int);
* as otherwise the timer could be removed before the softirq code finishes the
* the handling of the timer.
*
- * The HRTIMER_STATE_ENQUEUE bit is always or'ed to the current state to
+ * The HRTIMER_STATE_ENQUEUED bit is always or'ed to the current state to
* preserve the HRTIMER_STATE_CALLBACK bit in the above scenario.
*
* All state transitions are protected by cpu_base->lock.
}
int hugetlb_sysctl_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *);
+int hugetlb_overcommit_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *);
int hugetlb_treat_movable_handler(struct ctl_table *, int, struct file *, void __user *, size_t *, loff_t *);
int copy_hugetlb_page_range(struct mm_struct *, struct mm_struct *, struct vm_area_struct *);
int follow_hugetlb_page(struct mm_struct *, struct vm_area_struct *, struct page **, struct vm_area_struct **, unsigned long *, int *, int, int);
void *security;
};
-struct ipc_ids;
-struct ipc_namespace {
- struct kref kref;
- struct ipc_ids *ids[3];
-
- int sem_ctls[4];
- int used_sems;
-
- int msg_ctlmax;
- int msg_ctlmnb;
- int msg_ctlmni;
- atomic_t msg_bytes;
- atomic_t msg_hdrs;
-
- size_t shm_ctlmax;
- size_t shm_ctlall;
- int shm_ctlmni;
- int shm_tot;
-};
-
-extern struct ipc_namespace init_ipc_ns;
-
-#ifdef CONFIG_SYSVIPC
-#define INIT_IPC_NS(ns) .ns = &init_ipc_ns,
-extern void free_ipc_ns(struct kref *kref);
-extern struct ipc_namespace *copy_ipcs(unsigned long flags,
- struct ipc_namespace *ns);
-#else
-#define INIT_IPC_NS(ns)
-static inline struct ipc_namespace *copy_ipcs(unsigned long flags,
- struct ipc_namespace *ns)
-{
- return ns;
-}
-#endif
-
-static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns)
-{
-#ifdef CONFIG_SYSVIPC
- if (ns)
- kref_get(&ns->kref);
-#endif
- return ns;
-}
-
-static inline void put_ipc_ns(struct ipc_namespace *ns)
-{
-#ifdef CONFIG_SYSVIPC
- kref_put(&ns->kref, free_ipc_ns);
-#endif
-}
-
#endif /* __KERNEL__ */
#endif /* _LINUX_IPC_H */
--- /dev/null
+#ifndef __IPC_NAMESPACE_H__
+#define __IPC_NAMESPACE_H__
+
+#include <linux/err.h>
+#include <linux/idr.h>
+#include <linux/rwsem.h>
+
+struct ipc_ids {
+ int in_use;
+ unsigned short seq;
+ unsigned short seq_max;
+ struct rw_semaphore rw_mutex;
+ struct idr ipcs_idr;
+};
+
+struct ipc_namespace {
+ struct kref kref;
+ struct ipc_ids ids[3];
+
+ int sem_ctls[4];
+ int used_sems;
+
+ int msg_ctlmax;
+ int msg_ctlmnb;
+ int msg_ctlmni;
+ atomic_t msg_bytes;
+ atomic_t msg_hdrs;
+
+ size_t shm_ctlmax;
+ size_t shm_ctlall;
+ int shm_ctlmni;
+ int shm_tot;
+};
+
+extern struct ipc_namespace init_ipc_ns;
+
+#ifdef CONFIG_SYSVIPC
+#define INIT_IPC_NS(ns) .ns = &init_ipc_ns,
+#else
+#define INIT_IPC_NS(ns)
+#endif
+
+#if defined(CONFIG_SYSVIPC) && defined(CONFIG_IPC_NS)
+extern void free_ipc_ns(struct kref *kref);
+extern struct ipc_namespace *copy_ipcs(unsigned long flags,
+ struct ipc_namespace *ns);
+extern void free_ipcs(struct ipc_namespace *ns, struct ipc_ids *ids,
+ void (*free)(struct ipc_namespace *,
+ struct kern_ipc_perm *));
+
+static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns)
+{
+ if (ns)
+ kref_get(&ns->kref);
+ return ns;
+}
+
+static inline void put_ipc_ns(struct ipc_namespace *ns)
+{
+ kref_put(&ns->kref, free_ipc_ns);
+}
+#else
+static inline struct ipc_namespace *copy_ipcs(unsigned long flags,
+ struct ipc_namespace *ns)
+{
+ if (flags & CLONE_NEWIPC)
+ return ERR_PTR(-EINVAL);
+
+ return ns;
+}
+
+static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns)
+{
+ return ns;
+}
+
+static inline void put_ipc_ns(struct ipc_namespace *ns)
+{
+}
+#endif
+#endif
#include <asm/irq_regs.h>
struct irq_desc;
-typedef void fastcall (*irq_flow_handler_t)(unsigned int irq,
+typedef void (*irq_flow_handler_t)(unsigned int irq,
struct irq_desc *desc);
* Built-in IRQ handlers for various IRQ types,
* callable via desc->chip->handle_irq()
*/
-extern void fastcall handle_level_irq(unsigned int irq, struct irq_desc *desc);
-extern void fastcall handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
-extern void fastcall handle_edge_irq(unsigned int irq, struct irq_desc *desc);
-extern void fastcall handle_simple_irq(unsigned int irq, struct irq_desc *desc);
-extern void fastcall handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
-extern void fastcall handle_bad_irq(unsigned int irq, struct irq_desc *desc);
+extern void handle_level_irq(unsigned int irq, struct irq_desc *desc);
+extern void handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc);
+extern void handle_edge_irq(unsigned int irq, struct irq_desc *desc);
+extern void handle_simple_irq(unsigned int irq, struct irq_desc *desc);
+extern void handle_percpu_irq(unsigned int irq, struct irq_desc *desc);
+extern void handle_bad_irq(unsigned int irq, struct irq_desc *desc);
/*
* Monolithic do_IRQ implementation.
* (is an explicit fastcall, because i386 4KSTACKS calls it from assembly)
*/
#ifndef CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ
-extern fastcall unsigned int __do_IRQ(unsigned int irq);
+extern unsigned int __do_IRQ(unsigned int irq);
#endif
/*
__set_irq_handler(irq, handle, 1, NULL);
}
+extern void set_irq_noprobe(unsigned int irq);
+extern void set_irq_probe(unsigned int irq);
+
/* Handle dynamic irq creation and destruction */
extern int create_irq(void);
extern void destroy_irq(unsigned int irq);
/* LATCH is used in the interval timer and ftape setup. */
#define LATCH ((CLOCK_TICK_RATE + HZ/2) / HZ) /* For divider */
-/* Suppose we want to devide two numbers NOM and DEN: NOM/DEN, the we can
+/* Suppose we want to devide two numbers NOM and DEN: NOM/DEN, then we can
* improve accuracy by shifting LSH bits, hence calculating:
* (NOM << LSH) / DEN
* This however means trouble for large NOM, because (NOM << LSH) may no
* We want to do realistic conversions of time so we need to use the same
* values the update wall clock code uses as the jiffies size. This value
* is: TICK_NSEC (which is defined in timex.h). This
- * is a constant and is in nanoseconds. We will used scaled math
+ * is a constant and is in nanoseconds. We will use scaled math
* with a set of scales defined here as SEC_JIFFIE_SC, USEC_JIFFIE_SC and
* NSEC_JIFFIE_SC. Note that these defines contain nothing but
* constants and so are computed at compile time. SHIFT_HZ (computed in
* operator if the result is a long long AND at least one of the
* operands is cast to long long (usually just prior to the "*" so as
* not to confuse it into thinking it really has a 64-bit operand,
- * which, buy the way, it can do, but it take more code and at least 2
+ * which, buy the way, it can do, but it takes more code and at least 2
* mpys).
* We also need to be aware that one second in nanoseconds is only a
extern void oops_enter(void);
extern void oops_exit(void);
extern int oops_may_print(void);
-fastcall NORET_TYPE void do_exit(long error_code)
+NORET_TYPE void do_exit(long error_code)
ATTRIB_NORET;
NORET_TYPE void complete_and_exit(struct completion *, long)
ATTRIB_NORET;
extern long simple_strtol(const char *,char **,unsigned int);
extern unsigned long long simple_strtoull(const char *,char **,unsigned int);
extern long long simple_strtoll(const char *,char **,unsigned int);
+extern int strict_strtoul(const char *, unsigned int, unsigned long *);
+extern int strict_strtol(const char *, unsigned int, long *);
+extern int strict_strtoull(const char *, unsigned int, unsigned long long *);
+extern int strict_strtoll(const char *, unsigned int, long long *);
extern int sprintf(char * buf, const char * fmt, ...)
__attribute__ ((format (printf, 2, 3)));
extern int vsprintf(char *buf, const char *, va_list)
struct pid;
extern struct pid *session_of_pgrp(struct pid *pgrp);
-extern void dump_thread(struct pt_regs *regs, struct user *dump);
-
#ifdef CONFIG_PRINTK
asmlinkage int vprintk(const char *fmt, va_list args)
__attribute__ ((format (printf, 1, 0)));
extern int log_buf_get_len(void);
extern int log_buf_read(int idx);
extern int log_buf_copy(char *dest, int idx, int len);
+
+extern int printk_ratelimit_jiffies;
+extern int printk_ratelimit_burst;
+extern int printk_ratelimit(void);
+extern int __printk_ratelimit(int ratelimit_jiffies, int ratelimit_burst);
+extern bool printk_timed_ratelimit(unsigned long *caller_jiffies,
+ unsigned int interval_msec);
#else
static inline int vprintk(const char *s, va_list args)
__attribute__ ((format (printf, 1, 0)));
static inline int log_buf_get_len(void) { return 0; }
static inline int log_buf_read(int idx) { return 0; }
static inline int log_buf_copy(char *dest, int idx, int len) { return 0; }
+static inline int printk_ratelimit(void) { return 0; }
+static inline int __printk_ratelimit(int ratelimit_jiffies, \
+ int ratelimit_burst) { return 0; }
+static inline bool printk_timed_ratelimit(unsigned long *caller_jiffies, \
+ unsigned int interval_msec) \
+ { return false; }
#endif
extern void __attribute__((format(printf, 1, 2)))
unsigned long int_sqrt(unsigned long);
-extern int printk_ratelimit(void);
-extern int __printk_ratelimit(int ratelimit_jiffies, int ratelimit_burst);
-extern bool printk_timed_ratelimit(unsigned long *caller_jiffies,
- unsigned int interval_msec);
-
static inline void console_silent(void)
{
console_loglevel = 0;
extern int tainted;
extern const char *print_tainted(void);
extern void add_taint(unsigned);
+extern int root_mountflags;
/* Values used for system_state */
extern enum system_states {
MLX4_STAT_RATE_OFFSET = 5
};
+static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
+{
+ return (major << 32) | (minor << 16) | subminor;
+}
+
struct mlx4_caps {
u64 fw_ver;
int num_ports;
};
struct mlx4_buf {
- union {
- struct mlx4_buf_list direct;
- struct mlx4_buf_list *page_list;
- } u;
+ struct mlx4_buf_list direct;
+ struct mlx4_buf_list *page_list;
int nbufs;
int npages;
int page_shift;
int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
struct mlx4_buf *buf);
void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
+static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
+{
+ if (BITS_PER_LONG == 64 || buf->nbufs == 1)
+ return buf->direct.buf + offset;
+ else
+ return buf->page_list[offset >> PAGE_SHIFT].buf +
+ (offset & (PAGE_SIZE - 1));
+}
int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
u32 reserved5[10];
};
+/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
+#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
+
enum {
+ MLX4_WQE_CTRL_NEC = 1 << 29,
MLX4_WQE_CTRL_FENCE = 1 << 6,
MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
MLX4_WQE_CTRL_SOLICITED = 1 << 1,
#define pte_lockptr(mm, pmd) ({(void)(pmd); &(mm)->page_table_lock;})
#endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+static inline void pgtable_page_ctor(struct page *page)
+{
+ pte_lock_init(page);
+ inc_zone_page_state(page, NR_PAGETABLE);
+}
+
+static inline void pgtable_page_dtor(struct page *page)
+{
+ pte_lock_deinit(page);
+ dec_zone_page_state(page, NR_PAGETABLE);
+}
+
#define pte_offset_map_lock(mm, pmd, address, ptlp) \
({ \
spinlock_t *__ptl = pte_lockptr(mm, pmd); \
#define FOLL_GET 0x04 /* do get_page on page */
#define FOLL_ANON 0x08 /* give ZERO_PAGE if no pgtable */
-typedef int (*pte_fn_t)(pte_t *pte, struct page *pmd_page, unsigned long addr,
+typedef int (*pte_fn_t)(pte_t *pte, pgtable_t token, unsigned long addr,
void *data);
extern int apply_to_page_range(struct mm_struct *mm, unsigned long address,
unsigned long size, pte_fn_t fn, void *data);
/* For kallsyms to ask for address resolution. namebuf should be at
* least KSYM_NAME_LEN long: a pointer to namebuf is returned if
* found, otherwise NULL. */
-char *module_address_lookup(unsigned long addr,
+const char *module_address_lookup(unsigned long addr,
unsigned long *symbolsize,
unsigned long *offset,
char **modname,
#define module_name(mod) "kernel"
/* For kallsyms to ask for address resolution. NULL means not found. */
-static inline char *module_address_lookup(unsigned long addr,
+static inline const char *module_address_lookup(unsigned long addr,
unsigned long *symbolsize,
unsigned long *offset,
char **modname,
*
* Returns 1 if the mutex is locked, 0 if unlocked.
*/
-static inline int fastcall mutex_is_locked(struct mutex *lock)
+static inline int mutex_is_locked(struct mutex *lock)
{
return atomic_read(&lock->count) != 1;
}
#define mutex_lock_interruptible(lock) mutex_lock_interruptible_nested(lock, 0)
#define mutex_lock_killable(lock) mutex_lock_killable_nested(lock, 0)
#else
-extern void fastcall mutex_lock(struct mutex *lock);
-extern int __must_check fastcall mutex_lock_interruptible(struct mutex *lock);
-extern int __must_check fastcall mutex_lock_killable(struct mutex *lock);
+extern void mutex_lock(struct mutex *lock);
+extern int __must_check mutex_lock_interruptible(struct mutex *lock);
+extern int __must_check mutex_lock_killable(struct mutex *lock);
# define mutex_lock_nested(lock, subclass) mutex_lock(lock)
# define mutex_lock_interruptible_nested(lock, subclass) mutex_lock_interruptible(lock)
* NOTE: mutex_trylock() follows the spin_trylock() convention,
* not the down_trylock() convention!
*/
-extern int fastcall mutex_trylock(struct mutex *lock);
-extern void fastcall mutex_unlock(struct mutex *lock);
+extern int mutex_trylock(struct mutex *lock);
+extern void mutex_unlock(struct mutex *lock);
#endif
};
#define nbd_cmd(req) ((req)->cmd[0])
-#define MAX_NBD 128
/* userspace doesn't need the nbd_device structure */
#ifdef __KERNEL__
#define SADB_X_EALG_BLOWFISHCBC 7
#define SADB_EALG_NULL 11
#define SADB_X_EALG_AESCBC 12
+#define SADB_X_EALG_AESCTR 13
#define SADB_X_EALG_AES_CCM_ICV8 14
#define SADB_X_EALG_AES_CCM_ICV12 15
#define SADB_X_EALG_AES_CCM_ICV16 16
*/
extern struct pid *find_get_pid(int nr);
extern struct pid *find_ge_pid(int nr, struct pid_namespace *);
+int next_pidmap(struct pid_namespace *pid_ns, int last);
extern struct pid *alloc_pid(struct pid_namespace *ns);
extern void FASTCALL(free_pid(struct pid *pid));
-extern void zap_pid_ns_processes(struct pid_namespace *pid_ns);
/*
* the helpers to get the pid's id seen from different namespaces
*
* pid_nr() : global id, i.e. the id seen from the init namespace;
- * pid_vnr() : virtual id, i.e. the id seen from the namespace this pid
- * belongs to. this only makes sence when called in the
- * context of the task that belongs to the same namespace;
+ * pid_vnr() : virtual id, i.e. the id seen from the pid namespace of
+ * current.
* pid_nr_ns() : id seen from the ns specified.
*
* see also task_xid_nr() etc in include/linux/sched.h
}
pid_t pid_nr_ns(struct pid *pid, struct pid_namespace *ns);
-
-static inline pid_t pid_vnr(struct pid *pid)
-{
- pid_t nr = 0;
- if (pid)
- nr = pid->numbers[pid->level].nr;
- return nr;
-}
+pid_t pid_vnr(struct pid *pid);
#define do_each_pid_task(pid, type, task) \
do { \
hlist_for_each_entry_rcu((task), pos___, \
&pid->tasks[type], pids[type].node) {
+ /*
+ * Both old and new leaders may be attached to
+ * the same pid in the middle of de_thread().
+ */
#define while_each_pid_task(pid, type, task) \
+ if (type == PIDTYPE_PID) \
+ break; \
} \
} while (0)
extern struct pid_namespace *copy_pid_ns(unsigned long flags, struct pid_namespace *ns);
extern void free_pid_ns(struct kref *kref);
+extern void zap_pid_ns_processes(struct pid_namespace *pid_ns);
static inline void put_pid_ns(struct pid_namespace *ns)
{
{
}
+
+static inline void zap_pid_ns_processes(struct pid_namespace *ns)
+{
+ BUG();
+}
#endif /* CONFIG_PID_NS */
static inline struct pid_namespace *task_active_pid_ns(struct task_struct *tsk)
#include <linux/list.h>
#ifdef CONFIG_DEBUG_PREEMPT
- extern void fastcall add_preempt_count(int val);
- extern void fastcall sub_preempt_count(int val);
+ extern void add_preempt_count(int val);
+ extern void sub_preempt_count(int val);
#else
# define add_preempt_count(val) do { preempt_count() += (val); } while (0)
# define sub_preempt_count(val) do { preempt_count() -= (val); } while (0)
int proc_pid_readdir(struct file * filp, void * dirent, filldir_t filldir);
unsigned long task_vsize(struct mm_struct *);
int task_statm(struct mm_struct *, int *, int *, int *, int *);
-char *task_mem(struct mm_struct *, char *);
+void task_mem(struct seq_file *, struct mm_struct *);
+void clear_refs_smap(struct mm_struct *mm);
struct proc_dir_entry *de_get(struct proc_dir_entry *de);
void de_put(struct proc_dir_entry *de);
extern struct proc_dir_entry *create_proc_entry(const char *name, mode_t mode,
struct proc_dir_entry *parent);
+struct proc_dir_entry *proc_create(const char *name, mode_t mode,
+ struct proc_dir_entry *parent,
+ const struct file_operations *proc_fops);
extern void remove_proc_entry(const char *name, struct proc_dir_entry *parent);
extern struct vfsmount *proc_mnt;
static inline struct proc_dir_entry *create_proc_entry(const char *name,
mode_t mode, struct proc_dir_entry *parent) { return NULL; }
-
+static inline struct proc_dir_entry *proc_create(const char *name,
+ mode_t mode, struct proc_dir_entry *parent,
+ const struct file_operations *proc_fops)
+{
+ return NULL;
+}
#define remove_proc_entry(name, parent) do {} while (0)
static inline struct proc_dir_entry *proc_symlink(const char *name,
union proc_op {
int (*proc_get_link)(struct inode *, struct dentry **, struct vfsmount **);
int (*proc_read)(struct task_struct *task, char *page);
+ int (*proc_show)(struct seq_file *m,
+ struct pid_namespace *ns, struct pid *pid,
+ struct task_struct *task);
};
struct proc_inode {
#define PT_TRACE_EXEC 0x00000080
#define PT_TRACE_VFORK_DONE 0x00000100
#define PT_TRACE_EXIT 0x00000200
-#define PT_ATTACHED 0x00000400 /* parent != real_parent */
#define PT_TRACE_MASK 0x000003f4
#define rcu_bh_qsctr_inc(cpu)
#define call_rcu_bh(head, rcu) call_rcu(head, rcu)
-extern void __rcu_read_lock(void);
-extern void __rcu_read_unlock(void);
+extern void __rcu_read_lock(void) __acquires(RCU);
+extern void __rcu_read_unlock(void) __releases(RCU);
extern int rcu_pending(int cpu);
extern int rcu_needs_cpu(int cpu);
/* Don't trust REISERFS_SB(sb)->s_bmap_nr, it's a u16
* which overflows on large file systems. */
-static inline u32 reiserfs_bmap_count(struct super_block *sb)
+static inline __u32 reiserfs_bmap_count(struct super_block *sb)
{
return (SB_BLOCK_COUNT(sb) - 1) / (sb->s_blocksize * 8) + 1;
}
/* ITIMER_REAL timer for the process */
struct hrtimer real_timer;
- struct task_struct *tsk;
+ struct pid *leader_pid;
ktime_t it_real_incr;
/* ITIMER_PROF and ITIMER_VIRTUAL timers for the process */
* from various namespaces
*
* task_xid_nr() : global id, i.e. the id seen from the init namespace;
- * task_xid_vnr() : virtual id, i.e. the id seen from the namespace the task
- * belongs to. this only makes sence when called in the
- * context of the task that belongs to the same namespace;
+ * task_xid_vnr() : virtual id, i.e. the id seen from the pid namespace of
+ * current.
* task_xid_nr_ns() : id seen from the ns specified;
*
* set_task_vxid() : assigns a virtual id to a task;
extern struct task_struct *find_task_by_pid_ns(pid_t nr,
struct pid_namespace *ns);
-extern void __set_special_pids(pid_t session, pid_t pgrp);
+extern void __set_special_pids(struct pid *pid);
/* per-UID process charging. */
extern struct user_struct * alloc_uid(struct user_namespace *, uid_t);
extern void unblock_all_signals(void);
extern void release_task(struct task_struct * p);
extern int send_sig_info(int, struct siginfo *, struct task_struct *);
-extern int send_group_sig_info(int, struct siginfo *, struct task_struct *);
extern int force_sigsegv(int, struct task_struct *);
extern int force_sig_info(int, struct siginfo *, struct task_struct *);
extern int __kill_pgrp_info(int sig, struct siginfo *info, struct pid *pgrp);
-extern int kill_pgrp_info(int sig, struct siginfo *info, struct pid *pgrp);
extern int kill_pid_info(int sig, struct siginfo *info, struct pid *pid);
extern int kill_pid_info_as_uid(int, struct siginfo *, struct pid *, uid_t, uid_t, u32);
extern int kill_pgrp(struct pid *pid, int sig, int priv);
#define PORT_MCF 78
+/* MN10300 on-chip UART numbers */
+#define PORT_MN10300 80
+#define PORT_MN10300_CTS 81
+
#ifdef __KERNEL__
#include <linux/compiler.h>
unsigned long free_blocks; /* How many are left for allocation */
unsigned long max_inodes; /* How many inodes are allowed */
unsigned long free_inodes; /* How many are left for allocation */
+ spinlock_t stat_lock; /* Serialize shmem_sb_info changes */
+ uid_t uid; /* Mount uid for root directory */
+ gid_t gid; /* Mount gid for root directory */
+ mode_t mode; /* Mount mode for root directory */
int policy; /* Default NUMA memory alloc policy */
nodemask_t policy_nodes; /* nodemask for preferred and bind */
- spinlock_t stat_lock;
};
static inline struct shmem_inode_info *SHMEM_I(struct inode *inode)
struct pt_regs;
extern int get_signal_to_deliver(siginfo_t *info, struct k_sigaction *return_ka, struct pt_regs *regs, void *cookie);
+extern void exit_signals(struct task_struct *tsk);
extern struct kmem_cache *sighand_cachep;
#define LOCK_SECTION_END \
".previous\n\t"
-#define __lockfunc fastcall __attribute__((section(".spinlock.text")))
+#define __lockfunc __attribute__((section(".spinlock.text")))
/*
* Pull the raw_spinlock_t and raw_rwlock_t definitions:
extern void monotonic_to_bootbased(struct timespec *ts);
extern struct timespec timespec_trunc(struct timespec t, unsigned gran);
-extern int timekeeping_is_continuous(void);
+extern int timekeeping_valid_for_hres(void);
extern void update_wall_time(void);
extern void update_xtime_cache(u64 nsec);
struct timer_list _name = \
TIMER_INITIALIZER(_function, _expires, _data)
-void fastcall init_timer(struct timer_list * timer);
-void fastcall init_timer_deferrable(struct timer_list *timer);
+void init_timer(struct timer_list *timer);
+void init_timer_deferrable(struct timer_list *timer);
static inline void setup_timer(struct timer_list * timer,
void (*function)(unsigned long),
}
#endif
-extern void delayed_work_timer_fn(unsigned long __data);
-
/**
* add_timer - start a timer
* @timer: the timer to be added
typedef __kernel_gid_t gid_t;
#endif /* __KERNEL__ */
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#if defined(__GNUC__)
typedef __kernel_loff_t loff_t;
#endif
typedef __u16 uint16_t;
typedef __u32 uint32_t;
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#if defined(__GNUC__)
typedef __u64 uint64_t;
typedef __u64 u_int64_t;
typedef __s64 int64_t;
typedef __u16 __bitwise __be16;
typedef __u32 __bitwise __le32;
typedef __u32 __bitwise __be32;
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#if defined(__GNUC__)
typedef __u64 __bitwise __le64;
typedef __u64 __bitwise __be64;
#endif
#define UDF_PREALLOCATE
#define UDF_DEFAULT_PREALLOC_BLOCKS 8
-#define UDFFS_DATE "2004/29/09"
-#define UDFFS_VERSION "0.9.8.1"
-
#undef UDFFS_DEBUG
#ifdef UDFFS_DEBUG
#define udf_debug(f, a...) \
- { \
+ do { \
printk (KERN_DEBUG "UDF-fs DEBUG %s:%d:%s: ", \
__FILE__, __LINE__, __FUNCTION__); \
printk (f, ##a); \
- }
+ } while (0)
#else
#define udf_debug(f, a...) /**/
#endif
struct udf_sb_info
{
struct udf_part_map *s_partmaps;
- __u8 s_volident[32];
+ __u8 s_volume_ident[32];
/* Overall info */
__u16 s_partitions;
/* Sector headers */
__s32 s_session;
__u32 s_anchor[4];
- __u32 s_lastblock;
+ __u32 s_last_block;
- struct buffer_head *s_lvidbh;
+ struct buffer_head *s_lvid_bh;
/* Default permissions */
mode_t s_umask;
uid_t s_uid;
/* Root Info */
- struct timespec s_recordtime;
+ struct timespec s_record_time;
/* Fileset Info */
- __u16 s_serialnum;
+ __u16 s_serial_number;
/* highest UDF revision we have recorded to this media */
__u16 s_udfrev;
struct nls_table *s_nls_map;
/* VAT inode */
- struct inode *s_vat;
+ struct inode *s_vat_inode;
struct mutex s_alloc_mutex;
};
#include <linux/sched.h>
#include <linux/kref.h>
#include <linux/nsproxy.h>
+#include <linux/err.h>
#include <asm/atomic.h>
struct uts_namespace {
};
extern struct uts_namespace init_uts_ns;
+#ifdef CONFIG_UTS_NS
static inline void get_uts_ns(struct uts_namespace *ns)
{
kref_get(&ns->kref);
{
kref_put(&ns->kref, free_uts_ns);
}
+#else
+static inline void get_uts_ns(struct uts_namespace *ns)
+{
+}
+
+static inline void put_uts_ns(struct uts_namespace *ns)
+{
+}
+
+static inline struct uts_namespace *copy_utsname(unsigned long flags,
+ struct uts_namespace *ns)
+{
+ if (flags & CLONE_NEWUTS)
+ return ERR_PTR(-EINVAL);
+
+ return ns;
+}
+#endif
+
static inline struct new_utsname *utsname(void)
{
return ¤t->nsproxy->uts_ns->name;
*
*/
-#define RTPRI_FIREWALL 8 /* Firewall control information */
-#define RTPRI_FLOW 16 /* Flow based forwarding rules */
-#define RTPRI_KERN_CTL 32 /* Kernel control routes */
-
-#define RTPRI_USER_MIN 256 /* Mimimum user priority */
-#define RTPRI_USER_MAX 1024 /* Maximum user priority */
-
-#define RTPRI_KERN_DFLT 4096 /* Kernel default routes */
-
-#define MAX_FLOW_BACKTRACE 32
-
-
-typedef void (*f_pnode)(struct fib6_node *fn, void *);
struct fib6_table {
struct hlist_node tb6_hlist;
#ifndef _NET_IP6_ROUTE_H
#define _NET_IP6_ROUTE_H
-#define IP6_RT_PRIO_FW 16
#define IP6_RT_PRIO_USER 1024
#define IP6_RT_PRIO_ADDRCONF 256
#define IP6_RT_PRIO_KERN 512
-#define IP6_RT_FLOW_MASK 0x00ff
struct route_info {
__u8 type;
void (*destroy)(struct nf_conn *ct);
/* Called when realloacted (can be NULL).
Contents has already been moved. */
- void (*move)(struct nf_conn *ct, void *old);
+ void (*move)(void *new, void *old);
enum nf_ct_ext_id id;
return msg_bits(m, 1, 29, 0x7);
}
-static inline u32 msg_direct(struct tipc_msg *m)
-{
- return (msg_type(m) == TIPC_DIRECT_MSG);
-}
-
static inline u32 msg_named(struct tipc_msg *m)
{
return (msg_type(m) == TIPC_NAMED_MSG);
return msg_word(m, 10);
}
-static inline char *msg_options(struct tipc_msg *m, u32 *len)
-{
- u32 pos = msg_bits(m, 1, 16, 0x7);
-
- if (!pos)
- return 0;
- pos = (pos * 4) + 28;
- *len = msg_hdr_sz(m) - pos;
- return (char *)&m->hdr[pos/4];
-}
-
#endif
#endif
IB_DEVICE_N_NOTIFY_CQ = (1<<14),
IB_DEVICE_ZERO_STAG = (1<<15),
IB_DEVICE_SEND_W_INV = (1<<16),
- IB_DEVICE_MEM_WINDOW = (1<<17)
+ IB_DEVICE_MEM_WINDOW = (1<<17),
+ /*
+ * Devices should set IB_DEVICE_UD_IP_SUM if they support
+ * insertion of UDP and TCP checksum on outgoing UD IPoIB
+ * messages and can verify the validity of checksum for
+ * incoming messages. Setting this flag implies that the
+ * IPoIB driver may set NETIF_F_IP_CSUM for datagram mode.
+ */
+ IB_DEVICE_UD_IP_CSUM = (1<<18),
};
enum ib_atomic_cap {
u8 sl;
u8 dlid_path_bits;
u8 port_num; /* valid only for DR SMPs on switches */
+ int csum_ok;
};
enum ib_cq_notify_flags {
IB_SEND_FENCE = 1,
IB_SEND_SIGNALED = (1<<1),
IB_SEND_SOLICITED = (1<<2),
- IB_SEND_INLINE = (1<<3)
+ IB_SEND_INLINE = (1<<3),
+ IB_SEND_IP_CSUM = (1<<4)
};
struct ib_sge {
int *pkey_tbl_len;
int *gid_tbl_len;
- u32 flags;
-
int num_comp_vectors;
struct iw_cm_verbs *iwcm;
Say N if unsure.
-config USER_NS
- bool "User Namespaces (EXPERIMENTAL)"
- default n
- depends on EXPERIMENTAL
- help
- Support user namespaces. This allows containers, i.e.
- vservers, to use user namespaces to provide different
- user info for different servers. If unsure, say N.
-
-config PID_NS
- bool "PID Namespaces (EXPERIMENTAL)"
- default n
- depends on EXPERIMENTAL
- help
- Suport process id namespaces. This allows having multiple
- process with the same pid as long as they are in different
- pid namespaces. This is a building block of containers.
-
- Unless you want to work with an experimental feature
- say N here.
-
config AUDIT
bool "Auditing support"
depends on NET
If unsure, say N.
+config NAMESPACES
+ bool "Namespaces support" if EMBEDDED
+ default !EMBEDDED
+ help
+ Provides the way to make tasks work with different objects using
+ the same id. For example same IPC id may refer to different objects
+ or same user id or pid may refer to different tasks when used in
+ different namespaces.
+
+config UTS_NS
+ bool "UTS namespace"
+ depends on NAMESPACES
+ help
+ In this namespace tasks see different info provided with the
+ uname() system call
+
+config IPC_NS
+ bool "IPC namespace"
+ depends on NAMESPACES && SYSVIPC
+ help
+ In this namespace tasks work with IPC ids which correspond to
+ different IPC objects in different namespaces
+
+config USER_NS
+ bool "User namespace (EXPERIMENTAL)"
+ depends on NAMESPACES && EXPERIMENTAL
+ help
+ This allows containers, i.e. vservers, to use user namespaces
+ to provide different user info for different servers.
+ If unsure, say N.
+
+config PID_NS
+ bool "PID Namespaces (EXPERIMENTAL)"
+ default n
+ depends on NAMESPACES && EXPERIMENTAL
+ help
+ Suport process id namespaces. This allows having multiple
+ process with the same pid as long as they are in different
+ pid namespaces. This is a building block of containers.
+
+ Unless you want to work with an experimental feature
+ say N here.
+
config BLK_DEV_INITRD
bool "Initial RAM filesystem and RAM disk (initramfs/initrd) support"
depends on BROKEN || !FRV
static int __init debug_kernel(char *str)
{
- if (*str)
- return 0;
console_loglevel = 10;
- return 1;
+ return 0;
}
static int __init quiet_kernel(char *str)
{
- if (*str)
- return 0;
console_loglevel = 4;
- return 1;
+ return 0;
}
-__setup("debug", debug_kernel);
-__setup("quiet", quiet_kernel);
+early_param("debug", debug_kernel);
+early_param("quiet", quiet_kernel);
static int __init loglevel(char *str)
{
return 1;
}
-__setup("loglevel=", loglevel);
+early_param("loglevel", loglevel);
/*
* Unknown boot options get handed to init, unless they look like
*/
init_pid_ns.child_reaper = current;
- __set_special_pids(1, 1);
cad_pid = task_pid(current);
smp_prepare_cpus(setup_max_cpus);
obj-$(CONFIG_SYSVIPC_SYSCTL) += ipc_sysctl.o
obj_mq-$(CONFIG_COMPAT) += compat_mq.o
obj-$(CONFIG_POSIX_MQUEUE) += mqueue.o msgutil.o $(obj_mq-y)
+obj-$(CONFIG_IPC_NS) += namespace.o
#include <linux/nsproxy.h>
#include <linux/sysctl.h>
#include <linux/uaccess.h>
+#include <linux/ipc_namespace.h>
static void *get_ipc(ctl_table *table)
{
(info->notify_owner &&
info->notify.sigev_notify == SIGEV_SIGNAL) ?
info->notify.sigev_signo : 0,
- pid_nr_ns(info->notify_owner,
- current->nsproxy->pid_ns));
+ pid_vnr(info->notify_owner));
spin_unlock(&info->lock);
buffer[sizeof(buffer)-1] = '\0';
slen = strlen(buffer)+1;
sig_i.si_errno = 0;
sig_i.si_code = SI_MESGQ;
sig_i.si_value = info->notify.sigev_value;
- sig_i.si_pid = task_pid_vnr(current);
+ sig_i.si_pid = task_tgid_vnr(current);
sig_i.si_uid = current->uid;
kill_pid_info(info->notify.sigev_signo,
#include <linux/seq_file.h>
#include <linux/rwsem.h>
#include <linux/nsproxy.h>
+#include <linux/ipc_namespace.h>
#include <asm/current.h>
#include <asm/uaccess.h>
#define SEARCH_NOTEQUAL 3
#define SEARCH_LESSEQUAL 4
-static struct ipc_ids init_msg_ids;
-
-#define msg_ids(ns) (*((ns)->ids[IPC_MSG_IDS]))
+#define msg_ids(ns) ((ns)->ids[IPC_MSG_IDS])
#define msg_unlock(msq) ipc_unlock(&(msq)->q_perm)
#define msg_buildid(id, seq) ipc_buildid(id, seq)
-static void freeque(struct ipc_namespace *, struct msg_queue *);
+static void freeque(struct ipc_namespace *, struct kern_ipc_perm *);
static int newque(struct ipc_namespace *, struct ipc_params *);
#ifdef CONFIG_PROC_FS
static int sysvipc_msg_proc_show(struct seq_file *s, void *it);
#endif
-static void __msg_init_ns(struct ipc_namespace *ns, struct ipc_ids *ids)
+void msg_init_ns(struct ipc_namespace *ns)
{
- ns->ids[IPC_MSG_IDS] = ids;
ns->msg_ctlmax = MSGMAX;
ns->msg_ctlmnb = MSGMNB;
ns->msg_ctlmni = MSGMNI;
atomic_set(&ns->msg_bytes, 0);
atomic_set(&ns->msg_hdrs, 0);
- ipc_init_ids(ids);
-}
-
-int msg_init_ns(struct ipc_namespace *ns)
-{
- struct ipc_ids *ids;
-
- ids = kmalloc(sizeof(struct ipc_ids), GFP_KERNEL);
- if (ids == NULL)
- return -ENOMEM;
-
- __msg_init_ns(ns, ids);
- return 0;
+ ipc_init_ids(&ns->ids[IPC_MSG_IDS]);
}
+#ifdef CONFIG_IPC_NS
void msg_exit_ns(struct ipc_namespace *ns)
{
- struct msg_queue *msq;
- struct kern_ipc_perm *perm;
- int next_id;
- int total, in_use;
-
- down_write(&msg_ids(ns).rw_mutex);
-
- in_use = msg_ids(ns).in_use;
-
- for (total = 0, next_id = 0; total < in_use; next_id++) {
- perm = idr_find(&msg_ids(ns).ipcs_idr, next_id);
- if (perm == NULL)
- continue;
- ipc_lock_by_ptr(perm);
- msq = container_of(perm, struct msg_queue, q_perm);
- freeque(ns, msq);
- total++;
- }
-
- up_write(&msg_ids(ns).rw_mutex);
-
- kfree(ns->ids[IPC_MSG_IDS]);
- ns->ids[IPC_MSG_IDS] = NULL;
+ free_ipcs(ns, &msg_ids(ns), freeque);
}
+#endif
void __init msg_init(void)
{
- __msg_init_ns(&init_ipc_ns, &init_msg_ids);
+ msg_init_ns(&init_ipc_ns);
ipc_init_proc_interface("sysvipc/msg",
" key msqid perms cbytes qnum lspid lrpid uid gid cuid cgid stime rtime ctime\n",
IPC_MSG_IDS, sysvipc_msg_proc_show);
* msg_ids.rw_mutex (writer) and the spinlock for this message queue are held
* before freeque() is called. msg_ids.rw_mutex remains locked on exit.
*/
-static void freeque(struct ipc_namespace *ns, struct msg_queue *msq)
+static void freeque(struct ipc_namespace *ns, struct kern_ipc_perm *ipcp)
{
struct list_head *tmp;
+ struct msg_queue *msq = container_of(ipcp, struct msg_queue, q_perm);
expunge_all(msq, -EIDRM);
ss_wakeup(&msq->q_senders, 1);
break;
}
case IPC_RMID:
- freeque(ns, msq);
+ freeque(ns, &msq->q_perm);
break;
}
err = 0;
--- /dev/null
+/*
+ * linux/ipc/namespace.c
+ * Copyright (C) 2006 Pavel Emelyanov <xemul@openvz.org> OpenVZ, SWsoft Inc.
+ */
+
+#include <linux/ipc.h>
+#include <linux/msg.h>
+#include <linux/ipc_namespace.h>
+#include <linux/rcupdate.h>
+#include <linux/nsproxy.h>
+#include <linux/slab.h>
+
+#include "util.h"
+
+static struct ipc_namespace *clone_ipc_ns(struct ipc_namespace *old_ns)
+{
+ struct ipc_namespace *ns;
+
+ ns = kmalloc(sizeof(struct ipc_namespace), GFP_KERNEL);
+ if (ns == NULL)
+ return ERR_PTR(-ENOMEM);
+
+ sem_init_ns(ns);
+ msg_init_ns(ns);
+ shm_init_ns(ns);
+
+ kref_init(&ns->kref);
+ return ns;
+}
+
+struct ipc_namespace *copy_ipcs(unsigned long flags, struct ipc_namespace *ns)
+{
+ struct ipc_namespace *new_ns;
+
+ BUG_ON(!ns);
+ get_ipc_ns(ns);
+
+ if (!(flags & CLONE_NEWIPC))
+ return ns;
+
+ new_ns = clone_ipc_ns(ns);
+
+ put_ipc_ns(ns);
+ return new_ns;
+}
+
+/*
+ * free_ipcs - free all ipcs of one type
+ * @ns: the namespace to remove the ipcs from
+ * @ids: the table of ipcs to free
+ * @free: the function called to free each individual ipc
+ *
+ * Called for each kind of ipc when an ipc_namespace exits.
+ */
+void free_ipcs(struct ipc_namespace *ns, struct ipc_ids *ids,
+ void (*free)(struct ipc_namespace *, struct kern_ipc_perm *))
+{
+ struct kern_ipc_perm *perm;
+ int next_id;
+ int total, in_use;
+
+ down_write(&ids->rw_mutex);
+
+ in_use = ids->in_use;
+
+ for (total = 0, next_id = 0; total < in_use; next_id++) {
+ perm = idr_find(&ids->ipcs_idr, next_id);
+ if (perm == NULL)
+ continue;
+ ipc_lock_by_ptr(perm);
+ free(ns, perm);
+ total++;
+ }
+ up_write(&ids->rw_mutex);
+}
+
+void free_ipc_ns(struct kref *kref)
+{
+ struct ipc_namespace *ns;
+
+ ns = container_of(kref, struct ipc_namespace, kref);
+ sem_exit_ns(ns);
+ msg_exit_ns(ns);
+ shm_exit_ns(ns);
+ kfree(ns);
+}
#include <linux/seq_file.h>
#include <linux/rwsem.h>
#include <linux/nsproxy.h>
+#include <linux/ipc_namespace.h>
#include <asm/uaccess.h>
#include "util.h"
-#define sem_ids(ns) (*((ns)->ids[IPC_SEM_IDS]))
+#define sem_ids(ns) ((ns)->ids[IPC_SEM_IDS])
#define sem_unlock(sma) ipc_unlock(&(sma)->sem_perm)
#define sem_checkid(sma, semid) ipc_checkid(&sma->sem_perm, semid)
#define sem_buildid(id, seq) ipc_buildid(id, seq)
-static struct ipc_ids init_sem_ids;
-
static int newary(struct ipc_namespace *, struct ipc_params *);
-static void freeary(struct ipc_namespace *, struct sem_array *);
+static void freeary(struct ipc_namespace *, struct kern_ipc_perm *);
#ifdef CONFIG_PROC_FS
static int sysvipc_sem_proc_show(struct seq_file *s, void *it);
#endif
#define sc_semopm sem_ctls[2]
#define sc_semmni sem_ctls[3]
-static void __sem_init_ns(struct ipc_namespace *ns, struct ipc_ids *ids)
+void sem_init_ns(struct ipc_namespace *ns)
{
- ns->ids[IPC_SEM_IDS] = ids;
ns->sc_semmsl = SEMMSL;
ns->sc_semmns = SEMMNS;
ns->sc_semopm = SEMOPM;
ns->sc_semmni = SEMMNI;
ns->used_sems = 0;
- ipc_init_ids(ids);
-}
-
-int sem_init_ns(struct ipc_namespace *ns)
-{
- struct ipc_ids *ids;
-
- ids = kmalloc(sizeof(struct ipc_ids), GFP_KERNEL);
- if (ids == NULL)
- return -ENOMEM;
-
- __sem_init_ns(ns, ids);
- return 0;
+ ipc_init_ids(&ns->ids[IPC_SEM_IDS]);
}
+#ifdef CONFIG_IPC_NS
void sem_exit_ns(struct ipc_namespace *ns)
{
- struct sem_array *sma;
- struct kern_ipc_perm *perm;
- int next_id;
- int total, in_use;
-
- down_write(&sem_ids(ns).rw_mutex);
-
- in_use = sem_ids(ns).in_use;
-
- for (total = 0, next_id = 0; total < in_use; next_id++) {
- perm = idr_find(&sem_ids(ns).ipcs_idr, next_id);
- if (perm == NULL)
- continue;
- ipc_lock_by_ptr(perm);
- sma = container_of(perm, struct sem_array, sem_perm);
- freeary(ns, sma);
- total++;
- }
- up_write(&sem_ids(ns).rw_mutex);
-
- kfree(ns->ids[IPC_SEM_IDS]);
- ns->ids[IPC_SEM_IDS] = NULL;
+ free_ipcs(ns, &sem_ids(ns), freeary);
}
+#endif
void __init sem_init (void)
{
- __sem_init_ns(&init_ipc_ns, &init_sem_ids);
+ sem_init_ns(&init_ipc_ns);
ipc_init_proc_interface("sysvipc/sem",
" key semid perms nsems uid gid cuid cgid otime ctime\n",
IPC_SEM_IDS, sysvipc_sem_proc_show);
* as a writer and the spinlock for this semaphore set hold. sem_ids.rw_mutex
* remains locked on exit.
*/
-static void freeary(struct ipc_namespace *ns, struct sem_array *sma)
+static void freeary(struct ipc_namespace *ns, struct kern_ipc_perm *ipcp)
{
struct sem_undo *un;
struct sem_queue *q;
+ struct sem_array *sma = container_of(ipcp, struct sem_array, sem_perm);
/* Invalidate the existing undo structures for this semaphore set.
* (They will be freed without any further action in exit_sem()
}
}
-static int semctl_nolock(struct ipc_namespace *ns, int semid, int semnum,
- int cmd, int version, union semun arg)
+static int semctl_nolock(struct ipc_namespace *ns, int semid,
+ int cmd, int version, union semun arg)
{
int err = -EINVAL;
struct sem_array *sma;
return -EFAULT;
return (max_id < 0) ? 0: max_id;
}
+ case IPC_STAT:
case SEM_STAT:
{
struct semid64_ds tbuf;
int id;
- sma = sem_lock(ns, semid);
- if (IS_ERR(sma))
- return PTR_ERR(sma);
+ if (cmd == SEM_STAT) {
+ sma = sem_lock(ns, semid);
+ if (IS_ERR(sma))
+ return PTR_ERR(sma);
+ id = sma->sem_perm.id;
+ } else {
+ sma = sem_lock_check(ns, semid);
+ if (IS_ERR(sma))
+ return PTR_ERR(sma);
+ id = 0;
+ }
err = -EACCES;
if (ipcperms (&sma->sem_perm, S_IRUGO))
if (err)
goto out_unlock;
- id = sma->sem_perm.id;
-
memset(&tbuf, 0, sizeof(tbuf));
kernel_to_ipc64_perm(&sma->sem_perm, &tbuf.sem_perm);
err = 0;
goto out_unlock;
}
- case IPC_STAT:
- {
- struct semid64_ds tbuf;
- memset(&tbuf,0,sizeof(tbuf));
- kernel_to_ipc64_perm(&sma->sem_perm, &tbuf.sem_perm);
- tbuf.sem_otime = sma->sem_otime;
- tbuf.sem_ctime = sma->sem_ctime;
- tbuf.sem_nsems = sma->sem_nsems;
- sem_unlock(sma);
- if (copy_semid_to_user (arg.buf, &tbuf, version))
- return -EFAULT;
- return 0;
- }
/* GETVAL, GETPID, GETNCTN, GETZCNT, SETVAL: fall-through */
}
err = -EINVAL;
switch(cmd){
case IPC_RMID:
- freeary(ns, sma);
+ freeary(ns, ipcp);
err = 0;
break;
case IPC_SET:
switch(cmd) {
case IPC_INFO:
case SEM_INFO:
+ case IPC_STAT:
case SEM_STAT:
- err = semctl_nolock(ns,semid,semnum,cmd,version,arg);
+ err = semctl_nolock(ns, semid, cmd, version, arg);
return err;
case GETALL:
case GETVAL:
case GETPID:
case GETNCNT:
case GETZCNT:
- case IPC_STAT:
case SETVAL:
case SETALL:
err = semctl_main(ns,semid,semnum,cmd,version,arg);
#include <linux/rwsem.h>
#include <linux/nsproxy.h>
#include <linux/mount.h>
+#include <linux/ipc_namespace.h>
#include <asm/uaccess.h>
static const struct file_operations shm_file_operations;
static struct vm_operations_struct shm_vm_ops;
-static struct ipc_ids init_shm_ids;
-
-#define shm_ids(ns) (*((ns)->ids[IPC_SHM_IDS]))
+#define shm_ids(ns) ((ns)->ids[IPC_SHM_IDS])
#define shm_unlock(shp) \
ipc_unlock(&(shp)->shm_perm)
static int sysvipc_shm_proc_show(struct seq_file *s, void *it);
#endif
-static void __shm_init_ns(struct ipc_namespace *ns, struct ipc_ids *ids)
+void shm_init_ns(struct ipc_namespace *ns)
{
- ns->ids[IPC_SHM_IDS] = ids;
ns->shm_ctlmax = SHMMAX;
ns->shm_ctlall = SHMALL;
ns->shm_ctlmni = SHMMNI;
ns->shm_tot = 0;
- ipc_init_ids(ids);
+ ipc_init_ids(&ns->ids[IPC_SHM_IDS]);
}
/*
* Called with shm_ids.rw_mutex (writer) and the shp structure locked.
* Only shm_ids.rw_mutex remains locked on exit.
*/
-static void do_shm_rmid(struct ipc_namespace *ns, struct shmid_kernel *shp)
+static void do_shm_rmid(struct ipc_namespace *ns, struct kern_ipc_perm *ipcp)
{
+ struct shmid_kernel *shp;
+ shp = container_of(ipcp, struct shmid_kernel, shm_perm);
+
if (shp->shm_nattch){
shp->shm_perm.mode |= SHM_DEST;
/* Do not find it any more */
shm_destroy(ns, shp);
}
-int shm_init_ns(struct ipc_namespace *ns)
-{
- struct ipc_ids *ids;
-
- ids = kmalloc(sizeof(struct ipc_ids), GFP_KERNEL);
- if (ids == NULL)
- return -ENOMEM;
-
- __shm_init_ns(ns, ids);
- return 0;
-}
-
+#ifdef CONFIG_IPC_NS
void shm_exit_ns(struct ipc_namespace *ns)
{
- struct shmid_kernel *shp;
- struct kern_ipc_perm *perm;
- int next_id;
- int total, in_use;
-
- down_write(&shm_ids(ns).rw_mutex);
-
- in_use = shm_ids(ns).in_use;
-
- for (total = 0, next_id = 0; total < in_use; next_id++) {
- perm = idr_find(&shm_ids(ns).ipcs_idr, next_id);
- if (perm == NULL)
- continue;
- ipc_lock_by_ptr(perm);
- shp = container_of(perm, struct shmid_kernel, shm_perm);
- do_shm_rmid(ns, shp);
- total++;
- }
- up_write(&shm_ids(ns).rw_mutex);
-
- kfree(ns->ids[IPC_SHM_IDS]);
- ns->ids[IPC_SHM_IDS] = NULL;
+ free_ipcs(ns, &shm_ids(ns), do_shm_rmid);
}
+#endif
void __init shm_init (void)
{
- __shm_init_ns(&init_ipc_ns, &init_shm_ids);
+ shm_init_ns(&init_ipc_ns);
ipc_init_proc_interface("sysvipc/shm",
" key shmid perms size cpid lpid nattch uid gid cuid cgid atime dtime ctime\n",
IPC_SHM_IDS, sysvipc_shm_proc_show);
if (err)
goto out_unlock_up;
- do_shm_rmid(ns, shp);
+ do_shm_rmid(ns, &shp->shm_perm);
up_write(&shm_ids(ns).rw_mutex);
goto out;
}
#include <linux/audit.h>
#include <linux/nsproxy.h>
#include <linux/rwsem.h>
+#include <linux/ipc_namespace.h>
#include <asm/unistd.h>
},
};
-static struct ipc_namespace *clone_ipc_ns(struct ipc_namespace *old_ns)
-{
- int err;
- struct ipc_namespace *ns;
-
- err = -ENOMEM;
- ns = kmalloc(sizeof(struct ipc_namespace), GFP_KERNEL);
- if (ns == NULL)
- goto err_mem;
-
- err = sem_init_ns(ns);
- if (err)
- goto err_sem;
- err = msg_init_ns(ns);
- if (err)
- goto err_msg;
- err = shm_init_ns(ns);
- if (err)
- goto err_shm;
-
- kref_init(&ns->kref);
- return ns;
-
-err_shm:
- msg_exit_ns(ns);
-err_msg:
- sem_exit_ns(ns);
-err_sem:
- kfree(ns);
-err_mem:
- return ERR_PTR(err);
-}
-
-struct ipc_namespace *copy_ipcs(unsigned long flags, struct ipc_namespace *ns)
-{
- struct ipc_namespace *new_ns;
-
- BUG_ON(!ns);
- get_ipc_ns(ns);
-
- if (!(flags & CLONE_NEWIPC))
- return ns;
-
- new_ns = clone_ipc_ns(ns);
-
- put_ipc_ns(ns);
- return new_ns;
-}
-
-void free_ipc_ns(struct kref *kref)
-{
- struct ipc_namespace *ns;
-
- ns = container_of(kref, struct ipc_namespace, kref);
- sem_exit_ns(ns);
- msg_exit_ns(ns);
- shm_exit_ns(ns);
- kfree(ns);
-}
-
/**
* ipc_init - initialise IPC subsystem
*
* This routine is called by sys_msgget, sys_semget() and sys_shmget()
* when the key is IPC_PRIVATE.
*/
-int ipcget_new(struct ipc_namespace *ns, struct ipc_ids *ids,
+static int ipcget_new(struct ipc_namespace *ns, struct ipc_ids *ids,
struct ipc_ops *ops, struct ipc_params *params)
{
int err;
*
* On success, the ipc id is returned.
*/
-int ipcget_public(struct ipc_namespace *ns, struct ipc_ids *ids,
+static int ipcget_public(struct ipc_namespace *ns, struct ipc_ids *ids,
struct ipc_ops *ops, struct ipc_params *params)
{
struct kern_ipc_perm *ipcp;
return out;
}
+struct kern_ipc_perm *ipc_lock_check_down(struct ipc_ids *ids, int id)
+{
+ struct kern_ipc_perm *out;
+
+ out = ipc_lock_down(ids, id);
+ if (IS_ERR(out))
+ return out;
+
+ if (ipc_checkid(out, id)) {
+ ipc_unlock(out);
+ return ERR_PTR(-EIDRM);
+ }
+
+ return out;
+}
+
+struct kern_ipc_perm *ipc_lock_check(struct ipc_ids *ids, int id)
+{
+ struct kern_ipc_perm *out;
+
+ out = ipc_lock(ids, id);
+ if (IS_ERR(out))
+ return out;
+
+ if (ipc_checkid(out, id)) {
+ ipc_unlock(out);
+ return ERR_PTR(-EIDRM);
+ }
+
+ return out;
+}
+
+/**
+ * ipcget - Common sys_*get() code
+ * @ns : namsepace
+ * @ids : IPC identifier set
+ * @ops : operations to be called on ipc object creation, permission checks
+ * and further checks
+ * @params : the parameters needed by the previous operations.
+ *
+ * Common routine called by sys_msgget(), sys_semget() and sys_shmget().
+ */
+int ipcget(struct ipc_namespace *ns, struct ipc_ids *ids,
+ struct ipc_ops *ops, struct ipc_params *params)
+{
+ if (params->key == IPC_PRIVATE)
+ return ipcget_new(ns, ids, ops, params);
+ else
+ return ipcget_public(ns, ids, ops, params);
+}
+
#ifdef __ARCH_WANT_IPC_PARSE_VERSION
if (ipc && ipc != SEQ_START_TOKEN)
ipc_unlock(ipc);
- return sysvipc_find_ipc(iter->ns->ids[iface->ids], *pos, pos);
+ return sysvipc_find_ipc(&iter->ns->ids[iface->ids], *pos, pos);
}
/*
struct ipc_proc_iface *iface = iter->iface;
struct ipc_ids *ids;
- ids = iter->ns->ids[iface->ids];
+ ids = &iter->ns->ids[iface->ids];
/*
* Take the lock - this will be released by the corresponding
if (ipc && ipc != SEQ_START_TOKEN)
ipc_unlock(ipc);
- ids = iter->ns->ids[iface->ids];
+ ids = &iter->ns->ids[iface->ids];
/* Release the lock we took in start() */
up_read(&ids->rw_mutex);
}
#ifndef _IPC_UTIL_H
#define _IPC_UTIL_H
-#include <linux/idr.h>
#include <linux/err.h>
#define USHRT_MAX 0xffff
void msg_init (void);
void shm_init (void);
-int sem_init_ns(struct ipc_namespace *ns);
-int msg_init_ns(struct ipc_namespace *ns);
-int shm_init_ns(struct ipc_namespace *ns);
+struct ipc_namespace;
+
+void sem_init_ns(struct ipc_namespace *ns);
+void msg_init_ns(struct ipc_namespace *ns);
+void shm_init_ns(struct ipc_namespace *ns);
void sem_exit_ns(struct ipc_namespace *ns);
void msg_exit_ns(struct ipc_namespace *ns);
void shm_exit_ns(struct ipc_namespace *ns);
-struct ipc_ids {
- int in_use;
- unsigned short seq;
- unsigned short seq_max;
- struct rw_semaphore rw_mutex;
- struct idr ipcs_idr;
-};
-
/*
* Structure that holds the parameters needed by the ipc operations
* (see after)
};
struct seq_file;
+struct ipc_ids;
void ipc_init_ids(struct ipc_ids *);
#ifdef CONFIG_PROC_FS
extern void free_msg(struct msg_msg *msg);
extern struct msg_msg *load_msg(const void __user *src, int len);
extern int store_msg(void __user *dest, struct msg_msg *msg, int len);
-extern int ipcget_new(struct ipc_namespace *, struct ipc_ids *,
- struct ipc_ops *, struct ipc_params *);
-extern int ipcget_public(struct ipc_namespace *, struct ipc_ids *,
- struct ipc_ops *, struct ipc_params *);
static inline int ipc_buildid(int id, int seq)
{
rcu_read_unlock();
}
-static inline struct kern_ipc_perm *ipc_lock_check_down(struct ipc_ids *ids,
- int id)
-{
- struct kern_ipc_perm *out;
-
- out = ipc_lock_down(ids, id);
- if (IS_ERR(out))
- return out;
-
- if (ipc_checkid(out, id)) {
- ipc_unlock(out);
- return ERR_PTR(-EIDRM);
- }
-
- return out;
-}
-
-static inline struct kern_ipc_perm *ipc_lock_check(struct ipc_ids *ids,
- int id)
-{
- struct kern_ipc_perm *out;
-
- out = ipc_lock(ids, id);
- if (IS_ERR(out))
- return out;
-
- if (ipc_checkid(out, id)) {
- ipc_unlock(out);
- return ERR_PTR(-EIDRM);
- }
-
- return out;
-}
-
-/**
- * ipcget - Common sys_*get() code
- * @ns : namsepace
- * @ids : IPC identifier set
- * @ops : operations to be called on ipc object creation, permission checks
- * and further checks
- * @params : the parameters needed by the previous operations.
- *
- * Common routine called by sys_msgget(), sys_semget() and sys_shmget().
- */
-static inline int ipcget(struct ipc_namespace *ns, struct ipc_ids *ids,
- struct ipc_ops *ops, struct ipc_params *params)
-{
- if (params->key == IPC_PRIVATE)
- return ipcget_new(ns, ids, ops, params);
- else
- return ipcget_public(ns, ids, ops, params);
-}
+struct kern_ipc_perm *ipc_lock_check_down(struct ipc_ids *ids, int id);
+struct kern_ipc_perm *ipc_lock_check(struct ipc_ids *ids, int id);
+int ipcget(struct ipc_namespace *ns, struct ipc_ids *ids,
+ struct ipc_ops *ops, struct ipc_params *params);
#endif
obj-y = sched.o fork.o exec_domain.o panic.o printk.o profile.o \
exit.o itimer.o time.o softirq.o resource.o \
- sysctl.o capability.o ptrace.o timer.o user.o user_namespace.o \
+ sysctl.o capability.o ptrace.o timer.o user.o \
signal.o sys.o kmod.o workqueue.o pid.o \
rcupdate.o extable.o params.o posix-timers.o \
kthread.o wait.o kfifo.o sys_ni.o posix-cpu-timers.o mutex.o \
hrtimer.o rwsem.o nsproxy.o srcu.o \
- utsname.o notifier.o ksysfs.o pm_qos_params.o
+ notifier.o ksysfs.o pm_qos_params.o
obj-$(CONFIG_SYSCTL) += sysctl_check.o
obj-$(CONFIG_STACKTRACE) += stacktrace.o
obj-$(CONFIG_CGROUP_DEBUG) += cgroup_debug.o
obj-$(CONFIG_CPUSETS) += cpuset.o
obj-$(CONFIG_CGROUP_NS) += ns_cgroup.o
+obj-$(CONFIG_UTS_NS) += utsname.o
+obj-$(CONFIG_USER_NS) += user_namespace.o
+obj-$(CONFIG_PID_NS) += pid_namespace.o
obj-$(CONFIG_IKCONFIG) += configs.o
obj-$(CONFIG_RESOURCE_COUNTERS) += res_counter.o
obj-$(CONFIG_STOP_MACHINE) += stop_machine.o
targets += config_data.h
$(obj)/config_data.h: $(obj)/config_data.gz FORCE
$(call if_changed,ikconfiggz)
+
+$(obj)/time.o: $(obj)/timeconst.h
+
+quiet_cmd_timeconst = TIMEC $@
+ cmd_timeconst = $(PERL) $< $(CONFIG_HZ) > $@
+targets += timeconst.h
+$(obj)/timeconst.h: $(src)/timeconst.pl FORCE
+ $(call if_changed,timeconst)
return error;
}
-void enable_nonboot_cpus(void)
+void __ref enable_nonboot_cpus(void)
{
int cpu, error;
#endif /* CONFIG_PROC_PID_CPUSET */
/* Display task cpus_allowed, mems_allowed in /proc/<pid>/status file. */
-char *cpuset_task_status_allowed(struct task_struct *task, char *buffer)
-{
- buffer += sprintf(buffer, "Cpus_allowed:\t");
- buffer += cpumask_scnprintf(buffer, PAGE_SIZE, task->cpus_allowed);
- buffer += sprintf(buffer, "\n");
- buffer += sprintf(buffer, "Mems_allowed:\t");
- buffer += nodemask_scnprintf(buffer, PAGE_SIZE, task->mems_allowed);
- buffer += sprintf(buffer, "\n");
- return buffer;
+void cpuset_task_status_allowed(struct seq_file *m, struct task_struct *task)
+{
+ seq_printf(m, "Cpus_allowed:\t");
+ m->count += cpumask_scnprintf(m->buf + m->count, m->size - m->count,
+ task->cpus_allowed);
+ seq_printf(m, "\n");
+ seq_printf(m, "Mems_allowed:\t");
+ m->count += nodemask_scnprintf(m->buf + m->count, m->size - m->count,
+ task->mems_allowed);
+ seq_printf(m, "\n");
}
switch_uid(INIT_USER);
}
-void __set_special_pids(pid_t session, pid_t pgrp)
+void __set_special_pids(struct pid *pid)
{
struct task_struct *curr = current->group_leader;
+ pid_t nr = pid_nr(pid);
- if (task_session_nr(curr) != session) {
+ if (task_session(curr) != pid) {
detach_pid(curr, PIDTYPE_SID);
- set_task_session(curr, session);
- attach_pid(curr, PIDTYPE_SID, find_pid(session));
+ attach_pid(curr, PIDTYPE_SID, pid);
+ set_task_session(curr, nr);
}
- if (task_pgrp_nr(curr) != pgrp) {
+ if (task_pgrp(curr) != pid) {
detach_pid(curr, PIDTYPE_PGID);
- set_task_pgrp(curr, pgrp);
- attach_pid(curr, PIDTYPE_PGID, find_pid(pgrp));
+ attach_pid(curr, PIDTYPE_PGID, pid);
+ set_task_pgrp(curr, nr);
}
}
-static void set_special_pids(pid_t session, pid_t pgrp)
+static void set_special_pids(struct pid *pid)
{
write_lock_irq(&tasklist_lock);
- __set_special_pids(session, pgrp);
+ __set_special_pids(pid);
write_unlock_irq(&tasklist_lock);
}
*/
current->flags |= PF_NOFREEZE;
- set_special_pids(1, 1);
+ if (current->nsproxy != &init_nsproxy) {
+ get_nsproxy(&init_nsproxy);
+ switch_task_namespaces(current, &init_nsproxy);
+ }
+ set_special_pids(&init_struct_pid);
proc_clear_tty(current);
/* Block and flush all signals */
current->fs = fs;
atomic_inc(&fs->count);
- if (current->nsproxy != init_task.nsproxy) {
- get_nsproxy(init_task.nsproxy);
- switch_task_namespaces(current, init_task.nsproxy);
- }
-
exit_files(current);
current->files = init_task.files;
atomic_inc(¤t->files->count);
return files;
}
-void fastcall put_files_struct(struct files_struct *files)
+void put_files_struct(struct files_struct *files)
{
struct fdtable *fdt;
struct task_struct *t;
struct pid *pgrp;
- if (signal_pending(tsk) && !(tsk->signal->flags & SIGNAL_GROUP_EXIT)
- && !thread_group_empty(tsk)) {
- /*
- * This occurs when there was a race between our exit
- * syscall and a group signal choosing us as the one to
- * wake up. It could be that we are the only thread
- * alerted to check for pending signals, but another thread
- * should be woken now to take the signal since we will not.
- * Now we'll wake all the threads in the group just to make
- * sure someone gets all the pending signals.
- */
- spin_lock_irq(&tsk->sighand->siglock);
- for (t = next_thread(tsk); t != tsk; t = next_thread(t))
- if (!signal_pending(t) && !(t->flags & PF_EXITING))
- recalc_sigpending_and_wake(t);
- spin_unlock_irq(&tsk->sighand->siglock);
- }
-
/*
* This does two things:
*
zap_pid_ns_processes(tsk->nsproxy->pid_ns);
}
-fastcall NORET_TYPE void do_exit(long code)
+NORET_TYPE void do_exit(long code)
{
struct task_struct *tsk = current;
int group_dead;
schedule();
}
- tsk->flags |= PF_EXITING;
+ exit_signals(tsk); /* sets PF_EXITING */
/*
* tsk->flags are checked in the futex code to protect against
* an exiting task cleaning up the robust pi futexes.
do_group_exit((error_code & 0xff) << 8);
}
-static int eligible_child(pid_t pid, int options, struct task_struct *p)
+static struct pid *task_pid_type(struct task_struct *task, enum pid_type type)
+{
+ struct pid *pid = NULL;
+ if (type == PIDTYPE_PID)
+ pid = task->pids[type].pid;
+ else if (type < PIDTYPE_MAX)
+ pid = task->group_leader->pids[type].pid;
+ return pid;
+}
+
+static int eligible_child(enum pid_type type, struct pid *pid, int options,
+ struct task_struct *p)
{
int err;
- struct pid_namespace *ns;
- ns = current->nsproxy->pid_ns;
- if (pid > 0) {
- if (task_pid_nr_ns(p, ns) != pid)
- return 0;
- } else if (!pid) {
- if (task_pgrp_nr_ns(p, ns) != task_pgrp_vnr(current))
- return 0;
- } else if (pid != -1) {
- if (task_pgrp_nr_ns(p, ns) != -pid)
+ if (type < PIDTYPE_MAX) {
+ if (task_pid_type(p, type) != pid)
return 0;
}
if (((p->exit_signal != SIGCHLD) ^ ((options & __WCLONE) != 0))
&& !(options & __WALL))
return 0;
- /*
- * Do not consider thread group leaders that are
- * in a non-empty thread group:
- */
- if (delay_group_leader(p))
- return 2;
err = security_task_wait(p);
- if (err)
- return err;
+ if (likely(!err))
+ return 1;
- return 1;
+ if (type != PIDTYPE_PID)
+ return 0;
+ /* This child was explicitly requested, abort */
+ read_unlock(&tasklist_lock);
+ return err;
}
static int wait_noreap_copyout(struct task_struct *p, pid_t pid, uid_t uid,
{
unsigned long state;
int retval, status, traced;
- struct pid_namespace *ns;
-
- ns = current->nsproxy->pid_ns;
+ pid_t pid = task_pid_vnr(p);
if (unlikely(noreap)) {
- pid_t pid = task_pid_nr_ns(p, ns);
uid_t uid = p->uid;
int exit_code = p->exit_code;
int why, status;
- if (unlikely(p->exit_state != EXIT_ZOMBIE))
- return 0;
- if (unlikely(p->exit_signal == -1 && p->ptrace == 0))
- return 0;
get_task_struct(p);
read_unlock(&tasklist_lock);
if ((exit_code & 0x7f) == 0) {
retval = put_user(status, &infop->si_status);
}
if (!retval && infop)
- retval = put_user(task_pid_nr_ns(p, ns), &infop->si_pid);
+ retval = put_user(pid, &infop->si_pid);
if (!retval && infop)
retval = put_user(p->uid, &infop->si_uid);
if (!retval)
- retval = task_pid_nr_ns(p, ns);
+ retval = pid;
if (traced) {
write_lock_irq(&tasklist_lock);
* the lock and this task is uninteresting. If we return nonzero, we have
* released the lock and the system call should return.
*/
-static int wait_task_stopped(struct task_struct *p, int delayed_group_leader,
+static int wait_task_stopped(struct task_struct *p,
int noreap, struct siginfo __user *infop,
int __user *stat_addr, struct rusage __user *ru)
{
- int retval, exit_code;
+ int retval, exit_code, why;
+ uid_t uid = 0; /* unneeded, required by compiler */
pid_t pid;
- if (!p->exit_code)
- return 0;
- if (delayed_group_leader && !(p->ptrace & PT_PTRACED) &&
- p->signal->group_stop_count > 0)
+ exit_code = 0;
+ spin_lock_irq(&p->sighand->siglock);
+
+ if (unlikely(!task_is_stopped_or_traced(p)))
+ goto unlock_sig;
+
+ if (!(p->ptrace & PT_PTRACED) && p->signal->group_stop_count > 0)
/*
* A group stop is in progress and this is the group leader.
* We won't report until all threads have stopped.
*/
+ goto unlock_sig;
+
+ exit_code = p->exit_code;
+ if (!exit_code)
+ goto unlock_sig;
+
+ if (!noreap)
+ p->exit_code = 0;
+
+ uid = p->uid;
+unlock_sig:
+ spin_unlock_irq(&p->sighand->siglock);
+ if (!exit_code)
return 0;
/*
* keep holding onto the tasklist_lock while we call getrusage and
* possibly take page faults for user memory.
*/
- pid = task_pid_nr_ns(p, current->nsproxy->pid_ns);
get_task_struct(p);
+ pid = task_pid_vnr(p);
+ why = (p->ptrace & PT_PTRACED) ? CLD_TRAPPED : CLD_STOPPED;
read_unlock(&tasklist_lock);
- if (unlikely(noreap)) {
- uid_t uid = p->uid;
- int why = (p->ptrace & PT_PTRACED) ? CLD_TRAPPED : CLD_STOPPED;
-
- exit_code = p->exit_code;
- if (unlikely(!exit_code) || unlikely(p->exit_state))
- goto bail_ref;
+ if (unlikely(noreap))
return wait_noreap_copyout(p, pid, uid,
why, exit_code,
infop, ru);
- }
-
- write_lock_irq(&tasklist_lock);
-
- /*
- * This uses xchg to be atomic with the thread resuming and setting
- * it. It must also be done with the write lock held to prevent a
- * race with the EXIT_ZOMBIE case.
- */
- exit_code = xchg(&p->exit_code, 0);
- if (unlikely(p->exit_state)) {
- /*
- * The task resumed and then died. Let the next iteration
- * catch it in EXIT_ZOMBIE. Note that exit_code might
- * already be zero here if it resumed and did _exit(0).
- * The task itself is dead and won't touch exit_code again;
- * other processors in this function are locked out.
- */
- p->exit_code = exit_code;
- exit_code = 0;
- }
- if (unlikely(exit_code == 0)) {
- /*
- * Another thread in this function got to it first, or it
- * resumed, or it resumed and then died.
- */
- write_unlock_irq(&tasklist_lock);
-bail_ref:
- put_task_struct(p);
- /*
- * We are returning to the wait loop without having successfully
- * removed the process and having released the lock. We cannot
- * continue, since the "p" task pointer is potentially stale.
- *
- * Return -EAGAIN, and do_wait() will restart the loop from the
- * beginning. Do _not_ re-acquire the lock.
- */
- return -EAGAIN;
- }
-
- /* move to end of parent's list to avoid starvation */
- remove_parent(p);
- add_parent(p);
-
- write_unlock_irq(&tasklist_lock);
retval = ru ? getrusage(p, RUSAGE_BOTH, ru) : 0;
if (!retval && stat_addr)
if (!retval && infop)
retval = put_user(0, &infop->si_errno);
if (!retval && infop)
- retval = put_user((short)((p->ptrace & PT_PTRACED)
- ? CLD_TRAPPED : CLD_STOPPED),
- &infop->si_code);
+ retval = put_user(why, &infop->si_code);
if (!retval && infop)
retval = put_user(exit_code, &infop->si_status);
if (!retval && infop)
retval = put_user(pid, &infop->si_pid);
if (!retval && infop)
- retval = put_user(p->uid, &infop->si_uid);
+ retval = put_user(uid, &infop->si_uid);
if (!retval)
retval = pid;
put_task_struct(p);
int retval;
pid_t pid;
uid_t uid;
- struct pid_namespace *ns;
if (!(p->signal->flags & SIGNAL_STOP_CONTINUED))
return 0;
p->signal->flags &= ~SIGNAL_STOP_CONTINUED;
spin_unlock_irq(&p->sighand->siglock);
- ns = current->nsproxy->pid_ns;
- pid = task_pid_nr_ns(p, ns);
+ pid = task_pid_vnr(p);
uid = p->uid;
get_task_struct(p);
read_unlock(&tasklist_lock);
if (!retval && stat_addr)
retval = put_user(0xffff, stat_addr);
if (!retval)
- retval = task_pid_nr_ns(p, ns);
+ retval = pid;
} else {
retval = wait_noreap_copyout(p, pid, uid,
CLD_CONTINUED, SIGCONT,
return retval;
}
-
-static inline int my_ptrace_child(struct task_struct *p)
-{
- if (!(p->ptrace & PT_PTRACED))
- return 0;
- if (!(p->ptrace & PT_ATTACHED))
- return 1;
- /*
- * This child was PTRACE_ATTACH'd. We should be seeing it only if
- * we are the attacher. If we are the real parent, this is a race
- * inside ptrace_attach. It is waiting for the tasklist_lock,
- * which we have to switch the parent links, but has already set
- * the flags in p->ptrace.
- */
- return (p->parent != p->real_parent);
-}
-
-static long do_wait(pid_t pid, int options, struct siginfo __user *infop,
- int __user *stat_addr, struct rusage __user *ru)
+static long do_wait(enum pid_type type, struct pid *pid, int options,
+ struct siginfo __user *infop, int __user *stat_addr,
+ struct rusage __user *ru)
{
DECLARE_WAITQUEUE(wait, current);
struct task_struct *tsk;
int flag, retval;
- int allowed, denied;
add_wait_queue(¤t->signal->wait_chldexit,&wait);
repeat:
+ /* If there is nothing that can match our critier just get out */
+ retval = -ECHILD;
+ if ((type < PIDTYPE_MAX) && (!pid || hlist_empty(&pid->tasks[type])))
+ goto end;
+
/*
* We will set this flag if we see any child that might later
* match our criteria, even if we are not able to reap it yet.
*/
- flag = 0;
- allowed = denied = 0;
+ flag = retval = 0;
current->state = TASK_INTERRUPTIBLE;
read_lock(&tasklist_lock);
tsk = current;
do {
struct task_struct *p;
- int ret;
list_for_each_entry(p, &tsk->children, sibling) {
- ret = eligible_child(pid, options, p);
+ int ret = eligible_child(type, pid, options, p);
if (!ret)
continue;
if (unlikely(ret < 0)) {
- denied = ret;
- continue;
- }
- allowed = 1;
-
- if (task_is_stopped_or_traced(p)) {
+ retval = ret;
+ } else if (task_is_stopped_or_traced(p)) {
/*
* It's stopped now, so it might later
* continue, exit, or stop again.
- *
- * When we hit the race with PTRACE_ATTACH, we
- * will not report this child. But the race
- * means it has not yet been moved to our
- * ptrace_children list, so we need to set the
- * flag here to avoid a spurious ECHILD when
- * the race happens with the only child.
*/
flag = 1;
+ if (!(p->ptrace & PT_PTRACED) &&
+ !(options & WUNTRACED))
+ continue;
- if (!my_ptrace_child(p)) {
- if (task_is_traced(p))
- continue;
- if (!(options & WUNTRACED))
- continue;
- }
-
- retval = wait_task_stopped(p, ret == 2,
+ retval = wait_task_stopped(p,
(options & WNOWAIT), infop,
stat_addr, ru);
- if (retval == -EAGAIN)
- goto repeat;
- if (retval != 0) /* He released the lock. */
- goto end;
- } else if (p->exit_state == EXIT_ZOMBIE) {
+ } else if (p->exit_state == EXIT_ZOMBIE &&
+ !delay_group_leader(p)) {
/*
- * Eligible but we cannot release it yet:
+ * We don't reap group leaders with subthreads.
*/
- if (ret == 2)
- goto check_continued;
if (!likely(options & WEXITED))
continue;
retval = wait_task_zombie(p,
(options & WNOWAIT), infop,
stat_addr, ru);
- /* He released the lock. */
- if (retval != 0)
- goto end;
} else if (p->exit_state != EXIT_DEAD) {
-check_continued:
/*
* It's running now, so it might later
* exit, stop, or stop and then continue.
retval = wait_task_continued(p,
(options & WNOWAIT), infop,
stat_addr, ru);
- if (retval != 0) /* He released the lock. */
- goto end;
}
+ if (retval != 0) /* tasklist_lock released */
+ goto end;
}
if (!flag) {
list_for_each_entry(p, &tsk->ptrace_children,
- ptrace_list) {
- if (!eligible_child(pid, options, p))
+ ptrace_list) {
+ flag = eligible_child(type, pid, options, p);
+ if (!flag)
continue;
- flag = 1;
- break;
+ if (likely(flag > 0))
+ break;
+ retval = flag;
+ goto end;
}
}
if (options & __WNOTHREAD)
tsk = next_thread(tsk);
BUG_ON(tsk->signal != current->signal);
} while (tsk != current);
-
read_unlock(&tasklist_lock);
+
if (flag) {
- retval = 0;
if (options & WNOHANG)
goto end;
retval = -ERESTARTSYS;
goto repeat;
}
retval = -ECHILD;
- if (unlikely(denied) && !allowed)
- retval = denied;
end:
current->state = TASK_RUNNING;
remove_wait_queue(¤t->signal->wait_chldexit,&wait);
if (infop) {
if (retval > 0)
- retval = 0;
+ retval = 0;
else {
/*
* For a WNOHANG return, clear out all the fields
return retval;
}
-asmlinkage long sys_waitid(int which, pid_t pid,
+asmlinkage long sys_waitid(int which, pid_t upid,
struct siginfo __user *infop, int options,
struct rusage __user *ru)
{
+ struct pid *pid = NULL;
+ enum pid_type type;
long ret;
if (options & ~(WNOHANG|WNOWAIT|WEXITED|WSTOPPED|WCONTINUED))
switch (which) {
case P_ALL:
- pid = -1;
+ type = PIDTYPE_MAX;
break;
case P_PID:
- if (pid <= 0)
+ type = PIDTYPE_PID;
+ if (upid <= 0)
return -EINVAL;
break;
case P_PGID:
- if (pid <= 0)
+ type = PIDTYPE_PGID;
+ if (upid <= 0)
return -EINVAL;
- pid = -pid;
break;
default:
return -EINVAL;
}
- ret = do_wait(pid, options, infop, NULL, ru);
+ if (type < PIDTYPE_MAX)
+ pid = find_get_pid(upid);
+ ret = do_wait(type, pid, options, infop, NULL, ru);
+ put_pid(pid);
/* avoid REGPARM breakage on x86: */
prevent_tail_call(ret);
return ret;
}
-asmlinkage long sys_wait4(pid_t pid, int __user *stat_addr,
+asmlinkage long sys_wait4(pid_t upid, int __user *stat_addr,
int options, struct rusage __user *ru)
{
+ struct pid *pid = NULL;
+ enum pid_type type;
long ret;
if (options & ~(WNOHANG|WUNTRACED|WCONTINUED|
__WNOTHREAD|__WCLONE|__WALL))
return -EINVAL;
- ret = do_wait(pid, options | WEXITED, NULL, stat_addr, ru);
+
+ if (upid == -1)
+ type = PIDTYPE_MAX;
+ else if (upid < 0) {
+ type = PIDTYPE_PGID;
+ pid = find_get_pid(-upid);
+ } else if (upid == 0) {
+ type = PIDTYPE_PGID;
+ pid = get_pid(task_pgrp(current));
+ } else /* upid > 0 */ {
+ type = PIDTYPE_PID;
+ pid = find_get_pid(upid);
+ }
+
+ ret = do_wait(type, pid, options | WEXITED, NULL, stat_addr, ru);
+ put_pid(pid);
/* avoid REGPARM breakage on x86: */
prevent_tail_call(ret);
* is dropped: either by a lazy thread or by
* mmput. Free the page directory and the mm.
*/
-void fastcall __mmdrop(struct mm_struct *mm)
+void __mmdrop(struct mm_struct *mm)
{
BUG_ON(mm == &init_mm);
mm_free_pgd(mm);
hrtimer_init(&sig->real_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
sig->it_real_incr.tv64 = 0;
sig->real_timer.function = it_real_fn;
- sig->tsk = tsk;
sig->it_virt_expires = cputime_zero;
sig->it_virt_incr = cputime_zero;
if (clone_flags & CLONE_NEWPID)
p->nsproxy->pid_ns->child_reaper = p;
+ p->signal->leader_pid = pid;
p->signal->tty = current->signal->tty;
set_task_pgrp(p, task_pgrp_nr(current));
set_task_session(p, task_session_nr(current));
if (!IS_ERR(p)) {
struct completion vfork;
- /*
- * this is enough to call pid_nr_ns here, but this if
- * improves optimisation of regular fork()
- */
- nr = (clone_flags & CLONE_NEWPID) ?
- task_pid_nr_ns(p, current->nsproxy->pid_ns) :
- task_pid_vnr(p);
+ nr = task_pid_vnr(p);
if (clone_flags & CLONE_PARENT_SETTID)
put_user(nr, parent_tidptr);
* Note: The caller is expected to handle the ack, clear, mask and
* unmask issues if necessary.
*/
-void fastcall
+void
handle_simple_irq(unsigned int irq, struct irq_desc *desc)
{
struct irqaction *action;
* it after the associated handler has acknowledged the device, so the
* interrupt line is back to inactive.
*/
-void fastcall
+void
handle_level_irq(unsigned int irq, struct irq_desc *desc)
{
unsigned int cpu = smp_processor_id();
* for modern forms of interrupt handlers, which handle the flow
* details in hardware, transparently.
*/
-void fastcall
+void
handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
{
unsigned int cpu = smp_processor_id();
* the handler was running. If all pending interrupts are handled, the
* loop is left.
*/
-void fastcall
+void
handle_edge_irq(unsigned int irq, struct irq_desc *desc)
{
const unsigned int cpu = smp_processor_id();
*
* Per CPU interrupts on SMP machines without locking requirements
*/
-void fastcall
+void
handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
{
irqreturn_t action_ret;
set_irq_chip(irq, chip);
__set_irq_handler(irq, handle, 0, name);
}
+
+void __init set_irq_noprobe(unsigned int irq)
+{
+ struct irq_desc *desc;
+ unsigned long flags;
+
+ if (irq >= NR_IRQS) {
+ printk(KERN_ERR "Trying to mark IRQ%d non-probeable\n", irq);
+
+ return;
+ }
+
+ desc = irq_desc + irq;
+
+ spin_lock_irqsave(&desc->lock, flags);
+ desc->status |= IRQ_NOPROBE;
+ spin_unlock_irqrestore(&desc->lock, flags);
+}
+
+void __init set_irq_probe(unsigned int irq)
+{
+ struct irq_desc *desc;
+ unsigned long flags;
+
+ if (irq >= NR_IRQS) {
+ printk(KERN_ERR "Trying to mark IRQ%d probeable\n", irq);
+
+ return;
+ }
+
+ desc = irq_desc + irq;
+
+ spin_lock_irqsave(&desc->lock, flags);
+ desc->status &= ~IRQ_NOPROBE;
+ spin_unlock_irqrestore(&desc->lock, flags);
+}
*
* Handles spurious and unhandled IRQ's. It also prints a debugmessage.
*/
-void fastcall
+void
handle_bad_irq(unsigned int irq, struct irq_desc *desc)
{
print_irq_desc(irq, desc);
* This is the original x86 implementation which is used for every
* interrupt type.
*/
-fastcall unsigned int __do_IRQ(unsigned int irq)
+unsigned int __do_IRQ(unsigned int irq)
{
struct irq_desc *desc = irq_desc + irq;
struct irqaction *action;
struct signal_struct *sig =
container_of(timer, struct signal_struct, real_timer);
- send_group_sig_info(SIGALRM, SEND_SIG_PRIV, sig->tsk);
+ kill_pid_info(SIGALRM, SEND_SIG_PRIV, sig->leader_pid);
return HRTIMER_NORESTART;
}
#include <asm/semaphore.h>
#include <asm/cacheflush.h>
#include <linux/license.h>
+#include <asm/sections.h>
#if 0
#define DEBUGP printk
}
}
DEBUGP("Failed to find symbol %s\n", name);
- return 0;
+ return -ENOENT;
}
/* Search for module by name: must hold module_mutex. */
return val;
}
-/* Created by linker magic */
-extern char __per_cpu_start[], __per_cpu_end[];
-
static void *percpu_modalloc(unsigned long size, unsigned long align,
const char *name)
{
const unsigned long *crc;
preempt_disable();
- if (!__find_symbol(symbol, &owner, &crc, 1))
+ if (IS_ERR_VALUE(__find_symbol(symbol, &owner, &crc, 1)))
BUG();
module_put(owner);
preempt_enable();
const unsigned long *crc;
struct module *owner;
- if (!__find_symbol("struct_module", &owner, &crc, 1))
+ if (IS_ERR_VALUE(__find_symbol("struct_module",
+ &owner, &crc, 1)))
BUG();
return check_version(sechdrs, versindex, "struct_module", mod,
crc);
ret = __find_symbol(name, &owner, &crc,
!(mod->taints & TAINT_PROPRIETARY_MODULE));
- if (ret) {
+ if (!IS_ERR_VALUE(ret)) {
/* use_module can fail due to OOM,
or module initialization or unloading */
if (!check_version(sechdrs, versindex, name, mod, crc) ||
!use_module(mod, owner))
- ret = 0;
+ ret = -EINVAL;
}
return ret;
}
preempt_disable();
value = __find_symbol(symbol, &owner, &crc, 1);
- if (value && strong_try_module_get(owner) != 0)
+ if (IS_ERR_VALUE(value))
+ value = 0;
+ else if (strong_try_module_get(owner))
value = 0;
preempt_enable();
const unsigned long *crc;
for (i = 0; i < mod->num_syms; i++)
- if (__find_symbol(mod->syms[i].name, &owner, &crc, 1)) {
+ if (!IS_ERR_VALUE(__find_symbol(mod->syms[i].name,
+ &owner, &crc, 1))) {
name = mod->syms[i].name;
ret = -ENOEXEC;
goto dup;
}
for (i = 0; i < mod->num_gpl_syms; i++)
- if (__find_symbol(mod->gpl_syms[i].name, &owner, &crc, 1)) {
+ if (!IS_ERR_VALUE(__find_symbol(mod->gpl_syms[i].name,
+ &owner, &crc, 1))) {
name = mod->gpl_syms[i].name;
ret = -ENOEXEC;
goto dup;
strtab + sym[i].st_name, mod);
/* Ok if resolved. */
- if (sym[i].st_value != 0)
+ if (!IS_ERR_VALUE(sym[i].st_value))
break;
/* Ok if weak. */
if (ELF_ST_BIND(sym[i].st_info) == STB_WEAK)
/* For kallsyms to ask for address resolution. NULL means not found. Careful
* not to lock to avoid deadlock on oopses, simply disable preemption. */
-char *module_address_lookup(unsigned long addr,
+const char *module_address_lookup(unsigned long addr,
unsigned long *size,
unsigned long *offset,
char **modname,
ret = namebuf;
}
preempt_enable();
- return (char *)ret;
+ return ret;
}
int lookup_module_symbol_name(unsigned long addr, char *symname)
* use of the mutex is forbidden. The mutex must not be locked when
* this function is called.
*/
-void fastcall mutex_destroy(struct mutex *lock)
+void mutex_destroy(struct mutex *lock)
{
DEBUG_LOCKS_WARN_ON(mutex_is_locked(lock));
lock->magic = NULL;
* We also put the fastpath first in the kernel image, to make sure the
* branch is predicted by the CPU as default-untaken.
*/
-static void fastcall noinline __sched
+static void noinline __sched
__mutex_lock_slowpath(atomic_t *lock_count);
/***
*
* This function is similar to (but not equivalent to) down().
*/
-void inline fastcall __sched mutex_lock(struct mutex *lock)
+void inline __sched mutex_lock(struct mutex *lock)
{
might_sleep();
/*
EXPORT_SYMBOL(mutex_lock);
#endif
-static void fastcall noinline __sched
-__mutex_unlock_slowpath(atomic_t *lock_count);
+static noinline void __sched __mutex_unlock_slowpath(atomic_t *lock_count);
/***
* mutex_unlock - release the mutex
*
* This function is similar to (but not equivalent to) up().
*/
-void fastcall __sched mutex_unlock(struct mutex *lock)
+void __sched mutex_unlock(struct mutex *lock)
{
/*
* The unlocking fastpath is the 0->1 transition from 'locked'
/*
* Release the lock, slowpath:
*/
-static fastcall inline void
+static inline void
__mutex_unlock_common_slowpath(atomic_t *lock_count, int nested)
{
struct mutex *lock = container_of(lock_count, struct mutex, count);
/*
* Release the lock, slowpath:
*/
-static fastcall noinline void
+static noinline void
__mutex_unlock_slowpath(atomic_t *lock_count)
{
__mutex_unlock_common_slowpath(lock_count, 1);
* Here come the less common (and hence less performance-critical) APIs:
* mutex_lock_interruptible() and mutex_trylock().
*/
-static int fastcall noinline __sched
+static noinline int __sched
__mutex_lock_killable_slowpath(atomic_t *lock_count);
-static noinline int fastcall __sched
+static noinline int __sched
__mutex_lock_interruptible_slowpath(atomic_t *lock_count);
/***
*
* This function is similar to (but not equivalent to) down_interruptible().
*/
-int fastcall __sched mutex_lock_interruptible(struct mutex *lock)
+int __sched mutex_lock_interruptible(struct mutex *lock)
{
might_sleep();
return __mutex_fastpath_lock_retval
EXPORT_SYMBOL(mutex_lock_interruptible);
-int fastcall __sched mutex_lock_killable(struct mutex *lock)
+int __sched mutex_lock_killable(struct mutex *lock)
{
might_sleep();
return __mutex_fastpath_lock_retval
}
EXPORT_SYMBOL(mutex_lock_killable);
-static void fastcall noinline __sched
+static noinline void __sched
__mutex_lock_slowpath(atomic_t *lock_count)
{
struct mutex *lock = container_of(lock_count, struct mutex, count);
__mutex_lock_common(lock, TASK_UNINTERRUPTIBLE, 0, _RET_IP_);
}
-static int fastcall noinline __sched
+static noinline int __sched
__mutex_lock_killable_slowpath(atomic_t *lock_count)
{
struct mutex *lock = container_of(lock_count, struct mutex, count);
return __mutex_lock_common(lock, TASK_KILLABLE, 0, _RET_IP_);
}
-static noinline int fastcall __sched
+static noinline int __sched
__mutex_lock_interruptible_slowpath(atomic_t *lock_count)
{
struct mutex *lock = container_of(lock_count, struct mutex, count);
* This function must not be used in interrupt context. The
* mutex must be released by the same task that acquired it.
*/
-int fastcall __sched mutex_trylock(struct mutex *lock)
+int __sched mutex_trylock(struct mutex *lock)
{
return __mutex_fastpath_trylock(&lock->count,
__mutex_trylock_slowpath);
#include <linux/utsname.h>
#include <linux/pid_namespace.h>
#include <net/net_namespace.h>
+#include <linux/ipc_namespace.h>
static struct kmem_cache *nsproxy_cachep;
#define STANDARD_PARAM_DEF(name, type, format, tmptype, strtolfn) \
int param_set_##name(const char *val, struct kernel_param *kp) \
{ \
- char *endp; \
tmptype l; \
+ int ret; \
\
if (!val) return -EINVAL; \
- l = strtolfn(val, &endp, 0); \
- if (endp == val || ((type)l != l)) \
+ ret = strtolfn(val, 0, &l); \
+ if (ret == -EINVAL || ((type)l != l)) \
return -EINVAL; \
*((type *)kp->arg) = l; \
return 0; \
return sprintf(buffer, format, *((type *)kp->arg)); \
}
-STANDARD_PARAM_DEF(byte, unsigned char, "%c", unsigned long, simple_strtoul);
-STANDARD_PARAM_DEF(short, short, "%hi", long, simple_strtol);
-STANDARD_PARAM_DEF(ushort, unsigned short, "%hu", unsigned long, simple_strtoul);
-STANDARD_PARAM_DEF(int, int, "%i", long, simple_strtol);
-STANDARD_PARAM_DEF(uint, unsigned int, "%u", unsigned long, simple_strtoul);
-STANDARD_PARAM_DEF(long, long, "%li", long, simple_strtol);
-STANDARD_PARAM_DEF(ulong, unsigned long, "%lu", unsigned long, simple_strtoul);
+STANDARD_PARAM_DEF(byte, unsigned char, "%c", unsigned long, strict_strtoul);
+STANDARD_PARAM_DEF(short, short, "%hi", long, strict_strtol);
+STANDARD_PARAM_DEF(ushort, unsigned short, "%hu", unsigned long, strict_strtoul);
+STANDARD_PARAM_DEF(int, int, "%i", long, strict_strtol);
+STANDARD_PARAM_DEF(uint, unsigned int, "%u", unsigned long, strict_strtoul);
+STANDARD_PARAM_DEF(long, long, "%li", long, strict_strtol);
+STANDARD_PARAM_DEF(ulong, unsigned long, "%lu", unsigned long, strict_strtoul);
int param_set_charp(const char *val, struct kernel_param *kp)
{
static struct hlist_head *pid_hash;
static int pidhash_shift;
struct pid init_struct_pid = INIT_STRUCT_PID;
-static struct kmem_cache *pid_ns_cachep;
int pid_max = PID_MAX_DEFAULT;
static __cacheline_aligned_in_smp DEFINE_SPINLOCK(pidmap_lock);
-static fastcall void free_pidmap(struct pid_namespace *pid_ns, int pid)
+static void free_pidmap(struct pid_namespace *pid_ns, int pid)
{
struct pidmap *map = pid_ns->pidmap + pid / BITS_PER_PAGE;
int offset = pid & BITS_PER_PAGE_MASK;
return -1;
}
-static int next_pidmap(struct pid_namespace *pid_ns, int last)
+int next_pidmap(struct pid_namespace *pid_ns, int last)
{
int offset;
struct pidmap *map, *end;
return -1;
}
-fastcall void put_pid(struct pid *pid)
+void put_pid(struct pid *pid)
{
struct pid_namespace *ns;
put_pid(pid);
}
-fastcall void free_pid(struct pid *pid)
+void free_pid(struct pid *pid)
{
/* We can be called with write_lock_irq(&tasklist_lock) held */
int i;
goto out;
}
-struct pid * fastcall find_pid_ns(int nr, struct pid_namespace *ns)
+struct pid *find_pid_ns(int nr, struct pid_namespace *ns)
{
struct hlist_node *elem;
struct upid *pnr;
/*
* attach_pid() must be called with the tasklist_lock write-held.
*/
-int fastcall attach_pid(struct task_struct *task, enum pid_type type,
+int attach_pid(struct task_struct *task, enum pid_type type,
struct pid *pid)
{
struct pid_link *link;
return 0;
}
-void fastcall detach_pid(struct task_struct *task, enum pid_type type)
+void detach_pid(struct task_struct *task, enum pid_type type)
{
struct pid_link *link;
struct pid *pid;
}
/* transfer_pid is an optimization of attach_pid(new), detach_pid(old) */
-void fastcall transfer_pid(struct task_struct *old, struct task_struct *new,
+void transfer_pid(struct task_struct *old, struct task_struct *new,
enum pid_type type)
{
new->pids[type].pid = old->pids[type].pid;
old->pids[type].pid = NULL;
}
-struct task_struct * fastcall pid_task(struct pid *pid, enum pid_type type)
+struct task_struct *pid_task(struct pid *pid, enum pid_type type)
{
struct task_struct *result = NULL;
if (pid) {
return pid;
}
-struct task_struct *fastcall get_pid_task(struct pid *pid, enum pid_type type)
+struct task_struct *get_pid_task(struct pid *pid, enum pid_type type)
{
struct task_struct *result;
rcu_read_lock();
return nr;
}
+pid_t pid_vnr(struct pid *pid)
+{
+ return pid_nr_ns(pid, current->nsproxy->pid_ns);
+}
+EXPORT_SYMBOL_GPL(pid_vnr);
+
pid_t task_pid_nr_ns(struct task_struct *tsk, struct pid_namespace *ns)
{
return pid_nr_ns(task_pid(tsk), ns);
}
EXPORT_SYMBOL_GPL(find_get_pid);
-struct pid_cache {
- int nr_ids;
- char name[16];
- struct kmem_cache *cachep;
- struct list_head list;
-};
-
-static LIST_HEAD(pid_caches_lh);
-static DEFINE_MUTEX(pid_caches_mutex);
-
-/*
- * creates the kmem cache to allocate pids from.
- * @nr_ids: the number of numerical ids this pid will have to carry
- */
-
-static struct kmem_cache *create_pid_cachep(int nr_ids)
-{
- struct pid_cache *pcache;
- struct kmem_cache *cachep;
-
- mutex_lock(&pid_caches_mutex);
- list_for_each_entry (pcache, &pid_caches_lh, list)
- if (pcache->nr_ids == nr_ids)
- goto out;
-
- pcache = kmalloc(sizeof(struct pid_cache), GFP_KERNEL);
- if (pcache == NULL)
- goto err_alloc;
-
- snprintf(pcache->name, sizeof(pcache->name), "pid_%d", nr_ids);
- cachep = kmem_cache_create(pcache->name,
- sizeof(struct pid) + (nr_ids - 1) * sizeof(struct upid),
- 0, SLAB_HWCACHE_ALIGN, NULL);
- if (cachep == NULL)
- goto err_cachep;
-
- pcache->nr_ids = nr_ids;
- pcache->cachep = cachep;
- list_add(&pcache->list, &pid_caches_lh);
-out:
- mutex_unlock(&pid_caches_mutex);
- return pcache->cachep;
-
-err_cachep:
- kfree(pcache);
-err_alloc:
- mutex_unlock(&pid_caches_mutex);
- return NULL;
-}
-
-#ifdef CONFIG_PID_NS
-static struct pid_namespace *create_pid_namespace(int level)
-{
- struct pid_namespace *ns;
- int i;
-
- ns = kmem_cache_alloc(pid_ns_cachep, GFP_KERNEL);
- if (ns == NULL)
- goto out;
-
- ns->pidmap[0].page = kzalloc(PAGE_SIZE, GFP_KERNEL);
- if (!ns->pidmap[0].page)
- goto out_free;
-
- ns->pid_cachep = create_pid_cachep(level + 1);
- if (ns->pid_cachep == NULL)
- goto out_free_map;
-
- kref_init(&ns->kref);
- ns->last_pid = 0;
- ns->child_reaper = NULL;
- ns->level = level;
-
- set_bit(0, ns->pidmap[0].page);
- atomic_set(&ns->pidmap[0].nr_free, BITS_PER_PAGE - 1);
-
- for (i = 1; i < PIDMAP_ENTRIES; i++) {
- ns->pidmap[i].page = 0;
- atomic_set(&ns->pidmap[i].nr_free, BITS_PER_PAGE);
- }
-
- return ns;
-
-out_free_map:
- kfree(ns->pidmap[0].page);
-out_free:
- kmem_cache_free(pid_ns_cachep, ns);
-out:
- return ERR_PTR(-ENOMEM);
-}
-
-static void destroy_pid_namespace(struct pid_namespace *ns)
-{
- int i;
-
- for (i = 0; i < PIDMAP_ENTRIES; i++)
- kfree(ns->pidmap[i].page);
- kmem_cache_free(pid_ns_cachep, ns);
-}
-
-struct pid_namespace *copy_pid_ns(unsigned long flags, struct pid_namespace *old_ns)
-{
- struct pid_namespace *new_ns;
-
- BUG_ON(!old_ns);
- new_ns = get_pid_ns(old_ns);
- if (!(flags & CLONE_NEWPID))
- goto out;
-
- new_ns = ERR_PTR(-EINVAL);
- if (flags & CLONE_THREAD)
- goto out_put;
-
- new_ns = create_pid_namespace(old_ns->level + 1);
- if (!IS_ERR(new_ns))
- new_ns->parent = get_pid_ns(old_ns);
-
-out_put:
- put_pid_ns(old_ns);
-out:
- return new_ns;
-}
-
-void free_pid_ns(struct kref *kref)
-{
- struct pid_namespace *ns, *parent;
-
- ns = container_of(kref, struct pid_namespace, kref);
-
- parent = ns->parent;
- destroy_pid_namespace(ns);
-
- if (parent != NULL)
- put_pid_ns(parent);
-}
-#endif /* CONFIG_PID_NS */
-
-void zap_pid_ns_processes(struct pid_namespace *pid_ns)
-{
- int nr;
- int rc;
-
- /*
- * The last thread in the cgroup-init thread group is terminating.
- * Find remaining pid_ts in the namespace, signal and wait for them
- * to exit.
- *
- * Note: This signals each threads in the namespace - even those that
- * belong to the same thread group, To avoid this, we would have
- * to walk the entire tasklist looking a processes in this
- * namespace, but that could be unnecessarily expensive if the
- * pid namespace has just a few processes. Or we need to
- * maintain a tasklist for each pid namespace.
- *
- */
- read_lock(&tasklist_lock);
- nr = next_pidmap(pid_ns, 1);
- while (nr > 0) {
- kill_proc_info(SIGKILL, SEND_SIG_PRIV, nr);
- nr = next_pidmap(pid_ns, nr);
- }
- read_unlock(&tasklist_lock);
-
- do {
- clear_thread_flag(TIF_SIGPENDING);
- rc = sys_wait4(-1, NULL, __WALL, NULL);
- } while (rc != -ECHILD);
-
-
- /* Child reaper for the pid namespace is going away */
- pid_ns->child_reaper = NULL;
- return;
-}
-
/*
* The pid hash table is scaled according to the amount of memory in the
* machine. From a minimum of 16 slots up to 4096 slots at one gigabyte or
set_bit(0, init_pid_ns.pidmap[0].page);
atomic_dec(&init_pid_ns.pidmap[0].nr_free);
- init_pid_ns.pid_cachep = create_pid_cachep(1);
- if (init_pid_ns.pid_cachep == NULL)
- panic("Can't create pid_1 cachep\n");
-
- pid_ns_cachep = KMEM_CACHE(pid_namespace, SLAB_PANIC);
+ init_pid_ns.pid_cachep = KMEM_CACHE(pid,
+ SLAB_HWCACHE_ALIGN | SLAB_PANIC);
}
--- /dev/null
+/*
+ * Pid namespaces
+ *
+ * Authors:
+ * (C) 2007 Pavel Emelyanov <xemul@openvz.org>, OpenVZ, SWsoft Inc.
+ * (C) 2007 Sukadev Bhattiprolu <sukadev@us.ibm.com>, IBM
+ * Many thanks to Oleg Nesterov for comments and help
+ *
+ */
+
+#include <linux/pid.h>
+#include <linux/pid_namespace.h>
+#include <linux/syscalls.h>
+#include <linux/err.h>
+
+#define BITS_PER_PAGE (PAGE_SIZE*8)
+
+struct pid_cache {
+ int nr_ids;
+ char name[16];
+ struct kmem_cache *cachep;
+ struct list_head list;
+};
+
+static LIST_HEAD(pid_caches_lh);
+static DEFINE_MUTEX(pid_caches_mutex);
+static struct kmem_cache *pid_ns_cachep;
+
+/*
+ * creates the kmem cache to allocate pids from.
+ * @nr_ids: the number of numerical ids this pid will have to carry
+ */
+
+static struct kmem_cache *create_pid_cachep(int nr_ids)
+{
+ struct pid_cache *pcache;
+ struct kmem_cache *cachep;
+
+ mutex_lock(&pid_caches_mutex);
+ list_for_each_entry(pcache, &pid_caches_lh, list)
+ if (pcache->nr_ids == nr_ids)
+ goto out;
+
+ pcache = kmalloc(sizeof(struct pid_cache), GFP_KERNEL);
+ if (pcache == NULL)
+ goto err_alloc;
+
+ snprintf(pcache->name, sizeof(pcache->name), "pid_%d", nr_ids);
+ cachep = kmem_cache_create(pcache->name,
+ sizeof(struct pid) + (nr_ids - 1) * sizeof(struct upid),
+ 0, SLAB_HWCACHE_ALIGN, NULL);
+ if (cachep == NULL)
+ goto err_cachep;
+
+ pcache->nr_ids = nr_ids;
+ pcache->cachep = cachep;
+ list_add(&pcache->list, &pid_caches_lh);
+out:
+ mutex_unlock(&pid_caches_mutex);
+ return pcache->cachep;
+
+err_cachep:
+ kfree(pcache);
+err_alloc:
+ mutex_unlock(&pid_caches_mutex);
+ return NULL;
+}
+
+static struct pid_namespace *create_pid_namespace(int level)
+{
+ struct pid_namespace *ns;
+ int i;
+
+ ns = kmem_cache_alloc(pid_ns_cachep, GFP_KERNEL);
+ if (ns == NULL)
+ goto out;
+
+ ns->pidmap[0].page = kzalloc(PAGE_SIZE, GFP_KERNEL);
+ if (!ns->pidmap[0].page)
+ goto out_free;
+
+ ns->pid_cachep = create_pid_cachep(level + 1);
+ if (ns->pid_cachep == NULL)
+ goto out_free_map;
+
+ kref_init(&ns->kref);
+ ns->last_pid = 0;
+ ns->child_reaper = NULL;
+ ns->level = level;
+
+ set_bit(0, ns->pidmap[0].page);
+ atomic_set(&ns->pidmap[0].nr_free, BITS_PER_PAGE - 1);
+
+ for (i = 1; i < PIDMAP_ENTRIES; i++) {
+ ns->pidmap[i].page = 0;
+ atomic_set(&ns->pidmap[i].nr_free, BITS_PER_PAGE);
+ }
+
+ return ns;
+
+out_free_map:
+ kfree(ns->pidmap[0].page);
+out_free:
+ kmem_cache_free(pid_ns_cachep, ns);
+out:
+ return ERR_PTR(-ENOMEM);
+}
+
+static void destroy_pid_namespace(struct pid_namespace *ns)
+{
+ int i;
+
+ for (i = 0; i < PIDMAP_ENTRIES; i++)
+ kfree(ns->pidmap[i].page);
+ kmem_cache_free(pid_ns_cachep, ns);
+}
+
+struct pid_namespace *copy_pid_ns(unsigned long flags, struct pid_namespace *old_ns)
+{
+ struct pid_namespace *new_ns;
+
+ BUG_ON(!old_ns);
+ new_ns = get_pid_ns(old_ns);
+ if (!(flags & CLONE_NEWPID))
+ goto out;
+
+ new_ns = ERR_PTR(-EINVAL);
+ if (flags & CLONE_THREAD)
+ goto out_put;
+
+ new_ns = create_pid_namespace(old_ns->level + 1);
+ if (!IS_ERR(new_ns))
+ new_ns->parent = get_pid_ns(old_ns);
+
+out_put:
+ put_pid_ns(old_ns);
+out:
+ return new_ns;
+}
+
+void free_pid_ns(struct kref *kref)
+{
+ struct pid_namespace *ns, *parent;
+
+ ns = container_of(kref, struct pid_namespace, kref);
+
+ parent = ns->parent;
+ destroy_pid_namespace(ns);
+
+ if (parent != NULL)
+ put_pid_ns(parent);
+}
+
+void zap_pid_ns_processes(struct pid_namespace *pid_ns)
+{
+ int nr;
+ int rc;
+
+ /*
+ * The last thread in the cgroup-init thread group is terminating.
+ * Find remaining pid_ts in the namespace, signal and wait for them
+ * to exit.
+ *
+ * Note: This signals each threads in the namespace - even those that
+ * belong to the same thread group, To avoid this, we would have
+ * to walk the entire tasklist looking a processes in this
+ * namespace, but that could be unnecessarily expensive if the
+ * pid namespace has just a few processes. Or we need to
+ * maintain a tasklist for each pid namespace.
+ *
+ */
+ read_lock(&tasklist_lock);
+ nr = next_pidmap(pid_ns, 1);
+ while (nr > 0) {
+ kill_proc_info(SIGKILL, SEND_SIG_PRIV, nr);
+ nr = next_pidmap(pid_ns, nr);
+ }
+ read_unlock(&tasklist_lock);
+
+ do {
+ clear_thread_flag(TIF_SIGPENDING);
+ rc = sys_wait4(-1, NULL, __WALL, NULL);
+ } while (rc != -ECHILD);
+
+
+ /* Child reaper for the pid namespace is going away */
+ pid_ns->child_reaper = NULL;
+ return;
+}
+
+static __init int pid_namespaces_init(void)
+{
+ pid_ns_cachep = KMEM_CACHE(pid_namespace, SLAB_PANIC);
+ return 0;
+}
+
+__initcall(pid_namespaces_init);
return 0;
read_lock(&tasklist_lock);
- p = find_task_by_pid(pid);
+ p = find_task_by_vpid(pid);
if (!p || !(CPUCLOCK_PERTHREAD(which_clock) ?
same_thread_group(p, current) : thread_group_leader(p))) {
error = -EINVAL;
*/
struct task_struct *p;
rcu_read_lock();
- p = find_task_by_pid(pid);
+ p = find_task_by_vpid(pid);
if (p) {
if (CPUCLOCK_PERTHREAD(which_clock)) {
if (same_thread_group(p, current)) {
if (pid == 0) {
p = current;
} else {
- p = find_task_by_pid(pid);
+ p = find_task_by_vpid(pid);
if (p && !same_thread_group(p, current))
p = NULL;
}
if (pid == 0) {
p = current->group_leader;
} else {
- p = find_task_by_pid(pid);
+ p = find_task_by_vpid(pid);
if (p && !thread_group_leader(p))
p = NULL;
}
struct task_struct *rtn = current->group_leader;
if ((event->sigev_notify & SIGEV_THREAD_ID ) &&
- (!(rtn = find_task_by_pid(event->sigev_notify_thread_id)) ||
+ (!(rtn = find_task_by_vpid(event->sigev_notify_thread_id)) ||
!same_thread_group(rtn, current) ||
(event->sigev_notify & ~SIGEV_THREAD_ID) != SIGEV_SIGNAL))
return NULL;
#include <linux/security.h>
#include <linux/bootmem.h>
#include <linux/syscalls.h>
-#include <linux/jiffies.h>
#include <asm/uaccess.h>
#endif
module_param_named(time, printk_time, bool, S_IRUGO | S_IWUSR);
-static int __init printk_time_setup(char *str)
-{
- if (*str)
- return 0;
- printk_time = 1;
- printk(KERN_NOTICE "The 'time' option is deprecated and "
- "is scheduled for removal in early 2008\n");
- printk(KERN_NOTICE "Use 'printk.time=<value>' instead\n");
- return 1;
-}
-
-__setup("time", printk_time_setup);
-
/* Check if we have any console registered that can be called early in boot. */
static int have_callable_console(void)
{
return;
}
+#if defined CONFIG_PRINTK
/*
* printk rate limiting, lifted from the networking subsystem.
*
return false;
}
EXPORT_SYMBOL(printk_timed_ratelimit);
+#endif
#include <linux/mm.h>
#include <linux/cpumask.h>
#include <linux/cpu.h>
-#include <linux/profile.h>
#include <linux/highmem.h>
#include <linux/mutex.h>
#include <asm/sections.h>
* be changed by us so it's not changing right after this.
*/
read_lock(&tasklist_lock);
- if ((child->ptrace & PT_PTRACED) && child->parent == current &&
- (!(child->ptrace & PT_ATTACHED) || child->real_parent != current)
- && child->signal != NULL) {
+ if ((child->ptrace & PT_PTRACED) && child->parent == current) {
ret = 0;
+ /*
+ * child->sighand can't be NULL, release_task()
+ * does ptrace_unlink() before __exit_signal().
+ */
spin_lock_irq(&child->sighand->siglock);
if (task_is_stopped(child))
child->state = TASK_TRACED;
goto bad;
/* Go */
- task->ptrace |= PT_PTRACED | ((task->real_parent != current)
- ? PT_ATTACHED : 0);
+ task->ptrace |= PT_PTRACED;
if (capable(CAP_SYS_PTRACE))
task->ptrace |= PT_PTRACE_CAP;
EXPORT_SYMBOL(release_resource);
-#ifdef CONFIG_MEMORY_HOTPLUG
+#if defined(CONFIG_MEMORY_HOTPLUG) && !defined(CONFIG_ARCH_HAS_WALK_MEMORY)
/*
* Finds the lowest memory reosurce exists within [res->start.res->end)
* the caller must specify res->start, res->end, res->flags.
task = rt_mutex_owner(act_waiter->lock);
if (task && task != current) {
- act_waiter->deadlock_task_pid = task->pid;
+ act_waiter->deadlock_task_pid = get_pid(task_pid(task));
act_waiter->deadlock_lock = lock;
}
}
if (!waiter->deadlock_lock || !rt_trace_on)
return;
- task = find_task_by_pid(waiter->deadlock_task_pid);
- if (!task)
+ rcu_read_lock();
+ task = pid_task(waiter->deadlock_task_pid, PIDTYPE_PID);
+ if (!task) {
+ rcu_read_unlock();
return;
+ }
TRACE_OFF_NOLOCK();
current->comm, task_pid_nr(current));
dump_stack();
debug_show_all_locks();
+ rcu_read_unlock();
printk("[ turning off deadlock detection."
"Please report this trace. ]\n\n");
memset(waiter, 0x11, sizeof(*waiter));
plist_node_init(&waiter->list_entry, MAX_PRIO);
plist_node_init(&waiter->pi_list_entry, MAX_PRIO);
+ waiter->deadlock_task_pid = NULL;
}
void debug_rt_mutex_free_waiter(struct rt_mutex_waiter *waiter)
{
+ put_pid(waiter->deadlock_task_pid);
TRACE_WARN_ON(!plist_node_empty(&waiter->list_entry));
TRACE_WARN_ON(!plist_node_empty(&waiter->pi_list_entry));
TRACE_WARN_ON(waiter->task);
struct rt_mutex *lock;
#ifdef CONFIG_DEBUG_RT_MUTEXES
unsigned long ip;
- pid_t deadlock_task_pid;
+ struct pid *deadlock_task_pid;
struct rt_mutex *deadlock_lock;
#endif
};
return success;
}
-int fastcall wake_up_process(struct task_struct *p)
+int wake_up_process(struct task_struct *p)
{
return try_to_wake_up(p, TASK_ALL, 0);
}
EXPORT_SYMBOL(wake_up_process);
-int fastcall wake_up_state(struct task_struct *p, unsigned int state)
+int wake_up_state(struct task_struct *p, unsigned int state)
{
return try_to_wake_up(p, state, 0);
}
* that must be done for every newly created context, then puts the task
* on the runqueue and wakes it.
*/
-void fastcall wake_up_new_task(struct task_struct *p, unsigned long clone_flags)
+void wake_up_new_task(struct task_struct *p, unsigned long clone_flags)
{
unsigned long flags;
struct rq *rq;
#if defined(CONFIG_PREEMPT) && defined(CONFIG_DEBUG_PREEMPT)
-void fastcall add_preempt_count(int val)
+void add_preempt_count(int val)
{
/*
* Underflow?
}
EXPORT_SYMBOL(add_preempt_count);
-void fastcall sub_preempt_count(int val)
+void sub_preempt_count(int val)
{
/*
* Underflow?
* @nr_exclusive: how many wake-one or wake-many threads to wake up
* @key: is directly passed to the wakeup function
*/
-void fastcall __wake_up(wait_queue_head_t *q, unsigned int mode,
+void __wake_up(wait_queue_head_t *q, unsigned int mode,
int nr_exclusive, void *key)
{
unsigned long flags;
/*
* Same as __wake_up but called with the spinlock in wait_queue_head_t held.
*/
-void fastcall __wake_up_locked(wait_queue_head_t *q, unsigned int mode)
+void __wake_up_locked(wait_queue_head_t *q, unsigned int mode)
{
__wake_up_common(q, mode, 1, 0, NULL);
}
*
* On UP it can prevent extra preemption.
*/
-void fastcall
+void
__wake_up_sync(wait_queue_head_t *q, unsigned int mode, int nr_exclusive)
{
unsigned long flags;
}
/*
- * kill_pgrp_info() sends a signal to a process group: this is what the tty
+ * __kill_pgrp_info() sends a signal to a process group: this is what the tty
* control characters do (^C, ^Z etc)
*/
return success ? 0 : retval;
}
-int kill_pgrp_info(int sig, struct siginfo *info, struct pid *pgrp)
-{
- int retval;
-
- read_lock(&tasklist_lock);
- retval = __kill_pgrp_info(sig, info, pgrp);
- read_unlock(&tasklist_lock);
-
- return retval;
-}
-
int kill_pid_info(int sig, struct siginfo *info, struct pid *pid)
{
- int error;
+ int error = -ESRCH;
struct task_struct *p;
rcu_read_lock();
if (unlikely(sig_needs_tasklist(sig)))
read_lock(&tasklist_lock);
+retry:
p = pid_task(pid, PIDTYPE_PID);
- error = -ESRCH;
- if (p)
+ if (p) {
error = group_send_sig_info(sig, info, p);
+ if (unlikely(error == -ESRCH))
+ /*
+ * The task was unhashed in between, try again.
+ * If it is dead, pid_task() will return NULL,
+ * if we race with de_thread() it will find the
+ * new leader.
+ */
+ goto retry;
+ }
if (unlikely(sig_needs_tasklist(sig)))
read_unlock(&tasklist_lock);
static int kill_something_info(int sig, struct siginfo *info, int pid)
{
int ret;
- rcu_read_lock();
- if (!pid) {
- ret = kill_pgrp_info(sig, info, task_pgrp(current));
- } else if (pid == -1) {
+
+ if (pid > 0) {
+ rcu_read_lock();
+ ret = kill_pid_info(sig, info, find_vpid(pid));
+ rcu_read_unlock();
+ return ret;
+ }
+
+ read_lock(&tasklist_lock);
+ if (pid != -1) {
+ ret = __kill_pgrp_info(sig, info,
+ pid ? find_vpid(-pid) : task_pgrp(current));
+ } else {
int retval = 0, count = 0;
struct task_struct * p;
- read_lock(&tasklist_lock);
for_each_process(p) {
if (p->pid > 1 && !same_thread_group(p, current)) {
int err = group_send_sig_info(sig, info, p);
retval = err;
}
}
- read_unlock(&tasklist_lock);
ret = count ? retval : -ESRCH;
- } else if (pid < 0) {
- ret = kill_pgrp_info(sig, info, find_vpid(-pid));
- } else {
- ret = kill_pid_info(sig, info, find_vpid(pid));
}
- rcu_read_unlock();
+ read_unlock(&tasklist_lock);
+
return ret;
}
return send_sig_info(sig, __si_special(priv), p);
}
-/*
- * This is the entry point for "process-wide" signals.
- * They will go to an appropriate thread in the thread group.
- */
-int
-send_group_sig_info(int sig, struct siginfo *info, struct task_struct *p)
-{
- int ret;
- read_lock(&tasklist_lock);
- ret = group_send_sig_info(sig, info, p);
- read_unlock(&tasklist_lock);
- return ret;
-}
-
void
force_sig(int sig, struct task_struct *p)
{
int kill_pgrp(struct pid *pid, int sig, int priv)
{
- return kill_pgrp_info(sig, __si_special(priv), pid);
+ int ret;
+
+ read_lock(&tasklist_lock);
+ ret = __kill_pgrp_info(sig, __si_special(priv), pid);
+ read_unlock(&tasklist_lock);
+
+ return ret;
}
EXPORT_SYMBOL(kill_pgrp);
{
if (!likely(current->ptrace & PT_PTRACED))
return 0;
-
- if (unlikely(current->parent == current->real_parent &&
- (current->ptrace & PT_ATTACHED)))
- return 0;
-
/*
* Are we in the middle of do_coredump?
* If so and our tracer is also part of the coredump stopping
* That makes it a way to test a stopped process for
* being ptrace-stopped vs being job-control-stopped.
*
- * If we actually decide not to stop at all because the tracer is gone,
- * we leave nostop_code in current->exit_code.
+ * If we actually decide not to stop at all because the tracer
+ * is gone, we keep current->exit_code unless clear_code.
*/
-static void ptrace_stop(int exit_code, int nostop_code, siginfo_t *info)
+static void ptrace_stop(int exit_code, int clear_code, siginfo_t *info)
{
int killed = 0;
} else {
/*
* By the time we got the lock, our tracer went away.
- * Don't stop here.
+ * Don't drop the lock yet, another tracer may come.
*/
+ __set_current_state(TASK_RUNNING);
+ if (clear_code)
+ current->exit_code = 0;
read_unlock(&tasklist_lock);
- set_current_state(TASK_RUNNING);
- current->exit_code = nostop_code;
}
/*
/* Let the debugger run. */
spin_lock_irq(¤t->sighand->siglock);
- ptrace_stop(exit_code, 0, &info);
+ ptrace_stop(exit_code, 1, &info);
spin_unlock_irq(¤t->sighand->siglock);
}
* stop is always done with the siglock held,
* so this check has no races.
*/
- if (!t->exit_state &&
+ if (!(t->flags & PF_EXITING) &&
!task_is_stopped_or_traced(t)) {
stop_count++;
signal_wake_up(t, 0);
ptrace_signal_deliver(regs, cookie);
/* Let the debugger run. */
- ptrace_stop(signr, signr, info);
+ ptrace_stop(signr, 0, info);
/* We're back. Did the debugger cancel the sig? */
signr = current->exit_code;
return signr;
}
+void exit_signals(struct task_struct *tsk)
+{
+ int group_stop = 0;
+ struct task_struct *t;
+
+ if (thread_group_empty(tsk) || signal_group_exit(tsk->signal)) {
+ tsk->flags |= PF_EXITING;
+ return;
+ }
+
+ spin_lock_irq(&tsk->sighand->siglock);
+ /*
+ * From now this task is not visible for group-wide signals,
+ * see wants_signal(), do_signal_stop().
+ */
+ tsk->flags |= PF_EXITING;
+ if (!signal_pending(tsk))
+ goto out;
+
+ /* It could be that __group_complete_signal() choose us to
+ * notify about group-wide signal. Another thread should be
+ * woken now to take the signal since we will not.
+ */
+ for (t = tsk; (t = next_thread(t)) != tsk; )
+ if (!signal_pending(t) && !(t->flags & PF_EXITING))
+ recalc_sigpending_and_wake(t);
+
+ if (unlikely(tsk->signal->group_stop_count) &&
+ !--tsk->signal->group_stop_count) {
+ tsk->signal->flags = SIGNAL_STOP_STOPPED;
+ group_stop = 1;
+ }
+out:
+ spin_unlock_irq(&tsk->sighand->siglock);
+
+ if (unlikely(group_stop)) {
+ read_lock(&tasklist_lock);
+ do_notify_parent_cldstop(tsk, CLD_STOPPED);
+ read_unlock(&tasklist_lock);
+ }
+}
+
EXPORT_SYMBOL(recalc_sigpending);
EXPORT_SYMBOL_GPL(dequeue_signal);
EXPORT_SYMBOL(flush_signals);
/*
* This function must run with irqs disabled!
*/
-inline fastcall void raise_softirq_irqoff(unsigned int nr)
+inline void raise_softirq_irqoff(unsigned int nr)
{
__raise_softirq_irqoff(nr);
wakeup_softirqd();
}
-void fastcall raise_softirq(unsigned int nr)
+void raise_softirq(unsigned int nr)
{
unsigned long flags;
static DEFINE_PER_CPU(struct tasklet_head, tasklet_vec) = { NULL };
static DEFINE_PER_CPU(struct tasklet_head, tasklet_hi_vec) = { NULL };
-void fastcall __tasklet_schedule(struct tasklet_struct *t)
+void __tasklet_schedule(struct tasklet_struct *t)
{
unsigned long flags;
EXPORT_SYMBOL(__tasklet_schedule);
-void fastcall __tasklet_hi_schedule(struct tasklet_struct *t)
+void __tasklet_hi_schedule(struct tasklet_struct *t)
{
unsigned long flags;
{
struct task_struct *p;
struct task_struct *group_leader = current->group_leader;
- int err = -EINVAL;
- struct pid_namespace *ns;
+ struct pid *pgrp;
+ int err;
if (!pid)
pid = task_pid_vnr(group_leader);
/* From this point forward we keep holding onto the tasklist lock
* so that our parent does not change from under us. -DaveM
*/
- ns = current->nsproxy->pid_ns;
-
write_lock_irq(&tasklist_lock);
err = -ESRCH;
- p = find_task_by_pid_ns(pid, ns);
+ p = find_task_by_vpid(pid);
if (!p)
goto out;
if (!thread_group_leader(p))
goto out;
- if (p->real_parent->tgid == group_leader->tgid) {
+ if (same_thread_group(p->real_parent, group_leader)) {
err = -EPERM;
if (task_session(p) != task_session(group_leader))
goto out;
if (p->signal->leader)
goto out;
+ pgrp = task_pid(p);
if (pgid != pid) {
struct task_struct *g;
- g = find_task_by_pid_type_ns(PIDTYPE_PGID, pgid, ns);
+ pgrp = find_vpid(pgid);
+ g = pid_task(pgrp, PIDTYPE_PGID);
if (!g || task_session(g) != task_session(group_leader))
goto out;
}
if (err)
goto out;
- if (task_pgrp_nr_ns(p, ns) != pgid) {
- struct pid *pid;
-
+ if (task_pgrp(p) != pgrp) {
detach_pid(p, PIDTYPE_PGID);
- pid = find_vpid(pgid);
- attach_pid(p, PIDTYPE_PGID, pid);
- set_task_pgrp(p, pid_nr(pid));
+ attach_pid(p, PIDTYPE_PGID, pgrp);
+ set_task_pgrp(p, pid_nr(pgrp));
}
err = 0;
else {
int retval;
struct task_struct *p;
- struct pid_namespace *ns;
-
- ns = current->nsproxy->pid_ns;
read_lock(&tasklist_lock);
- p = find_task_by_pid_ns(pid, ns);
+ p = find_task_by_vpid(pid);
retval = -ESRCH;
if (p) {
retval = security_task_getpgid(p);
if (!retval)
- retval = task_pgrp_nr_ns(p, ns);
+ retval = task_pgrp_vnr(p);
}
read_unlock(&tasklist_lock);
return retval;
else {
int retval;
struct task_struct *p;
- struct pid_namespace *ns;
-
- ns = current->nsproxy->pid_ns;
- read_lock(&tasklist_lock);
- p = find_task_by_pid_ns(pid, ns);
+ rcu_read_lock();
+ p = find_task_by_vpid(pid);
retval = -ESRCH;
if (p) {
retval = security_task_getsid(p);
if (!retval)
- retval = task_session_nr_ns(p, ns);
+ retval = task_session_vnr(p);
}
- read_unlock(&tasklist_lock);
+ rcu_read_unlock();
return retval;
}
}
asmlinkage long sys_setsid(void)
{
struct task_struct *group_leader = current->group_leader;
- pid_t session;
+ struct pid *sid = task_pid(group_leader);
+ pid_t session = pid_vnr(sid);
int err = -EPERM;
write_lock_irq(&tasklist_lock);
-
/* Fail if I am already a session leader */
if (group_leader->signal->leader)
goto out;
- session = group_leader->pid;
/* Fail if a process group id already exists that equals the
* proposed session id.
- *
- * Don't check if session id == 1 because kernel threads use this
- * session id and so the check will always fail and make it so
- * init cannot successfully call setsid.
*/
- if (session > 1 && find_task_by_pid_type_ns(PIDTYPE_PGID,
- session, &init_pid_ns))
+ if (pid_task(sid, PIDTYPE_PGID))
goto out;
group_leader->signal->leader = 1;
- __set_special_pids(session, session);
+ __set_special_pids(sid);
spin_lock(&group_leader->sighand->siglock);
group_leader->signal->tty = NULL;
spin_unlock(&group_leader->sighand->siglock);
- err = task_pgrp_vnr(group_leader);
+ err = session;
out:
write_unlock_irq(&tasklist_lock);
return err;
#include <linux/highuid.h>
#include <linux/writeback.h>
#include <linux/hugetlb.h>
-#include <linux/security.h>
#include <linux/initrd.h>
#include <linux/times.h>
#include <linux/limits.h>
extern char core_pattern[];
extern int pid_max;
extern int min_free_kbytes;
-extern int printk_ratelimit_jiffies;
-extern int printk_ratelimit_burst;
extern int pid_max_min, pid_max_max;
extern int sysctl_drop_caches;
extern int percpu_pagelist_fraction;
.mode = 0644,
.proc_handler = &proc_dointvec,
},
- {
- .ctl_name = KERN_PRINTK,
- .procname = "printk",
- .data = &console_loglevel,
- .maxlen = 4*sizeof(int),
- .mode = 0644,
- .proc_handler = &proc_dointvec,
- },
#ifdef CONFIG_KMOD
{
.ctl_name = KERN_MODPROBE,
.mode = 0644,
.proc_handler = &proc_dointvec,
},
+#if defined CONFIG_PRINTK
+ {
+ .ctl_name = KERN_PRINTK,
+ .procname = "printk",
+ .data = &console_loglevel,
+ .maxlen = 4*sizeof(int),
+ .mode = 0644,
+ .proc_handler = &proc_dointvec,
+ },
{
.ctl_name = KERN_PRINTK_RATELIMIT,
.procname = "printk_ratelimit",
.mode = 0644,
.proc_handler = &proc_dointvec,
},
+#endif
{
.ctl_name = KERN_NGROUPS_MAX,
.procname = "ngroups_max",
.data = &nr_overcommit_huge_pages,
.maxlen = sizeof(nr_overcommit_huge_pages),
.mode = 0644,
- .proc_handler = &proc_doulongvec_minmax,
+ .proc_handler = &hugetlb_overcommit_handler,
},
#endif
{
pid_t tmp;
int r;
- tmp = pid_nr_ns(cad_pid, current->nsproxy->pid_ns);
+ tmp = pid_vnr(cad_pid);
r = __do_proc_dointvec(&tmp, table, write, filp, buffer,
lenp, ppos, NULL, NULL);
struct trans_ctl_table {
int ctl_name;
const char *procname;
- struct trans_ctl_table *child;
+ const struct trans_ctl_table *child;
};
-static struct trans_ctl_table trans_random_table[] = {
+static const struct trans_ctl_table trans_random_table[] = {
{ RANDOM_POOLSIZE, "poolsize" },
{ RANDOM_ENTROPY_COUNT, "entropy_avail" },
{ RANDOM_READ_THRESH, "read_wakeup_threshold" },
{}
};
-static struct trans_ctl_table trans_pty_table[] = {
+static const struct trans_ctl_table trans_pty_table[] = {
{ PTY_MAX, "max" },
{ PTY_NR, "nr" },
{}
};
-static struct trans_ctl_table trans_kern_table[] = {
+static const struct trans_ctl_table trans_kern_table[] = {
{ KERN_OSTYPE, "ostype" },
{ KERN_OSRELEASE, "osrelease" },
/* KERN_OSREV not used */
{}
};
-static struct trans_ctl_table trans_vm_table[] = {
+static const struct trans_ctl_table trans_vm_table[] = {
{ VM_OVERCOMMIT_MEMORY, "overcommit_memory" },
{ VM_PAGE_CLUSTER, "page-cluster" },
{ VM_DIRTY_BACKGROUND, "dirty_background_ratio" },
{}
};
-static struct trans_ctl_table trans_net_core_table[] = {
+static const struct trans_ctl_table trans_net_core_table[] = {
{ NET_CORE_WMEM_MAX, "wmem_max" },
{ NET_CORE_RMEM_MAX, "rmem_max" },
{ NET_CORE_WMEM_DEFAULT, "wmem_default" },
{},
};
-static struct trans_ctl_table trans_net_unix_table[] = {
+static const struct trans_ctl_table trans_net_unix_table[] = {
/* NET_UNIX_DESTROY_DELAY unused */
/* NET_UNIX_DELETE_DELAY unused */
{ NET_UNIX_MAX_DGRAM_QLEN, "max_dgram_qlen" },
{}
};
-static struct trans_ctl_table trans_net_ipv4_route_table[] = {
+static const struct trans_ctl_table trans_net_ipv4_route_table[] = {
{ NET_IPV4_ROUTE_FLUSH, "flush" },
{ NET_IPV4_ROUTE_MIN_DELAY, "min_delay" },
{ NET_IPV4_ROUTE_MAX_DELAY, "max_delay" },
{}
};
-static struct trans_ctl_table trans_net_ipv4_conf_vars_table[] = {
+static const struct trans_ctl_table trans_net_ipv4_conf_vars_table[] = {
{ NET_IPV4_CONF_FORWARDING, "forwarding" },
{ NET_IPV4_CONF_MC_FORWARDING, "mc_forwarding" },
{}
};
-static struct trans_ctl_table trans_net_ipv4_conf_table[] = {
+static const struct trans_ctl_table trans_net_ipv4_conf_table[] = {
{ NET_PROTO_CONF_ALL, "all", trans_net_ipv4_conf_vars_table },
{ NET_PROTO_CONF_DEFAULT, "default", trans_net_ipv4_conf_vars_table },
{ 0, NULL, trans_net_ipv4_conf_vars_table },
{}
};
-static struct trans_ctl_table trans_net_neigh_vars_table[] = {
+static const struct trans_ctl_table trans_net_neigh_vars_table[] = {
{ NET_NEIGH_MCAST_SOLICIT, "mcast_solicit" },
{ NET_NEIGH_UCAST_SOLICIT, "ucast_solicit" },
{ NET_NEIGH_APP_SOLICIT, "app_solicit" },
{}
};
-static struct trans_ctl_table trans_net_neigh_table[] = {
+static const struct trans_ctl_table trans_net_neigh_table[] = {
{ NET_PROTO_CONF_DEFAULT, "default", trans_net_neigh_vars_table },
{ 0, NULL, trans_net_neigh_vars_table },
{}
};
-static struct trans_ctl_table trans_net_ipv4_netfilter_table[] = {
+static const struct trans_ctl_table trans_net_ipv4_netfilter_table[] = {
{ NET_IPV4_NF_CONNTRACK_MAX, "ip_conntrack_max" },
{ NET_IPV4_NF_CONNTRACK_TCP_TIMEOUT_SYN_SENT, "ip_conntrack_tcp_timeout_syn_sent" },
{}
};
-static struct trans_ctl_table trans_net_ipv4_table[] = {
+static const struct trans_ctl_table trans_net_ipv4_table[] = {
{ NET_IPV4_FORWARD, "ip_forward" },
{ NET_IPV4_DYNADDR, "ip_dynaddr" },
{}
};
-static struct trans_ctl_table trans_net_ipx_table[] = {
+static const struct trans_ctl_table trans_net_ipx_table[] = {
{ NET_IPX_PPROP_BROADCASTING, "ipx_pprop_broadcasting" },
/* NET_IPX_FORWARDING unused */
{}
};
-static struct trans_ctl_table trans_net_atalk_table[] = {
+static const struct trans_ctl_table trans_net_atalk_table[] = {
{ NET_ATALK_AARP_EXPIRY_TIME, "aarp-expiry-time" },
{ NET_ATALK_AARP_TICK_TIME, "aarp-tick-time" },
{ NET_ATALK_AARP_RETRANSMIT_LIMIT, "aarp-retransmit-limit" },
{},
};
-static struct trans_ctl_table trans_net_netrom_table[] = {
+static const struct trans_ctl_table trans_net_netrom_table[] = {
{ NET_NETROM_DEFAULT_PATH_QUALITY, "default_path_quality" },
{ NET_NETROM_OBSOLESCENCE_COUNT_INITIALISER, "obsolescence_count_initialiser" },
{ NET_NETROM_NETWORK_TTL_INITIALISER, "network_ttl_initialiser" },
{}
};
-static struct trans_ctl_table trans_net_ax25_param_table[] = {
+static const struct trans_ctl_table trans_net_ax25_param_table[] = {
{ NET_AX25_IP_DEFAULT_MODE, "ip_default_mode" },
{ NET_AX25_DEFAULT_MODE, "ax25_default_mode" },
{ NET_AX25_BACKOFF_TYPE, "backoff_type" },
{}
};
-static struct trans_ctl_table trans_net_ax25_table[] = {
+static const struct trans_ctl_table trans_net_ax25_table[] = {
{ 0, NULL, trans_net_ax25_param_table },
{}
};
-static struct trans_ctl_table trans_net_bridge_table[] = {
+static const struct trans_ctl_table trans_net_bridge_table[] = {
{ NET_BRIDGE_NF_CALL_ARPTABLES, "bridge-nf-call-arptables" },
{ NET_BRIDGE_NF_CALL_IPTABLES, "bridge-nf-call-iptables" },
{ NET_BRIDGE_NF_CALL_IP6TABLES, "bridge-nf-call-ip6tables" },
{}
};
-static struct trans_ctl_table trans_net_rose_table[] = {
+static const struct trans_ctl_table trans_net_rose_table[] = {
{ NET_ROSE_RESTART_REQUEST_TIMEOUT, "restart_request_timeout" },
{ NET_ROSE_CALL_REQUEST_TIMEOUT, "call_request_timeout" },
{ NET_ROSE_RESET_REQUEST_TIMEOUT, "reset_request_timeout" },
{}
};
-static struct trans_ctl_table trans_net_ipv6_conf_var_table[] = {
+static const struct trans_ctl_table trans_net_ipv6_conf_var_table[] = {
{ NET_IPV6_FORWARDING, "forwarding" },
{ NET_IPV6_HOP_LIMIT, "hop_limit" },
{ NET_IPV6_MTU, "mtu" },
{}
};
-static struct trans_ctl_table trans_net_ipv6_conf_table[] = {
+static const struct trans_ctl_table trans_net_ipv6_conf_table[] = {
{ NET_PROTO_CONF_ALL, "all", trans_net_ipv6_conf_var_table },
{ NET_PROTO_CONF_DEFAULT, "default", trans_net_ipv6_conf_var_table },
{ 0, NULL, trans_net_ipv6_conf_var_table },
{}
};
-static struct trans_ctl_table trans_net_ipv6_route_table[] = {
+static const struct trans_ctl_table trans_net_ipv6_route_table[] = {
{ NET_IPV6_ROUTE_FLUSH, "flush" },
{ NET_IPV6_ROUTE_GC_THRESH, "gc_thresh" },
{ NET_IPV6_ROUTE_MAX_SIZE, "max_size" },
{}
};
-static struct trans_ctl_table trans_net_ipv6_icmp_table[] = {
+static const struct trans_ctl_table trans_net_ipv6_icmp_table[] = {
{ NET_IPV6_ICMP_RATELIMIT, "ratelimit" },
{}
};
-static struct trans_ctl_table trans_net_ipv6_table[] = {
+static const struct trans_ctl_table trans_net_ipv6_table[] = {
{ NET_IPV6_CONF, "conf", trans_net_ipv6_conf_table },
{ NET_IPV6_NEIGH, "neigh", trans_net_neigh_table },
{ NET_IPV6_ROUTE, "route", trans_net_ipv6_route_table },
{}
};
-static struct trans_ctl_table trans_net_x25_table[] = {
+static const struct trans_ctl_table trans_net_x25_table[] = {
{ NET_X25_RESTART_REQUEST_TIMEOUT, "restart_request_timeout" },
{ NET_X25_CALL_REQUEST_TIMEOUT, "call_request_timeout" },
{ NET_X25_RESET_REQUEST_TIMEOUT, "reset_request_timeout" },
{}
};
-static struct trans_ctl_table trans_net_tr_table[] = {
+static const struct trans_ctl_table trans_net_tr_table[] = {
{ NET_TR_RIF_TIMEOUT, "rif_timeout" },
{}
};
-static struct trans_ctl_table trans_net_decnet_conf_vars[] = {
+static const struct trans_ctl_table trans_net_decnet_conf_vars[] = {
{ NET_DECNET_CONF_DEV_FORWARDING, "forwarding" },
{ NET_DECNET_CONF_DEV_PRIORITY, "priority" },
{ NET_DECNET_CONF_DEV_T2, "t2" },
{}
};
-static struct trans_ctl_table trans_net_decnet_conf[] = {
+static const struct trans_ctl_table trans_net_decnet_conf[] = {
{ 0, NULL, trans_net_decnet_conf_vars },
{}
};
-static struct trans_ctl_table trans_net_decnet_table[] = {
+static const struct trans_ctl_table trans_net_decnet_table[] = {
{ NET_DECNET_CONF, "conf", trans_net_decnet_conf },
{ NET_DECNET_NODE_ADDRESS, "node_address" },
{ NET_DECNET_NODE_NAME, "node_name" },
{}
};
-static struct trans_ctl_table trans_net_sctp_table[] = {
+static const struct trans_ctl_table trans_net_sctp_table[] = {
{ NET_SCTP_RTO_INITIAL, "rto_initial" },
{ NET_SCTP_RTO_MIN, "rto_min" },
{ NET_SCTP_RTO_MAX, "rto_max" },
{}
};
-static struct trans_ctl_table trans_net_llc_llc2_timeout_table[] = {
+static const struct trans_ctl_table trans_net_llc_llc2_timeout_table[] = {
{ NET_LLC2_ACK_TIMEOUT, "ack" },
{ NET_LLC2_P_TIMEOUT, "p" },
{ NET_LLC2_REJ_TIMEOUT, "rej" },
{}
};
-static struct trans_ctl_table trans_net_llc_station_table[] = {
+static const struct trans_ctl_table trans_net_llc_station_table[] = {
{ NET_LLC_STATION_ACK_TIMEOUT, "ack_timeout" },
{}
};
-static struct trans_ctl_table trans_net_llc_llc2_table[] = {
+static const struct trans_ctl_table trans_net_llc_llc2_table[] = {
{ NET_LLC2, "timeout", trans_net_llc_llc2_timeout_table },
{}
};
-static struct trans_ctl_table trans_net_llc_table[] = {
+static const struct trans_ctl_table trans_net_llc_table[] = {
{ NET_LLC2, "llc2", trans_net_llc_llc2_table },
{ NET_LLC_STATION, "station", trans_net_llc_station_table },
{}
};
-static struct trans_ctl_table trans_net_netfilter_table[] = {
+static const struct trans_ctl_table trans_net_netfilter_table[] = {
{ NET_NF_CONNTRACK_MAX, "nf_conntrack_max" },
{ NET_NF_CONNTRACK_TCP_TIMEOUT_SYN_SENT, "nf_conntrack_tcp_timeout_syn_sent" },
{ NET_NF_CONNTRACK_TCP_TIMEOUT_SYN_RECV, "nf_conntrack_tcp_timeout_syn_recv" },
{}
};
-static struct trans_ctl_table trans_net_dccp_table[] = {
+static const struct trans_ctl_table trans_net_dccp_table[] = {
{ NET_DCCP_DEFAULT, "default" },
{}
};
-static struct trans_ctl_table trans_net_irda_table[] = {
+static const struct trans_ctl_table trans_net_irda_table[] = {
{ NET_IRDA_DISCOVERY, "discovery" },
{ NET_IRDA_DEVNAME, "devname" },
{ NET_IRDA_DEBUG, "debug" },
{}
};
-static struct trans_ctl_table trans_net_table[] = {
+static const struct trans_ctl_table trans_net_table[] = {
{ NET_CORE, "core", trans_net_core_table },
/* NET_ETHER not used */
/* NET_802 not used */
{}
};
-static struct trans_ctl_table trans_fs_quota_table[] = {
+static const struct trans_ctl_table trans_fs_quota_table[] = {
{ FS_DQ_LOOKUPS, "lookups" },
{ FS_DQ_DROPS, "drops" },
{ FS_DQ_READS, "reads" },
{}
};
-static struct trans_ctl_table trans_fs_xfs_table[] = {
+static const struct trans_ctl_table trans_fs_xfs_table[] = {
{ XFS_RESTRICT_CHOWN, "restrict_chown" },
{ XFS_SGID_INHERIT, "irix_sgid_inherit" },
{ XFS_SYMLINK_MODE, "irix_symlink_mode" },
{}
};
-static struct trans_ctl_table trans_fs_ocfs2_nm_table[] = {
+static const struct trans_ctl_table trans_fs_ocfs2_nm_table[] = {
{ 1, "hb_ctl_path" },
{}
};
-static struct trans_ctl_table trans_fs_ocfs2_table[] = {
+static const struct trans_ctl_table trans_fs_ocfs2_table[] = {
{ 1, "nm", trans_fs_ocfs2_nm_table },
{}
};
-static struct trans_ctl_table trans_inotify_table[] = {
+static const struct trans_ctl_table trans_inotify_table[] = {
{ INOTIFY_MAX_USER_INSTANCES, "max_user_instances" },
{ INOTIFY_MAX_USER_WATCHES, "max_user_watches" },
{ INOTIFY_MAX_QUEUED_EVENTS, "max_queued_events" },
{}
};
-static struct trans_ctl_table trans_fs_table[] = {
+static const struct trans_ctl_table trans_fs_table[] = {
{ FS_NRINODE, "inode-nr" },
{ FS_STATINODE, "inode-state" },
/* FS_MAXINODE unused */
{}
};
-static struct trans_ctl_table trans_debug_table[] = {
+static const struct trans_ctl_table trans_debug_table[] = {
{}
};
-static struct trans_ctl_table trans_cdrom_table[] = {
+static const struct trans_ctl_table trans_cdrom_table[] = {
{ DEV_CDROM_INFO, "info" },
{ DEV_CDROM_AUTOCLOSE, "autoclose" },
{ DEV_CDROM_AUTOEJECT, "autoeject" },
{}
};
-static struct trans_ctl_table trans_ipmi_table[] = {
+static const struct trans_ctl_table trans_ipmi_table[] = {
{ DEV_IPMI_POWEROFF_POWERCYCLE, "poweroff_powercycle" },
{}
};
-static struct trans_ctl_table trans_mac_hid_files[] = {
+static const struct trans_ctl_table trans_mac_hid_files[] = {
/* DEV_MAC_HID_KEYBOARD_SENDS_LINUX_KEYCODES unused */
/* DEV_MAC_HID_KEYBOARD_LOCK_KEYCODES unused */
{ DEV_MAC_HID_MOUSE_BUTTON_EMULATION, "mouse_button_emulation" },
{}
};
-static struct trans_ctl_table trans_raid_table[] = {
+static const struct trans_ctl_table trans_raid_table[] = {
{ DEV_RAID_SPEED_LIMIT_MIN, "speed_limit_min" },
{ DEV_RAID_SPEED_LIMIT_MAX, "speed_limit_max" },
{}
};
-static struct trans_ctl_table trans_scsi_table[] = {
+static const struct trans_ctl_table trans_scsi_table[] = {
{ DEV_SCSI_LOGGING_LEVEL, "logging_level" },
{}
};
-static struct trans_ctl_table trans_parport_default_table[] = {
+static const struct trans_ctl_table trans_parport_default_table[] = {
{ DEV_PARPORT_DEFAULT_TIMESLICE, "timeslice" },
{ DEV_PARPORT_DEFAULT_SPINTIME, "spintime" },
{}
};
-static struct trans_ctl_table trans_parport_device_table[] = {
+static const struct trans_ctl_table trans_parport_device_table[] = {
{ DEV_PARPORT_DEVICE_TIMESLICE, "timeslice" },
{}
};
-static struct trans_ctl_table trans_parport_devices_table[] = {
+static const struct trans_ctl_table trans_parport_devices_table[] = {
{ DEV_PARPORT_DEVICES_ACTIVE, "active" },
{ 0, NULL, trans_parport_device_table },
{}
};
-static struct trans_ctl_table trans_parport_parport_table[] = {
+static const struct trans_ctl_table trans_parport_parport_table[] = {
{ DEV_PARPORT_SPINTIME, "spintime" },
{ DEV_PARPORT_BASE_ADDR, "base-addr" },
{ DEV_PARPORT_IRQ, "irq" },
{ DEV_PARPORT_AUTOPROBE + 4, "autoprobe3" },
{}
};
-static struct trans_ctl_table trans_parport_table[] = {
+static const struct trans_ctl_table trans_parport_table[] = {
{ DEV_PARPORT_DEFAULT, "default", trans_parport_default_table },
{ 0, NULL, trans_parport_parport_table },
{}
};
-static struct trans_ctl_table trans_dev_table[] = {
+static const struct trans_ctl_table trans_dev_table[] = {
{ DEV_CDROM, "cdrom", trans_cdrom_table },
/* DEV_HWMON unused */
{ DEV_PARPORT, "parport", trans_parport_table },
{}
};
-static struct trans_ctl_table trans_bus_isa_table[] = {
+static const struct trans_ctl_table trans_bus_isa_table[] = {
{ BUS_ISA_MEM_BASE, "membase" },
{ BUS_ISA_PORT_BASE, "portbase" },
{ BUS_ISA_PORT_SHIFT, "portshift" },
{}
};
-static struct trans_ctl_table trans_bus_table[] = {
+static const struct trans_ctl_table trans_bus_table[] = {
{ CTL_BUS_ISA, "isa", trans_bus_isa_table },
{}
};
-static struct trans_ctl_table trans_arlan_conf_table0[] = {
+static const struct trans_ctl_table trans_arlan_conf_table0[] = {
{ 1, "spreadingCode" },
{ 2, "channelNumber" },
{ 3, "scramblingDisable" },
{}
};
-static struct trans_ctl_table trans_arlan_conf_table1[] = {
+static const struct trans_ctl_table trans_arlan_conf_table1[] = {
{ 1, "spreadingCode" },
{ 2, "channelNumber" },
{ 3, "scramblingDisable" },
{}
};
-static struct trans_ctl_table trans_arlan_conf_table2[] = {
+static const struct trans_ctl_table trans_arlan_conf_table2[] = {
{ 1, "spreadingCode" },
{ 2, "channelNumber" },
{ 3, "scramblingDisable" },
{}
};
-static struct trans_ctl_table trans_arlan_conf_table3[] = {
+static const struct trans_ctl_table trans_arlan_conf_table3[] = {
{ 1, "spreadingCode" },
{ 2, "channelNumber" },
{ 3, "scramblingDisable" },
{}
};
-static struct trans_ctl_table trans_arlan_table[] = {
+static const struct trans_ctl_table trans_arlan_table[] = {
{ 1, "arlan0", trans_arlan_conf_table0 },
{ 2, "arlan1", trans_arlan_conf_table1 },
{ 3, "arlan2", trans_arlan_conf_table2 },
{}
};
-static struct trans_ctl_table trans_s390dbf_table[] = {
+static const struct trans_ctl_table trans_s390dbf_table[] = {
{ 5678 /* CTL_S390DBF_STOPPABLE */, "debug_stoppable" },
{ 5679 /* CTL_S390DBF_ACTIVE */, "debug_active" },
{}
};
-static struct trans_ctl_table trans_sunrpc_table[] = {
+static const struct trans_ctl_table trans_sunrpc_table[] = {
{ CTL_RPCDEBUG, "rpc_debug" },
{ CTL_NFSDEBUG, "nfs_debug" },
{ CTL_NFSDDEBUG, "nfsd_debug" },
{}
};
-static struct trans_ctl_table trans_pm_table[] = {
+static const struct trans_ctl_table trans_pm_table[] = {
{ 1 /* CTL_PM_SUSPEND */, "suspend" },
{ 2 /* CTL_PM_CMODE */, "cmode" },
{ 3 /* CTL_PM_P0 */, "p0" },
{}
};
-static struct trans_ctl_table trans_frv_table[] = {
+static const struct trans_ctl_table trans_frv_table[] = {
{ 1, "cache-mode" },
{ 2, "pin-cxnr" },
{}
};
-static struct trans_ctl_table trans_root_table[] = {
+static const struct trans_ctl_table trans_root_table[] = {
{ CTL_KERN, "kernel", trans_kern_table },
{ CTL_VM, "vm", trans_vm_table },
{ CTL_NET, "net", trans_net_table },
return table;
}
-static struct trans_ctl_table *sysctl_binary_lookup(struct ctl_table *table)
+static const struct trans_ctl_table *sysctl_binary_lookup(struct ctl_table *table)
{
struct ctl_table *test;
- struct trans_ctl_table *ref;
- int depth, cur_depth;
+ const struct trans_ctl_table *ref;
+ int cur_depth;
- depth = sysctl_depth(table);
+ cur_depth = sysctl_depth(table);
- cur_depth = depth;
ref = trans_root_table;
repeat:
test = sysctl_parent(table, cur_depth);
static void sysctl_check_bin_path(struct ctl_table *table, const char **fail)
{
- struct trans_ctl_table *ref;
+ const struct trans_ctl_table *ref;
ref = sysctl_binary_lookup(table);
if (table->ctl_name && !ref)
#include <asm/uaccess.h>
#include <asm/unistd.h>
+#include "timeconst.h"
+
/*
* The timezone where the local system is located. Used as a default by some
* programs who obtain this value by using gettimeofday.
#endif /* __ARCH_WANT_SYS_TIME */
-asmlinkage long sys_gettimeofday(struct timeval __user *tv, struct timezone __user *tz)
+asmlinkage long sys_gettimeofday(struct timeval __user *tv,
+ struct timezone __user *tz)
{
if (likely(tv != NULL)) {
struct timeval ktv;
* hard to make the program warp the clock precisely n hours) or
* compile in the timezone information into the kernel. Bad, bad....
*
- * - TYT, 1992-01-01
+ * - TYT, 1992-01-01
*
* The best thing to do is to keep the CMOS clock in universal time (UTC)
* as real UNIX machines always do it. This avoids all headaches about
#elif HZ > MSEC_PER_SEC && !(HZ % MSEC_PER_SEC)
return (j + (HZ / MSEC_PER_SEC) - 1)/(HZ / MSEC_PER_SEC);
#else
- return (j * MSEC_PER_SEC) / HZ;
+# if BITS_PER_LONG == 32
+ return ((u64)HZ_TO_MSEC_MUL32 * j) >> HZ_TO_MSEC_SHR32;
+# else
+ return (j * HZ_TO_MSEC_NUM) / HZ_TO_MSEC_DEN;
+# endif
#endif
}
EXPORT_SYMBOL(jiffies_to_msecs);
#elif HZ > USEC_PER_SEC && !(HZ % USEC_PER_SEC)
return (j + (HZ / USEC_PER_SEC) - 1)/(HZ / USEC_PER_SEC);
#else
- return (j * USEC_PER_SEC) / HZ;
+# if BITS_PER_LONG == 32
+ return ((u64)HZ_TO_USEC_MUL32 * j) >> HZ_TO_USEC_SHR32;
+# else
+ return (j * HZ_TO_USEC_NUM) / HZ_TO_USEC_DEN;
+# endif
#endif
}
EXPORT_SYMBOL(jiffies_to_usecs);
*
* This function should be only used for timestamps returned by
* current_kernel_time() or CURRENT_TIME, not with do_gettimeofday() because
- * it doesn't handle the better resolution of the later.
+ * it doesn't handle the better resolution of the latter.
*/
struct timespec timespec_trunc(struct timespec t, unsigned gran)
{
* This algorithm was first published by Gauss (I think).
*
* WARNING: this function will overflow on 2106-02-07 06:28:16 on
- * machines were long is 32-bit! (However, as time_t is signed, we
+ * machines where long is 32-bit! (However, as time_t is signed, we
* will already get problems at other places on 2038-01-19 03:14:08)
*/
unsigned long
* normalize to the timespec storage format
*
* Note: The tv_nsec part is always in the range of
- * 0 <= tv_nsec < NSEC_PER_SEC
+ * 0 <= tv_nsec < NSEC_PER_SEC
* For negative values only the tv_sec field is negative !
*/
void set_normalized_timespec(struct timespec *ts, time_t sec, long nsec)
/*
* Generic case - multiply, round and divide. But first
* check that if we are doing a net multiplication, that
- * we wouldnt overflow:
+ * we wouldn't overflow:
*/
if (HZ > MSEC_PER_SEC && m > jiffies_to_msecs(MAX_JIFFY_OFFSET))
return MAX_JIFFY_OFFSET;
- return (m * HZ + MSEC_PER_SEC - 1) / MSEC_PER_SEC;
+ return ((u64)MSEC_TO_HZ_MUL32 * m + MSEC_TO_HZ_ADJ32)
+ >> MSEC_TO_HZ_SHR32;
#endif
}
EXPORT_SYMBOL(msecs_to_jiffies);
#elif HZ > USEC_PER_SEC && !(HZ % USEC_PER_SEC)
return u * (HZ / USEC_PER_SEC);
#else
- return (u * HZ + USEC_PER_SEC - 1) / USEC_PER_SEC;
+ return ((u64)USEC_TO_HZ_MUL32 * u + USEC_TO_HZ_ADJ32)
+ >> USEC_TO_HZ_SHR32;
#endif
}
EXPORT_SYMBOL(usecs_to_jiffies);
}
/*
- * Called after a notify add to make devices availble which were
+ * Called after a notify add to make devices available which were
* released from the notifier call.
*/
static void clockevents_notify_released(void)
*/
void clockevents_notify(unsigned long reason, void *arg)
{
+ struct list_head *node, *tmp;
+
spin_lock(&clockevents_lock);
clockevents_do_notify(reason, arg);
* Unregister the clock event devices which were
* released from the users in the notify chain.
*/
- while (!list_empty(&clockevents_released)) {
- struct clock_event_device *dev;
-
- dev = list_entry(clockevents_released.next,
- struct clock_event_device, list);
- list_del(&dev->list);
- }
+ list_for_each_safe(node, tmp, &clockevents_released)
+ list_del(node);
break;
default:
break;
cs->name, delta);
cs->flags &= ~(CLOCK_SOURCE_VALID_FOR_HRES | CLOCK_SOURCE_WATCHDOG);
clocksource_change_rating(cs, 0);
- cs->flags &= ~CLOCK_SOURCE_WATCHDOG;
list_del(&cs->wd_list);
}
if (ts->nohz_mode != NOHZ_MODE_INACTIVE)
return 0;
- if (!timekeeping_is_continuous() || !tick_is_oneshot_available())
+ if (!timekeeping_valid_for_hres() || !tick_is_oneshot_available())
return 0;
if (!allow_nohz)
#endif
/**
- * timekeeping_is_continuous - check to see if timekeeping is free running
+ * timekeeping_valid_for_hres - Check if timekeeping is suitable for hres
*/
-int timekeeping_is_continuous(void)
+int timekeeping_valid_for_hres(void)
{
unsigned long seq;
int ret;
* with losing too many ticks, otherwise we would overadjust and
* produce an even larger error. The smaller the adjustment the
* faster we try to adjust for it, as lost ticks can do less harm
- * here. This is tuned so that an error of about 1 msec is adusted
+ * here. This is tuned so that an error of about 1 msec is adjusted
* within about 1 sec (or 2^20 nsec in 2^SHIFT_HZ ticks).
*/
error2 = clock->error >> (TICK_LENGTH_SHIFT + 22 - 2 * SHIFT_HZ);
--- /dev/null
+#!/usr/bin/perl
+# -----------------------------------------------------------------------
+#
+# Copyright 2007 rPath, Inc. - All Rights Reserved
+#
+# This file is part of the Linux kernel, and is made available under
+# the terms of the GNU General Public License version 2 or (at your
+# option) any later version; incorporated herein by reference.
+#
+# -----------------------------------------------------------------------
+#
+
+#
+# Usage: timeconst.pl HZ > timeconst.h
+#
+
+# Precomputed values for systems without Math::BigInt
+# Generated by:
+# timeconst.pl --can 24 32 48 64 100 122 128 200 250 256 300 512 1000 1024 1200
+%canned_values = (
+ 24 => [
+ '0xa6aaaaab','0x2aaaaaa',26,
+ '0xa6aaaaaaaaaaaaab','0x2aaaaaaaaaaaaaa',58,
+ 125,3,
+ '0xc49ba5e4','0x1fbe76c8b4',37,
+ '0xc49ba5e353f7ceda','0x1fbe76c8b439581062',69,
+ 3,125,
+ '0xa2c2aaab','0xaaaa',16,
+ '0xa2c2aaaaaaaaaaab','0xaaaaaaaaaaaa',48,
+ 125000,3,
+ '0xc9539b89','0x7fffbce4217d',47,
+ '0xc9539b8887229e91','0x7fffbce4217d2849cb25',79,
+ 3,125000,
+ ], 32 => [
+ '0xfa000000','0x6000000',27,
+ '0xfa00000000000000','0x600000000000000',59,
+ 125,4,
+ '0x83126e98','0xfdf3b645a',36,
+ '0x83126e978d4fdf3c','0xfdf3b645a1cac0831',68,
+ 4,125,
+ '0xf4240000','0x0',17,
+ '0xf424000000000000','0x0',49,
+ 31250,1,
+ '0x8637bd06','0x3fff79c842fa',46,
+ '0x8637bd05af6c69b6','0x3fff79c842fa5093964a',78,
+ 1,31250,
+ ], 48 => [
+ '0xa6aaaaab','0x6aaaaaa',27,
+ '0xa6aaaaaaaaaaaaab','0x6aaaaaaaaaaaaaa',59,
+ 125,6,
+ '0xc49ba5e4','0xfdf3b645a',36,
+ '0xc49ba5e353f7ceda','0xfdf3b645a1cac0831',68,
+ 6,125,
+ '0xa2c2aaab','0x15555',17,
+ '0xa2c2aaaaaaaaaaab','0x1555555555555',49,
+ 62500,3,
+ '0xc9539b89','0x3fffbce4217d',46,
+ '0xc9539b8887229e91','0x3fffbce4217d2849cb25',78,
+ 3,62500,
+ ], 64 => [
+ '0xfa000000','0xe000000',28,
+ '0xfa00000000000000','0xe00000000000000',60,
+ 125,8,
+ '0x83126e98','0x7ef9db22d',35,
+ '0x83126e978d4fdf3c','0x7ef9db22d0e560418',67,
+ 8,125,
+ '0xf4240000','0x0',18,
+ '0xf424000000000000','0x0',50,
+ 15625,1,
+ '0x8637bd06','0x1fff79c842fa',45,
+ '0x8637bd05af6c69b6','0x1fff79c842fa5093964a',77,
+ 1,15625,
+ ], 100 => [
+ '0xa0000000','0x0',28,
+ '0xa000000000000000','0x0',60,
+ 10,1,
+ '0xcccccccd','0x733333333',35,
+ '0xcccccccccccccccd','0x73333333333333333',67,
+ 1,10,
+ '0x9c400000','0x0',18,
+ '0x9c40000000000000','0x0',50,
+ 10000,1,
+ '0xd1b71759','0x1fff2e48e8a7',45,
+ '0xd1b71758e219652c','0x1fff2e48e8a71de69ad4',77,
+ 1,10000,
+ ], 122 => [
+ '0x8325c53f','0xfbcda3a',28,
+ '0x8325c53ef368eb05','0xfbcda3ac10c9714',60,
+ 500,61,
+ '0xf9db22d1','0x7fbe76c8b',35,
+ '0xf9db22d0e560418a','0x7fbe76c8b43958106',67,
+ 61,500,
+ '0x8012e2a0','0x3ef36',18,
+ '0x8012e29f79b47583','0x3ef368eb04325',50,
+ 500000,61,
+ '0xffda4053','0x1ffffbce4217',45,
+ '0xffda4052d666a983','0x1ffffbce4217d2849cb2',77,
+ 61,500000,
+ ], 128 => [
+ '0xfa000000','0x1e000000',29,
+ '0xfa00000000000000','0x1e00000000000000',61,
+ 125,16,
+ '0x83126e98','0x3f7ced916',34,
+ '0x83126e978d4fdf3c','0x3f7ced916872b020c',66,
+ 16,125,
+ '0xf4240000','0x40000',19,
+ '0xf424000000000000','0x4000000000000',51,
+ 15625,2,
+ '0x8637bd06','0xfffbce4217d',44,
+ '0x8637bd05af6c69b6','0xfffbce4217d2849cb25',76,
+ 2,15625,
+ ], 200 => [
+ '0xa0000000','0x0',29,
+ '0xa000000000000000','0x0',61,
+ 5,1,
+ '0xcccccccd','0x333333333',34,
+ '0xcccccccccccccccd','0x33333333333333333',66,
+ 1,5,
+ '0x9c400000','0x0',19,
+ '0x9c40000000000000','0x0',51,
+ 5000,1,
+ '0xd1b71759','0xfff2e48e8a7',44,
+ '0xd1b71758e219652c','0xfff2e48e8a71de69ad4',76,
+ 1,5000,
+ ], 250 => [
+ '0x80000000','0x0',29,
+ '0x8000000000000000','0x0',61,
+ 4,1,
+ '0x80000000','0x180000000',33,
+ '0x8000000000000000','0x18000000000000000',65,
+ 1,4,
+ '0xfa000000','0x0',20,
+ '0xfa00000000000000','0x0',52,
+ 4000,1,
+ '0x83126e98','0x7ff7ced9168',43,
+ '0x83126e978d4fdf3c','0x7ff7ced916872b020c4',75,
+ 1,4000,
+ ], 256 => [
+ '0xfa000000','0x3e000000',30,
+ '0xfa00000000000000','0x3e00000000000000',62,
+ 125,32,
+ '0x83126e98','0x1fbe76c8b',33,
+ '0x83126e978d4fdf3c','0x1fbe76c8b43958106',65,
+ 32,125,
+ '0xf4240000','0xc0000',20,
+ '0xf424000000000000','0xc000000000000',52,
+ 15625,4,
+ '0x8637bd06','0x7ffde7210be',43,
+ '0x8637bd05af6c69b6','0x7ffde7210be9424e592',75,
+ 4,15625,
+ ], 300 => [
+ '0xd5555556','0x2aaaaaaa',30,
+ '0xd555555555555556','0x2aaaaaaaaaaaaaaa',62,
+ 10,3,
+ '0x9999999a','0x1cccccccc',33,
+ '0x999999999999999a','0x1cccccccccccccccc',65,
+ 3,10,
+ '0xd0555556','0xaaaaa',20,
+ '0xd055555555555556','0xaaaaaaaaaaaaa',52,
+ 10000,3,
+ '0x9d495183','0x7ffcb923a29',43,
+ '0x9d495182a9930be1','0x7ffcb923a29c779a6b5',75,
+ 3,10000,
+ ], 512 => [
+ '0xfa000000','0x7e000000',31,
+ '0xfa00000000000000','0x7e00000000000000',63,
+ 125,64,
+ '0x83126e98','0xfdf3b645',32,
+ '0x83126e978d4fdf3c','0xfdf3b645a1cac083',64,
+ 64,125,
+ '0xf4240000','0x1c0000',21,
+ '0xf424000000000000','0x1c000000000000',53,
+ 15625,8,
+ '0x8637bd06','0x3ffef39085f',42,
+ '0x8637bd05af6c69b6','0x3ffef39085f4a1272c9',74,
+ 8,15625,
+ ], 1000 => [
+ '0x80000000','0x0',31,
+ '0x8000000000000000','0x0',63,
+ 1,1,
+ '0x80000000','0x0',31,
+ '0x8000000000000000','0x0',63,
+ 1,1,
+ '0xfa000000','0x0',22,
+ '0xfa00000000000000','0x0',54,
+ 1000,1,
+ '0x83126e98','0x1ff7ced9168',41,
+ '0x83126e978d4fdf3c','0x1ff7ced916872b020c4',73,
+ 1,1000,
+ ], 1024 => [
+ '0xfa000000','0xfe000000',32,
+ '0xfa00000000000000','0xfe00000000000000',64,
+ 125,128,
+ '0x83126e98','0x7ef9db22',31,
+ '0x83126e978d4fdf3c','0x7ef9db22d0e56041',63,
+ 128,125,
+ '0xf4240000','0x3c0000',22,
+ '0xf424000000000000','0x3c000000000000',54,
+ 15625,16,
+ '0x8637bd06','0x1fff79c842f',41,
+ '0x8637bd05af6c69b6','0x1fff79c842fa5093964',73,
+ 16,15625,
+ ], 1200 => [
+ '0xd5555556','0xd5555555',32,
+ '0xd555555555555556','0xd555555555555555',64,
+ 5,6,
+ '0x9999999a','0x66666666',31,
+ '0x999999999999999a','0x6666666666666666',63,
+ 6,5,
+ '0xd0555556','0x2aaaaa',22,
+ '0xd055555555555556','0x2aaaaaaaaaaaaa',54,
+ 2500,3,
+ '0x9d495183','0x1ffcb923a29',41,
+ '0x9d495182a9930be1','0x1ffcb923a29c779a6b5',73,
+ 3,2500,
+ ]
+);
+
+$has_bigint = eval 'use Math::BigInt qw(bgcd); 1;';
+
+sub bint($)
+{
+ my($x) = @_;
+ return Math::BigInt->new($x);
+}
+
+#
+# Constants for division by reciprocal multiplication.
+# (bits, numerator, denominator)
+#
+sub fmul($$$)
+{
+ my ($b,$n,$d) = @_;
+
+ $n = bint($n);
+ $d = bint($d);
+
+ return scalar (($n << $b)+$d-bint(1))/$d;
+}
+
+sub fadj($$$)
+{
+ my($b,$n,$d) = @_;
+
+ $n = bint($n);
+ $d = bint($d);
+
+ $d = $d/bgcd($n, $d);
+ return scalar (($d-bint(1)) << $b)/$d;
+}
+
+sub fmuls($$$) {
+ my($b,$n,$d) = @_;
+ my($s,$m);
+ my($thres) = bint(1) << ($b-1);
+
+ $n = bint($n);
+ $d = bint($d);
+
+ for ($s = 0; 1; $s++) {
+ $m = fmul($s,$n,$d);
+ return $s if ($m >= $thres);
+ }
+ return 0;
+}
+
+# Provides mul, adj, and shr factors for a specific
+# (bit, time, hz) combination
+sub muladj($$$) {
+ my($b, $t, $hz) = @_;
+ my $s = fmuls($b, $t, $hz);
+ my $m = fmul($s, $t, $hz);
+ my $a = fadj($s, $t, $hz);
+ return ($m->as_hex(), $a->as_hex(), $s);
+}
+
+# Provides numerator, denominator values
+sub numden($$) {
+ my($n, $d) = @_;
+ my $g = bgcd($n, $d);
+ return ($n/$g, $d/$g);
+}
+
+# All values for a specific (time, hz) combo
+sub conversions($$) {
+ my ($t, $hz) = @_;
+ my @val = ();
+
+ # HZ_TO_xx
+ push(@val, muladj(32, $t, $hz));
+ push(@val, muladj(64, $t, $hz));
+ push(@val, numden($t, $hz));
+
+ # xx_TO_HZ
+ push(@val, muladj(32, $hz, $t));
+ push(@val, muladj(64, $hz, $t));
+ push(@val, numden($hz, $t));
+
+ return @val;
+}
+
+sub compute_values($) {
+ my($hz) = @_;
+ my @val = ();
+ my $s, $m, $a, $g;
+
+ if (!$has_bigint) {
+ die "$0: HZ == $hz not canned and ".
+ "Math::BigInt not available\n";
+ }
+
+ # MSEC conversions
+ push(@val, conversions(1000, $hz));
+
+ # USEC conversions
+ push(@val, conversions(1000000, $hz));
+
+ return @val;
+}
+
+sub output($@)
+{
+ my($hz, @val) = @_;
+ my $pfx, $bit, $suf, $s, $m, $a;
+
+ print "/* Automatically generated by kernel/timeconst.pl */\n";
+ print "/* Conversion constants for HZ == $hz */\n";
+ print "\n";
+ print "#ifndef KERNEL_TIMECONST_H\n";
+ print "#define KERNEL_TIMECONST_H\n";
+ print "\n";
+
+ print "#include <linux/param.h>\n";
+
+ print "\n";
+ print "#if HZ != $hz\n";
+ print "#error \"kernel/timeconst.h has the wrong HZ value!\"\n";
+ print "#endif\n";
+ print "\n";
+
+ foreach $pfx ('HZ_TO_MSEC','MSEC_TO_HZ',
+ 'USEC_TO_HZ','HZ_TO_USEC') {
+ foreach $bit (32, 64) {
+ foreach $suf ('MUL', 'ADJ', 'SHR') {
+ printf "#define %-23s %s\n",
+ "${pfx}_$suf$bit", shift(@val);
+ }
+ }
+ foreach $suf ('NUM', 'DEN') {
+ printf "#define %-23s %s\n",
+ "${pfx}_$suf", shift(@val);
+ }
+ }
+
+ print "\n";
+ print "#endif /* KERNEL_TIMECONST_H */\n";
+}
+
+($hz) = @ARGV;
+
+# Use this to generate the %canned_values structure
+if ($hz eq '--can') {
+ shift(@ARGV);
+ @hzlist = sort {$a <=> $b} (@ARGV);
+
+ print "# Precomputed values for systems without Math::BigInt\n";
+ print "# Generated by:\n";
+ print "# timeconst.pl --can ", join(' ', @hzlist), "\n";
+ print "\%canned_values = (\n";
+ my $pf = "\t";
+ foreach $hz (@hzlist) {
+ my @values = compute_values($hz);
+ print "$pf$hz => [\n";
+ while (scalar(@values)) {
+ my $bit;
+ foreach $bit (32, 64) {
+ my $m = shift(@values);
+ my $a = shift(@values);
+ my $s = shift(@values);
+ print "\t\t\'",$m,"\',\'",$a,"\',",$s,",\n";
+ }
+ my $n = shift(@values);
+ my $d = shift(@values);
+ print "\t\t",$n,',',$d,",\n";
+ }
+ print "\t]";
+ $pf = ', ';
+ }
+ print "\n);\n";
+} else {
+ $hz += 0; # Force to number
+ if ($hz < 1) {
+ die "Usage: $0 HZ\n";
+ }
+
+ @val = @{$canned_values{$hz}};
+ if (!defined(@val)) {
+ @val = compute_values($hz);
+ }
+ output($hz, @val);
+}
+exit 0;
* init_timer() must be done to a timer prior calling *any* of the
* other timer functions.
*/
-void fastcall init_timer(struct timer_list *timer)
+void init_timer(struct timer_list *timer)
{
timer->entry.next = NULL;
timer->base = __raw_get_cpu_var(tvec_bases);
}
EXPORT_SYMBOL(init_timer);
-void fastcall init_timer_deferrable(struct timer_list *timer)
+void init_timer_deferrable(struct timer_list *timer)
{
init_timer(timer);
timer_set_deferrable(timer);
int pid;
rcu_read_lock();
- pid = task_tgid_nr_ns(current->real_parent, current->nsproxy->pid_ns);
+ pid = task_tgid_vnr(current->real_parent);
rcu_read_unlock();
return pid;
*
* In all cases the return value is guaranteed to be non-negative.
*/
-fastcall signed long __sched schedule_timeout(signed long timeout)
+signed long __sched schedule_timeout(signed long timeout)
{
struct timer_list timer;
unsigned long expire;
#include <linux/module.h>
#include <linux/user_namespace.h>
+struct user_namespace init_user_ns = {
+ .kref = {
+ .refcount = ATOMIC_INIT(2),
+ },
+ .root_user = &root_user,
+};
+EXPORT_SYMBOL_GPL(init_user_ns);
+
/*
* UID task count cache, to get fast user lookup in "alloc_uid"
* when changing user ID's (ie setuid() and friends).
suid_keys(current);
}
+#ifdef CONFIG_USER_NS
void release_uids(struct user_namespace *ns)
{
int i;
free_uid(ns->root_user);
}
+#endif
static int __init uid_cache_init(void)
{
#include <linux/nsproxy.h>
#include <linux/user_namespace.h>
-struct user_namespace init_user_ns = {
- .kref = {
- .refcount = ATOMIC_INIT(2),
- },
- .root_user = &root_user,
-};
-
-EXPORT_SYMBOL_GPL(init_user_ns);
-
-#ifdef CONFIG_USER_NS
-
/*
* Clone a new ns copying an original user ns, setting refcount to 1
* @old_ns: namespace to clone
release_uids(ns);
kfree(ns);
}
-
-#endif /* CONFIG_USER_NS */
EXPORT_SYMBOL(init_waitqueue_head);
-void fastcall add_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
+void add_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
{
unsigned long flags;
}
EXPORT_SYMBOL(add_wait_queue);
-void fastcall add_wait_queue_exclusive(wait_queue_head_t *q, wait_queue_t *wait)
+void add_wait_queue_exclusive(wait_queue_head_t *q, wait_queue_t *wait)
{
unsigned long flags;
}
EXPORT_SYMBOL(add_wait_queue_exclusive);
-void fastcall remove_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
+void remove_wait_queue(wait_queue_head_t *q, wait_queue_t *wait)
{
unsigned long flags;
* stops them from bleeding out - it would still allow subsequent
* loads to move into the critical region).
*/
-void fastcall
+void
prepare_to_wait(wait_queue_head_t *q, wait_queue_t *wait, int state)
{
unsigned long flags;
}
EXPORT_SYMBOL(prepare_to_wait);
-void fastcall
+void
prepare_to_wait_exclusive(wait_queue_head_t *q, wait_queue_t *wait, int state)
{
unsigned long flags;
}
EXPORT_SYMBOL(prepare_to_wait_exclusive);
-void fastcall finish_wait(wait_queue_head_t *q, wait_queue_t *wait)
+void finish_wait(wait_queue_head_t *q, wait_queue_t *wait)
{
unsigned long flags;
* waiting, the actions of __wait_on_bit() and __wait_on_bit_lock() are
* permitted return codes. Nonzero return codes halt waiting and return.
*/
-int __sched fastcall
+int __sched
__wait_on_bit(wait_queue_head_t *wq, struct wait_bit_queue *q,
int (*action)(void *), unsigned mode)
{
}
EXPORT_SYMBOL(__wait_on_bit);
-int __sched fastcall out_of_line_wait_on_bit(void *word, int bit,
+int __sched out_of_line_wait_on_bit(void *word, int bit,
int (*action)(void *), unsigned mode)
{
wait_queue_head_t *wq = bit_waitqueue(word, bit);
}
EXPORT_SYMBOL(out_of_line_wait_on_bit);
-int __sched fastcall
+int __sched
__wait_on_bit_lock(wait_queue_head_t *wq, struct wait_bit_queue *q,
int (*action)(void *), unsigned mode)
{
}
EXPORT_SYMBOL(__wait_on_bit_lock);
-int __sched fastcall out_of_line_wait_on_bit_lock(void *word, int bit,
+int __sched out_of_line_wait_on_bit_lock(void *word, int bit,
int (*action)(void *), unsigned mode)
{
wait_queue_head_t *wq = bit_waitqueue(word, bit);
}
EXPORT_SYMBOL(out_of_line_wait_on_bit_lock);
-void fastcall __wake_up_bit(wait_queue_head_t *wq, void *word, int bit)
+void __wake_up_bit(wait_queue_head_t *wq, void *word, int bit)
{
struct wait_bit_key key = __WAIT_BIT_KEY_INITIALIZER(word, bit);
if (waitqueue_active(wq))
* may need to use a less regular barrier, such fs/inode.c's smp_mb(),
* because spin_unlock() does not guarantee a memory barrier.
*/
-void fastcall wake_up_bit(void *word, int bit)
+void wake_up_bit(void *word, int bit)
{
__wake_up_bit(bit_waitqueue(word, bit), word, bit);
}
EXPORT_SYMBOL(wake_up_bit);
-fastcall wait_queue_head_t *bit_waitqueue(void *word, int bit)
+wait_queue_head_t *bit_waitqueue(void *word, int bit)
{
const int shift = BITS_PER_LONG == 32 ? 5 : 6;
const struct zone *zone = page_zone(virt_to_page(word));
* We queue the work to the CPU it was submitted, but there is no
* guarantee that it will be processed by that CPU.
*/
-int fastcall queue_work(struct workqueue_struct *wq, struct work_struct *work)
+int queue_work(struct workqueue_struct *wq, struct work_struct *work)
{
int ret = 0;
}
EXPORT_SYMBOL_GPL(queue_work);
-void delayed_work_timer_fn(unsigned long __data)
+static void delayed_work_timer_fn(unsigned long __data)
{
struct delayed_work *dwork = (struct delayed_work *)__data;
struct cpu_workqueue_struct *cwq = get_wq_data(&dwork->work);
*
* Returns 0 if @work was already on a queue, non-zero otherwise.
*/
-int fastcall queue_delayed_work(struct workqueue_struct *wq,
+int queue_delayed_work(struct workqueue_struct *wq,
struct delayed_work *dwork, unsigned long delay)
{
timer_stats_timer_set_start_info(&dwork->timer);
* This function used to run the workqueues itself. Now we just wait for the
* helper threads to do it.
*/
-void fastcall flush_workqueue(struct workqueue_struct *wq)
+void flush_workqueue(struct workqueue_struct *wq)
{
const cpumask_t *cpu_map = wq_cpu_map(wq);
int cpu;
*
* This puts a job in the kernel-global workqueue.
*/
-int fastcall schedule_work(struct work_struct *work)
+int schedule_work(struct work_struct *work)
{
return queue_work(keventd_wq, work);
}
* After waiting for a given time this puts a job in the kernel-global
* workqueue.
*/
-int fastcall schedule_delayed_work(struct delayed_work *dwork,
+int schedule_delayed_work(struct delayed_work *dwork,
unsigned long delay)
{
timer_stats_timer_set_start_info(&dwork->timer);
config DEBUG_BUGVERBOSE
bool "Verbose BUG() reporting (adds 70K)" if DEBUG_KERNEL && EMBEDDED
depends on BUG
- depends on ARM || AVR32 || M32R || M68K || SPARC32 || SPARC64 || FRV || SUPERH || GENERIC_BUG || BLACKFIN
+ depends on ARM || AVR32 || M32R || M68K || SPARC32 || SPARC64 || \
+ FRV || SUPERH || GENERIC_BUG || BLACKFIN || MN10300
default !EMBEDDED
help
Say Y here to make BUG() panics output the file name and line number
config FRAME_POINTER
bool "Compile the kernel with frame pointers"
- depends on DEBUG_KERNEL && (X86 || CRIS || M68K || M68KNOMMU || FRV || UML || S390 || AVR32 || SUPERH || BLACKFIN)
+ depends on DEBUG_KERNEL && \
+ (X86 || CRIS || M68K || M68KNOMMU || FRV || UML || S390 || \
+ AVR32 || SUPERH || BLACKFIN || MN10300)
default y if DEBUG_INFO && UML
help
If you say Y here the resulting kernel image will be slightly larger
rbtree.o radix-tree.o dump_stack.o \
idr.o int_sqrt.o extable.o prio_tree.o \
sha1.o irq_regs.o reciprocal_div.o argv_split.o \
- proportions.o prio_heap.o scatterlist.o
+ proportions.o prio_heap.o
lib-$(CONFIG_MMU) += ioremap.o
lib-$(CONFIG_SMP) += cpumask.o
lib-y += kobject.o kref.o klist.o
obj-y += div64.o sort.o parser.o halfmd4.o debug_locks.o random32.o \
- bust_spinlocks.o hexdump.o kasprintf.o bitmap.o
+ bust_spinlocks.o hexdump.o kasprintf.o bitmap.o scatterlist.o
ifeq ($(CONFIG_DEBUG_KOBJECT),y)
CFLAGS_kobject.o += -DDEBUG
#ifdef CONFIG_FAULT_INJECTION_DEBUG_FS
-static void debugfs_ul_set(void *data, u64 val)
+static int debugfs_ul_set(void *data, u64 val)
{
*(unsigned long *)data = val;
+ return 0;
}
#ifdef CONFIG_FAULT_INJECTION_STACKTRACE_FILTER
-static void debugfs_ul_set_MAX_STACK_TRACE_DEPTH(void *data, u64 val)
+static int debugfs_ul_set_MAX_STACK_TRACE_DEPTH(void *data, u64 val)
{
*(unsigned long *)data =
val < MAX_STACK_TRACE_DEPTH ?
val : MAX_STACK_TRACE_DEPTH;
+ return 0;
}
#endif /* CONFIG_FAULT_INJECTION_STACKTRACE_FILTER */
-static u64 debugfs_ul_get(void *data)
+static int debugfs_ul_get(void *data, u64 *val)
{
- return *(unsigned long *)data;
+ *val = *(unsigned long *)data;
+ return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_ul, debugfs_ul_get, debugfs_ul_set, "%llu\n");
}
#endif /* CONFIG_FAULT_INJECTION_STACKTRACE_FILTER */
-static void debugfs_atomic_t_set(void *data, u64 val)
+static int debugfs_atomic_t_set(void *data, u64 val)
{
atomic_set((atomic_t *)data, val);
+ return 0;
}
-static u64 debugfs_atomic_t_get(void *data)
+static int debugfs_atomic_t_get(void *data, u64 *val)
{
- return atomic_read((atomic_t *)data);
+ *val = atomic_read((atomic_t *)data);
+ return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(fops_atomic_t, debugfs_atomic_t_get,
#define mmio_read32be(addr) be32_to_cpu(__raw_readl(addr))
#endif
-unsigned int fastcall ioread8(void __iomem *addr)
+unsigned int ioread8(void __iomem *addr)
{
IO_COND(addr, return inb(port), return readb(addr));
return 0xff;
}
-unsigned int fastcall ioread16(void __iomem *addr)
+unsigned int ioread16(void __iomem *addr)
{
IO_COND(addr, return inw(port), return readw(addr));
return 0xffff;
}
-unsigned int fastcall ioread16be(void __iomem *addr)
+unsigned int ioread16be(void __iomem *addr)
{
IO_COND(addr, return pio_read16be(port), return mmio_read16be(addr));
return 0xffff;
}
-unsigned int fastcall ioread32(void __iomem *addr)
+unsigned int ioread32(void __iomem *addr)
{
IO_COND(addr, return inl(port), return readl(addr));
return 0xffffffff;
}
-unsigned int fastcall ioread32be(void __iomem *addr)
+unsigned int ioread32be(void __iomem *addr)
{
IO_COND(addr, return pio_read32be(port), return mmio_read32be(addr));
return 0xffffffff;
#define mmio_write32be(val,port) __raw_writel(be32_to_cpu(val),port)
#endif
-void fastcall iowrite8(u8 val, void __iomem *addr)
+void iowrite8(u8 val, void __iomem *addr)
{
IO_COND(addr, outb(val,port), writeb(val, addr));
}
-void fastcall iowrite16(u16 val, void __iomem *addr)
+void iowrite16(u16 val, void __iomem *addr)
{
IO_COND(addr, outw(val,port), writew(val, addr));
}
-void fastcall iowrite16be(u16 val, void __iomem *addr)
+void iowrite16be(u16 val, void __iomem *addr)
{
IO_COND(addr, pio_write16be(val,port), mmio_write16be(val, addr));
}
-void fastcall iowrite32(u32 val, void __iomem *addr)
+void iowrite32(u32 val, void __iomem *addr)
{
IO_COND(addr, outl(val,port), writel(val, addr));
}
-void fastcall iowrite32be(u32 val, void __iomem *addr)
+void iowrite32be(u32 val, void __iomem *addr)
{
IO_COND(addr, pio_write32be(val,port), mmio_write32be(val, addr));
}
}
#endif
-void fastcall ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
+void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
{
IO_COND(addr, insb(port,dst,count), mmio_insb(addr, dst, count));
}
-void fastcall ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
+void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
{
IO_COND(addr, insw(port,dst,count), mmio_insw(addr, dst, count));
}
-void fastcall ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
+void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
{
IO_COND(addr, insl(port,dst,count), mmio_insl(addr, dst, count));
}
EXPORT_SYMBOL(ioread16_rep);
EXPORT_SYMBOL(ioread32_rep);
-void fastcall iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
+void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
{
IO_COND(addr, outsb(port, src, count), mmio_outsb(addr, src, count));
}
-void fastcall iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
+void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
{
IO_COND(addr, outsw(port, src, count), mmio_outsw(addr, src, count));
}
-void fastcall iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
+void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
{
IO_COND(addr, outsl(port, src,count), mmio_outsl(addr, src, count));
}
/*
* get a read lock on the semaphore
*/
-void fastcall __sched __down_read(struct rw_semaphore *sem)
+void __sched __down_read(struct rw_semaphore *sem)
{
struct rwsem_waiter waiter;
struct task_struct *tsk;
/*
* trylock for reading -- returns 1 if successful, 0 if contention
*/
-int fastcall __down_read_trylock(struct rw_semaphore *sem)
+int __down_read_trylock(struct rw_semaphore *sem)
{
unsigned long flags;
int ret = 0;
* get a write lock on the semaphore
* - we increment the waiting count anyway to indicate an exclusive lock
*/
-void fastcall __sched __down_write_nested(struct rw_semaphore *sem, int subclass)
+void __sched __down_write_nested(struct rw_semaphore *sem, int subclass)
{
struct rwsem_waiter waiter;
struct task_struct *tsk;
;
}
-void fastcall __sched __down_write(struct rw_semaphore *sem)
+void __sched __down_write(struct rw_semaphore *sem)
{
__down_write_nested(sem, 0);
}
/*
* trylock for writing -- returns 1 if successful, 0 if contention
*/
-int fastcall __down_write_trylock(struct rw_semaphore *sem)
+int __down_write_trylock(struct rw_semaphore *sem)
{
unsigned long flags;
int ret = 0;
/*
* release a read lock on the semaphore
*/
-void fastcall __up_read(struct rw_semaphore *sem)
+void __up_read(struct rw_semaphore *sem)
{
unsigned long flags;
/*
* release a write lock on the semaphore
*/
-void fastcall __up_write(struct rw_semaphore *sem)
+void __up_write(struct rw_semaphore *sem)
{
unsigned long flags;
* downgrade a write lock into a read lock
* - just wake up any readers at the front of the queue
*/
-void fastcall __downgrade_write(struct rw_semaphore *sem)
+void __downgrade_write(struct rw_semaphore *sem)
{
unsigned long flags;
* we cannot lose wakeup events.
*/
-fastcall void __up(struct semaphore *sem)
+void __up(struct semaphore *sem)
{
wake_up(&sem->wait);
}
-fastcall void __sched __down(struct semaphore * sem)
+void __sched __down(struct semaphore *sem)
{
struct task_struct *tsk = current;
DECLARE_WAITQUEUE(wait, tsk);
tsk->state = TASK_RUNNING;
}
-fastcall int __sched __down_interruptible(struct semaphore * sem)
+int __sched __down_interruptible(struct semaphore *sem)
{
int retval = 0;
struct task_struct *tsk = current;
* single "cmpxchg" without failure cases,
* but then it wouldn't work on a 386.
*/
-fastcall int __down_trylock(struct semaphore * sem)
+int __down_trylock(struct semaphore *sem)
{
int sleepers;
unsigned long flags;
return simple_strtoull(cp,endp,base);
}
+
+/**
+ * strict_strtoul - convert a string to an unsigned long strictly
+ * @cp: The string to be converted
+ * @base: The number base to use
+ * @res: The converted result value
+ *
+ * strict_strtoul converts a string to an unsigned long only if the
+ * string is really an unsigned long string, any string containing
+ * any invalid char at the tail will be rejected and -EINVAL is returned,
+ * only a newline char at the tail is acceptible because people generally
+ * change a module parameter in the following way:
+ *
+ * echo 1024 > /sys/module/e1000/parameters/copybreak
+ *
+ * echo will append a newline to the tail.
+ *
+ * It returns 0 if conversion is successful and *res is set to the converted
+ * value, otherwise it returns -EINVAL and *res is set to 0.
+ *
+ * simple_strtoul just ignores the successive invalid characters and
+ * return the converted value of prefix part of the string.
+ */
+int strict_strtoul(const char *cp, unsigned int base, unsigned long *res);
+
+/**
+ * strict_strtol - convert a string to a long strictly
+ * @cp: The string to be converted
+ * @base: The number base to use
+ * @res: The converted result value
+ *
+ * strict_strtol is similiar to strict_strtoul, but it allows the first
+ * character of a string is '-'.
+ *
+ * It returns 0 if conversion is successful and *res is set to the converted
+ * value, otherwise it returns -EINVAL and *res is set to 0.
+ */
+int strict_strtol(const char *cp, unsigned int base, long *res);
+
+/**
+ * strict_strtoull - convert a string to an unsigned long long strictly
+ * @cp: The string to be converted
+ * @base: The number base to use
+ * @res: The converted result value
+ *
+ * strict_strtoull converts a string to an unsigned long long only if the
+ * string is really an unsigned long long string, any string containing
+ * any invalid char at the tail will be rejected and -EINVAL is returned,
+ * only a newline char at the tail is acceptible because people generally
+ * change a module parameter in the following way:
+ *
+ * echo 1024 > /sys/module/e1000/parameters/copybreak
+ *
+ * echo will append a newline to the tail of the string.
+ *
+ * It returns 0 if conversion is successful and *res is set to the converted
+ * value, otherwise it returns -EINVAL and *res is set to 0.
+ *
+ * simple_strtoull just ignores the successive invalid characters and
+ * return the converted value of prefix part of the string.
+ */
+int strict_strtoull(const char *cp, unsigned int base, unsigned long long *res);
+
+/**
+ * strict_strtoll - convert a string to a long long strictly
+ * @cp: The string to be converted
+ * @base: The number base to use
+ * @res: The converted result value
+ *
+ * strict_strtoll is similiar to strict_strtoull, but it allows the first
+ * character of a string is '-'.
+ *
+ * It returns 0 if conversion is successful and *res is set to the converted
+ * value, otherwise it returns -EINVAL and *res is set to 0.
+ */
+int strict_strtoll(const char *cp, unsigned int base, long long *res);
+
+#define define_strict_strtoux(type, valtype) \
+int strict_strtou##type(const char *cp, unsigned int base, valtype *res)\
+{ \
+ char *tail; \
+ valtype val; \
+ size_t len; \
+ \
+ *res = 0; \
+ len = strlen(cp); \
+ if (len == 0) \
+ return -EINVAL; \
+ \
+ val = simple_strtoul(cp, &tail, base); \
+ if ((*tail == '\0') || \
+ ((len == (size_t)(tail - cp) + 1) && (*tail == '\n'))) {\
+ *res = val; \
+ return 0; \
+ } \
+ \
+ return -EINVAL; \
+} \
+
+#define define_strict_strtox(type, valtype) \
+int strict_strto##type(const char *cp, unsigned int base, valtype *res) \
+{ \
+ int ret; \
+ if (*cp == '-') { \
+ ret = strict_strtou##type(cp+1, base, res); \
+ if (ret != 0) \
+ *res = -(*res); \
+ } else \
+ ret = strict_strtou##type(cp, base, res); \
+ \
+ return ret; \
+} \
+
+define_strict_strtoux(l, unsigned long)
+define_strict_strtox(l, long)
+define_strict_strtoux(ll, unsigned long long)
+define_strict_strtox(ll, long long)
+
+EXPORT_SYMBOL(strict_strtoul);
+EXPORT_SYMBOL(strict_strtol);
+EXPORT_SYMBOL(strict_strtoll);
+EXPORT_SYMBOL(strict_strtoull);
+
static int skip_atoi(const char **s)
{
int i=0;
}
/**
- * do_generic_mapping_read - generic file read routine
- * @mapping: address_space to be read
- * @ra: file's readahead state
+ * do_generic_file_read - generic file read routine
* @filp: the file to read
* @ppos: current file position
* @desc: read_descriptor
*
* This is really ugly. But the goto's actually try to clarify some
* of the logic when it comes to error handling etc.
- *
- * Note the struct file* is only passed for the use of readpage.
- * It may be NULL.
*/
-void do_generic_mapping_read(struct address_space *mapping,
- struct file_ra_state *ra,
- struct file *filp,
- loff_t *ppos,
- read_descriptor_t *desc,
- read_actor_t actor)
+static void do_generic_file_read(struct file *filp, loff_t *ppos,
+ read_descriptor_t *desc, read_actor_t actor)
{
+ struct address_space *mapping = filp->f_mapping;
struct inode *inode = mapping->host;
+ struct file_ra_state *ra = &filp->f_ra;
pgoff_t index;
pgoff_t last_index;
pgoff_t prev_index;
if (filp)
file_accessed(filp);
}
-EXPORT_SYMBOL(do_generic_mapping_read);
int file_read_actor(read_descriptor_t *desc, struct page *page,
unsigned long offset, unsigned long size)
struct file_ra_state *ra = &file->f_ra;
struct inode *inode = mapping->host;
struct page *page;
- unsigned long size;
+ pgoff_t size;
int did_readaround = 0;
int ret = 0;
read_actor_t actor)
{
struct inode *inode = mapping->host;
- unsigned long index, end_index, offset;
+ pgoff_t index, end_index;
+ unsigned long offset;
loff_t isize;
BUG_ON(!mapping->a_ops->get_xip_page);
return 0;
}
+int hugetlb_overcommit_handler(struct ctl_table *table, int write,
+ struct file *file, void __user *buffer,
+ size_t *length, loff_t *ppos)
+{
+ spin_lock(&hugetlb_lock);
+ proc_doulongvec_minmax(table, write, file, buffer, length, ppos);
+ spin_unlock(&hugetlb_lock);
+ return 0;
+}
+
#endif /* CONFIG_SYSCTL */
int hugetlb_report_meminfo(char *buf)
*/
static void free_pte_range(struct mmu_gather *tlb, pmd_t *pmd)
{
- struct page *page = pmd_page(*pmd);
+ pgtable_t token = pmd_pgtable(*pmd);
pmd_clear(pmd);
- pte_lock_deinit(page);
- pte_free_tlb(tlb, page);
- dec_zone_page_state(page, NR_PAGETABLE);
+ pte_free_tlb(tlb, token);
tlb->mm->nr_ptes--;
}
int __pte_alloc(struct mm_struct *mm, pmd_t *pmd, unsigned long address)
{
- struct page *new = pte_alloc_one(mm, address);
+ pgtable_t new = pte_alloc_one(mm, address);
if (!new)
return -ENOMEM;
- pte_lock_init(new);
spin_lock(&mm->page_table_lock);
- if (pmd_present(*pmd)) { /* Another has populated it */
- pte_lock_deinit(new);
- pte_free(mm, new);
- } else {
+ if (!pmd_present(*pmd)) { /* Has another populated it ? */
mm->nr_ptes++;
- inc_zone_page_state(new, NR_PAGETABLE);
pmd_populate(mm, pmd, new);
+ new = NULL;
}
spin_unlock(&mm->page_table_lock);
+ if (new)
+ pte_free(mm, new);
return 0;
}
return -ENOMEM;
spin_lock(&init_mm.page_table_lock);
- if (pmd_present(*pmd)) /* Another has populated it */
- pte_free_kernel(&init_mm, new);
- else
+ if (!pmd_present(*pmd)) { /* Has another populated it ? */
pmd_populate_kernel(&init_mm, pmd, new);
+ new = NULL;
+ }
spin_unlock(&init_mm.page_table_lock);
+ if (new)
+ pte_free_kernel(&init_mm, new);
return 0;
}
{
pte_t *pte;
int err;
- struct page *pmd_page;
+ pgtable_t token;
spinlock_t *uninitialized_var(ptl);
pte = (mm == &init_mm) ?
BUG_ON(pmd_huge(*pmd));
- pmd_page = pmd_page(*pmd);
+ token = pmd_pgtable(*pmd);
do {
- err = fn(pte, pmd_page, addr, data);
+ err = fn(pte, token, addr, data);
if (err)
break;
} while (pte++, addr += PAGE_SIZE, addr != end);
}
-static struct page *special_mapping_nopage(struct vm_area_struct *vma,
- unsigned long address, int *type)
+static int special_mapping_fault(struct vm_area_struct *vma,
+ struct vm_fault *vmf)
{
+ pgoff_t pgoff;
struct page **pages;
- BUG_ON(address < vma->vm_start || address >= vma->vm_end);
+ /*
+ * special mappings have no vm_file, and in that case, the mm
+ * uses vm_pgoff internally. So we have to subtract it from here.
+ * We are allowed to do this because we are the mm; do not copy
+ * this code into drivers!
+ */
+ pgoff = vmf->pgoff - vma->vm_pgoff;
- address -= vma->vm_start;
- for (pages = vma->vm_private_data; address > 0 && *pages; ++pages)
- address -= PAGE_SIZE;
+ for (pages = vma->vm_private_data; pgoff && *pages; ++pages)
+ pgoff--;
if (*pages) {
struct page *page = *pages;
get_page(page);
- return page;
+ vmf->page = page;
+ return 0;
}
- return NOPAGE_SIGBUS;
+ return VM_FAULT_SIGBUS;
}
/*
static struct vm_operations_struct special_mapping_vmops = {
.close = special_mapping_close,
- .nopage = special_mapping_nopage,
+ .fault = special_mapping_fault,
};
/*
/*
* This is the 'heart' of the zoned buddy allocator.
*/
-struct page * fastcall
+struct page *
__alloc_pages(gfp_t gfp_mask, unsigned int order,
struct zonelist *zonelist)
{
#include <linux/ctype.h>
#include <linux/migrate.h>
#include <linux/highmem.h>
+#include <linux/seq_file.h>
#include <asm/uaccess.h>
#include <asm/div64.h>
SGP_WRITE, /* may exceed i_size, may allocate page */
};
+#ifdef CONFIG_TMPFS
+static unsigned long shmem_default_max_blocks(void)
+{
+ return totalram_pages / 2;
+}
+
+static unsigned long shmem_default_max_inodes(void)
+{
+ return min(totalram_pages - totalhigh_pages, totalram_pages / 2);
+}
+#endif
+
static int shmem_getpage(struct inode *inode, unsigned long idx,
struct page **pagep, enum sgp_type sgp, int *type);
}
#ifdef CONFIG_NUMA
-static inline int shmem_parse_mpol(char *value, int *policy, nodemask_t *policy_nodes)
+#ifdef CONFIG_TMPFS
+static int shmem_parse_mpol(char *value, int *policy, nodemask_t *policy_nodes)
{
char *nodelist = strchr(value, ':');
int err = 1;
return err;
}
+static void shmem_show_mpol(struct seq_file *seq, int policy,
+ const nodemask_t policy_nodes)
+{
+ char *policy_string;
+
+ switch (policy) {
+ case MPOL_PREFERRED:
+ policy_string = "prefer";
+ break;
+ case MPOL_BIND:
+ policy_string = "bind";
+ break;
+ case MPOL_INTERLEAVE:
+ policy_string = "interleave";
+ break;
+ default:
+ /* MPOL_DEFAULT */
+ return;
+ }
+
+ seq_printf(seq, ",mpol=%s", policy_string);
+
+ if (policy != MPOL_INTERLEAVE ||
+ !nodes_equal(policy_nodes, node_states[N_HIGH_MEMORY])) {
+ char buffer[64];
+ int len;
+
+ len = nodelist_scnprintf(buffer, sizeof(buffer), policy_nodes);
+ if (len < sizeof(buffer))
+ seq_printf(seq, ":%s", buffer);
+ else
+ seq_printf(seq, ":?");
+ }
+}
+#endif /* CONFIG_TMPFS */
+
static struct page *shmem_swapin(swp_entry_t entry, gfp_t gfp,
struct shmem_inode_info *info, unsigned long idx)
{
mpol_free(pvma.vm_policy);
return page;
}
-#else
+#else /* !CONFIG_NUMA */
+#ifdef CONFIG_TMPFS
static inline int shmem_parse_mpol(char *value, int *policy,
nodemask_t *policy_nodes)
{
return 1;
}
+static inline void shmem_show_mpol(struct seq_file *seq, int policy,
+ const nodemask_t policy_nodes)
+{
+}
+#endif /* CONFIG_TMPFS */
+
static inline struct page *shmem_swapin(swp_entry_t entry, gfp_t gfp,
struct shmem_inode_info *info, unsigned long idx)
{
{
return alloc_page(gfp);
}
-#endif
+#endif /* CONFIG_NUMA */
/*
* shmem_getpage - either get the page from swap or allocate a new one
.fh_to_dentry = shmem_fh_to_dentry,
};
-static int shmem_parse_options(char *options, int *mode, uid_t *uid,
- gid_t *gid, unsigned long *blocks, unsigned long *inodes,
- int *policy, nodemask_t *policy_nodes)
+static int shmem_parse_options(char *options, struct shmem_sb_info *sbinfo,
+ bool remount)
{
char *this_char, *value, *rest;
}
if (*rest)
goto bad_val;
- *blocks = DIV_ROUND_UP(size, PAGE_CACHE_SIZE);
+ sbinfo->max_blocks =
+ DIV_ROUND_UP(size, PAGE_CACHE_SIZE);
} else if (!strcmp(this_char,"nr_blocks")) {
- *blocks = memparse(value,&rest);
+ sbinfo->max_blocks = memparse(value, &rest);
if (*rest)
goto bad_val;
} else if (!strcmp(this_char,"nr_inodes")) {
- *inodes = memparse(value,&rest);
+ sbinfo->max_inodes = memparse(value, &rest);
if (*rest)
goto bad_val;
} else if (!strcmp(this_char,"mode")) {
- if (!mode)
+ if (remount)
continue;
- *mode = simple_strtoul(value,&rest,8);
+ sbinfo->mode = simple_strtoul(value, &rest, 8) & 07777;
if (*rest)
goto bad_val;
} else if (!strcmp(this_char,"uid")) {
- if (!uid)
+ if (remount)
continue;
- *uid = simple_strtoul(value,&rest,0);
+ sbinfo->uid = simple_strtoul(value, &rest, 0);
if (*rest)
goto bad_val;
} else if (!strcmp(this_char,"gid")) {
- if (!gid)
+ if (remount)
continue;
- *gid = simple_strtoul(value,&rest,0);
+ sbinfo->gid = simple_strtoul(value, &rest, 0);
if (*rest)
goto bad_val;
} else if (!strcmp(this_char,"mpol")) {
- if (shmem_parse_mpol(value,policy,policy_nodes))
+ if (shmem_parse_mpol(value, &sbinfo->policy,
+ &sbinfo->policy_nodes))
goto bad_val;
} else {
printk(KERN_ERR "tmpfs: Bad mount option %s\n",
static int shmem_remount_fs(struct super_block *sb, int *flags, char *data)
{
struct shmem_sb_info *sbinfo = SHMEM_SB(sb);
- unsigned long max_blocks = sbinfo->max_blocks;
- unsigned long max_inodes = sbinfo->max_inodes;
- int policy = sbinfo->policy;
- nodemask_t policy_nodes = sbinfo->policy_nodes;
+ struct shmem_sb_info config = *sbinfo;
unsigned long blocks;
unsigned long inodes;
int error = -EINVAL;
- if (shmem_parse_options(data, NULL, NULL, NULL, &max_blocks,
- &max_inodes, &policy, &policy_nodes))
+ if (shmem_parse_options(data, &config, true))
return error;
spin_lock(&sbinfo->stat_lock);
blocks = sbinfo->max_blocks - sbinfo->free_blocks;
inodes = sbinfo->max_inodes - sbinfo->free_inodes;
- if (max_blocks < blocks)
+ if (config.max_blocks < blocks)
goto out;
- if (max_inodes < inodes)
+ if (config.max_inodes < inodes)
goto out;
/*
* Those tests also disallow limited->unlimited while any are in
* but we must separately disallow unlimited->limited, because
* in that case we have no record of how much is already in use.
*/
- if (max_blocks && !sbinfo->max_blocks)
+ if (config.max_blocks && !sbinfo->max_blocks)
goto out;
- if (max_inodes && !sbinfo->max_inodes)
+ if (config.max_inodes && !sbinfo->max_inodes)
goto out;
error = 0;
- sbinfo->max_blocks = max_blocks;
- sbinfo->free_blocks = max_blocks - blocks;
- sbinfo->max_inodes = max_inodes;
- sbinfo->free_inodes = max_inodes - inodes;
- sbinfo->policy = policy;
- sbinfo->policy_nodes = policy_nodes;
+ sbinfo->max_blocks = config.max_blocks;
+ sbinfo->free_blocks = config.max_blocks - blocks;
+ sbinfo->max_inodes = config.max_inodes;
+ sbinfo->free_inodes = config.max_inodes - inodes;
+ sbinfo->policy = config.policy;
+ sbinfo->policy_nodes = config.policy_nodes;
out:
spin_unlock(&sbinfo->stat_lock);
return error;
}
-#endif
+
+static int shmem_show_options(struct seq_file *seq, struct vfsmount *vfs)
+{
+ struct shmem_sb_info *sbinfo = SHMEM_SB(vfs->mnt_sb);
+
+ if (sbinfo->max_blocks != shmem_default_max_blocks())
+ seq_printf(seq, ",size=%luk",
+ sbinfo->max_blocks << (PAGE_CACHE_SHIFT - 10));
+ if (sbinfo->max_inodes != shmem_default_max_inodes())
+ seq_printf(seq, ",nr_inodes=%lu", sbinfo->max_inodes);
+ if (sbinfo->mode != (S_IRWXUGO | S_ISVTX))
+ seq_printf(seq, ",mode=%03o", sbinfo->mode);
+ if (sbinfo->uid != 0)
+ seq_printf(seq, ",uid=%u", sbinfo->uid);
+ if (sbinfo->gid != 0)
+ seq_printf(seq, ",gid=%u", sbinfo->gid);
+ shmem_show_mpol(seq, sbinfo->policy, sbinfo->policy_nodes);
+ return 0;
+}
+#endif /* CONFIG_TMPFS */
static void shmem_put_super(struct super_block *sb)
{
{
struct inode *inode;
struct dentry *root;
- int mode = S_IRWXUGO | S_ISVTX;
- uid_t uid = current->fsuid;
- gid_t gid = current->fsgid;
- int err = -ENOMEM;
struct shmem_sb_info *sbinfo;
- unsigned long blocks = 0;
- unsigned long inodes = 0;
- int policy = MPOL_DEFAULT;
- nodemask_t policy_nodes = node_states[N_HIGH_MEMORY];
+ int err = -ENOMEM;
+
+ /* Round up to L1_CACHE_BYTES to resist false sharing */
+ sbinfo = kmalloc(max((int)sizeof(struct shmem_sb_info),
+ L1_CACHE_BYTES), GFP_KERNEL);
+ if (!sbinfo)
+ return -ENOMEM;
+
+ sbinfo->max_blocks = 0;
+ sbinfo->max_inodes = 0;
+ sbinfo->mode = S_IRWXUGO | S_ISVTX;
+ sbinfo->uid = current->fsuid;
+ sbinfo->gid = current->fsgid;
+ sbinfo->policy = MPOL_DEFAULT;
+ sbinfo->policy_nodes = node_states[N_HIGH_MEMORY];
+ sb->s_fs_info = sbinfo;
#ifdef CONFIG_TMPFS
/*
* but the internal instance is left unlimited.
*/
if (!(sb->s_flags & MS_NOUSER)) {
- blocks = totalram_pages / 2;
- inodes = totalram_pages - totalhigh_pages;
- if (inodes > blocks)
- inodes = blocks;
- if (shmem_parse_options(data, &mode, &uid, &gid, &blocks,
- &inodes, &policy, &policy_nodes))
- return -EINVAL;
+ sbinfo->max_blocks = shmem_default_max_blocks();
+ sbinfo->max_inodes = shmem_default_max_inodes();
+ if (shmem_parse_options(data, sbinfo, false)) {
+ err = -EINVAL;
+ goto failed;
+ }
}
sb->s_export_op = &shmem_export_ops;
#else
sb->s_flags |= MS_NOUSER;
#endif
- /* Round up to L1_CACHE_BYTES to resist false sharing */
- sbinfo = kmalloc(max((int)sizeof(struct shmem_sb_info),
- L1_CACHE_BYTES), GFP_KERNEL);
- if (!sbinfo)
- return -ENOMEM;
-
spin_lock_init(&sbinfo->stat_lock);
- sbinfo->max_blocks = blocks;
- sbinfo->free_blocks = blocks;
- sbinfo->max_inodes = inodes;
- sbinfo->free_inodes = inodes;
- sbinfo->policy = policy;
- sbinfo->policy_nodes = policy_nodes;
+ sbinfo->free_blocks = sbinfo->max_blocks;
+ sbinfo->free_inodes = sbinfo->max_inodes;
- sb->s_fs_info = sbinfo;
sb->s_maxbytes = SHMEM_MAX_BYTES;
sb->s_blocksize = PAGE_CACHE_SIZE;
sb->s_blocksize_bits = PAGE_CACHE_SHIFT;
sb->s_flags |= MS_POSIXACL;
#endif
- inode = shmem_get_inode(sb, S_IFDIR | mode, 0);
+ inode = shmem_get_inode(sb, S_IFDIR | sbinfo->mode, 0);
if (!inode)
goto failed;
- inode->i_uid = uid;
- inode->i_gid = gid;
+ inode->i_uid = sbinfo->uid;
+ inode->i_gid = sbinfo->gid;
root = d_alloc_root(inode);
if (!root)
goto failed_iput;
#ifdef CONFIG_TMPFS
.statfs = shmem_statfs,
.remount_fs = shmem_remount_fs,
+ .show_options = shmem_show_options,
#endif
.delete_inode = shmem_delete_inode,
.drop_inode = generic_delete_inode,
}
-static int f(pte_t *pte, struct page *pmd_page, unsigned long addr, void *data)
+static int f(pte_t *pte, pgtable_t table, unsigned long addr, void *data)
{
/* apply_to_page_range() does all the hard work. */
return 0;
config NET_NS
bool "Network namespace support"
default n
- depends on EXPERIMENTAL && !SYSFS
+ depends on EXPERIMENTAL && !SYSFS && NAMESPACES
help
Allow user space to create what appear to be multiple instances
of the network stack.
{
struct sock *sk;
struct can_proto *cp;
- char module_name[sizeof("can-proto-000")];
int err = 0;
sock->state = SS_UNCONNECTED;
if (net != &init_net)
return -EAFNOSUPPORT;
+#ifdef CONFIG_KMOD
/* try to load protocol module, when CONFIG_KMOD is defined */
if (!proto_tab[protocol]) {
- sprintf(module_name, "can-proto-%d", protocol);
- err = request_module(module_name);
+ err = request_module("can-proto-%d", protocol);
/*
* In case of error we only print a message but don't
* return the error code immediately. Below we will
* return -EPROTONOSUPPORT
*/
- if (err == -ENOSYS) {
- if (printk_ratelimit())
- printk(KERN_INFO "can: request_module(%s)"
- " not implemented.\n", module_name);
- } else if (err) {
- if (printk_ratelimit())
- printk(KERN_ERR "can: request_module(%s)"
- " failed.\n", module_name);
- }
+ if (err && printk_ratelimit())
+ printk(KERN_ERR "can: request_module "
+ "(can-proto-%d) failed.\n", protocol);
}
+#endif
spin_lock(&proto_tab_lock);
cp = proto_tab[protocol];
return -EINVAL;
}
+ err = proto_register(cp->prot, 0);
+ if (err < 0)
+ return err;
+
spin_lock(&proto_tab_lock);
if (proto_tab[proto]) {
printk(KERN_ERR "can: protocol %d already registered\n",
proto);
err = -EBUSY;
- goto errout;
+ } else {
+ proto_tab[proto] = cp;
+
+ /* use generic ioctl function if not defined by module */
+ if (!cp->ops->ioctl)
+ cp->ops->ioctl = can_ioctl;
}
+ spin_unlock(&proto_tab_lock);
- err = proto_register(cp->prot, 0);
if (err < 0)
- goto errout;
-
- proto_tab[proto] = cp;
-
- /* use generic ioctl function if the module doesn't bring its own */
- if (!cp->ops->ioctl)
- cp->ops->ioctl = can_ioctl;
-
- errout:
- spin_unlock(&proto_tab_lock);
+ proto_unregister(cp->prot);
return err;
}
printk(KERN_ERR "BUG: can: protocol %d is not registered\n",
proto);
}
- proto_unregister(cp->prot);
proto_tab[proto] = NULL;
spin_unlock(&proto_tab_lock);
+
+ proto_unregister(cp->prot);
}
EXPORT_SYMBOL(can_proto_unregister);
struct sock *sk = (struct sock *)data;
struct raw_sock *ro = raw_sk(sk);
struct sockaddr_can *addr;
- int error;
if (!ro->recv_own_msgs) {
/* check the received tx sock reference */
addr->can_family = AF_CAN;
addr->can_ifindex = skb->dev->ifindex;
- error = sock_queue_rcv_skb(sk, skb);
- if (error < 0)
+ if (sock_queue_rcv_skb(sk, skb) < 0)
kfree_skb(skb);
}
static int raw_enable_filters(struct net_device *dev, struct sock *sk,
- struct can_filter *filter,
- int count)
+ struct can_filter *filter, int count)
{
int err = 0;
int i;
}
static void raw_disable_filters(struct net_device *dev, struct sock *sk,
- struct can_filter *filter,
- int count)
+ struct can_filter *filter, int count)
{
int i;
/* filters set by default/setsockopt */
err = raw_enable_allfilters(dev, sk);
dev_put(dev);
-
} else {
ifindex = 0;
if (err) {
if (count > 1)
kfree(filter);
-
goto out_fil;
}
{
struct sock *sk = sock->sk;
struct sk_buff *skb;
- int error = 0;
+ int err = 0;
int noblock;
noblock = flags & MSG_DONTWAIT;
flags &= ~MSG_DONTWAIT;
- skb = skb_recv_datagram(sk, flags, noblock, &error);
+ skb = skb_recv_datagram(sk, flags, noblock, &err);
if (!skb)
- return error;
+ return err;
if (size < skb->len)
msg->msg_flags |= MSG_TRUNC;
else
size = skb->len;
- error = memcpy_toiovec(msg->msg_iov, skb->data, size);
- if (error < 0) {
+ err = memcpy_toiovec(msg->msg_iov, skb->data, size);
+ if (err < 0) {
skb_free_datagram(sk, skb);
- return error;
+ return err;
}
sock_recv_timestamp(msg, sk, skb);
struct flow_cache_entry *next;
u16 family;
u8 dir;
- struct flowi key;
u32 genid;
+ struct flowi key;
void *object;
atomic_t *object_ref;
};
int hash_rnd_recalc;
u32 hash_rnd;
int count;
-} ____cacheline_aligned;
+};
static DEFINE_PER_CPU(struct flow_percpu_info, flow_hash_info) = { 0 };
#define flow_hash_rnd_recalc(cpu) \
flow_cachep = kmem_cache_create("flow_cache",
sizeof(struct flow_cache_entry),
- 0, SLAB_HWCACHE_ALIGN|SLAB_PANIC,
+ 0, SLAB_PANIC,
NULL);
flow_hash_shift = 10;
flow_lwm = 2 * flow_hash_size;
{
struct dn_route *chain;
spinlock_t lock;
-} __attribute__((__aligned__(8)));
+};
extern struct neigh_table dn_neigh_table;
spin_unlock_bh(&nf_nat_lock);
}
-static void nf_nat_move_storage(struct nf_conn *conntrack, void *old)
+static void nf_nat_move_storage(void *new, void *old)
{
- struct nf_conn_nat *new_nat = nf_ct_ext_find(conntrack, NF_CT_EXT_NAT);
- struct nf_conn_nat *old_nat = (struct nf_conn_nat *)old;
+ struct nf_conn_nat *new_nat = new;
+ struct nf_conn_nat *old_nat = old;
struct nf_conn *ct = old_nat->ct;
if (!ct || !(ct->status & IPS_NAT_DONE_MASK))
int iif = dev->ifindex;
struct net *net;
- net = skb->dev->nd_net;
+ net = dev->nd_net;
tos &= IPTOS_RT_MASK;
hash = rt_hash(daddr, saddr, iif);
/* Create path. */
iucv->path = iucv_path_alloc(IUCV_QUEUELEN_DEFAULT,
IPRMDATA, GFP_KERNEL);
+ if (!iucv->path) {
+ err = -ENOMEM;
+ goto done;
+ }
err = iucv_path_connect(iucv->path, &af_iucv_handler,
sa->siucv_user_id, NULL, user_data, sk);
if (err) {
save_message:
save_msg = kzalloc(sizeof(struct sock_msg_q), GFP_ATOMIC | GFP_DMA);
+ if (!save_msg)
+ return;
save_msg->path = path;
save_msg->msg = *msg;
struct iucv_message *msg)
{
struct sock *sk = path->private;
- struct sk_buff *this;
+ struct sk_buff *this = NULL;
struct sk_buff_head *list = &iucv_sk(sk)->send_skb_q;
struct sk_buff *list_skb = list->next;
unsigned long flags;
- if (list_skb) {
+ if (!skb_queue_empty(list)) {
spin_lock_irqsave(&list->lock, flags);
- do {
- this = list_skb;
+ while (list_skb != (struct sk_buff *)list) {
+ if (!memcmp(&msg->tag, list_skb->cb, 4)) {
+ this = list_skb;
+ break;
+ }
list_skb = list_skb->next;
- } while (memcmp(&msg->tag, this->cb, 4) && list_skb);
+ }
+ if (this)
+ __skb_unlink(this, list);
spin_unlock_irqrestore(&list->lock, flags);
- skb_unlink(this, &iucv_sk(sk)->send_skb_q);
- kfree_skb(this);
+ if (this)
+ kfree_skb(this);
}
+ if (!this)
+ printk(KERN_ERR "AF_IUCV msg tag %u not found\n", msg->tag);
if (sk->sk_state == IUCV_CLOSING) {
if (skb_queue_empty(&iucv_sk(sk)->send_skb_q)) {
iucv_setmask_up();
INIT_LIST_HEAD(&handler->paths);
- spin_lock_irq(&iucv_table_lock);
+ spin_lock_bh(&iucv_table_lock);
list_add_tail(&handler->list, &iucv_handler_list);
- spin_unlock_irq(&iucv_table_lock);
+ spin_unlock_bh(&iucv_table_lock);
rc = 0;
out_mutex:
mutex_unlock(&iucv_register_mutex);
rcu_read_lock();
t = rcu_dereference(nf_ct_ext_types[i]);
if (t && t->move)
- t->move(ct, ct->ext + ct->ext->offset[i]);
+ t->move((void *)new + new->offset[i],
+ (void *)ct->ext + ct->ext->offset[i]);
rcu_read_unlock();
}
kfree(ct->ext);
* CLOSE_WAIT: ACK seen (after FIN)
* LAST_ACK: FIN seen (after FIN)
* TIME_WAIT: last ACK seen
- * CLOSE: closed connection
+ * CLOSE: closed connection (RST)
*
* LISTEN state is not used.
*
case TCP_CONNTRACK_SYN_SENT:
if (old_state < TCP_CONNTRACK_TIME_WAIT)
break;
- if ((ct->proto.tcp.seen[!dir].flags & IP_CT_TCP_FLAG_CLOSE_INIT)
+ /* RFC 1122: "When a connection is closed actively,
+ * it MUST linger in TIME-WAIT state for a time 2xMSL
+ * (Maximum Segment Lifetime). However, it MAY accept
+ * a new SYN from the remote TCP to reopen the connection
+ * directly from TIME-WAIT state, if..."
+ * We ignore the conditions because we are in the
+ * TIME-WAIT state anyway.
+ *
+ * Handle aborted connections: we and the server
+ * think there is an existing connection but the client
+ * aborts it and starts a new one.
+ */
+ if (((ct->proto.tcp.seen[dir].flags
+ | ct->proto.tcp.seen[!dir].flags)
+ & IP_CT_TCP_FLAG_CLOSE_INIT)
|| (ct->proto.tcp.last_dir == dir
&& ct->proto.tcp.last_index == TCP_RST_SET)) {
/* Attempt to reopen a closed/aborted connection.
/* Fall through */
case TCP_CONNTRACK_IGNORE:
/* Ignored packets:
+ *
+ * Our connection entry may be out of sync, so ignore
+ * packets which may signal the real connection between
+ * the client and the server.
*
* a) SYN in ORIGINAL
* b) SYN/ACK in REPLY
* c) ACK in reply direction after initial SYN in original.
+ *
+ * If the ignored packet is invalid, the receiver will send
+ * a RST we'll catch below.
*/
if (index == TCP_SYNACK_SET
&& ct->proto.tcp.last_index == TCP_SYN_SET
&& ct->proto.tcp.last_dir != dir
&& ntohl(th->ack_seq) == ct->proto.tcp.last_end) {
- /* This SYN/ACK acknowledges a SYN that we earlier
+ /* b) This SYN/ACK acknowledges a SYN that we earlier
* ignored as invalid. This means that the client and
* the server are both in sync, while the firewall is
* not. We kill this session and block the SYN/ACK so
write_unlock_bh(&tcp_lock);
if (LOG_INVALID(IPPROTO_TCP))
nf_log_packet(pf, 0, skb, NULL, NULL, NULL,
- "nf_ct_tcp: invalid packed ignored ");
+ "nf_ct_tcp: invalid packet ignored ");
return NF_ACCEPT;
case TCP_CONNTRACK_MAX:
/* Invalid packet */
ct->proto.tcp.state = new_state;
if (old_state != new_state
- && (new_state == TCP_CONNTRACK_FIN_WAIT
- || new_state == TCP_CONNTRACK_CLOSE))
+ && new_state == TCP_CONNTRACK_CLOSE)
ct->proto.tcp.seen[dir].flags |= IP_CT_TCP_FLAG_CLOSE_INIT;
timeout = ct->proto.tcp.retrans >= nf_ct_tcp_max_retrans
&& tcp_timeouts[new_state] > nf_ct_tcp_timeout_max_retrans
#include <linux/ip.h>
#include <linux/ipv6.h>
#include <linux/netfilter/x_tables.h>
+#include <linux/netfilter/xt_iprange.h>
#include <linux/netfilter_ipv4/ipt_iprange.h>
static bool
{
.name = "iprange",
.revision = 1,
- .family = AF_INET6,
+ .family = AF_INET,
.match = iprange_mt4,
.matchsize = sizeof(struct xt_iprange_mtinfo),
.me = THIS_MODULE,
static inline void meta_delete(struct meta_match *meta)
{
- struct meta_type_ops *ops = meta_type_ops(&meta->lvalue);
+ if (meta) {
+ struct meta_type_ops *ops = meta_type_ops(&meta->lvalue);
- if (ops && ops->destroy) {
- ops->destroy(&meta->lvalue);
- ops->destroy(&meta->rvalue);
+ if (ops && ops->destroy) {
+ ops->destroy(&meta->lvalue);
+ ops->destroy(&meta->rvalue);
+ }
}
kfree(meta);
return !((addr ^ tipc_own_addr) >> 12);
}
-static inline int in_own_zone(u32 addr)
-{
- return !((addr ^ tipc_own_addr) >> 24);
-}
-
static inline int is_slave(u32 addr)
{
return addr & 0x800;
extern char tipc_bclink_name[];
-/**
- * nmap_get - determine if node exists in a node map
- */
-
-static inline int tipc_nmap_get(struct node_map *nm_ptr, u32 node)
-{
- int n = tipc_node(node);
- int w = n / WSIZE;
- int b = n % WSIZE;
-
- return nm_ptr->map[w] & (1 << b);
-}
-
/**
* nmap_add - add a node to a node map
*/
msg_set_word(m, msg_hdr_sz(m)/4, a);
}
-static inline int msg_dataoctet(struct tipc_msg *m, u32 pos)
-{
- return(msg_data(m)[pos + 4] != 0);
-}
-
static inline void msg_set_dataoctet(struct tipc_msg *m, u32 pos)
{
msg_data(m)[pos + 4] = 1;
static u32 dispatch(struct tipc_port *tport, struct sk_buff *buf);
static void wakeupdispatch(struct tipc_port *tport);
-static struct proto_ops packet_ops;
-static struct proto_ops stream_ops;
-static struct proto_ops msg_ops;
+static const struct proto_ops packet_ops;
+static const struct proto_ops stream_ops;
+static const struct proto_ops msg_ops;
static struct proto tipc_proto;
* Protocol switches for the various types of TIPC sockets
*/
-static struct proto_ops msg_ops = {
+static const struct proto_ops msg_ops = {
.owner = THIS_MODULE,
.family = AF_TIPC,
.release = release,
.sendpage = sock_no_sendpage
};
-static struct proto_ops packet_ops = {
+static const struct proto_ops packet_ops = {
.owner = THIS_MODULE,
.family = AF_TIPC,
.release = release,
.sendpage = sock_no_sendpage
};
-static struct proto_ops stream_ops = {
+static const struct proto_ops stream_ops = {
.owner = THIS_MODULE,
.family = AF_TIPC,
.release = release,
.sendpage = sock_no_sendpage
};
-static struct net_proto_family tipc_family_ops = {
+static const struct net_proto_family tipc_family_ops = {
.owner = THIS_MODULE,
.family = AF_TIPC,
.create = tipc_create
.sadb_alg_maxbits = 256
}
},
+{
+ .name = "rfc3686(ctr(aes))",
+
+ .uinfo = {
+ .encr = {
+ .blockbits = 128,
+ .defkeybits = 160, /* 128-bit key + 32-bit nonce */
+ }
+ },
+
+ .desc = {
+ .sadb_alg_id = SADB_X_EALG_AESCTR,
+ .sadb_alg_ivlen = 8,
+ .sadb_alg_minbits = 128,
+ .sadb_alg_maxbits = 256
+ }
+},
};
static struct xfrm_algo_desc calg_list[] = {
my $P = $0;
$P =~ s@.*/@@g;
-my $V = '0.12';
+my $V = '0.14';
use Getopt::Long qw(:config no_auto_abbrev);
my $check = 0;
my $summary = 1;
my $mailback = 0;
+my $summary_file = 0;
my $root;
+my %debug;
GetOptions(
'q|quiet+' => \$quiet,
'tree!' => \$tree,
'signoff!' => \$chk_signoff,
'patch!' => \$chk_patch,
- 'test-type!' => \$tst_type,
'emacs!' => \$emacs,
'terse!' => \$terse,
'file!' => \$file,
'root=s' => \$root,
'summary!' => \$summary,
'mailback!' => \$mailback,
+ 'summary-file!' => \$summary_file,
+
+ 'debug=s' => \%debug,
+ 'test-type!' => \$tst_type,
) or exit;
my $exit = 0;
if ($#ARGV < 0) {
print "usage: $P [options] patchfile\n";
print "version: $V\n";
- print "options: -q => quiet\n";
- print " --no-tree => run without a kernel tree\n";
- print " --terse => one line per report\n";
- print " --emacs => emacs compile window format\n";
- print " --file => check a source file\n";
- print " --strict => enable more subjective tests\n";
- print " --root => path to the kernel tree root\n";
+ print "options: -q => quiet\n";
+ print " --no-tree => run without a kernel tree\n";
+ print " --terse => one line per report\n";
+ print " --emacs => emacs compile window format\n";
+ print " --file => check a source file\n";
+ print " --strict => enable more subjective tests\n";
+ print " --root => path to the kernel tree root\n";
+ print " --no-summary => suppress the per-file summary\n";
+ print " --summary-file => include the filename in summary\n";
exit(1);
}
+my $dbg_values = 0;
+my $dbg_possible = 0;
+for my $key (keys %debug) {
+ eval "\${dbg_$key} = '$debug{$key}';"
+}
+
if ($terse) {
$emacs = 1;
$quiet++;
our $Operators = qr{
<=|>=|==|!=|
=>|->|<<|>>|<|>|!|~|
- &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/
+ &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%
}x;
our $NonptrType;
$Type = qr{
\b$NonptrType\b
(?:\s*\*+\s*const|\s*\*+|(?:\s*\[\s*\])+)?
- (?:\s+$Sparse|\s+$Attribute)*
+ (?:\s+$Inline|\s+$Sparse|\s+$Attribute)*
}x;
$Declare = qr{(?:$Storage\s+)?$Type};
}
}
my @rawlines = ();
+my @lines = ();
+my $vname;
for my $filename (@ARGV) {
if ($file) {
open(FILE, "diff -u /dev/null $filename|") ||
open(FILE, "<$filename") ||
die "$P: $filename: open failed - $!\n";
}
+ if ($filename eq '-') {
+ $vname = 'Your patch';
+ } else {
+ $vname = $filename;
+ }
while (<FILE>) {
chomp;
push(@rawlines, $_);
}
close(FILE);
- if (!process($filename, @rawlines)) {
+ if (!process($filename)) {
$exit = 1;
}
@rawlines = ();
+ @lines = ();
}
exit($exit);
my $l = '';
my $quote = '';
+ my $qlen = 0;
foreach my $c (split(//, $line)) {
+ # The second backslash of a pair is not a "quote".
+ if ($l eq "\\" && $c eq "\\") {
+ $c = 'X';
+ }
if ($l ne "\\" && ($c eq "'" || $c eq '"')) {
if ($quote eq '') {
$quote = $c;
$res .= $c;
$l = $c;
+ $qlen = 0;
next;
} elsif ($quote eq $c) {
$quote = '';
}
}
+ if ($quote eq "'" && $qlen > 1) {
+ $quote = '';
+ }
if ($quote && $c ne "\t") {
$res .= "X";
+ $qlen++;
} else {
$res .= $c;
}
$l = $c;
}
+ # Clear out the comments.
+ while ($res =~ m@(/\*.*?\*/)@g) {
+ substr($res, $-[1], $+[1] - $-[1]) = $; x ($+[1] - $-[1]);
+ }
+ if ($res =~ m@(/\*.*)@) {
+ substr($res, $-[1], $+[1] - $-[1]) = $; x ($+[1] - $-[1]);
+ }
+ if ($res =~ m@^.(.*\*/)@) {
+ substr($res, $-[1], $+[1] - $-[1]) = $; x ($+[1] - $-[1]);
+ }
+
+ # The pathname on a #include may be surrounded by '<' and '>'.
+ if ($res =~ /^.#\s*include\s+\<(.*)\>/) {
+ my $clean = 'X' x length($1);
+ $res =~ s@\<.*\>@<$clean>@;
+
+ # The whole of a #error is a string.
+ } elsif ($res =~ /^.#\s*(?:error|warning)\s+(.*)\b/) {
+ my $clean = 'X' x length($1);
+ $res =~ s@(#\s*(?:error|warning)\s+).*@$1$clean@;
+ }
+
return $res;
}
my $soff = $off;
my $coff = $off - 1;
+ my $loff = 0;
+
my $type = '';
my $level = 0;
my $c;
my $len = 0;
+
+ my $remainder;
while (1) {
#warn "CSB: blk<$blk>\n";
# If we are about to drop off the end, pull in more
# context.
if ($off >= $len) {
for (; $remain > 0; $line++) {
- next if ($rawlines[$line] =~ /^-/);
+ next if ($lines[$line] =~ /^-/);
$remain--;
- $blk .= sanitise_line($rawlines[$line]) . "\n";
+ $loff = $len;
+ $blk .= $lines[$line] . "\n";
$len = length($blk);
$line++;
last;
}
# Bail if there is no further context.
#warn "CSB: blk<$blk> off<$off> len<$len>\n";
- if ($off == $len) {
+ if ($off >= $len) {
last;
}
}
$c = substr($blk, $off, 1);
+ $remainder = substr($blk, $off);
#warn "CSB: c<$c> type<$type> level<$level>\n";
# Statement ends at the ';' or a close '}' at the
last;
}
+ # An else is really a conditional as long as its not else if
+ if ($level == 0 && $remainder =~ /(\s+else)(?:\s|{)/ &&
+ $remainder !~ /\s+else\s+if\b/) {
+ $coff = $off + length($1);
+ }
+
if (($type eq '' || $type eq '(') && $c eq '(') {
$level++;
$type = '(';
}
$off++;
}
+ if ($off == $len) {
+ $line++;
+ $remain--;
+ }
my $statement = substr($blk, $soff, $off - $soff + 1);
my $condition = substr($blk, $soff, $coff - $soff + 1);
#warn "STATEMENT<$statement>\n";
#warn "CONDITION<$condition>\n";
- return ($statement, $condition);
+ #print "off<$off> loff<$loff>\n";
+
+ return ($statement, $condition,
+ $line, $remain + 1, $off - $loff + 1, $level);
+}
+
+sub ctx_statement_full {
+ my ($linenr, $remain, $off) = @_;
+ my ($statement, $condition, $level);
+
+ my (@chunks);
+
+ ($statement, $condition, $linenr, $remain, $off, $level) =
+ ctx_statement_block($linenr, $remain, $off);
+ #print "F: c<$condition> s<$statement>\n";
+ for (;;) {
+ push(@chunks, [ $condition, $statement ]);
+ last if (!($remain > 0 && $condition =~ /^.\s*(?:if|else|do)/));
+ ($statement, $condition, $linenr, $remain, $off, $level) =
+ ctx_statement_block($linenr, $remain, $off);
+ #print "C: c<$condition> s<$statement>\n";
+ }
+
+ return ($level, $linenr, @chunks);
}
sub ctx_block_get {
return $res;
}
+my $av_preprocessor = 0;
+my $av_paren = 0;
+my @av_paren_type;
+
+sub annotate_reset {
+ $av_preprocessor = 0;
+ $av_paren = 0;
+ @av_paren_type = ();
+}
+
sub annotate_values {
my ($stream, $type) = @_;
my $res;
my $cur = $stream;
- my $debug = 0;
-
- print "$stream\n" if ($debug);
-
- ##my $type = 'N';
- my $pos = 0;
- my $preprocessor = 0;
- my $paren = 0;
- my @paren_type;
+ print "$stream\n" if ($dbg_values > 1);
while (length($cur)) {
- print " <$type> " if ($debug);
+ print " <$type> " if ($dbg_values > 1);
if ($cur =~ /^(\s+)/o) {
- print "WS($1)\n" if ($debug);
- if ($1 =~ /\n/ && $preprocessor) {
- $preprocessor = 0;
+ print "WS($1)\n" if ($dbg_values > 1);
+ if ($1 =~ /\n/ && $av_preprocessor) {
+ $av_preprocessor = 0;
$type = 'N';
}
} elsif ($cur =~ /^($Type)/) {
- print "DECLARE($1)\n" if ($debug);
+ print "DECLARE($1)\n" if ($dbg_values > 1);
$type = 'T';
} elsif ($cur =~ /^(#\s*define\s*$Ident)(\(?)/o) {
- print "DEFINE($1)\n" if ($debug);
- $preprocessor = 1;
- $paren_type[$paren] = 'N';
+ print "DEFINE($1)\n" if ($dbg_values > 1);
+ $av_preprocessor = 1;
+ $av_paren_type[$av_paren] = 'N';
- } elsif ($cur =~ /^(#\s*(?:ifdef|ifndef|if|else|endif))/o) {
- print "PRE($1)\n" if ($debug);
- $preprocessor = 1;
+ } elsif ($cur =~ /^(#\s*(?:ifdef|ifndef|if|else|elif|endif))/o) {
+ print "PRE($1)\n" if ($dbg_values > 1);
+ $av_preprocessor = 1;
$type = 'N';
} elsif ($cur =~ /^(\\\n)/o) {
- print "PRECONT($1)\n" if ($debug);
+ print "PRECONT($1)\n" if ($dbg_values > 1);
} elsif ($cur =~ /^(sizeof)\s*(\()?/o) {
- print "SIZEOF($1)\n" if ($debug);
+ print "SIZEOF($1)\n" if ($dbg_values > 1);
if (defined $2) {
- $paren_type[$paren] = 'V';
+ $av_paren_type[$av_paren] = 'V';
}
$type = 'N';
- } elsif ($cur =~ /^(if|while|typeof|for)\b/o) {
- print "COND($1)\n" if ($debug);
- $paren_type[$paren] = 'N';
+ } elsif ($cur =~ /^(if|while|typeof|__typeof__|for)\b/o) {
+ print "COND($1)\n" if ($dbg_values > 1);
+ $av_paren_type[$av_paren] = 'N';
$type = 'N';
} elsif ($cur =~/^(return|case|else)/o) {
- print "KEYWORD($1)\n" if ($debug);
+ print "KEYWORD($1)\n" if ($dbg_values > 1);
$type = 'N';
} elsif ($cur =~ /^(\()/o) {
- print "PAREN('$1')\n" if ($debug);
- $paren++;
+ print "PAREN('$1')\n" if ($dbg_values > 1);
+ $av_paren++;
$type = 'N';
} elsif ($cur =~ /^(\))/o) {
- $paren-- if ($paren > 0);
- if (defined $paren_type[$paren]) {
- $type = $paren_type[$paren];
- undef $paren_type[$paren];
- print "PAREN('$1') -> $type\n" if ($debug);
+ $av_paren-- if ($av_paren > 0);
+ if (defined $av_paren_type[$av_paren]) {
+ $type = $av_paren_type[$av_paren];
+ undef $av_paren_type[$av_paren];
+ print "PAREN('$1') -> $type\n"
+ if ($dbg_values > 1);
} else {
- print "PAREN('$1')\n" if ($debug);
+ print "PAREN('$1')\n" if ($dbg_values > 1);
}
} elsif ($cur =~ /^($Ident)\(/o) {
- print "FUNC($1)\n" if ($debug);
- $paren_type[$paren] = 'V';
+ print "FUNC($1)\n" if ($dbg_values > 1);
+ $av_paren_type[$av_paren] = 'V';
} elsif ($cur =~ /^($Ident|$Constant)/o) {
- print "IDENT($1)\n" if ($debug);
+ print "IDENT($1)\n" if ($dbg_values > 1);
$type = 'V';
} elsif ($cur =~ /^($Assignment)/o) {
- print "ASSIGN($1)\n" if ($debug);
+ print "ASSIGN($1)\n" if ($dbg_values > 1);
$type = 'N';
+ } elsif ($cur =~/^(;)/) {
+ print "END($1)\n" if ($dbg_values > 1);
+ $type = 'E';
+
} elsif ($cur =~ /^(;|{|}|\?|:|\[)/o) {
- print "END($1)\n" if ($debug);
+ print "CLOSE($1)\n" if ($dbg_values > 1);
$type = 'N';
} elsif ($cur =~ /^($Operators)/o) {
- print "OP($1)\n" if ($debug);
+ print "OP($1)\n" if ($dbg_values > 1);
if ($1 ne '++' && $1 ne '--') {
$type = 'N';
}
} elsif ($cur =~ /(^.)/o) {
- print "C($1)\n" if ($debug);
+ print "C($1)\n" if ($dbg_values > 1);
}
if (defined $1) {
$cur = substr($cur, length($1));
}
sub possible {
- my ($possible) = @_;
+ my ($possible, $line) = @_;
#print "CHECK<$possible>\n";
if ($possible !~ /^(?:$Storage|$Type|DEFINE_\S+)$/ &&
$possible ne 'struct' && $possible ne 'enum' &&
$possible ne 'case' && $possible ne 'else' &&
$possible ne 'typedef') {
- #print "POSSIBLE<$possible>\n";
+ warn "POSSIBLE: $possible ($line)\n" if ($dbg_possible);
push(@typeList, $possible);
build_types();
}
my $prefix = '';
-my @report = ();
sub report {
my $line = $prefix . $_[0];
$line = (split('\n', $line))[0] . "\n" if ($terse);
- push(@report, $line);
+ push(our @report, $line);
}
sub report_dump {
- @report;
+ our @report;
}
sub ERROR {
report("ERROR: $_[0]\n");
sub process {
my $filename = shift;
- my @lines = @_;
my $linenr=0;
my $prevline="";
+ my $prevrawline="";
my $stashline="";
+ my $stashrawline="";
my $length;
my $indent;
my $signoff = 0;
my $is_patch = 0;
+ our @report = ();
our $cnt_lines = 0;
our $cnt_error = 0;
our $cnt_warn = 0;
my $realcnt = 0;
my $here = '';
my $in_comment = 0;
+ my $comment_edge = 0;
my $first_line = 0;
- my $prev_values = 'N';
+ my $prev_values = 'E';
+
+ # suppression flags
+ my $suppress_ifbraces = 0;
+ # Pre-scan the patch sanitizing the lines.
# Pre-scan the patch looking for any __setup documentation.
+ #
my @setup_docs = ();
my $setup_docs = 0;
- foreach my $line (@lines) {
+ my $line;
+ foreach my $rawline (@rawlines) {
+ # Standardise the strings and chars within the input to
+ # simplify matching.
+ $line = sanitise_line($rawline);
+ push(@lines, $line);
+
+ ##print "==>$rawline\n";
+ ##print "-->$line\n";
+
if ($line=~/^\+\+\+\s+(\S+)/) {
$setup_docs = 0;
if ($1 =~ m@Documentation/kernel-parameters.txt$@) {
foreach my $line (@lines) {
$linenr++;
- my $rawline = $line;
-
+ my $rawline = $rawlines[$linenr - 1];
#extract the filename as it passes
if ($line=~/^\+\+\+\s+(\S+)/) {
} else {
$realcnt=1+1;
}
- $prev_values = 'N';
+ annotate_reset();
+ $prev_values = 'E';
+
+ $suppress_ifbraces = $linenr - 1;
next;
}
if ($linenr == $first_line) {
my $edge;
for (my $ln = $first_line; $ln < ($linenr + $realcnt); $ln++) {
- ($edge) = ($lines[$ln - 1] =~ m@(/\*|\*/)@);
+ ($edge) = ($rawlines[$ln - 1] =~ m@(/\*|\*/)@);
last if (defined $edge);
}
if (defined $edge && $edge eq '*/') {
# Guestimate if this is a continuing comment. If this
# is the start of a diff block and this line starts
# ' *' then it is very likely a comment.
- if ($linenr == $first_line and $line =~ m@^.\s*\*@) {
+ if ($linenr == $first_line and $rawline =~ m@^.\s* \*(?:\s|$)@) {
$in_comment = 1;
}
# Find the last comment edge on _this_ line.
- while (($line =~ m@(/\*|\*/)@g)) {
+ $comment_edge = 0;
+ while (($rawline =~ m@(/\*|\*/)@g)) {
if ($1 eq '/*') {
$in_comment = 1;
} else {
$in_comment = 0;
}
+ $comment_edge = 1;
}
# Measure the line length and indent.
- ($length, $indent) = line_stats($line);
+ ($length, $indent) = line_stats($rawline);
# Track the previous line.
($prevline, $stashline) = ($stashline, $line);
($previndent, $stashindent) = ($stashindent, $indent);
+ ($prevrawline, $stashrawline) = ($stashrawline, $rawline);
+
+ #warn "ic<$in_comment> ce<$comment_edge> line<$line>\n";
} elsif ($realcnt == 1) {
$realcnt--;
$here = "#$realline: " if ($file);
$here .= "FILE: $realfile:$realline:" if ($realcnt != 0);
- my $hereline = "$here\n$line\n";
- my $herecurr = "$here\n$line\n";
- my $hereprev = "$here\n$prevline\n$line\n";
+ my $hereline = "$here\n$rawline\n";
+ my $herecurr = "$here\n$rawline\n";
+ my $hereprev = "$here\n$prevrawline\n$rawline\n";
$prefix = "$filename:$realline: " if ($emacs && $file);
$prefix = "$filename:$linenr: " if ($emacs && !$file);
# UTF-8 regex found at http://www.w3.org/International/questions/qa-forms-utf-8.en.php
if (($realfile =~ /^$/ || $line =~ /^\+/) &&
- !($line =~ m/^(
+ !($rawline =~ m/^(
[\x09\x0A\x0D\x20-\x7E] # ASCII
| [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte
| \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs
| [\xF1-\xF3][\x80-\xBF]{3} # planes 4-15
| \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16
)*$/x )) {
- ERROR("Invalid UTF-8\n" . $herecurr);
+ ERROR("Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $herecurr);
}
#ignore lines being removed
#trailing whitespace
if ($line =~ /^\+.*\015/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
+ my $herevet = "$here\n" . cat_vet($rawline) . "\n";
ERROR("DOS line endings\n" . $herevet);
- } elsif ($line =~ /^\+.*\S\s+$/ || $line =~ /^\+\s+$/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
+ } elsif ($rawline =~ /^\+.*\S\s+$/ || $rawline =~ /^\+\s+$/) {
+ my $herevet = "$here\n" . cat_vet($rawline) . "\n";
ERROR("trailing whitespace\n" . $herevet);
}
#80 column limit
- if ($line =~ /^\+/ && !($prevline=~/\/\*\*/) && $length > 80) {
+ if ($line =~ /^\+/ && !($prevrawline=~/\/\*\*/) && $length > 80) {
WARN("line over 80 characters\n" . $herecurr);
}
# at the beginning of a line any tabs must come first and anything
# more than 8 must use tabs.
- if ($line=~/^\+\s* \t\s*\S/ or $line=~/^\+\s* \s*/) {
- my $herevet = "$here\n" . cat_vet($line) . "\n";
+ if ($rawline =~ /^\+\s* \t\s*\S/ ||
+ $rawline =~ /^\+\s* \s*/) {
+ my $herevet = "$here\n" . cat_vet($rawline) . "\n";
ERROR("use tabs not spaces\n" . $herevet);
}
-# Remove comments from the line before processing.
- my $comment_edge = ($line =~ s@/\*.*\*/@@g) +
- ($line =~ s@/\*.*@@) +
- ($line =~ s@^(.).*\*/@$1@);
+# check for RCS/CVS revision markers
+ if ($rawline =~ /\$(Revision|Log|Id)(?:\$|)/) {
+ WARN("CVS style keyword markers, these will _not_ be updated\n". $herecurr);
+ }
# The rest of our checks refer specifically to C style
# only apply those _outside_ comments. Only skip
# lines in the middle of comments.
next if (!$comment_edge && $in_comment);
-# Standardise the strings and chars within the input to simplify matching.
- $line = sanitise_line($line);
-
# Check for potential 'bare' types
- if ($realcnt &&
- $line !~ /$Ident:\s*$/ &&
- ($line =~ /^.\s*$Ident\s*\(\*+\s*$Ident\)\s*\(/ ||
- $line !~ /^.\s*$Ident\s*\(/)) {
+ if ($realcnt) {
+ # Ignore goto labels.
+ if ($line =~ /$Ident:\*$/) {
+
+ # Ignore functions being called
+ } elsif ($line =~ /^.\s*$Ident\s*\(/) {
+
# definitions in global scope can only start with types
- if ($line =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b/) {
- possible($1);
+ } elsif ($line =~ /^.(?:$Storage\s+)?(?:$Inline\s+)?(?:const\s+)?($Ident)\b/) {
+ possible($1, $line);
# declarations always start with types
- } elsif ($prev_values eq 'N' && $line =~ /^.\s*(?:$Storage\s+)?($Ident)\b\s*\**\s*$Ident\s*(?:;|=)/) {
+ } elsif ($prev_values eq 'E' && $line =~ /^.\s*(?:$Storage\s+)?(?:const\s+)?($Ident)\b(:?\s+$Sparse)?\s*\**\s*$Ident\s*(?:;|=|,)/) {
possible($1);
+ }
# any (foo ... *) is a pointer cast, and foo is a type
- } elsif ($line =~ /\(($Ident)(?:\s+$Sparse)*\s*\*+\s*\)/) {
- possible($1);
+ while ($line =~ /\(($Ident)(?:\s+$Sparse)*\s*\*+\s*\)/g) {
+ possible($1, $line);
}
# Check for any sort of function declaration.
# int foo(something bar, other baz);
# void (*store_gdt)(x86_descr_ptr *);
- if ($prev_values eq 'N' && $line =~ /^(.(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/) {
+ if ($prev_values eq 'E' && $line =~ /^(.(?:typedef\s*)?(?:(?:$Storage|$Inline)\s*)*\s*$Type\s*(?:\b$Ident|\(\*\s*$Ident\))\s*)\(/) {
my ($name_len) = length($1);
my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, $name_len);
my $ctx = join("\n", @ctx);
for my $arg (split(/\s*,\s*/, $ctx)) {
if ($arg =~ /^(?:const\s+)?($Ident)(?:\s+$Sparse)*\s*\**\s*(:?\b$Ident)?$/ || $arg =~ /^($Ident)$/) {
- possible($1);
+ possible($1, $line);
}
}
}
my $opline = $line; $opline =~ s/^./ /;
my $curr_values = annotate_values($opline . "\n", $prev_values);
$curr_values = $prev_values . $curr_values;
- #warn "--> $opline\n";
- #warn "--> $curr_values ($prev_values)\n";
+ if ($dbg_values) {
+ my $outline = $opline; $outline =~ s/\t/ /g;
+ warn "--> .$outline\n";
+ warn "--> $curr_values\n";
+ }
$prev_values = substr($curr_values, -1);
#ignore lines not being added
ERROR("malformed #include filename\n" .
$herecurr);
}
- # Sanitise this special form of string.
- $path = 'X' x length($path);
- $line =~ s{\<.*\>}{<$path>};
}
# no C99 // comments
# }
if ($line =~ /\bLINUX_VERSION_CODE\b/) {
- WARN("LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged" . $herecurr);
+ WARN("LINUX_VERSION_CODE should be avoided, code should be for the version to which it is merged\n" . $herecurr);
}
# printk should use KERN_* levels. Note that follow on printk's on the
# function brace can't be on same line, except for #defines of do while,
# or if closed on same line
- if (($line=~/$Type\s*[A-Za-z\d_]+\(.*\).* {/) and
+ if (($line=~/$Type\s*[A-Za-z\d_]+\(.*\).*\s{/) and
!($line=~/\#define.*do\s{/) and !($line=~/}/)) {
ERROR("open brace '{' following function declarations go on the next line\n" . $herecurr);
}
# check for spaces between functions and their parentheses.
while ($line =~ /($Ident)\s+\(/g) {
- if ($1 !~ /^(?:if|for|while|switch|return|volatile|__volatile__|__attribute__|format|__extension__|Copyright|case)$/ &&
- $line !~ /$Type\s+\(/ && $line !~ /^.\#\s*define\b/) {
+ my $name = $1;
+ my $ctx = substr($line, 0, $-[1]);
+
+ # Ignore those directives where spaces _are_ permitted.
+ if ($name =~ /^(?:if|for|while|switch|return|volatile|__volatile__|__attribute__|format|__extension__|Copyright|case|__asm__)$/) {
+
+ # cpp #define statements have non-optional spaces, ie
+ # if there is a space between the name and the open
+ # parenthesis it is simply not a parameter group.
+ } elsif ($ctx =~ /^.\#\s*define\s*$/) {
+
+ # If this whole things ends with a type its most
+ # likely a typedef for a function.
+ } elsif ("$ctx$name" =~ /$Type$/) {
+
+ } else {
WARN("no space between function name and open parenthesis '('\n" . $herecurr);
}
}
<<=|>>=|<=|>=|==|!=|
\+=|-=|\*=|\/=|%=|\^=|\|=|&=|
=>|->|<<|>>|<|>|=|!|~|
- &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/
+ &&|\|\||,|\^|\+\+|--|&|\||\+|-|\*|\/|%
}x;
- my @elements = split(/($ops|;)/, $opline);
+ my @elements = split(/($;+|$ops|;)/, $opline);
my $off = 0;
my $blank = copy_spacing($opline);
# print "UNARY: <$op_left$op_type $is_unary $a:$op:$c> <$ca:$op:$cc> <$unary_ctx>\n";
#}
+ # Ignore operators passed as parameters.
+ if ($op_type ne 'V' &&
+ $ca =~ /\s$/ && $cc =~ /^\s*,/) {
+
+ # Ignore comments
+ } elsif ($op =~ /^$;+$/) {
+
# ; should have either the end of line or a space or \ after it
- if ($op eq ';') {
+ } elsif ($op eq ';') {
if ($ctx !~ /.x[WEB]/ && $cc !~ /^\\/ &&
$cc !~ /^;/) {
ERROR("need space after that '$op' $at\n" . $hereptr);
if ($ctx !~ /[WOB]x[^W]/ && $ctx !~ /[^W]x[WOBE]/) {
ERROR("need space one side of that '$op' $at\n" . $hereptr);
}
- if ($ctx =~ /Wx./ && $cc =~ /^;/) {
+ if ($ctx =~ /WxB/ || ($ctx =~ /Wx./ && $cc =~ /^;/)) {
ERROR("no space before that '$op' $at\n" . $hereptr);
}
} elsif ($op eq '<<' or $op eq '>>' or
$op eq '&' or $op eq '^' or $op eq '|' or
$op eq '+' or $op eq '-' or
- $op eq '*' or $op eq '/')
+ $op eq '*' or $op eq '/' or
+ $op eq '%')
{
if ($ctx !~ /VxV|WxW|VxE|WxE|VxO/) {
ERROR("need consistent spacing around '$op' $at\n" .
$line !~ /for\s*\(\s+;/) {
ERROR("no space after that open parenthesis '('\n" . $herecurr);
}
- if ($line =~ /\s\)/ && $line !~ /^.\s*\)/ &&
+ if ($line =~ /(\s+)\)/ && $line !~ /^.\s*\)/ &&
$line !~ /for\s*\(.*;\s+\)/) {
ERROR("no space before that close parenthesis ')'\n" . $herecurr);
}
my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0);
if ($c =~ /\bif\s*\(.*[^<>!=]=[^=].*/) {
- ERROR("do not use assignment in if condition ($c)\n" . $herecurr);
+ ERROR("do not use assignment in if condition\n" . $herecurr);
}
# Find out what is on the end of the line after the
# conditional.
substr($s, 0, length($c)) = '';
$s =~ s/\n.*//g;
-
- if (length($c) && $s !~ /^\s*({|;|\/\*.*\*\/)?\s*\\*\s*$/) {
+ $s =~ s/$;//g; # Remove any comments
+ if (length($c) && $s !~ /^\s*({|;|)\s*\\*\s*$/) {
ERROR("trailing statements should be on next line\n" . $herecurr);
}
}
+# Check for bitwise tests written as boolean
+ if ($line =~ /
+ (?:
+ (?:\[|\(|\&\&|\|\|)
+ \s*0[xX][0-9]+\s*
+ (?:\&\&|\|\|)
+ |
+ (?:\&\&|\|\|)
+ \s*0[xX][0-9]+\s*
+ (?:\&\&|\|\||\)|\])
+ )/x)
+ {
+ WARN("boolean test with hexadecimal, perhaps just 1 \& or \|?\n" . $herecurr);
+ }
+
# if and else should not have general statements after it
- if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/ &&
- $1 !~ /^\s*(?:\sif|{|\\|$)/) {
- ERROR("trailing statements should be on next line\n" . $herecurr);
+ if ($line =~ /^.\s*(?:}\s*)?else\b(.*)/) {
+ my $s = $1;
+ $s =~ s/$;//g; # Remove any comments
+ if ($s !~ /^\s*(?:\sif|(?:{|)\s*\\?\s*$)/) {
+ ERROR("trailing statements should be on next line\n" . $herecurr);
+ }
}
# Check for }<nl>else {, these must be at the same
ERROR("else should follow close brace '}'\n" . $hereprev);
}
+ if ($prevline=~/}\s*$/ and $line=~/^.\s*while\s*/ and
+ $previndent == $indent) {
+ my ($s, $c) = ctx_statement_block($linenr, $realcnt, 0);
+
+ # Find out what is on the end of the line after the
+ # conditional.
+ substr($s, 0, length($c)) = '';
+ $s =~ s/\n.*//g;
+
+ if ($s =~ /^\s*;/) {
+ ERROR("while should follow close brace '}'\n" . $hereprev);
+ }
+ }
+
#studly caps, commented out until figure out how to distinguish between use of existing and adding new
# if (($line=~/[\w_][a-z\d]+[A-Z]/) and !($line=~/print/)) {
# print "No studly caps, use _\n";
}
# check for redundant bracing round if etc
- if ($line =~ /\b(if|while|for|else)\b/) {
+ if ($line =~ /(^.*)\bif\b/ && $1 !~ /else\s*$/) {
+ my ($level, $endln, @chunks) =
+ ctx_statement_full($linenr, $realcnt, 0);
+ #print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n";
+ if ($#chunks > 1 && $level == 0) {
+ my $allowed = 0;
+ my $seen = 0;
+ for my $chunk (@chunks) {
+ my ($cond, $block) = @{$chunk};
+
+ substr($block, 0, length($cond)) = '';
+
+ $seen++ if ($block =~ /^\s*{/);
+
+ $block =~ s/(^|\n)./$1/g;
+ $block =~ s/^\s*{//;
+ $block =~ s/}\s*$//;
+ $block =~ s/^\s*//;
+ $block =~ s/\s*$//;
+
+ my @lines = ($block =~ /\n/g);
+ my @statements = ($block =~ /;/g);
+
+ #print "cond<$cond> block<$block> lines<" . scalar(@lines) . "> statements<" . scalar(@statements) . "> seen<$seen> allowed<$allowed>\n";
+ if (scalar(@lines) != 0) {
+ $allowed = 1;
+ }
+ if ($block =~/\b(?:if|for|while)\b/) {
+ $allowed = 1;
+ }
+ if (scalar(@statements) > 1) {
+ $allowed = 1;
+ }
+ }
+ if ($seen && !$allowed) {
+ WARN("braces {} are not necessary for any arm of this statement\n" . $herecurr);
+ $suppress_ifbraces = $endln;
+ }
+ }
+ }
+ if ($linenr > $suppress_ifbraces &&
+ $line =~ /\b(if|while|for|else)\b/) {
# Locate the end of the opening statement.
my @control = ctx_statement($linenr, $realcnt, 0);
my $nr = $linenr + (scalar(@control) - 1);
my $after = $1;
#print "block<" . join(' ', @block) . "><" . scalar(@block) . ">\n";
- #print "stmt<$stmt>\n\n";
+ #print "before<$before> stmt<$stmt> after<$after>\n\n";
# Count the newlines, if there is only one
# then the block should not have {}'s.
my @lines = ($stmt =~ /\n/g);
+ my @statements = ($stmt =~ /;/g);
#print "lines<" . scalar(@lines) . ">\n";
+ #print "statements<" . scalar(@statements) . ">\n";
if ($lvl == 0 && scalar(@lines) == 0 &&
+ scalar(@statements) < 2 &&
$stmt !~ /{/ && $stmt !~ /\bif\b/ &&
$before !~ /}/ && $after !~ /{/) {
my $herectx = "$here\n" . join("\n", @control, @block[1 .. $#block]) . "\n";
if ($line =~ /\*\s*\)\s*k[czm]alloc\b/) {
WARN("unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr);
}
+
+# check for gcc specific __FUNCTION__
+ if ($line =~ /__FUNCTION__/) {
+ WARN("__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr);
+ }
+ }
+
+ # If we have no input at all, then there is nothing to report on
+ # so just keep quiet.
+ if ($#rawlines == -1) {
+ exit(0);
}
# In mailback mode only produce a report in the negative, for
}
print report_dump();
- if ($summary) {
+ if ($summary && !($clean == 1 && $quiet == 1)) {
+ print "$filename " if ($summary_file);
print "total: $cnt_error errors, $cnt_warn warnings, " .
(($check)? "$cnt_chk checks, " : "") .
"$cnt_lines lines checked\n";
}
if ($clean == 1 && $quiet == 0) {
- print "Your patch has no obvious style problems and is ready for submission.\n"
+ print "$vname has no obvious style problems and is ready for submission.\n"
}
if ($clean == 0 && $quiet == 0) {
- print "Your patch has style problems, please review. If any of these errors\n";
+ print "$vname has style problems, please review. If any of these errors\n";
print "are false positives report them to the maintainer, see\n";
print "CHECKPATCH in MAINTAINERS.\n";
}
+ print <<EOL if ($file == 1 && $quiet == 0);
+
+WARNING: Using --file mode. Please do not send patches to linux-kernel
+that change whole existing files if you did not significantly change most
+of the the file for other reasons anyways or just wrote the file newly
+from scratch. Pure code style patches have a significant cost in a
+quickly changing code base like Linux because they cause rejects
+with other changes.
+EOL
+
return $clean;
}
// ******************************************************************************************
// Mixer file operations struct.
// ******************************************************************************************
-static /*const */ struct file_operations cs4297a_mixer_fops = {
+static const struct file_operations cs4297a_mixer_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.ioctl = cs4297a_ioctl_mixdev,
// ******************************************************************************************
// Wave (audio) file operations struct.
// ******************************************************************************************
-static /*const */ struct file_operations cs4297a_audio_fops = {
+static const struct file_operations cs4297a_audio_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.read = cs4297a_read,
return 0;
}
-static /*const */ struct file_operations trident_audio_fops = {
+static const struct file_operations trident_audio_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.read = trident_read,
return codec->mixer_ioctl(codec, cmd, arg);
}
-static /*const */ struct file_operations trident_mixer_fops = {
+static const struct file_operations trident_mixer_fops = {
.owner = THIS_MODULE,
.llseek = no_llseek,
.ioctl = trident_ioctl_mixdev,
.priority = 20, /* must be > scheduler priority */
};
-static u64 vm_stat_get(void *_offset)
+static int vm_stat_get(void *_offset, u64 *val)
{
unsigned offset = (long)_offset;
- u64 total = 0;
struct kvm *kvm;
+ *val = 0;
spin_lock(&kvm_lock);
list_for_each_entry(kvm, &vm_list, vm_list)
- total += *(u32 *)((void *)kvm + offset);
+ *val += *(u32 *)((void *)kvm + offset);
spin_unlock(&kvm_lock);
- return total;
+ return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(vm_stat_fops, vm_stat_get, NULL, "%llu\n");
-static u64 vcpu_stat_get(void *_offset)
+static int vcpu_stat_get(void *_offset, u64 *val)
{
unsigned offset = (long)_offset;
- u64 total = 0;
struct kvm *kvm;
struct kvm_vcpu *vcpu;
int i;
+ *val = 0;
spin_lock(&kvm_lock);
list_for_each_entry(kvm, &vm_list, vm_list)
for (i = 0; i < KVM_MAX_VCPUS; ++i) {
vcpu = kvm->vcpus[i];
if (vcpu)
- total += *(u32 *)((void *)vcpu + offset);
+ *val += *(u32 *)((void *)vcpu + offset);
}
spin_unlock(&kvm_lock);
- return total;
+ return 0;
}
DEFINE_SIMPLE_ATTRIBUTE(vcpu_stat_fops, vcpu_stat_get, NULL, "%llu\n");
projects / karo-tx-linux.git / commitdiff