to deadlock. This workaround puts DSB before executing ISB if
an abort may occur on cache maintenance.
+config ARM_ERRATA_782773
+ bool "ARM errata: Updating a translation entry might cause an unexpected translation fault"
+ depends on CPU_V7
+ help
+ This option enables the workaround for the 782773 Cortex-A9 (all r0,
+ r2 and r3 revisions) erratum. It might cause MMU exception in case
+ page table walk happens just after updating the existing
+ with setting page table in L1 data cache.
+
endmenu
source "arch/arm/common/Kconfig"
# CONFIG_IPC_NS is not set
# CONFIG_PID_NS is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ST1232=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_ADXL34X=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=9
CONFIG_SH_DMAE=y
CONFIG_ASYNC_TX_DMA=y
CONFIG_STAGING=y
+CONFIG_SENSORS_AK8975=y
+CONFIG_IIO=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY_USER=y
CONFIG_VFAT_FS=y
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_SH_MOBILE=y
# CONFIG_HWMON is not set
# CONFIG_MFD_SUPPORT is not set
CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_FB_SH_MOBILE_HDMI=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_LOGO=y
# CONFIG_LOGO_LINUX_MONO is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_SOC_SH4_FSI=y
+CONFIG_USB=y
+CONFIG_USB_RENESAS_USBHS_HCD=y
+CONFIG_USB_RENESAS_USBHS=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_DMADEVICES=y
+CONFIG_SH_DMAE=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
/* SDHI */
static struct sh_mobile_sdhi_info sdhi0_info = {
+ .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
+ .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
/* Micro SD */
static struct sh_mobile_sdhi_info sdhi2_info = {
+ .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX,
+ .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
TMIO_MMC_USE_GPIO_CD |
TMIO_MMC_WRPROTECT_DISABLE,
},
{
I2C_BOARD_INFO("r2025sd", 0x32),
- }
+ },
+ {
+ I2C_BOARD_INFO("ak8975", 0x0c),
+ .irq = intcs_evt2irq(0x3380), /* IRQ28 */
+ },
+ {
+ I2C_BOARD_INFO("adxl34x", 0x1d),
+ .irq = intcs_evt2irq(0x3340), /* IRQ26 */
+ },
};
static struct i2c_board_info i2c1_devices[] = {
SHDMA_SLAVE_SCIF5_RX,
SHDMA_SLAVE_SCIF6_TX,
SHDMA_SLAVE_SCIF6_RX,
+ SHDMA_SLAVE_FLCTL0_TX,
+ SHDMA_SLAVE_FLCTL0_RX,
+ SHDMA_SLAVE_FLCTL1_TX,
+ SHDMA_SLAVE_FLCTL1_RX,
SHDMA_SLAVE_SDHI0_RX,
SHDMA_SLAVE_SDHI0_TX,
SHDMA_SLAVE_SDHI1_RX,
.num_resources = ARRAY_SIZE(i2c1_resources),
};
+static struct resource pmu_resources[] = {
+ [0] = {
+ .start = evt2irq(0x19a0),
+ .end = evt2irq(0x19a0),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device pmu_device = {
+ .name = "arm-pmu",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(pmu_resources),
+ .resource = pmu_resources,
+};
+
static struct platform_device *r8a7740_late_devices[] __initdata = {
&i2c0_device,
&i2c1_device,
&dma1_device,
&dma2_device,
&usb_dma_device,
+ &pmu_device,
};
/*
.addr = 0xe6c30060,
.chcr = CHCR_RX(XMIT_SZ_8BIT),
.mid_rid = 0x3e,
+ }, {
+ .slave_id = SHDMA_SLAVE_FLCTL0_TX,
+ .addr = 0xe6a30050,
+ .chcr = CHCR_TX(XMIT_SZ_32BIT),
+ .mid_rid = 0x83,
+ }, {
+ .slave_id = SHDMA_SLAVE_FLCTL0_RX,
+ .addr = 0xe6a30050,
+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
+ .mid_rid = 0x83,
+ }, {
+ .slave_id = SHDMA_SLAVE_FLCTL1_TX,
+ .addr = 0xe6a30060,
+ .chcr = CHCR_TX(XMIT_SZ_32BIT),
+ .mid_rid = 0x87,
+ }, {
+ .slave_id = SHDMA_SLAVE_FLCTL1_RX,
+ .addr = 0xe6a30060,
+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
+ .mid_rid = 0x87,
}, {
.slave_id = SHDMA_SLAVE_SDHI0_TX,
.addr = 0xe6850030,
tstne r1, #L_PTE_PRESENT
moveq r3, #0
+#ifdef CONFIG_ARM_ERRATA_782773
+ mrs r2, cpsr @ save cpsr
+ cpsid if @ disable interrupts
+ mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
+#endif
ARM( str r3, [r0, #2048]! )
THUMB( add r0, r0, #2048 )
THUMB( str r3, [r0] )
+#ifdef CONFIG_ARM_ERRATA_782773
+ msr cpsr_c, r2 @ load cpsr
+#endif
mcr p15, 0, r0, c7, c10, 1 @ flush_pte
#endif
mov pc, lr