gpu: ipu-v3: add unsynchronised DP channel disabling

When disabling the foreground DP channel during a modeset, the DC is
already disabled without waiting for end of frame. There is no reason
to wait for a frame boundary before updating the DP registers in that
case.
Add support to apply updates immediately. No functional changes, yet.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
index 24819c9c3640012c42b62c1eac57ec25beb47821..55991d46ced501d13d0db2fd5d72fb4ab54bbfd0 100644 (file)
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -181,7 +181,7 @@ static int ipu_disable_plane(struct drm_plane *plane)
        ipu_idmac_wait_busy(ipu_plane->ipu_ch, 50);
 
        if (ipu_plane->dp)
-               ipu_dp_disable_channel(ipu_plane->dp);
+               ipu_dp_disable_channel(ipu_plane->dp, true);
        ipu_idmac_disable_channel(ipu_plane->ipu_ch);
        ipu_dmfc_disable_channel(ipu_plane->dmfc);
        if (ipu_plane->dp)

diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index 8368e6f766ee584b2947664d0f77e2b044410510..8a32ed25a1c29f8f08c0afa4b055bde2758f6f97 100644 (file)
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -51,15 +51,17 @@ int ipu_get_num(struct ipu_soc *ipu)
 }
 EXPORT_SYMBOL_GPL(ipu_get_num);
 
-void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
+void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync)
 {
        u32 val;
 
        val = ipu_cm_read(ipu, IPU_SRM_PRI2);
-       val |= 0x8;
+       val &= ~DP_S_SRM_MODE_MASK;
+       val |= sync ? DP_S_SRM_MODE_NEXT_FRAME :
+                     DP_S_SRM_MODE_NOW;
        ipu_cm_write(ipu, val, IPU_SRM_PRI2);
 }
-EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
+EXPORT_SYMBOL_GPL(ipu_srm_dp_update);
 
 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
 {

diff --git a/drivers/gpu/ipu-v3/ipu-dp.c b/drivers/gpu/ipu-v3/ipu-dp.c
index 98686edbcdbb05a4ec389632007ee9043afafec2..0e09c98248a0d68a88df821dd11acdfb0def8f01 100644 (file)
--- a/drivers/gpu/ipu-v3/ipu-dp.c
+++ b/drivers/gpu/ipu-v3/ipu-dp.c
@@ -112,7 +112,7 @@ int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable,
                writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);
        }
 
-       ipu_srm_dp_sync_update(priv->ipu);
+       ipu_srm_dp_update(priv->ipu, true);
 
        mutex_unlock(&priv->mutex);
 
@@ -127,7 +127,7 @@ int ipu_dp_set_window_pos(struct ipu_dp *dp, u16 x_pos, u16 y_pos)
 
        writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS);
 
-       ipu_srm_dp_sync_update(priv->ipu);
+       ipu_srm_dp_update(priv->ipu, true);
 
        return 0;
 }
@@ -207,7 +207,7 @@ int ipu_dp_setup_channel(struct ipu_dp *dp,
                                        flow->out_cs, DP_COM_CONF_CSC_DEF_FG);
        }
 
-       ipu_srm_dp_sync_update(priv->ipu);
+       ipu_srm_dp_update(priv->ipu, true);
 
        mutex_unlock(&priv->mutex);
 
@@ -247,7 +247,7 @@ int ipu_dp_enable_channel(struct ipu_dp *dp)
        reg |= DP_COM_CONF_FG_EN;
        writel(reg, flow->base + DP_COM_CONF);
 
-       ipu_srm_dp_sync_update(priv->ipu);
+       ipu_srm_dp_update(priv->ipu, true);
 
        mutex_unlock(&priv->mutex);
 
@@ -255,7 +255,7 @@ int ipu_dp_enable_channel(struct ipu_dp *dp)
 }
 EXPORT_SYMBOL_GPL(ipu_dp_enable_channel);
 
-void ipu_dp_disable_channel(struct ipu_dp *dp)
+void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync)
 {
        struct ipu_flow *flow = to_flow(dp);
        struct ipu_dp_priv *priv = flow->priv;
@@ -275,7 +275,7 @@ void ipu_dp_disable_channel(struct ipu_dp *dp)
        writel(reg, flow->base + DP_COM_CONF);
 
        writel(0, flow->base + DP_FG_POS);
-       ipu_srm_dp_sync_update(priv->ipu);
+       ipu_srm_dp_update(priv->ipu, sync);
 
        if (ipu_idmac_channel_busy(priv->ipu, IPUV3_CHANNEL_MEM_BG_SYNC))
                ipu_wait_interrupt(priv->ipu, IPU_IRQ_DP_SF_END, 50);

diff --git a/drivers/gpu/ipu-v3/ipu-prv.h b/drivers/gpu/ipu-v3/ipu-prv.h
index 22e47b68b14a230a6ad00814a827e4d3e4d11a51..285595702ee0fc83f53b53830e14979835b73a55 100644 (file)
--- a/drivers/gpu/ipu-v3/ipu-prv.h
+++ b/drivers/gpu/ipu-v3/ipu-prv.h
@@ -75,6 +75,11 @@ struct ipu_soc;
 #define IPU_INT_CTRL(n)                IPU_CM_REG(0x003C + 4 * (n))
 #define IPU_INT_STAT(n)                IPU_CM_REG(0x0200 + 4 * (n))
 
+/* SRM_PRI2 */
+#define DP_S_SRM_MODE_MASK             (0x3 << 3)
+#define DP_S_SRM_MODE_NOW              (0x3 << 3)
+#define DP_S_SRM_MODE_NEXT_FRAME       (0x1 << 3)
+
 /* FS_PROC_FLOW1 */
 #define FS_PRPENC_ROT_SRC_SEL_MASK     (0xf << 0)
 #define FS_PRPENC_ROT_SRC_SEL_ENC              (0x7 << 0)
@@ -215,7 +220,7 @@ static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
        writel(value, ipu->idmac_reg + offset);
 }
 
-void ipu_srm_dp_sync_update(struct ipu_soc *ipu);
+void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync);
 
 int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
 int ipu_module_disable(struct ipu_soc *ipu, u32 mask);

diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 53cd07ccaa4ce2d0c2881430371a4e929d2bb045..899d2b00ad6d4058734e44c907b5c17ac3a47708 100644 (file)
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -300,7 +300,7 @@ struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
 void ipu_dp_put(struct ipu_dp *);
 int ipu_dp_enable(struct ipu_soc *ipu);
 int ipu_dp_enable_channel(struct ipu_dp *dp);
-void ipu_dp_disable_channel(struct ipu_dp *dp);
+void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync);
 void ipu_dp_disable(struct ipu_soc *ipu);
 int ipu_dp_setup_channel(struct ipu_dp *dp,
                enum ipu_color_space in, enum ipu_color_space out);