arm64: dts: rockchip: add the pwm node info for RK3368 SoCs

The pulse-width modulator (PWM) feature is very common in
embedded systems. On the rk3368 there exist 4 built-in PWM channels.

In general, the pwm pins can via the pinctrl to
configure iomux mode except the pwm2 since the pwm2 iomux mode from
the SoC control register.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 02fe8718d6f08426f3e711ad21caff203bfbb0ac..61ca1abde947bb37d2047cb959d1ce8eb38f2450 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -498,6 +498,48 @@
                status = "disabled";
        };
 
+       pwm0: pwm@ff680000 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680000 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm0_pin>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm1: pwm@ff680010 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680010 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm1_pin>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm2: pwm@ff680020 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680020 0x0 0x10>;
+               #pwm-cells = <3>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm3: pwm@ff680030 {
+               compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff680030 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm3_pin>;
+               clocks = <&cru PCLK_PWM1>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
        uart2: serial@ff690000 {
                compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
                reg = <0x0 0xff690000 0x0 0x100>;
@@ -739,6 +781,24 @@
                        };
                };
 
+               pwm0 {
+                       pwm0_pin: pwm0-pin {
+                               rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm1 {
+                       pwm1_pin: pwm1-pin {
+                               rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm3 {
+                       pwm3_pin: pwm3-pin {
+                               rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+               };
+
                sdio0 {
                        sdio0_bus1: sdio0-bus1 {
                                rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;