drm/i915/chv: Add display interrupt registers bits for Cherryview

v2: Rebase on top of Ben's GT interrupt shuffling.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3fe9b56337abc5a42dd1cb7ce0b841e6a75ea6a5..4250717e8dec3ded163df9f0d7a3dd0004cfdca5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1124,24 +1124,43 @@ enum punit_power_well {
 
 /* These are all the "old" interrupts */
 #define ILK_BSD_USER_INTERRUPT                         (1<<5)
+
+#define I915_PM_INTERRUPT                              (1<<31)
+#define I915_ISP_INTERRUPT                             (1<<22)
+#define I915_LPE_PIPE_B_INTERRUPT                      (1<<21)
+#define I915_LPE_PIPE_A_INTERRUPT                      (1<<20)
+#define I915_MIPIB_INTERRUPT                           (1<<19)
+#define I915_MIPIA_INTERRUPT                           (1<<18)
 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT             (1<<18)
 #define I915_DISPLAY_PORT_INTERRUPT                    (1<<17)
+#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT           (1<<16)
+#define I915_MASTER_ERROR_INTERRUPT                    (1<<15)
 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT     (1<<15)
+#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT           (1<<14)
 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT       (1<<14) /* p-state */
+#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT           (1<<13)
 #define I915_HWB_OOM_INTERRUPT                         (1<<13)
+#define I915_LPE_PIPE_C_INTERRUPT                      (1<<12)
 #define I915_SYNC_STATUS_INTERRUPT                     (1<<12)
+#define I915_MISC_INTERRUPT                            (1<<11)
 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT    (1<<11)
+#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT           (1<<10)
 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT    (1<<10)
+#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT            (1<<9)
 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT      (1<<9)
+#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT             (1<<8)
 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT    (1<<8)
 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT           (1<<7)
 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT            (1<<6)
 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT           (1<<5)
 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT            (1<<4)
+#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT             (1<<3)
+#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT             (1<<2)
 #define I915_DEBUG_INTERRUPT                           (1<<2)
+#define I915_WINVALID_INTERRUPT                                (1<<1)
 #define I915_USER_INTERRUPT                            (1<<1)
 #define I915_ASLE_INTERRUPT                            (1<<0)
-#define I915_BSD_USER_INTERRUPT                                (1 << 25)
+#define I915_BSD_USER_INTERRUPT                                (1<<25)
 
 #define GEN6_BSD_RNCID                 0x12198